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DrZ80.s
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DrZ80.s
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.DATA
;@ Reesy's Z80 Emulator Version 0.001
;@ (c) Copyright 2004 Reesy, All rights reserved
;@ DrZ80 is free for non-commercial use.
;@ For commercial use, separate licencing terms must be obtained.
.global DrZ80Run
.global DrZ80Ver
.equiv INTERRUPT_MODE, 1 ;@0 = Use internal int handler, 1 = Use Mames int handler
.equiv FAST_Z80SP, 1 ;@0 = Use mem functions for stack pointer, 1 = Use direct mem pointer
.equiv UPDATE_CONTEXT, 0
.equiv FAST_REBASE_PC, 1 ;@1=try not to call the rebase functions
.equiv FAST_REBASE_SP, 1 ;@1=try not to call the rebase functions
.equiv FAKE_PORTIO, 1 ;@1=don't really do any port IO
.if INTERRUPT_MODE
.extern Interrupt
.endif
DrZ80Ver: .long 0x0001
;@---------------------------------------
.macro fetch cycs
subs z80_icount,z80_icount,#\cycs
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
str z80_icount,[cpucontext,#cycles_pointer]
ldr r1,[cpucontext,#z80pc_base]
sub r2,z80pc,r1
str r2,[cpucontext,#previouspc]
.endif
ldrplb r0,[z80pc],#1
ldrpl pc,[opcodes,r0, lsl #2]
bmi z80_execute_end
.endm
.macro eatcycles cycs
sub z80_icount,z80_icount,#\cycs
.if UPDATE_CONTEXT
str z80_icount,[cpucontext,#cycles_pointer]
.endif
.endm
.macro readmem8
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
ldmfd sp!,{r3,r12}
.endm
.macro readmem8HL
mov r0,z80hl, lsr #16
readmem8
.endm
.macro readmem16
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read16]
ldmfd sp!,{r3,r12}
.endm
.macro writemem8
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endm
.macro writemem8DE
mov r1,z80de, lsr #16
writemem8
.endm
.macro writemem8HL
mov r1,z80hl, lsr #16
writemem8
.endm
.macro writemem16
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_write16] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endm
.macro copymem8HL_DE
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
mov r0,z80hl, lsr #16
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
mov r1,z80de, lsr #16
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endm
;@---------------------------------------
.macro rebasepc
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if FAST_REBASE_PC
ldr r1,[cpucontext,#z80pc_base]
add z80pc,r0,r1
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0
ldmfd sp!,{r3,r12}
mov z80pc,r0
.endif
.endm
.macro rebasesp
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if FAST_REBASE_SP
ldr r1,[cpucontext,#z80sp_base]
add r0,r0,r1
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_rebaseSP] ;@ external function must rebase sp
ldmfd sp!,{r3,r12}
.endif
.endm
;@----------------------------------------------------------------------------
.macro opADC
movs z80f,z80f,lsr#2 ;@ get C
subcs r0,r0,#0x100
eor z80f,r0,z80a,lsr#24 ;@ prepare for check of half carry
adcs z80a,z80a,r0,ror#8
mrs r0,cpsr ;@ S,Z,V&C
eor z80f,z80f,z80a,lsr#24
and z80f,z80f,#1<<HFlag ;@ H, correct
orr z80f,z80f,r0,lsr#28
.endm
.macro opADCA
movs z80f,z80f,lsr#2 ;@ get C
orrcs z80a,z80a,#0x00800000
adds z80a,z80a,z80a
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
tst z80a,#0x10000000 ;@ H, correct
orrne z80f,z80f,#1<<HFlag
fetch 4
.endm
.macro opADCH reg
mov r0,\reg,lsr#24
opADC
fetch 4
.endm
.macro opADCL reg
movs z80f,z80f,lsr#2 ;@ get C
adc r0,\reg,\reg,lsr#15
orrcs z80a,z80a,#0x00800000
mov r1,z80a,lsl#4 ;@ Prepare for check of half carry
adds z80a,z80a,r0,lsl#23
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
cmn r1,r0,lsl#27
orrcs z80f,z80f,#1<<HFlag ;@ H, correct
fetch 4
.endm
.macro opADCb
opADC
.endm
;@---------------------------------------
.macro opADD reg shift
mov r1,z80a,lsl#4 ;@ Prepare for check of half carry
adds z80a,z80a,\reg,lsl#\shift
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
cmn r1,\reg,lsl#\shift+4
orrcs z80f,z80f,#1<<HFlag
.endm
.macro opADDA
adds z80a,z80a,z80a
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
tst z80a,#0x10000000 ;@ H, correct
orrne z80f,z80f,#1<<HFlag
fetch 4
.endm
.macro opADDH reg
and r0,\reg,#0xFF000000
opADD r0 0
fetch 4
.endm
.macro opADDL reg
opADD \reg 8
fetch 4
.endm
.macro opADDb
opADD r0 24
.endm
;@---------------------------------------
.macro opADC16 reg
movs z80f,z80f,lsr#2 ;@ get C
adc r0,z80a,\reg,lsr#15
orrcs z80hl,z80hl,#0x00008000
mov r1,z80hl,lsl#4
adds z80hl,z80hl,r0,lsl#15
mrs z80f,cpsr ;@ S, Z, V & C
mov z80f,z80f,lsr#28
cmn r1,r0,lsl#19
orrcs z80f,z80f,#1<<HFlag
fetch 15
.endm
.macro opADC16HL
movs z80f,z80f,lsr#2 ;@ get C
orrcs z80hl,z80hl,#0x00008000
adds z80hl,z80hl,z80hl
mrs z80f,cpsr ;@ S, Z, V & C
mov z80f,z80f,lsr#28
tst z80hl,#0x10000000 ;@ H, correct.
orrne z80f,z80f,#1<<HFlag
fetch 15
.endm
.macro opADD16 reg1 reg2
mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry
adds \reg1,\reg1,\reg2
bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)
orrcs z80f,z80f,#1<<CFlag
cmn r1,\reg2,lsl#4
orrcs z80f,z80f,#1<<HFlag
.endm
.macro opADD16s reg1 reg2 shift
mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry
adds \reg1,\reg1,\reg2,lsl#\shift
bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)
orrcs z80f,z80f,#1<<CFlag
cmn r1,\reg2,lsl#4+\shift
orrcs z80f,z80f,#1<<HFlag
.endm
.macro opADD16_2 reg
adds \reg,\reg,\reg
bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)
orrcs z80f,z80f,#1<<CFlag
tst \reg,#0x10000000 ;@ H, correct.
orrne z80f,z80f,#1<<HFlag
.endm
;@---------------------------------------
.macro opAND reg shift
and z80a,z80a,\reg,lsl#\shift
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
orr z80f,z80f,#1<<HFlag
.endm
.macro opANDA
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
orr z80f,z80f,#1<<HFlag
fetch 4
.endm
.macro opANDH reg
opAND \reg 0
fetch 4
.endm
.macro opANDL reg
opAND \reg 8
fetch 4
.endm
.macro opANDb
opAND r0 24
.endm
;@---------------------------------------
.macro opBITH reg bit
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(24+\bit)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)
fetch 8
.endm
.macro opBIT7H reg
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(24+7)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)
fetch 8
.endm
.macro opBITL reg bit
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(16+\bit)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)
fetch 8
.endm
.macro opBIT7L reg
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(16+7)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)
fetch 8
.endm
.macro opBITb bit
and z80f,z80f,#1<<CFlag
tst r0,#1<<\bit
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)
.endm
.macro opBIT7b
and z80f,z80f,#1<<CFlag
tst r0,#1<<7
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)
.endm
;@---------------------------------------
.macro opCP reg shift
mov r1,z80a,lsl#4 ;@ prepare for check of half carry
cmp z80a,\reg,lsl#\shift
mrs z80f,cpsr
mov z80f,z80f,lsr#28 ;@ S,Z,V&C
eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n
cmp r1,\reg,lsl#\shift+4
orrcc z80f,z80f,#1<<HFlag
.endm
.macro opCPA
mov z80f,#(1<<ZFlag)|(1<<NFlag) ;@ set Z & n
fetch 4
.endm
.macro opCPH reg
and r0,\reg,#0xFF000000
opCP r0 0
fetch 4
.endm
.macro opCPL reg
opCP \reg 8
fetch 4
.endm
.macro opCPb
opCP r0 24
.endm
;@---------------------------------------
.macro opDEC8 reg ;@for A and memory
and z80f,z80f,#1<<CFlag ;@save carry
orr z80f,z80f,#1<<NFlag ;@set n
tst \reg,#0x0f000000
orreq z80f,z80f,#1<<HFlag
subs \reg,\reg,#0x01000000
orrmi z80f,z80f,#1<<SFlag
orrvs z80f,z80f,#1<<VFlag
orreq z80f,z80f,#1<<ZFlag
.endm
.macro opDEC8H reg ;@for B, D & H
and z80f,z80f,#1<<CFlag ;@save carry
orr z80f,z80f,#1<<NFlag ;@set n
tst \reg,#0x0f000000
orreq z80f,z80f,#1<<HFlag
subs \reg,\reg,#0x01000000
orrmi z80f,z80f,#1<<SFlag
orrvs z80f,z80f,#1<<VFlag
tst \reg,#0xff000000 ;@Z
orreq z80f,z80f,#1<<ZFlag
.endm
.macro opDEC8L reg ;@for C, E & L
mov \reg,\reg,ror#24
opDEC8H \reg
mov \reg,\reg,ror#8
.endm
.macro opDEC8b ;@for memory
mov r0,r0,lsl#24
opDEC8 r0
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opIN
.if FAKE_PORTIO
mov r0, #0xFF
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_in] ;@ r0=port - data returned in r0
ldmfd sp!,{r3,r12}
.endif
.endm
.macro opIN_C
mov r0,z80bc, lsr #16
opIN
.endm
;@---------------------------------------
.macro opINC8 reg ;@for A and memory
and z80f,z80f,#1<<CFlag ;@save carry, clear n
adds \reg,\reg,#0x01000000
orrmi z80f,z80f,#1<<SFlag
orrvs z80f,z80f,#1<<VFlag
orrcs z80f,z80f,#1<<ZFlag ;@cs when going from 0xFF to 0x00
tst \reg,#0x0f000000
orreq z80f,z80f,#1<<HFlag
.endm
.macro opINC8H reg ;@for B, D & H
opINC8 \reg
.endm
.macro opINC8L reg ;@for C, E & L
mov \reg,\reg,ror#24
opINC8 \reg
mov \reg,\reg,ror#8
.endm
.macro opINC8b ;@for memory
mov r0,r0,lsl#24
opINC8 r0
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opOR reg shift
orr z80a,z80a,\reg,lsl#\shift
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
.endm
.macro opORA
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
fetch 4
.endm
.macro opORH reg
and r0,\reg,#0xFF000000
opOR r0 0
fetch 4
.endm
.macro opORL reg
opOR \reg 8
fetch 4
.endm
.macro opORb
opOR r0 24
.endm
;@---------------------------------------
.macro opOUT
.if FAKE_PORTIO
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_out] ;@ r0=port r1=data
ldmfd sp!,{r3,r12}
.endif
.endm
.macro opOUT_C
mov r0,z80bc, lsr #16
opOUT
.endm
;@---------------------------------------
.macro opPOP
.if FAST_Z80SP
ldrb r0,[z80sp],#1
ldrb r1,[z80sp],#1
orr r0,r0,r1, lsl #8
.else
mov r0,z80sp
readmem16
add z80sp,z80sp,#2
.endif
.endm
.macro opPOPreg reg
opPOP
mov \reg,r0, lsl #16
fetch 10
.endm
;@---------------------------------------
.macro opPUSHreg reg
.if FAST_Z80SP
mov r1,\reg, lsr #24
strb r1,[z80sp,#-1]!
mov r1,\reg, lsr #16
strb r1,[z80sp,#-1]!
.else
mov r0,\reg,lsr #16
sub z80sp,z80sp,#2
mov r1,z80sp
writemem16
.endif
.endm
;@---------------------------------------
.macro opRESmemHL bit
mov r0,z80hl, lsr #16
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
bic r0,r0,#1<<\bit
mov r1,z80hl, lsr #16
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
fetch 15
.endm
;@---------------------------------------
.macro opRESmem bit
stmfd sp!,{r3,r12}
stmfd sp!,{r0} ;@ save addr as well
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0
bic r0,r0,#1<<\bit
ldmfd sp!,{r1} ;@ restore addr into r1
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
fetch 23
.endm
;@---------------------------------------
.macro opRL reg1 reg2 shift
movs \reg1,\reg2,lsl#\shift
tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!
orrne \reg1,\reg1,#0x01000000
;@ and r2,z80f,#1<<CFlag
;@ orr $x,$x,r2,lsl#23
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1,lsr#24] ;@get PZS
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRLA
opRL z80a z80a 1
fetch 8
.endm
.macro opRLH reg
and r0,\reg,#0xFF000000 ;@mask high to r0
adds \reg,\reg,r0
tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!
orrne \reg,\reg,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24] ;@get PZS
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRLL reg
opRL r0 \reg 9
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsr#8
fetch 8
.endm
.macro opRLb
opRL r0 r0 25
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opRLC reg1 reg2 shift
movs \reg1,\reg2,lsl#\shift
orrcs \reg1,\reg1,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1,lsr#24]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRLCA
opRLC z80a z80a 1
fetch 8
.endm
.macro opRLCH reg
and r0,\reg,#0xFF000000 ;@mask high to r0
adds \reg,\reg,r0
orrcs \reg,\reg,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRLCL reg
opRLC r0 \reg 9
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsr#8
fetch 8
.endm
.macro opRLCb
opRLC r0 r0 25
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opRR reg1 reg2 shift
movs \reg1,\reg2,lsr#\shift
tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!
orrne \reg1,\reg1,#0x00000080
;@ and r2,z80_f,#PSR_C
;@ orr \reg1,\reg1,r2,lsl#6
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRRA
orr z80a,z80a,z80f,lsr#1 ;@get C
movs z80a,z80a,ror#25
mov z80a,z80a,lsl#24
sub r1,opcodes,#0x100
ldrb z80f,[r1,z80a,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRRH reg
orr r0,\reg,z80f,lsr#1 ;@get C
movs r0,r0,ror#25
and \reg,\reg,#0x00FF0000 ;@mask out low
orr \reg,\reg,r0,lsl#24
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRRL reg
and r0,\reg,#0x00FF0000 ;@mask out low to r0
opRR r0 r0 17
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsl#16
fetch 8
.endm
.macro opRRb
opRR r0 r0 1
.endm
;@---------------------------------------
.macro opRRC reg1 reg2 shift
movs \reg1,\reg2,lsr#\shift
orrcs \reg1,\reg1,#0x00000080
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRRCA
opRRC z80a z80a 25
mov z80a,z80a,lsl#24
fetch 8
.endm
.macro opRRCH reg
opRRC r0 \reg 25
and \reg,\reg,#0x00FF0000 ;@mask out low
orr \reg,\reg,r0,lsl#24
fetch 8
.endm
.macro opRRCL reg
and r0,\reg,#0x00FF0000 ;@mask low to r0
opRRC r0 r0 17
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsl#16
fetch 8
.endm
.macro opRRCb
opRRC r0 r0 1
.endm
;@---------------------------------------
.macro opRST addr
ldr r0,[cpucontext,#z80pc_base]
sub r0,z80pc,r0
.if FAST_Z80SP
mov r1,r0, lsr #8
strb r1,[z80sp,#-1]!
strb r0,[z80sp,#-1]!
.else
sub z80sp,z80sp,#2
mov r1,z80sp
writemem16
.endif
mov r0,#\addr
rebasepc
fetch 11
.endm
;@---------------------------------------
.macro opSBC
eor z80f,z80f,#1<<CFlag ;@ invert C
movs z80f,z80f,lsr#2 ;@ get C
subcc r0,r0,#0x100
eor z80f,r0,z80a,lsr#24 ;@ prepare for check of H
sbcs z80a,z80a,r0,ror#8
mrs r0,cpsr
eor z80f,z80f,z80a,lsr#24
and z80f,z80f,#1<<HFlag ;@ H, correct
orr z80f,z80f,r0,lsr#28 ;@ S,Z,V&C
eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.
.endm
.macro opSBCA
movs z80f,z80f,lsr#2 ;@ get C
movcc z80a,#0x00000000
movcs z80a,#0xFF000000
movcc z80f,#(1<<NFlag)|(1<<ZFlag)
movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)
fetch 4
.endm
.macro opSBCH reg
mov r0,\reg,lsr#24
opSBC
fetch 4
.endm
.macro opSBCL reg
mov r0,\reg,lsl#8
eor z80f,z80f,#1<<CFlag ;@ invert C
movs z80f,z80f,lsr#2 ;@ get C
sbccc r0,r0,#0xFF000000
mov r1,z80a,lsl#4 ;@ prepare for check of H
sbcs z80a,z80a,r0
mrs z80f,cpsr
mov z80f,z80f,lsr#28 ;@ S,Z,V&C
eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.
cmp r1,r0,lsl#4
orrcc z80f,z80f,#1<<HFlag ;@ H, correct
fetch 4
.endm
.macro opSBCb
opSBC
.endm
;@---------------------------------------
.macro opSBC16 reg
eor z80f,z80f,#1<<CFlag ;@ invert C
movs z80f,z80f,lsr#2 ;@ get C
sbc r1,r1,r1 ;@ set r1 to -1 or 0.
orr r0,\reg,r1,lsr#16
mov r1,z80hl,lsl#4 ;@ prepare for check of H
sbcs z80hl,z80hl,r0
mrs z80f,cpsr
mov z80f,z80f,lsr#28 ;@ S,Z,V&C
eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.
cmp r1,r0,lsl#4
orrcc z80f,z80f,#1<<HFlag ;@ H, correct
fetch 15
.endm
.macro opSBC16HL
movs z80f,z80f,lsr#2 ;@ get C
mov z80hl,#0x00000000
subcs z80hl,z80hl,#0x00010000
movcc z80f,#(1<<NFlag)|(1<<ZFlag)
movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)
fetch 15
.endm
;@---------------------------------------
.macro opSETmemHL bit
mov r0,z80hl, lsr #16
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
orr r0,r0,#1<<\bit
mov r1,z80hl, lsr #16
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
fetch 15
.endm
;@---------------------------------------
.macro opSETmem bit
stmfd sp!,{r3,r12}
stmfd sp!,{r0} ;@ save addr as well
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0
orr r0,r0,#1<<\bit
ldmfd sp!,{r1} ;@ restore addr into r1
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
fetch 23
.endm
;@---------------------------------------
.macro opSLA reg1 reg2 shift
movs \reg1,\reg2,lsl#\shift
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1,lsr#24]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opSLAA
opSLA z80a z80a 1
fetch 8
.endm
.macro opSLAH reg
and r0,\reg,#0xFF000000 ;@mask high to r0
adds \reg,\reg,r0
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opSLAL reg
opSLA r0 \reg 9
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsr#8
fetch 8
.endm
.macro opSLAb
opSLA r0 r0 25
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opSLL reg1 reg2 shift
movs \reg1,\reg2,lsl#\shift
orr \reg1,\reg1,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1,lsr#24]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opSLLA
opSLL z80a z80a 1
fetch 8
.endm
.macro opSLLH reg
and r0,\reg,#0xFF000000 ;@mask high to r0
adds \reg,\reg,r0
orr \reg,\reg,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opSLLL reg
opSLL r0 \reg 9
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsr#8
fetch 8
.endm
.macro opSLLb
opSLL r0 r0 25
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opSRA reg1 reg2
movs \reg1,\reg2,asr#25
and \reg1,\reg1,#0xFF
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opSRAA
movs r0,z80a,asr#25
mov z80a,r0,lsl#24
sub r1,opcodes,#0x100
ldrb z80f,[r1,z80a,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opSRAH reg
movs r0,\reg,asr#25
and \reg,\reg,#0x00FF0000 ;@mask out low
orr \reg,\reg,r0,lsl#24
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opSRAL reg
mov r0,\reg,lsl#8
opSRA r0 r0
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsl#16
fetch 8
.endm
.macro opSRAb
mov r0,r0,lsl#24
opSRA r0 r0
.endm
;@---------------------------------------
.macro opSRL reg1 reg2 shift
movs \reg1,\reg2,lsr#\shift
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opSRLA
opSRL z80a z80a 25
mov z80a,z80a,lsl#24
fetch 8
.endm
.macro opSRLH reg
opSRL r0 \reg 25
and \reg,\reg,#0x00FF0000 ;@mask out low
orr \reg,\reg,r0,lsl#24
fetch 8
.endm
.macro opSRLL reg
mov r0,\reg,lsl#8
opSRL r0 r0 25
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsl#16
fetch 8
.endm
.macro opSRLb
opSRL r0 r0 1
.endm
;@---------------------------------------
.macro opSUB reg shift
mov r1,z80a,lsl#4 ;@ Prepare for check of half carry
subs z80a,z80a,\reg,lsl#\shift
mrs z80f,cpsr
mov z80f,z80f,lsr#28 ;@ S,Z,V&C
eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n