From d92b3ff31e46276d9d1548336161086efddbeac9 Mon Sep 17 00:00:00 2001 From: Nicola Mazzucato Date: Fri, 22 Dec 2023 11:10:25 +0000 Subject: [PATCH 01/17] scmi: Shorten long error messages Two log messages are over 80 chars and thus are truncated. Shorten them without losing the sense. Signed-off-by: Nicola Mazzucato Change-Id: I840c6de0c555f5e8a7f7a30104eda3af44f80c4e --- module/scmi/src/mod_scmi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/module/scmi/src/mod_scmi.c b/module/scmi/src/mod_scmi.c index 604cef21a..dc8952efe 100644 --- a/module/scmi/src/mod_scmi.c +++ b/module/scmi/src/mod_scmi.c @@ -157,7 +157,7 @@ static const char *get_message_type_str(const struct scmi_service_ctx *ctx) return "Notif"; default: - return "Invalid message"; + return "Invalid msg"; } } @@ -1044,8 +1044,7 @@ static int scmi_process_event(const struct fwk_event *event, if (protocol_idx == 0) { #if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_ERROR FWK_LOG_ERR( - "[SCMI] %s: %s [%" PRIu16 - "(0x%x:0x%x)] requested an unsupported protocol", + "[SCMI] %s: %s [%" PRIu16 "(0x%x:0x%x)] Unsupported protocol", service_name, message_type_name, ctx->scmi_token, From b9b7aa9cf145b1dfaf1c746102c1f54d359bc475 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 28 Dec 2023 09:08:39 +0530 Subject: [PATCH 02/17] module/cmn_cyprus: suppress release build warnings A couple of helper functions and variables in the CMN Cyprus driver are used only in the Debug build. So, if the module is compiled in a Release build, the compiler throws unused variable/function warnings. Hence, add workaround to suppress the warning. Signed-off-by: Shriram K Change-Id: I99fcc836f3a039655880fb0b861e1e883a0de3bf --- .../src/cmn_cyprus_discovery_setup.c | 37 +++++++++++++------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/module/cmn_cyprus/src/cmn_cyprus_discovery_setup.c b/module/cmn_cyprus/src/cmn_cyprus_discovery_setup.c index 6dbe3f3fe..ad7fdaa40 100644 --- a/module/cmn_cyprus/src/cmn_cyprus_discovery_setup.c +++ b/module/cmn_cyprus/src/cmn_cyprus_discovery_setup.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -66,6 +66,7 @@ static struct cmn_cyprus_ctx *shared_ctx; /* RNSAM table index */ static unsigned int rnsam_entry; +#if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_INFO /* CMN Revision Numbers */ enum cmn_cyprus_revision { REV_R0_P0, @@ -104,6 +105,7 @@ static const char *const node_type_to_name[NODE_TYPE_COUNT] = { [NODE_TYPE_HN_S_MPAM_S] = "HN-S MPAM-S", [NODE_TYPE_HN_S_MPAM_NS] = "HN-S MPAM-NS", }; +#endif /* * Determine the number of bits used to represent each node coordinate based @@ -156,6 +158,7 @@ static unsigned int get_node_pos_y( return (node_id >> NODE_ID_Y_POS) & mask_bits; } +#if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_INFO /* Get node type name */ static const char *get_node_type_name(enum cmn_cyprus_node_type node_type) { @@ -187,6 +190,7 @@ static const char *get_cmn_cyprus_revision_name( return cmn_cyprus_rev_to_name[revision]; } +#endif static inline unsigned int get_child_count(FWK_R uint64_t child_info) { @@ -486,22 +490,15 @@ static void disable_hns_isolation(struct cmn_cyprus_mxp_reg *mxp) } } -static int discover_mxp_nodes(struct cmn_cyprus_mxp_reg *mxp) +#if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_INFO +static void print_node_info(struct cmn_cyprus_mxp_reg *mxp) { - int status; - unsigned int node_count; + uint8_t mesh_size_x; + uint8_t mesh_size_y; unsigned int node_id; - unsigned int node_idx; unsigned int node_pos_x; unsigned int node_pos_y; - uint8_t mesh_size_x; - uint8_t mesh_size_y; - struct cmn_cyprus_node_cfg_reg *node; - - /* Get number of children connected to the cross point */ - node_count = get_child_count(mxp->CHILD_INFO); - /* Get node id */ node_id = node_info_get_id(mxp->NODE_INFO); mesh_size_x = shared_ctx->config->mesh_size_x; @@ -516,6 +513,22 @@ static int discover_mxp_nodes(struct cmn_cyprus_mxp_reg *mxp) node_pos_y, node_id, node_info_get_ldid(mxp->NODE_INFO)); +} +#endif + +static int discover_mxp_nodes(struct cmn_cyprus_mxp_reg *mxp) +{ + int status; + unsigned int node_count; + unsigned int node_idx; + struct cmn_cyprus_node_cfg_reg *node; + + /* Get number of children connected to the cross point */ + node_count = get_child_count(mxp->CHILD_INFO); + +#if FWK_LOG_LEVEL <= FWK_LOG_LEVEL_INFO + print_node_info(mxp); +#endif /* Traverse nodes connected to the cross point */ for (node_idx = 0; node_idx < node_count; node_idx++) { From 82f04c2fba95356a80572367eacbde0627f76ef7 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 28 Dec 2023 11:27:18 +0530 Subject: [PATCH 03/17] module/cmn_cyprus: fix incorrect format specifier for clang The Clang compiler considers uint32_t data type as 'unsigned int' whereas the GCC considers it as 'long unsigned int'. A potential solution is to use PRIx format specifiers provided in the inttypes header but it is not compatible with aarch64 host machines. Hence, as a workaround, cast the uint32_t variables as unsigned int data type when printing as the concerned variables are guaranteed to be under 16 bits. Signed-off-by: Shriram K Change-Id: I548f2709e2dfe460c176455b02982b33d1a2041e --- module/cmn_cyprus/src/cmn_cyprus_rnsam_setup.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/module/cmn_cyprus/src/cmn_cyprus_rnsam_setup.c b/module/cmn_cyprus/src/cmn_cyprus_rnsam_setup.c index 7f4696eae..d6a7bd0f1 100644 --- a/module/cmn_cyprus/src/cmn_cyprus_rnsam_setup.c +++ b/module/cmn_cyprus/src/cmn_cyprus_rnsam_setup.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -98,7 +98,8 @@ static int program_io_region( if (region_idx >= RNSAM_NON_HASH_MEM_REGION_COUNT) { FWK_LOG_ERR( - MOD_NAME "Error! Invalid non-hashed region %lu", region_idx); + MOD_NAME "Error! Invalid non-hashed region %u", + (unsigned int)region_idx); FWK_LOG_ERR( MOD_NAME "Max non-hashed region supported is %u", RNSAM_NON_HASH_MEM_REGION_COUNT); @@ -228,7 +229,8 @@ static int program_scg_region( ->rnsam_scg_config; if (scg_idx >= MAX_SCG_COUNT) { - FWK_LOG_ERR(MOD_NAME "Error! Invalid SCG region %lu", scg_idx); + FWK_LOG_ERR( + MOD_NAME "Error! Invalid SCG region %u", (unsigned int)scg_idx); FWK_LOG_ERR(MOD_NAME "Max SCG region supported is %u ", MAX_SCG_COUNT); return FWK_E_DATA; } From 843f2f0431084fb7f232ba70b0ae979cf1bd9095 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 14 Sep 2023 22:10:41 +0000 Subject: [PATCH 04/17] rdfremont: add sid module config data for scp_ramfw The SID peripheral provides information about the platform and its configuration. So, add the configuration data for sid module in scp ramfw. The configuration data includes the expected value of its PID/CID registers for identification. PID5, PID6 and PID7 are not implemented by this peripheral and this is indicated using the valid register bitmap. Signed-off-by: Shriram K Change-Id: I9ce8ad9eff33dedf32a6129fc5181871fe595fc3 --- .../rdfremont/scp_ramfw/config_sid.c | 64 +++++++++++++++++++ .../scp_ramfw/include/scp_css_mmap.h | 18 ++++++ 2 files changed, 82 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_sid.c create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_sid.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_sid.c new file mode 100644 index 000000000..715855fc1 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_sid.c @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'sid'. + */ + +#include "scp_css_mmap.h" + +#include + +#include +#include +#include + +#define RD_FREMONT_PART_NUMBER 0x7EE + +/* Module 'sid' element count */ +#define MOD_SID_ELEMENT_COUNT 2 + +static const struct fwk_element subsystem_table[MOD_SID_ELEMENT_COUNT] = { + { .name = "RD-Fremont", + .data = + &(struct mod_sid_subsystem_config){ + .part_number = RD_FREMONT_PART_NUMBER, + } }, + { 0 }, +}; + +static const struct fwk_element *get_subsystem_table(fwk_id_t id) +{ + return subsystem_table; +} + +const struct fwk_module_config config_sid = { + .data = &(struct mod_sid_config) { + .sid_base = SCP_SID_BASE, + .valid_pcid_registers = + MOD_PCID_REGISTER_PID0 | + MOD_PCID_REGISTER_PID1 | + MOD_PCID_REGISTER_PID2 | + MOD_PCID_REGISTER_PID3 | + MOD_PCID_REGISTER_PID4 | + MOD_PCID_REGISTER_CID0 | + MOD_PCID_REGISTER_CID1 | + MOD_PCID_REGISTER_CID2 | + MOD_PCID_REGISTER_CID3, + .pcid_expected = { + .PID0 = 0xBC, + .PID1 = 0xB0, + .PID2 = 0x0B, + .PID3 = 0x00, + .PID4 = 0x04, + .CID0 = 0x0D, + .CID1 = 0xF0, + .CID2 = 0x05, + .CID3 = 0xB1, + }, + }, + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_subsystem_table), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h new file mode 100644 index 000000000..5a0789274 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the SCP's sub-system and access extending + * into the rest of the CSS. + */ + +#ifndef SCP_CSS_MMAP_H +#define SCP_CSS_MMAP_H + +/* SCP sub-system peripherals */ +#define SCP_SID_BASE (0x2A4A0000) + +#endif /* SCP_CSS_MMAP_H */ From 90da07c1ba44d4cb00439cb5d58623ecc2626f98 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Mon, 11 Sep 2023 15:58:32 +0000 Subject: [PATCH 05/17] rdfremont: add system info module config data for scp_ramfw System Info module provides API to obtain platform configuration data in a platform independent manner. So, add configuration data for system info module in scp ramfw. The configuration data specifies the PID module as the driver to obtain the platform configuration data. Signed-off-by: Shriram K Change-Id: I5de1b605ec66057709ea407865958504b9410562 --- .../rdfremont/scp_ramfw/config_system_info.c | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_system_info.c diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_system_info.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_system_info.c new file mode 100644 index 000000000..45fbbd448 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_system_info.c @@ -0,0 +1,27 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'system_info'. + */ + +#include +#include + +#include +#include +#include + +#include + +const struct fwk_module_config config_system_info = { + .data = &((struct mod_system_info_config){ + .system_info_driver_module_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SID), + .system_info_driver_data_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SID, + MOD_SID_SYSTEM_INFO_DRIVER_DATA_API_IDX), + }), +}; From c1beb21235209a9cb47b72678c6533300253a79d Mon Sep 17 00:00:00 2001 From: Shriram K Date: Mon, 11 Sep 2023 16:15:58 +0000 Subject: [PATCH 06/17] rdfremont: add pl011 module config data for scp_ramfw PL011 controller is used as a console port for debug and log messages. Add config data of this controller in scp ramfw, including base address and input clock frequency for the PL011 module to use. Signed-off-by: Shriram K Change-Id: I96ba337a98de643b1be6b998da05023308ac91e5 --- .../rdfremont/scp_ramfw/config_pl011.c | 40 +++++++++++++++++++ .../scp_ramfw/include/scp_css_mmap.h | 1 + 2 files changed, 41 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_pl011.c diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_pl011.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_pl011.c new file mode 100644 index 000000000..a1c0a8f30 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_pl011.c @@ -0,0 +1,40 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'pl011'. + */ + +#include "scp_css_mmap.h" + +#include + +#include +#include +#include +#include + +/* Module 'PL011' element count */ +#define MOD_PL011_ELEMENT_COUNT 2 + +static const struct fwk_element pl011_table[MOD_PL011_ELEMENT_COUNT] = { + { + .name = "scp_uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + .pd_id = FWK_ID_NONE_INIT, + }, + }, + { 0 }, +}; + +const struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(pl011_table), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h index 5a0789274..51fd2f10f 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -14,5 +14,6 @@ /* SCP sub-system peripherals */ #define SCP_SID_BASE (0x2A4A0000) +#define SCP_UART_BASE (0x44002000) #endif /* SCP_CSS_MMAP_H */ From d7fcf08bf462f203ffb08a4bc0679a3dd8626a7a Mon Sep 17 00:00:00 2001 From: Shriram K Date: Mon, 11 Sep 2023 14:10:56 +0000 Subject: [PATCH 07/17] rdfremont: configure I/O stream for scp_ramfw Configure the macros FMW_IO_STDIN_ID and FWM_IO_STDOUT_ID exposed by the I/O framework to set the SCP UART as the system entity responsible for handling I/O for the scp firmware. Signed-off-by: Shriram K Change-Id: I79424c10a61d2e12b8d1336cf4239f54d11b4c97 --- .../rdfremont/scp_ramfw/include/fmw_io.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_io.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_io.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_io.h new file mode 100644 index 000000000..ec7f58908 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_io.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_IO_H +#define FMW_IO_H + +#include +#include + +#define FMW_IO_STDIN_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) +#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) + +#endif /* FMW_IO_H */ From e6b12ca93297423897e2fbd1d1e60a5bcb2c8823 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Mon, 11 Sep 2023 16:30:54 +0000 Subject: [PATCH 08/17] rdfremont: add MPU module config data for scp_ramfw Add config data for armv7m_mpu module in scp ramfw. The SCP RAMs, trusted RAM and non-trusted memory regions are specified. Signed-off-by: Shriram K Change-Id: I4b0ac74a322f997894a6f9140ebce5ba4a62600d --- .../rdfremont/scp_ramfw/config_armv7m_mpu.c | 103 ++++++++++++++++++ .../rdfremont/scp_ramfw/include/fmw_cmsis.h | 44 ++++++++ .../scp_ramfw/include/scp_css_mmap.h | 14 +++ .../rdfremont/scp_ramfw/include/scp_fw_mmap.h | 42 +++++++ 4 files changed, 203 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_armv7m_mpu.c create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_cmsis.h create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/scp_fw_mmap.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_armv7m_mpu.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_armv7m_mpu.c new file mode 100644 index 000000000..9432317b0 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_armv7m_mpu.c @@ -0,0 +1,103 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'armv7m_mpu'. + */ + +#include "scp_css_mmap.h" +#include "scp_fw_mmap.h" + +#include + +#include +#include + +#include + +/* Number of regions to be configured in SCP's MPU */ +#define SCP_MPU_REGION_COUNT 5 + +static const ARM_MPU_Region_t regions[SCP_MPU_REGION_COUNT] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), + }, + { + /* 0x0000_0000 - 0x0003_FFFF */ + .RBAR = ARM_MPU_RBAR(1, SCP_ITC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, + { + /* 0x2000_0000 - 0x2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, SCP_DTC_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, + { + /* + * 0x7000_0000 - 0x7000_1FFF + * This is mapped to 0x0000_0000 - 0x0000_1FFF in AP memory map. + */ + .RBAR = ARM_MPU_RBAR(3, SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_8KB), + }, + { + /* + * 0x7000_2000 - 0x7000_3000 + * This is mapped to 0x0000_2000 - 0x0000_3000 in AP memory map. + */ + .RBAR = ARM_MPU_RBAR(4, SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_4KB), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_cmsis.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_cmsis.h new file mode 100644 index 000000000..3d6b3dfa5 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/fmw_cmsis.h @@ -0,0 +1,44 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include + +#define __CHECK_DEVICE_DEFINES +#define __CM7_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __ICACHE_PRESENT 0U +#define __DCACHE_PRESENT 0U +#define __DTCM_PRESENT 0U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U +#define __VTOR_PRESENT 1U + +/* System Clock Frequency (Core Clock) */ +extern uint32_t SystemCoreClock; + +typedef enum IRQn { + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + IRQn_MAX = INT16_MAX, +} IRQn_Type; + +#include + +#endif /* FMW_CMSIS_H */ diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h index 51fd2f10f..e38e10347 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -12,8 +12,22 @@ #ifndef SCP_CSS_MMAP_H #define SCP_CSS_MMAP_H +/* Base address and size of SCP's ITCM */ +#define SCP_ITC_RAM_BASE (0x00000000) +#define SCP_ITC_RAM_SIZE (256 * 1024) + +/* Base address and size of SCP's DTCM */ +#define SCP_DTC_RAM_BASE (0x20000000) +#define SCP_DTC_RAM_SIZE (256 * 1024) + /* SCP sub-system peripherals */ #define SCP_SID_BASE (0x2A4A0000) #define SCP_UART_BASE (0x44002000) +/* SCP addresses mapped via ATU into address translation windows */ +#define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) + +/* Offsets within SCP's Address Translation Window0 */ +#define SCP_ATW0_AP_PERIPHERAL_SRAM_OFFSET (0x10000000) + #endif /* SCP_CSS_MMAP_H */ diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_fw_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_fw_mmap.h new file mode 100644 index 000000000..ce38da3f1 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_fw_mmap.h @@ -0,0 +1,42 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address and size definitions for the various SCP's firmware defined + * memory carveouts. + */ + +#ifndef SCP_FW_MMAP_H +#define SCP_FW_MMAP_H + +#include "scp_css_mmap.h" + +#include + +#include + +/* + * AP Peripheral SRAM in the AP memory map with base address of 0x00000000 is + * mapped in the SCP's address translation window 0 (0x60000000 - 0x9FFFFFFF) + * at the offset 'SCP_ATW0_AP_PERIPHERAL_SRAM_OFFSET' via ATU configuration. + */ + +/* Secure SRAM size reserved by AP */ +#define SCP_AP_PERIPHERAL_SRAM_TRUSTED_RESERVED (0x19000) + +/* AP Peripheral trusted SRAM base in SCP's memory map */ +#define SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE \ + (SCP_ADDRESS_TRANSLATION_WINDOW0_BASE + \ + SCP_ATW0_AP_PERIPHERAL_SRAM_OFFSET + \ + SCP_AP_PERIPHERAL_SRAM_TRUSTED_RESERVED) +#define SCP_AP_PERIPHERAL_SRAM_TRUSTED_SIZE (4 * FWK_KIB) + +/* AP Peripheral non-trusted SRAM base in SCP's memory map */ +#define SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_BASE \ + (SCP_AP_PERIPHERAL_SRAM_TRUSTED_BASE + SCP_AP_PERIPHERAL_SRAM_TRUSTED_SIZE) +#define SCP_AP_PERIPHERAL_SRAM_NONTRUSTED_SIZE (4 * FWK_KIB) + +#endif /* SCP_FW_MMAP_H */ From 1df315d1bab2dbd1ead5529fc28ad05442f61c23 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Mon, 11 Sep 2023 20:14:49 +0000 Subject: [PATCH 09/17] rdfremont: add SCP power control block register declaration SCP's power control block includes registers for various system configuration and status. Add the register space declaration for this block. Signed-off-by: Shriram K Change-Id: I29cf403afa0b36b17f0a5e171e66a37a2ddf14b1 --- .../scp_ramfw/include/scp_css_mmap.h | 1 + .../rdfremont/scp_ramfw/include/scp_pwrctrl.h | 139 ++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/scp_pwrctrl.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h index e38e10347..7b862753a 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -23,6 +23,7 @@ /* SCP sub-system peripherals */ #define SCP_SID_BASE (0x2A4A0000) #define SCP_UART_BASE (0x44002000) +#define SCP_POWER_CONTROL_BASE (0x50000000) /* SCP addresses mapped via ATU into address translation windows */ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_pwrctrl.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_pwrctrl.h new file mode 100644 index 000000000..2c2988a6d --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_pwrctrl.h @@ -0,0 +1,139 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP Power Control registers + */ + +#ifndef SCP_PWRCTRL_H +#define SCP_PWRCTRL_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief SCP Power Control register definitions + */ + +// clang-format off +struct scp_power_control_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x18 - 0x14]; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP0; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP1; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP2; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP3; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP4; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP5; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP6; + FWK_RW uint32_t LCP2SCP_INT_SOURCE_GROUP7; + uint8_t RESERVED2[0x200 - 0x38]; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP0; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP1; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP2; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP3; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP4; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP5; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP6; + FWK_R uint32_t SCP2LCP_MHU_PBX_INT_SOURCE_GROUP7; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP0; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP1; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP2; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP3; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP4; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP5; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP6; + FWK_R uint32_t LCP2SCP_MHU_MBX_INT_SOURCE_GROUP7; + uint8_t RESERVED3[0x810 - 0x248]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED4[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED5[0x830 - 0x828]; + FWK_RW uint32_t GTSYNCCLK_CTRL; + FWK_RW uint32_t GTSYNCCLK_DIV1; + uint8_t RESERVED6[0x840 - 0x838]; + FWK_RW uint32_t LCPCLK_CTRL; + FWK_RW uint32_t LCPCLK_DIV1; + uint8_t RESERVED7[0xA00 - 0x848]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLEAR; + uint8_t RESERVED8[0xA50 - 0xA0C]; + FWK_R uint32_t CONS_MMUTCU_INT_STATUS; + FWK_W uint32_t CONS_MMUTCU_INT_CLR; + FWK_R uint32_t CONS_MMUTCU1_INT_STATUS; + FWK_W uint32_t CONS_MMUTCU1_INT_CLR; + uint8_t RESERVED9[0xA68 - 0xA60]; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; + FWK_W uint32_t CONS_MMUTBU_INT_CLR0; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; + FWK_W uint32_t CONS_MMUTBU_INT_CLR1; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS2; + FWK_W uint32_t CONS_MMUTBU_INT_CLR2; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS3; + FWK_W uint32_t CONS_MMUTBU_INT_CLR3; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS4; + FWK_W uint32_t CONS_MMUTBU_INT_CLR4; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS5; + FWK_W uint32_t CONS_MMUTBU_INT_CLR5; + uint8_t RESERVED10[0xB20 - 0xA98]; + FWK_R uint32_t CPU_PPU_INT_STATUS[8]; + FWK_R uint32_t CLUS_PPU_INT_STATUS[8]; + FWK_R uint32_t PROC_PEX_INT_STATUS[8]; + FWK_RW uint32_t CPU_PLL_LOCK_STATUS[8]; + uint8_t RESERVED11[0xBC0 - 0xBA0]; + FWK_RW uint32_t CPU_PLL_UNLOCK_STATUS[7]; + uint8_t RESERVED12[0xC10 - 0xBE0]; + FWK_W uint32_t SMCF_MGI_TRIGGER; + uint8_t RESERVED13[0xC20 - 0xC14]; + FWK_R uint32_t SRAMECC_ERRFR; + FWK_R uint32_t SRAMECC_ERRFR_H; + FWK_RW uint32_t SRAMECC_ERRCTRL; + FWK_RW uint32_t SRAMECC_ERRCTRL_H; + FWK_RW uint32_t SRAMECC_ERRSTATUS; + FWK_RW uint32_t SRAMECC_ERRSTATUS_H; + FWK_RW uint32_t SRAMECC_ERRADDR; + FWK_RW uint32_t SRAMECC_ERRADDR_H; + uint8_t RESERVED14[0xC48 - 0xC40]; + FWK_RW uint32_t SRAMECC_ERRMISC1; + FWK_RW uint32_t SRAMECC_ERRMISC1_H; + uint8_t RESERVED15[0xC60 - 0xC50]; + FWK_R uint32_t SYSNCI_PMU_CONS_INT_STATUS; + FWK_R uint32_t SYSNCI_CONS_INT_STATUS; + FWK_R uint32_t INTNCI_PMU_CONS_INT_STATUS; + FWK_R uint32_t INTNCI_CONS_INT_STATUS; + FWK_R uint32_t PERIPHNCI_PMU_CONS_INT_STATUS; + FWK_R uint32_t PERIPHNCI_CONS_INT_STATUS; + uint8_t RESERVED16[0xFC0 - 0xC78]; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED17[0xFD0 - 0xFC4]; + FWK_R uint32_t PERIPHERAL_ID4; + FWK_R uint32_t PERIPHERAL_ID5; + FWK_R uint32_t PERIPHERAL_ID6; + FWK_R uint32_t PERIPHERAL_ID7; + FWK_R uint32_t PERIPHERAL_ID0; + FWK_R uint32_t PERIPHERAL_ID1; + FWK_R uint32_t PERIPHERAL_ID2; + FWK_R uint32_t PERIPHERAL_ID3; + FWK_R uint32_t COMPONENT_ID0; + FWK_R uint32_t COMPONENT_ID1; + FWK_R uint32_t COMPONENT_ID2; + FWK_R uint32_t COMPONENT_ID3; +}; +// clang-format on + +/* Pointer to SCP Power Control register block */ +#define SCP_PWRCTRL_PTR ((struct scp_power_control_reg *)SCP_POWER_CONTROL_BASE) + +#endif /* SCP_PWRCTRL_H */ From 3e325b92132082a9f1fa63166dd8dbfba6d98323 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Tue, 12 Sep 2023 04:55:31 +0000 Subject: [PATCH 10/17] rdfremont: add core manager register block declaration Core Manager block includes registers for configuration and clock control for application cores and the associated clusters. Add the register space declaration and the base address macro for the core manager block. Signed-off-by: Shriram K Change-Id: I14c91e97947b70dd6c2e3fa885e9b9ef00a0713d --- .../scp_ramfw/include/core_manager.h | 76 +++++++++++++++++++ .../scp_ramfw/include/scp_css_mmap.h | 26 +++++++ 2 files changed, 102 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/core_manager.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/core_manager.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/core_manager.h new file mode 100644 index 000000000..1982e890e --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/core_manager.h @@ -0,0 +1,76 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Core Manager and clock control registers + */ + +#ifndef CORE_MANAGER_H +#define CORE_MANAGER_H + +#include "scp_css_mmap.h" + +#include + +#include + +// clang-format off +struct core_manager_reg { + uint8_t RESERVED0[0x10 - 0x00]; + FWK_RW uint32_t PE_STATIC_CONFIG; + uint8_t RESERVED1[0x18 - 0x14]; + FWK_RW uint32_t PE_RVBARADDR_LW; + FWK_RW uint32_t PE_RVBARADDR_UP; + uint8_t RESERVED2[0x030-0x020]; + FWK_R uint32_t PE_STATUS; + uint8_t RESERVED3[0x800-0x034]; + FWK_RW uint32_t CLUS_MGRCLK_CTRL; + FWK_RW uint32_t CLUS_MGRCLK_DIV1; + uint8_t RESERVED4[0x820 - 0x808]; + FWK_RW uint32_t CLUS_EXP1CLK_CTRL; + FWK_RW uint32_t CLUS_EXP1CLK_DIV; + uint8_t RESERVED5[0x830 - 0x828]; + FWK_RW uint32_t CLUS_EXP2CLK_CTRL; + FWK_RW uint32_t CLUS_EXP2CLK_DIV; + uint8_t RESERVED6[0x840 - 0x838]; + FWK_RW uint32_t CLUS_GICCLK_CTRL; + FWK_RW uint32_t CLUS_GICCLK_DIV1; + uint8_t RESERVED7[0x850 -0x848]; + FWK_RW uint32_t CLUS_PERIPHCLK_CTRL; + FWK_RW uint32_t CLUS_PERIPHCLK_DIV1; + uint8_t RESERVED8[0x860 - 0x858]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + FWK_RW uint32_t CORECLK_MOD1; + uint8_t RESERVED9[0xA00 - 0x086C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED10[0x0FB4 - 0x0A0C]; + FWK_R uint32_t CAP3; + FWK_R uint32_t CAP2; + FWK_R uint32_t CAP1; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; +// clang-format on + +#define SCP_CLUSTER_UTILITY_CORE_MANAGER_PTR(IDX) \ + ((struct core_manager_reg *)SCP_CLUSTER_UTILITY_CORE_MANAGER_BASE(IDX)) + +#endif /* CORE_MANAGER_H */ diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h index 7b862753a..dbddb9331 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -29,6 +29,32 @@ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) /* Offsets within SCP's Address Translation Window0 */ +#define SCP_ATW0_LCP_AND_CLUSTER_UTILITY_OFFSET (0x0) #define SCP_ATW0_AP_PERIPHERAL_SRAM_OFFSET (0x10000000) +/* + * LCP subsystem and Cluster Utility memory region that is addressable in the AP + * memory map between 0x2_0000_0000 - 0x2_0FFF_FFFF is mapped in the SCP address + * translation window 0 from 0x6000_0000 to 0x6FFF_FFFF via ATU configuration. + */ + +/* + * Size of SCP's view of per-cluster LCP subsystem and utility memory region. + */ +#define SCP_LCP_AND_CLUSTER_UTILITY_SIZE (0x200000) + +/* + * Offsets of various blocks within LCP subsystem and cluster utility that is + * mapped into SCP's address translation window 0. These offsets are applicable + * to each cluster in the system. + */ +#define SCP_CLUSTER_UTILITY_CORE_MANAGER_OFFSET (0x80000) + +/* Core Manager base address for a cluster 'n' */ +#define SCP_CLUSTER_UTILITY_CORE_MANAGER_BASE(n) \ + (SCP_ADDRESS_TRANSLATION_WINDOW0_BASE + \ + SCP_ATW0_LCP_AND_CLUSTER_UTILITY_OFFSET + \ + (n * SCP_LCP_AND_CLUSTER_UTILITY_SIZE) + \ + SCP_CLUSTER_UTILITY_CORE_MANAGER_OFFSET) + #endif /* SCP_CSS_MMAP_H */ From f43b7159575dbb2208c8f7799841d4e7e6121d9c Mon Sep 17 00:00:00 2001 From: Shriram K Date: Tue, 12 Sep 2023 08:56:14 +0000 Subject: [PATCH 11/17] rdfremont: add System PIK register space declaration System Power Integration Kit (PIK) control register block includes registers for clock control of clocks in SYSTOP power domain. Add the register space declaration for System PIK. Signed-off-by: Shriram K Change-Id: Ib6623d872b956923f0d604f33d0c710a9e702fc5 --- .../scp_ramfw/include/scp_css_mmap.h | 1 + .../rdfremont/scp_ramfw/include/system_pik.h | 80 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/system_pik.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h index dbddb9331..b676e5d74 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -24,6 +24,7 @@ #define SCP_SID_BASE (0x2A4A0000) #define SCP_UART_BASE (0x44002000) #define SCP_POWER_CONTROL_BASE (0x50000000) +#define SCP_SYSTEM_PIK_BASE (0x50040000) /* SCP addresses mapped via ATU into address translation windows */ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/system_pik.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/system_pik.h new file mode 100644 index 000000000..2c5272199 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/system_pik.h @@ -0,0 +1,80 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP System PIK registers + */ + +#ifndef SYSTEM_PIK_H +#define SYSTEM_PIK_H + +#include "scp_css_mmap.h" + +#include + +#include + +/*! + * \brief System PIK register definitions + */ + +// clang-format off +struct system_pik_reg { + uint8_t RESERVED0[0x820 - 0x0]; + FWK_RW uint32_t INTCLK_CTRL; + FWK_RW uint32_t INTCLK_DIV1; + uint8_t RESERVED1[0x850 - 0x828]; + FWK_RW uint32_t GICCLK_CTRL; + FWK_RW uint32_t GICCLK_DIV1; + uint8_t RESERVED2[0x860 - 0x858]; + FWK_RW uint32_t SCPPIKCLK_CTRL; + FWK_RW uint32_t SCPPIKCLK_DIV1; + uint8_t RESERVED3[0x870 - 0x868]; + FWK_RW uint32_t SYSPERCLK_CTRL; + FWK_RW uint32_t SYSPERCLK_DIV1; + uint8_t RESERVED4[0x8A0 - 0x878]; + FWK_RW uint32_t APUARTCLK_CTRL; + FWK_RW uint32_t APUARTCLK_DIV1; + uint8_t RESERVED5[0x8B0 - 0x8A8]; + FWK_RW uint32_t IONCICLK_CTRL; + FWK_RW uint32_t IONCICLK_DIV1; + uint8_t RESERVED6[0x900 - 0x8B8]; + FWK_RW uint32_t TCUCLK_CTRL; + FWK_RW uint32_t TCUCLK_DIV1; + uint8_t RESERVED7[0x940 - 0x908]; + FWK_RW uint32_t TCU_CLK_ENABLE; + FWK_RW uint32_t NCI_CLK_ENABLE; + uint8_t RESERVED8[0xA00 - 0x948]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB10 - 0xA0C]; + FWK_RW uint32_t IOMACRO_OVERRIDE; + FWK_RW uint32_t RSSPSI_STATUS; + FWK_RW uint32_t RSSSAM_STATUS0; + FWK_RW uint32_t RSSSAM_STATUS1; + FWK_RW uint32_t RSSLCM_STATUS; + uint8_t RESERVED10[0xFC0 - 0xB24]; + FWK_R uint32_t PIK_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; +// clang-format on + +#define SYSTEM_PIK_PTR ((struct system_pik_reg *)SCP_SYSTEM_PIK_BASE) + +#endif /* SYSTEM_PIK_H */ From 522e4f5728543a0846b23cce242e767eebdc01f6 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 14 Sep 2023 12:33:05 +0000 Subject: [PATCH 12/17] rdfremont: add config data for system pll driver in scp_ramfw PLLs are connected to the SCP's expansion3 memory region. Add the configuration data for the module 'system_pll' that will manage and setup these PLLs to required frequency. The configuration data includes the SYSTOP PLL and the interconnect PLL. Signed-off-by: Shriram K Change-Id: Ia1d80d8631f7200069745130ee92f031008f58bb --- .../rdfremont/scp_ramfw/config_system_pll.c | 61 +++++++++++++++++++ .../rdfremont/scp_ramfw/include/scp_clock.h | 23 +++++++ .../scp_ramfw/include/scp_css_mmap.h | 3 + .../scp_ramfw/include/scp_exp_mmap.h | 27 ++++++++ 4 files changed, 114 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_system_pll.c create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/scp_exp_mmap.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_system_pll.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_system_pll.c new file mode 100644 index 000000000..490eb4d73 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_system_pll.c @@ -0,0 +1,61 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'system_pll'. + */ + +#include "scp_clock.h" +#include "scp_exp_mmap.h" +#include "scp_pwrctrl.h" + +#include + +#include +#include +#include +#include + +/* Module 'system_pll' element count */ +#define MOD_SYSTEM_PLL_ELEMENT_COUNT (CFGD_MOD_SYSTEM_PLL_EIDX_COUNT + 1) + +static const struct fwk_element sys_pll_table[MOD_SYSTEM_PLL_ELEMENT_COUNT] = { + [CFGD_MOD_SYSTEM_PLL_EIDX_SYS] = { + .name = "SYS_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_SYSPLL, + .status_reg = (void *)SCP_PLL_STATUS0, + .lock_flag_mask = PLL_STATUS_0_SYSPLL_LOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CFGD_MOD_SYSTEM_PLL_EIDX_INTERCONNECT] = { + .name = "INT_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_INTERCONNECT, + .status_reg = (void *)SCP_PLL_STATUS0, + .lock_flag_mask = PLL_STATUS_0_INTPLL_LOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CFGD_MOD_SYSTEM_PLL_EIDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *system_pll_get_element_table( + fwk_id_t module_id) +{ + return sys_pll_table; +} + +const struct fwk_module_config config_system_pll = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h new file mode 100644 index 000000000..46442cf74 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h @@ -0,0 +1,23 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP clock definitions. + */ + +#ifndef SCP_CLOCK_H +#define SCP_CLOCK_H + +/* + * PLL clock indices. + */ +enum clock_pll_idx { + CFGD_MOD_SYSTEM_PLL_EIDX_SYS, + CFGD_MOD_SYSTEM_PLL_EIDX_INTERCONNECT, + CFGD_MOD_SYSTEM_PLL_EIDX_COUNT +}; + +#endif /* SCP_CLOCK_H */ diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h index b676e5d74..0c552662f 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_css_mmap.h @@ -26,6 +26,9 @@ #define SCP_POWER_CONTROL_BASE (0x50000000) #define SCP_SYSTEM_PIK_BASE (0x50040000) +/* Base address of SCP expansion memory regions */ +#define SCP_SOC_EXPANSION3_BASE (0x40000000) /* 64MB size */ + /* SCP addresses mapped via ATU into address translation windows */ #define SCP_ADDRESS_TRANSLATION_WINDOW0_BASE (0x60000000) diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_exp_mmap.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_exp_mmap.h new file mode 100644 index 000000000..0a97ab58c --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_exp_mmap.h @@ -0,0 +1,27 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Base address definitions for the SCP's expansion memory regions. + */ + +#ifndef SCP_EXP_MMAP_H +#define SCP_EXP_MMAP_H + +#include "scp_css_mmap.h" + +/* PLLs are connected in SCP's expansion3 memory region */ +#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) + +#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) +#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) +#define SCP_PLL_STATUS0 (SCP_PLL_BASE + 0x00000180) + +/* PLL lock status flag mask */ +#define PLL_STATUS_0_SYSPLL_LOCK (0x00000002) +#define PLL_STATUS_0_INTPLL_LOCK (0x00000008) + +#endif /* SCP_EXP_MMAP_H */ From d762551927e6666a7c1667693630bff5a34ad3f8 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 14 Sep 2023 12:39:55 +0000 Subject: [PATCH 13/17] rdfremont: add config data for PIK clock driver in scp_ramfw The configuration data for PIK clock devices includes register address of its control and dividers, the rate table and the initial rate. The clock controller devices for all the CPUs, interconnect, systop, gic, scp, uart and other clocks are included in the configuration data. Signed-off-by: Shriram K Change-Id: I5c41e4bfe379f41bf90fb6bcaf2e0f32bab535a1 --- .../rdfremont/scp_ramfw/config_pik_clock.c | 229 ++++++++++++++++++ .../rdfremont/scp_ramfw/include/clock_css.h | 18 ++ .../rdfremont/scp_ramfw/include/scp_clock.h | 35 +++ 3 files changed, 282 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_pik_clock.c create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/clock_css.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_pik_clock.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_pik_clock.c new file mode 100644 index 000000000..03e843602 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_pik_clock.c @@ -0,0 +1,229 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'pik_clock'. + */ + +#include "core_manager.h" +#include "scp_clock.h" +#include "scp_pwrctrl.h" +#include "system_pik.h" + +#include + +#include +#include +#include +#include + +#include + +/* Rate table count */ +#define CPU_CLK_RATE_COUNT 1 +#define INT_CLK_RATE_COUNT 1 +#define SCP_CLK_RATE_COUNT 1 +#define GIC_CLK_RATE_COUNT 1 +#define SCP_PIK_CLK_RATE_COUNT 1 +#define SYSPER_CLK_RATE_COUNT 1 +#define UART_CLK_RATE_COUNT 1 + +/* Module 'pik_clock' element count */ +#define MOD_PIK_CLOCK_ELEMENT_COUNT (CFGD_MOD_PIK_CLOCK_EIDX_COUNT + 1) + +#define CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(n) \ + [CFGD_MOD_PIK_CLOCK_EIDX_CPU##n] = { \ + .name = "PIK CLK CPU" #n, \ + .data = &((struct mod_pik_clock_dev_config){ \ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, \ + .is_group_member = false, \ + .control_reg = \ + &SCP_CLUSTER_UTILITY_CORE_MANAGER_PTR(n)->CORECLK_CTRL, \ + .divext_reg = \ + &SCP_CLUSTER_UTILITY_CORE_MANAGER_PTR(n)->CORECLK_DIV1, \ + .rate_table = rate_table_cpu_clk, \ + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_clk), \ + .initial_rate = 0, \ + }), \ + } + +/* CPU clock rate table */ +static const struct mod_pik_clock_rate + rate_table_cpu_clk[CPU_CLK_RATE_COUNT] = { + { + .rate = 0, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, + }; + +/* Cache Coherent Interconnect clock rate table */ +static const struct mod_pik_clock_rate + rate_table_int_clk[INT_CLK_RATE_COUNT] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_INTCLK_SOURCE_INTPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, + }; + +/* SCP CORE clock rate table */ +static const struct mod_pik_clock_rate + rate_table_scp_clk[SCP_CLK_RATE_COUNT] = { + { + .rate = 800 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (800 * FWK_MHZ), + }, + }; + +/* GIC clock rate table */ +static const struct mod_pik_clock_rate + rate_table_gic_clk[GIC_CLK_RATE_COUNT] = { + { + .rate = 1000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (1000 * FWK_MHZ), + }, + }; + +/* SCP PIK clock rate table */ +static const struct mod_pik_clock_rate + rate_table_scp_pik_clk[SCP_PIK_CLK_RATE_COUNT] = { + { + .rate = 400 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (400 * FWK_MHZ), + }, + }; + +/* System Peripheral clock rate table */ +static const struct mod_pik_clock_rate + rate_table_sysper_clk[SYSPER_CLK_RATE_COUNT] = { + { + .rate = 500 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (500 * FWK_MHZ), + }, + }; + +/* UART clock rate table */ +static const struct mod_pik_clock_rate + rate_table_uart_clk[UART_CLK_RATE_COUNT] = { + { + .rate = 250 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ), + }, + }; + +static const struct fwk_element pik_clock_table[MOD_PIK_CLOCK_ELEMENT_COUNT] = { + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(0), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(1), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(2), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(3), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(4), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(5), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(6), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(7), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(8), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(9), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(10), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(11), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(12), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(13), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(14), + CFGD_MOD_PIK_CLOCK_ELEMENT_CPU(15), + [CFGD_MOD_PIK_CLOCK_EIDX_CMN] = { + .name = "PIK CLK CMN", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->INTCLK_CTRL, + .divext_reg = &SYSTEM_PIK_PTR->INTCLK_DIV1, + .rate_table = rate_table_int_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_int_clk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_SCP] = { + .name = "PIK CLK SCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCP_PWRCTRL_PTR->CORECLK_CTRL, + .divsys_reg = &SCP_PWRCTRL_PTR->CORECLK_DIV1, + .rate_table = rate_table_scp_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_clk), + .initial_rate = 800 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_GIC] = { + .name = "PIK CLK GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, + .rate_table = rate_table_gic_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gic_clk), + .initial_rate = 1000 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_SCP_PIK] = { + .name = "PIK CLK SCP PIK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SCPPIKCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SCPPIKCLK_DIV1, + .rate_table = rate_table_scp_pik_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp_pik_clk), + .initial_rate = 400 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_SYSPERCLK] = { + .name = "PIK CLK SYSPER", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, + .rate_table = rate_table_sysper_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysper_clk), + .initial_rate = 500 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_UARTCLK] = { + .name = "PIK CLK UART", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->APUARTCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->APUARTCLK_DIV1, + .rate_table = rate_table_uart_clk, + .rate_count = FWK_ARRAY_SIZE(rate_table_uart_clk), + .initial_rate = 250 * FWK_MHZ, + }), + }, + [CFGD_MOD_PIK_CLOCK_EIDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) +{ + return pik_clock_table; +} + +const struct fwk_module_config config_pik_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/clock_css.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/clock_css.h new file mode 100644 index 000000000..f8be45862 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/clock_css.h @@ -0,0 +1,18 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * CSS clock definitions. + */ + +#ifndef CLOCK_CSS_H +#define CLOCK_CSS_H + +#include + +#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) + +#endif /* CLOCK_CSS_H */ diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h index 46442cf74..4c3f390e4 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h @@ -11,6 +11,12 @@ #ifndef SCP_CLOCK_H #define SCP_CLOCK_H +#include "clock_css.h" + +#include + +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) + /* * PLL clock indices. */ @@ -20,4 +26,33 @@ enum clock_pll_idx { CFGD_MOD_SYSTEM_PLL_EIDX_COUNT }; +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CFGD_MOD_PIK_CLOCK_EIDX_CPU0, + CFGD_MOD_PIK_CLOCK_EIDX_CPU1, + CFGD_MOD_PIK_CLOCK_EIDX_CPU2, + CFGD_MOD_PIK_CLOCK_EIDX_CPU3, + CFGD_MOD_PIK_CLOCK_EIDX_CPU4, + CFGD_MOD_PIK_CLOCK_EIDX_CPU5, + CFGD_MOD_PIK_CLOCK_EIDX_CPU6, + CFGD_MOD_PIK_CLOCK_EIDX_CPU7, + CFGD_MOD_PIK_CLOCK_EIDX_CPU8, + CFGD_MOD_PIK_CLOCK_EIDX_CPU9, + CFGD_MOD_PIK_CLOCK_EIDX_CPU10, + CFGD_MOD_PIK_CLOCK_EIDX_CPU11, + CFGD_MOD_PIK_CLOCK_EIDX_CPU12, + CFGD_MOD_PIK_CLOCK_EIDX_CPU13, + CFGD_MOD_PIK_CLOCK_EIDX_CPU14, + CFGD_MOD_PIK_CLOCK_EIDX_CPU15, + CFGD_MOD_PIK_CLOCK_EIDX_CMN, + CFGD_MOD_PIK_CLOCK_EIDX_SCP, + CFGD_MOD_PIK_CLOCK_EIDX_GIC, + CFGD_MOD_PIK_CLOCK_EIDX_SCP_PIK, + CFGD_MOD_PIK_CLOCK_EIDX_SYSPERCLK, + CFGD_MOD_PIK_CLOCK_EIDX_UARTCLK, + CFGD_MOD_PIK_CLOCK_EIDX_COUNT +}; + #endif /* SCP_CLOCK_H */ From ce8e70f25c848bebc7f5cd893dbad8172bba0972 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 14 Sep 2023 14:39:32 +0000 Subject: [PATCH 14/17] rdfremont: add config data for subsystem clock driver in scp_ramfw The application core clocks is configured by the css clock driver. Add the configuration data for this driver that includes the rate table, initial rate and PLL driving each of the css clocks. Signed-off-by: Shriram K Change-Id: I8d91329d2e41e020856002c619c735771062a105 --- .../rdfremont/scp_ramfw/config_css_clock.c | 146 ++++++++++++++++++ .../rdfremont/scp_ramfw/include/scp_clock.h | 23 +++ 2 files changed, 169 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_css_clock.c diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_css_clock.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_css_clock.c new file mode 100644 index 000000000..3a972c673 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_css_clock.c @@ -0,0 +1,146 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'css_clock'. + */ + +#include "scp_clock.h" + +#include +#include +#include + +#include +#include +#include +#include + +/* Module 'css_clock' element count */ +#define MOD_CSS_CLOCK_ELEMENT_COUNT (CFGD_MOD_CSS_CLOCK_EIDX_COUNT + 1) + +/* CPU clock rate table count */ +#define CPU_RATE_TABLE_COUNT 3 + +/* + * Helper macro to instantiate a member table that lists the clocks included in + * a CPU clock device. + */ +#define CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(n) \ + static const fwk_id_t css_clock_dev_member_table_cpu##n[] = { \ + FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_PIK_CLOCK, CFGD_MOD_PIK_CLOCK_EIDX_CPU##n), \ + } + +/* + * Helper macro to instantiate a CPU clock device. + */ +#define CSS_CLOCK_DEV_CPU(n) \ + [CFGD_MOD_CSS_CLOCK_EIDX_CPU##n] = { \ + .name = "CPU_" #n, \ + .data = &((struct mod_css_clock_dev_config){ \ + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, \ + .rate_table = rate_table_cpu, \ + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu), \ + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, \ + .pll_id = FWK_ID_ELEMENT_INIT( \ + FWK_MODULE_IDX_SYSTEM_PLL, CFGD_MOD_SYSTEM_PLL_EIDX_CPU##n), \ + .pll_api_id = FWK_ID_API_INIT( \ + FWK_MODULE_IDX_SYSTEM_PLL, MOD_SYSTEM_PLL_API_TYPE_DEFAULT), \ + .member_table = css_clock_dev_member_table_cpu##n, \ + .member_count = FWK_ARRAY_SIZE(css_clock_dev_member_table_cpu##n), \ + .member_api_id = FWK_ID_API_INIT( \ + FWK_MODULE_IDX_PIK_CLOCK, MOD_PIK_CLOCK_API_TYPE_CSS), \ + .initial_rate = 2600 * FWK_MHZ, \ + .modulation_supported = true, \ + }), \ + } + +/* + * List of application core clock speeds + */ +static const struct mod_css_clock_rate rate_table_cpu[CPU_RATE_TABLE_COUNT] = { + { + .rate = 2300 * FWK_MHZ, + .pll_rate = 2300 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + .rate = 3200 * FWK_MHZ, + .pll_rate = 3200 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +/* + * Instantiate clock device member table for all the application core clocks. + */ +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(0); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(1); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(2); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(3); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(4); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(5); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(6); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(7); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(8); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(9); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(10); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(11); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(12); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(13); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(14); +CSS_CLOCK_DEV_MEMBER_TABLE_CPUCLK(15); + +/* + * Instantiate 'css_clock' module elements. + */ +static const struct fwk_element + css_clock_element_table[MOD_CSS_CLOCK_ELEMENT_COUNT] = { + CSS_CLOCK_DEV_CPU(0), + CSS_CLOCK_DEV_CPU(1), + CSS_CLOCK_DEV_CPU(2), + CSS_CLOCK_DEV_CPU(3), + CSS_CLOCK_DEV_CPU(4), + CSS_CLOCK_DEV_CPU(5), + CSS_CLOCK_DEV_CPU(6), + CSS_CLOCK_DEV_CPU(7), + CSS_CLOCK_DEV_CPU(8), + CSS_CLOCK_DEV_CPU(9), + CSS_CLOCK_DEV_CPU(10), + CSS_CLOCK_DEV_CPU(11), + CSS_CLOCK_DEV_CPU(12), + CSS_CLOCK_DEV_CPU(13), + CSS_CLOCK_DEV_CPU(14), + CSS_CLOCK_DEV_CPU(15), + [CFGD_MOD_CSS_CLOCK_EIDX_COUNT] = { 0 }, + }; + +static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) +{ + return css_clock_element_table; +} + +const struct fwk_module_config config_css_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h index 4c3f390e4..38f1c4443 100644 --- a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_clock.h @@ -55,4 +55,27 @@ enum clock_pik_idx { CFGD_MOD_PIK_CLOCK_EIDX_COUNT }; +/* + * Module 'css_clock' element indexes + */ +enum cfgd_mod_css_clock_element_idx { + CFGD_MOD_CSS_CLOCK_EIDX_CPU0, + CFGD_MOD_CSS_CLOCK_EIDX_CPU1, + CFGD_MOD_CSS_CLOCK_EIDX_CPU2, + CFGD_MOD_CSS_CLOCK_EIDX_CPU3, + CFGD_MOD_CSS_CLOCK_EIDX_CPU4, + CFGD_MOD_CSS_CLOCK_EIDX_CPU5, + CFGD_MOD_CSS_CLOCK_EIDX_CPU6, + CFGD_MOD_CSS_CLOCK_EIDX_CPU7, + CFGD_MOD_CSS_CLOCK_EIDX_CPU8, + CFGD_MOD_CSS_CLOCK_EIDX_CPU9, + CFGD_MOD_CSS_CLOCK_EIDX_CPU10, + CFGD_MOD_CSS_CLOCK_EIDX_CPU11, + CFGD_MOD_CSS_CLOCK_EIDX_CPU12, + CFGD_MOD_CSS_CLOCK_EIDX_CPU13, + CFGD_MOD_CSS_CLOCK_EIDX_CPU14, + CFGD_MOD_CSS_CLOCK_EIDX_CPU15, + CFGD_MOD_CSS_CLOCK_EIDX_COUNT +}; + #endif /* SCP_CLOCK_H */ From caa5b48206fe5f93e5bb38434d3cd9738216f4d6 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Thu, 14 Sep 2023 14:44:39 +0000 Subject: [PATCH 15/17] rdfremont: add helpers to obtain platform topology in scp_ramfw Add functions to obtain the platform topology information such as core count and cluster count. These functions can be used in module config data to obtain platform topology. Signed-off-by: Shriram K Change-Id: Ice0495d8f1dbb3541f3b3c47e0ab0bb756dffbd7 --- .../scp_ramfw/include/platform_core.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/platform_core.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/platform_core.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/platform_core.h new file mode 100644 index 000000000..f208d9b80 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/platform_core.h @@ -0,0 +1,43 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Platform generic definitions. + */ + +#ifndef PLATFORM_CORE_H +#define PLATFORM_CORE_H + +#include + +#define PLATFORM_CORE_PER_CLUSTER_MAX 1 + +#define CORES_PER_CLUSTER 1 +#define NUMBER_OF_CLUSTERS 16 + +/* Number of chips supported on the platform. */ +enum platform_chip_id { PLATFORM_CHIP_0, PLATFORM_CHIP_COUNT }; + +static inline unsigned int platform_get_cluster_count(void) +{ + return NUMBER_OF_CLUSTERS; +} + +static inline unsigned int platform_get_core_per_cluster_count( + unsigned int cluster) +{ + fwk_assert(cluster < platform_get_cluster_count()); + + return CORES_PER_CLUSTER; +} + +static inline unsigned int platform_get_core_count(void) +{ + return platform_get_core_per_cluster_count(0) * + platform_get_cluster_count(); +} + +#endif /* PLATFORM_CORE_H */ From a39e8ab01fa04f8c4b8fb4c0d81f0de586d34e75 Mon Sep 17 00:00:00 2001 From: Shriram K Date: Tue, 12 Sep 2023 12:33:37 +0000 Subject: [PATCH 16/17] rdfremont: add config data for power domain module in scp_ramfw Provide the configuration data of all the available power domains to the power domain HAL. The configuration data includes details of all the supported CPU, cluster and the SYSTOP power domain. Signed-off-by: Shriram K Change-Id: If4a67cf0559668712fadc2d863e9a06feb569fbb --- .../rdfremont/scp_ramfw/config_power_domain.c | 111 ++++++++++++++++++ .../scp_ramfw/include/scp_cfgd_power_domain.h | 29 +++++ 2 files changed, 140 insertions(+) create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/config_power_domain.c create mode 100644 product/neoverse-rd/rdfremont/scp_ramfw/include/scp_cfgd_power_domain.h diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_power_domain.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_power_domain.c new file mode 100644 index 000000000..1a8e8a50c --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/config_power_domain.c @@ -0,0 +1,111 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Configuration data for module 'power_domain'. + */ + +#include "platform_core.h" +#include "scp_cfgd_power_domain.h" + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Module 'power_domain' static element count */ +#define PD_STATIC_ELEMENT_COUNT (PD_STATIC_DEV_IDX_SYSTOP + 1) + +/* Allowed PD state count */ +#define SYSTOP_PD_STATE_COUNT 1 +#define CLUS_PD_STATE_COUNT 2 +#define CORE_PD_STATE_COUNT 2 + +/* Maximum power domain name size including the null terminator */ +#define PD_NAME_SIZE 12 + +/* Mask for the cluster valid power states */ +#define CLUSTER_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) + +/* Mask for the core valid power states */ +#define CORE_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) + +/* Mask of the allowed states for the systop power domain */ +static const uint32_t systop_allowed_state_mask_table[SYSTOP_PD_STATE_COUNT] = { + [0] = MOD_PD_STATE_ON_MASK +}; + +/* + * Mask of the allowed states for the cluster power domain depending on the + * system states. + */ +static const uint32_t + cluster_pd_allowed_state_mask_table[CLUS_PD_STATE_COUNT] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = CLUSTER_VALID_STATE_MASK, + }; + +/* Mask of the allowed states for a core depending on the cluster states. */ +static const uint32_t core_pd_allowed_state_mask_table[CORE_PD_STATE_COUNT] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = CORE_VALID_STATE_MASK, +}; + +/* Power module specific configuration data (none) */ +static const struct mod_power_domain_config platform_power_domain_config = { + 0 +}; + +static struct fwk_element pd_static_element_table[PD_STATIC_ELEMENT_COUNT] = { + [PD_STATIC_DEV_IDX_SYSTOP] = { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .parent_idx = PD_STATIC_DEV_IDX_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) + }), + }, +}; + +static const struct fwk_element *platform_power_domain_get_element_table( + fwk_id_t module_id) +{ + return create_power_domain_element_table( + platform_get_core_count(), + platform_get_cluster_count(), + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER, + core_pd_allowed_state_mask_table, + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table), + cluster_pd_allowed_state_mask_table, + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table), + pd_static_element_table, + FWK_ARRAY_SIZE(pd_static_element_table)); +} + +const struct fwk_module_config config_power_domain = { + .data = &platform_power_domain_config, + .elements = + FWK_MODULE_DYNAMIC_ELEMENTS(platform_power_domain_get_element_table), +}; diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_cfgd_power_domain.h b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_cfgd_power_domain.h new file mode 100644 index 000000000..4c1a43de1 --- /dev/null +++ b/product/neoverse-rd/rdfremont/scp_ramfw/include/scp_cfgd_power_domain.h @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for power domain module configuration data in SCP-firmware. + */ + +#ifndef SCP_CFGD_POWER_DOMAIN_H +#define SCP_CFGD_POWER_DOMAIN_H + +#include + +/* + * Power domain indices for the statically defined domains used for: + * - Indexing the domains in the platform_power_domain_static_element_table + * - Indexing the SYSTOP children in the power domain tree + * + * When calculating a power domain element index, use the formula: + * core_count + cluster_count + pd_static_dev_idx + */ +enum pd_static_dev_idx { + PD_STATIC_DEV_IDX_SYSTOP, + PD_STATIC_DEV_IDX_NONE = UINT32_MAX +}; + +#endif /* SCP_CFGD_POWER_DOMAIN_H */ From f29ae1c08da55d6465a4ed6576dfd4ee5681fe0c Mon Sep 17 00:00:00 2001 From: Joe Zhu Date: Fri, 19 May 2023 17:15:34 +0800 Subject: [PATCH 17/17] module: timer: add API to update timer status without alarm Some devices need overflow interrupt to update internal status. Add new driver API to handle this if there is no acitve alarm. Change-Id: I6a3106beb8dce8de7de29dfa5ff5742a9fd9692b Signed-off-by: Joe Zhu --- module/timer/include/mod_timer.h | 9 ++++++++- module/timer/src/mod_timer.c | 13 ++++++++++--- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/module/timer/include/mod_timer.h b/module/timer/include/mod_timer.h index c7b7f37d5..1d583a9a1 100644 --- a/module/timer/include/mod_timer.h +++ b/module/timer/include/mod_timer.h @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -120,6 +120,13 @@ struct mod_timer_driver_api { /*! Get counter frequency */ int (*get_frequency)(fwk_id_t dev_id, uint32_t *value); + + /*! + * Timer device may need to update internal status in alarm or overflow + * event. This handler is used to process overflow event when there is no + * active alarm. Optional + */ + void (*overflow_handler)(fwk_id_t dev_id); }; /*! diff --git a/module/timer/src/mod_timer.c b/module/timer/src/mod_timer.c index f65f27d35..c944798d2 100644 --- a/module/timer/src/mod_timer.c +++ b/module/timer/src/mod_timer.c @@ -1,6 +1,6 @@ /* * Arm SCP/MCP Software - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -557,8 +557,15 @@ static void timer_isr(uintptr_t ctx_ptr) (struct alarm_sub_element_ctx *)fwk_list_pop_head(&ctx->alarms_active); if (alarm == NULL) { - /* Timer interrupt triggered without any alarm in the active queue */ - fwk_unexpected(); + if (ctx->driver->overflow_handler != NULL) { + ctx->driver->overflow_handler(ctx->driver_dev_id); + } else { + /* + * Timer interrupt triggered without any alarm in the active queue nor an + * overflow handler provided. + */ + fwk_unexpected(); + } return; }