diff --git a/README.md b/README.md index be8ca57..7a2202d 100755 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ This repository contains source files and instructions for building PYNQ to run on the [Ultra96 board](http://zedboard.org/product/ultra96). Users can leverage the included -Petalinux 2018.3 BSPs to build the images on their own. +Petalinux BSPs to build the images on their own. ## Quick Start @@ -19,8 +19,10 @@ Building PYNQ for Ultra96 can take many hours to complete. Plan accordingly! * Roughly 60GB of free hard drive space if you have the Xilinx tools installed * You may be able to get away with less free hard drive space, YMMV * At least 8GB of RAM (more is better) -* Xilinx PetaLinux 2018.3, read Xilinx UG1144 for PetaLinux setup requirements -* A free Xilinx developer account to obtain and license the tools: https://www.xilinx.com/registration/create-account.html +* Xilinx PetaLinux (find the version compatible to a specific PYNQ release at +[Xilinx Tool Version](https://pynq.readthedocs.io/en/latest/pynq_sd_card.html)); +read Xilinx UG1144 for PetaLinux setup requirements +* [Create a Xilinx account](https://www.xilinx.com/registration/create-account.html) to obtain and license the tools. Retrieve the Ultra96 PYNQ board git into a NEW directory somewhere outside the PYNQ git directory. @@ -28,11 +30,11 @@ Retrieve the Ultra96 PYNQ board git into a NEW directory somewhere outside the P git clone https://github.com/Avnet/Ultra96-PYNQ.git ``` -Setup Ultra96-PYNQ git to work on branch `image_v2.4_v2`. +Setup Ultra96-PYNQ git to work on a branch (for example,`image_v2.5`). ```shell cd -git checkout origin/image_v2.4_v2 +git checkout origin/image_v2.5 ``` ## Using Included BSPs @@ -52,23 +54,27 @@ cp -f sensors96b/sensors96b.hwh.vX sensors96b/sensors96b.hwh ``` Retrieve the main PYNQ repo into a NEW directory somewhere outside the Ultra96-PYNQ directory. + ```shell git clone https://github.com/Xilinx/PYNQ.git ``` -Setup PYNQ git to work on branch `image_v2.4`. +Setup PYNQ git to work on a branch (for example, `image_v2.5`). + ```shell cd -git checkout origin/image_v2.4 +git checkout origin/image_v2.5 ``` -Configure and install build tools, this will take some effort and will be an iterative process. Install on your own any missing tools. +Configure and install build tools, this will take some effort and will be an iterative process. Run `setup_host.sh` to install missing tools, `make checkenv` to check if all tools are installed. + ```shell cd sdbuild +./scripts/setup_host.sh make checkenv ``` -In your PYNQ repository go to the directory "sdbuild" and run make. +In your PYNQ repository go to the directory `sdbuild` and run make. **IMPORTANT: For the BOARDDIR path setting it should be absolute not relative, you have been warned!** @@ -77,7 +83,9 @@ make clean make BOARDDIR= ``` -Once the build has completed (it will take a long long time), if successful an SD card image will be available under the PYNQ git directory here: `./sdbuild/output/Ultra96_v2.4.img`. +Once the build has completed (it will take a long long time), if successful an SD card image will be available under the PYNQ git directory `sdbuild/output`. +Depending on the PYNQ release, the image may have different names; +as an example, for PYNQ v2.5, the image is `Ultra96-2.5.img`. Use Etcher or Win32DiskImager to write this image to an SD card. Insert card, PYNQ should boot up on the Ultra96! @@ -89,10 +97,25 @@ to the [online documentation](https://ultra96-pynq.readthedocs.io/en/latest/). Note this is optional; it is needed only if you have good reason not to use the included BSP. -Obtain and install Xilinx Vivado or SDx and PetaLinux v2018.3 on Ubuntu 16.04 LTS. If you are installing the Xilinx tools for the first time on your existing setup you must read Xilinx UG1144 for PetaLinux setup requirements. If you prefer, you can also setup all the tools on a VirtualBox VM (e.g. using [Vagrant software](https://pynq.readthedocs.io/en/latest/pynq_sd_card.html#prepare-the-building-environment)). -If you purchase an Ultra96 board, a free voucher for the full-version Xilinx SDX tool suite and PetaLinux 2018.3 is included. - -Use the Xilinx SDx or Vivado tools to generate the hardware design. The hardware design source files contain a PL (Xilinx Programmable Logic) design that will enable PYNQ to interact with a Grove mezzanine board. The hardware design also contains Ultra96 board specific settings. After building the hardware design, it will be manually imported into the PetaLinux BSP to be used for PYNQ. To build the hardware design that PetaLinux will boot up with: +Obtain and install Xilinx Vivado or SDx and PetaLinux on Ubuntu 16.04 +LTS. For Xilinx tools, you will need a version compatible to the PYNQ release +(for Xilinx tool compatibility, please find information at +[Xilinx Tool Version](https://pynq.readthedocs.io/en/latest/pynq_sd_card.html). +If you are installing the Xilinx tools for the first time on your +existing setup you must read Xilinx UG1144 for PetaLinux setup requirements. + +If you prefer, you can also setup all the tools on a VirtualBox VM +(e.g. using [Vagrant software](https://pynq.readthedocs.io/en/latest/pynq_sd_card.html#prepare-the-building-environment)). +If you purchase an Ultra96 board, a free voucher for the full-version Xilinx +SDX tool suite and PetaLinux is included. + +Use the Xilinx SDx or Vivado tools to generate the hardware design. +The hardware design source files contain a PL (Xilinx Programmable Logic) +design that will enable PYNQ to interact with a Grove mezzanine board. +The hardware design also contains Ultra96 board specific settings. +After building the hardware design, it will be manually imported into the +PetaLinux BSP to be used for PYNQ. To build the hardware design that +PetaLinux will boot up with: ```shell cd /Ultra96/sensors96b @@ -100,14 +123,18 @@ cp -f sensors96b.tcl.vX sensors96b.tcl make ``` -After the hardware design has finished building and you have installed PetaLinux 2018.3 then create the Ultra96 BSP by executing PetaLinux cmds FROM the TOP DIRECTORY of the Ultra96 PYNQ board git. You may see a couple warnings after the -config, those are normal: +After the hardware design has finished building and you have installed +PetaLinux then create the Ultra96 BSP by executing PetaLinux commands from the +ROOT DIRECTORY of the Ultra96 PYNQ board git. You may see a couple warnings +after the -config, those are normal: + ```shell cd mkdir bsp cd bsp petalinux-create -t project -n sensors96b --template zynqMP cd sensors96b -petalinux-config --get-hw-description=../../Ultra96/sensors96b/sensors96b/sensors96b.sdk +petalinux-config --get-hw-description=../../Ultra96/sensors96b ``` After the system config menus appear you need to set the following case-sensitive values, after completion exit and save: @@ -117,25 +144,21 @@ After the system config menus appear you need to set the following case-sensitiv * Image Packaging Configuration → Root filesystem type → (SD card) * Yocto Settings → YOCTO_MACHINE_NAME → (ultra96-zynqmp) -To work around a bug for Ultra96 that prevents including your own hardware design you must edit `/bsp/sensors96b/project-spec/meta-user/conf/petalinuxbsp.conf`. -Add the following line at the bottom of the file: +To work around a bug for Ultra96 that prevents including your own hardware +design you must edit `/bsp/sensors96b/project-spec/meta-user/conf/petalinuxbsp.conf`. +Add the following line at the bottom of the file: ``` MACHINE_FEATURES_remove_ultra96-zynqmp = "mipi" ``` -OPTIONAL: configure u-boot to decrease the boot delay. -```shell -petalinux-config -c u-boot -``` - -Optionally change "delay in seconds before automatically booting", default is 4 seconds then exit and save. - -For V2 you may want to remove the TI WiFi driver module. Search through device drivers, networking, wireless and deselect the Texas Instrument drivers: +For V2 you may want to remove the TI WiFi driver module. Search through +device drivers, networking, wireless and deselect the Texas Instrument drivers: ```shell petalinux-config -c kernel ``` -Finish creating the BSP by packaging it up into a single BSP file and placing it for PYNQ to find. 'X' should be set to '1' or '2' for U96 v1 or v2: +Finish creating the BSP by packaging it up into a single BSP file and placing +it for PYNQ to find. 'X' should be set to '1' or '2' for U96 v1 or v2: ```shell cd /bsp @@ -143,10 +166,4 @@ rm ../Ultra96/sensors96b_vX.bsp petalinux-package --bsp -p sensors96b --hwsource ../Ultra96/sensors96b/sensors96b --output ../Ultra96/sensors96b_vX.bsp ``` -Note: The Microchip wilc driver used for U96 V2 has been pre-built and resides in the pre-stage PYNQ package area (wilc3000). To rebuild the `wilc-sdio.ko` driver you will need to wait for a PYNQ build to finish, then go back under the `/sdbuild/build/Ultra96/petalinux_bsp/sensors96b` the base directory of the PYNQ built BSP and manually run: - -```shell -petalinux-build -c rootfs -``` - -This will build the device driver with the correct Linux kernel `#defines`. After the rootfs has finished building you will need to locate the file `wilc-sdio.ko` and manually copy it over to the U96 PYNQ rootfs and update the git file version of it under the `/Ultra96/packages/wilc3000` folder and then rebuild the SD image after which will contain and startup the Microchip wifi driver. +Note: The PYNQ packages scripts and extra files will pull in v2 critical changes such as the wifi driver. \ No newline at end of file diff --git a/Ultra96/packages/wilc3000/pre.sh b/Ultra96/packages/wilc3000/pre.sh index 76bdff4..8b195d4 100755 --- a/Ultra96/packages/wilc3000/pre.sh +++ b/Ultra96/packages/wilc3000/pre.sh @@ -7,5 +7,7 @@ sudo cp $script_dir/wpa_ap.service $target/lib/systemd/system sudo cp -r $script_dir/wpa_ap $target/usr/local/share/ sudo mkdir $target/wilc_bld sudo mkdir -p $target/lib/firmware/mchp -sudo mkdir -p $target/lib/modules/4.14.0-xilinx-v2018.3/extra -sudo cp $script_dir/wilc-sdio.ko $target/lib/modules/4.14.0-xilinx-v2018.3/extra/ +cd $BUILD_ROOT/${PYNQ_BOARD}/petalinux_project +petalinux-build -c wilc +sudo mkdir -p $target/lib/modules/4.19.0-xilinx-v2019.1/extra +sudo cp -rf build/tmp/sysroots-components/*/wilc/lib/modules/4.19.0-xilinx-v2019.1/extra/wilc-sdio.ko $target/lib/modules/4.19.0-xilinx-v2019.1/extra/ diff --git a/Ultra96/packages/wilc3000/wilc-sdio.ko b/Ultra96/packages/wilc3000/wilc-sdio.ko deleted file mode 100755 index c19b403..0000000 Binary files a/Ultra96/packages/wilc3000/wilc-sdio.ko and /dev/null differ diff --git a/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/pmu-firmware/pmu-firmware_%.bbappend b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/pmu-firmware/pmu-firmware_%.bbappend new file mode 100755 index 0000000..322306e --- /dev/null +++ b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/pmu-firmware/pmu-firmware_%.bbappend @@ -0,0 +1,7 @@ +#Add debug for PMUFW +#XSCTH_BUILD_DEBUG = "1" + +ULTRA96_VERSION = "1" +YAML_COMPILER_FLAGS_append_ultra96-zynqmp = "-DENABLE_MOD_ULTRA96 -DENABLE_SCHEDULER" +YAML_COMPILER_FLAGS_append_ultra96-zynqmp = "${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2', ' -DULTRA96_VERSION=1', d)}" + diff --git a/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/files/bsp.cfg b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/files/bsp.cfg new file mode 100644 index 0000000..37ec1bd --- /dev/null +++ b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/files/bsp.cfg @@ -0,0 +1,9 @@ +CONFIG_NET=y +CONFIG_NET_TFTP_VARS=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_BOOTDELAY=2 diff --git a/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/files/platform-top.h b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/files/platform-top.h new file mode 100644 index 0000000..c21eefe --- /dev/null +++ b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/files/platform-top.h @@ -0,0 +1,24 @@ +#include +#define CONFIG_SYS_BOOTM_LEN 0xF000000 + +#define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "setenv dfu_alt_info " \ + "image.ub ram $netstart 0x1e00000\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +#define DFU_ALT_INFO_MMC \ + "dfu_mmc_info=" \ + "set dfu_alt_info " \ + "${kernel_image} fat 0 1\\\\;" \ + "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ + "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" + +/*Required for uartless designs */ +#ifndef CONFIG_BAUDRATE +#define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DEBUG_UART +#undef CONFIG_DEBUG_UART +#endif +#endif diff --git a/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend new file mode 100644 index 0000000..9d4e4dd --- /dev/null +++ b/Ultra96/petalinux_bsp_v1/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend @@ -0,0 +1,4 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +SRC_URI += "file://platform-top.h" +SRC_URI += "file://bsp.cfg" diff --git a/Ultra96/petalinux_bsp_v1/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg b/Ultra96/petalinux_bsp_v1/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg index 794b18b..f4f5ff6 100644 --- a/Ultra96/petalinux_bsp_v1/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg +++ b/Ultra96/petalinux_bsp_v1/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg @@ -55,3 +55,8 @@ CONFIG_USB_UAS=y # CONFIG_SPI_SPIDEV=y +# +# Networking configurations +# +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m diff --git a/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/device-tree/files/system-user.dtsi index ccfc776..05af5ce 100644 --- a/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/device-tree/files/system-user.dtsi +++ b/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -1,12 +1,11 @@ /include/ "system-conf.dtsi" / { - // This is already in U96 V1 DT except for on delay, so we'll merge it in - sdio_pwrseq: sdio_pwrseq { - compatible = "mmc-pwrseq-simple"; - /*post-power-on-delay-ms = <10>;*/ - reset-gpios = <&gpio 7 1>; /* MIO[7] RESETN for WILC3000 active low */ - /* reset-gpios = <&gpio 78 1>; // device pin A3 for RESETN, Active low, JT5 strapped to pins 1-2 */ - chip_en-gpios = <&gpio 8 1>; // This REQUIRES a patched pwrseq_simple.c to have it use this pin properly for the WILC3000 wifi part + sdio_pwrseq: sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + // MIO[7] RESETN for WILC3000 active low + reset-gpios = <&gpio 7 1>; + // requires a patched pwrseq_simple.c for WILC3000 + chip_en-gpios = <&gpio 8 1>; }; // Remove V1 Power ON/OFF controller from U96 V1 DT @@ -22,32 +21,13 @@ /delete-property/gpio-line-names; }; -// This is what is in sdhci1 DT from V1, it will merge with below: -// -// bus-width = <0x4>; -// non-removable; -// disable-wp; -// cap-power-off-card; -// mmc-pwrseq = <&sdio_pwrseq>; -// vqmmc-supply = <&wmmcsdio_fixed>; -// #address-cells = <1>; -// #size-cells = <0>; -// wlcore: wifi@2 { -// compatible = "ti,wl1831"; -// reg = <2>; -// interrupt-parent = <&gpio>; -// interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ -// }; -// &sdhci1 { max-frequency = <50000000>; - /delete-property/cap-power-off-card; // This is not compatible with the WILC3000 and means the WILC will always be powered on + // cap-power-off-card not compatible with WILC3000 + /delete-property/cap-power-off-card; wilc_sdio@1 { - compatible = "microchip,wilc3000", "microchip,wilc3000"; + compatible = "microchip,wilc3000"; reg = <0>; - // interrupt-parent = <&gpio>; // WILC driver does NOT use gpio IRQ - // interrupts = <76 2>; /* MIO76 WILC IRQ 1V8 */ // WILC driver does NOT use gpio IRQ - // irq-gpios = <&gpio 76 0>; // WILC driver does NOT use gpio IRQ bus-width = <0x4>; status = "okay"; }; @@ -77,10 +57,3 @@ }; }; -///////////////////////////////////////////////////////////////////////////////// -// -// NOTE: This content is redundant (a duplicate of what is in the PetaLinux bsp) -// because the PYNQ build process over-writes the system-user.dtsi that -// is in the meta-user layer of a PetaLinux bsp -// -///////////////////////////////////////////////////////////////////////////////// diff --git a/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/pmu-firmware/pmu-firmware_%.bbappend b/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/pmu-firmware/pmu-firmware_%.bbappend new file mode 100644 index 0000000..854eed1 --- /dev/null +++ b/Ultra96/petalinux_bsp_v2/meta-user/recipes-bsp/pmu-firmware/pmu-firmware_%.bbappend @@ -0,0 +1,7 @@ +#Add debug for PMUFW +#XSCTH_BUILD_DEBUG = "1" + +ULTRA96_VERSION = "2" +YAML_COMPILER_FLAGS_append_ultra96-zynqmp = "-DENABLE_MOD_ULTRA96 -DENABLE_SCHEDULER" +YAML_COMPILER_FLAGS_append_ultra96-zynqmp = "${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2', ' -DULTRA96_VERSION=1', d)}" + diff --git a/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg b/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg index 794b18b..66422b2 100644 --- a/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg +++ b/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg @@ -1,3 +1,4 @@ + # # Enable usb gadget # @@ -55,3 +56,8 @@ CONFIG_USB_UAS=y # CONFIG_SPI_SPIDEV=y +# +# Networking configurations +# +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m diff --git a/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/fix_u96v2_pwrseq_simple.patch b/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/fix_u96v2_pwrseq_simple.patch index e999ce4..f952b02 100644 --- a/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/fix_u96v2_pwrseq_simple.patch +++ b/Ultra96/petalinux_bsp_v2/meta-user/recipes-kernel/linux/linux-xlnx/fix_u96v2_pwrseq_simple.patch @@ -1,47 +1,47 @@ -From 0e457444d0e102d4fd95d23ee430c441e25f3126 Mon Sep 17 00:00:00 2001 +From cd88af06be5bad2bf19f4ca7ff5f19f4295ebbca Mon Sep 17 00:00:00 2001 From: Fred Kellerman -Date: Sat, 18 May 2019 23:21:35 -0400 -Subject: [PATCH] fix up pwrseq_simple for U96 v2 +Date: Tue, 24 Sep 2019 19:49:30 -0400 +Subject: [PATCH] Patch the kernel to manipulate the wifi part's pins --- drivers/mmc/core/pwrseq_simple.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c -index 13ef162..59bb337 100644 +index a8b9fee..3cfdc66 100644 --- a/drivers/mmc/core/pwrseq_simple.c +++ b/drivers/mmc/core/pwrseq_simple.c -@@ -105,6 +105,33 @@ static int mmc_pwrseq_simple_probe(struct platform_device *pdev) +@@ -109,6 +109,33 @@ static int mmc_pwrseq_simple_probe(struct platform_device *pdev) { struct mmc_pwrseq_simple *pwrseq; struct device *dev = &pdev->dev; -+ struct gpio_desc *gpio_chip_en; -+ struct gpio_desc *gpio_resetn; ++ struct gpio_desc *gpio_chip_en; ++ struct gpio_desc *gpio_resetn; + -+ // Leave resetn low and let pwrseq take care of it -+ gpio_resetn = gpiod_get(dev, "reset", GPIOD_ASIS); -+ if (IS_ERR(gpio_resetn)) { -+ dev_warn(dev, ++ // Leave resetn low and let pwrseq take care of it ++ gpio_resetn = gpiod_get(dev, "reset", GPIOD_ASIS); ++ if (IS_ERR(gpio_resetn)) { ++ dev_warn(dev, + "mmc failed to get default resetn GPIO\n"); -+ } else { -+ dev_info(dev, "mmc succesfully got gpio_resetn\n"); -+ gpiod_direction_output(gpio_resetn, 1); // low -+ gpiod_put(gpio_resetn); -+ } ++ } else { ++ dev_info(dev, "mmc succesfully got gpio_resetn\n"); ++ gpiod_direction_output(gpio_resetn, 1); // low ++ gpiod_put(gpio_resetn); ++ } + -+ // Turn power off then back on -+ gpio_chip_en = gpiod_get(dev, "chip_en", GPIOD_ASIS); -+ if (IS_ERR(gpio_chip_en)) { -+ dev_warn(dev, ++ // Turn power off then back on ++ gpio_chip_en = gpiod_get(dev, "chip_en", GPIOD_ASIS); ++ if (IS_ERR(gpio_chip_en)) { ++ dev_warn(dev, + "mmc failed to get default chip_en GPIO\n"); -+ } else { -+ dev_info(dev, "mmc succesfully got gpio_chip_en\n"); -+ gpiod_direction_output(gpio_chip_en, 1); // low (chip off) -+ mdelay(5); -+ gpiod_set_value(gpio_chip_en, 0); // high (chip on) -+ gpiod_put(gpio_chip_en); -+ mdelay(5); -+ } ++ } else { ++ dev_info(dev, "mmc succesfully got gpio_chip_en\n"); ++ gpiod_direction_output(gpio_chip_en, 1); // low (chip off) ++ mdelay(5); ++ gpiod_set_value(gpio_chip_en, 0); // high (chip on) ++ gpiod_put(gpio_chip_en); ++ mdelay(5); ++ } pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL); if (!pwrseq) diff --git a/Ultra96/petalinux_bsp_v2/meta-user/recipes-modules/wilc/wilc_15.2.bb b/Ultra96/petalinux_bsp_v2/meta-user/recipes-modules/wilc/wilc_15.2.bb index d784e0c..5fae9b2 100644 --- a/Ultra96/petalinux_bsp_v2/meta-user/recipes-modules/wilc/wilc_15.2.bb +++ b/Ultra96/petalinux_bsp_v2/meta-user/recipes-modules/wilc/wilc_15.2.bb @@ -5,9 +5,9 @@ LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-3.0;md5=c79ff39f19dfec6d293 inherit module -SRC_URI = "git://github.com/Avnet/u96v2-wilc-driver;protocol=http;branch=master" +SRC_URI = "git://github.com/Avnet/u96v2-wilc-driver;protocol=http;branch=v15_2" -SRCREV = "master" +SRCREV = "01ab7484e0e6b2191c69d7ec7c6e89da5ca51f0f" DEPENDS += "virtual/kernel" @@ -20,4 +20,3 @@ EXTRA_OEMAKE = 'CONFIG_WILC=y \ CONFIG_WILC1000_HW_OOB_INTR=n \ KERNEL_SRC="${STAGING_KERNEL_DIR}" \ O=${STAGING_KERNEL_BUILDDIR}' - diff --git a/Ultra96/sensors96b/build_bitstream.tcl b/Ultra96/sensors96b/build_bitstream.tcl new file mode 100644 index 0000000..8c62ee5 --- /dev/null +++ b/Ultra96/sensors96b/build_bitstream.tcl @@ -0,0 +1,29 @@ +set overlay_name "sensors96b" +set design_name "sensors96b" + +# open block design +open_project ./${overlay_name}/${overlay_name}.xpr +open_bd_design ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd + +# Add top wrapper and xdc files +make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top +add_files -norecurse ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v +set_property top ${design_name}_wrapper [current_fileset] +import_files -fileset constrs_1 -norecurse ./vivado/constraints/${overlay_name}.xdc +update_compile_order -fileset sources_1 + +# call implement +launch_runs impl_1 -to_step write_bitstream -jobs 4 +wait_on_run impl_1 + +# This hardware definition file will be used for microblaze projects +file mkdir ./${overlay_name}/${overlay_name}.sdk +write_hwdef -force -file ./${overlay_name}/${overlay_name}.sdk/${overlay_name}.hdf +file copy -force ./${overlay_name}/${overlay_name}.sdk/${overlay_name}.hdf . + +# move and rename bitstream to final location +file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ${overlay_name}.bit + +# copy hwh files +file copy -force ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/hw_handoff/${design_name}.hwh ${overlay_name}.hwh + diff --git a/Ultra96/sensors96b/build_sensors96b_dsa.tcl b/Ultra96/sensors96b/build_sensors96b_dsa.tcl index 0b780f5..e980982 100755 --- a/Ultra96/sensors96b/build_sensors96b_dsa.tcl +++ b/Ultra96/sensors96b/build_sensors96b_dsa.tcl @@ -21,7 +21,7 @@ set_property PFM.AXI_PORT { \ S_AXI_LPD {memport "S_AXI_HP"} \ } [get_bd_cells /zynq_ultra_ps_e_0] set intVar [] -for {set i 1} {$i < 8} {incr i} { +for {set i 2} {$i < 8} {incr i} { lappend intVar In$i {} } set_property PFM.IRQ $intVar [get_bd_cells /xlconcat_0] diff --git a/Ultra96/sensors96b/makefile b/Ultra96/sensors96b/makefile index 4e544d9..7d2cd91 100755 --- a/Ultra96/sensors96b/makefile +++ b/Ultra96/sensors96b/makefile @@ -1,23 +1,23 @@ overlay_name := sensors96b design_name := sensors96b -all: bitstream check_timing dsa +all: block_design bitstream check_timing dsa @echo @tput setaf 2 ; echo "Built $(overlay_name) successfully!"; tput sgr0; @echo -bitstream: +block_design: vivado -mode batch -source $(overlay_name).tcl -notrace +bitstream: + vivado -mode batch -source build_bitstream.tcl -notrace + check_timing: vivado -mode batch -source check_$(overlay_name).tcl -notrace dsa: vivado -mode batch -source build_$(overlay_name)_dsa.tcl -notrace - unzip -qo $(overlay_name).dsa -d .dsa - cp -rf .dsa/$(design_name).hwh ./$(overlay_name).hwh clean: - rm -rf $(overlay_name) *.jou *.log - rm -rf .dsa - rm -rf $(overlay_name).hdf $(overlay_name).dsa + rm -rf $(overlay_name) *.jou *.log NA + diff --git a/Ultra96/sensors96b/sensors96b.bit.v1 b/Ultra96/sensors96b/sensors96b.bit.v1 index 40ac8c3..fe06fdf 100644 Binary files a/Ultra96/sensors96b/sensors96b.bit.v1 and b/Ultra96/sensors96b/sensors96b.bit.v1 differ diff --git a/Ultra96/sensors96b/sensors96b.bit.v2 b/Ultra96/sensors96b/sensors96b.bit.v2 index f3396c7..578b907 100644 Binary files a/Ultra96/sensors96b/sensors96b.bit.v2 and b/Ultra96/sensors96b/sensors96b.bit.v2 differ diff --git a/Ultra96/sensors96b/sensors96b.hwh.v1 b/Ultra96/sensors96b/sensors96b.hwh.v1 index cd452d3..678ec4a 100644 --- a/Ultra96/sensors96b/sensors96b.hwh.v1 +++ b/Ultra96/sensors96b/sensors96b.hwh.v1 @@ -1,5 +1,5 @@  - + @@ -34,29 +34,29 @@ - + - + - + - + - + - + - + - + - + - + @@ -69,16 +69,777 @@ - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -629,15 +1390,15 @@ - + - - + + @@ -650,103 +1411,99 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + @@ -754,26 +1511,22 @@ - - - - - + - + - + - + - + - + @@ -795,13 +1548,13 @@ - - + + - - + + @@ -889,20 +1642,22 @@ + + - + - + @@ -1249,6 +2004,108 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1284,6 +2141,7 @@ + @@ -1324,6 +2182,11 @@ + + + + + @@ -1339,6 +2202,11 @@ + + + + + @@ -1374,6 +2242,7 @@ + @@ -1389,6 +2258,11 @@ + + + + + @@ -1414,133 +2288,98 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + + @@ -1548,6 +2387,7 @@ + @@ -1556,9 +2396,11 @@ + + @@ -1566,62 +2408,67 @@ + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - + @@ -1656,8 +2503,8 @@ - - + + @@ -1667,7 +2514,12 @@ - + + + + + + @@ -1675,9 +2527,9 @@ - + - + @@ -1713,7 +2565,7 @@ - + @@ -1925,15 +2777,15 @@ - + - - + + - + @@ -1943,8 +2795,8 @@ - - + + @@ -2099,6 +2951,7 @@ + @@ -2200,6 +3053,15 @@ + + + + + + + + + @@ -2222,7 +3084,7 @@ - + @@ -2324,393 +3186,471 @@ - - - + + + + - - - + + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + @@ -2783,6 +3723,7 @@ + @@ -3209,7 +4150,7 @@ - + @@ -3255,6 +4196,14 @@ + + + + + + + + @@ -3522,17 +4471,7 @@ - - - - - - - - - - - + @@ -3545,9 +4484,11 @@ + + @@ -3648,18 +4589,14 @@ - - - - - - + + diff --git a/Ultra96/sensors96b/sensors96b.hwh.v2 b/Ultra96/sensors96b/sensors96b.hwh.v2 index f35bdc9..6fac74f 100644 --- a/Ultra96/sensors96b/sensors96b.hwh.v2 +++ b/Ultra96/sensors96b/sensors96b.hwh.v2 @@ -1,5 +1,5 @@  - + @@ -34,29 +34,29 @@ - + - + - + - + - + - + - + - + - + - + @@ -69,16 +69,777 @@ - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -629,15 +1390,15 @@ - + - - + + @@ -650,103 +1411,99 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + @@ -754,26 +1511,22 @@ - - - - - + - + - + - + - + - + @@ -795,13 +1548,13 @@ - - + + - - + + @@ -889,20 +1642,22 @@ + + - + - + @@ -1249,6 +2004,21 @@ + + + + + + + + + + + + + + + @@ -1284,6 +2054,7 @@ + @@ -1324,6 +2095,11 @@ + + + + + @@ -1339,6 +2115,11 @@ + + + + + @@ -1374,6 +2155,7 @@ + @@ -1389,6 +2171,11 @@ + + + + + @@ -1419,20 +2206,13 @@ - - - - - - - - + - + @@ -1447,13 +2227,12 @@ - - + - + @@ -1463,12 +2242,12 @@ - + - + @@ -1478,20 +2257,13 @@ - - - - - - - - + - + @@ -1506,41 +2278,108 @@ - - + - + - + - + - + + - + - + - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1548,6 +2387,7 @@ + @@ -1556,9 +2396,11 @@ + + @@ -1566,62 +2408,67 @@ + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - + @@ -1656,8 +2503,8 @@ - - + + @@ -1667,7 +2514,12 @@ - + + + + + + @@ -1675,9 +2527,9 @@ - + - + @@ -1713,7 +2565,7 @@ - + @@ -1925,15 +2777,15 @@ - + - - + + - + @@ -1943,8 +2795,8 @@ - - + + @@ -2099,6 +2951,7 @@ + @@ -2200,6 +3053,15 @@ + + + + + + + + + @@ -2222,7 +3084,7 @@ - + @@ -2324,393 +3186,471 @@ - - - + + + + - - - + + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + - - + + + @@ -2783,6 +3723,7 @@ + @@ -3209,7 +4150,7 @@ - + @@ -3255,6 +4196,14 @@ + + + + + + + + @@ -3522,17 +4471,7 @@ - - - - - - - - - - - + @@ -3545,9 +4484,11 @@ + + @@ -3648,18 +4589,14 @@ - - - - - - + + diff --git a/Ultra96/sensors96b/sensors96b.tcl.v1 b/Ultra96/sensors96b/sensors96b.tcl.v1 index be28ea6..bfb9f30 100755 --- a/Ultra96/sensors96b/sensors96b.tcl.v1 +++ b/Ultra96/sensors96b/sensors96b.tcl.v1 @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2018.3 +set scripts_vivado_version 2019.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } { xilinx.com:ip:axi_uart16550:2.0\ xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.2\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ " set list_ips_missing "" @@ -191,7 +191,7 @@ proc create_root_design { parentCell } { # Create interface ports set GPIO_SENSORS [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_SENSORS ] - set UART1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART1 ] + # Create ports set BT_ctsn [ create_bd_port -dir I BT_ctsn ] @@ -200,6 +200,8 @@ proc create_root_design { parentCell } { set UART0_rtsn [ create_bd_port -dir O -type data UART0_rtsn ] set UART0_rxd [ create_bd_port -dir I UART0_rxd ] set UART0_txd [ create_bd_port -dir O UART0_txd ] + set UART1_rxd [ create_bd_port -dir I UART1_rxd ] + set UART1_txd [ create_bd_port -dir O UART1_txd ] # Create instance: axi_uart16550_0, and set properties set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] @@ -207,23 +209,29 @@ proc create_root_design { parentCell } { CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \ ] $axi_uart16550_0 + # Create instance: axi_uart16550_1, and set properties + set axi_uart16550_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_1 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \ + ] $axi_uart16550_1 + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] # Create instance: ps8_0_axi_periph, and set properties set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] set_property -dict [ list \ - CONFIG.NUM_MI {1} \ + CONFIG.NUM_MI {2} \ ] $ps8_0_axi_periph # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ - CONFIG.NUM_PORTS {1} \ + CONFIG.NUM_PORTS {2} \ ] $xlconcat_0 # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 zynq_ultra_ps_e_0 ] + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] set_property -dict [ list \ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ @@ -232,129 +240,209 @@ proc create_root_design { parentCell } { CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_MIO_0_DIRECTION {inout} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ CONFIG.PSU_MIO_12_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ CONFIG.PSU_MIO_13_DIRECTION {inout} \ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ CONFIG.PSU_MIO_14_DIRECTION {inout} \ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ CONFIG.PSU_MIO_15_DIRECTION {inout} \ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ CONFIG.PSU_MIO_16_DIRECTION {inout} \ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ CONFIG.PSU_MIO_18_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_1_DIRECTION {in} \ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_1_SLEW {slow} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ CONFIG.PSU_MIO_21_DIRECTION {inout} \ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ CONFIG.PSU_MIO_22_DIRECTION {out} \ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ CONFIG.PSU_MIO_24_DIRECTION {in} \ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_SLEW {slow} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ CONFIG.PSU_MIO_26_DIRECTION {in} \ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_26_SLEW {slow} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ CONFIG.PSU_MIO_28_DIRECTION {in} \ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_SLEW {slow} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ CONFIG.PSU_MIO_2_DIRECTION {in} \ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ CONFIG.PSU_MIO_30_DIRECTION {in} \ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_SLEW {slow} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ CONFIG.PSU_MIO_35_DIRECTION {inout} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ CONFIG.PSU_MIO_36_DIRECTION {inout} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ CONFIG.PSU_MIO_37_DIRECTION {inout} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ CONFIG.PSU_MIO_3_DIRECTION {out} \ - CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ CONFIG.PSU_MIO_45_DIRECTION {inout} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ CONFIG.PSU_MIO_52_DIRECTION {in} \ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_SLEW {slow} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ CONFIG.PSU_MIO_53_DIRECTION {in} \ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_SLEW {slow} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ CONFIG.PSU_MIO_55_DIRECTION {in} \ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_SLEW {slow} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ CONFIG.PSU_MIO_5_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ CONFIG.PSU_MIO_64_DIRECTION {in} \ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_SLEW {slow} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ CONFIG.PSU_MIO_65_DIRECTION {in} \ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_SLEW {slow} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ CONFIG.PSU_MIO_66_DIRECTION {inout} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ CONFIG.PSU_MIO_67_DIRECTION {in} \ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_SLEW {slow} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ CONFIG.PSU_MIO_68_DIRECTION {inout} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ CONFIG.PSU_MIO_69_DIRECTION {inout} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ CONFIG.PSU_MIO_71_DIRECTION {inout} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ CONFIG.PSU_MIO_72_DIRECTION {inout} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ CONFIG.PSU_MIO_73_DIRECTION {inout} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ CONFIG.PSU_MIO_74_DIRECTION {inout} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ CONFIG.PSU_MIO_75_DIRECTION {inout} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ CONFIG.PSU_MIO_76_DIRECTION {inout} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ CONFIG.PSU_MIO_7_DIRECTION {inout} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ + CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.332825} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.998901} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ @@ -627,6 +715,14 @@ proc create_root_design { parentCell } { CONFIG.PSU__DDRC__VREF {0} \ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ CONFIG.PSU__DDR_QOS_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \ CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \ CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \ CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \ @@ -723,13 +819,15 @@ proc create_root_design { parentCell } { CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.3333} \ CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ @@ -740,6 +838,7 @@ proc create_root_design { parentCell } { CONFIG.PSU__SD0__RESET__ENABLE {0} \ CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \ CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ @@ -773,7 +872,7 @@ proc create_root_design { parentCell } { CONFIG.PSU__UART1__BAUD_RATE {115200} \ CONFIG.PSU__UART1__MODEM__ENABLE {0} \ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \ CONFIG.PSU__USB0_COHERENCY {0} \ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ @@ -803,33 +902,37 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_uart16550_1/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_GPIO_0 [get_bd_intf_ports GPIO_SENSORS] [get_bd_intf_pins zynq_ultra_ps_e_0/GPIO_0] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_UART_1 [get_bd_intf_ports UART1] [get_bd_intf_pins zynq_ultra_ps_e_0/UART_1] # Create port connections connect_bd_net -net UART0_ctsn [get_bd_ports UART0_ctsn] [get_bd_pins axi_uart16550_0/ctsn] + connect_bd_net -net UART1_rxd_1 [get_bd_ports UART1_rxd] [get_bd_pins axi_uart16550_1/sin] connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In0] connect_bd_net -net axi_uart16550_0_rtsn [get_bd_ports UART0_rtsn] [get_bd_pins axi_uart16550_0/rtsn] connect_bd_net -net axi_uart16550_0_sout [get_bd_ports UART0_txd] [get_bd_pins axi_uart16550_0/sout] + connect_bd_net -net axi_uart16550_1_ip2intc_irpt [get_bd_pins axi_uart16550_1/ip2intc_irpt] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net axi_uart16550_1_sout [get_bd_ports UART1_txd] [get_bd_pins axi_uart16550_1/sout] connect_bd_net -net emio_uart0_ctsn_1 [get_bd_ports BT_ctsn] [get_bd_pins zynq_ultra_ps_e_0/emio_uart0_ctsn] connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins axi_uart16550_1/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] connect_bd_net -net sin_1 [get_bd_ports UART0_rxd] [get_bd_pins axi_uart16550_0/sin] connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] connect_bd_net -net zynq_ultra_ps_e_0_emio_uart0_rtsn [get_bd_ports BT_rtsn] [get_bd_pins zynq_ultra_ps_e_0/emio_uart0_rtsn] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins axi_uart16550_1/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] # Create address segments create_bd_addr_seg -range 0x00010000 -offset 0x80060000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] SEG_axi_uart16550_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x80070000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_uart16550_1/S_AXI/Reg] SEG_axi_uart16550_1_Reg # Restore current instance current_bd_instance $oldCurInst # Create PFM attributes - set_property PFM_NAME {xilinx.com:xd:sensors96b:2.0} [get_files [current_bd_design].bd] + set_property PFM_NAME {xilinx.com:xd:${design_name}:2.0} [get_files [current_bd_design].bd] validate_bd_design @@ -843,25 +946,3 @@ proc create_root_design { parentCell } { ################################################################## create_root_design "" - -# Add top wrapper and xdc files -make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top -add_files -norecurse ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v -set_property top ${design_name}_wrapper [current_fileset] -import_files -fileset constrs_1 -norecurse ./vivado/constraints/${overlay_name}.xdc -update_compile_order -fileset sources_1 - -# call implement -launch_runs impl_1 -to_step write_bitstream -jobs 4 -wait_on_run impl_1 - -# Create overlay hardware definition file and bitstream -write_hwdef -force -file ./${overlay_name}.hdf -file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./${overlay_name}.bit - -# Create files for optional PetaLinux integration -file mkdir ./${overlay_name}/${overlay_name}.sdk -file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.sysdef ./${overlay_name}/${overlay_name}.sdk/${design_name}_wrapper.hdf -file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./${overlay_name}/${overlay_name}.sdk/${design_name}_wrapper.bit - - diff --git a/Ultra96/sensors96b/sensors96b.tcl.v2 b/Ultra96/sensors96b/sensors96b.tcl.v2 index 51a5f73..96b24df 100755 --- a/Ultra96/sensors96b/sensors96b.tcl.v2 +++ b/Ultra96/sensors96b/sensors96b.tcl.v2 @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2018.3 +set scripts_vivado_version 2019.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } { xilinx.com:ip:axi_uart16550:2.0\ xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.2\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ " set list_ips_missing "" @@ -191,7 +191,7 @@ proc create_root_design { parentCell } { # Create interface ports set GPIO_SENSORS [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_SENSORS ] - set UART1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART1 ] + # Create ports set BT_ctsn [ create_bd_port -dir I BT_ctsn ] @@ -200,6 +200,8 @@ proc create_root_design { parentCell } { set UART0_rtsn [ create_bd_port -dir O -type data UART0_rtsn ] set UART0_rxd [ create_bd_port -dir I UART0_rxd ] set UART0_txd [ create_bd_port -dir O UART0_txd ] + set UART1_rxd [ create_bd_port -dir I UART1_rxd ] + set UART1_txd [ create_bd_port -dir O UART1_txd ] # Create instance: axi_uart16550_0, and set properties set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] @@ -207,23 +209,29 @@ proc create_root_design { parentCell } { CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \ ] $axi_uart16550_0 + # Create instance: axi_uart16550_1, and set properties + set axi_uart16550_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_1 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \ + ] $axi_uart16550_1 + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] # Create instance: ps8_0_axi_periph, and set properties set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] set_property -dict [ list \ - CONFIG.NUM_MI {1} \ + CONFIG.NUM_MI {2} \ ] $ps8_0_axi_periph # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ - CONFIG.NUM_PORTS {1} \ + CONFIG.NUM_PORTS {2} \ ] $xlconcat_0 # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 zynq_ultra_ps_e_0 ] + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] set_property -dict [ list \ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ @@ -232,129 +240,209 @@ proc create_root_design { parentCell } { CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_MIO_0_DIRECTION {inout} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ CONFIG.PSU_MIO_12_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ CONFIG.PSU_MIO_13_DIRECTION {inout} \ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ CONFIG.PSU_MIO_14_DIRECTION {inout} \ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ CONFIG.PSU_MIO_15_DIRECTION {inout} \ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ CONFIG.PSU_MIO_16_DIRECTION {inout} \ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ CONFIG.PSU_MIO_18_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_1_DIRECTION {in} \ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_1_SLEW {slow} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ CONFIG.PSU_MIO_21_DIRECTION {inout} \ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ CONFIG.PSU_MIO_22_DIRECTION {out} \ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ CONFIG.PSU_MIO_24_DIRECTION {in} \ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_SLEW {slow} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ CONFIG.PSU_MIO_26_DIRECTION {in} \ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_26_SLEW {slow} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ CONFIG.PSU_MIO_28_DIRECTION {in} \ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_SLEW {slow} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ CONFIG.PSU_MIO_2_DIRECTION {in} \ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ CONFIG.PSU_MIO_30_DIRECTION {in} \ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_SLEW {slow} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ CONFIG.PSU_MIO_35_DIRECTION {inout} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ CONFIG.PSU_MIO_36_DIRECTION {inout} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ CONFIG.PSU_MIO_37_DIRECTION {inout} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ CONFIG.PSU_MIO_3_DIRECTION {out} \ - CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ CONFIG.PSU_MIO_45_DIRECTION {inout} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ CONFIG.PSU_MIO_52_DIRECTION {in} \ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_SLEW {slow} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ CONFIG.PSU_MIO_53_DIRECTION {in} \ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_SLEW {slow} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ CONFIG.PSU_MIO_55_DIRECTION {in} \ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_SLEW {slow} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ CONFIG.PSU_MIO_5_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ CONFIG.PSU_MIO_64_DIRECTION {in} \ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_SLEW {slow} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ CONFIG.PSU_MIO_65_DIRECTION {in} \ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_SLEW {slow} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ CONFIG.PSU_MIO_66_DIRECTION {inout} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ CONFIG.PSU_MIO_67_DIRECTION {in} \ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_SLEW {slow} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ CONFIG.PSU_MIO_68_DIRECTION {inout} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ CONFIG.PSU_MIO_69_DIRECTION {inout} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ CONFIG.PSU_MIO_71_DIRECTION {inout} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ CONFIG.PSU_MIO_72_DIRECTION {inout} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ CONFIG.PSU_MIO_73_DIRECTION {inout} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ CONFIG.PSU_MIO_74_DIRECTION {inout} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ CONFIG.PSU_MIO_75_DIRECTION {inout} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ CONFIG.PSU_MIO_76_DIRECTION {inout} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ CONFIG.PSU_MIO_7_DIRECTION {inout} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ + CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.332825} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.998901} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ @@ -627,6 +715,14 @@ proc create_root_design { parentCell } { CONFIG.PSU__DDRC__VREF {0} \ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ CONFIG.PSU__DDR_QOS_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \ CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \ CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \ CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \ @@ -723,13 +819,15 @@ proc create_root_design { parentCell } { CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.3333} \ CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ @@ -740,6 +838,7 @@ proc create_root_design { parentCell } { CONFIG.PSU__SD0__RESET__ENABLE {0} \ CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \ CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ @@ -773,7 +872,7 @@ proc create_root_design { parentCell } { CONFIG.PSU__UART1__BAUD_RATE {115200} \ CONFIG.PSU__UART1__MODEM__ENABLE {0} \ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \ CONFIG.PSU__USB0_COHERENCY {0} \ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ @@ -803,33 +902,37 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_uart16550_1/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_GPIO_0 [get_bd_intf_ports GPIO_SENSORS] [get_bd_intf_pins zynq_ultra_ps_e_0/GPIO_0] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_UART_1 [get_bd_intf_ports UART1] [get_bd_intf_pins zynq_ultra_ps_e_0/UART_1] # Create port connections connect_bd_net -net UART0_ctsn [get_bd_ports UART0_ctsn] [get_bd_pins axi_uart16550_0/ctsn] + connect_bd_net -net UART1_rxd_1 [get_bd_ports UART1_rxd] [get_bd_pins axi_uart16550_1/sin] connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In0] connect_bd_net -net axi_uart16550_0_rtsn [get_bd_ports UART0_rtsn] [get_bd_pins axi_uart16550_0/rtsn] connect_bd_net -net axi_uart16550_0_sout [get_bd_ports UART0_txd] [get_bd_pins axi_uart16550_0/sout] + connect_bd_net -net axi_uart16550_1_ip2intc_irpt [get_bd_pins axi_uart16550_1/ip2intc_irpt] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net axi_uart16550_1_sout [get_bd_ports UART1_txd] [get_bd_pins axi_uart16550_1/sout] connect_bd_net -net emio_uart0_ctsn_1 [get_bd_ports BT_ctsn] [get_bd_pins zynq_ultra_ps_e_0/emio_uart0_ctsn] connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins axi_uart16550_1/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] connect_bd_net -net sin_1 [get_bd_ports UART0_rxd] [get_bd_pins axi_uart16550_0/sin] connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] connect_bd_net -net zynq_ultra_ps_e_0_emio_uart0_rtsn [get_bd_ports BT_rtsn] [get_bd_pins zynq_ultra_ps_e_0/emio_uart0_rtsn] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins axi_uart16550_1/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] # Create address segments create_bd_addr_seg -range 0x00010000 -offset 0x80060000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] SEG_axi_uart16550_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x80070000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_uart16550_1/S_AXI/Reg] SEG_axi_uart16550_1_Reg # Restore current instance current_bd_instance $oldCurInst # Create PFM attributes - set_property PFM_NAME {xilinx.com:xd:sensors96b:2.0} [get_files [current_bd_design].bd] + set_property PFM_NAME {xilinx.com:xd:${design_name}:2.0} [get_files [current_bd_design].bd] validate_bd_design @@ -843,25 +946,3 @@ proc create_root_design { parentCell } { ################################################################## create_root_design "" - -# Add top wrapper and xdc files -make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top -add_files -norecurse ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v -set_property top ${design_name}_wrapper [current_fileset] -import_files -fileset constrs_1 -norecurse ./vivado/constraints/${overlay_name}.xdc -update_compile_order -fileset sources_1 - -# call implement -launch_runs impl_1 -to_step write_bitstream -jobs 4 -wait_on_run impl_1 - -# Create overlay hardware definition file and bitstream -write_hwdef -force -file ./${overlay_name}.hdf -file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./${overlay_name}.bit - -# Create files for optional PetaLinux integration -file mkdir ./${overlay_name}/${overlay_name}.sdk -file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.sysdef ./${overlay_name}/${overlay_name}.sdk/${design_name}_wrapper.hdf -file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./${overlay_name}/${overlay_name}.sdk/${design_name}_wrapper.bit - - diff --git a/Ultra96/sensors96b_v1.bsp b/Ultra96/sensors96b_v1.bsp index ed0cd78..a882e9d 100644 Binary files a/Ultra96/sensors96b_v1.bsp and b/Ultra96/sensors96b_v1.bsp differ diff --git a/Ultra96/sensors96b_v2.bsp b/Ultra96/sensors96b_v2.bsp index 616067f..806d4d4 100644 Binary files a/Ultra96/sensors96b_v2.bsp and b/Ultra96/sensors96b_v2.bsp differ diff --git a/Ultra96/specs/Ultra96_v1.spec b/Ultra96/specs/Ultra96_v1.spec index 3c80cd2..c64f635 100755 --- a/Ultra96/specs/Ultra96_v1.spec +++ b/Ultra96/specs/Ultra96_v1.spec @@ -1,4 +1,6 @@ ARCH_Ultra96 := aarch64 BSP_Ultra96 := sensors96b_v1.bsp +BITSTREAM_Ultra96 := sensors96b/sensors96b.bit STAGE4_PACKAGES_Ultra96 := pynq mraa upm usbgadget wpa_ap usb-eth0 sensorconf +STAGE4_PACKAGES_Ultra96 += xrt diff --git a/Ultra96/specs/Ultra96_v2.spec b/Ultra96/specs/Ultra96_v2.spec index 2922639..46d27d0 100755 --- a/Ultra96/specs/Ultra96_v2.spec +++ b/Ultra96/specs/Ultra96_v2.spec @@ -1,5 +1,6 @@ ARCH_Ultra96 := aarch64 BSP_Ultra96 := sensors96b_v2.bsp +BITSTREAM_Ultra96 := sensors96b/sensors96b.bit STAGE4_PACKAGES_Ultra96 := pynq mraa upm usbgadget usb-eth0 sensorconf -STAGE4_PACKAGES_Ultra96 += wilc3000 +STAGE4_PACKAGES_Ultra96 += wilc3000 xrt