devicetree.no-uart.dts

/dts-v1/;

/ {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "unknown,unknown";
    model = "unknown,unknown";
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;
        timebase-frequency = <500000>;
        CPU0: cpu@0 {
            device_type = "cpu";
            reg = <0>;
            status = "okay";
            compatible = "riscv";
            riscv,isa = "rv64imafdc";
            mmu-type = "riscv,sv39";
            clock-frequency = <50000000>;
            CPU0_intc: interrupt-controller {
                #address-cells = <1>;
		#interrupt-cells = <1>;
                interrupt-controller;
                compatible = "riscv,cpu-intc";
            };
        };
    };
    memory@C0000000 {
        device_type = "memory";
        reg = <0xC0000000 0x40000000>;
    };
    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "simple-bus";
        ranges;
        clint@10000000 {
            compatible = "riscv,clint0";
            interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
            reg = <0x10000000 0x10000>;
        };
        plic: interrupt-controller@c000000 {
            #address-cells = <1>;
            #interrupt-cells = <1>;
            compatible = "riscv,plic0";
            interrupt-controller;
            interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
            reg = <0xc000000 0x400000>;
            reg-names = "control";
            riscv,max-priority = <7>;
            riscv,ndev = <16>;
        };
    };
};