From b40da5ee68f27b5f2773a7db6c4c773521443598 Mon Sep 17 00:00:00 2001 From: Chia-Wei Wang Date: Thu, 30 Nov 2023 15:53:55 +0800 Subject: [PATCH] core: arm: fix NS entrypoint for secondary cores The NS entrypoint was originally backup from LR to R5. The commit f332e77c4b7c revises the register preservation to R8. The way to retrieve the NS entrypoint for secondary cores should be updated as well. Fixes: f332e77c4b7c ("core: arm: refactor boot argument handling") Signed-off-by: Chia-Wei Wang --- core/arch/arm/kernel/entry_a32.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/arm/kernel/entry_a32.S b/core/arch/arm/kernel/entry_a32.S index 373b648fbcf..a43d36afb7c 100644 --- a/core/arch/arm/kernel/entry_a32.S +++ b/core/arch/arm/kernel/entry_a32.S @@ -880,7 +880,7 @@ UNWIND( .cantunwind) bl boot_core_hpen ldm r0, {r0, r6} #else - mov r0, r5 /* ns-entry address */ + mov r0, r8 /* ns-entry address */ mov r6, #0 #endif bl boot_init_secondary