From cf8d24531e0464d32031e5490cf2772f47645674 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Thu, 24 Oct 2024 20:46:49 -0700 Subject: [PATCH] [msan] Reduces overhead of #113200, by 10% (#113201) CTMark #113200 size overhead was 5.3%, now it's 4.7%. The patch affects only signed integers. https://alive2.llvm.org/ce/z/Lv5hyi * The patch replaces code which extracted sign bit, maximized/minimized it, then packed it back, with simple sign bit flip. The another way to think about transformation is as a subtraction of MIN_SINT from A/B. Then we map MIN_SINT to 0, 0 to -MIN_SINT, and MAX_SINT to MAX_UINT. * Then to maximize/minimize A/B we don't need to extract sign bit, we can apply shadow the same way as to other bits. * After sign bit flip, we had to switch to unsigned version of the predicates. * After change above getHighestPossibleValue/getLowestPossibleValue became very similar, so we can combine into a single function. * Because the function does sign bit flip and requires unsigned predicates used for returned values, there is no point in keeping it as a member of class, to hide, we switch to function local lambda. --- .../Instrumentation/MemorySanitizer.cpp | 64 +- .../MemorySanitizer/msan_basic.ll | 606 ++++++------------ .../MemorySanitizer/pr32842.ll | 36 +- 3 files changed, 217 insertions(+), 489 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 0208c800a4fc3e..391fb30d95e2ae 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2694,40 +2694,6 @@ struct MemorySanitizerVisitor : public InstVisitor { setOriginForNaryOp(I); } - /// Build the lowest possible value of V, taking into account V's - /// uninitialized bits. - Value *getLowestPossibleValue(IRBuilder<> &IRB, Value *A, Value *Sa, - bool isSigned) { - if (isSigned) { - // Split shadow into sign bit and other bits. - Value *SaOtherBits = IRB.CreateLShr(IRB.CreateShl(Sa, 1), 1); - Value *SaSignBit = IRB.CreateXor(Sa, SaOtherBits); - // Maximise the undefined shadow bit, minimize other undefined bits. - return IRB.CreateOr(IRB.CreateAnd(A, IRB.CreateNot(SaOtherBits)), - SaSignBit); - } else { - // Minimize undefined bits. - return IRB.CreateAnd(A, IRB.CreateNot(Sa)); - } - } - - /// Build the highest possible value of V, taking into account V's - /// uninitialized bits. - Value *getHighestPossibleValue(IRBuilder<> &IRB, Value *A, Value *Sa, - bool isSigned) { - if (isSigned) { - // Split shadow into sign bit and other bits. - Value *SaOtherBits = IRB.CreateLShr(IRB.CreateShl(Sa, 1), 1); - Value *SaSignBit = IRB.CreateXor(Sa, SaOtherBits); - // Minimise the undefined shadow bit, maximise other undefined bits. - return IRB.CreateOr(IRB.CreateAnd(A, IRB.CreateNot(SaSignBit)), - SaOtherBits); - } else { - // Maximize undefined bits. - return IRB.CreateOr(A, Sa); - } - } - /// Instrument relational comparisons. /// /// This function does exact shadow propagation for all relational @@ -2750,12 +2716,30 @@ struct MemorySanitizerVisitor : public InstVisitor { // its undefined bits. Let [b0, b1] be the interval of possible values of B. // Then (A cmp B) is defined iff (a0 cmp b1) == (a1 cmp b0). bool IsSigned = I.isSigned(); - Value *Amin = getLowestPossibleValue(IRB, A, Sa, IsSigned); - Value *Bmax = getHighestPossibleValue(IRB, B, Sb, IsSigned); - Value *S1 = IRB.CreateICmp(I.getPredicate(), Amin, Bmax); - Value *Amax = getHighestPossibleValue(IRB, A, Sa, IsSigned); - Value *Bmin = getLowestPossibleValue(IRB, B, Sb, IsSigned); - Value *S2 = IRB.CreateICmp(I.getPredicate(), Amax, Bmin); + + auto GetMinMaxUnsigned = [&](Value *V, Value *S) { + if (IsSigned) { + // Sign-flip to map from signed range to unsigned range. Relation A vs B + // should be preserved, if checked with `getUnsignedPredicate()`. + // Relationship between Amin, Amax, Bmin, Bmax also will not be + // affected, as they are created by effectively adding/substructing from + // A (or B) a value, derived from shadow, with no overflow, either + // before or after sign flip. + APInt MinVal = + APInt::getSignedMinValue(V->getType()->getScalarSizeInBits()); + V = IRB.CreateXor(V, ConstantInt::get(V->getType(), MinVal)); + } + // Minimize undefined bits. + Value *Min = IRB.CreateAnd(V, IRB.CreateNot(S)); + Value *Max = IRB.CreateOr(V, S); + return std::make_pair(Min, Max); + }; + + auto [Amin, Amax] = GetMinMaxUnsigned(A, Sa); + auto [Bmin, Bmax] = GetMinMaxUnsigned(B, Sb); + Value *S1 = IRB.CreateICmp(I.getUnsignedPredicate(), Amin, Bmax); + Value *S2 = IRB.CreateICmp(I.getUnsignedPredicate(), Amax, Bmin); + Value *Si = IRB.CreateXor(S1, S2); setShadow(&I, Si); setOriginForNaryOp(I); diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll index 7aeb763b309048..8746f7f19023e4 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -1622,20 +1622,12 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP7]], 0 -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i32 [[TMP14]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 [[TMP4]], -2147483648 +; CHECK-NEXT: [[TMP15:%.*]] = icmp ult i32 [[TMP5]], -2147483648 ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp slt i32 [[X]], 0 ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1646,20 +1638,12 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0 -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0 +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP5]], -2147483648 +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ult i32 [[TMP6]], -2147483648 ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp slt i32 [[X]], 0 ; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1671,20 +1655,12 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0 -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0 +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP5]], -2147483648 +; CALLS-NEXT: [[TMP16:%.*]] = icmp ult i32 [[TMP6]], -2147483648 ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp slt i32 [[X]], 0 ; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1701,20 +1677,12 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sge i32 [[TMP7]], 0 -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP14]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp uge i32 [[TMP4]], -2147483648 +; CHECK-NEXT: [[TMP15:%.*]] = icmp uge i32 [[TMP5]], -2147483648 ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i32 [[X]], 0 ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1725,20 +1693,12 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0 -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0 +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp uge i32 [[TMP5]], -2147483648 +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp uge i32 [[TMP6]], -2147483648 ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp sge i32 [[X]], 0 ; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1750,20 +1710,12 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0 -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0 +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp uge i32 [[TMP5]], -2147483648 +; CALLS-NEXT: [[TMP16:%.*]] = icmp uge i32 [[TMP6]], -2147483648 ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp sge i32 [[X]], 0 ; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1780,20 +1732,12 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i32 0, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i32 0, [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i32 -2147483648, [[TMP5]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ugt i32 -2147483648, [[TMP4]] ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sgt i32 0, [[X]] ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1804,20 +1748,12 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]] -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]] +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ugt i32 -2147483648, [[TMP6]] +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ugt i32 -2147483648, [[TMP5]] ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -1831,20 +1767,12 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]] -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]] +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ugt i32 -2147483648, [[TMP6]] +; CALLS-NEXT: [[TMP16:%.*]] = icmp ugt i32 -2147483648, [[TMP5]] ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -1863,20 +1791,12 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sle i32 0, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sle i32 0, [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ule i32 -2147483648, [[TMP5]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ule i32 -2147483648, [[TMP4]] ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sle i32 0, [[X]] ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1887,20 +1807,12 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sle i32 0, [[TMP8]] -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sle i32 0, [[TMP15]] +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ule i32 -2147483648, [[TMP6]] +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ule i32 -2147483648, [[TMP5]] ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -1914,20 +1826,12 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sle i32 0, [[TMP8]] -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sle i32 0, [[TMP15]] +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ule i32 -2147483648, [[TMP6]] +; CALLS-NEXT: [[TMP16:%.*]] = icmp ule i32 -2147483648, [[TMP5]] ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -1949,20 +1853,12 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 -1, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i32 -1, [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 2147483647, [[TMP5]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ult i32 2147483647, [[TMP4]] ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp slt i32 -1, [[X]] ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1973,20 +1869,12 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp slt i32 -1, [[TMP8]] -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp slt i32 -1, [[TMP15]] +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ult i32 2147483647, [[TMP6]] +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ult i32 2147483647, [[TMP5]] ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -2000,20 +1888,12 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp slt i32 -1, [[TMP8]] -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp slt i32 -1, [[TMP15]] +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ult i32 2147483647, [[TMP6]] +; CALLS-NEXT: [[TMP16:%.*]] = icmp ult i32 2147483647, [[TMP5]] ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -2032,20 +1912,12 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sge i32 -1, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sge i32 -1, [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp uge i32 2147483647, [[TMP5]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp uge i32 2147483647, [[TMP4]] ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i32 -1, [[X]] ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -2056,20 +1928,12 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sge i32 -1, [[TMP8]] -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sge i32 -1, [[TMP15]] +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp uge i32 2147483647, [[TMP6]] +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp uge i32 2147483647, [[TMP5]] ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -2083,20 +1947,12 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sge i32 -1, [[TMP8]] -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sge i32 -1, [[TMP15]] +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp uge i32 2147483647, [[TMP6]] +; CALLS-NEXT: [[TMP16:%.*]] = icmp uge i32 2147483647, [[TMP5]] ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -2115,20 +1971,12 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[TMP7]], -1 -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i32 [[TMP14]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i32 [[TMP4]], 2147483647 +; CHECK-NEXT: [[TMP15:%.*]] = icmp ugt i32 [[TMP5]], 2147483647 ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sgt i32 [[X]], -1 ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -2139,20 +1987,12 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sgt i32 [[TMP8]], -1 -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP15]], -1 +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ugt i32 [[TMP5]], 2147483647 +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ugt i32 [[TMP6]], 2147483647 ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp sgt i32 [[X]], -1 ; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -2164,20 +2004,12 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sgt i32 [[TMP8]], -1 -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP15]], -1 +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ugt i32 [[TMP5]], 2147483647 +; CALLS-NEXT: [[TMP16:%.*]] = icmp ugt i32 [[TMP6]], 2147483647 ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp sgt i32 [[X]], -1 ; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -2194,20 +2026,12 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sle i32 [[TMP7]], -1 -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sle i32 [[TMP14]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ule i32 [[TMP4]], 2147483647 +; CHECK-NEXT: [[TMP15:%.*]] = icmp ule i32 [[TMP5]], 2147483647 ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sle i32 [[X]], -1 ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -2218,20 +2042,12 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sle i32 [[TMP8]], -1 -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sle i32 [[TMP15]], -1 +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ule i32 [[TMP5]], 2147483647 +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ule i32 [[TMP6]], 2147483647 ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp sle i32 [[X]], -1 ; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -2243,20 +2059,12 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sle i32 [[TMP8]], -1 -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sle i32 [[TMP15]], -1 +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ule i32 [[TMP5]], 2147483647 +; CALLS-NEXT: [[TMP16:%.*]] = icmp ule i32 [[TMP6]], 2147483647 ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp sle i32 [[X]], -1 ; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -2278,20 +2086,12 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone san ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <2 x ptr> [[X]] to <2 x i64> -; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP1]], -; CHECK-NEXT: [[TMP4:%.*]] = lshr <2 x i64> [[TMP3]], -; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i64> [[TMP1]], [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i64> [[TMP4]], -; CHECK-NEXT: [[TMP7:%.*]] = and <2 x i64> [[TMP2]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], [[TMP5]] -; CHECK-NEXT: [[TMP9:%.*]] = icmp slt <2 x i64> [[TMP8]], zeroinitializer -; CHECK-NEXT: [[TMP10:%.*]] = shl <2 x i64> [[TMP1]], -; CHECK-NEXT: [[TMP11:%.*]] = lshr <2 x i64> [[TMP10]], -; CHECK-NEXT: [[TMP12:%.*]] = xor <2 x i64> [[TMP1]], [[TMP11]] -; CHECK-NEXT: [[TMP13:%.*]] = xor <2 x i64> [[TMP12]], -; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i64> [[TMP2]], [[TMP13]] -; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP11]] -; CHECK-NEXT: [[TMP16:%.*]] = icmp slt <2 x i64> [[TMP15]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i64> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP1]], +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP3]], [[TMP1]] +; CHECK-NEXT: [[TMP9:%.*]] = icmp ult <2 x i64> [[TMP5]], +; CHECK-NEXT: [[TMP16:%.*]] = icmp ult <2 x i64> [[TMP6]], ; CHECK-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[TMP9]], [[TMP16]] ; CHECK-NEXT: [[TMP18:%.*]] = icmp slt <2 x ptr> [[X]], zeroinitializer ; CHECK-NEXT: store <2 x i1> [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -2303,20 +2103,12 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone san ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() ; ORIGIN-NEXT: [[TMP3:%.*]] = ptrtoint <2 x ptr> [[X]] to <2 x i64> -; ORIGIN-NEXT: [[TMP4:%.*]] = shl <2 x i64> [[TMP1]], -; ORIGIN-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], -; ORIGIN-NEXT: [[TMP6:%.*]] = xor <2 x i64> [[TMP1]], [[TMP5]] -; ORIGIN-NEXT: [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], -; ORIGIN-NEXT: [[TMP8:%.*]] = and <2 x i64> [[TMP3]], [[TMP7]] -; ORIGIN-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP6]] -; ORIGIN-NEXT: [[TMP10:%.*]] = icmp slt <2 x i64> [[TMP9]], zeroinitializer -; ORIGIN-NEXT: [[TMP11:%.*]] = shl <2 x i64> [[TMP1]], -; ORIGIN-NEXT: [[TMP12:%.*]] = lshr <2 x i64> [[TMP11]], -; ORIGIN-NEXT: [[TMP13:%.*]] = xor <2 x i64> [[TMP1]], [[TMP12]] -; ORIGIN-NEXT: [[TMP14:%.*]] = xor <2 x i64> [[TMP13]], -; ORIGIN-NEXT: [[TMP15:%.*]] = and <2 x i64> [[TMP3]], [[TMP14]] -; ORIGIN-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP12]] -; ORIGIN-NEXT: [[TMP17:%.*]] = icmp slt <2 x i64> [[TMP16]], zeroinitializer +; ORIGIN-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP3]], +; ORIGIN-NEXT: [[TMP5:%.*]] = xor <2 x i64> [[TMP1]], +; ORIGIN-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], [[TMP5]] +; ORIGIN-NEXT: [[TMP7:%.*]] = or <2 x i64> [[TMP4]], [[TMP1]] +; ORIGIN-NEXT: [[TMP10:%.*]] = icmp ult <2 x i64> [[TMP6]], +; ORIGIN-NEXT: [[TMP17:%.*]] = icmp ult <2 x i64> [[TMP7]], ; ORIGIN-NEXT: [[TMP18:%.*]] = xor <2 x i1> [[TMP10]], [[TMP17]] ; ORIGIN-NEXT: [[TMP19:%.*]] = icmp slt <2 x ptr> [[X]], zeroinitializer ; ORIGIN-NEXT: store <2 x i1> [[TMP18]], ptr @__msan_retval_tls, align 8 @@ -2329,20 +2121,12 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone san ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() ; CALLS-NEXT: [[TMP3:%.*]] = ptrtoint <2 x ptr> [[X]] to <2 x i64> -; CALLS-NEXT: [[TMP4:%.*]] = shl <2 x i64> [[TMP1]], -; CALLS-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], -; CALLS-NEXT: [[TMP6:%.*]] = xor <2 x i64> [[TMP1]], [[TMP5]] -; CALLS-NEXT: [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], -; CALLS-NEXT: [[TMP8:%.*]] = and <2 x i64> [[TMP3]], [[TMP7]] -; CALLS-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP6]] -; CALLS-NEXT: [[TMP10:%.*]] = icmp slt <2 x i64> [[TMP9]], zeroinitializer -; CALLS-NEXT: [[TMP11:%.*]] = shl <2 x i64> [[TMP1]], -; CALLS-NEXT: [[TMP12:%.*]] = lshr <2 x i64> [[TMP11]], -; CALLS-NEXT: [[TMP13:%.*]] = xor <2 x i64> [[TMP1]], [[TMP12]] -; CALLS-NEXT: [[TMP14:%.*]] = xor <2 x i64> [[TMP13]], -; CALLS-NEXT: [[TMP15:%.*]] = and <2 x i64> [[TMP3]], [[TMP14]] -; CALLS-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP12]] -; CALLS-NEXT: [[TMP17:%.*]] = icmp slt <2 x i64> [[TMP16]], zeroinitializer +; CALLS-NEXT: [[TMP4:%.*]] = xor <2 x i64> [[TMP3]], +; CALLS-NEXT: [[TMP5:%.*]] = xor <2 x i64> [[TMP1]], +; CALLS-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], [[TMP5]] +; CALLS-NEXT: [[TMP7:%.*]] = or <2 x i64> [[TMP4]], [[TMP1]] +; CALLS-NEXT: [[TMP10:%.*]] = icmp ult <2 x i64> [[TMP6]], +; CALLS-NEXT: [[TMP17:%.*]] = icmp ult <2 x i64> [[TMP7]], ; CALLS-NEXT: [[TMP18:%.*]] = xor <2 x i1> [[TMP10]], [[TMP17]] ; CALLS-NEXT: [[TMP19:%.*]] = icmp slt <2 x ptr> [[X]], zeroinitializer ; CALLS-NEXT: store <2 x i1> [[TMP18]], ptr @__msan_retval_tls, align 8 @@ -2362,20 +2146,12 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone ; CHECK-SAME: <2 x i32> [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i32> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i32> [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], -; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or <2 x i32> [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp slt <2 x i32> , [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl <2 x i32> [[TMP1]], -; CHECK-NEXT: [[TMP10:%.*]] = lshr <2 x i32> [[TMP9]], -; CHECK-NEXT: [[TMP11:%.*]] = xor <2 x i32> [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor <2 x i32> [[TMP10]], -; CHECK-NEXT: [[TMP13:%.*]] = and <2 x i32> [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp slt <2 x i32> , [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[X]], +; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = and <2 x i32> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i32> [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ult <2 x i32> , [[TMP5]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ult <2 x i32> , [[TMP4]] ; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i1> [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp slt <2 x i32> , [[X]] ; CHECK-NEXT: store <2 x i1> [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -2386,20 +2162,12 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone ; ORIGIN-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl <2 x i32> [[TMP1]], -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr <2 x i32> [[TMP3]], -; ORIGIN-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor <2 x i32> [[TMP5]], -; ORIGIN-NEXT: [[TMP7:%.*]] = and <2 x i32> [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], [[TMP4]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp slt <2 x i32> , [[TMP8]] -; ORIGIN-NEXT: [[TMP10:%.*]] = shl <2 x i32> [[TMP1]], -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr <2 x i32> [[TMP10]], -; ORIGIN-NEXT: [[TMP12:%.*]] = xor <2 x i32> [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor <2 x i32> [[TMP11]], -; ORIGIN-NEXT: [[TMP14:%.*]] = and <2 x i32> [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or <2 x i32> [[TMP14]], [[TMP12]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp slt <2 x i32> , [[TMP15]] +; ORIGIN-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[X]], +; ORIGIN-NEXT: [[TMP4:%.*]] = xor <2 x i32> [[TMP1]], +; ORIGIN-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or <2 x i32> [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ult <2 x i32> , [[TMP6]] +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ult <2 x i32> , [[TMP5]] ; ORIGIN-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 ; ORIGIN-NEXT: [[TMP19:%.*]] = icmp ne i64 [[TMP18]], 0 @@ -2414,20 +2182,12 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone ; CALLS-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl <2 x i32> [[TMP1]], -; CALLS-NEXT: [[TMP4:%.*]] = lshr <2 x i32> [[TMP3]], -; CALLS-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor <2 x i32> [[TMP5]], -; CALLS-NEXT: [[TMP7:%.*]] = and <2 x i32> [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], [[TMP4]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp slt <2 x i32> , [[TMP8]] -; CALLS-NEXT: [[TMP10:%.*]] = shl <2 x i32> [[TMP1]], -; CALLS-NEXT: [[TMP11:%.*]] = lshr <2 x i32> [[TMP10]], -; CALLS-NEXT: [[TMP12:%.*]] = xor <2 x i32> [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor <2 x i32> [[TMP11]], -; CALLS-NEXT: [[TMP14:%.*]] = and <2 x i32> [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or <2 x i32> [[TMP14]], [[TMP12]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp slt <2 x i32> , [[TMP15]] +; CALLS-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[X]], +; CALLS-NEXT: [[TMP4:%.*]] = xor <2 x i32> [[TMP1]], +; CALLS-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or <2 x i32> [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ult <2 x i32> , [[TMP6]] +; CALLS-NEXT: [[TMP16:%.*]] = icmp ult <2 x i32> , [[TMP5]] ; CALLS-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 ; CALLS-NEXT: [[TMP19:%.*]] = icmp ne i64 [[TMP18]], 0 @@ -2454,8 +2214,8 @@ define zeroext i1 @ICmpUGTConst(i32 %x) nounwind uwtable readnone sanitize_memor ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[TMP0]], -1 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 7 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[X]], [[TMP0]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 7 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i32 [[TMP4]], 7 ; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], 7 @@ -2470,8 +2230,8 @@ define zeroext i1 @ICmpUGTConst(i32 %x) nounwind uwtable readnone sanitize_memor ; ORIGIN-NEXT: call void @llvm.donothing() ; ORIGIN-NEXT: [[TMP2:%.*]] = xor i32 [[TMP0]], -1 ; ORIGIN-NEXT: [[TMP3:%.*]] = and i32 [[X]], [[TMP2]] -; ORIGIN-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 7 ; ORIGIN-NEXT: [[TMP5:%.*]] = or i32 [[X]], [[TMP0]] +; ORIGIN-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 7 ; ORIGIN-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 7 ; ORIGIN-NEXT: [[TMP7:%.*]] = xor i1 [[TMP4]], [[TMP6]] ; ORIGIN-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], 7 @@ -2487,8 +2247,8 @@ define zeroext i1 @ICmpUGTConst(i32 %x) nounwind uwtable readnone sanitize_memor ; CALLS-NEXT: call void @llvm.donothing() ; CALLS-NEXT: [[TMP2:%.*]] = xor i32 [[TMP0]], -1 ; CALLS-NEXT: [[TMP3:%.*]] = and i32 [[X]], [[TMP2]] -; CALLS-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 7 ; CALLS-NEXT: [[TMP5:%.*]] = or i32 [[X]], [[TMP0]] +; CALLS-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 7 ; CALLS-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 7 ; CALLS-NEXT: [[TMP7:%.*]] = xor i1 [[TMP4]], [[TMP6]] ; CALLS-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], 7 diff --git a/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll b/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll index 17fe78d292bd04..6d275b3e2d3839 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll @@ -15,32 +15,16 @@ define zeroext i1 @_Z1fii(i32 %x, i32 %y) sanitize_memory { ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP28:%.*]] = shl i32 [[TMP0]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP28]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP0]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP9:%.*]] = lshr i32 [[TMP8]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[TMP1]], [[TMP9]] -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[Y]], [[TMP11]] -; CHECK-NEXT: [[TMP13:%.*]] = or i32 [[TMP12]], [[TMP9]] -; CHECK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[TMP7]], [[TMP13]] -; CHECK-NEXT: [[TMP15:%.*]] = shl i32 [[TMP0]], 1 -; CHECK-NEXT: [[TMP16:%.*]] = lshr i32 [[TMP15]], 1 -; CHECK-NEXT: [[TMP17:%.*]] = xor i32 [[TMP0]], [[TMP16]] -; CHECK-NEXT: [[TMP18:%.*]] = xor i32 [[TMP17]], -1 -; CHECK-NEXT: [[TMP19:%.*]] = and i32 [[X]], [[TMP18]] -; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP19]], [[TMP16]] -; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP21]], 1 -; CHECK-NEXT: [[TMP23:%.*]] = xor i32 [[TMP1]], [[TMP22]] -; CHECK-NEXT: [[TMP24:%.*]] = xor i32 [[TMP22]], -1 -; CHECK-NEXT: [[TMP25:%.*]] = and i32 [[Y]], [[TMP24]] -; CHECK-NEXT: [[TMP26:%.*]] = or i32 [[TMP25]], [[TMP23]] -; CHECK-NEXT: [[TMP27:%.*]] = icmp slt i32 [[TMP20]], [[TMP26]] +; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP0]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP10]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP10]], [[TMP0]] +; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[Y]], -2147483648 +; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP6]], [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = or i32 [[TMP6]], [[TMP1]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp ult i32 [[TMP4]], [[TMP9]] +; CHECK-NEXT: [[TMP27:%.*]] = icmp ult i32 [[TMP5]], [[TMP8]] ; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP14]], [[TMP27]] ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X]], [[Y]] ; CHECK-NEXT: store i1 [[TMP2]], ptr @__msan_retval_tls, align 8