From b31e4a3c273119f0e3926eed0af195d0e5e23be6 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Fri, 25 Oct 2024 14:27:16 -0700 Subject: [PATCH] JIT: Moves Arm64 JIT up one folder We have only one JIT, there is no reason to subfolder this. Move it up one folder. NFC --- FEXCore/Source/CMakeLists.txt | 22 +++++++++---------- FEXCore/Source/Interface/Core/Core.cpp | 4 ++-- .../Interface/Core/JIT/{Arm64 => }/ALUOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/Arm64Relocations.cpp | 2 +- .../Core/JIT/{Arm64 => }/AtomicOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/BranchOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/ConversionOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/EncryptionOps.cpp | 2 +- .../Interface/Core/JIT/{Arm64 => }/JIT.cpp | 2 +- .../Interface/Core/JIT/{Arm64 => }/JITClass.h | 3 +++ FEXCore/Source/Interface/Core/JIT/JITCore.h | 21 ------------------ .../Core/JIT/{Arm64 => }/MemoryOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/MiscOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/MoveOps.cpp | 2 +- .../Core/JIT/{Arm64 => }/VectorOps.cpp | 2 +- 15 files changed, 27 insertions(+), 45 deletions(-) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/ALUOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/Arm64Relocations.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/AtomicOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/BranchOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/ConversionOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/EncryptionOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/JIT.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/JITClass.h (98%) delete mode 100644 FEXCore/Source/Interface/Core/JIT/JITCore.h rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/MemoryOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/MiscOps.cpp (99%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/MoveOps.cpp (95%) rename FEXCore/Source/Interface/Core/JIT/{Arm64 => }/VectorOps.cpp (99%) diff --git a/FEXCore/Source/CMakeLists.txt b/FEXCore/Source/CMakeLists.txt index e25fe4327a..13be501484 100644 --- a/FEXCore/Source/CMakeLists.txt +++ b/FEXCore/Source/CMakeLists.txt @@ -105,17 +105,17 @@ set (SRCS Interface/Core/ArchHelpers/Arm64Emitter.cpp Interface/Core/Dispatcher/Dispatcher.cpp Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp - Interface/Core/JIT/Arm64/JIT.cpp - Interface/Core/JIT/Arm64/ALUOps.cpp - Interface/Core/JIT/Arm64/AtomicOps.cpp - Interface/Core/JIT/Arm64/BranchOps.cpp - Interface/Core/JIT/Arm64/ConversionOps.cpp - Interface/Core/JIT/Arm64/EncryptionOps.cpp - Interface/Core/JIT/Arm64/MemoryOps.cpp - Interface/Core/JIT/Arm64/MiscOps.cpp - Interface/Core/JIT/Arm64/MoveOps.cpp - Interface/Core/JIT/Arm64/VectorOps.cpp - Interface/Core/JIT/Arm64/Arm64Relocations.cpp + Interface/Core/JIT/JIT.cpp + Interface/Core/JIT/ALUOps.cpp + Interface/Core/JIT/AtomicOps.cpp + Interface/Core/JIT/BranchOps.cpp + Interface/Core/JIT/ConversionOps.cpp + Interface/Core/JIT/EncryptionOps.cpp + Interface/Core/JIT/MemoryOps.cpp + Interface/Core/JIT/MiscOps.cpp + Interface/Core/JIT/MoveOps.cpp + Interface/Core/JIT/VectorOps.cpp + Interface/Core/JIT/Arm64Relocations.cpp Interface/Core/X86Tables/BaseTables.cpp Interface/Core/X86Tables/DDDTables.cpp Interface/Core/X86Tables/H0F38Tables.cpp diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp index d6fcb77c81..c261ad0ef0 100644 --- a/FEXCore/Source/Interface/Core/Core.cpp +++ b/FEXCore/Source/Interface/Core/Core.cpp @@ -9,14 +9,14 @@ desc: Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispa */ #include -#include "Interface/Core/ArchHelpers//Arm64Emitter.h" +#include "Interface/Core/ArchHelpers/Arm64Emitter.h" #include "Interface/Core/LookupCache.h" #include "Interface/Core/CPUBackend.h" #include "Interface/Core/CPUID.h" #include "Interface/Core/Frontend.h" #include "Interface/Core/ObjectCache/ObjectCacheService.h" #include "Interface/Core/OpcodeDispatcher.h" -#include "Interface/Core/JIT/JITCore.h" +#include "Interface/Core/JIT/JITClass.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/Core/X86Tables/X86Tables.h" #include "Interface/IR/IR.h" diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp rename to FEXCore/Source/Interface/Core/JIT/ALUOps.cpp index 940b8e21a6..99b01acb5a 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp @@ -8,7 +8,7 @@ tags: backend|arm64 #include "CodeEmitter/Emitter.h" #include "FEXCore/IR/IR.h" #include "Interface/Context/Context.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include "Interface/IR/Passes/RegisterAllocationPass.h" namespace FEXCore::CPU { diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp rename to FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp index c643ca733b..bf4afe0b96 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp @@ -6,7 +6,7 @@ desc: relocation logic of the arm64 splatter backend $end_info$ */ #include "Interface/Context/Context.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp b/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp rename to FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp index 3c71f28d89..3834cba702 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp @@ -7,7 +7,7 @@ tags: backend|arm64 #include "Interface/Context/Context.h" #include "Interface/Core/Dispatcher/Dispatcher.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" namespace FEXCore::CPU { #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp rename to FEXCore/Source/Interface/Core/JIT/BranchOps.cpp index 9591f2e126..215ea9459d 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp @@ -9,7 +9,7 @@ tags: backend|arm64 #include "FEXCore/IR/IR.h" #include "Interface/Core/LookupCache.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include #include diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp b/FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp rename to FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp index 01d9724d6a..77824059a5 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp @@ -5,7 +5,7 @@ tags: backend|arm64 $end_info$ */ -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" namespace FEXCore::CPU { #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp b/FEXCore/Source/Interface/Core/JIT/EncryptionOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp rename to FEXCore/Source/Interface/Core/JIT/EncryptionOps.cpp index 33af7f911e..5b3cf4d9b0 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/EncryptionOps.cpp @@ -5,7 +5,7 @@ tags: backend|arm64 $end_info$ */ -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" namespace FEXCore::CPU { #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp rename to FEXCore/Source/Interface/Core/JIT/JIT.cpp index ea6e23322d..be19356219 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/JIT.cpp @@ -16,7 +16,7 @@ desc: Main glue logic of the arm64 splatter backend #include "Interface/Core/LookupCache.h" #include "Interface/Core/Dispatcher/Dispatcher.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include "Interface/IR/Passes/RegisterAllocationPass.h" diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h b/FEXCore/Source/Interface/Core/JIT/JITClass.h similarity index 98% rename from FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h rename to FEXCore/Source/Interface/Core/JIT/JITClass.h index 3cee644c32..ca142224dd 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h +++ b/FEXCore/Source/Interface/Core/JIT/JITClass.h @@ -352,4 +352,7 @@ class Arm64JITCore final : public CPUBackend, public Arm64Emitter { #undef DEF_OP }; +[[nodiscard]] +fextl::unique_ptr CreateArm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread); + } // namespace FEXCore::CPU diff --git a/FEXCore/Source/Interface/Core/JIT/JITCore.h b/FEXCore/Source/Interface/Core/JIT/JITCore.h deleted file mode 100644 index 4cc5f0be7e..0000000000 --- a/FEXCore/Source/Interface/Core/JIT/JITCore.h +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: MIT -#pragma once - -#include "Interface/Core/CPUBackend.h" -#include - -namespace FEXCore::Context { -class ContextImpl; -} - -namespace FEXCore::Core { -struct InternalThreadState; -} - -namespace FEXCore::CPU { -class CPUBackend; - -[[nodiscard]] -fextl::unique_ptr CreateArm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread); - -} // namespace FEXCore::CPU diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp rename to FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp index b8defb9b37..1ca09cc8c8 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp @@ -9,7 +9,7 @@ tags: backend|arm64 #include "FEXCore/Utils/LogManager.h" #include "Interface/Context/Context.h" #include "Interface/Core/CPUID.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include #include diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp b/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp rename to FEXCore/Source/Interface/Core/JIT/MiscOps.cpp index 8699ee699e..b826c038c7 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp @@ -10,7 +10,7 @@ tags: backend|arm64 #endif #include "Interface/Context/Context.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include "FEXCore/Debug/InternalThreadState.h" #include diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp b/FEXCore/Source/Interface/Core/JIT/MoveOps.cpp similarity index 95% rename from FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp rename to FEXCore/Source/Interface/Core/JIT/MoveOps.cpp index 695fcc1a98..bbb1c74061 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MoveOps.cpp @@ -5,7 +5,7 @@ tags: backend|arm64 $end_info$ */ -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" namespace FEXCore::CPU { #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp similarity index 99% rename from FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp rename to FEXCore/Source/Interface/Core/JIT/VectorOps.cpp index d6d2ce70c8..04a5909a21 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp @@ -6,7 +6,7 @@ tags: backend|arm64 */ #include "Interface/Core/Dispatcher/Dispatcher.h" -#include "Interface/Core/JIT/Arm64/JITClass.h" +#include "Interface/Core/JIT/JITClass.h" #include