From 0e31077735eda285e9752718fcd9d661f11ec1a4 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 27 Oct 2024 18:36:53 -0700 Subject: [PATCH] IR: Change VFNMLAScalarInsert to use IR::OpSize --- FEXCore/Source/Interface/IR/IR.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index d6be27e51d..9578195e4d 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -1849,7 +1849,7 @@ "NumElements": "RegisterSize / ElementSize", "TiedSource": 0 }, - "FPR = VFNMLAScalarInsert u8:#RegisterSize, u8:#ElementSize, FPR:$Upper, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": { + "FPR = VFNMLAScalarInsert OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Upper, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": { "Desc": [ "Dest = (-Vector1 * Vector2) + Addend", "This explicitly matches x86 FMA semantics because ARM semantics are mind-bending.",