From 22648794dad65478cb9460e11f5ca958c9a45ee7 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 29 Jan 2024 13:33:38 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../FlagM/PrimaryGroup.json | 24 +++++--------- .../InstructionCountCI/FlagM/Secondary.json | 21 +++++------- .../InstructionCountCI/PrimaryGroup.json | 32 +++++++------------ unittests/InstructionCountCI/Secondary.json | 21 +++++------- 4 files changed, 36 insertions(+), 62 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 42390392e4..8a55b250fa 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -1113,16 +1113,14 @@ ] }, "shr al, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w26, w20, #2", "bfxil x4, x26, #0, #8", - "cset w21, vs", "cmn wzr, w26, lsl #24", - "rmif x20, #0, #nzCv", - "rmif x21, #0, #nzcV" + "rmif x20, #0, #nzCv" ] }, "sar al, 2": { @@ -1331,42 +1329,36 @@ ] }, "shr ax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w26, w20, #2", "bfxil x4, x26, #0, #16", - "cset w21, vs", "cmn wzr, w26, lsl #16", - "rmif x20, #0, #nzCv", - "rmif x21, #0, #nzcV" + "rmif x20, #0, #nzCv" ] }, "shr eax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "mov w20, w4", "lsr w4, w20, #2", - "cset w21, vs", "tst w4, w4", "rmif x20, #0, #nzCv", - "mov x26, x4", - "rmif x21, #0, #nzcV" + "mov x26, x4" ] }, "shr rax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "mov x20, x4", "lsr x4, x20, #2", - "cset w21, vs", "tst x4, x4", "rmif x20, #0, #nzCv", - "mov x26, x4", - "rmif x21, #0, #nzcV" + "mov x26, x4" ] }, "sar ax, 2": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index d0a30a9b1f..8c173f88d8 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -779,13 +779,12 @@ ] }, "shld ax, bx, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", - "uxtb w22, w5", - "and x22, x22, #0x1f", + "and x22, x5, #0x1f", "mov w23, #0x10", "sub x23, x23, x22", "lsl x24, x21, x22", @@ -809,15 +808,13 @@ ] }, "shld eax, ebx, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w4", - "uxtb w22, w5", - "and x22, x22, #0x1f", - "mov w23, #0x20", - "sub x23, x23, x22", + "and x22, x5, #0x1f", + "neg x23, x22", "lsl x24, x21, x22", "lsr w20, w20, w23", "orr x20, x24, x20", @@ -839,14 +836,12 @@ ] }, "shld rax, rbx, cl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "mov x20, x4", - "uxtb w21, w5", - "and x21, x21, #0x3f", - "mov w22, #0x40", - "sub x22, x22, x21", + "and x21, x5, #0x3f", + "neg x22, x21", "lsl x23, x20, x21", "lsr x22, x7, x22", "orr x22, x23, x22", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 8c3ee4fc23..15ac891099 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -1239,18 +1239,16 @@ ] }, "shr al, 2": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w26, w20, #2", "bfxil x4, x26, #0, #8", - "cset w21, vs", "cmn wzr, w26, lsl #24", - "mrs x22, nzcv", + "mrs x21, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w22, w20, lsl #29", - "orr w20, w20, w21, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1508,50 +1506,44 @@ ] }, "shr ax, 2": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w26, w20, #2", "bfxil x4, x26, #0, #16", - "cset w21, vs", "cmn wzr, w26, lsl #16", - "mrs x22, nzcv", + "mrs x21, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w22, w20, lsl #29", - "orr w20, w20, w21, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "shr eax, 2": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "mov w20, w4", "lsr w4, w20, #2", - "cset w21, vs", "tst w4, w4", - "mrs x22, nzcv", + "mrs x21, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w22, w20, lsl #29", + "orr w20, w21, w20, lsl #29", "mov x26, x4", - "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "shr rax, 2": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "mov x20, x4", "lsr x4, x20, #2", - "cset w21, vs", "tst x4, x4", - "mrs x22, nzcv", + "mrs x21, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w22, w20, lsl #29", + "orr w20, w21, w20, lsl #29", "mov x26, x4", - "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 591b8751ba..2c13ad430c 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -1593,13 +1593,12 @@ ] }, "shld ax, bx, cl": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 27, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", - "uxtb w22, w5", - "and x22, x22, #0x1f", + "and x22, x5, #0x1f", "mov w23, #0x10", "sub x23, x23, x22", "lsl x24, x21, x22", @@ -1627,15 +1626,13 @@ ] }, "shld eax, ebx, cl": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w4", - "uxtb w22, w5", - "and x22, x22, #0x1f", - "mov w23, #0x20", - "sub x23, x23, x22", + "and x22, x5, #0x1f", + "neg x23, x22", "lsl x24, x21, x22", "lsr w20, w20, w23", "orr x20, x24, x20", @@ -1661,14 +1658,12 @@ ] }, "shld rax, rbx, cl": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 24, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "mov x20, x4", - "uxtb w21, w5", - "and x21, x21, #0x3f", - "mov w22, #0x40", - "sub x22, x22, x21", + "and x21, x5, #0x3f", + "neg x22, x21", "lsl x23, x20, x21", "lsr x22, x7, x22", "orr x22, x23, x22",