diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 1add165faf..a36bd7e209 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -1280,6 +1280,13 @@ void OpDispatchBuilder::TESTOp(OpcodeArgs) {
 
   auto Size = GetDstSize(Op);
 
+  // Optimize out masking constants
+  uint64_t Const;
+  if (IsValueConstant(WrapNode(Src), &Const)) {
+    if (Const == (Size == 8 ? ~0ULL : ((1ull << Size * 8) - 1)))
+      Src = Dest;
+  }
+
   InvalidateDeferredFlags();
 
   // SF/ZF/CF/OF
diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json
index 8018a7a67f..4b89af631c 100644
--- a/unittests/InstructionCountCI/FlagM/Primary.json
+++ b/unittests/InstructionCountCI/FlagM/Primary.json
@@ -2413,7 +2413,7 @@
       "ExpectedInstructionCount": 2,
       "Comment": "0xa8",
       "ExpectedArm64ASM": [
-        "and w26, w4, #0xff",
+        "mov x26, x4",
         "cmn wzr, w26, lsl #24"
       ]
     },
@@ -2421,24 +2421,22 @@
       "ExpectedInstructionCount": 2,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
-        "and w26, w4, #0xffff",
+        "mov x26, x4",
         "cmn wzr, w26, lsl #16"
       ]
     },
     "test eax, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
-        "mov w20, #0xffffffff",
-        "ands w26, w4, w20"
+        "ands w26, w4, w4"
       ]
     },
     "test rax, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
-        "mov x20, #0xffffffffffffffff",
-        "ands x26, x4, x20"
+        "ands x26, x4, x4"
       ]
     },
     "scasb": {
diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
index 05cfdc6a94..db45d4965f 100644
--- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -2345,24 +2345,22 @@
       "ExpectedInstructionCount": 2,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
-        "and w26, w7, #0xffff",
+        "mov x26, x7",
         "cmn wzr, w26, lsl #16"
       ]
     },
     "test ebx, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
-        "mov w20, #0xffffffff",
-        "ands w26, w7, w20"
+        "ands w26, w7, w7"
       ]
     },
     "test rbx, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
-        "mov x20, #0xffffffffffffffff",
-        "ands x26, x7, x20"
+        "ands x26, x7, x7"
       ]
     },
     "neg bx": {
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index 0f9d2037fc..01d6df23d9 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -3611,7 +3611,7 @@
       "ExpectedInstructionCount": 2,
       "Comment": "0xa8",
       "ExpectedArm64ASM": [
-        "and w26, w4, #0xff",
+        "mov x26, x4",
         "cmn wzr, w26, lsl #24"
       ]
     },
@@ -3619,24 +3619,22 @@
       "ExpectedInstructionCount": 2,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
-        "and w26, w4, #0xffff",
+        "mov x26, x4",
         "cmn wzr, w26, lsl #16"
       ]
     },
     "test eax, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
-        "mov w20, #0xffffffff",
-        "ands w26, w4, w20"
+        "ands w26, w4, w4"
       ]
     },
     "test rax, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
-        "mov x20, #0xffffffffffffffff",
-        "ands x26, x4, x20"
+        "ands x26, x4, x4"
       ]
     },
     "stosb": {
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index 8500998d66..d29181e0b8 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -2839,24 +2839,22 @@
       "ExpectedInstructionCount": 2,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
-        "and w26, w7, #0xffff",
+        "mov x26, x7",
         "cmn wzr, w26, lsl #16"
       ]
     },
     "test ebx, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
-        "mov w20, #0xffffffff",
-        "ands w26, w7, w20"
+        "ands w26, w7, w7"
       ]
     },
     "test rbx, -1": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
-        "mov x20, #0xffffffffffffffff",
-        "ands x26, x7, x20"
+        "ands x26, x7, x7"
       ]
     },
     "not bx": {