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mc.py
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mc.py
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# coding=utf-8
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# Dynamic Reduced Instruction Set Computer (d'RISC) [a.k.a. multi-OISC (mOISC)] cross-compiler/translator and linker
# Copyright (C) March 18, 2020, Marco Crepaldi, Istituto Italiano di Tecnologia (IIT)
# Electronic Design Laboratory (EDL)
# Via Melen 83, 16152, Genova, Italy
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
# taken from GNU Blender: https://svn.blender.org/svnroot/bf-blender/trunk/blender/build_files/scons/tools/bcolors.py
class bcolors:
HEADER = '\033[95m'
OKGREEN = '\033[92m'
OKBLUE = '\033[94m'
WARNING = '\033[93m'
FAIL = '\033[91m'
ENDC = '\033[0m'
BOLD = '\033[1m'
UNDERLINE = '\033[4m'
import sys
if sys.version_info.major < 3:
sys.stdout.write(bcolors.FAIL + "Error: " + bcolors.ENDC + "Cannot run this program with Python 2.\n")
sys.exit(1)
import os
import re
try:
import argparse
except:
sys.stdout.write(bcolors.FAIL + "Error: " + bcolors.ENDC + "Python module argparse not found. If you want to install it, please run python3 -m pip install argparse\n")
sys.exit(1)
from pathlib import Path
from dataclasses import dataclass
class arch_to_drisc:
_MIPSEL = 'mipsel'
_X86 = 'x86'
_ARM = 'arm'
_RISCV32 = 'riscv32'
_LL = 'll'
def __init__(self, intermediate='mipsel', linker=True):
self.intermediate = intermediate
self.linker = linker
if self.intermediate != self._MIPSEL and self.intermediate != self._X86 and self.intermediate != self._ARM and self.intermediate != self._RISCV32 and self.intermediate != self._LL:
sys.stdout.write(bcolors.FAIL + "Error: " + bcolors.ENDC + self.intermediate + " architecture not implemented.\n")
sys.exit(1)
self.stack_offset = '31500'
self.sp_offset = self.stack_offset
self.esp_offset = '0' #self.stack_offset
self.es_offset = '0'
self.isp_offset = self.stack_offset
self.lr_offset = self.stack_offset
self.CODERAM_LBL = []
self.CODERAM_MNEMONIC = []
self.DATARAM_LBL = []
self.DATARAM_VALUE = []
self.BOOTSTRAP = ['MCR', 'CHR', 'IWR', 'ICR', 'CSR', 'ISR', 'IDR', 'IOR']
self.BOOTSTRAP_DMEM = ['255', '0', '0', '0', '0', '0', '0', '0']
self.primitive_directory = "./lib/arch"
self.primitives_mipsel = ['sra','beq', 'movz', 'lui', 'not', 'add', 'and', 'move', 'or', 'sll', 'srl', 'sub', 'xnor', 'xor', 'lw', 'sw','label','j','jr','nop','jal','main','slti','beqz','bgtz','bnez','bne','negu','bgez','__setcsr','__seticr','__setidr','__setiwr','__setchr', '__setior', '__getior','__getisr']
self.primitives_x86 = ['al_restore', 'bl_restore', 'cl_restore', 'dl_restore', 'leal_leftmost_quadruple','testb','setl','movl_rightmost_vector_zero','movl_leftmost_vector_zero', 'movl_rightmost_triple', 'movl_leftmost_zero', 'movl_rightmost_zero', 'al_reg', 'bl_reg', 'dl_reg', 'main_redirect', 'rep_movsl_noop', 'movl_leftmost_triple', 'rep_movsl', 'cl_reg', 'addl_leftmost', 'addl_rightmost', 'jl', 'leal', 'leal_leftmost', 'jne', 'jle', 'jg', 'je', 'sarl','jge', '__setior','__setcsr', '__setidr', '__seticr', '__setiwr', '__setchr', '__getior', '__getisr', 'jmp','addl','shll','andl','orl','orl_leftmost','orl_rightmost','calll', 'subl', 'subl_rightmost', 'subl_leftmost', 'xorl', 'retl', 'popl', 'main', 'pushl', 'label', 'movl', 'movl_rightmost', 'movl_leftmost', 'cmpl', 'cmpl_rightmost', 'cmpl_leftmost']
self.primitives_arm = ['movlt','ldr_triple_lsl_wb','str_triple_lsl','tst','blx', 'add_lsl','bx_noex', 'main_redirect', 'ble', 'bge', 'ldr_double_const','lsl','mvn','bne','stm_xt','stm_xt_wb','stm_xt_op','ldm_xt','ldm_xt_wb','ldm_xt_op','blt','asr','ldr_triple_lsl','beq', 'bic', 'ldrb_double', 'ldrb_triple', 'pop', 'pop2','lsr','rsb','orr','orr_lsl', 'and', 'and_lsr', 'bl','push', 'push2', 'push3', 'push4', 'push5', 'push6', 'bgt','cmp', 'ldr_double', 'ldr_triple','b', 'move', 'mov_pc_lr', 'add', 'str_double', 'str_triple', 'sub', '_main','label','__setcsr','__seticr','__setidr','__setiwr','__setchr', '__setior', '__getior','__getisr','cmn']
self.primitives_riscv32 = ['sra','bge','blt','beq', 'lui', 'not', 'add', 'and', 'mv', 'or', 'sll', 'srl', 'sub', 'xnor', 'xor', 'lw', 'sw','label','j','jr','nop','call','main','slti','beqz','bgtz','bnez','bne','bgez','__setcsr','__seticr','__setidr','__setiwr','__setchr', '__setior', '__getior','__getisr']
self.primitives_ll = ['constant','global', 'label','add','icmp','getelementptr','and','alloca','bitcast_to','sext_to','store','inttoptr','br','load']
#self.primitives_ll = ['icmp','and','br']
if intermediate == self._MIPSEL:
self.primitives = self.primitives_mipsel
elif intermediate == self._X86:
self.primitives = self.primitives_x86
elif intermediate == self._ARM:
self.primitives = self.primitives_arm
elif intermediate == self._RISCV32:
self.primitives = self.primitives_riscv32
elif intermediate == self._LL:
self.primitives = self.primitives_ll
self.mnemonic = 'exec'
self.macro_primitives_exec = []
self.macro_primitives_dmem = []
self.macro_primitives_dmem_data = []
for _ in self.primitives:
self.macro_primitives_exec.append([])
self.macro_primitives_dmem.append([])
self.macro_primitives_dmem_data.append([])
self.NUMSET = "-0123456789"
self.immvar = 0
self.immvarprefix = "imm."
self.lvar = 0
# fast mode (express MCR)
self.MCRsSYM = ['_SUBLMCR', '_MOVMCR', '_ADDMCR', '_SHLMCR', '_SHRMCR', '_ORMCR', '_ANDMCR', '_XORMCR', '_XNORMCR', '_PCMCR','_MEMMCR','_MEMRMCR','_PCSMCR']
self.MCRsVAL = [0xFF, 0xEE, 0xCC, 0x99, 0x88, 0x77, 0x66, 0x55, 0x44, 0x33, 0x22, 0x11, 0x00]
self.OPCODE = ['subleq', 'movleq', 'addleq', 'shlleq', 'shrleq', 'orleq', 'andleq', 'xorleq', 'xnorleq', 'pc', 'mem', 'memr', 'pcs']
self._INSTR_ID = 'exec'
self._MEMID = ':'
self.PCMCR_RESCALE = '_PCMCR_'
def set_stack_offset(self, stack_offset):
self.stack_offset = stack_offset
self.sp_offset = self.stack_offset
self.esp_offset = self.stack_offset
self.es_offset = '0'
self.isp_offset = self.stack_offset
self.lr_offset = self.stack_offset
self.llvm_m_ptr = self.stack_offset
def load_primitives(self):
try:
for primitive in self.primitives:
fp = open(self.primitive_directory + "/" + self.intermediate + '/' + primitive + ".asm",'r')
while True:
line = fp.readline().replace('\t','').replace('\n','').replace('\r','')
if line != "":
if line[0] != '#':
if self.mnemonic in line:
self.macro_primitives_exec[self.primitives.index(primitive)].append(line)
else:
line = line.replace(' ','')
meta = line.split(':')
if meta[1] == '':
self.macro_primitives_exec[self.primitives.index(primitive)].append(line)
else:
self.macro_primitives_dmem[self.primitives.index(primitive)].append(meta[0])
self.macro_primitives_dmem_data[self.primitives.index(primitive)].append(meta[1])
else:
break
fp.close()
for i in range(len(self.macro_primitives_dmem)):
for j in range(len(self.macro_primitives_dmem[i])):
if (self.macro_primitives_dmem[i][j] not in self.DATARAM_LBL) and (self.macro_primitives_dmem[i][j] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(self.macro_primitives_dmem[i][j])
self.DATARAM_VALUE.append(self.macro_primitives_dmem_data[i][j])
except:
sys.stdout.write(bcolors.FAIL + "Error: " + bcolors.ENDC + "Cannot load " + self.intermediate + " primitives. Some of them may be missing.\n")
sys.exit(1)
def update_links_riscv32(self, primitivein, operands, operands_len, isref=False):
self.isdefined0 = False
self.isdefined1 = False
self.isdefined2 = False
self.tomem0 = ''
self.tomem1 = ''
self.tomem2 = ''
self.lvar += 1
for idx in range(len(operands)):
if [i in self.NUMSET for i in operands[idx]] == [True] * len(operands[idx]):
if idx == 0:
self.tomem0 = str(operands[idx])
elif idx == 1:
self.tomem1 = str(operands[idx])
elif idx == 2:
self.tomem2 = str(operands[idx])
indices = [i for i, x in enumerate(self.DATARAM_VALUE) if x == str(operands[idx]) and self.DATARAM_LBL[i][0:len(self.immvarprefix)] == self.immvarprefix]
if indices == []:
operands[idx] = self.immvarprefix + str(self.immvar)
self.immvar += 1
if idx == 0:
self.isdefined0 = True
elif idx == 1:
self.isdefined1 = True
elif idx == 2:
self.isdefined2 = True
else:
operands[idx] = self.DATARAM_LBL[indices[0]]
newprimitive = []
for primitive in primitivein:
if len(operands) >= 3:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
elif len(operands) == 2:
tmp = primitive.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
else:
tmp = primitive.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
newprimitive.append(tmp)
if isref == False:
if (len(operands) > 0):
if (operands[0] not in self.DATARAM_LBL) and (operands[0] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(operands[0])
if (self.isdefined0 == True):
self.DATARAM_VALUE.append(self.tomem0)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 1):
if (operands[1] not in self.DATARAM_LBL) and (operands[1] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(operands[1])
if (self.isdefined1 == True):
self.DATARAM_VALUE.append(self.tomem1)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 2):
if (operands[2] not in self.DATARAM_LBL) and (operands[2] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(operands[2])
if (self.isdefined2 == True):
self.DATARAM_VALUE.append(self.tomem2)
else:
self.DATARAM_VALUE.append('0')
return newprimitive
def update_links(self, primitivein, operands, operands_len, isref=False):
self.isdefined0 = False
self.isdefined1 = False
self.isdefined2 = False
self.tomem0 = ''
self.tomem1 = ''
self.tomem2 = ''
self.lvar += 1
for idx in range(len(operands)):
if [i in self.NUMSET for i in operands[idx]] == [True] * len(operands[idx]):
if idx == 0:
self.tomem0 = str(operands[idx])
elif idx == 1:
self.tomem1 = str(operands[idx])
elif idx == 2:
self.tomem2 = str(operands[idx])
indices = [i for i, x in enumerate(self.DATARAM_VALUE) if x == str(operands[idx]) and self.DATARAM_LBL[i][0:len(self.immvarprefix)] == self.immvarprefix]
if indices == []:
operands[idx] = self.immvarprefix + str(self.immvar)
self.immvar += 1
if idx == 0:
self.isdefined0 = True
elif idx == 1:
self.isdefined1 = True
elif idx == 2:
self.isdefined2 = True
else:
operands[idx] = self.DATARAM_LBL[indices[0]]
newprimitive = []
for primitive in primitivein:
if len(operands) >= 3:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
elif len(operands) == 2:
tmp = primitive.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
else:
tmp = primitive.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
newprimitive.append(tmp)
if isref == False:
if (len(operands) > 0):
if (operands[0] not in self.DATARAM_LBL) and (operands[0] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(operands[0])
if (self.isdefined0 == True):
self.DATARAM_VALUE.append(self.tomem0)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 1):
if (operands[1] not in self.DATARAM_LBL) and (operands[1] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(operands[1])
if (self.isdefined1 == True):
self.DATARAM_VALUE.append(self.tomem1)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 2):
if (operands[2] not in self.DATARAM_LBL) and (operands[2] not in self.BOOTSTRAP):
self.DATARAM_LBL.append(operands[2])
if (self.isdefined2 == True):
self.DATARAM_VALUE.append(self.tomem2)
else:
self.DATARAM_VALUE.append('0')
return newprimitive
def update_links_x86(self, primitivein, operands, operands_len, isref=False):
self.isdefined0 = False
self.isdefined1 = False
self.isdefined2 = False
self.isdefined3 = False
self.isdefined4 = False
self.tomem0 = ''
self.tomem1 = ''
self.tomem2 = ''
self.tomem3 = ''
self.tomem4 = ''
self.lvar += 1
for i in range(len(operands)):
try:
idata = int(operands[i])
except:
idata = -1
if idata > 0x7FFF:
sys.stdout.write(bcolors.WARNING + "Warning: " + bcolors.ENDC + "Immediate bigger than 0x7FFF, " + operands[i] + ". Killed to 0x7FFF. \n")
operands[i] = str(0x7FFF)
for idx in range(len(operands)):
if [i in self.NUMSET for i in operands[idx]] == [True] * len(operands[idx]):
if idx == 0:
self.tomem0 = str(operands[idx])
elif idx == 1:
self.tomem1 = str(operands[idx])
elif idx == 2:
self.tomem2 = str(operands[idx])
elif idx == 3:
self.tomem3 = str(operands[idx])
elif idx == 4:
self.tomem4 = str(operands[idx])
indices = [i for i, x in enumerate(self.DATARAM_VALUE) if x == str(operands[idx]) and self.DATARAM_LBL[i][0:len(self.immvarprefix)] == self.immvarprefix]
if indices == []:
operands[idx] = self.immvarprefix + str(self.immvar)
self.immvar += 1
if idx == 0:
self.isdefined0 = True
elif idx == 1:
self.isdefined1 = True
elif idx == 2:
self.isdefined2 = True
elif idx == 3:
self.isdefined3 = True
elif idx == 4:
self.isdefined4 = True
else:
operands[idx] = self.DATARAM_LBL[indices[0]]
newprimitive = []
for primitive in primitivein:
if len(operands) >= 5:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", operands[3])
tmp = tmp.replace("%5", operands[4])
tmp = tmp.replace("%6", str(self.lvar))
elif len(operands) >= 4:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", operands[3])
tmp = tmp.replace("%5", str(self.lvar))
elif len(operands) >= 3:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
elif len(operands) == 2:
tmp = primitive.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
else:
tmp = primitive.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
newprimitive.append(tmp)
if isref == False:
if (len(operands) > 0):
if (operands[0] not in self.DATARAM_LBL) and (operands[0] not in self.BOOTSTRAP) and (operands[0][0:4] != 'l___') and (operands[0][0] != '_'):
self.DATARAM_LBL.append(operands[0])
if (self.isdefined0 == True):
self.DATARAM_VALUE.append(self.tomem0)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 1):
if (operands[1] not in self.DATARAM_LBL) and (operands[1] not in self.BOOTSTRAP) and (operands[1][0:4] != 'l___') and (operands[1][0] != '_'):
self.DATARAM_LBL.append(operands[1])
if (self.isdefined1 == True):
self.DATARAM_VALUE.append(self.tomem1)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 2):
if (operands[2] not in self.DATARAM_LBL) and (operands[2] not in self.BOOTSTRAP) and (operands[2][0:4] != 'l___') and (operands[2][0] != '_'):
self.DATARAM_LBL.append(operands[2])
if (self.isdefined2 == True):
self.DATARAM_VALUE.append(self.tomem2)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 3):
if (operands[3] not in self.DATARAM_LBL) and (operands[3] not in self.BOOTSTRAP) and (operands[3][0:4] != 'l___') and (operands[3][0] != '_'):
self.DATARAM_LBL.append(operands[3])
if (self.isdefined3 == True):
self.DATARAM_VALUE.append(self.tomem3)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 4):
if (operands[4] not in self.DATARAM_LBL) and (operands[4] not in self.BOOTSTRAP) and (operands[4][0:4] != 'l___') and (operands[4][0] != '_'):
self.DATARAM_LBL.append(operands[4])
if (self.isdefined4 == True):
self.DATARAM_VALUE.append(self.tomem4)
else:
self.DATARAM_VALUE.append('0')
return newprimitive
def update_links_arm(self, primitivein, operands, operands_len, isref=False):
self.isdefined0 = False
self.isdefined1 = False
self.isdefined2 = False
self.isdefined3 = False
self.isdefined4 = False
self.isdefined5 = False
self.tomem0 = ''
self.tomem1 = ''
self.tomem2 = ''
self.tomem3 = ''
self.tomem4 = ''
self.tomem5 = ''
self.lvar += 1
for i in range(len(operands)):
try:
idata = int(operands[i])
except:
idata = -1
if idata > 0x7FFF:
sys.stdout.write(bcolors.WARNING + "Warning: " + bcolors.ENDC + "Immediate bigger than 0x7FFF, " + operands[i] + ". Killed to 0x7FFF. \n")
operands[i] = str(0x7FFF)
for idx in range(len(operands)):
if [i in self.NUMSET for i in operands[idx]] == [True] * len(operands[idx]):
if idx == 0:
self.tomem0 = str(operands[idx])
elif idx == 1:
self.tomem1 = str(operands[idx])
elif idx == 2:
self.tomem2 = str(operands[idx])
elif idx == 3:
self.tomem3 = str(operands[idx])
elif idx == 4:
self.tomem4 = str(operands[idx])
elif idx == 5:
self.tomem5 = str(operands[idx])
indices = [i for i, x in enumerate(self.DATARAM_VALUE) if x == str(operands[idx]) and self.DATARAM_LBL[i][0:len(self.immvarprefix)] == self.immvarprefix]
if indices == []:
operands[idx] = self.immvarprefix + str(self.immvar)
self.immvar += 1
if idx == 0:
self.isdefined0 = True
elif idx == 1:
self.isdefined1 = True
elif idx == 2:
self.isdefined2 = True
elif idx == 3:
self.isdefined3 = True
elif idx == 4:
self.isdefined4 = True
elif idx == 5:
self.isdefined5 = True
else:
operands[idx] = self.DATARAM_LBL[indices[0]]
newprimitive = []
for primitive in primitivein:
if len(operands) >= 6:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", operands[3])
tmp = tmp.replace("%5", operands[4])
tmp = tmp.replace("%6", operands[5])
tmp = tmp.replace("%7", str(self.lvar))
elif len(operands) >= 5:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", operands[3])
tmp = tmp.replace("%5", operands[4])
tmp = tmp.replace("%6", str(self.lvar))
elif len(operands) >= 4:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", operands[3])
tmp = tmp.replace("%5", str(self.lvar))
elif len(operands) >= 3:
tmp = primitive.replace("%3", operands[2])
tmp = tmp.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
elif len(operands) == 2:
tmp = primitive.replace("%2", operands[1])
tmp = tmp.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
else:
tmp = primitive.replace("%1", operands[0])
tmp = tmp.replace("%4", str(self.lvar))
newprimitive.append(tmp)
if isref == False:
if (len(operands) > 0):
if (operands[0] not in self.DATARAM_LBL) and (operands[0] not in self.BOOTSTRAP) and (operands[0][0:4] != 'l___') and (operands[0][0:2] != 'LC') and (operands[0][0:3] != '.LC'):
self.DATARAM_LBL.append(operands[0])
if (self.isdefined0 == True):
self.DATARAM_VALUE.append(self.tomem0)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 1):
if (operands[1] not in self.DATARAM_LBL) and (operands[1] not in self.BOOTSTRAP) and (operands[1][0:4] != 'l___') and (operands[1][0:2] != 'LC') and (operands[1][0:3] != '.LC'):
self.DATARAM_LBL.append(operands[1])
if (self.isdefined1 == True):
self.DATARAM_VALUE.append(self.tomem1)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 2):
if (operands[2] not in self.DATARAM_LBL) and (operands[2] not in self.BOOTSTRAP) and (operands[2][0:4] != 'l___') and (operands[2][0:2] != 'LC') and (operands[2][0:3] != '.LC'):
self.DATARAM_LBL.append(operands[2])
if (self.isdefined2 == True):
self.DATARAM_VALUE.append(self.tomem2)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 3):
if (operands[3] not in self.DATARAM_LBL) and (operands[3] not in self.BOOTSTRAP) and (operands[3][0:4] != 'l___') and (operands[3][0:2] != 'LC') and (operands[3][0:3] != '.LC'):
self.DATARAM_LBL.append(operands[3])
if (self.isdefined3 == True):
self.DATARAM_VALUE.append(self.tomem3)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 4):
if (operands[4] not in self.DATARAM_LBL) and (operands[4] not in self.BOOTSTRAP) and (operands[4][0:4] != 'l___') and (operands[4][0:2] != 'LC') and (operands[4][0:3] != '.LC'):
self.DATARAM_LBL.append(operands[4])
if (self.isdefined4 == True):
self.DATARAM_VALUE.append(self.tomem4)
else:
self.DATARAM_VALUE.append('0')
if (len(operands) > 5):
if (operands[5] not in self.DATARAM_LBL) and (operands[5] not in self.BOOTSTRAP) and (operands[5][0:4] != 'l___') and (operands[5][0:2] != 'LC') and (operands[5][0:3] != '.LC'):
self.DATARAM_LBL.append(operands[5])
if (self.isdefined5 == True):
self.DATARAM_VALUE.append(self.tomem5)
else:
self.DATARAM_VALUE.append('0')
return newprimitive
def push_initial_vars(self):
self.DATARAM_LBL.append('$sp')
self.DATARAM_VALUE.append(self.sp_offset)
def push_initial_vars_riscv32(self):
self.DATARAM_LBL.append('sp')
self.DATARAM_VALUE.append(self.sp_offset)
def push_initial_vars_arm(self):
self.DATARAM_LBL.append('sp')
self.DATARAM_VALUE.append(self.sp_offset)
self.DATARAM_LBL.append('lr')
self.DATARAM_VALUE.append(self.lr_offset)
def push_initial_vars_x86(self):
self.DATARAM_LBL.append('esp')
self.DATARAM_VALUE.append(self.esp_offset)
self.DATARAM_LBL.append('isp')
self.DATARAM_VALUE.append(self.isp_offset)
self.DATARAM_LBL.append('es')
self.DATARAM_VALUE.append(self.es_offset)
def translate(self, filename="t0.arch", fileout="t0.asm", llvm_cc='fast'):
if self.intermediate == self._MIPSEL:
self.compile_mips(filename=filename, fileout=fileout)
if self.intermediate == self._X86:
self.compile_x86(filename=filename, fileout=fileout)
if self.intermediate == self._ARM:
self.compile_arm(filename=filename, fileout=fileout)
if self.intermediate == self._RISCV32:
self.compile_riscv32(filename=filename, fileout=fileout)
if self.intermediate == self._LL:
self.compile_llvm(filename=filename, fileout=fileout, cc=llvm_cc)
def llvm_adjust_line(self, linein):
newline = linein
newline = re.sub(r"^\s+|\s+$", "", newline)
newline = newline.replace('\n',"")
newline = newline.replace('\r',"")
return newline
def llvm_compact_generics(self, token):
ntoken = []
ingeneric = False
inGlobal = False
chars = ""
for i in range(len(token)):
if token[i][0] == self.LLVM_GENERICS_MANDATORY_START and token[i][len(token[i])-1] != self.LLVM_GENERICS_MANDATORY_END and token[i][len(token[i])-2] != self.LLVM_GENERICS_MANDATORY_END:
ingeneric = True
elif (token[i][0] != self.LLVM_GENERICS_MANDATORY_START) and (token[i][len(token[i])-1] == self.LLVM_GENERICS_MANDATORY_END):
chars += token[i]
ntoken.append(chars)
ingeneric = False
chars = ""
else:
ntoken.append(token[i])
if ingeneric == True:
chars += token[i] + " "
return ntoken
@dataclass
class LLVM_IR:
name: ['']
positional_required: ['']
leftmost: False
required: ['']
positional_name: ['']
actual_values: ['']
def llvm_lexer_initialize(self):
self.LLVM_LEXER_MTYPE = []
self.LLVM_LEXER_OTYPE = []
self.LLVM_LEX = []
self.llvm_initialize_functend()
def llvm_lexer_populate(self, token):
#m = re.findall('\[(.+?)\]', text)
required = []
positional_required = []
positional_name = []
leftmost = False
name = []
chars = ""
position = 0
isvar = False
if token == []:
return
if token[1] == self.LLVM_ASSIGN:
leftmost = True
else:
leftmost = False
if len(token) > 2:
if token[2] == self.LLVM_ASSIGN:
leftmost = True
for i in range(len(token)):
if token[i][0] == self.LLVM_GENERICS_MANDATORY_START and (token[i][len(token[i])-1] == self.LLVM_GENERICS_MANDATORY_END or token[i][len(token[i])-2] == self.LLVM_GENERICS_MANDATORY_END) or self.LLVM_GLOBAL == token[i][0] or self.LLVM_ARB == token[i][0]:
required.append(token[i])
positional_required.append(position)
#position += 1
elif not self.llvm_is_delimiter(token[i]) and token[i] != self.LLVM_PTR and token[i] != self.LLVM_ASSIGN and self.LLVM_GLOBAL != token[i][0]:
#if name == "":
name.append(token[i])
positional_name.append(position)
#else:
# name += " " + token[i]
elif self.llvm_is_delimiter(token[i]) and token[i] != self.LLVM_ASSIGN and token[i] != self.LLVM_PTR:
required.append(token[i])
positional_required.append(position)
if token[i][0] == self.LLVM_ARB:
name.append(token[i])
positional_name.append(position)
position += 1
actual = [''] * len(required)
self.LLVM_LEX.append(self.LLVM_IR(name=name, required=required, positional_required=positional_required, leftmost=leftmost, positional_name=positional_name, actual_values=actual))
def llvm_load_commands(self):
try:
self.llvm_lexer_initialize()
self.primitives = os.listdir(self.primitive_directory + "/" + self.intermediate)
i = 0
L = len(self.primitives)
while i < (L):
if self.primitives[i][0] == '.':
self.primitives.remove(self.primitives[i])
i += 1
L = len(self.primitives)
for primitive in self.primitives:
fp = open(self.primitive_directory + "/" + self.intermediate + '/' + primitive,'r')
while True:
rawline = fp.readline()
if rawline != "" and rawline != "#":
line = self.llvm_adjust_line(rawline)
token = self.llvm_token(line)
token = self.llvm_remove_comments(token)
token = self.llvm_compact_generics(token)
self.llvm_lexer_populate(token)
#print("TOKEN: ", token)
else:
break
fp.close()
#for i in range(len(self.LLVM_LEX)):
# print(self.LLVM_LEX[i])
# print("")
except:
sys.stdout.write(bcolors.FAIL + "Error: " + bcolors.ENDC + "Cannot load " + self.intermediate + " commands. Some of them may be missing.\n")
sys.exit(1)
def llvm_parse_left_toright(self, line):
chars = ""
newline = line
i = -1
if line != "":
for i in range(len(line)):
if self.llvm_isnot_blank(line[i]):
chars += line[i]
else:
break
newline=line[i+1:]
return chars, newline
def llvm_token_is_comment(self, data):
if data == self.LLVM_COMMENT:
return True
else:
return False
def llvm_remove_comments(self, token):
tokens = []
for i in range(len(token)):
if self.llvm_token_is_comment(token[i]):
break
else:
tokens.append(token[i])
return tokens
def llvm_token(self, line):
newline = line
tokenp = []
token = []
while newline != "":
t, newline = self.llvm_parse_left_toright(newline)
tokenp.append(t)
for i in range(len(tokenp)):
chars = ""
for j in range(len(tokenp[i])):
if self.llvm_is_delimiter(tokenp[i][j]):
if chars != "":
token.append(chars)
token.append(tokenp[i][j])
chars = ""
else:
chars += tokenp[i][j]
if chars != "":
token.append(chars)
return token
def llvm_isnot_blank(self,c):
if c == " " or c == "\t":
return False
else:
return True
def llvm_is_alphanum(self, c):
if (c.upper() in self.LLVM_NUMSET) or (c.upper() in self.LLVM_ALPHASET):
return True
else:
return False
def llvm_is_delimiter(self, c):
if c in self.LLVM_DELIMITSET:
return True
else:
return False
def llvm_print_lex(self):
for i in range(len(self.LLVM_LEX)):
sys.stdout.write("node name: " + self.LLVM_LEX[i].name +"\n")
sys.stdout.write("node most: " + self.LLVM_LEX[i].leftmost + "\n")
sys.stdout.write("positionals: " + self.LLVM_LEX[i].positional_required + "\n")
def llvm_print_lex_single(self, lex):
print("\tnode name:\t\t", lex.name)
print("\tnode name positionals:\t", lex.positional_name)
print("\tnode leftmost:\t\t", lex.leftmost)
print("\trequired positionals:\t", lex.positional_required)
print("\trequired:\t\t", lex.required)
print("\trequired actuals:\t", lex.actual_values)
def llvm_decode_instr(self, token):
if token == []:
return False
llvmtype = self.llvm_detect_type(token)
datac = []
if llvmtype == self.LLVM_iTYPE_LABEL:
datac = [i for idx, i in enumerate(self.LLVM_LEX) if self.LLVM_LEX[idx].name == ["label"]]
elif llvmtype == self.LLVM_iTYPE_LEFTMOST:
datac = [i for idx, i in enumerate(self.LLVM_LEX) if self.LLVM_LEX[idx].leftmost == True]
elif llvmtype == self.LLVM_iTYPE_RIGHTMOST:
datac = [i for idx, i in enumerate(self.LLVM_LEX) if self.LLVM_LEX[idx].leftmost == False]
elif llvmtype == self.LLVM_iTYPE_FUNCTEND:
datac = [i for idx, i in enumerate(self.LLVM_LEX) if self.LLVM_LEX[idx].name == [self.LLVM_FUNCTEND]]
if len(datac) == 1:
#sys.stdout.write("decoded instruction: \n")
actual_null = [str(token[0])] #[''] * len(datac[0].required)
newdatac = self.LLVM_IR(name=datac[0].name, required=datac[0].required, positional_required=datac[0].positional_required, leftmost=datac[0].leftmost, positional_name=datac[0].positional_name, actual_values=actual_null)
self.LLVM_I.append(newdatac)
#self.llvm_print_lex_single(self.LLVM_I[len(self.LLVM_I)-1])
return True
elif len(datac) > 1:
i = 0
while (i < (len(datac))):
found = True
foundR = False
enterR = False
j = 0
#print("DATAC: ", datac[i])
#print("TOKEN; ", token)
while (j < (len(datac[i].name))):
if datac[i].name[j] != '$':
if datac[i].positional_name[j] < len(token):
if datac[i].name[j] != token[datac[i].positional_name[j]]:
found = False
break
else:
found = False
break
else:
enterR = True
if j == len(datac[i].name)-1:
found = True
break
r = j+1
k = datac[i].positional_name[j]
foundR = False
while k < len(token):
if datac[i].name[r] == "$":
foundR = True
break
elif token[k] == datac[i].name[r]:
foundR = True
k += 1
j += 1
if enterR == True and foundR == False:
found = False
break
if foundR == True:
found = True
break
if found == True:
break
i += 1
if found:
#sys.stdout.write("decoded instruction: \n")
actual_values = []
j = 0
offset = 0
while j < len(datac[i].required):
#for j in range(len(datac[i].required)):
if datac[i].required[j] == "$":
k = datac[i].positional_required[j]
initial = k + 1
arb = []
while k < len(token):
if token[k] != datac[i].required[j+1]:
arb.append(token[k])
else:
#arb.append(token[k])
offset = k - initial
j += 1
break
k += 1
actual_values.append(arb)
actual_values.append(token[k])
else:
#if datac[i].positional_name[datac[i].positional_required[i]+1
actual_values.append(token[datac[i].positional_required[j]+offset])
j += 1
datac[i].actual_values = actual_values
newdatac = self.LLVM_IR(name=datac[i].name, required=datac[i].required, positional_required=datac[i].positional_required, leftmost=datac[i].leftmost, positional_name=datac[i].positional_name, actual_values=actual_values)
self.LLVM_I.append(newdatac)
#self.llvm_print_lex_single(datac[i])
#self.llvm_print_lex_single(self.LLVM_I[len(self.LLVM_I)-1])
return True
else:
return False
@dataclass
class LLVM_F:
Function: ""
FunctionAllocs: [[""]]
FunctionMaps:[""]
FunctionIns: [""]
FunctionOuts: [""]
FunctionType: [""]
def llvm_push_dram(self, label, value):
if label not in self.LLVM_DRAM:
self.LLVM_DRAM.append(label)
self.LLVM_DRAM_VALUE.append(str(value))
def llvm_push_immediate_dram(self, value):
immediates = []
values = []
for i in range(len(self.LLVM_DRAM)):
if self.LLVM_DRAM[i][0:4] == "imm.":
immediates.append(self.LLVM_DRAM[i])
values.append(self.LLVM_DRAM_VALUE[i])
if str(value) in values:
return immediates[values.index(str(value))]
label = self.LLVM_CONST + str(self.immediate)
self.LLVM_DRAM.append(label)
self.LLVM_DRAM_VALUE.append(str(value))
self.immediate += 1
return label
def llvm_call_retrieve_operands(self, args, thisfunc_index):
operands = []
for i in range(len(args)):
if args[i][0] == "%":
op0 = self.LLVM_WRITER_VAR + args[i][1:] + self.LLVM_WRITER_UNDERSCORE + self.LLVM_FUNC[thisfunc_index].Function[1:]
self.llvm_push_dram(op0, 0)
elif args[i][0] == "@":
op0 = self.LLVM_WRITER_PTR+self.LLVM_WRITER_GLOBAL+args[i][1:]
else:
newimmediate = self.llvm_push_immediate_dram(args[i])
op0 = newimmediate
operands.append(op0)
return operands
def llvm_probe_operands(self, bases, thisfunc_index, index):
lbases = len(bases)
if lbases < 1:
return None
op0 = ""
op1 = ""
op2 = ""
op3 = ""
op0_inAllocs = False
op1_inAllocs = False
op2_inAllocs = False
op3_inAllocs = False
BASE0 = bases[0]
if lbases >= 2:
BASE1 = bases[1]
if lbases >= 3:
BASE2 = bases[2]
if lbases== 4:
BASE3 = bases[3]
if self.LLVM_I[index].actual_values[BASE0] in self.LLVM_FUNC[thisfunc_index].FunctionAllocs:
op0_inAllocs = True
if lbases >= 2:
if self.LLVM_I[index].actual_values[BASE1] in self.LLVM_FUNC[thisfunc_index].FunctionAllocs:
op1_inAllocs = True
if lbases >= 3:
if self.LLVM_I[index].actual_values[BASE2] in self.LLVM_FUNC[thisfunc_index].FunctionAllocs:
op2_inAllocs = True
if lbases == 4:
if self.LLVM_I[index].actual_values[BASE3] in self.LLVM_FUNC[thisfunc_index].FunctionAllocs:
op3_inAllocs = True
if self.LLVM_I[index].actual_values[BASE0][0] == "%":
op0 = self.LLVM_WRITER_VAR + self.LLVM_I[index].actual_values[BASE0][1:] + self.LLVM_WRITER_UNDERSCORE + self.LLVM_FUNC[thisfunc_index].Function[1:]
self.llvm_push_dram(op0, 0)
elif self.LLVM_I[index].actual_values[BASE0][0] == "@":
op0 = self.LLVM_WRITER_PTR+self.LLVM_WRITER_GLOBAL+self.LLVM_I[index].actual_values[BASE0][1:]
else:
newimmediate = self.llvm_push_immediate_dram(self.LLVM_I[index].actual_values[BASE0])
op0 = newimmediate
if lbases >= 2:
if op1_inAllocs:
#print(self.LLVM_FUNC[thisfunc_index].FunctionMaps)
#print(self.LLVM_FUNC[thisfunc_index].FunctionAllocs)
offset = int(self.LLVM_FUNC[thisfunc_index].FunctionMaps[int(self.LLVM_FUNC[thisfunc_index].FunctionAllocs.index(self.LLVM_I[index].actual_values[BASE1]))])
newimmediate = self.llvm_push_immediate_dram(offset)
op1 = newimmediate
elif not op1_inAllocs:
if self.LLVM_I[index].actual_values[BASE1][0] == "@":
op1 = self.LLVM_WRITER_PTR+self.LLVM_WRITER_GLOBAL+self.LLVM_I[index].actual_values[BASE1][1:]
elif self.LLVM_I[index].actual_values[BASE1][0] == "%":
op1 = self.LLVM_WRITER_VAR + self.LLVM_I[index].actual_values[BASE1][1:] + self.LLVM_WRITER_UNDERSCORE + self.LLVM_FUNC[thisfunc_index].Function[1:]
self.llvm_push_dram(op1, 0)
else:
newimmediate = self.llvm_push_immediate_dram(self.LLVM_I[index].actual_values[BASE1])
op1 = newimmediate
if lbases >= 3:
if op2_inAllocs:
#print(self.LLVM_FUNC[thisfunc_index].FunctionMaps)
#print(self.LLVM_FUNC[thisfunc_index].FunctionAllocs)
offset = int(self.LLVM_FUNC[thisfunc_index].FunctionMaps[int(self.LLVM_FUNC[thisfunc_index].FunctionAllocs.index(self.LLVM_I[index].actual_values[BASE2]))])
newimmediate = self.llvm_push_immediate_dram(offset)
op2 = newimmediate
elif not op2_inAllocs:
if self.LLVM_I[index].actual_values[BASE2][0] == "@":
op2 = self.LLVM_WRITER_PTR+self.LLVM_WRITER_GLOBAL+self.LLVM_I[index].actual_values[BASE2][1:]
elif self.LLVM_I[index].actual_values[BASE2][0] == "%":
op2 = self.LLVM_WRITER_VAR + self.LLVM_I[index].actual_values[BASE2][1:] + self.LLVM_WRITER_UNDERSCORE + self.LLVM_FUNC[thisfunc_index].Function[1:]