diff --git a/Documentation/04_Connecting_Module_Docs/00_Top_Level.md b/Documentation/04_Connecting_Module_Docs/00_Top_Level.md index 651dc7d..61aacee 100644 --- a/Documentation/04_Connecting_Module_Docs/00_Top_Level.md +++ b/Documentation/04_Connecting_Module_Docs/00_Top_Level.md @@ -1,3 +1,5 @@ +THIS OUTLINE IS INCOMPLETE + # Top Level Module # ## Contents diff --git a/Documentation/04_Connecting_Module_Docs/01_Instruction_Cache.md b/Documentation/04_Connecting_Module_Docs/01_Instruction_Cache.md index ec3ba8d..7371341 100644 --- a/Documentation/04_Connecting_Module_Docs/01_Instruction_Cache.md +++ b/Documentation/04_Connecting_Module_Docs/01_Instruction_Cache.md @@ -1,7 +1,7 @@ THIS OUTLINE IS INCOMPLETE # Instruction Cache # -(Verilog module known as Conn_Instruction_Cache) +(Verilog module known as Con_Instruction_Cache) ## Contents * [Inputs](#inputs) @@ -17,11 +17,18 @@ THIS OUTLINE IS INCOMPLETE |```cache_clk```|1-bit| |```rstn```|1-bit| |```pc```|32-bit| +|```mem_response_data```|32-bit| +|```mem_busy```|1-bit| ## Outputs |Name|Bits wide| |:---|:---:| |```ins```|32-bit| +|```wEn```|1-bit| +|```rEn```|1-bit| +|```isBurst```|1-bit| +|```mem_address```|32-bit| +|```mem_write_data```|32-bit| ## Modules diff --git a/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md b/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md index 360467a..bda0eec 100644 --- a/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md +++ b/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md @@ -1,3 +1,5 @@ +THIS OUTLINE IS INCOMPLETE + # IF Connection Module # (Verilog module known as Con_IF) @@ -59,11 +61,19 @@ |:---:|:---:| |```cache_clk```|1-bit| |```rstn```|1-bit| +|```mem_response_data```|32-bit| +|```mem_busy```|1-bit| ##### External Outputs |Name|Bits wide| |:---:|:---:| |```ins```|32-bit| +|```ins```|32-bit| +|```wEn```|1-bit| +|```rEn```|1-bit| +|```isBurst```|1-bit| +|```mem_address```|32-bit| +|```mem_write_data```|32-bit| #### Internal IO