diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h
index 423adfdb1d2..d2c4f0e74f0 100644
--- a/core/arch/arm/include/arm64.h
+++ b/core/arch/arm/include/arm64.h
@@ -288,6 +288,11 @@ static inline __noprof void dsb_ishst(void)
 	asm volatile ("dsb ishst" : : : "memory");
 }
 
+static inline __noprof void dsb_osh(void)
+{
+	asm volatile ("dsb osh" : : : "memory");
+}
+
 static inline __noprof void sev(void)
 {
 	asm volatile ("sev" : : : "memory");
diff --git a/core/drivers/crypto/caam/utils/utils_dmaobj.c b/core/drivers/crypto/caam/utils/utils_dmaobj.c
index 04f912202a7..384f0306327 100644
--- a/core/drivers/crypto/caam/utils/utils_dmaobj.c
+++ b/core/drivers/crypto/caam/utils/utils_dmaobj.c
@@ -537,7 +537,7 @@ static TEE_Result check_buffer_boundary(struct caamdmaobj *obj,
 
 	for (idx = 0; idx < nb_pa_area && remlen; idx++) {
 		DMAOBJ_TRACE("Remaining length = %zu", remlen);
-		if (ADD_OVERFLOW(pabufs[idx].paddr, pabufs[idx].length,
+		if ((pabufs[idx].paddr, pabufs[idx].length,
 				 &last_pa))
 			goto out;
 
diff --git a/core/drivers/crypto/hisilicon/hisi_qm.c b/core/drivers/crypto/hisilicon/hisi_qm.c
index 2c658232c3a..caeeeec8071 100644
--- a/core/drivers/crypto/hisilicon/hisi_qm.c
+++ b/core/drivers/crypto/hisilicon/hisi_qm.c
@@ -138,7 +138,7 @@ static void qm_db(struct hisi_qm *qm, uint16_t qn, uint8_t cmd, uint16_t index,
 	io_write64(qm->io_base + QM_DOORBELL_SQ_CQ_BASE, doorbell);
 }
 
-static int32_t qm_wait_mb_ready(struct hisi_qm *qm)
+static TEE_Result qm_wait_mb_ready(struct hisi_qm *qm)
 {
 	uint32_t val = 0;
 
@@ -163,7 +163,7 @@ static void qm_mb_write(struct hisi_qm *qm, void *src)
 	dsb();
 }
 
-static int32_t qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr,
+static TEE_Result qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr,
 		     uint16_t qn, uint8_t op)
 {
 	struct qm_mailbox mb = { };
@@ -176,14 +176,14 @@ static int32_t qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr,
 
 	if (qm_wait_mb_ready(qm)) {
 		EMSG("QM mailbox is busy");
-		return -HISI_QM_DRVCRYPT_EBUSY;
+		return HISI_QM_DRVCRYPT_EBUSY;
 	}
 
 	qm_mb_write(qm, &mb);
 
 	if (qm_wait_mb_ready(qm)) {
 		EMSG("QM mailbox operation timeout");
-		return -HISI_QM_DRVCRYPT_EBUSY;
+		return HISI_QM_DRVCRYPT_EBUSY;
 	}
 
 	return HISI_QM_DRVCRYPT_NO_ERR;
@@ -215,11 +215,11 @@ static void qm_cfg_vft_data(struct hisi_qm *qm, uint8_t vft_type,
 	io_write32(qm->io_base + QM_VFT_CFG_DATA_H, data_h);
 }
 
-static int32_t qm_set_vft_common(struct hisi_qm *qm, uint8_t vft_type,
+static TEE_Result qm_set_vft_common(struct hisi_qm *qm, uint8_t vft_type,
 				 uint32_t function, uint32_t base, uint32_t num)
 {
 	uint32_t val = 0;
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
 					 val & QM_FVT_CFG_RDY_BIT, POLL_PERIOD,
@@ -241,15 +241,15 @@ static int32_t qm_set_vft_common(struct hisi_qm *qm, uint8_t vft_type,
 					  POLL_TIMEOUT);
 }
 
-static int32_t qm_set_xqc_vft(struct hisi_qm *qm, uint32_t function,
+static TEE_Result qm_set_xqc_vft(struct hisi_qm *qm, uint32_t function,
 			      uint32_t base, uint32_t num)
 {
-	int32_t ret = 0;
+	uint32_t ret = 0;
 	int32_t i = 0;
 
 	if (!num) {
 		EMSG("Invalid sq num");
-		return -HISI_QM_DRVCRYPT_EINVAL;
+		return HISI_QM_DRVCRYPT_EINVAL;
 	}
 
 	for (i = QM_SQC_VFT; i <= QM_CQC_VFT; i++) {
@@ -263,10 +263,10 @@ static int32_t qm_set_xqc_vft(struct hisi_qm *qm, uint32_t function,
 	return HISI_QM_DRVCRYPT_NO_ERR;
 }
 
-static int32_t qm_get_vft(struct hisi_qm *qm, uint32_t *base, uint32_t *num)
+static TEE_Result qm_get_vft(struct hisi_qm *qm, uint32_t *base, uint32_t *num)
 {
 	uint64_t sqc_vft = 0;
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	ret = qm_mb(qm, QM_MB_CMD_SQC_VFT, 0, 0, QM_MB_OP_RD);
 	if (ret)
@@ -287,24 +287,24 @@ static void qp_memory_uninit(struct hisi_qm *qm, uint32_t id)
 	free(qp->cqe);
 }
 
-static int32_t qp_memory_init(struct hisi_qm *qm, uint32_t id)
+static TEE_Result qp_memory_init(struct hisi_qm *qm, uint32_t id)
 {
 	size_t sq_size = qm->sqe_size * HISI_QM_Q_DEPTH;
 	size_t cq_size = sizeof(struct qm_cqe) * HISI_QM_Q_DEPTH;
 	struct hisi_qp *qp = &qm->qp_array[id];
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	qp->sqe = memalign(HISI_QM_ALIGN128, sq_size);
 	if (!qp->sqe) {
 		EMSG("Fail to malloc sq[%"PRIu32"]", id);
-		return -HISI_QM_DRVCRYPT_ENOMEM;
+		return HISI_QM_DRVCRYPT_ENOMEM;
 	}
 	qp->sqe_dma = virt_to_phys(qp->sqe);
 	assert(qp->sqe_dma);
 	qp->cqe = memalign(HISI_QM_ALIGN32, cq_size);
 	if (!qp->cqe) {
 		EMSG("Fail to malloc cq[%"PRIu32"]", id);
-		ret = -HISI_QM_DRVCRYPT_ENOMEM;
+		ret = HISI_QM_DRVCRYPT_ENOMEM;
 		goto free_sqe;
 	}
 	qp->cqe_dma = virt_to_phys(qp->cqe);
@@ -331,12 +331,13 @@ static void qm_memory_uninit(struct hisi_qm *qm)
 	free(qm->cqc);
 }
 
-static int32_t qm_memory_init(struct hisi_qm *qm)
+static TEE_Result qm_memory_init(struct hisi_qm *qm)
 {
 	size_t sqc_size = 0;
 	size_t cqc_size = 0;
 	size_t qp_size = 0;
-	int32_t j, ret;
+	int32_t j = 0;
+	uint32_t ret = 0;
 	uint32_t i;
 
 	sqc_size = sizeof(struct qm_sqc) * qm->qp_num;
@@ -346,14 +347,14 @@ static int32_t qm_memory_init(struct hisi_qm *qm)
 	qm->sqc = memalign(HISI_QM_ALIGN32, sqc_size);
 	if (!qm->sqc) {
 		EMSG("Fail to malloc sqc");
-		return -HISI_QM_DRVCRYPT_ENOMEM;
+		return HISI_QM_DRVCRYPT_ENOMEM;
 	}
 	qm->sqc_dma = virt_to_phys(qm->sqc);
 	assert(qm->sqc_dma);
 	qm->cqc = memalign(HISI_QM_ALIGN32, cqc_size);
 	if (!qm->cqc) {
 		EMSG("Fail to malloc cqc");
-		ret = -HISI_QM_DRVCRYPT_ENOMEM;
+		ret = HISI_QM_DRVCRYPT_ENOMEM;
 		goto free_sqc;
 	}
 	qm->cqc_dma = virt_to_phys(qm->cqc);
@@ -362,14 +363,14 @@ static int32_t qm_memory_init(struct hisi_qm *qm)
 	qm->qp_array = (struct hisi_qp *)malloc(qp_size);
 	if (!qm->qp_array) {
 		EMSG("Fail to malloc qp_array");
-		ret = -HISI_QM_DRVCRYPT_ENOMEM;
+		ret = HISI_QM_DRVCRYPT_ENOMEM;
 		goto free_cqc;
 	}
 
 	for (i = 0; i < qm->qp_num; i++) {
 		ret = qp_memory_init(qm, i);
 		if (ret) {
-			ret = -HISI_QM_DRVCRYPT_ENOMEM;
+			ret = HISI_QM_DRVCRYPT_ENOMEM;
 			goto free_qp_mem;
 		}
 	}
@@ -387,9 +388,9 @@ static int32_t qm_memory_init(struct hisi_qm *qm)
 	return ret;
 }
 
-int32_t hisi_qm_init(struct hisi_qm *qm)
+TEE_Result hisi_qm_init(struct hisi_qm *qm)
 {
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	if (qm->fun_type == HISI_QM_HW_VF) {
 		ret = qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
@@ -401,7 +402,7 @@ int32_t hisi_qm_init(struct hisi_qm *qm)
 
 	if (qm->qp_num == 0 || qm->sqe_size == 0) {
 		EMSG("Invalid qm parameters");
-		return -HISI_QM_DRVCRYPT_EINVAL;
+		return HISI_QM_DRVCRYPT_EINVAL;
 	}
 
 	ret = qm_memory_init(qm);
@@ -434,7 +435,7 @@ void hisi_qm_uninit(struct hisi_qm *qm)
 	mutex_destroy(&qm->qp_lock);
 }
 
-static int32_t qm_hw_mem_reset(struct hisi_qm *qm)
+static TEE_Result qm_hw_mem_reset(struct hisi_qm *qm)
 {
 	uint32_t val = 0;
 
@@ -445,20 +446,20 @@ static int32_t qm_hw_mem_reset(struct hisi_qm *qm)
 					  POLL_TIMEOUT);
 }
 
-static int32_t qm_func_vft_cfg(struct hisi_qm *qm)
+static TEE_Result qm_func_vft_cfg(struct hisi_qm *qm)
 {
 	uint32_t q_base = qm->qp_num;
 	uint32_t act_q_num = 0;
 	uint32_t i = 0;
 	uint32_t j = 0;
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	if (qm->vfs_num == 0)
 		return HISI_QM_DRVCRYPT_NO_ERR;
 
 	if (qm->vfs_num > HISI_QM_MAX_VFS_NUM) {
 		EMSG("Invalid QM vfs_num");
-		return -HISI_QM_DRVCRYPT_EINVAL;
+		return HISI_QM_DRVCRYPT_EINVAL;
 	}
 
 	for (i = 1; i <= qm->vfs_num; i++) {
@@ -475,9 +476,9 @@ static int32_t qm_func_vft_cfg(struct hisi_qm *qm)
 	return HISI_QM_DRVCRYPT_NO_ERR;
 }
 
-int32_t hisi_qm_start(struct hisi_qm *qm)
+TEE_Result hisi_qm_start(struct hisi_qm *qm)
 {
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	if (qm->fun_type == HISI_QM_HW_PF) {
 		ret = qm_hw_mem_reset(qm);
@@ -542,7 +543,7 @@ void hisi_qm_dev_init(struct hisi_qm *qm)
 		   HISI_QM_ABNML_INT_MASK_CFG);
 }
 
-static int32_t qm_sqc_cfg(struct hisi_qp *qp)
+static TEE_Result qm_sqc_cfg(struct hisi_qp *qp)
 {
 	struct hisi_qm *qm = qp->qm;
 	struct qm_sqc *sqc = NULL;
@@ -551,7 +552,7 @@ static int32_t qm_sqc_cfg(struct hisi_qp *qp)
 
 	sqc = memalign(HISI_QM_ALIGN32, sizeof(struct qm_sqc));
 	if (!sqc)
-		return -HISI_QM_DRVCRYPT_ENOMEM;
+		return HISI_QM_DRVCRYPT_ENOMEM;
 
 	sqc_dma = virt_to_phys(sqc);
 	assert(sqc_dma);
@@ -571,7 +572,7 @@ static int32_t qm_sqc_cfg(struct hisi_qp *qp)
 	return ret;
 }
 
-static int32_t qm_cqc_cfg(struct hisi_qp *qp)
+static TEE_Result qm_cqc_cfg(struct hisi_qp *qp)
 {
 	struct hisi_qm *qm = qp->qm;
 	struct qm_cqc *cqc = NULL;
@@ -580,7 +581,7 @@ static int32_t qm_cqc_cfg(struct hisi_qp *qp)
 
 	cqc = memalign(HISI_QM_ALIGN32, sizeof(struct qm_cqc));
 	if (!cqc)
-		return -HISI_QM_DRVCRYPT_ENOMEM;
+		return HISI_QM_DRVCRYPT_ENOMEM;
 
 	cqc_dma = virt_to_phys(cqc);
 	assert(cqc_dma);
@@ -666,15 +667,15 @@ static void qm_sq_tail_update(struct hisi_qp *qp)
  * One task thread will just bind to one hardware queue, and
  * hardware does not support msi. So we have no lock here.
  */
-int32_t hisi_qp_send(struct hisi_qp *qp, void *msg)
+TEE_Result hisi_qp_send(struct hisi_qp *qp, void *msg)
 {
 	struct hisi_qm *qm = NULL;
-	int32_t ret = 0;
+	uuint32_t ret = 0;
 	void *sqe = NULL;
 
 	if (!qp) {
 		EMSG("qp is NULL");
-		return -HISI_QM_DRVCRYPT_EINVAL;
+		return HISI_QM_DRVCRYPT_EINVAL;
 	}
 
 	qm = qp->qm;
@@ -710,11 +711,11 @@ static void qm_cq_head_update(struct hisi_qp *qp)
 }
 
 #define HISI_QM_RECV_DONE 1
-static int32_t hisi_qp_recv(struct hisi_qp *qp, void *msg)
+static TEE_Result hisi_qp_recv(struct hisi_qp *qp, void *msg)
 {
 	struct hisi_qm *qm = qp->qm;
 	struct qm_cqe *cqe = NULL;
-	int32_t ret = 0;
+	uint32_t ret = 0;
 	void *sqe = NULL;
 
 	ret = qm->dev_status_check(qm);
@@ -723,8 +724,7 @@ static int32_t hisi_qp_recv(struct hisi_qp *qp, void *msg)
 
 	cqe = qp->cqe + qp->cq_head;
 	if (QM_CQE_PHASE(cqe) == qp->cqc_phase) {
-		// TODO
-		__asm__ volatile("dmb osh");
+		dsb_osh();
 		sqe = (void *)((vaddr_t)qp->sqe + qm->sqe_size * cqe->sq_head);
 		ret = qp->parse_sqe(sqe, msg);
 		qm_cq_head_update(qp);
@@ -755,14 +755,14 @@ static void qm_dfx_dump(struct hisi_qm *qm)
 	}
 }
 
-int32_t hisi_qp_recv_sync(struct hisi_qp *qp, void *msg)
+TEE_Result hisi_qp_recv_sync(struct hisi_qp *qp, void *msg)
 {
 	uint32_t cnt = 0;
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	if (!qp) {
 		EMSG("qp is NULL");
-		return -HISI_QM_DRVCRYPT_EINVAL;
+		return HISI_QM_DRVCRYPT_EINVAL;
 	}
 
 	while (true) {
@@ -771,7 +771,7 @@ int32_t hisi_qp_recv_sync(struct hisi_qp *qp, void *msg)
 			if (++cnt > HISI_QM_RECV_SYNC_TIMEOUT) {
 				EMSG("qm recv task timeout");
 				qm_dfx_dump(qp->qm);
-				ret = -HISI_QM_DRVCRYPT_ETMOUT;
+				ret = HISI_QM_DRVCRYPT_ETMOUT;
 				break;
 			}
 		} else if (ret < 0) {
diff --git a/core/drivers/crypto/hisilicon/include/hisi_cipher.h b/core/drivers/crypto/hisilicon/include/hisi_cipher.h
index b8944ab3744..db941f1863f 100644
--- a/core/drivers/crypto/hisilicon/include/hisi_cipher.h
+++ b/core/drivers/crypto/hisilicon/include/hisi_cipher.h
@@ -46,7 +46,11 @@ enum C_MODE {
 
 static inline uint32_t multiple_round(uint32_t x, uint32_t y)
 {
-	return (x + y - 1) / y;
+	uint32_t res = 0;
+
+	assert(!ADD_OVERFLOW(x, y - 1, &res));
+
+	return res;
 }
 
 struct sec_cipher_ctx {
diff --git a/core/drivers/crypto/hisilicon/include/hisi_qm.h b/core/drivers/crypto/hisilicon/include/hisi_qm.h
index 7e3711c8b7a..9fb2f9cd1bf 100644
--- a/core/drivers/crypto/hisilicon/include/hisi_qm.h
+++ b/core/drivers/crypto/hisilicon/include/hisi_qm.h
@@ -5,7 +5,6 @@
 #ifndef __HISI_QM_H__
 #define __HISI_QM_H__
 
-#include <initcall.h>
 #include <io.h>
 #include <kernel/delay.h>
 #include <kernel/mutex.h>
@@ -140,8 +139,8 @@ struct hisi_qp {
 	paddr_t sqe_dma;
 	paddr_t cqe_dma;
 
-	int32_t (*fill_sqe)(void *sqe, void *msg);
-	int32_t (*parse_sqe)(void *sqe, void *msg);
+	TEE_Result (*fill_sqe)(void *sqe, void *msg);
+	TEE_Result (*parse_sqe)(void *sqe, void *msg);
 };
 
 struct hisi_qm {
@@ -164,7 +163,7 @@ struct hisi_qm {
 	struct hisi_qp *qp_array;
 	struct mutex qp_lock; /* protect the qp instance */
 
-	int32_t (*dev_status_check)(struct hisi_qm *qm);
+	TEE_Result (*dev_status_check)(struct hisi_qm *qm);
 };
 
 enum hisi_drv_status {
@@ -198,7 +197,7 @@ enum hisi_drv_status {
 		timeout += (_delay_us); \
 		udelay(_delay_us); \
 	} \
-	(flag) ? 0 : -HISI_QM_DRVCRYPT_ETMOUT; \
+	(flag) ? 0 : HISI_QM_DRVCRYPT_ETMOUT; \
 })
 
 struct acc_device {
@@ -220,9 +219,9 @@ void hisi_qm_get_version(struct hisi_qm *qm);
 /**
  *@Description: Init QM for Kunpeng drv
  *@param qm: Handle of Queue Management module
- *@return success: 0，fail: -HISI_QM_DRVCRYPT_EBUSY/HISI_QM_DRVCRYPT_EINVAL
+ *@return success: 0，fail: HISI_QM_DRVCRYPT_EBUSY/HISI_QM_DRVCRYPT_EINVAL
  */
-int32_t hisi_qm_init(struct hisi_qm *qm);
+TEE_Result hisi_qm_init(struct hisi_qm *qm);
 
 /**
  *@Description:deinit QM for Kunpeng drv
@@ -234,7 +233,7 @@ void hisi_qm_uninit(struct hisi_qm *qm);
  *@Description: Start QM for Kunpeng drv
  *@param qm: Handle of Queue Management module
  */
-int32_t hisi_qm_start(struct hisi_qm *qm);
+TEE_Result hisi_qm_start(struct hisi_qm *qm);
 
 /**
  *@Description: Config QM for Kunpeng drv
@@ -260,15 +259,15 @@ void hisi_qm_release_qp(struct hisi_qp *qp);
 /**
  *@Description: Send SQE(Submmision Queue Element) to Kunpeng dev
  *@param qm: Handle of Queue Management module
- *@return success: 0，fail: -HISI_QM_DRVCRYPT_EINVAL
+ *@return success: 0，fail: HISI_QM_DRVCRYPT_EINVAL
  */
-int32_t hisi_qp_send(struct hisi_qp *qp, void *msg);
+TEE_Result hisi_qp_send(struct hisi_qp *qp, void *msg);
 
 /**
  *@Description: Recevice result from Kunpeng dev
  *@param qm: Handle of Queue Management module
- *@return success: 0，fail: -HISI_QM_DRVCRYPT_EINVAL
+ *@return success: 0，fail: HISI_QM_DRVCRYPT_EINVAL
  */
-int32_t hisi_qp_recv_sync(struct hisi_qp *qp, void *msg);
+TEE_Result hisi_qp_recv_sync(struct hisi_qp *qp, void *msg);
 
 #endif
diff --git a/core/drivers/crypto/hisilicon/include/hisi_sec.h b/core/drivers/crypto/hisilicon/include/hisi_sec.h
index a220b8a0aac..0e57540d533 100644
--- a/core/drivers/crypto/hisilicon/include/hisi_sec.h
+++ b/core/drivers/crypto/hisilicon/include/hisi_sec.h
@@ -336,6 +336,12 @@ enum hisi_buff_type {
 	HISI_SGL_BUF,
 };
 
+/**
+ *@Description: Create Queue Pair for SEC, allocated to PF/VF for configure
+ * and service use. Each QP includes one SQ and one CQ
+ *@param sq_type: Accelerator specific algorithm type in sqc
+ *@return success: Handle of QP，fail: NULL
+ */
 struct hisi_qp *hisi_sec_create_qp(uint8_t sq_type);
 
 #endif
diff --git a/core/drivers/crypto/hisilicon/sec/hisi_sec.c b/core/drivers/crypto/hisilicon/sec/hisi_sec.c
index 8187373b930..1eb6f76a5b3 100644
--- a/core/drivers/crypto/hisilicon/sec/hisi_sec.c
+++ b/core/drivers/crypto/hisilicon/sec/hisi_sec.c
@@ -30,7 +30,6 @@
 #define SEC_RAS_FE_ENB_MASK 0x0
 #define SEC_RAS_NFE_ENB_MASK 0x177
 #define SEC_CLK_GATE_ENABLE BIT(3)
-#define SEC_CLK_GATE_DISABLE (~BIT(3))
 #define SEC_DYNAMIC_GATE_EN 0x7bff
 #define SEC_CORE_AUTO_GATE_EN GENMASK_32(3, 0)
 #define SEC_TRNG_EN_MASK BIT(8)
@@ -76,13 +75,8 @@ struct hisi_qp *hisi_sec_create_qp(uint8_t sq_type)
 
 static void sec_disable_clock_gate(struct hisi_qm *qm)
 {
-	uint32_t val = 0;
-
 	/* HISI_QM_HW_V2 version need to close clock gating */
-	val = io_read32(qm->io_base + SEC_CONTROL_REG) &
-	      SEC_CLK_GATE_DISABLE;
-
-	io_write32(qm->io_base + SEC_CONTROL_REG, val);
+	val = io_clrbits32(qm->io_base + SEC_CONTROL_REG, SEC_CLK_GATE_ENABLE);
 }
 
 static void sec_enable_clock_gate(struct hisi_qm *qm)
@@ -152,14 +146,14 @@ static int32_t sec_engine_init(struct acc_device *sec_dev)
 	return HISI_QM_DRVCRYPT_NO_ERR;
 }
 
-static int32_t sec_dev_status_check(struct hisi_qm *qm)
+static uint32_t sec_dev_status_check(struct hisi_qm *qm)
 {
 	uint32_t val = 0;
 
 	val = io_read32(qm->io_base + SEC_CORE_INT_SOURCE);
 	if (val & SEC_RAS_NFE_ENB_MASK) {
 		EMSG("SEC NFE RAS happened, need to reset");
-		return -HISI_QM_DRVCRYPT_HW_EACCESS;
+		return HISI_QM_DRVCRYPT_HW_EACCESS;
 	}
 
 	val = io_read32(qm->io_base + HISI_QM_ABNML_INT_SRC);
@@ -173,7 +167,7 @@ static int32_t sec_dev_status_check(struct hisi_qm *qm)
 				   HISI_QM_INVALID_DB);
 		}
 
-		return -HISI_QM_DRVCRYPT_HW_EACCESS;
+		return HISI_QM_DRVCRYPT_HW_EACCESS;
 	}
 
 	return HISI_QM_DRVCRYPT_NO_ERR;
@@ -188,7 +182,7 @@ static int32_t sec_qm_init(struct acc_device *sec_dev)
 							 sec_dev->io_size);
 		if (!qm->io_base) {
 			EMSG("Fail to get qm io_base");
-			return -HISI_QM_DRVCRYPT_EFAULT;
+			return HISI_QM_DRVCRYPT_EFAULT;
 		}
 	} else {
 		qm->io_base = sec_dev->io_base;
@@ -238,7 +232,7 @@ static uint32_t sec_probe(void)
 	IMSG("SEC driver init start, version %s", SEC_MODULE_VERSION);
 	sec_dev = sec_pre_init();
 	if (!sec_dev)
-		return -HISI_QM_DRVCRYPT_ENOMEM;
+		return HISI_QM_DRVCRYPT_ENOMEM;
 
 	qm = &sec_dev->qm;
 	ret = sec_qm_init(sec_dev);
@@ -268,7 +262,7 @@ static uint32_t sec_probe(void)
 	SLIST_REMOVE_HEAD(&sec_list, link);
 	free(sec_dev);
 
-	return -HISI_QM_DRVCRYPT_FAIL;
+	return HISI_QM_DRVCRYPT_FAIL;
 }
 
 driver_init(sec_probe);
diff --git a/core/drivers/crypto/hisilicon/sec/sec_cipher.c b/core/drivers/crypto/hisilicon/sec/sec_cipher.c
index 7b0e567e94d..da687107a46 100644
--- a/core/drivers/crypto/hisilicon/sec/sec_cipher.c
+++ b/core/drivers/crypto/hisilicon/sec/sec_cipher.c
@@ -7,7 +7,7 @@
 
 static TEE_Result sec_do_cipher_task(struct hisi_qp *qp, void *msg)
 {
-	int32_t ret = 0;
+	uint32_t ret = 0;
 
 	ret = hisi_qp_send(qp, msg);
 	if (ret) {
@@ -229,8 +229,8 @@ static TEE_Result sec_cipher_sm4_get_c_key_len(const int key_len,
 }
 
 static TEE_Result sec_cipher_set_key(struct sec_cipher_ctx *c_ctx,
-			      const uint8_t *key1, const int key1_len,
-			      const uint8_t *key2, const int key2_len)
+				     const uint8_t *key1, const int key1_len,
+			             const uint8_t *key2, const int key2_len)
 {
 	int key_len = key1_len + key2_len;
 	uint8_t c_key_len = 0;
@@ -330,7 +330,7 @@ static TEE_Result sec_cipher_set_iv(struct sec_cipher_ctx *c_ctx,
 	return TEE_SUCCESS;
 }
 
-static int32_t sec_cipher_bd_fill(void *bd, void *msg)
+static TEE_Result sec_cipher_bd_fill(void *bd, void *msg)
 {
 	struct sec_cipher_ctx *c_ctx = (struct sec_cipher_ctx *)msg;
 	struct hisi_sec_sqe *sqe = (struct hisi_sec_sqe *)bd;
@@ -365,7 +365,7 @@ static int32_t sec_cipher_bd_fill(void *bd, void *msg)
 	return TEE_SUCCESS;
 }
 
-static int32_t sec_cipher_bd_parse(void *bd, void *msg __unused)
+static TEE_Result sec_cipher_bd_parse(void *bd, void *msg __unused)
 {
 	struct hisi_sec_sqe *sqe = (struct hisi_sec_sqe *)bd;
 
@@ -378,7 +378,7 @@ static int32_t sec_cipher_bd_parse(void *bd, void *msg __unused)
 	return TEE_SUCCESS;
 }
 
-static int32_t sec_cipher_bd3_fill(void *bd, void *msg)
+static TEE_Result sec_cipher_bd3_fill(void *bd, void *msg)
 {
 	struct hisi_sec_bd3_sqe *sqe = (struct hisi_sec_bd3_sqe *)bd;
 	struct sec_cipher_ctx *c_ctx = (struct sec_cipher_ctx *)msg;
@@ -414,7 +414,7 @@ static int32_t sec_cipher_bd3_fill(void *bd, void *msg)
 	return TEE_SUCCESS;
 }
 
-static int32_t sec_cipher_bd3_parse(void *bd, void *msg __unused)
+static TEE_Result sec_cipher_bd3_parse(void *bd, void *msg __unused)
 {
 	struct hisi_sec_bd3_sqe *sqe = (struct hisi_sec_bd3_sqe *)bd;