From 963a90d842b565291bf2dbeb699e2fd98b15d526 Mon Sep 17 00:00:00 2001 From: Sahil Malhotra Date: Tue, 23 Jan 2024 12:54:47 +0100 Subject: [PATCH] drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms The SECO firmware enables the RNG prediction resistance by default. There is no need to read the CAAM RNG status registers. Signed-off-by: Sahil Malhotra Acked-by: Jens Wiklander Acked-by: Clement Faure --- core/drivers/crypto/caam/hal/common/hal_rng.c | 5 ++++- core/drivers/crypto/caam/hal/imx_8q/hal_rng.c | 11 ++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/core/drivers/crypto/caam/hal/common/hal_rng.c b/core/drivers/crypto/caam/hal/common/hal_rng.c index 5f8f0afc291..aba8cbcd4b0 100644 --- a/core/drivers/crypto/caam/hal/common/hal_rng.c +++ b/core/drivers/crypto/caam/hal/common/hal_rng.c @@ -62,7 +62,10 @@ bool caam_hal_rng_key_loaded(vaddr_t baseaddr) return io_caam_read32(baseaddr + RNG_STA) & RNG_STA_SKVN; } -bool caam_hal_rng_pr_enabled(vaddr_t baseaddr) +/* + * This function will be overridden for i.MX8QX and i.MX8DX platforms. + */ +bool __weak caam_hal_rng_pr_enabled(vaddr_t baseaddr) { uint32_t bitmask = RNG_STA_PR0; diff --git a/core/drivers/crypto/caam/hal/imx_8q/hal_rng.c b/core/drivers/crypto/caam/hal/imx_8q/hal_rng.c index a561ab1235b..40d9a6b2242 100644 --- a/core/drivers/crypto/caam/hal/imx_8q/hal_rng.c +++ b/core/drivers/crypto/caam/hal/imx_8q/hal_rng.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-2-Clause /* - * Copyright 2020-2021 NXP + * Copyright 2020-2021, 2024 NXP */ #include #include @@ -18,3 +18,12 @@ enum caam_status caam_hal_rng_instantiated(vaddr_t baseaddr __unused) else return CAAM_NO_ERROR; } + +bool caam_hal_rng_pr_enabled(vaddr_t baseaddr __unused) +{ + /* + * On platforms i.MX8Q and i.MX8DXL CAAM RNG Prediction + * resistance is enabled by default. So returning true. + */ + return true; +}