From 9c64457b897f1f6564ed79534cdeab5cd6a639a4 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Wed, 2 Oct 2024 15:30:24 +0200 Subject: [PATCH 01/14] dts: stm32: default disable DMA at SoC level for stm32mp15 platforms DMA node in stm32mp15* SoC DTSI files shouldn't be enabled by default, we don't even have a driver to handle it. Therefore default disable it. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/dts/stm32mp151.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/core/arch/arm/dts/stm32mp151.dtsi b/core/arch/arm/dts/stm32mp151.dtsi index d6729c8c1fd..7a64e9fb3cc 100644 --- a/core/arch/arm/dts/stm32mp151.dtsi +++ b/core/arch/arm/dts/stm32mp151.dtsi @@ -1011,6 +1011,7 @@ #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + status = "disabled"; }; dma2: dma-controller@48001000 { @@ -1029,6 +1030,7 @@ #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + status = "disabled"; }; dmamux1: dma-router@48002000 { @@ -1040,6 +1042,7 @@ dma-channels = <16>; clocks = <&rcc DMAMUX>; resets = <&rcc DMAMUX_R>; + status = "disabled"; }; adc: adc@48003000 { From 8e79111010043ef27b382eef4bc6c5f5cf958154 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Wed, 2 Oct 2024 15:42:39 +0200 Subject: [PATCH 02/14] dts: stm32: disable ADC2 on stm32mp135f-dk Remove ADC2 configuration in stm32mp135-dk.dts since OP-TEE does not use the device. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/dts/stm32mp135f-dk.dts | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/core/arch/arm/dts/stm32mp135f-dk.dts b/core/arch/arm/dts/stm32mp135f-dk.dts index 7357601bac9..cf29f83200c 100644 --- a/core/arch/arm/dts/stm32mp135f-dk.dts +++ b/core/arch/arm/dts/stm32mp135f-dk.dts @@ -61,21 +61,6 @@ }; }; -&adc_2 { - vdda-supply = <&vdd_adc>; - vref-supply = <&vdd_adc>; - status = "okay"; - - adc2: adc@0 { - status = "okay"; - - channel@15 { - reg = <15>; - label = "vbat"; - }; - }; -}; - &bsec { board_id: board_id@f0 { reg = <0xf0 0x4>; From d73639c404ff38c96eee82e2f6e13b249c223402 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Wed, 2 Oct 2024 17:15:46 +0200 Subject: [PATCH 03/14] dts: stm32: disable VREFBUF on stm32mp15-dkx platforms VREFBUF is currently not used on stm32mp15-dkx platforms, so disable it. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/dts/stm32mp15xx-dkx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/arm/dts/stm32mp15xx-dkx.dtsi b/core/arch/arm/dts/stm32mp15xx-dkx.dtsi index af5a0534455..e33a04ae404 100644 --- a/core/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/core/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -742,5 +742,5 @@ regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; vdda-supply = <&vdd>; - status = "okay"; + status = "disabled"; }; From 36bd3870dbec87ddcacab9100c86028821fbd3b2 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Wed, 2 Oct 2024 17:33:03 +0200 Subject: [PATCH 04/14] dts: stm32: use st,stm32mp15-i2c-non-secure compatible for the I2C4 Use st,stm32mp15-i2c-non-secure compatible for the I2C4 as it is currently non-secure on stm32mp15 dkx and evx platforms. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/dts/stm32mp157c-ed1.dts | 1 + core/arch/arm/dts/stm32mp15xx-dkx.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/core/arch/arm/dts/stm32mp157c-ed1.dts b/core/arch/arm/dts/stm32mp157c-ed1.dts index c0b4e1a294d..ef19d70a761 100644 --- a/core/arch/arm/dts/stm32mp157c-ed1.dts +++ b/core/arch/arm/dts/stm32mp157c-ed1.dts @@ -161,6 +161,7 @@ }; &i2c4 { + compatible = "st,stm32mp15-i2c-non-secure"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; pinctrl-1 = <&i2c4_sleep_pins_a>; diff --git a/core/arch/arm/dts/stm32mp15xx-dkx.dtsi b/core/arch/arm/dts/stm32mp15xx-dkx.dtsi index e33a04ae404..8500a96eea2 100644 --- a/core/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/core/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -242,6 +242,7 @@ }; &i2c4 { + compatible = "st,stm32mp15-i2c-non-secure"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; pinctrl-1 = <&i2c4_sleep_pins_a>; From 3dddcb6fca5d33db6fb421a16dbb622c56dfb948 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 05/14] dt-bindings: add platform specific ETZPC bindings Define ETZPC bindings for STM32MP15 and STM32MP13 and add these header files into the stm32mp_dt_bindings helper. While there, also update some includes to fix the path errors. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/plat-stm32mp1/main.c | 3 +- .../arch/arm/plat-stm32mp1/shared_resources.c | 3 +- core/drivers/stm32_rng.c | 4 +- core/include/drivers/stm32mp_dt_bindings.h | 4 +- .../dt-bindings/firewall/stm32mp13-etzpc.h | 85 +++++++++++++++++ .../dt-bindings/firewall/stm32mp15-etzpc.h} | 92 ++++++------------- 6 files changed, 122 insertions(+), 69 deletions(-) create mode 100644 core/include/dt-bindings/firewall/stm32mp13-etzpc.h rename core/{arch/arm/plat-stm32mp1/drivers/stm32mp1_etzpc.h => include/dt-bindings/firewall/stm32mp15-etzpc.h} (60%) diff --git a/core/arch/arm/plat-stm32mp1/main.c b/core/arch/arm/plat-stm32mp1/main.c index b8bb1f43905..c0dd7c1c94e 100644 --- a/core/arch/arm/plat-stm32mp1/main.c +++ b/core/arch/arm/plat-stm32mp1/main.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-2-Clause /* - * Copyright (c) 2017-2022, STMicroelectronics + * Copyright (c) 2017-2024, STMicroelectronics * Copyright (c) 2016-2018, Linaro Limited */ @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/core/arch/arm/plat-stm32mp1/shared_resources.c b/core/arch/arm/plat-stm32mp1/shared_resources.c index 4562ebd07d3..3717aebd836 100644 --- a/core/arch/arm/plat-stm32mp1/shared_resources.c +++ b/core/arch/arm/plat-stm32mp1/shared_resources.c @@ -1,13 +1,12 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2017-2023, STMicroelectronics + * Copyright (c) 2017-2024, STMicroelectronics */ #include #include #include #include -#include #include #include #include diff --git a/core/drivers/stm32_rng.c b/core/drivers/stm32_rng.c index c15e6aee5ad..be68afdcc76 100644 --- a/core/drivers/stm32_rng.c +++ b/core/drivers/stm32_rng.c @@ -7,9 +7,9 @@ #include #include #include -#include #if defined(CFG_STM32MP15) -#include +#include +#include #endif /* defined(CFG_STM32MP15) */ #include #include diff --git a/core/include/drivers/stm32mp_dt_bindings.h b/core/include/drivers/stm32mp_dt_bindings.h index 9e6a9344107..e6de73d3cae 100644 --- a/core/include/drivers/stm32mp_dt_bindings.h +++ b/core/include/drivers/stm32mp_dt_bindings.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2022, STMicroelectronics + * Copyright (c) 2022-2024, STMicroelectronics */ #ifndef __DRIVERS_STM32MP_DT_BINDINGS_H #define __DRIVERS_STM32MP_DT_BINDINGS_H @@ -8,12 +8,14 @@ #ifdef CFG_STM32MP13 #include #include +#include #include #include #endif #ifdef CFG_STM32MP15 #include +#include #include #include #endif diff --git a/core/include/dt-bindings/firewall/stm32mp13-etzpc.h b/core/include/dt-bindings/firewall/stm32mp13-etzpc.h new file mode 100644 index 00000000000..74662116fde --- /dev/null +++ b/core/include/dt-bindings/firewall/stm32mp13-etzpc.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2022-2024, STMicroelectronics + */ + +#ifndef _DT_BINDINGS_FIREWALL_STM32MP13_ETZPC_H +#define _DT_BINDINGS_FIREWALL_STM32MP13_ETZPC_H + +/* define DECPROT modes */ +#define DECPROT_S_RW 0x0 +#define DECPROT_NS_R_S_W 0x1 +#define DECPROT_NS_RW 0x3 + +/* define DECPROT lock */ +#define DECPROT_UNLOCK 0x0 +#define DECPROT_LOCK 0x1 + +/* define TZMA IDs*/ +#define ETZPC_TZMA0_ID 200 +#define ETZPC_TZMA1_ID 201 + +/* define ETZPC ID */ +#define STM32MP1_ETZPC_VREFBUF_ID 0 +#define STM32MP1_ETZPC_LPTIM2_ID 1 +#define STM32MP1_ETZPC_LPTIM3_ID 2 +#define STM32MP1_ETZPC_LTDC_ID 3 +#define STM32MP1_ETZPC_DCMIPP_ID 4 +#define STM32MP1_ETZPC_USBPHYCTRL_ID 5 +#define STM32MP1_ETZPC_DDRCTRLPHY_ID 6 +/* 7-11 Reserved */ +#define STM32MP1_ETZPC_IWDG1_ID 12 +#define STM32MP1_ETZPC_STGENC_ID 13 +/* 14-15 Reserved */ +#define STM32MP1_ETZPC_USART1_ID 16 +#define STM32MP1_ETZPC_USART2_ID 17 +#define STM32MP1_ETZPC_SPI4_ID 18 +#define STM32MP1_ETZPC_SPI5_ID 19 +#define STM32MP1_ETZPC_I2C3_ID 20 +#define STM32MP1_ETZPC_I2C4_ID 21 +#define STM32MP1_ETZPC_I2C5_ID 22 +#define STM32MP1_ETZPC_TIM12_ID 23 +#define STM32MP1_ETZPC_TIM13_ID 24 +#define STM32MP1_ETZPC_TIM14_ID 25 +#define STM32MP1_ETZPC_TIM15_ID 26 +#define STM32MP1_ETZPC_TIM16_ID 27 +#define STM32MP1_ETZPC_TIM17_ID 28 +/* 29-31 Reserved */ +#define STM32MP1_ETZPC_ADC1_ID 32 +#define STM32MP1_ETZPC_ADC2_ID 33 +#define STM32MP1_ETZPC_OTG_ID 34 +#define STM32MP1_ETZPC_TSC_ID 37 +/* 38-39 Reserved */ +#define STM32MP1_ETZPC_RNG_ID 40 +#define STM32MP1_ETZPC_HASH_ID 41 +#define STM32MP1_ETZPC_CRYP_ID 42 +#define STM32MP1_ETZPC_SAES_ID 43 +#define STM32MP1_ETZPC_PKA_ID 44 +#define STM32MP1_ETZPC_BKPSRAM_ID 45 +/* 46-47 Reserved */ +#define STM32MP1_ETZPC_ETH1_ID 48 +#define STM32MP1_ETZPC_ETH2_ID 49 +#define STM32MP1_ETZPC_SDMMC1_ID 50 +#define STM32MP1_ETZPC_SDMMC2_ID 51 +/* 52 Reserved */ +#define STM32MP1_ETZPC_MCE_ID 53 +#define STM32MP1_ETZPC_FMC_ID 54 +#define STM32MP1_ETZPC_QSPI_ID 55 +/* 56-59 Reserved */ +#define STM32MP1_ETZPC_SRAM1_ID 60 +#define STM32MP1_ETZPC_SRAM2_ID 61 +#define STM32MP1_ETZPC_SRAM3_ID 62 +/* 63 Reserved */ + +#define STM32MP1_ETZPC_MAX_ID 64 + +#define DECPROT(id, mode, lock) ((id) | ((mode) << ETZPC_MODE_SHIFT) | \ + ((lock) << ETZPC_LOCK_SHIFT)) + +#define ETZPC_ID_MASK GENMASK_32(7, 0) +#define ETZPC_LOCK_MASK BIT(8) +#define ETZPC_LOCK_SHIFT 8 +#define ETZPC_MODE_SHIFT 9 +#define ETZPC_MODE_MASK GENMASK_32(31, 9) + +#endif /* _DT_BINDINGS_FIREWALL_STM32MP13_ETZPC_H */ diff --git a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_etzpc.h b/core/include/dt-bindings/firewall/stm32mp15-etzpc.h similarity index 60% rename from core/arch/arm/plat-stm32mp1/drivers/stm32mp1_etzpc.h rename to core/include/dt-bindings/firewall/stm32mp15-etzpc.h index bc0b78fa25a..cc99f4931ba 100644 --- a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_etzpc.h +++ b/core/include/dt-bindings/firewall/stm32mp15-etzpc.h @@ -1,13 +1,26 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2018-2019, STMicroelectronics + * Copyright (c) 2018-2024, STMicroelectronics */ -#ifndef __STM32MP1_ETZPC_H -#define __STM32MP1_ETZPC_H +#ifndef _DT_BINDINGS_FIREWALL_STM32MP15_ETZPC_H +#define _DT_BINDINGS_FIREWALL_STM32MP15_ETZPC_H -/* Define DECPROT IDs for stm32mp1 familly */ -#ifdef CFG_STM32MP15 +/* define DECPROT modes */ +#define DECPROT_S_RW 0x0 +#define DECPROT_NS_R_S_W 0x1 +#define DECPROT_MCU_ISOLATION 0x2 +#define DECPROT_NS_RW 0x3 + +/* define DECPROT lock */ +#define DECPROT_UNLOCK 0x0 +#define DECPROT_LOCK 0x1 + +/* define TZMA IDs*/ +#define ETZPC_TZMA0_ID 200 +#define ETZPC_TZMA1_ID 201 + +/* define ETZPC ID */ #define STM32MP1_ETZPC_STGENC_ID 0 #define STM32MP1_ETZPC_BKPSRAM_ID 1 #define STM32MP1_ETZPC_IWDG1_ID 2 @@ -96,61 +109,16 @@ #define STM32MP1_ETZPC_DLYBQ_ID 93 #define STM32MP1_ETZPC_ETH_ID 94 /* 95 Reserved */ + #define STM32MP1_ETZPC_MAX_ID 96 -#endif /* CFG_STM32MP15 */ -#ifdef CFG_STM32MP13 -#define STM32MP1_ETZPC_VREFBUF_ID 0 -#define STM32MP1_ETZPC_LPTIM2_ID 1 -#define STM32MP1_ETZPC_LPTIM3_ID 2 -#define STM32MP1_ETZPC_LTDC_ID 3 -#define STM32MP1_ETZPC_DCMIPP_ID 4 -#define STM32MP1_ETZPC_USBPHYCTRL_ID 5 -#define STM32MP1_ETZPC_DDRCTRLPHY_ID 6 -/* 7-11 Reserved */ -#define STM32MP1_ETZPC_IWDG1_ID 12 -#define STM32MP1_ETZPC_STGENC_ID 13 -/* 14-15 Reserved */ -#define STM32MP1_ETZPC_USART1_ID 16 -#define STM32MP1_ETZPC_USART2_ID 17 -#define STM32MP1_ETZPC_SPI4_ID 18 -#define STM32MP1_ETZPC_SPI5_ID 19 -#define STM32MP1_ETZPC_I2C3_ID 20 -#define STM32MP1_ETZPC_I2C4_ID 21 -#define STM32MP1_ETZPC_I2C5_ID 22 -#define STM32MP1_ETZPC_TIM12_ID 23 -#define STM32MP1_ETZPC_TIM13_ID 24 -#define STM32MP1_ETZPC_TIM14_ID 25 -#define STM32MP1_ETZPC_TIM15_ID 26 -#define STM32MP1_ETZPC_TIM16_ID 27 -#define STM32MP1_ETZPC_TIM17_ID 28 -/* 29-31 Reserved */ -#define STM32MP1_ETZPC_ADC1_ID 32 -#define STM32MP1_ETZPC_ADC2_ID 33 -#define STM32MP1_ETZPC_OTG_ID 34 -/* 35-36 Reserved */ -#define STM32MP1_ETZPC_TSC_ID 37 -/* 38-39 Reserved */ -#define STM32MP1_ETZPC_RNG_ID 40 -#define STM32MP1_ETZPC_HASH_ID 41 -#define STM32MP1_ETZPC_CRYP_ID 42 -#define STM32MP1_ETZPC_SAES_ID 43 -#define STM32MP1_ETZPC_PKA_ID 44 -#define STM32MP1_ETZPC_BKPSRAM_ID 45 -/* 46-47 Reserved */ -#define STM32MP1_ETZPC_ETH1_ID 48 -#define STM32MP1_ETZPC_ETH2_ID 49 -#define STM32MP1_ETZPC_SDMMC1_ID 50 -#define STM32MP1_ETZPC_SDMMC2_ID 51 -/* 52 Reserved */ -#define STM32MP1_ETZPC_MCE_ID 53 -#define STM32MP1_ETZPC_FMC_ID 54 -#define STM32MP1_ETZPC_QSPI_ID 55 -/* 56-59 Reserved */ -#define STM32MP1_ETZPC_SRAM1_ID 60 -#define STM32MP1_ETZPC_SRAM2_ID 61 -#define STM32MP1_ETZPC_SRAM3_ID 62 -/* 63 Reserved */ -#define STM32MP1_ETZPC_MAX_ID 64 -#endif /* CFG_STM32MP13 */ -#endif /*__STM32MP1_ETZPC_H*/ +#define DECPROT(id, mode, lock) ((id) | ((mode) << ETZPC_MODE_SHIFT) | \ + ((lock) << ETZPC_LOCK_SHIFT)) + +#define ETZPC_ID_MASK GENMASK_32(7, 0) +#define ETZPC_LOCK_MASK BIT(8) +#define ETZPC_LOCK_SHIFT 8 +#define ETZPC_MODE_SHIFT 9 +#define ETZPC_MODE_MASK GENMASK_32(31, 9) + +#endif /* _DT_BINDINGS_FIREWALL_STM32MP15_ETZPC_H */ From 7aae566c3d187dbbd651aa53f8564b3bd862d0b4 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 06/14] dts: stm32: add the ETZPC configuration table for stm32mp1x boards Add the tables defining the ETZPC firewall controller configuration that will be set at boot time on stm32mp1x boards. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere Acked-by: Johann Neuhauser --- core/arch/arm/dts/stm32mp131.dtsi | 1 + core/arch/arm/dts/stm32mp135f-dk.dts | 47 +++++++++++++++++++- core/arch/arm/dts/stm32mp151.dtsi | 1 + core/arch/arm/dts/stm32mp157a-dk1-scmi.dts | 17 ++++++- core/arch/arm/dts/stm32mp157a-dk1.dts | 17 ++++++- core/arch/arm/dts/stm32mp157c-dk2-scmi.dts | 18 +++++++- core/arch/arm/dts/stm32mp157c-dk2.dts | 18 +++++++- core/arch/arm/dts/stm32mp157c-ed1-scmi.dts | 18 +++++++- core/arch/arm/dts/stm32mp157c-ed1.dts | 18 +++++++- core/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 16 +++++++ core/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi | 16 +++++++ 11 files changed, 180 insertions(+), 7 deletions(-) diff --git a/core/arch/arm/dts/stm32mp131.dtsi b/core/arch/arm/dts/stm32mp131.dtsi index 3ddfaab8ce2..1cf2bd51ea3 100644 --- a/core/arch/arm/dts/stm32mp131.dtsi +++ b/core/arch/arm/dts/stm32mp131.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/core/arch/arm/dts/stm32mp135f-dk.dts b/core/arch/arm/dts/stm32mp135f-dk.dts index cf29f83200c..fe66def4d74 100644 --- a/core/arch/arm/dts/stm32mp135f-dk.dts +++ b/core/arch/arm/dts/stm32mp135f-dk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved + * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -68,6 +68,51 @@ }; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &gpiob { st,protreg = ; }; diff --git a/core/arch/arm/dts/stm32mp151.dtsi b/core/arch/arm/dts/stm32mp151.dtsi index 7a64e9fb3cc..b35dd07fe2b 100644 --- a/core/arch/arm/dts/stm32mp151.dtsi +++ b/core/arch/arm/dts/stm32mp151.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; diff --git a/core/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/core/arch/arm/dts/stm32mp157a-dk1-scmi.dts index 8236375389b..2d0cad2ca9d 100644 --- a/core/arch/arm/dts/stm32mp157a-dk1-scmi.dts +++ b/core/arch/arm/dts/stm32mp157a-dk1-scmi.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2023 + * Copyright (C) STMicroelectronics 2023-2024 */ /dts-v1/; @@ -12,6 +12,21 @@ compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157"; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure"; status = "okay"; diff --git a/core/arch/arm/dts/stm32mp157a-dk1.dts b/core/arch/arm/dts/stm32mp157a-dk1.dts index 294746da4ff..6ce8c6ae224 100644 --- a/core/arch/arm/dts/stm32mp157a-dk1.dts +++ b/core/arch/arm/dts/stm32mp157a-dk1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (C) STMicroelectronics 2019-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -36,3 +36,18 @@ reg = <0xf0 0x10>; }; }; + +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + ; +}; diff --git a/core/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/core/arch/arm/dts/stm32mp157c-dk2-scmi.dts index e80e2a47c1e..30436d148af 100644 --- a/core/arch/arm/dts/stm32mp157c-dk2-scmi.dts +++ b/core/arch/arm/dts/stm32mp157c-dk2-scmi.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2023 + * Copyright (C) STMicroelectronics 2023-2024 */ /dts-v1/; @@ -12,6 +12,22 @@ compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157"; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure"; status = "okay"; diff --git a/core/arch/arm/dts/stm32mp157c-dk2.dts b/core/arch/arm/dts/stm32mp157c-dk2.dts index dfb8f9830fd..471a062e2a0 100644 --- a/core/arch/arm/dts/stm32mp157c-dk2.dts +++ b/core/arch/arm/dts/stm32mp157c-dk2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (C) STMicroelectronics 2019-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -74,6 +74,22 @@ }; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &i2c1 { touchscreen@38 { compatible = "focaltech,ft6236"; diff --git a/core/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/core/arch/arm/dts/stm32mp157c-ed1-scmi.dts index 19cf9bc6b93..5c2c172984b 100644 --- a/core/arch/arm/dts/stm32mp157c-ed1-scmi.dts +++ b/core/arch/arm/dts/stm32mp157c-ed1-scmi.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2023 + * Copyright (C) STMicroelectronics 2023-2024 */ /dts-v1/; @@ -11,6 +11,22 @@ compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157"; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &iwdg1 { timeout-sec = <32>; }; diff --git a/core/arch/arm/dts/stm32mp157c-ed1.dts b/core/arch/arm/dts/stm32mp157c-ed1.dts index ef19d70a761..90a85cf7f05 100644 --- a/core/arch/arm/dts/stm32mp157c-ed1.dts +++ b/core/arch/arm/dts/stm32mp157c-ed1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Copyright (C) STMicroelectronics 2017-2024 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ /dts-v1/; @@ -152,6 +152,22 @@ status = "disabled"; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &gpu { contiguous-area = <&gpu_reserved>; }; diff --git a/core/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/core/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index b4fc6da5b4a..be1c35bddf9 100644 --- a/core/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/core/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -147,6 +147,22 @@ }; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &fmc { pinctrl-names = "default", "sleep"; pinctrl-0 = <&fmc_pins_b>; diff --git a/core/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/core/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 312f3870a6c..6a793e9837a 100644 --- a/core/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ b/core/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -72,6 +72,22 @@ status = "okay"; }; +&etzpc { + st,decprot = + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; From 617e63ffcfa76915cefeded1c50df4bd87dfa5fc Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 07/14] dts: stm32: define ETZPC as an access controller for stm32mp15 platforms ETZPC is a firewall controller. Add the access-controllers property to all ETZPC sub-nodes on stm32mp15x platforms. Also add the "simple-bus" compatible for backward compatibility and "#access-controllers-cells" to the ETZPC node. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/dts/stm32mp151.dtsi | 2991 ++++++++++++++-------------- core/arch/arm/dts/stm32mp153.dtsi | 54 +- core/arch/arm/dts/stm32mp15xc.dtsi | 21 +- 3 files changed, 1566 insertions(+), 1500 deletions(-) diff --git a/core/arch/arm/dts/stm32mp151.dtsi b/core/arch/arm/dts/stm32mp151.dtsi index b35dd07fe2b..bda0ac76224 100644 --- a/core/arch/arm/dts/stm32mp151.dtsi +++ b/core/arch/arm/dts/stm32mp151.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Copyright (C) STMicroelectronics 2017-2024 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ #include @@ -123,1707 +123,1772 @@ interrupt-parent = <&intc>; ranges; - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <&exti 61 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc IPCC>; + wakeup-source; status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; }; - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; }; - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4"; - status = "disabled"; + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; }; - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; }; - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; + pwr_mcu: pwr_mcu@50001014 { + compatible = "st,stm32mp151-pwr-mcu", "syscon"; + reg = <0x50001014 0x4>; }; - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; }; - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; }; - timers12: timer@40006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40006000 0x400>; - clocks = <&rcc TIM12_K>; - clock-names = "int"; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = ; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; }; - timers13: timer@40007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40007000 0x400>; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; + mdma1: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; }; - timers14: timer@40008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40008000 0x400>; - clocks = <&rcc TIM14_K>; - clock-names = "int"; + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x58005000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; }; - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x58007000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; }; - spi2: spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = ; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; - dma-names = "rx", "tx"; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; status = "disabled"; }; - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000b000 0x400>; - interrupts = ; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; status = "disabled"; }; - spi3: spi@4000c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = ; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; - dma-names = "rx", "tx"; + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; status = "disabled"; }; - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000c000 0x400>; - interrupts = ; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; status = "disabled"; - }; - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - #sound-dai-cells = <0>; - reg = <0x4000d000 0x400>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = ; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; }; - usart2: serial@4000e000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000e000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x15>, - <&dmamux1 44 0x400 0x11>; - dma-names = "rx", "tx"; + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + interrupts = ; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; status = "disabled"; }; - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x15>, - <&dmamux1 46 0x400 0x11>; - dma-names = "rx", "tx"; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; status = "disabled"; - }; - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x15>, - <&dmamux1 64 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x15>, - <&dmamux1 66 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; }; - i2c1: i2c@40012000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - wakeup-source; - i2c-analog-filter; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + clocks = <&rcc RTCAPB>, <&rcc RTC>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - i2c2: i2c@40013000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; + bsec: efuse@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c3: i2c@40014000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40014000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; + #size-cells = <1>; - i2c5: i2c@40015000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40015000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; + cfg0_otp: cfg0_otp@0 { + reg = <0x0 0x1>; + }; + part_number_otp: part_number_otp@4 { + reg = <0x4 0x1>; + }; + monotonic_otp: monotonic_otp@10 { + reg = <0x10 0x4>; + }; + nand_otp: nand_otp@24 { + reg = <0x24 0x4>; + }; + uid_otp: uid_otp@34 { + reg = <0x34 0xc>; + }; + package_otp: package_otp@40 { + reg = <0x40 0x4>; + }; + hw2_otp: hw2_otp@48 { + reg = <0x48 0x4>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + pkh_otp: pkh_otp@60 { + reg = <0x60 0x20>; + }; + ethernet_mac_address: mac@e4 { + reg = <0xe4 0x8>; + st,non-secure-otp; + }; }; - cec: cec@40016000 { - compatible = "st,stm32-cec"; - reg = <0x40016000 0x400>; - interrupts = ; - clocks = <&rcc CEC_K>, <&rcc CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + clocks = <&rcc RTCAPB>; }; - dac: dac@40017000 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40017000 0x400>; - clocks = <&rcc DAC12>; - clock-names = "pclk"; + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pinctrl@50002000 { #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + #size-cells = <1>; + compatible = "st,stm32mp157-pinctrl"; + ranges = <0 0x50002000 0xa400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; + pins-are-numbered; - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA>; + st,bank-name = "GPIOA"; status = "disabled"; }; - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOB>; + st,bank-name = "GPIOB"; status = "disabled"; }; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x15>, - <&dmamux1 80 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x15>, - <&dmamux1 82 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOC>; + st,bank-name = "GPIOC"; status = "disabled"; }; - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc GPIOD>; + st,bank-name = "GPIOD"; status = "disabled"; }; - counter { - compatible = "st,stm32-timer-counter"; + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc GPIOE>; + st,bank-name = "GPIOE"; status = "disabled"; }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc GPIOF>; + st,bank-name = "GPIOF"; status = "disabled"; }; - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc GPIOG>; + st,bank-name = "GPIOG"; status = "disabled"; }; - counter { - compatible = "st,stm32-timer-counter"; + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc GPIOH>; + st,bank-name = "GPIOH"; status = "disabled"; }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = ; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x44004000 0x400>; - interrupts = ; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@44005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44005000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers15: timer@44006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44006000 0x400>; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc GPIOI>; + st,bank-name = "GPIOI"; status = "disabled"; }; - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; + gpioj: gpio@5000b000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x400>; + clocks = <&rcc GPIOJ>; + st,bank-name = "GPIOJ"; status = "disabled"; }; - }; - - timers16: timer@44007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44007000 0x400>; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; + gpiok: gpio@5000c000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa000 0x400>; + clocks = <&rcc GPIOK>; + st,bank-name = "GPIOK"; status = "disabled"; }; }; - timers17: timer@44008000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44008000 0x400>; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; + #size-cells = <1>; + compatible = "st,stm32mp157-z-pinctrl"; + ranges = <0 0x54004000 0x400>; + pins-are-numbered; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; + gpioz: gpio@54004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&rcc GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; status = "disabled"; }; }; - spi5: spi@44009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44009000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; + etzpc: etzpc@5c007000 { + compatible = "st,stm32-etzpc", "simple-bus"; + reg = <0x5C007000 0x400>; + clocks = <&rcc TZPC>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x4400a000 0x400>; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - interrupts = ; - resets = <&rcc SAI1_R>; - status = "disabled"; + #access-controller-cells = <1>; - sai1a: audio-controller@4400a004 { - #sound-dai-cells = <0>; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; - sai1b: audio-controller@4400a024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; }; - }; - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400b000 0x400>; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - interrupts = ; - resets = <&rcc SAI2_R>; - status = "disabled"; + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - sai2a: audio-controller@4400b004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; }; - sai2b: audio-controller@4400b024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; }; - }; - sai3: sai@4400c000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400c000 0x400>; - reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; - interrupts = ; - resets = <&rcc SAI3_R>; - status = "disabled"; + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - sai3a: audio-controller@4400c004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 113 0x400 0x01>; - status = "disabled"; + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; }; - sai3b: audio-controller@4400c024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 114 0x400 0x01>; - status = "disabled"; + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; }; - }; - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = ; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; + timers12: timer@40006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40006000 0x400>; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; }; - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <1>; - interrupts = ; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; + timers13: timer@40007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40007000 0x400>; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; }; - dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <2>; - interrupts = ; - dmas = <&dmamux1 103 0x400 0x01>; - dma-names = "rx"; + timers14: timer@40008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40008000 0x400>; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; }; - dfsdm3: filter@3 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <3>; - interrupts = ; - dmas = <&dmamux1 104 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; }; - dfsdm4: filter@4 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <4>; - interrupts = ; - dmas = <&dmamux1 91 0x400 0x01>; - dma-names = "rx"; + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; status = "disabled"; }; - dfsdm5: filter@5 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <5>; - interrupts = ; - dmas = <&dmamux1 92 0x400 0x01>; - dma-names = "rx"; + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + interrupts = ; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; status = "disabled"; }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - #dma-cells = <3>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - dma-channels = <16>; - clocks = <&rcc DMAMUX>; - resets = <&rcc DMAMUX_R>; - status = "disabled"; - }; - - adc: adc@48003000 { - compatible = "st,stm32mp1-adc-core"; - reg = <0x48003000 0x400>; - interrupts = , - ; - clocks = <&rcc ADC12>, <&rcc ADC12_K>; - clock-names = "bus", "adc"; - interrupt-controller; - st,syscfg = <&syscfg>; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + spi3: spi@4000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; + status = "disabled"; + }; - adc1: adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; - dma-names = "rx"; + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000c000 0x400>; + interrupts = ; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; status = "disabled"; }; - adc2: adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; - dma-names = "rx"; + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; + status = "disabled"; + }; + + usart2: serial@4000e000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000e000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART4_K>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; + status = "disabled"; + }; + + i2c1: i2c@40012000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; + i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; status = "disabled"; }; - }; - sdmmc3: mmc@48004000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x48004000 0x400>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC3_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC3_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; + i2c2: i2c@40013000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; + i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; + status = "disabled"; + }; - usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; + i2c3: i2c@40014000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40014000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; + i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; + status = "disabled"; + }; - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; - clocks = <&rcc IPCC>; - wakeup-source; - status = "disabled"; - }; + i2c5: i2c@40015000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40015000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; + i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; + status = "disabled"; + }; - dcmi: dcmi@4c006000 { - compatible = "st,stm32-dcmi"; - reg = <0x4c006000 0x400>; - interrupts = ; - resets = <&rcc CAMITF_R>; - clocks = <&rcc DCMI>; - clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x01>; - dma-names = "tx"; - status = "disabled"; - }; + cec: cec@40016000 { + compatible = "st,stm32-cec"; + reg = <0x40016000 0x400>; + interrupts = ; + clocks = <&rcc CEC_K>, <&rcc CEC>; + clock-names = "cec", "hdmi-cec"; + access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; + status = "disabled"; + }; - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; + status = "disabled"; - pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + status = "disabled"; + }; - reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + status = "disabled"; + }; }; - reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; + status = "disabled"; }; - usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; + status = "disabled"; }; - }; - pwr_mcu: pwr_mcu@50001014 { - compatible = "st,stm32mp151-pwr-mcu", "syscon"; - reg = <0x50001014 0x4>; - }; + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp1-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; }; - counter { - compatible = "st,stm32-lptimer-counter"; + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; status = "disabled"; }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; + spi1: spi@44004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; status = "disabled"; }; - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x44004000 0x400>; + interrupts = ; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; status = "disabled"; }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; + spi4: spi@44005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44005000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; status = "disabled"; }; - }; - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; }; - }; - vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; + timers16: timer@44007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44007000 0x400>; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; - sai4: sai@50027000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50027000 0x400>; - reg = <0x50027000 0x4>, <0x500273f0 0x10>; - interrupts = ; - resets = <&rcc SAI4_R>; - status = "disabled"; + timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44008000 0x400>; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; - sai4a: audio-controller@50027004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 99 0x400 0x01>; - status = "disabled"; + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; }; - sai4b: audio-controller@50027024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 100 0x400 0x01>; + spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44009000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; status = "disabled"; }; - }; - dts: thermal@50028000 { - compatible = "st,stm32-thermal"; - reg = <0x50028000 0x100>; - interrupts = ; - clocks = <&rcc TMPSENS>; - clock-names = "pclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400a000 0x400>; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = ; + resets = <&rcc SAI1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; - hash1: hash@54002000 { - compatible = "st,stm32f756-hash"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; - dma-names = "in"; - dma-maxburst = <2>; - status = "disabled"; - }; + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; - rng1: rng@54003000 { - compatible = "st,stm32-rng"; - reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = ; + resets = <&rcc SAI2_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; - mdma1: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = ; - clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; - fmc: memory-controller@58002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; + sai3: sai@4400c000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400c000 0x400>; + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = ; + resets = <&rcc SAI3_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; + status = "disabled"; + }; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; + status = "disabled"; + }; + }; - nand-controller@4,0 { + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; #address-cells = <1>; #size-cells = <0>; - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - interrupts = ; - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; + access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; status = "disabled"; - }; - }; - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = ; - dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, - <&mdma1 22 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <0>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58005000 0x1000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58007000 0x1000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <2>; + interrupts = ; + dmas = <&dmamux1 103 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; - crc1: crc@58009000 { - compatible = "st,stm32f7-crc"; - reg = <0x58009000 0x400>; - clocks = <&rcc CRC1>; - status = "disabled"; - }; + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <3>; + interrupts = ; + dmas = <&dmamux1 104 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; - ethernet0: ethernet@5800a000 { - compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "eth-ck", - "ptp_ref", - "ethstp"; - clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHCK_K>, - <&rcc ETHPTP_K>, - <&rcc ETHSTP>; - st,syscon = <&syscfg 0x4>; - snps,mixed-burst; - snps,pbl = <2>; - snps,en-tx-lpi-clockgating; - snps,axi-config = <&stmmac_axi_config_0>; - snps,tso; - status = "disabled"; + dfsdm4: filter@4 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <4>; + interrupts = ; + dmas = <&dmamux1 91 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; + dfsdm5: filter@5 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <5>; + interrupts = ; + dmas = <&dmamux1 92 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; }; - }; - - usbh_ohci: usb@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - status = "disabled"; - }; - usbh_ehci: usb@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - ltdc: display-controller@5a001000 { - compatible = "st,stm32-ltdc"; - reg = <0x5a001000 0x400>; - interrupts = , - ; - clocks = <&rcc LTDC_PX>; - clock-names = "lcd"; - resets = <&rcc LTDC_R>; - status = "disabled"; - - port { + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; + status = "disabled"; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; + status = "disabled"; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; + status = "disabled"; + }; + + adc: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = , + ; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + interrupt-controller; + st,syscfg = <&syscfg>; + #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; - }; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - interrupts = ; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; + access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dmamux1 10 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; }; - }; - usart1: serial@5c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x5c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - wakeup-source; - status = "disabled"; - }; - - spi6: spi@5c001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x5c001000 0x400>; - interrupts = ; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@5c002000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c002000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - iwdg1: watchdog@5c003000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5C003000 0x400>; - interrupts = ; - clocks = <&rcc IWDG1>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + sdmmc3: mmc@48004000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x48004000 0x400>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; + status = "disabled"; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; + status = "disabled"; + }; + + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = ; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x01>; + dma-names = "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; + status = "disabled"; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; - bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; - cfg0_otp: cfg0_otp@0 { - reg = <0x0 0x1>; - }; - part_number_otp: part_number_otp@4 { - reg = <0x4 0x1>; - }; - monotonic_otp: monotonic_otp@10 { - reg = <0x10 0x4>; - }; - nand_otp: nand_otp@24 { - reg = <0x24 0x4>; - }; - uid_otp: uid_otp@34 { - reg = <0x34 0xc>; - }; - package_otp: package_otp@40 { - reg = <0x40 0x4>; - }; - hw2_otp: hw2_otp@48 { - reg = <0x48 0x4>; - }; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; - pkh_otp: pkh_otp@60 { - reg = <0x60 0x20>; - }; - ethernet_mac_address: mac@e4 { - reg = <0xe4 0x8>; - st,non-secure-otp; + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; }; - }; - - etzpc: etzpc@5c007000 { - compatible = "st,stm32-etzpc"; - reg = <0x5C007000 0x400>; - clocks = <&rcc TZPC>; - status = "disabled"; - secure-status = "okay"; - }; - - i2c6: i2c@5c009000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c009000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x20>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - tamp: tamp@5c00a000 { - compatible = "st,stm32-tamp", "syscon", "simple-mfd"; - reg = <0x5c00a000 0x400>; - clocks = <&rcc RTCAPB>; - }; - - /* - * Break node order to solve dependency probe issue between - * pinctrl and exti. - */ - pinctrl: pinctrl@50002000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-pinctrl"; - ranges = <0 0x50002000 0xa400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; - gpioa: gpio@50002000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA>; - st,bank-name = "GPIOA"; - status = "disabled"; + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; }; - gpiob: gpio@50003000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOB>; - st,bank-name = "GPIOB"; + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; status = "disabled"; - }; - gpioc: gpio@50004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOC>; - st,bank-name = "GPIOC"; - status = "disabled"; + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; }; - gpiod: gpio@50005000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x400>; - clocks = <&rcc GPIOD>; - st,bank-name = "GPIOD"; + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; }; - gpioe: gpio@50006000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x400>; - clocks = <&rcc GPIOE>; - st,bank-name = "GPIOE"; + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; status = "disabled"; }; - gpiof: gpio@50007000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x400>; - clocks = <&rcc GPIOF>; - st,bank-name = "GPIOF"; - status = "disabled"; + sai4: sai@50027000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50027000 0x400>; + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = ; + resets = <&rcc SAI4_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; + status = "disabled"; + + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; + status = "disabled"; + }; + + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; + status = "disabled"; + }; }; - gpiog: gpio@50008000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x400>; - clocks = <&rcc GPIOG>; - st,bank-name = "GPIOG"; - status = "disabled"; + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; + status = "disabled"; + }; + + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; + status = "disabled"; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; }; - gpioh: gpio@50009000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x400>; - clocks = <&rcc GPIOH>; - st,bank-name = "GPIOH"; - status = "disabled"; + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; + status = "disabled"; + }; + + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4>; + snps,mixed-burst; + snps,pbl = <2>; + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; + status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; }; - gpioi: gpio@5000a000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x400>; - clocks = <&rcc GPIOI>; - st,bank-name = "GPIOI"; + usart1: serial@5c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x5c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + wakeup-source; + access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; status = "disabled"; }; - gpioj: gpio@5000b000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x400>; - clocks = <&rcc GPIOJ>; - st,bank-name = "GPIOJ"; + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = ; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; + status = "disabled"; + }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; + i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; status = "disabled"; }; - gpiok: gpio@5000c000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xa000 0x400>; - clocks = <&rcc GPIOK>; - st,bank-name = "GPIOK"; + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5C003000 0x400>; + interrupts = ; + clocks = <&rcc IWDG1>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; status = "disabled"; }; - }; - - pinctrl_z: pinctrl@54004000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-z-pinctrl"; - ranges = <0 0x54004000 0x400>; - pins-are-numbered; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - gpioz: gpio@54004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x400>; - clocks = <&rcc GPIOZ>; - st,bank-name = "GPIOZ"; - st,bank-ioport = <11>; + i2c6: i2c@5c009000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; + i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; status = "disabled"; }; }; diff --git a/core/arch/arm/dts/stm32mp153.dtsi b/core/arch/arm/dts/stm32mp153.dtsi index 486084e0b80..3578195afc3 100644 --- a/core/arch/arm/dts/stm32mp153.dtsi +++ b/core/arch/arm/dts/stm32mp153.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (C) STMicroelectronics 2019-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -28,32 +28,34 @@ , ; }; +}; - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; +&etzpc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + access-controllers = <&etzpc STM32MP1_ETZPC_TT_FDCAN_ID>; + status = "disabled"; + }; - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + access-controllers = <&etzpc STM32MP1_ETZPC_TT_FDCAN_ID>; + status = "disabled"; }; }; diff --git a/core/arch/arm/dts/stm32mp15xc.dtsi b/core/arch/arm/dts/stm32mp15xc.dtsi index b06a55a2fa1..0cc03124bac 100644 --- a/core/arch/arm/dts/stm32mp15xc.dtsi +++ b/core/arch/arm/dts/stm32mp15xc.dtsi @@ -1,18 +1,17 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (C) STMicroelectronics 2019-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ -/ { - soc { - cryp1: cryp@54001000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54001000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_CRYP1_ID>; + status = "disabled"; }; }; From 0a60c07ee8f0b0b38e29b7b33cb0dbe37333f63b Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 08/14] dts: stm32: define ETZPC as an access controller for stm32mp13 platforms ETZPC is a firewall controller. Add the access-controllers property to all ETZPC sub-nodes on stm32mp13 platforms. Also add the "simple-bus" compatible for backward compatibility and "#access-controllers-cells" to the ETZPC node. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/dts/stm32mp131.dtsi | 26 +++++++++++++++++++++++--- core/arch/arm/dts/stm32mp135.dtsi | 3 ++- core/arch/arm/dts/stm32mp13xc.dtsi | 5 ++++- core/arch/arm/dts/stm32mp13xf.dtsi | 5 ++++- 4 files changed, 33 insertions(+), 6 deletions(-) diff --git a/core/arch/arm/dts/stm32mp131.dtsi b/core/arch/arm/dts/stm32mp131.dtsi index 1cf2bd51ea3..45aca5b9d30 100644 --- a/core/arch/arm/dts/stm32mp131.dtsi +++ b/core/arch/arm/dts/stm32mp131.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved + * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -396,11 +396,12 @@ }; etzpc: etzpc@5c007000 { - compatible = "st,stm32-etzpc", "firewall-bus"; + compatible = "st,stm32-etzpc", "simple-bus"; reg = <0x5C007000 0x400>; clocks = <&rcc TZPC>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; adc_2: adc@48004000 { reg = <0x48004000 0x400>; @@ -412,6 +413,7 @@ #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; status = "disabled"; adc2: adc@0 { @@ -452,6 +454,7 @@ interrupts = ; clocks = <&rcc USART1_K>; resets = <&rcc USART1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; status = "disabled"; }; @@ -461,6 +464,7 @@ interrupts = ; clocks = <&rcc USART2_K>; resets = <&rcc USART2_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; status = "disabled"; }; @@ -473,6 +477,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x4>; i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; status = "disabled"; }; @@ -485,6 +490,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x8>; i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; status = "disabled"; }; @@ -497,6 +503,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x10>; i2c-analog-filter; + access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; status = "disabled"; }; @@ -508,6 +515,8 @@ interrupts = ; clocks = <&rcc TIM12_K>; clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; + status = "disabled"; counter { compatible = "st,stm32-timer-counter"; @@ -522,6 +531,7 @@ reg = <0x4c008000 0x400>; clocks = <&rcc TIM13_K>; clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; status = "disabled"; }; @@ -532,6 +542,7 @@ reg = <0x4c009000 0x400>; clocks = <&rcc TIM14_K>; clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; status = "disabled"; }; @@ -543,6 +554,7 @@ interrupts = ; clocks = <&rcc TIM15_K>; clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; status = "disabled"; counter { @@ -558,8 +570,8 @@ reg = <0x4c00b000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; status = "disabled"; - }; timers17: timer@4c00c000 { @@ -569,6 +581,7 @@ reg = <0x4c00c000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int"; + access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; status = "disabled"; }; @@ -580,6 +593,7 @@ interrupts = ; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; status = "disabled"; }; @@ -591,6 +605,7 @@ interrupts = ; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; status = "disabled"; counter { @@ -606,6 +621,7 @@ regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2500000>; clocks = <&rcc VREF>; + access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; status = "disabled"; }; @@ -615,6 +631,7 @@ interrupts = ; clocks = <&rcc HASH1>; resets = <&rcc HASH1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; status = "disabled"; }; @@ -623,6 +640,7 @@ reg = <0x54004000 0x400>; clocks = <&rcc RNG1_K>; resets = <&rcc RNG1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; status = "disabled"; }; @@ -632,12 +650,14 @@ interrupts = ; clocks = <&rcc IWDG1>, <&rcc CK_LSI>; clock-names = "pclk", "lsi"; + access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; status = "disabled"; }; stgen: stgen@5c008000 { compatible = "st,stm32-stgen"; reg = <0x5C008000 0x1000>; + access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; }; }; }; diff --git a/core/arch/arm/dts/stm32mp135.dtsi b/core/arch/arm/dts/stm32mp135.dtsi index 1e790f9df1b..ca795da52aa 100644 --- a/core/arch/arm/dts/stm32mp135.dtsi +++ b/core/arch/arm/dts/stm32mp135.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -17,6 +17,7 @@ clocks = <&rcc LTDC_PX>; clock-names = "lcd"; resets = <&rcc LTDC_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_LTDC_ID>; status = "disabled"; }; }; diff --git a/core/arch/arm/dts/stm32mp13xc.dtsi b/core/arch/arm/dts/stm32mp13xc.dtsi index f7ff57bb62f..b073f8442dc 100644 --- a/core/arch/arm/dts/stm32mp13xc.dtsi +++ b/core/arch/arm/dts/stm32mp13xc.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -11,6 +11,7 @@ interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_CRYP_ID>; status = "disabled"; }; @@ -21,6 +22,7 @@ clocks = <&rcc SAES_K>, <&rcc RNG1_K>; clock-names = "bus", "rng"; resets = <&rcc SAES_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_SAES_ID>; status = "disabled"; }; @@ -30,6 +32,7 @@ interrupts = ; clocks = <&rcc PKA>; resets = <&rcc PKA_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_PKA_ID>; status = "disabled"; }; }; diff --git a/core/arch/arm/dts/stm32mp13xf.dtsi b/core/arch/arm/dts/stm32mp13xf.dtsi index f7ff57bb62f..b073f8442dc 100644 --- a/core/arch/arm/dts/stm32mp13xf.dtsi +++ b/core/arch/arm/dts/stm32mp13xf.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -11,6 +11,7 @@ interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_CRYP_ID>; status = "disabled"; }; @@ -21,6 +22,7 @@ clocks = <&rcc SAES_K>, <&rcc RNG1_K>; clock-names = "bus", "rng"; resets = <&rcc SAES_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_SAES_ID>; status = "disabled"; }; @@ -30,6 +32,7 @@ interrupts = ; clocks = <&rcc PKA>; resets = <&rcc PKA_R>; + access-controllers = <&etzpc STM32MP1_ETZPC_PKA_ID>; status = "disabled"; }; }; From a6b9cd498c62698f446e6b9b5629a6c7160d493a Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 09/14] plat-stm32mp1: default enable CFG_DRIVERS_FIREWALL Default enable the CFG_DRIVERS_FIREWALL switch that is used to enable the support of the firewall framework. On this platform, only the ETZPC is a firewall controller for now. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/plat-stm32mp1/conf.mk | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/core/arch/arm/plat-stm32mp1/conf.mk b/core/arch/arm/plat-stm32mp1/conf.mk index 782020221a4..83011297063 100644 --- a/core/arch/arm/plat-stm32mp1/conf.mk +++ b/core/arch/arm/plat-stm32mp1/conf.mk @@ -411,3 +411,8 @@ CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) $(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) endif + +CFG_DRIVERS_FIREWALL ?= y +ifeq ($(CFG_STM32_ETZPC),y) +$(call force,CFG_DRIVERS_FIREWALL,y) +endif From 18ce76c9662b49ccd5d0dab43590329098bc7aa7 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 10/14] drivers: stm32_etzpc: update driver to set ETZPC configuration from DT Remove old implementation where the ETZPC configuration was a hard coded table in the shared resources file and use the device tree to get it. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/plat-stm32mp1/main.c | 85 +--- .../arch/arm/plat-stm32mp1/shared_resources.c | 65 ---- core/drivers/stm32_etzpc.c | 365 +++++++++++------- core/include/drivers/stm32_etzpc.h | 47 +-- 4 files changed, 233 insertions(+), 329 deletions(-) diff --git a/core/arch/arm/plat-stm32mp1/main.c b/core/arch/arm/plat-stm32mp1/main.c index c0dd7c1c94e..36031ace62e 100644 --- a/core/arch/arm/plat-stm32mp1/main.c +++ b/core/arch/arm/plat-stm32mp1/main.c @@ -164,84 +164,6 @@ void boot_secondary_init_intc(void) stm32mp_register_online_cpu(); } -#ifdef CFG_STM32MP13 -#ifdef CFG_STM32_ETZPC -/* Configure ETZPC cell and lock it when resource is secure */ -static void config_lock_decprot(uint32_t decprot_id, - enum etzpc_decprot_attributes decprot_attr) -{ - etzpc_configure_decprot(decprot_id, decprot_attr); - - if (decprot_attr == ETZPC_DECPROT_S_RW) - etzpc_lock_decprot(decprot_id); -} - -static TEE_Result set_etzpc_secure_configuration(void) -{ - config_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_DDRCTRLPHY_ID, - ETZPC_DECPROT_NS_R_S_W); - - /* Configure ETZPC with peripheral registering */ - config_lock_decprot(STM32MP1_ETZPC_ADC1_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_ADC2_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_CRYP_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_DCMIPP_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_ETH1_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_ETH2_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_FMC_ID, ETZPC_DECPROT_NS_RW); - /* HASH is secure */ - config_lock_decprot(STM32MP1_ETZPC_HASH_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_I2C3_ID, ETZPC_DECPROT_NS_RW); - /* I2C4 is secure */ - config_lock_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_I2C5_ID, ETZPC_DECPROT_NS_RW); - /* IWDG1 is secure */ - config_lock_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_LPTIM2_ID, ETZPC_DECPROT_NS_RW); - /* LPTIM3 is secure */ - config_lock_decprot(STM32MP1_ETZPC_LPTIM3_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_LTDC_ID, ETZPC_DECPROT_NS_RW); - /* MCE is secure */ - config_lock_decprot(STM32MP1_ETZPC_MCE_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_OTG_ID, ETZPC_DECPROT_NS_RW); - /* PKA is secure */ - config_lock_decprot(STM32MP1_ETZPC_PKA_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_QSPI_ID, ETZPC_DECPROT_NS_RW); - /* RNG is secure */ - config_lock_decprot(STM32MP1_ETZPC_RNG_ID, ETZPC_DECPROT_S_RW); - /* SAES is secure */ - config_lock_decprot(STM32MP1_ETZPC_SAES_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_SDMMC1_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_SDMMC2_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_SPI4_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_SPI5_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_SRAM1_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_SRAM2_ID, ETZPC_DECPROT_NS_RW); - /* SRAM3 is secure */ - config_lock_decprot(STM32MP1_ETZPC_SRAM3_ID, ETZPC_DECPROT_S_RW); - /* STGENC is secure */ - config_lock_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); - /* TIM12 is secure */ - config_lock_decprot(STM32MP1_ETZPC_TIM12_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_TIM13_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_TIM14_ID, ETZPC_DECPROT_NS_RW); - /* TIM15 is secure */ - config_lock_decprot(STM32MP1_ETZPC_TIM15_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_TIM16_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_TIM17_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_USART2_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_USBPHYCTRL_ID, ETZPC_DECPROT_NS_RW); - config_lock_decprot(STM32MP1_ETZPC_VREFBUF_ID, ETZPC_DECPROT_NS_RW); - - return TEE_SUCCESS; -} - -driver_init_late(set_etzpc_secure_configuration); -#endif /* CFG_STM32_ETZPC */ -#endif /* CFG_STM32MP13 */ - #ifdef CFG_STM32MP15 /* * This concerns OP-TEE pager for STM32MP1 to use secure internal @@ -380,12 +302,8 @@ service_init_late(init_stm32mp15_secure_srams); static TEE_Result init_stm32mp1_drivers(void) { - /* Secure internal memories for the platform, once ETZPC is ready */ - etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); - etzpc_lock_tzma(0); - +#if defined(CFG_STM32_ETZPC) etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); - etzpc_lock_tzma(1); if (SYSRAM_SIZE > SYSRAM_SEC_SIZE) { size_t nsec_size = SYSRAM_SIZE - SYSRAM_SEC_SIZE; @@ -398,6 +316,7 @@ static TEE_Result init_stm32mp1_drivers(void) /* Clear content from the non-secure part */ memset(va, 0, nsec_size); } +#endif /* CFG_STM32_ETZPC */ return TEE_SUCCESS; } diff --git a/core/arch/arm/plat-stm32mp1/shared_resources.c b/core/arch/arm/plat-stm32mp1/shared_resources.c index 3717aebd836..8c86d675deb 100644 --- a/core/arch/arm/plat-stm32mp1/shared_resources.c +++ b/core/arch/arm/plat-stm32mp1/shared_resources.c @@ -593,70 +593,6 @@ static bool mckprot_resource(enum stm32mp_shres id) } } -#ifdef CFG_STM32_ETZPC -static enum etzpc_decprot_attributes shres2decprot_attr(enum stm32mp_shres id) -{ - if (!stm32mp_periph_is_secure(id)) - return ETZPC_DECPROT_NS_RW; - - if (mckprot_resource(id)) - return ETZPC_DECPROT_MCU_ISOLATION; - - return ETZPC_DECPROT_S_RW; -} - -/* Configure ETZPC cell and lock it when resource is secure */ -static void config_lock_decprot(uint32_t decprot_id, - enum etzpc_decprot_attributes decprot_attr) -{ - etzpc_configure_decprot(decprot_id, decprot_attr); - - if (decprot_attr == ETZPC_DECPROT_S_RW) - etzpc_lock_decprot(decprot_id); -} - -static void set_etzpc_secure_configuration(void) -{ - /* Some peripherals shall be secure */ - config_lock_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); - config_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_NS_R_S_W); - config_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_NS_R_S_W); - - /* Configure ETZPC with peripheral registering */ - config_lock_decprot(STM32MP1_ETZPC_IWDG1_ID, - shres2decprot_attr(STM32MP1_SHRES_IWDG1)); - config_lock_decprot(STM32MP1_ETZPC_USART1_ID, - shres2decprot_attr(STM32MP1_SHRES_USART1)); - config_lock_decprot(STM32MP1_ETZPC_SPI6_ID, - shres2decprot_attr(STM32MP1_SHRES_SPI6)); - config_lock_decprot(STM32MP1_ETZPC_I2C4_ID, - shres2decprot_attr(STM32MP1_SHRES_I2C4)); - config_lock_decprot(STM32MP1_ETZPC_RNG1_ID, - shres2decprot_attr(STM32MP1_SHRES_RNG1)); - config_lock_decprot(STM32MP1_ETZPC_HASH1_ID, - shres2decprot_attr(STM32MP1_SHRES_HASH1)); - config_lock_decprot(STM32MP1_ETZPC_CRYP1_ID, - shres2decprot_attr(STM32MP1_SHRES_CRYP1)); - config_lock_decprot(STM32MP1_ETZPC_I2C6_ID, - shres2decprot_attr(STM32MP1_SHRES_I2C6)); - - config_lock_decprot(STM32MP1_ETZPC_SRAM1_ID, - shres2decprot_attr(STM32MP1_SHRES_SRAM1)); - config_lock_decprot(STM32MP1_ETZPC_SRAM2_ID, - shres2decprot_attr(STM32MP1_SHRES_SRAM2)); - config_lock_decprot(STM32MP1_ETZPC_SRAM3_ID, - shres2decprot_attr(STM32MP1_SHRES_SRAM3)); - config_lock_decprot(STM32MP1_ETZPC_SRAM4_ID, - shres2decprot_attr(STM32MP1_SHRES_SRAM4)); -} -#else -static void set_etzpc_secure_configuration(void) -{ - /* Nothing to do */ -} -#endif - static void rcc_secure_configuration(void) { bool secure = stm32_rcc_is_secure(); @@ -740,7 +676,6 @@ static TEE_Result stm32mp1_init_final_shres(void) shres2str_id(id), id, shres2str_state(*state)); } - set_etzpc_secure_configuration(); if (IS_ENABLED(CFG_STM32_GPIO)) { set_gpio_secure_configuration(); register_pm_driver_cb(gpioz_pm, NULL, diff --git a/core/drivers/stm32_etzpc.c b/core/drivers/stm32_etzpc.c index 19c7d708ec1..3a7a927cf87 100644 --- a/core/drivers/stm32_etzpc.c +++ b/core/drivers/stm32_etzpc.c @@ -1,43 +1,38 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2017-2019, STMicroelectronics + * Copyright (c) 2017-2024, STMicroelectronics */ /* * STM32 ETPZC acts as a firewall on stm32mp SoC peripheral interfaces and * internal memories. The driver expects a single instance of the controller * in the platform. - * - * The driver API is defined in header file stm32_etzpc.h. - * - * Driver registers a PM callback for restoration of the access permissions - * when it resumes. */ #include +#include #include +#include #include #include #include #include #include -#include #include #include +#include #include #include +#include #include -/* Devicetree compatibility */ -#define ETZPC_COMPAT "st,stm32-etzpc" - /* ID Registers */ -#define ETZPC_TZMA0_SIZE 0x000U -#define ETZPC_DECPROT0 0x010U -#define ETZPC_DECPROT_LOCK0 0x030U -#define ETZPC_HWCFGR 0x3F0U -#define ETZPC_VERR 0x3F4U +#define ETZPC_TZMA0_SIZE U(0x000) +#define ETZPC_DECPROT0 U(0x010) +#define ETZPC_DECPROT_LOCK0 U(0x030) +#define ETZPC_HWCFGR U(0x3F0) +#define ETZPC_VERR U(0x3F4) /* ID Registers fields */ #define ETZPC_TZMA0_SIZE_LOCK BIT(31) @@ -48,12 +43,12 @@ #define ETZPC_HWCFGR_NUM_PER_SEC_SHIFT 8 #define ETZPC_HWCFGR_NUM_AHB_SEC_MASK GENMASK_32(23, 16) #define ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT 16 -#define ETZPC_HWCFGR_CHUNCKS1N4_MASK GENMASK_32(31, 24) -#define ETZPC_HWCFGR_CHUNCKS1N4_SHIFT 24 +#define ETZPC_HWCFGR_CHUNKS1N4_MASK GENMASK_32(31, 24) +#define ETZPC_HWCFGR_CHUNKS1N4_SHIFT 24 #define DECPROT_SHIFT 1 -#define IDS_PER_DECPROT_REGS 16U -#define IDS_PER_DECPROT_LOCK_REGS 32U +#define IDS_PER_DECPROT_REGS U(16) +#define IDS_PER_DECPROT_LOCK_REGS U(32) /* * Implementation uses uint8_t to store each securable DECPROT configuration @@ -66,67 +61,114 @@ #define TZMA_PM_VALUE_MASK GENMASK_32(9, 0) /* - * @base - iobase for interface base address - * @num_tzma - number of TZMA zone, read from the hardware - * @num_ahb_sec - number of securable AHB master zone, read from the hardware - * @num_per_sec - number of securable AHB & APB periphs, read from the hardware - * @periph_cfg - Backup for restoring DECPROT when resuming (PERIH_PM_*) - * @tzma_cfg - Backup for restoring TZMA when resuming (TZMA_PM_*) + * struct stm32_etzpc_platdata - Driver data set at initialization + * + * @name: Name of the peripheral + * @clk: ETZPC clock + * @periph_cfg: Peripheral DECPROT configuration + * @tzma_cfg: TZMA configuration + * @base: ETZPC IOMEM base address */ -struct etzpc_instance { +struct stm32_etzpc_platdata { + char *name; + struct clk *clk; + uint8_t *periph_cfg; + uint16_t *tzma_cfg; struct io_pa_va base; +}; + +/* + * struct stm32_etzpc_driver_data - configuration data from the hardware + * + * @num_tzma: Number of TZMA zones, read from the hardware + * @num_per_sec: Number of securable AHB & APB periphs, read from the hardware + * @num_ahb_sec: Number of securable AHB master zones, read from the hardware + */ +struct stm32_etzpc_driver_data { unsigned int num_tzma; unsigned int num_per_sec; unsigned int num_ahb_sec; - uint8_t *periph_cfg; - uint16_t *tzma_cfg; }; -/* Only 1 instance of the ETZPC is expected per platform */ -static struct etzpc_instance etzpc_dev; +/* + * struct etzpc_device - ETZPC device driver instance + * @pdata: Platform data set during initialization + * @ddata: Device configuration data from the hardware + * @lock: Access contention + */ +struct etzpc_device { + struct stm32_etzpc_platdata pdata; + struct stm32_etzpc_driver_data ddata; + unsigned int lock; +}; + +static struct etzpc_device *etzpc_device; + +static uint32_t etzpc_lock(void) +{ + return cpu_spin_lock_xsave(&etzpc_device->lock); +} -static vaddr_t etzpc_base(void) +static void etzpc_unlock(uint32_t exceptions) { - return io_pa_or_va_secure(&etzpc_dev.base, 1); + cpu_spin_unlock_xrestore(&etzpc_device->lock, exceptions); } -static bool __maybe_unused valid_decprot_id(unsigned int id) +static bool valid_decprot_id(unsigned int id) { - return id < etzpc_dev.num_per_sec; + return id < etzpc_device->ddata.num_per_sec; } static bool __maybe_unused valid_tzma_id(unsigned int id) { - return id < etzpc_dev.num_tzma; + return id < etzpc_device->ddata.num_tzma; +} + +static enum etzpc_decprot_attributes etzpc_binding2decprot(uint32_t mode) +{ + switch (mode) { + case DECPROT_S_RW: + return ETZPC_DECPROT_S_RW; + case DECPROT_NS_R_S_W: + return ETZPC_DECPROT_NS_R_S_W; +#ifdef CFG_STM32MP15 + case DECPROT_MCU_ISOLATION: + return ETZPC_DECPROT_MCU_ISOLATION; +#endif + case DECPROT_NS_RW: + return ETZPC_DECPROT_NS_RW; + default: + panic(); + } } -void etzpc_configure_decprot(uint32_t decprot_id, - enum etzpc_decprot_attributes decprot_attr) +static void etzpc_configure_decprot(uint32_t decprot_id, + enum etzpc_decprot_attributes attr) { - size_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS); + size_t offset = U(4) * (decprot_id / IDS_PER_DECPROT_REGS); uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; - uint32_t masked_decprot = (uint32_t)decprot_attr & ETZPC_DECPROT0_MASK; - vaddr_t base = etzpc_base(); + uint32_t masked_decprot = (uint32_t)attr & ETZPC_DECPROT0_MASK; + vaddr_t base = etzpc_device->pdata.base.va; + unsigned int exceptions = 0; assert(valid_decprot_id(decprot_id)); + DMSG("ID : %"PRIu32", CONF %d", decprot_id, attr); + + exceptions = etzpc_lock(); + io_clrsetbits32(base + ETZPC_DECPROT0 + offset, ETZPC_DECPROT0_MASK << shift, masked_decprot << shift); - /* Save for PM */ - assert((decprot_attr & ~PERIPH_PM_ATTR_MASK) == 0); - COMPILE_TIME_ASSERT(ETZPC_DECPROT_MAX <= UINT8_MAX); - - etzpc_dev.periph_cfg[decprot_id] &= ~PERIPH_PM_ATTR_MASK; - etzpc_dev.periph_cfg[decprot_id] |= (uint8_t)decprot_attr; + etzpc_unlock(exceptions); } enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id) { - size_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS); + size_t offset = U(4) * (decprot_id / IDS_PER_DECPROT_REGS); uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; uint32_t value = 0; assert(valid_decprot_id(decprot_id)); @@ -137,25 +179,27 @@ enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id) return (enum etzpc_decprot_attributes)value; } -void etzpc_lock_decprot(uint32_t decprot_id) +static void etzpc_lock_decprot(uint32_t decprot_id) { - size_t offset = 4U * (decprot_id / IDS_PER_DECPROT_LOCK_REGS); + size_t offset = U(4) * (decprot_id / IDS_PER_DECPROT_LOCK_REGS); uint32_t mask = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS); - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; + uint32_t exceptions = 0; assert(valid_decprot_id(decprot_id)); + exceptions = etzpc_lock(); + io_write32(base + offset + ETZPC_DECPROT_LOCK0, mask); - /* Save for PM */ - etzpc_dev.periph_cfg[decprot_id] |= PERIPH_PM_LOCK_BIT; + etzpc_unlock(exceptions); } -bool etzpc_get_lock_decprot(uint32_t decprot_id) +static bool decprot_is_locked(uint32_t decprot_id) { - size_t offset = 4U * (decprot_id / IDS_PER_DECPROT_LOCK_REGS); + size_t offset = U(4) * (decprot_id / IDS_PER_DECPROT_LOCK_REGS); uint32_t mask = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS); - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; assert(valid_decprot_id(decprot_id)); @@ -165,45 +209,47 @@ bool etzpc_get_lock_decprot(uint32_t decprot_id) void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value) { size_t offset = sizeof(uint32_t) * tzma_id; - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; + uint32_t exceptions = 0; assert(valid_tzma_id(tzma_id)); + exceptions = etzpc_lock(); + io_write32(base + ETZPC_TZMA0_SIZE + offset, tzma_value); - /* Save for PM */ - assert((tzma_value & ~TZMA_PM_VALUE_MASK) == 0); - etzpc_dev.tzma_cfg[tzma_id] &= ~TZMA_PM_VALUE_MASK; - etzpc_dev.tzma_cfg[tzma_id] |= tzma_value; + etzpc_unlock(exceptions); } -uint16_t etzpc_get_tzma(uint32_t tzma_id) +static uint16_t etzpc_get_tzma(uint32_t tzma_id) { size_t offset = sizeof(uint32_t) * tzma_id; - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; assert(valid_tzma_id(tzma_id)); return io_read32(base + ETZPC_TZMA0_SIZE + offset); } -void etzpc_lock_tzma(uint32_t tzma_id) +static void etzpc_lock_tzma(uint32_t tzma_id) { size_t offset = sizeof(uint32_t) * tzma_id; - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; + uint32_t exceptions = 0; assert(valid_tzma_id(tzma_id)); + exceptions = etzpc_lock(); + io_setbits32(base + ETZPC_TZMA0_SIZE + offset, ETZPC_TZMA0_SIZE_LOCK); - /* Save for PM */ - etzpc_dev.tzma_cfg[tzma_id] |= TZMA_PM_LOCK_BIT; + etzpc_unlock(exceptions); } -bool etzpc_get_lock_tzma(uint32_t tzma_id) +static bool tzma_is_locked(uint32_t tzma_id) { size_t offset = sizeof(uint32_t) * tzma_id; - vaddr_t base = etzpc_base(); + vaddr_t base = etzpc_device->pdata.base.va; assert(valid_tzma_id(tzma_id)); @@ -212,31 +258,46 @@ bool etzpc_get_lock_tzma(uint32_t tzma_id) } static TEE_Result etzpc_pm(enum pm_op op, unsigned int pm_hint __unused, - const struct pm_callback_handle *pm_handle) + const struct pm_callback_handle *pm_handle __unused) { - struct etzpc_instance *dev = NULL; + struct stm32_etzpc_driver_data *ddata = &etzpc_device->ddata; + struct stm32_etzpc_platdata *pdata = &etzpc_device->pdata; unsigned int n = 0; - if (op != PM_OP_RESUME) - return TEE_SUCCESS; + if (op == PM_OP_SUSPEND) { + for (n = 0; n < ddata->num_per_sec; n++) { + pdata->periph_cfg[n] = + (uint8_t)etzpc_get_decprot(n); + if (decprot_is_locked(n)) + pdata->periph_cfg[n] |= PERIPH_PM_LOCK_BIT; + } + + for (n = 0; n < ddata->num_tzma; n++) { + pdata->tzma_cfg[n] = + (uint8_t)etzpc_get_tzma(n); + if (tzma_is_locked(n)) + pdata->tzma_cfg[n] |= TZMA_PM_LOCK_BIT; + } - dev = (struct etzpc_instance *)PM_CALLBACK_GET_HANDLE(pm_handle); + return TEE_SUCCESS; + } - for (n = 0; n < dev->num_per_sec; n++) { - unsigned int attr = dev->periph_cfg[n] & PERIPH_PM_ATTR_MASK; + /* PM_OP_RESUME */ + for (n = 0; n < ddata->num_per_sec; n++) { + unsigned int attr = pdata->periph_cfg[n] & PERIPH_PM_ATTR_MASK; etzpc_configure_decprot(n, (enum etzpc_decprot_attributes)attr); - if (dev->periph_cfg[n] & PERIPH_PM_LOCK_BIT) + if (pdata->periph_cfg[n] & PERIPH_PM_LOCK_BIT) etzpc_lock_decprot(n); } - for (n = 0; n < dev->num_tzma; n++) { - uint16_t value = dev->tzma_cfg[n] & TZMA_PM_VALUE_MASK; + for (n = 0; n < ddata->num_tzma; n++) { + uint16_t value = pdata->tzma_cfg[n] & TZMA_PM_VALUE_MASK; etzpc_configure_tzma(n, value); - if (dev->tzma_cfg[n] & TZMA_PM_LOCK_BIT) + if (pdata->tzma_cfg[n] & TZMA_PM_LOCK_BIT) etzpc_lock_tzma(n); } @@ -244,85 +305,113 @@ static TEE_Result etzpc_pm(enum pm_op op, unsigned int pm_hint __unused, } DECLARE_KEEP_PAGER(etzpc_pm); -static void init_pm(struct etzpc_instance *dev) +static void stm32_etzpc_set_driverdata(void) { - unsigned int n = 0; - - dev->periph_cfg = calloc(dev->num_per_sec, sizeof(*dev->periph_cfg)); - dev->tzma_cfg = calloc(dev->num_tzma, sizeof(*dev->tzma_cfg)); - if (!dev->periph_cfg || !dev->tzma_cfg) - panic(); + struct stm32_etzpc_driver_data *ddata = &etzpc_device->ddata; + vaddr_t base = etzpc_device->pdata.base.va; + uint32_t reg = io_read32(base + ETZPC_HWCFGR); + + ddata->num_tzma = (reg & ETZPC_HWCFGR_NUM_TZMA_MASK) >> + ETZPC_HWCFGR_NUM_TZMA_SHIFT; + ddata->num_per_sec = (reg & ETZPC_HWCFGR_NUM_PER_SEC_MASK) >> + ETZPC_HWCFGR_NUM_PER_SEC_SHIFT; + ddata->num_ahb_sec = (reg & ETZPC_HWCFGR_NUM_AHB_SEC_MASK) >> + ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT; + + DMSG("ETZPC revision 0x%02"PRIx8", per_sec %u, ahb_sec %u, tzma %u", + io_read8(base + ETZPC_VERR), + ddata->num_per_sec, ddata->num_ahb_sec, ddata->num_tzma); +} - for (n = 0; n < dev->num_per_sec; n++) { - dev->periph_cfg[n] = (uint8_t)etzpc_get_decprot(n); - if (etzpc_get_lock_decprot(n)) - dev->periph_cfg[n] |= PERIPH_PM_LOCK_BIT; +static void fdt_etzpc_conf_decprot(const void *fdt, int node) +{ + const fdt32_t *cuint = NULL; + size_t i = 0; + int len = 0; + + cuint = fdt_getprop(fdt, node, "st,decprot", &len); + if (!cuint) { + DMSG("No ETZPC DECPROT configuration in DT"); + return; } - for (n = 0; n < dev->num_tzma; n++) { - dev->tzma_cfg[n] = (uint8_t)etzpc_get_tzma(n); - if (etzpc_get_lock_tzma(n)) - dev->tzma_cfg[n] |= TZMA_PM_LOCK_BIT; - } + clk_enable(etzpc_device->pdata.clk); - register_pm_core_service_cb(etzpc_pm, dev, "stm32-etzpc"); -} + for (i = 0; i < len / sizeof(uint32_t); i++) { + uint32_t value = fdt32_to_cpu(cuint[i]); + uint32_t id = value & ETZPC_ID_MASK; + uint32_t mode = (value & ETZPC_MODE_MASK) >> ETZPC_MODE_SHIFT; + bool lock = value & ETZPC_LOCK_MASK; + enum etzpc_decprot_attributes attr = ETZPC_DECPROT_MAX; -struct etzpc_hwcfg { - unsigned int num_tzma; - unsigned int num_per_sec; - unsigned int num_ahb_sec; - unsigned int chunk_size; -}; + if (!valid_decprot_id(id)) { + DMSG("Invalid DECPROT %"PRIu32, id); + panic(); + } -static void get_hwcfg(struct etzpc_hwcfg *hwcfg) -{ - uint32_t reg = io_read32(etzpc_base() + ETZPC_HWCFGR); - - hwcfg->num_tzma = (reg & ETZPC_HWCFGR_NUM_TZMA_MASK) >> - ETZPC_HWCFGR_NUM_TZMA_SHIFT; - hwcfg->num_per_sec = (reg & ETZPC_HWCFGR_NUM_PER_SEC_MASK) >> - ETZPC_HWCFGR_NUM_PER_SEC_SHIFT; - hwcfg->num_ahb_sec = (reg & ETZPC_HWCFGR_NUM_AHB_SEC_MASK) >> - ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT; - hwcfg->chunk_size = (reg & ETZPC_HWCFGR_CHUNCKS1N4_MASK) >> - ETZPC_HWCFGR_CHUNCKS1N4_SHIFT; + attr = etzpc_binding2decprot(mode); + etzpc_configure_decprot(id, attr); + + if (lock) + etzpc_lock_decprot(id); + } + + clk_disable(etzpc_device->pdata.clk); } -static void init_device_from_hw_config(struct etzpc_instance *dev, - paddr_t pbase) +static TEE_Result init_etzpc_from_dt(const void *fdt, int node) { - struct etzpc_hwcfg hwcfg = { }; + TEE_Result res = TEE_ERROR_GENERIC; + struct dt_node_info etzpc_info = { }; + int len = 0; + + fdt_fill_device_info(fdt, &etzpc_info, node); + if (etzpc_info.reg == DT_INFO_INVALID_REG || + etzpc_info.reg_size == DT_INFO_INVALID_REG_SIZE) + return TEE_ERROR_ITEM_NOT_FOUND; - assert(!dev->base.pa && cpu_mmu_enabled()); - dev->base.pa = pbase; - dev->base.va = (vaddr_t)phys_to_virt(dev->base.pa, MEM_AREA_IO_SEC, 1); - assert(etzpc_base()); + etzpc_device->pdata.base.pa = etzpc_info.reg; + etzpc_device->pdata.name = strdup(fdt_get_name(fdt, node, &len)); + io_pa_or_va_secure(&etzpc_device->pdata.base, etzpc_info.reg_size); + res = clk_dt_get_by_index(fdt, node, 0, &etzpc_device->pdata.clk); + if (res) + return res; - get_hwcfg(&hwcfg); - dev->num_tzma = hwcfg.num_tzma; - dev->num_per_sec = hwcfg.num_per_sec; - dev->num_ahb_sec = hwcfg.num_ahb_sec; + stm32_etzpc_set_driverdata(); - DMSG("ETZPC revison 0x02%" PRIu8 ", per_sec %u, ahb_sec %u, tzma %u", - io_read8(etzpc_base() + ETZPC_VERR), - hwcfg.num_per_sec, hwcfg.num_ahb_sec, hwcfg.num_tzma); + etzpc_device->pdata.periph_cfg = + calloc(etzpc_device->ddata.num_per_sec, + sizeof(*etzpc_device->pdata.periph_cfg)); - init_pm(dev); + etzpc_device->pdata.tzma_cfg = + calloc(etzpc_device->ddata.num_tzma, + sizeof(*etzpc_device->pdata.tzma_cfg)); + if (!etzpc_device->pdata.periph_cfg || !etzpc_device->pdata.tzma_cfg) + return TEE_ERROR_OUT_OF_MEMORY; + + fdt_etzpc_conf_decprot(fdt, node); + + return TEE_SUCCESS; } static TEE_Result stm32_etzpc_probe(const void *fdt, int node, const void *compat_data __unused) { TEE_Result res = TEE_ERROR_GENERIC; - paddr_t pbase = 0; int subnode = 0; - pbase = fdt_reg_base_address(fdt, node); - if (pbase == DT_INFO_INVALID_REG) - panic(); - - init_device_from_hw_config(&etzpc_dev, pbase); + etzpc_device = calloc(1, sizeof(*etzpc_device)); + if (!etzpc_device) + panic("ETZPC probe failed"); + + res = init_etzpc_from_dt(fdt, node); + if (res) { + free(etzpc_device->pdata.periph_cfg); + free(etzpc_device->pdata.tzma_cfg); + free(etzpc_device->pdata.name); + free(etzpc_device); + return res; + } fdt_for_each_subnode(subnode, fdt, node) { res = dt_driver_maybe_add_probe_node(fdt, subnode); @@ -333,6 +422,8 @@ static TEE_Result stm32_etzpc_probe(const void *fdt, int node, } } + register_pm_core_service_cb(etzpc_pm, NULL, "stm32-etzpc"); + return TEE_SUCCESS; } diff --git a/core/include/drivers/stm32_etzpc.h b/core/include/drivers/stm32_etzpc.h index 48f0385a347..e49d30de6e4 100644 --- a/core/include/drivers/stm32_etzpc.h +++ b/core/include/drivers/stm32_etzpc.h @@ -18,17 +18,6 @@ enum etzpc_decprot_attributes { ETZPC_DECPROT_MAX = 4, }; -#define ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) -#define ETZPC_TZMA_ALL_NO_SECURE 0x0 - -/* - * Load a DECPROT configuration - * @decprot_id: ID that is the index of the DECPROT in the ETZPC interface - * @decprot_attr: Restriction access attributes - */ -void etzpc_configure_decprot(uint32_t decprot_id, - enum etzpc_decprot_attributes decprot_attr); - /* * Get the DECPROT attribute * @decprot_id: ID that is the index of the DECPROT in the ETZPC interface @@ -37,41 +26,11 @@ void etzpc_configure_decprot(uint32_t decprot_id, enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id); /* - * Lock access to the DECPROT attributes - * @decprot_id: ID that is the index of the DECPROT in the ETZPC interface - */ -void etzpc_lock_decprot(uint32_t decprot_id); - -/* - * Return the lock status of the target DECPROT - * @decprot_id: ID that is the index of the DECPROT in the ETZPC interface - */ -bool etzpc_get_lock_decprot(uint32_t decprot_id); - -/* - * Configure the target TZMA read only size + * Configure the target TZMA secure memory range * @tzma_id: ID that is the index of the TZMA in the ETZPC interface - * @tzma_value: Read-only size + * @tzma_value: Secure memory secure size in 4kByte page size. Note that this + * is an offset from the memory base address */ void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value); -/* - * Get the target TZMA read only size - * @tzma_id: ID that is the index of the TZMA in the ETZPC interface - * Return the size of read-only area - */ -uint16_t etzpc_get_tzma(uint32_t tzma_id); - -/* - * Lock the target TZMA - * @tzma_id: ID that is the index of the TZMA in the ETZPC interface - */ -void etzpc_lock_tzma(uint32_t tzma_id); - -/* - * Return the lock status of the target TZMA - * @tzma_id: ID that is the index of the TZMA in the ETZPC interface - * Return true if TZMA is locked, false otherwise - */ -bool etzpc_get_lock_tzma(uint32_t tzma_id); #endif /*__DRIVERS_STM32_ETZPC_H*/ From 38ecc5512d499d87adaa5fbf79671d2ef06e5059 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Tue, 8 Oct 2024 14:35:40 +0200 Subject: [PATCH 11/14] drivers: stm32_etzpc: move the stm32_etzpc driver to the firewall folder The ETZPC is a firewall controller. Therefore, move the stm32_etzpc driver to the firewall folder. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/drivers/{ => firewall}/stm32_etzpc.c | 0 core/drivers/firewall/sub.mk | 1 + core/drivers/sub.mk | 1 - 3 files changed, 1 insertion(+), 1 deletion(-) rename core/drivers/{ => firewall}/stm32_etzpc.c (100%) diff --git a/core/drivers/stm32_etzpc.c b/core/drivers/firewall/stm32_etzpc.c similarity index 100% rename from core/drivers/stm32_etzpc.c rename to core/drivers/firewall/stm32_etzpc.c diff --git a/core/drivers/firewall/sub.mk b/core/drivers/firewall/sub.mk index 93bd2eee5da..1dd5339ad5d 100644 --- a/core/drivers/firewall/sub.mk +++ b/core/drivers/firewall/sub.mk @@ -1,3 +1,4 @@ +srcs-$(CFG_STM32_ETZPC) += stm32_etzpc.c srcs-$(CFG_STM32_IAC) += stm32_iac.c srcs-$(CFG_STM32_RIF) += stm32_rif.c srcs-$(CFG_STM32_RIFSC) += stm32_rifsc.c diff --git a/core/drivers/sub.mk b/core/drivers/sub.mk index 1538bd6b898..3b0e8ca7fb7 100644 --- a/core/drivers/sub.mk +++ b/core/drivers/sub.mk @@ -35,7 +35,6 @@ srcs-$(CFG_ATMEL_TCB) += atmel_tcb.c srcs-$(CFG_AMLOGIC_UART) += amlogic_uart.c srcs-$(CFG_MVEBU_UART) += mvebu_uart.c srcs-$(CFG_STM32_BSEC) += stm32_bsec.c -srcs-$(CFG_STM32_ETZPC) += stm32_etzpc.c srcs-$(CFG_STM32_FMC) += stm32_fmc.c srcs-$(CFG_STM32_GPIO) += stm32_gpio.c srcs-$(CFG_STM32_HPDMA) += stm32_hpdma.c From 810b07a992d51e61cec21118d5316a98bf116662 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Tue, 8 Oct 2024 18:04:10 +0200 Subject: [PATCH 12/14] plat-stm32mp1: add CFG_STM32_ALLOW_UNSAFE_PROBE to probe unsafe peripherals Add CFG_STM32_ALLOW_UNSAFE_PROBE that allows to unsafely probe peripherals. This means that the firewall configuration will not be checked before probing a peripheral. Default enable this switch for DH platforms that use non-securable peripherals in OP-TEE. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/plat-stm32mp1/conf.mk | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/core/arch/arm/plat-stm32mp1/conf.mk b/core/arch/arm/plat-stm32mp1/conf.mk index 83011297063..efabb95ad12 100644 --- a/core/arch/arm/plat-stm32mp1/conf.mk +++ b/core/arch/arm/plat-stm32mp1/conf.mk @@ -58,6 +58,9 @@ flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ flavorlist-MP13 = $(flavor_dts_file-135F_DK) +flavorlist-dh-platforms = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ + $(flavor_dts_file-157C_DHCOM_PDK2) + ifneq ($(PLATFORM_FLAVOR),) ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) $(error Invalid platform flavor $(PLATFORM_FLAVOR)) @@ -89,6 +92,10 @@ ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) $(call force,CFG_STM32MP15,y) endif +ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-dh-platforms)),) +CFG_STM32_ALLOW_UNSAFE_PROBE ?= y +endif + # CFG_STM32MP1x switches are exclusive. # - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) # - CFG_STM32MP13 is enabled for STM32MP13x-* targets @@ -416,3 +423,6 @@ CFG_DRIVERS_FIREWALL ?= y ifeq ($(CFG_STM32_ETZPC),y) $(call force,CFG_DRIVERS_FIREWALL,y) endif + +# Allow probing of unsafe peripherals. Firewall config will not be checked +CFG_STM32_ALLOW_UNSAFE_PROBE ?= n From 6be9e120e574b1d4b22cc8a42b2b23947a514045 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 2 May 2024 16:51:17 +0200 Subject: [PATCH 13/14] drivers: stm32_etzpc: new driver to use firewall API Implement stm32_etzpc.c driver in the firewall driver directory. Use the new firewall API to populate the firewall bus and register the ETZPC as a firewall provider. Implement a driver specific firewall bus probe that will only probe secure peripherals and implement firewall exceptions for which no firewall operations will be done when CFG_INSECURE is set. This allows, for example, to share a console with the non-secure world for development purposes. The ETZPC driver register the following ops: -set_conf -acquire_access -acquire_memory_access Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- core/arch/arm/plat-stm32mp1/main.c | 31 +++ core/arch/arm/plat-stm32mp1/platform_config.h | 3 + core/arch/arm/plat-stm32mp1/stm32_util.h | 2 + core/drivers/firewall/stm32_etzpc.c | 222 ++++++++++++++++-- 4 files changed, 244 insertions(+), 14 deletions(-) diff --git a/core/arch/arm/plat-stm32mp1/main.c b/core/arch/arm/plat-stm32mp1/main.c index 36031ace62e..60aa70b7758 100644 --- a/core/arch/arm/plat-stm32mp1/main.c +++ b/core/arch/arm/plat-stm32mp1/main.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -492,3 +493,33 @@ early_init_late(init_debug); /* Some generic resources need to be unpaged */ DECLARE_KEEP_PAGER(pinctrl_apply_state); + +bool stm32mp_allow_probe_shared_device(const void *fdt, int node) +{ + static int uart_console_node = -1; + const char *compat = NULL; + static bool once; + + if (IS_ENABLED(CFG_STM32_ALLOW_UNSAFE_PROBE)) + return true; + + if (!once) { + get_console_node_from_dt((void *)fdt, &uart_console_node, + NULL, NULL); + once = true; + } + + compat = fdt_stringlist_get(fdt, node, "compatible", 0, NULL); + + /* + * Allow OP-TEE console and MP15 I2C and RNG to be shared + * with non-secure world. + */ + if (node == uart_console_node || + !strcmp(compat, "st,stm32mp15-i2c-non-secure") || + (!strcmp(compat, "st,stm32-rng") && + IS_ENABLED(CFG_WITH_SOFTWARE_PRNG))) + return true; + + return false; +} diff --git a/core/arch/arm/plat-stm32mp1/platform_config.h b/core/arch/arm/plat-stm32mp1/platform_config.h index c3867fc8ed2..b6cb608476f 100644 --- a/core/arch/arm/plat-stm32mp1/platform_config.h +++ b/core/arch/arm/plat-stm32mp1/platform_config.h @@ -109,6 +109,9 @@ #define UART7_BASE 0x40018000 #define UART8_BASE 0x40019000 +#define ROM_BASE 0 +#define ROM_SIZE 0x20000 + /* Console configuration */ #define STM32MP1_DEBUG_USART_BASE UART4_BASE #define GIC_SPI_UART4 84 diff --git a/core/arch/arm/plat-stm32mp1/stm32_util.h b/core/arch/arm/plat-stm32mp1/stm32_util.h index 627933e4ad6..cd0471347e6 100644 --- a/core/arch/arm/plat-stm32mp1/stm32_util.h +++ b/core/arch/arm/plat-stm32mp1/stm32_util.h @@ -202,6 +202,8 @@ enum stm32mp_shres { STM32MP1_SHRES_COUNT }; +bool stm32mp_allow_probe_shared_device(const void *fdt, int node); + #ifdef CFG_STM32MP1_SHARED_RESOURCES /* Register resource @id as a secure peripheral */ void stm32mp_register_secure_periph(enum stm32mp_shres id); diff --git a/core/drivers/firewall/stm32_etzpc.c b/core/drivers/firewall/stm32_etzpc.c index 3a7a927cf87..15698c13d0d 100644 --- a/core/drivers/firewall/stm32_etzpc.c +++ b/core/drivers/firewall/stm32_etzpc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -22,8 +24,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -104,6 +108,13 @@ struct etzpc_device { static struct etzpc_device *etzpc_device; +static const char *const etzpc_decprot_strings[] __maybe_unused = { + "ETZPC_DECPROT_S_RW", + "ETZPC_DECPROT_NS_R_S_W", + "ETZPC_DECPROT_MCU_ISOLATION", + "ETZPC_DECPROT_NS_RW", +}; + static uint32_t etzpc_lock(void) { return cpu_spin_lock_xsave(&etzpc_device->lock); @@ -153,7 +164,7 @@ static void etzpc_configure_decprot(uint32_t decprot_id, assert(valid_decprot_id(decprot_id)); - DMSG("ID : %"PRIu32", CONF %d", decprot_id, attr); + FMSG("ID : %"PRIu32", config %i", decprot_id, attr); exceptions = etzpc_lock(); @@ -305,6 +316,104 @@ static TEE_Result etzpc_pm(enum pm_op op, unsigned int pm_hint __unused, } DECLARE_KEEP_PAGER(etzpc_pm); +static TEE_Result stm32_etzpc_acquire_access(struct firewall_query *firewall) +{ + enum etzpc_decprot_attributes attr = ETZPC_DECPROT_MCU_ISOLATION; + uint32_t id = 0; + + if (!firewall || firewall->arg_count != 1) + return TEE_ERROR_BAD_PARAMETERS; + + id = firewall->args[0] & ETZPC_ID_MASK; + if (id < etzpc_device->ddata.num_per_sec) { + attr = etzpc_get_decprot(id); + if (attr != ETZPC_DECPROT_S_RW && + attr != ETZPC_DECPROT_NS_R_S_W) + return TEE_ERROR_ACCESS_DENIED; + } else { + return TEE_ERROR_BAD_PARAMETERS; + } + + return TEE_SUCCESS; +} + +static TEE_Result +stm32_etzpc_acquire_memory_access(struct firewall_query *firewall, + paddr_t paddr, size_t size, + bool read __unused, bool write __unused) +{ + paddr_t tzma_base = 0; + size_t prot_size = 0; + uint32_t id = 0; + + if (!firewall || firewall->arg_count != 1) + return TEE_ERROR_BAD_PARAMETERS; + + id = firewall->args[0] & ETZPC_ID_MASK; + switch (id) { + case ETZPC_TZMA0_ID: + tzma_base = ROM_BASE; + prot_size = etzpc_get_tzma(0) * SMALL_PAGE_SIZE; + break; + case ETZPC_TZMA1_ID: + tzma_base = SYSRAM_BASE; + prot_size = etzpc_get_tzma(1) * SMALL_PAGE_SIZE; + break; + default: + return TEE_ERROR_BAD_PARAMETERS; + } + + DMSG("Acquiring access for TZMA%u, secured from %#"PRIxPA" to %#"PRIxPA, + id == ETZPC_TZMA0_ID ? 0 : 1, tzma_base, tzma_base + prot_size); + + if (core_is_buffer_inside(paddr, size, tzma_base, prot_size)) + return TEE_SUCCESS; + + return TEE_ERROR_ACCESS_DENIED; +} + +static TEE_Result stm32_etzpc_configure(struct firewall_query *firewall) +{ + enum etzpc_decprot_attributes attr = ETZPC_DECPROT_MAX; + uint32_t id = 0; + + if (firewall->arg_count != 1) + return TEE_ERROR_BAD_PARAMETERS; + + id = firewall->args[0] & ETZPC_ID_MASK; + + if (id < etzpc_device->ddata.num_per_sec) { + uint32_t mode = 0; + + /* + * Peripheral configuration, we assume the configuration is as + * follows: + * firewall->args[0]: Firewall configuration to apply + */ + + mode = (firewall->args[0] & ETZPC_MODE_MASK) >> + ETZPC_MODE_SHIFT; + attr = etzpc_binding2decprot(mode); + + if (decprot_is_locked(id)) { + EMSG("Peripheral configuration locked"); + return TEE_ERROR_ACCESS_DENIED; + } + + DMSG("Setting access config for periph %"PRIu32" - attr %s", id, + etzpc_decprot_strings[attr]); + + etzpc_configure_decprot(id, attr); + if (firewall->args[0] & ETZPC_LOCK_MASK) + etzpc_lock_decprot(id); + + return TEE_SUCCESS; + } + EMSG("Unknown firewall ID: %"PRIu32, id); + + return TEE_ERROR_BAD_PARAMETERS; +} + static void stm32_etzpc_set_driverdata(void) { struct stm32_etzpc_driver_data *ddata = &etzpc_device->ddata; @@ -359,6 +468,72 @@ static void fdt_etzpc_conf_decprot(const void *fdt, int node) clk_disable(etzpc_device->pdata.clk); } +static TEE_Result +stm32_etzpc_dt_probe_bus(const void *fdt, int node, + struct firewall_controller *ctrl __maybe_unused) +{ + TEE_Result res = TEE_ERROR_GENERIC; + struct firewall_query *fw = NULL; + int subnode = 0; + + DMSG("Populating %s firewall bus", ctrl->name); + + fdt_for_each_subnode(subnode, fdt, node) { + unsigned int i = 0; + + if (fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED) + continue; + + if (IS_ENABLED(CFG_INSECURE) && + stm32mp_allow_probe_shared_device(fdt, subnode)) { + DMSG("Skipping firewall attributes check for %s", + fdt_get_name(fdt, subnode, NULL)); + goto skip_check; + } + + DMSG("Acquiring firewall access for %s when probing bus", + fdt_get_name(fdt, subnode, NULL)); + + do { + /* + * The access-controllers property is mandatory for + * firewall bus devices + */ + res = firewall_dt_get_by_index(fdt, subnode, i, &fw); + if (res == TEE_ERROR_ITEM_NOT_FOUND) { + /* Stop when nothing more to parse */ + break; + } else if (res) { + EMSG("%s: Error on node %s: %#"PRIx32, + ctrl->name, + fdt_get_name(fdt, subnode, NULL), res); + panic(); + } + + res = firewall_acquire_access(fw); + if (res) { + EMSG("%s: %s not accessible: %#"PRIx32, + ctrl->name, + fdt_get_name(fdt, subnode, NULL), res); + panic(); + } + + firewall_put(fw); + i++; + } while (true); + +skip_check: + res = dt_driver_maybe_add_probe_node(fdt, subnode); + if (res) { + EMSG("Failed on node %s with %#"PRIx32, + fdt_get_name(fdt, subnode, NULL), res); + panic(); + } + } + + return TEE_SUCCESS; +} + static TEE_Result init_etzpc_from_dt(const void *fdt, int node) { TEE_Result res = TEE_ERROR_GENERIC; @@ -382,27 +557,35 @@ static TEE_Result init_etzpc_from_dt(const void *fdt, int node) etzpc_device->pdata.periph_cfg = calloc(etzpc_device->ddata.num_per_sec, sizeof(*etzpc_device->pdata.periph_cfg)); + if (!etzpc_device->pdata.periph_cfg) + return TEE_ERROR_OUT_OF_MEMORY; etzpc_device->pdata.tzma_cfg = calloc(etzpc_device->ddata.num_tzma, sizeof(*etzpc_device->pdata.tzma_cfg)); - if (!etzpc_device->pdata.periph_cfg || !etzpc_device->pdata.tzma_cfg) + if (!etzpc_device->pdata.tzma_cfg) { + free(etzpc_device->pdata.periph_cfg); return TEE_ERROR_OUT_OF_MEMORY; - - fdt_etzpc_conf_decprot(fdt, node); + } return TEE_SUCCESS; } +static const struct firewall_controller_ops firewall_ops = { + .set_conf = stm32_etzpc_configure, + .acquire_access = stm32_etzpc_acquire_access, + .acquire_memory_access = stm32_etzpc_acquire_memory_access, +}; + static TEE_Result stm32_etzpc_probe(const void *fdt, int node, const void *compat_data __unused) { TEE_Result res = TEE_ERROR_GENERIC; - int subnode = 0; + struct firewall_controller *controller = NULL; etzpc_device = calloc(1, sizeof(*etzpc_device)); if (!etzpc_device) - panic("ETZPC probe failed"); + panic(); res = init_etzpc_from_dt(fdt, node); if (res) { @@ -410,17 +593,28 @@ static TEE_Result stm32_etzpc_probe(const void *fdt, int node, free(etzpc_device->pdata.tzma_cfg); free(etzpc_device->pdata.name); free(etzpc_device); + free(controller); return res; } - fdt_for_each_subnode(subnode, fdt, node) { - res = dt_driver_maybe_add_probe_node(fdt, subnode); - if (res) { - EMSG("Failed to add node %s to probe list: %#"PRIx32, - fdt_get_name(fdt, subnode, NULL), res); - panic(); - } - } + controller = calloc(1, sizeof(*controller)); + if (!controller) + panic(); + + controller->base = &etzpc_device->pdata.base; + controller->name = etzpc_device->pdata.name; + controller->priv = etzpc_device; + controller->ops = &firewall_ops; + + res = firewall_dt_controller_register(fdt, node, controller); + if (res) + panic("Cannot register ETZPC as a firewall controller"); + + fdt_etzpc_conf_decprot(fdt, node); + + res = stm32_etzpc_dt_probe_bus(fdt, node, controller); + if (res) + panic("Cannot populate bus"); register_pm_core_service_cb(etzpc_pm, NULL, "stm32-etzpc"); From feacc0114b143b0546a0f0f693b3f907a65256c8 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Tue, 8 Oct 2024 18:12:28 +0200 Subject: [PATCH 14/14] drivers: stm32_rng: embed ETZPC functions when CFG_STM32_ETZPC is set On platforms when CFG_STM32_ETZPC is disabled, ETZPC cannot be interrogated to get decprot attributes. Therefore do not embed ETZPC related code. While there, revert commit 326382a059a8 ("drivers: stm32_rng: MP15 RNG is non-secure when PRNG is enable") and prefer to use ETZPC API. Signed-off-by: Gatien Chevallier Fixes: d773ec0baf4c ("drivers: stm32_rng: update clock and power management") Reviewed-by: Etienne Carriere --- core/drivers/stm32_rng.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/drivers/stm32_rng.c b/core/drivers/stm32_rng.c index be68afdcc76..8e1282c07ce 100644 --- a/core/drivers/stm32_rng.c +++ b/core/drivers/stm32_rng.c @@ -670,13 +670,13 @@ static TEE_Result stm32_rng_probe(const void *fdt, int offs, if (res) goto err; -#if defined(CFG_STM32MP15) +#if defined(CFG_STM32MP15) && defined(CFG_STM32_ETZPC) /* Only STM32MP15 requires a software registering of RNG secure state */ - if (IS_ENABLED(CFG_WITH_SOFTWARE_PRNG)) + if (etzpc_get_decprot(STM32MP1_ETZPC_RNG1_ID) == ETZPC_DECPROT_NS_RW) stm32mp_register_non_secure_periph_iomem(stm32_rng->base.pa); else stm32mp_register_secure_periph_iomem(stm32_rng->base.pa); -#endif /* defined(CFG_STM32MP15) */ +#endif /* defined(CFG_STM32MP15) && defined(CFG_STM32_ETZPC) */ /* Power management implementation expects both or none are set */ assert(stm32_rng->ddata->has_power_optim ==