diff --git a/perceval/rendering/circuit/renderer.py b/perceval/rendering/circuit/renderer.py
index 20272186..7c363e8a 100644
--- a/perceval/rendering/circuit/renderer.py
+++ b/perceval/rendering/circuit/renderer.py
@@ -104,7 +104,7 @@ def render_circuit(self,
if c.is_composite() and c._components:
if recursive:
self._current_subblock_info = self._subblock_info.setdefault(c, {})
- self.open_subblock(shiftr, c.name, self.get_circuit_size(c, recursive=True), c._color)
+ self.open_subblock(shiftr, c.name, self.get_circuit_size(c, recursive=False), c._color)
self.render_circuit(
c,
shift=shiftr[0],
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateFFF.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateFFF.svg
new file mode 100644
index 00000000..65fde859
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateFFF.svg
@@ -0,0 +1,511 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateFFT.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateFFT.svg
new file mode 100644
index 00000000..4d279308
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateFFT.svg
@@ -0,0 +1,788 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateFTF.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateFTF.svg
new file mode 100644
index 00000000..642febfd
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateFTF.svg
@@ -0,0 +1,807 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateFTT.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateFTT.svg
new file mode 100644
index 00000000..a4cf2fd4
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateFTT.svg
@@ -0,0 +1,880 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateTFF.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateTFF.svg
new file mode 100644
index 00000000..dd183b44
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateTFF.svg
@@ -0,0 +1,522 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateTFT.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateTFT.svg
new file mode 100644
index 00000000..37feea00
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateTFT.svg
@@ -0,0 +1,742 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateTTF.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateTTF.svg
new file mode 100644
index 00000000..431fba69
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateTTF.svg
@@ -0,0 +1,746 @@
+
+
+
diff --git a/tests/imgs/test_svg_dump_circuit_box_bell_stateTTT.svg b/tests/imgs/test_svg_dump_circuit_box_bell_stateTTT.svg
new file mode 100644
index 00000000..d8991b03
--- /dev/null
+++ b/tests/imgs/test_svg_dump_circuit_box_bell_stateTTT.svg
@@ -0,0 +1,770 @@
+
+
+
diff --git a/tests/test_visualization.py b/tests/test_visualization.py
index e9f5340c..713733b2 100644
--- a/tests/test_visualization.py
+++ b/tests/test_visualization.py
@@ -27,6 +27,8 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
+import pytest
+
import sys
import sympy as sp
@@ -321,3 +323,59 @@ def test_svg_dump_barrier_phys(tmp_path, save_figs):
def test_svg_dump_barrier_symb(tmp_path, save_figs):
c = pcvl.Circuit(4) // BS() @ (2, BS()) // (1, BS()) @ BS()
_save_or_check(c, tmp_path, sys._getframe().f_code.co_name, save_figs, recursive=True, skin_type=SymbSkin)
+
+
+@pytest.mark.parametrize("merge_pre_MZI", [False, True])
+@pytest.mark.parametrize("merge_upper_MZI", [False, True])
+@pytest.mark.parametrize("merge_lower_MZI", [False, True])
+def test_svg_dump_circuit_box_bell_state(tmp_path, save_figs,
+ merge_pre_MZI,
+ merge_upper_MZI,
+ merge_lower_MZI):
+
+ pre_MZI = (pcvl.Circuit(4, name="Bell State Prep")
+ .add(0, BS())
+ .add(2, BS())
+ .add(1, PERM([1, 0])))
+
+ upper_MZI = (pcvl.Circuit(2, name="upper MZI")
+ .add(0, PS(phi=pcvl.P('phi_0')))
+ .add(0, BS())
+ .add(0, PS(phi=pcvl.P('phi_2')))
+ .add(0, BS()))
+
+ lower_MZI = (pcvl.Circuit(2, name="lower MZI")
+ .add(0, PS(phi=pcvl.P('phi_1')))
+ .add(0, BS())
+ .add(0, PS(phi=pcvl.P('phi_3')))
+ .add(0, BS()))
+
+ chip = (pcvl.Circuit(4)
+ .add(0, pre_MZI, merge=merge_pre_MZI)
+ .add(0, upper_MZI, merge=merge_upper_MZI)
+ .add(2, lower_MZI, merge=merge_lower_MZI))
+
+ processor = pcvl.Processor('SLOS', chip)
+
+ fig_name = sys._getframe().f_code.co_name
+
+ if merge_pre_MZI:
+ fig_name = f"{fig_name}T"
+ else:
+ fig_name = f"{fig_name}F"
+
+ if merge_upper_MZI:
+ fig_name = f"{fig_name}T"
+ else:
+ fig_name = f"{fig_name}F"
+
+ if merge_lower_MZI:
+ fig_name = f"{fig_name}T"
+ else:
+ fig_name = f"{fig_name}F"
+
+ _save_or_check(c=processor,
+ tmp_path=tmp_path,
+ circuit_name=fig_name,
+ save_figs=save_figs,
+ recursive=True)