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function slave_mask_t invert_slave_mask;
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xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable datatype.
function slave_mask_t invert_slave_mask;
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xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable datatype.
parameter bit [SLAVES-1:0] ERROR_ON_SLAVE_MASK[MASTERS] = invert_slave_mask(),
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xmvlog: *N,CFCALL (../rtl/verilog/ahb3lite_interconnect.sv,136|76): Function invert_slave_mask treated as a constant function because of this call.
module worklib.ahb3lite_interconnect:sv
What do I miss?
I use xcellium version 20.03-s003
The text was updated successfully, but these errors were encountered:
The code has been compiled using the Intel, Xilinx, and Lattice design flows.
We run simulations with the Aldec and Mentor tools. Unfortunately I do not have access to the Cadence tools.
It seems like the tool doesn't like/find the type definition. You can try moving the type definition before its use. Or place the type definition in a separate package.
when it try to compile standalone RTL as :
xrun submodules/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv rtl/verilog/*.sv
I'm getting following error:
What do I miss?
I use xcellium version 20.03-s003
The text was updated successfully, but these errors were encountered: