From c0ec4da84929acc942dd48f9fc143c417379af4f Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 1 Feb 2024 18:14:19 -0800 Subject: [PATCH 1/4] Revert "Mingw: Update for GDT" This reverts commit ae2f98e017f32039ee31b1fbda581ee1ab828dfa. --- Source/Windows/WOW64/Module.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Source/Windows/WOW64/Module.cpp b/Source/Windows/WOW64/Module.cpp index cdd4b8e401..a0fba02602 100644 --- a/Source/Windows/WOW64/Module.cpp +++ b/Source/Windows/WOW64/Module.cpp @@ -146,8 +146,7 @@ namespace Context { State.gs_idx = Context->SegGs & 0xffff; // The TEB is the only populated GDT entry by default - State.SetGDTBase(&State.gdt[(Context->SegFs & 0xffff) >> 3], WowTEB); - State.SetGDTLimit(&State.gdt[(Context->SegFs & 0xffff) >> 3], 0xF'FFFFU); + State.gdt[(Context->SegFs & 0xffff) >> 3].base = WowTEB; State.fs_cached = WowTEB; State.es_cached = 0; State.cs_cached = 0; From da0e1b515a6561648c78c0f57fe9f0f8f2a0fa8a Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 1 Feb 2024 18:14:24 -0800 Subject: [PATCH 2/4] Revert "OpcodeDispatcher: Initial support for runtime long-mode switch" This reverts commit 9e5d7aa5fe65461b0067ea72034e23cb1dc44285. --- FEXCore/Source/Interface/Context/Context.h | 2 + FEXCore/Source/Interface/Core/Core.cpp | 8 +- FEXCore/Source/Interface/Core/Frontend.cpp | 37 ++--- FEXCore/Source/Interface/Core/Frontend.h | 4 +- .../Interface/Core/OpcodeDispatcher.cpp | 143 ++++++++---------- .../Source/Interface/Core/OpcodeDispatcher.h | 15 +- .../Core/OpcodeDispatcher/Vector.cpp | 54 +++---- .../Source/Interface/HLE/Thunks/Thunks.cpp | 2 +- 8 files changed, 125 insertions(+), 140 deletions(-) diff --git a/FEXCore/Source/Interface/Context/Context.h b/FEXCore/Source/Interface/Context/Context.h index 9916303a7d..6e40dc1996 100644 --- a/FEXCore/Source/Interface/Context/Context.h +++ b/FEXCore/Source/Interface/Context/Context.h @@ -336,6 +336,8 @@ namespace FEXCore::Context { void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread); + uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; } + FEXCore::JITSymbols Symbols; void GetVDSOSigReturn(VDSOSigReturn *VDSOPointers) override { diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp index 5ba18b8cd2..6de199a8f0 100644 --- a/FEXCore/Source/Interface/Core/Core.cpp +++ b/FEXCore/Source/Interface/Core/Core.cpp @@ -777,7 +777,7 @@ namespace FEXCore::Context { bool HadDispatchError {false}; - Thread->FrontendDecoder->DecodeInstructionsAtEntry(Thread, GuestCode, GuestRIP, MaxInst, [Thread](uint64_t BlockEntry, uint64_t Start, uint64_t Length) { + Thread->FrontendDecoder->DecodeInstructionsAtEntry(GuestCode, GuestRIP, MaxInst, [Thread](uint64_t BlockEntry, uint64_t Start, uint64_t Length) { if (Thread->LookupCache->AddBlockExecutableRange(BlockEntry, Start, Length)) { static_cast(Thread->CTX)->SyscallHandler->MarkGuestExecutableRange(Thread, Start, Length); } @@ -786,9 +786,9 @@ namespace FEXCore::Context { auto BlockInfo = Thread->FrontendDecoder->GetDecodedBlockInfo(); auto CodeBlocks = &BlockInfo->Blocks; - Thread->OpDispatcher->BeginFunction(GuestRIP, CodeBlocks, BlockInfo->TotalInstructionCount, BlockInfo->Is64BitMode); + Thread->OpDispatcher->BeginFunction(GuestRIP, CodeBlocks, BlockInfo->TotalInstructionCount); - const uint8_t GPRSize = Thread->OpDispatcher->GetGPRSize(); + const uint8_t GPRSize = GetGPRSize(); for (size_t j = 0; j < CodeBlocks->size(); ++j) { FEXCore::Frontend::Decoder::DecodedBlocks const &Block = CodeBlocks->at(j); @@ -873,6 +873,8 @@ namespace FEXCore::Context { } if (NeedsBlockEnd) { + const uint8_t GPRSize = GetGPRSize(); + // We had some instructions. Early exit Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(IR::SizeToOpSize(GPRSize), Block.Entry + BlockInstructionsLength - GuestRIP)); break; diff --git a/FEXCore/Source/Interface/Core/Frontend.cpp b/FEXCore/Source/Interface/Core/Frontend.cpp index 93bb483dd9..f7b5c8c198 100644 --- a/FEXCore/Source/Interface/Core/Frontend.cpp +++ b/FEXCore/Source/Interface/Core/Frontend.cpp @@ -310,7 +310,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, uint8_t DestSize{}; const bool HasWideningDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST) != 0 || - (Options.w && BlockInfo.Is64BitMode); + (Options.w && CTX->Config.Is64BitMode); const bool HasNarrowingDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0; const bool HasXMMFlags = (Info->Flags & InstFlags::FLAGS_XMM_FLAGS) != 0; @@ -331,7 +331,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, const bool HasMODRM = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM); const bool HasREX = !!(DecodeInst->Flags & DecodeFlags::FLAG_REX_PREFIX); - const bool Has16BitAddressing = !BlockInfo.Is64BitMode && + const bool Has16BitAddressing = !CTX->Config.Is64BitMode && DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE; // This is used for ModRM register modification @@ -386,7 +386,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DestSize = 2; } else if ( - (HasXMMDst || HasMMDst || BlockInfo.Is64BitMode) && + (HasXMMDst || HasMMDst || CTX->Config.Is64BitMode) && (HasWideningDisplacement || DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT || DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) { @@ -424,7 +424,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_16BIT); } else if ( - (HasXMMSrc || HasMMSrc || BlockInfo.Is64BitMode) && + (HasXMMSrc || HasMMSrc || CTX->Config.Is64BitMode) && (HasWideningDisplacement || SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT || SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) { @@ -692,7 +692,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16 DecodedHeader options{}; if ((Byte1 & 0b10000000) == 0) { - LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode, "VEX.R shouldn't be 0 in 32-bit mode!"); + LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.R shouldn't be 0 in 32-bit mode!"); DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_R; } @@ -709,10 +709,10 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16 options.w = (Byte2 & 0b10000000) != 0; options.L = (Byte2 & 0b100) != 0; if ((Byte1 & 0b01000000) == 0) { - LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode, "VEX.X shouldn't be 0 in 32-bit mode!"); + LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.X shouldn't be 0 in 32-bit mode!"); DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X; } - if (BlockInfo.Is64BitMode && (Byte1 & 0b00100000) == 0) { + if (CTX->Config.Is64BitMode && (Byte1 & 0b00100000) == 0) { DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B; } if (!(map_select >= 1 && map_select <= 3)) { @@ -787,7 +787,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) { FEXCore::X86Tables::ModRMDecoded ModRM; ModRM.Hex = DecodeInst->ModRM; - const bool Has16BitAddressing = !BlockInfo.Is64BitMode && + const bool Has16BitAddressing = !CTX->Config.Is64BitMode && DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE; // All 3DNow! instructions have the second argument as the rm handler @@ -898,17 +898,17 @@ bool Decoder::DecodeInstruction(uint64_t PC) { DecodeInst->Flags |= DecodeFlags::FLAG_ADDRESS_SIZE; break; case 0x26: // ES legacy prefix - if (!BlockInfo.Is64BitMode) { + if (!CTX->Config.Is64BitMode) { DecodeInst->Flags |= DecodeFlags::FLAG_ES_PREFIX; } break; case 0x2E: // CS legacy prefix - if (!BlockInfo.Is64BitMode) { + if (!CTX->Config.Is64BitMode) { DecodeInst->Flags |= DecodeFlags::FLAG_CS_PREFIX; } break; case 0x36: // SS legacy prefix - if (!BlockInfo.Is64BitMode) { + if (!CTX->Config.Is64BitMode) { DecodeInst->Flags |= DecodeFlags::FLAG_SS_PREFIX; } break; @@ -916,7 +916,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) { // Annoyingly GCC generates NOP ops with these prefixes // Just ignore them for now // eg. 66 2e 0f 1f 84 00 00 00 00 00 nop WORD PTR cs:[rax+rax*1+0x0] - if (!BlockInfo.Is64BitMode) { + if (!CTX->Config.Is64BitMode) { DecodeInst->Flags |= DecodeFlags::FLAG_DS_PREFIX; } break; @@ -942,7 +942,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) { auto Info = &FEXCore::X86Tables::BaseOps[Op]; if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) { - LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode, "Got REX prefix in 32bit mode"); + LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode"); DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX; // Widening displacement @@ -985,7 +985,7 @@ void Decoder::BranchTargetInMultiblockRange() { // If the RIP setting is conditional AND within our symbol range then it can be considered for multiblock uint64_t TargetRIP = 0; - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); bool Conditional = true; switch (DecodeInst->OP) { @@ -1052,7 +1052,7 @@ bool Decoder::BranchTargetCanContinue(bool FinalInstruction) const { } uint64_t TargetRIP = 0; - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); if (DecodeInst->OP == 0xE8) { // Call - immediate target const uint64_t NextRIP = DecodeInst->PC + DecodeInst->InstSize; @@ -1094,7 +1094,7 @@ const uint8_t *Decoder::AdjustAddrForSpecialRegion(uint8_t const* _InstStream, u return _InstStream - EntryPoint + RIP; } -void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, uint8_t const* _InstStream, uint64_t PC, uint64_t MaxInst, std::function AddContainedCodePage) { +void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC, uint64_t MaxInst, std::function AddContainedCodePage) { FEXCORE_PROFILE_SCOPED("DecodeInstructions"); BlockInfo.TotalInstructionCount = 0; BlockInfo.Blocks.clear(); @@ -1106,11 +1106,6 @@ void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thre MaxCondBranchBackwards = ~0ULL; DecodedBuffer = PoolObject.ReownOrClaimBuffer(); - // Decode operating mode from thread's CS segment. - const auto CSSegment = Thread->CurrentFrame->State.gdt[Thread->CurrentFrame->State.cs_idx >> 3]; - BlockInfo.Is64BitMode = CSSegment.L == 1; - LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode == CTX->Config.Is64BitMode, "Expected operating mode to not change at runtime!"); - // XXX: Load symbol data SymbolAvailable = false; EntryPoint = PC; diff --git a/FEXCore/Source/Interface/Core/Frontend.h b/FEXCore/Source/Interface/Core/Frontend.h index 656f184d66..6f0eab8efb 100644 --- a/FEXCore/Source/Interface/Core/Frontend.h +++ b/FEXCore/Source/Interface/Core/Frontend.h @@ -29,13 +29,12 @@ class Decoder final { struct DecodedBlockInformation final { uint64_t TotalInstructionCount; - bool Is64BitMode{}; fextl::vector Blocks; }; Decoder(FEXCore::Context::ContextImpl *ctx); ~Decoder(); - void DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, uint8_t const* InstStream, uint64_t PC, uint64_t MaxInst, std::function AddContainedCodePage); + void DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC, uint64_t MaxInst, std::function AddContainedCodePage); DecodedBlockInformation const *GetDecodedBlockInfo() const { return &BlockInfo; @@ -82,7 +81,6 @@ class Decoder final { size_t DecodedSize {}; uint8_t const *InstStream; - uint8_t GetGPRSize() const { return BlockInfo.Is64BitMode ? 8 : 4; } static constexpr size_t MAX_INST_SIZE = 15; uint8_t InstructionSize; diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 77e4ea4d1b..d155dbd28d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -108,7 +108,7 @@ void OpDispatchBuilder::SyscallOp(OpcodeArgs) { // Calculate flags early. CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); auto NewRIP = GetRelocatedPC(Op, -Op->InstSize); _StoreContext(GPRSize, GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip)); @@ -170,10 +170,10 @@ void OpDispatchBuilder::ThunkOp(OpcodeArgs) { // Calculate flags early. CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); uint8_t *sha256 = (uint8_t *)(Op->PC + 2); - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { // x86-64 ABI puts the function argument in RDI _Thunk( LoadGPRRegister(X86State::REG_RDI), @@ -206,14 +206,14 @@ void OpDispatchBuilder::LEAOp(OpcodeArgs) { // LEA specifically ignores segment prefixes const auto SrcSize = GetSrcSize(Op); - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { const uint32_t DstSize = X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST ? 2 : X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST ? 8 : 4; auto Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], SrcSize, Op->Flags, {.LoadData = false}); if (DstSize != SrcSize) { // If the SrcSize isn't the DstSize then we need to zero extend. - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); Src = _Bfe(IR::SizeToOpSize(GPRSize), SrcSize * 8, 0, Src); } StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Src, DstSize, -1); @@ -230,7 +230,7 @@ void OpDispatchBuilder::NOPOp(OpcodeArgs) { } void OpDispatchBuilder::RETOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // ABI Optimization: Flags don't survive calls or rets if (CTX->Config.ABILocalFlags) { @@ -285,7 +285,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) { // Calculate flags early. CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); auto Constant = _Constant(GPRSize); @@ -305,7 +305,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) { SetPackedRFLAG(false, eflags); SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant); - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { // RSP and SS only happen in 64-bit mode or if this is a CPL mode jump! // FEX doesn't support a CPL mode switch, so don't need to worry about this on 32-bit StoreGPRRegister(X86State::REG_RSP, _LoadMem(GPRClass, GPRSize, SP, GPRSize)); @@ -329,7 +329,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) { } void OpDispatchBuilder::CallbackReturnOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // Store the new RIP _CallbackReturn(); auto NewRIP = _LoadContext(GPRSize, GPRClass, offsetof(FEXCore::Core::CPUState, rip)); @@ -523,7 +523,7 @@ void OpDispatchBuilder::PUSHOp(OpcodeArgs) { auto OldSP = LoadGPRRegister(X86State::REG_RSP); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); auto NewSP = _Push(GPRSize, Size, Src, OldSP); // Store the new stack pointer @@ -537,7 +537,7 @@ void OpDispatchBuilder::PUSHREGOp(OpcodeArgs) { {.AllowUpperGarbage = true}); auto OldSP = LoadGPRRegister(X86State::REG_RSP); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); auto NewSP = _Push(GPRSize, Size, Src, OldSP); // Store the new stack pointer StoreGPRRegister(X86State::REG_RSP, NewSP); @@ -562,7 +562,7 @@ void OpDispatchBuilder::PUSHAOp(OpcodeArgs) { OrderedNode *Src{}; OrderedNode *NewSP = OldSP; - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); Src = LoadGPRRegister(X86State::REG_RAX); NewSP = _Push(GPRSize, Size, Src, NewSP); @@ -600,7 +600,7 @@ void OpDispatchBuilder::PUSHSegmentOp(OpcodeArgs) { auto OldSP = LoadGPRRegister(X86State::REG_RSP); OrderedNode *Src{}; - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode()) { switch (SegmentReg) { case FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX: Src = _LoadContext(SrcSize, GPRClass, offsetof(FEXCore::Core::CPUState, es_idx)); @@ -647,7 +647,7 @@ void OpDispatchBuilder::PUSHSegmentOp(OpcodeArgs) { } } - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // Store our value to the new stack location // AMD hardware zexts segment selector to 32bit // Intel hardware inserts segment selector @@ -780,7 +780,7 @@ void OpDispatchBuilder::LEAVEOp(OpcodeArgs) { } void OpDispatchBuilder::CALLOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); BlockSetRIP = true; @@ -951,7 +951,7 @@ void OpDispatchBuilder::SETccOp(OpcodeArgs) { } void OpDispatchBuilder::CMOVOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // Calculate flags early. CalculateDeferredFlags(); @@ -983,7 +983,7 @@ void OpDispatchBuilder::CondJUMPOp(OpcodeArgs) { uint64_t InstRIP = Op->PC + Op->InstSize; uint64_t Target = InstRIP + TargetOffset; - if (GetGPRSize() == 4) { + if (CTX->GetGPRSize() == 4) { // If the GPRSize is 4 then we need to be careful about PC wrapping if (TargetOffset < 0 && -TargetOffset > InstRIP) { // Invert the signed value if we are underflowing @@ -1058,7 +1058,7 @@ void OpDispatchBuilder::CondJUMPRCXOp(OpcodeArgs) { CalculateDeferredFlags(); BlockSetRIP = true; - uint8_t JcxGPRSize = GetGPRSize(); + uint8_t JcxGPRSize = CTX->GetGPRSize(); JcxGPRSize = (Op->Flags & X86Tables::DecodeFlags::FLAG_ADDRESS_SIZE) ? (JcxGPRSize >> 1) : JcxGPRSize; IRPair TakeBranch; @@ -1211,7 +1211,7 @@ void OpDispatchBuilder::JUMPOp(OpcodeArgs) { uint64_t InstRIP = Op->PC + Op->InstSize; uint64_t TargetRIP = InstRIP + TargetOffset; - if (GetGPRSize() == 4) { + if (CTX->GetGPRSize() == 4) { // If the GPRSize is 4 then we need to be careful about PC wrapping if (TargetOffset < 0 && -TargetOffset > InstRIP) { // Invert the signed value if we are underflowing @@ -1498,7 +1498,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs) { break; case FEXCore::X86State::REG_RBP: // GS case FEXCore::X86State::REG_R13: // GS - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { _StoreContext(2, GPRClass, Src, offsetof(FEXCore::Core::CPUState, gs_idx)); UpdatePrefixFromSegment(Src, FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX); } else { @@ -1508,7 +1508,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs) { break; case FEXCore::X86State::REG_RSP: // FS case FEXCore::X86State::REG_R12: // FS - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { _StoreContext(2, GPRClass, Src, offsetof(FEXCore::Core::CPUState, fs_idx)); UpdatePrefixFromSegment(Src, FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX); } else { @@ -1544,7 +1544,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs) { break; case FEXCore::X86State::REG_RBP: // GS case FEXCore::X86State::REG_R13: // GS - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { Segment = _Constant(0); } else { @@ -1553,7 +1553,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs) { break; case FEXCore::X86State::REG_RSP: // FS case FEXCore::X86State::REG_R12: // FS - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { Segment = _Constant(0); } else { @@ -1600,7 +1600,7 @@ void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) { } void OpDispatchBuilder::CPUIDOp(OpcodeArgs) { - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); OrderedNode *Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], GPRSize, Op->Flags); OrderedNode *Leaf = LoadGPRRegister(X86State::REG_RCX); @@ -2214,7 +2214,7 @@ void OpDispatchBuilder::BLSRBMIOp(OpcodeArgs) { void OpDispatchBuilder::BMI2Shift(OpcodeArgs) { // In the event the source is a memory operand, use the // exact width instead of the GPR size. - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); const auto Size = GetSrcSize(Op); const auto SrcSize = Op->Src[0].IsGPR() ? GPRSize : Size; @@ -2276,7 +2276,7 @@ void OpDispatchBuilder::RORX(OpcodeArgs) { const auto Amount = Op->Src[1].Data.Literal.Value; const auto SrcSize = GetSrcSize(Op); const auto SrcSizeBits = SrcSize * 8; - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); const auto DoRotation = Amount != 0 && Amount < SrcSizeBits; const auto IsSameGPR = Op->Src[0].IsGPR() && Op->Dest.IsGPR() && @@ -2309,7 +2309,7 @@ void OpDispatchBuilder::MULX(OpcodeArgs) { // Src1 can be a memory operand, so ensure we constrain to the // absolute width of the access in that scenario. - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); const auto Src1Size = Op->Src[1].IsGPR() ? GPRSize : OperandSize; OrderedNode* Src1 = LoadSource_WithOpSize(GPRClass, Op, Op->Src[1], Src1Size, Op->Flags); @@ -2805,7 +2805,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) { if (Op->Dest.IsGPR()) { // When the destination is a GPR, we don't care about garbage in the upper bits. // Load the full register. - auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, GetGPRSize(), Op->Flags); + auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPRSize(), Op->Flags); Value = Dest; // Get the bit selection from the src. We need to mask for 8/16-bit, but @@ -3041,7 +3041,7 @@ void OpDispatchBuilder::IMULOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RDX, LocalResultHigh); } else if (Size == 8) { - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { LogMan::Msg::EFmt("Doesn't exist in 32bit mode"); DecodeFailure = true; return; @@ -3091,7 +3091,7 @@ void OpDispatchBuilder::MULOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RDX, ResultHigh); } else if (Size == 8) { - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { LogMan::Msg::EFmt("Doesn't exist in 32bit mode"); DecodeFailure = true; return; @@ -3138,7 +3138,7 @@ void OpDispatchBuilder::NOTOp(OpcodeArgs) { // Always load full size, we explicitly want the upper bits to get the // insert behaviour for free/implicitly. - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); OrderedNode *Src = LoadSource_WithOpSize(GPRClass, Op, Dest, GPRSize, Op->Flags); // For 8/16-bit, use 64-bit invert so we invert in place, while getting @@ -3502,7 +3502,7 @@ void OpDispatchBuilder::WriteSegmentReg(OpcodeArgs) { } void OpDispatchBuilder::EnterOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); LOGMAN_THROW_A_FMT(Op->Src[0].IsLiteral(), "Src1 needs to be literal here"); const uint64_t Value = Op->Src[0].Data.Literal.Value; @@ -3511,7 +3511,7 @@ void OpDispatchBuilder::EnterOp(OpcodeArgs) { const uint8_t Level = (Value >> 16) & 0x1F; const auto PushValue = [&](uint8_t Size, OrderedNode *Src) -> OrderedNode* { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); auto OldSP = LoadGPRRegister(X86State::REG_RSP); auto NewSP = _Push(GPRSize, Size, Src, OldSP); @@ -3552,7 +3552,7 @@ void OpDispatchBuilder::SGDTOp(OpcodeArgs) { // Operand size prefix is ignored on this instruction, size purely depends on operating mode. uint64_t GDTAddress = 0xFFFFFFFFFFFE0000ULL; size_t GDTStoreSize = 8; - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { // Mask off upper bits if 32-bit result. GDTAddress &= ~0U; GDTStoreSize = 4; @@ -3656,7 +3656,7 @@ void OpDispatchBuilder::STOSOp(OpcodeArgs) { // Calculate direction. auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); // Offset the pointer OrderedNode *TailDest = LoadGPRRegister(X86State::REG_RDI); @@ -3718,7 +3718,7 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) { } else { auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); OrderedNode *RSI = LoadGPRRegister(X86State::REG_RSI); OrderedNode *RDI = LoadGPRRegister(X86State::REG_RDI); @@ -3765,7 +3765,7 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); // Offset the pointer Dest_RDI = _Add(OpSize::i64Bit, Dest_RDI, PtrDir); @@ -3784,7 +3784,7 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { // read DF once auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); auto JumpStart = Jump(); // Make sure to start a new block after ending this one @@ -3878,7 +3878,7 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) { auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); // Offset the pointer OrderedNode *TailDest_RSI = LoadGPRRegister(X86State::REG_RSI); @@ -3899,7 +3899,7 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) { // Read DF once auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); auto JumpStart = Jump(); // Make sure to start a new block after ending this one @@ -3976,7 +3976,7 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) { auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); // Offset the pointer OrderedNode *TailDest_RDI = LoadGPRRegister(X86State::REG_RDI); @@ -3993,7 +3993,7 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) { // read DF once auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC); auto SizeConst = _Constant(Size); - auto PtrDir = _SubShift(IR::SizeToOpSize(GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); + auto PtrDir = _SubShift(IR::SizeToOpSize(CTX->GetGPRSize()), SizeConst, DF, ShiftType::LSL, FEXCore::ilog2(Size) + 1); auto JumpStart = Jump(); // Make sure to start a new block after ending this one @@ -4068,7 +4068,7 @@ void OpDispatchBuilder::BSWAPOp(OpcodeArgs) { Dest = _Constant(0); } else { - Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, GetGPRSize(), Op->Flags); + Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPRSize(), Op->Flags); Dest = _Rev(IR::SizeToOpSize(Size), Dest); } StoreResult(GPRClass, Op, Dest, -1); @@ -4084,7 +4084,7 @@ void OpDispatchBuilder::PUSHFOp(OpcodeArgs) { auto OldSP = LoadGPRRegister(X86State::REG_RSP); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); auto NewSP = _Push(GPRSize, Size, Src, OldSP); // Store the new stack pointer @@ -4141,7 +4141,7 @@ void OpDispatchBuilder::DIVOp(OpcodeArgs) { // This loads the divisor OrderedNode *Divisor = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); const auto Size = GetSrcSize(Op); if (Size == 1) { @@ -4174,7 +4174,7 @@ void OpDispatchBuilder::DIVOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RDX, URemOp); } else if (Size == 8) { - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { LogMan::Msg::EFmt("Doesn't exist in 32bit mode"); DecodeFailure = true; return; @@ -4194,7 +4194,7 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) { // This loads the divisor OrderedNode *Divisor = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); const auto Size = GetSrcSize(Op); if (Size == 1) { @@ -4229,7 +4229,7 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RDX, URemOp); } else if (Size == 8) { - if (!Is64BitMode) { + if (!CTX->Config.Is64BitMode) { LogMan::Msg::EFmt("Doesn't exist in 32bit mode"); DecodeFailure = true; return; @@ -4246,7 +4246,7 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) { } void OpDispatchBuilder::BSFOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); const uint8_t DstSize = GetDstSize(Op) == 2 ? 2 : GPRSize; OrderedNode *Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, DstSize, Op->Flags); OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); @@ -4267,7 +4267,7 @@ void OpDispatchBuilder::BSFOp(OpcodeArgs) { } void OpDispatchBuilder::BSROp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); const uint8_t DstSize = GetDstSize(Op) == 2 ? 2 : GPRSize; OrderedNode *Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, DstSize, Op->Flags); OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); @@ -4303,7 +4303,7 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) { // *Xn = Xt // Xs = MemData - const auto GPRSize = GetGPRSize(); + const auto GPRSize = CTX->GetGPRSize(); auto Size = GetSrcSize(Op); // This is our source register @@ -4501,11 +4501,8 @@ void OpDispatchBuilder::CreateJumpBlocks(fextl::vector const *Blocks, uint32_t NumInstructions, bool _Is64BitMode) { +void OpDispatchBuilder::BeginFunction(uint64_t RIP, fextl::vector const *Blocks, uint32_t NumInstructions) { Entry = RIP; - Is64BitMode = _Is64BitMode; - LOGMAN_THROW_A_FMT(Is64BitMode == CTX->Config.Is64BitMode, "Expected operating mode to not change at runtime!"); - auto IRHeader = _IRHeader(InvalidNode, RIP, 0, NumInstructions); CreateJumpBlocks(Blocks); @@ -4520,7 +4517,7 @@ void OpDispatchBuilder::Finalize() { // Calculate flags early. // This usually doesn't emit any IR but in the case of hitting the block instruction limit it will CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // Node 0 is invalid node OrderedNode *RealNode = reinterpret_cast(GetNode(1)); @@ -4561,7 +4558,7 @@ uint32_t OpDispatchBuilder::GetDstBitSize(X86Tables::DecodedOp Op) const { } OrderedNode *OpDispatchBuilder::GetSegment(uint32_t Flags, uint32_t DefaultPrefix, bool Override) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); if (CTX->Config.Is64BitMode) { if (Flags & FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX) { @@ -4708,14 +4705,8 @@ void OpDispatchBuilder::UpdatePrefixFromSegment(OrderedNode *Segment, uint32_t S // Use BFE to extract the selector index in bits [15,3] of the segment register. // In some cases the upper 16-bits of the 32-bit GPR contain garbage to ignore. Segment = _Bfe(OpSize::i32Bit, 16 - 3, 3, Segment); - OrderedNode *NewSegment = _LoadContextIndexed(Segment, 8, offsetof(FEXCore::Core::CPUState, gdt[0]), 8, GPRClass); + auto NewSegment = _LoadContextIndexed(Segment, 4, offsetof(FEXCore::Core::CPUState, gdt[0]), 4, GPRClass); CheckLegacySegmentWrite(NewSegment, SegmentReg); - - // Extract the 32-bit base from the GDT segment. - auto Upper32 = _Lshr(OpSize::i64Bit, NewSegment, _Constant(32)); - auto Masked = _And(OpSize::i32Bit, Upper32, _Constant(0xFF00'0000)); - OrderedNode *Merged = _Orlshr(OpSize::i32Bit, Masked, NewSegment, 16); - NewSegment = _Bfi(OpSize::i32Bit, 8, 16, Merged, Upper32); switch (SegmentReg) { case FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX: _StoreContext(4, GPRClass, NewSegment, offsetof(FEXCore::Core::CPUState, es_cached)); @@ -4753,7 +4744,7 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X OrderedNode *Src {nullptr}; bool LoadableType = false; - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); const uint32_t AddrSize = (Op->Flags & X86Tables::DecodeFlags::FLAG_ADDRESS_SIZE) != 0 ? (GPRSize >> 1) : GPRSize; if (Operand.IsLiteral()) { @@ -4811,7 +4802,7 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X } } else if (Operand.IsRIPRelative()) { - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { Src = GetRelocatedPC(Op, Operand.Data.RIPLiteral.Value.s); } else { @@ -4913,12 +4904,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X } OrderedNode *OpDispatchBuilder::GetRelocatedPC(FEXCore::X86Tables::DecodedOp const& Op, int64_t Offset) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); return _EntrypointOffset(IR::SizeToOpSize(GPRSize), Op->PC + Op->InstSize + Offset - Entry); } OrderedNode *OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, int8_t Size, uint8_t Offset, bool AllowUpperGarbage) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); if (Size == -1) { Size = GPRSize; } @@ -4946,7 +4937,7 @@ OrderedNode *OpDispatchBuilder::LoadXMMRegister(uint32_t XMM) { } void OpDispatchBuilder::StoreGPRRegister(uint32_t GPR, OrderedNode *const Src, int8_t Size, uint8_t Offset) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); if (Size == -1) { Size = GPRSize; } @@ -4989,7 +4980,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl // 32bit ops ZEXT the result to 64bit OrderedNode *MemStoreDst {nullptr}; bool MemStore = false; - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); const uint32_t AddrSize = (Op->Flags & X86Tables::DecodeFlags::FLAG_ADDRESS_SIZE) != 0 ? (GPRSize >> 1) : GPRSize; if (Operand.IsLiteral()) { @@ -5067,7 +5058,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl } } else if (Operand.IsRIPRelative()) { - if (Is64BitMode) { + if (CTX->Config.Is64BitMode) { MemStoreDst = GetRelocatedPC(Op, Operand.Data.RIPLiteral.Value.s); } else { @@ -5334,7 +5325,7 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) { // Calculate flags early. CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); if (SetRIPToNext) { BlockSetRIP = SetRIPToNext; @@ -5395,7 +5386,7 @@ void OpDispatchBuilder::LZCNT(OpcodeArgs) { } void OpDispatchBuilder::MOVBEOp(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); const auto SrcSize = GetSrcSize(Op); OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.Align = 1}); @@ -5485,7 +5476,7 @@ void OpDispatchBuilder::RDTSCPOp(OpcodeArgs) { } void OpDispatchBuilder::CRC32(OpcodeArgs) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // Destination GPR size is always 4 or 8 bytes depending on widening uint8_t DstSize = Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_REX_WIDENING ? 8 : 4; @@ -5518,7 +5509,7 @@ void OpDispatchBuilder::UnimplementedOp(OpcodeArgs) { // Ensure flags are calculated on invalid op. CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // We don't actually support this instruction // Multiblock may hit it though @@ -5543,7 +5534,7 @@ void OpDispatchBuilder::InvalidOp(OpcodeArgs) { // Ensure flags are calculated on invalid op. CalculateDeferredFlags(); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // We don't actually support this instruction // Multiblock may hit it though diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index abee3f8b89..807c24f434 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -185,7 +185,7 @@ friend class FEXCore::IR::PassManager; auto it = JumpTargets.find(NextRIP); if (it == JumpTargets.end()) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // If we don't have a jump target to a new block then we have to leave // Set the RIP to the next instruction and leave auto RelocatedNextRIP = _EntrypointOffset(IR::SizeToOpSize(GPRSize), NextRIP - Entry); @@ -245,7 +245,7 @@ friend class FEXCore::IR::PassManager; void SetDumpIR(bool DumpIR) { ShouldDump = DumpIR; } bool ShouldDumpIR() const { return ShouldDump; } - void BeginFunction(uint64_t RIP, fextl::vector const *Blocks, uint32_t NumInstructions, bool Is64BitMode); + void BeginFunction(uint64_t RIP, fextl::vector const *Blocks, uint32_t NumInstructions); void Finalize(); // Dispatch builder functions @@ -923,8 +923,6 @@ friend class FEXCore::IR::PassManager; } } - uint8_t GetGPRSize() const { return Is64BitMode ? 8 : 4; } - protected: void SaveNZCV(IROps Op = OP_DUMMY) override { /* Some opcodes are conservatively marked as clobbering flags, but in fact @@ -1367,9 +1365,9 @@ friend class FEXCore::IR::PassManager; if (IsNZCV(BitOffset)) { InsertNZCV(BitOffset, Value, ValueOffset, MustMask); } else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) { - _StoreRegister(Value, false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, GetGPRSize()); + _StoreRegister(Value, false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize()); } else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) { - _StoreRegister(Value, false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, GetGPRSize()); + _StoreRegister(Value, false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize()); } else { if (ValueOffset || MustMask) Value = _Bfe(OpSize::i32Bit, 1, ValueOffset, Value); @@ -1423,9 +1421,9 @@ friend class FEXCore::IR::PassManager; _Constant(1), _Constant(0)); } } else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) { - return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, GetGPRSize()); + return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize()); } else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) { - return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, GetGPRSize()); + return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize()); } else { return _LoadFlag(BitOffset); } @@ -2160,7 +2158,6 @@ friend class FEXCore::IR::PassManager; bool Multiblock{}; uint64_t Entry; - bool Is64BitMode{}; OrderedNode* _StoreMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, OrderedNode *Addr, OrderedNode *Value, uint8_t Align = 1) { if (CTX->IsAtomicTSOEnabled()) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 71f020930e..a23cb0f78a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -698,7 +698,7 @@ OrderedNode* OpDispatchBuilder::InsertCVTGPR_To_FPRImpl(OpcodeArgs, if (Src2Op.IsGPR()) { // If the source is a GPR then convert directly from the GPR. - auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPRSize(), Op->Flags); + auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPRSize(), Op->Flags); return _VSToFGPRInsert(IR::SizeToOpSize(DstSize), DstElementSize, SrcSize, Src1, Src2, ZeroUpperBits); } else if (SrcSize != DstElementSize) { @@ -1060,7 +1060,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs) { GPR = _Bfi(OpSize::i64Bit, 32, 31, GPR, GPR); // Shift right to only get the two sign bits we care about. GPR = _Lshr(OpSize::i64Bit, GPR, _Constant(62)); - StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, GetGPRSize(), -1); + StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, CTX->GetGPRSize(), -1); } else if (Size == 16 && ElementSize == 4) { // Shift all the sign bits to the bottom of their respective elements. @@ -1073,7 +1073,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs) { Src = _VAddV(Size, 4, Src); // Extract to a GPR. OrderedNode *GPR = _VExtractToGPR(Size, 4, Src, 0); - StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, GetGPRSize(), -1); + StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, CTX->GetGPRSize(), -1); } else { OrderedNode *CurrentVal = _Constant(0); @@ -1759,7 +1759,7 @@ void OpDispatchBuilder::VBROADCASTOp(OpcodeArgs) { Result = _VDupElement(DstSize, ElementSize, Src, 0); } else { // Get the address to broadcast from into a GPR. - OrderedNode *Address = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], GetGPRSize(), Op->Flags, + OrderedNode *Address = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], CTX->GetGPRSize(), Op->Flags, {.LoadData = false}); Address = AppendSegmentOffset(Address, Op->Flags); @@ -1795,7 +1795,7 @@ OrderedNode* OpDispatchBuilder::PINSROpImpl(OpcodeArgs, size_t ElementSize, if (Src2Op.IsGPR()) { // If the source is a GPR then convert directly from the GPR. - auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPRSize(), Op->Flags); + auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPRSize(), Op->Flags); return _VInsGPR(Size, ElementSize, Index, Src1, Src2); } @@ -1924,7 +1924,7 @@ void OpDispatchBuilder::PExtrOp(OpcodeArgs) { Index &= NumElements - 1; if (Op->Dest.IsGPR()) { - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); // Extract already zero extends the result. OrderedNode *Result = _VExtractToGPR(16, OverridenElementSize, Src, Index); StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Result, GPRSize, -1); @@ -2477,7 +2477,7 @@ OrderedNode* OpDispatchBuilder::CVTGPR_To_FPRImpl(OpcodeArgs, size_t DstElementS OrderedNode *Converted{}; if (Src2Op.IsGPR()) { // If the source is a GPR then convert directly from the GPR. - auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPRSize(), Op->Flags); + auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPRSize(), Op->Flags); Converted = _Float_FromGPR_S(DstElementSize, SrcSize, Src2); } else if (SrcSize != DstElementSize) { @@ -2826,7 +2826,7 @@ void OpDispatchBuilder::VMASKMOVOpImpl(OpcodeArgs, size_t ElementSize, size_t Da const X86Tables::DecodedOperand& DataOp) { const auto MakeAddress = [this, Op](const X86Tables::DecodedOperand& Data) { - OrderedNode *BaseAddr = LoadSource_WithOpSize(GPRClass, Op, Data, GetGPRSize(), Op->Flags, + OrderedNode *BaseAddr = LoadSource_WithOpSize(GPRClass, Op, Data, CTX->GetGPRSize(), Op->Flags, {.LoadData = false}); return AppendSegmentOffset(BaseAddr, Op->Flags); }; @@ -2877,7 +2877,7 @@ void OpDispatchBuilder::MOVBetweenGPR_FPR(OpcodeArgs) { Op->Dest.Data.GPR.GPR >= FEXCore::X86State::REG_XMM_0) { if (Op->Src[0].IsGPR()) { // Loading from GPR and moving to Vector. - OrderedNode *Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], GetGPRSize(), Op->Flags); + OrderedNode *Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], CTX->GetGPRSize(), Op->Flags); // zext to 128bit auto Converted = _VCastFromGPR(16, GetSrcSize(Op), Src); StoreResult(FPRClass, Op, Op->Dest, Converted, -1); @@ -3011,7 +3011,7 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) { // for features that are in the lower 32 bits, so EAX only is sufficient. OrderedNode *Mask = LoadGPRRegister(X86State::REG_RAX); OrderedNode *Base = XSaveBase(); - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); const auto StoreIfFlagSet = [&](uint32_t BitIndex, auto fn, uint32_t FieldSize = 1){ OrderedNode *BitFlag = _Bfe(OpSize, FieldSize, BitIndex, Mask); @@ -3065,7 +3065,7 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) { } void OpDispatchBuilder::SaveX87State(OpcodeArgs, OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); // Saves 512bytes to the memory location provided // Header changes depending on if REX.W is set or not if (Op->Flags & X86Tables::DecodeFlags::FLAG_REX_WIDENING) { @@ -3151,8 +3151,8 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, OrderedNode *MemBase) { } void OpDispatchBuilder::SaveSSEState(OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; for (uint32_t i = 0; i < NumRegs; ++i) { OrderedNode *XMMReg = LoadXMMRegister(i); @@ -3163,7 +3163,7 @@ void OpDispatchBuilder::SaveSSEState(OrderedNode *MemBase) { } void OpDispatchBuilder::SaveMXCSRState(OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); OrderedNode *MXCSR = GetMXCSR(); OrderedNode *MXCSRLocation = _Add(OpSize, MemBase, _Constant(24)); @@ -3175,8 +3175,8 @@ void OpDispatchBuilder::SaveMXCSRState(OrderedNode *MemBase) { } void OpDispatchBuilder::SaveAVXState(OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; for (uint32_t i = 0; i < NumRegs; ++i) { OrderedNode *Upper = _VDupElement(32, 16, LoadXMMRegister(i), 1); @@ -3194,7 +3194,7 @@ OrderedNode *OpDispatchBuilder::GetMXCSR() { } void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.LoadData = false}); Mem = AppendSegmentOffset(Mem, Op->Flags); @@ -3208,7 +3208,7 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) { } void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); const auto XSaveBase = [this, Op] { OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false}); @@ -3283,7 +3283,7 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) { } void OpDispatchBuilder::RestoreX87State(OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); auto NewFCW = _LoadMem(GPRClass, 2, MemBase, 2); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); @@ -3309,8 +3309,8 @@ void OpDispatchBuilder::RestoreX87State(OrderedNode *MemBase) { } void OpDispatchBuilder::RestoreSSEState(OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; for (uint32_t i = 0; i < NumRegs; ++i) { OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 160)); @@ -3326,8 +3326,8 @@ void OpDispatchBuilder::RestoreMXCSRState(OrderedNode *MXCSR) { } void OpDispatchBuilder::RestoreAVXState(OrderedNode *MemBase) { - const auto OpSize = IR::SizeToOpSize(GetGPRSize()); - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; for (uint32_t i = 0; i < NumRegs; ++i) { OrderedNode *XMMReg = LoadXMMRegister(i); @@ -3352,7 +3352,7 @@ void OpDispatchBuilder::DefaultX87State(OpcodeArgs) { } void OpDispatchBuilder::DefaultSSEState() { - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; OrderedNode *ZeroVector = LoadAndCacheNamedVectorConstant(Core::CPUState::XMM_SSE_REG_SIZE, FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_ZERO); for (uint32_t i = 0; i < NumRegs; ++i) { @@ -3361,7 +3361,7 @@ void OpDispatchBuilder::DefaultSSEState() { } void OpDispatchBuilder::DefaultAVXState() { - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; for (uint32_t i = 0; i < NumRegs; i++) { OrderedNode* Reg = LoadXMMRegister(i); @@ -5346,7 +5346,7 @@ void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) { void OpDispatchBuilder::VZEROOp(OpcodeArgs) { const auto DstSize = GetDstSize(Op); const auto IsVZEROALL = DstSize == Core::CPUState::XMM_AVX_REG_SIZE; - const auto NumRegs = Is64BitMode ? 16U : 8U; + const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U; if (IsVZEROALL) { // NOTE: Despite the name being VZEROALL, this will still only ever @@ -5550,7 +5550,7 @@ void OpDispatchBuilder::PCMPXSTRXOpImpl(OpcodeArgs, bool IsExplicit, bool IsMask OrderedNode *Result = _Select(IR::COND_EQ, ResultNoFlags, ZeroConst, IfZero, IfNotZero); - const uint8_t GPRSize = GetGPRSize(); + const uint8_t GPRSize = CTX->GetGPRSize(); if (GPRSize == 8) { // If being stored to an 8-byte register, zero extend the 4-byte result. Result = _Bfe(OpSize::i64Bit, 32, 0, Result); diff --git a/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp b/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp index 12b993a609..9fcdb2a6a3 100644 --- a/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp +++ b/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp @@ -240,7 +240,7 @@ namespace FEXCore { IRHeader.first->Blocks = emit->WrapNode(Block); emit->SetCurrentCodeBlock(Block); - const uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4; + const uint8_t GPRSize = CTX->GetGPRSize(); if (GPRSize == 8) { emit->_StoreRegister(emit->_Constant(Entrypoint), false, offsetof(Core::CPUState, gregs[X86State::REG_R11]), IR::GPRClass, IR::GPRFixedClass, GPRSize); From ccf1402fe6d8dbcb1ef9929e0b13cb8e1e8f9db4 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 1 Feb 2024 18:14:30 -0800 Subject: [PATCH 3/4] Revert "FEXCore: Accurately store segment descriptors" This reverts commit 8648fb148556459b277dcd7e53a0fc092b626875. --- FEXCore/Source/Interface/Core/Core.cpp | 16 ------- FEXCore/include/FEXCore/Core/CoreState.h | 44 +------------------ .../LinuxSyscalls/SignalDelegator.cpp | 24 +++++----- .../LinuxSyscalls/x32/Thread.cpp | 21 ++++----- 4 files changed, 25 insertions(+), 80 deletions(-) diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp index 6de199a8f0..fa95821a94 100644 --- a/FEXCore/Source/Interface/Core/Core.cpp +++ b/FEXCore/Source/Interface/Core/Core.cpp @@ -569,22 +569,6 @@ namespace FEXCore::Context { Thread->CurrentFrame->State.gregs[X86State::REG_RSP] = StackPointer; Thread->CurrentFrame->State.rip = InitialRIP; - // Set up default code segment. - // Default code segment indexes match the numbers that the Linux kernel uses. - Thread->CurrentFrame->State.cs_idx = 6 << 3; - auto &GDT = Thread->CurrentFrame->State.gdt[Thread->CurrentFrame->State.cs_idx >> 3]; - Thread->CurrentFrame->State.SetGDTBase(&GDT, 0); - Thread->CurrentFrame->State.SetGDTLimit(&GDT, 0xF'FFFFU); - - if (Config.Is64BitMode) { - GDT.L = 1; // L = Long Mode = 64-bit - GDT.D = 0; // D = Default Operand SIze = Reserved - } - else { - GDT.L = 0; // L = Long Mode = 32-bit - GDT.D = 1; // D = Default Operand Size = 32-bit - } - // Copy over the new thread state to the new object if (NewThreadState) { memcpy(&Thread->CurrentFrame->State, NewThreadState, sizeof(FEXCore::Core::CPUState)); diff --git a/FEXCore/include/FEXCore/Core/CoreState.h b/FEXCore/include/FEXCore/Core/CoreState.h index 6d80e9e1a4..5d7ab16d44 100644 --- a/FEXCore/include/FEXCore/Core/CoreState.h +++ b/FEXCore/include/FEXCore/Core/CoreState.h @@ -107,48 +107,9 @@ namespace FEXCore::Core { uint64_t mm[8][2]{}; // 32bit x86 state - struct gdt_segment { - uint16_t Limit0; - uint16_t Base0; - uint16_t Base1 : 8; - uint16_t Type : 4; - uint16_t S : 1; - uint16_t DPL : 2; - uint16_t P : 1; - uint16_t Limit1 : 4; - uint16_t AVL : 1; - uint16_t L : 1; - uint16_t D : 1; - uint16_t G : 1; - uint16_t Base2 : 8; + struct { + uint32_t base; } gdt[32]{}; - - static uint32_t CalculateGDTBase(gdt_segment GDT) { - uint32_t Base{}; - Base |= GDT.Base2 << 24; - Base |= GDT.Base1 << 16; - Base |= GDT.Base0; - return Base; - } - - static uint32_t CalculateGDTLimit(gdt_segment GDT) { - uint32_t Limit{}; - Limit |= GDT.Limit1 << 16; - Limit |= GDT.Limit0; - return Limit; - } - - static void SetGDTBase(gdt_segment *GDT, uint32_t Base) { - GDT->Base0 = Base; - GDT->Base1 = Base >> 16; - GDT->Base2 = Base >> 24; - } - - static void SetGDTLimit(gdt_segment *GDT, uint32_t Limit) { - GDT->Limit0 = Limit; - GDT->Limit1 = Limit >> 16; - } - uint16_t FCW { 0x37F }; uint8_t AbridgedFTW{}; @@ -161,7 +122,6 @@ namespace FEXCore::Core { static constexpr size_t FLAG_SIZE = sizeof(flags[0]); static constexpr size_t GDT_SIZE = sizeof(gdt[0]); - static_assert(GDT_SIZE == sizeof(uint64_t), "Segments required to be 8-byte in size."); static constexpr size_t GPR_REG_SIZE = sizeof(gregs[0]); static constexpr size_t XMM_AVX_REG_SIZE = sizeof(xmm.avx.data[0]); static constexpr size_t XMM_SSE_REG_SIZE = XMM_AVX_REG_SIZE / 2; diff --git a/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp b/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp index 1eb8985f43..92e4248388 100644 --- a/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp +++ b/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp @@ -512,12 +512,12 @@ namespace FEX::HLE { Frame->State.gs_idx = guest_uctx->sc.gs; Frame->State.ss_idx = guest_uctx->sc.ss; - Frame->State.cs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.cs_idx >> 3]); - Frame->State.ds_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ds_idx >> 3]); - Frame->State.es_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.es_idx >> 3]); - Frame->State.fs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.fs_idx >> 3]); - Frame->State.gs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.gs_idx >> 3]); - Frame->State.ss_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ss_idx >> 3]); + Frame->State.cs_cached = Frame->State.gdt[Frame->State.cs_idx >> 3].base; + Frame->State.ds_cached = Frame->State.gdt[Frame->State.ds_idx >> 3].base; + Frame->State.es_cached = Frame->State.gdt[Frame->State.es_idx >> 3].base; + Frame->State.fs_cached = Frame->State.gdt[Frame->State.fs_idx >> 3].base; + Frame->State.gs_cached = Frame->State.gdt[Frame->State.gs_idx >> 3].base; + Frame->State.ss_cached = Frame->State.gdt[Frame->State.ss_idx >> 3].base; #define COPY_REG(x, y) \ Frame->State.gregs[FEXCore::X86State::REG_##x] = guest_uctx->sc.y; @@ -592,12 +592,12 @@ namespace FEX::HLE { Frame->State.gs_idx = guest_uctx->uc.uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS]; Frame->State.ss_idx = guest_uctx->uc.uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS]; - Frame->State.cs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.cs_idx >> 3]); - Frame->State.ds_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ds_idx >> 3]); - Frame->State.es_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.es_idx >> 3]); - Frame->State.fs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.fs_idx >> 3]); - Frame->State.gs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.gs_idx >> 3]); - Frame->State.ss_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ss_idx >> 3]); + Frame->State.cs_cached = Frame->State.gdt[Frame->State.cs_idx >> 3].base; + Frame->State.ds_cached = Frame->State.gdt[Frame->State.ds_idx >> 3].base; + Frame->State.es_cached = Frame->State.gdt[Frame->State.es_idx >> 3].base; + Frame->State.fs_cached = Frame->State.gdt[Frame->State.fs_idx >> 3].base; + Frame->State.gs_cached = Frame->State.gdt[Frame->State.gs_idx >> 3].base; + Frame->State.ss_cached = Frame->State.gdt[Frame->State.ss_idx >> 3].base; #define COPY_REG(x) \ Frame->State.gregs[FEXCore::X86State::REG_##x] = guest_uctx->uc.uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x]; diff --git a/Source/Tools/LinuxEmulation/LinuxSyscalls/x32/Thread.cpp b/Source/Tools/LinuxEmulation/LinuxSyscalls/x32/Thread.cpp index bc5d9123bf..9bbfbdfefa 100644 --- a/Source/Tools/LinuxEmulation/LinuxSyscalls/x32/Thread.cpp +++ b/Source/Tools/LinuxEmulation/LinuxSyscalls/x32/Thread.cpp @@ -53,8 +53,8 @@ namespace FEX::HLE::x32 { if (u_info->entry_number == -1) { for (uint32_t i = TLS_NextEntry; i < TLS_MaxEntry; ++i) { auto GDT = &Frame->State.gdt[i]; - if (Frame->State.CalculateGDTLimit(*GDT) == 0) { - // If the limit is zero then it isn't present in our setup. + if (GDT->base == 0) { + // If the base is zero then it isn't present with our setup u_info->entry_number = i; break; } @@ -68,29 +68,29 @@ namespace FEX::HLE::x32 { // Now we need to update the thread's GDT to handle this change auto GDT = &Frame->State.gdt[u_info->entry_number]; - Frame->State.SetGDTBase(GDT, u_info->base_addr); + GDT->base = u_info->base_addr; // With the segment register optimization we need to check all of the segment registers and update. const auto GetEntry = [](auto value) { return value >> 3; }; if (GetEntry(Frame->State.cs_idx) == u_info->entry_number) { - Frame->State.cs_cached = Frame->State.CalculateGDTBase(*GDT); + Frame->State.cs_cached = GDT->base; } if (GetEntry(Frame->State.ds_idx) == u_info->entry_number) { - Frame->State.ds_cached = Frame->State.CalculateGDTBase(*GDT); + Frame->State.ds_cached = GDT->base; } if (GetEntry(Frame->State.es_idx) == u_info->entry_number) { - Frame->State.es_cached = Frame->State.CalculateGDTBase(*GDT); + Frame->State.es_cached = GDT->base; } if (GetEntry(Frame->State.fs_idx) == u_info->entry_number) { - Frame->State.fs_cached = Frame->State.CalculateGDTBase(*GDT); + Frame->State.fs_cached = GDT->base; } if (GetEntry(Frame->State.gs_idx) == u_info->entry_number) { - Frame->State.gs_cached = Frame->State.CalculateGDTBase(*GDT); + Frame->State.gs_cached = GDT->base; } if (GetEntry(Frame->State.ss_idx) == u_info->entry_number) { - Frame->State.ss_cached = Frame->State.CalculateGDTBase(*GDT); + Frame->State.ss_cached = GDT->base; } return 0; } @@ -150,7 +150,8 @@ namespace FEX::HLE::x32 { memset(u_info, 0, sizeof(*u_info)); - u_info->base_addr = Frame->State.CalculateGDTBase(*GDT); + // FEX only stores base instead of the full GDT + u_info->base_addr = GDT->base; // Fill the rest of the structure with expected data (even if wrong at the moment) if (u_info->base_addr) { From 45587278c994f81de2bbc1043f4c470d9cf4c3cc Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 1 Feb 2024 18:17:28 -0800 Subject: [PATCH 4/4] InstCountCI: Update for segment changes --- .../InstructionCountCI/Crypto/H0F3A.json | 4 +- .../InstructionCountCI/FEXOpt/libnss.json | 6 +- .../FlagM/SecondaryGroup.json | 20 +- .../FlagM/SecondaryModRM.json | 8 +- unittests/InstructionCountCI/FlagM/x87.json | 1814 ++++++++--------- .../InstructionCountCI/FlagM/x87_f64.json | 724 +++---- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 14 +- unittests/InstructionCountCI/Primary.json | 30 +- .../InstructionCountCI/PrimaryGroup.json | 8 +- .../InstructionCountCI/Primary_32Bit.json | 30 +- unittests/InstructionCountCI/Secondary.json | 38 +- .../InstructionCountCI/SecondaryGroup.json | 20 +- .../InstructionCountCI/SecondaryModRM.json | 8 +- .../InstructionCountCI/Secondary_32Bit.json | 20 +- .../InstructionCountCI/Secondary_OpSize.json | 6 +- .../InstructionCountCI/Secondary_REP.json | 2 +- .../InstructionCountCI/Secondary_REPNE.json | 4 +- unittests/InstructionCountCI/VEX_map1.json | 14 +- unittests/InstructionCountCI/VEX_map2.json | 2 +- unittests/InstructionCountCI/VEX_map3.json | 4 +- unittests/InstructionCountCI/x87.json | 1814 ++++++++--------- unittests/InstructionCountCI/x87_f64.json | 724 +++---- 23 files changed, 2638 insertions(+), 2678 deletions(-) diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 7d029a69cc..28d7f326ec 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -55,7 +55,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2208]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -68,7 +68,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2208]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 78c4778ef6..7a5cc458b3 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -199,10 +199,10 @@ "ldr q19, [x11, #272]", "ldr q24, [x11]", "ldr q23, [x11, #16]", - "ldr x0, [x28, #1816]", + "ldr x0, [x28, #1688]", "ldr q2, [x0, #2832]", "tbl v16.16b, {v18.16b}, v2.16b", - "ldr x0, [x28, #1816]", + "ldr x0, [x28, #1688]", "ldr q3, [x0, #432]", "tbl v18.16b, {v19.16b}, v3.16b", "ldr q22, [x11, #32]", @@ -346,7 +346,7 @@ "mov v4.s[1], w21", "mov v20.16b, v4.16b", "mov v20.s[0], w23", - "ldr x0, [x28, #1816]", + "ldr x0, [x28, #1688]", "ldr q4, [x0, #224]", "tbl v16.16b, {v16.16b}, v4.16b", "mov w20, v20.s[3]", diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 494785471c..441dfd9a66 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -1200,7 +1200,7 @@ "ExpectedInstructionCount": 58, "Comment": "GROUP15 0x0F 0xAE /0", "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1214,7 +1214,7 @@ "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", "strh w20, [x4, #2]", - "ldrb w20, [x28, #1154]", + "ldrb w20, [x28, #1026]", "strb w20, [x4, #4]", "ldr q2, [x28, #768]", "str q2, [x4, #32]", @@ -1279,7 +1279,7 @@ "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1292,7 +1292,7 @@ "strb w23, [x28, #746]", "strb w20, [x28, #750]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "ldr q2, [x4, #32]", "str q2, [x28, #768]", "ldr q2, [x4, #48]", @@ -1417,7 +1417,7 @@ "ubfx x22, x20, #0, #1", "cbnz x22, #+0x8", "b #+0x84", - "ldrh w22, [x28, #1152]", + "ldrh w22, [x28, #1024]", "strh w22, [x21]", "mov w22, #0x0", "ldrb w23, [x28, #747]", @@ -1431,7 +1431,7 @@ "orr x22, x22, x25, lsl #10", "orr x22, x22, x30, lsl #14", "strh w22, [x21, #2]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "strb w22, [x21, #4]", "ldr q2, [x28, #768]", "str q2, [x21, #32]", @@ -1502,7 +1502,7 @@ "cbnz x22, #+0x8", "b #+0x84", "ldrh w22, [x20]", - "strh w22, [x28, #1152]", + "strh w22, [x28, #1024]", "ldrh w22, [x20, #2]", "ubfx w23, w22, #11, #3", "strb w23, [x28, #747]", @@ -1515,7 +1515,7 @@ "strb w25, [x28, #746]", "strb w22, [x28, #750]", "ldrb w22, [x20, #4]", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "ldr q2, [x20, #32]", "str q2, [x28, #768]", "ldr q2, [x20, #48]", @@ -1535,13 +1535,13 @@ "b #+0x4c", "mov w22, #0x0", "mov w23, #0x37f", - "strh w23, [x28, #1152]", + "strh w23, [x28, #1024]", "strb w22, [x28, #747]", "strb w22, [x28, #744]", "strb w22, [x28, #745]", "strb w22, [x28, #746]", "strb w22, [x28, #750]", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "movi v2.2d, #0x0", "str q2, [x28, #768]", "str q2, [x28, #784]", diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index a74055f7d0..cc7c0b8487 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -42,8 +42,8 @@ "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64", "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64", "mov w1, w5", - "ldr x0, [x28, #1240]", - "ldr x2, [x28, #1256]", + "ldr x0, [x28, #1112]", + "ldr x2, [x28, #1128]", "blr x2", "ldr w4, [x28, #728]", "msr nzcv, x4", @@ -85,7 +85,7 @@ "str w0, [x28, #728]", "str x8, [x28, #40]", "mov w0, #0x100", - "str x0, [x28, #1184]", + "str x0, [x28, #1056]", "sub sp, sp, #0x10 (16)", "mov w8, #0xa8", "mov x0, sp", @@ -96,7 +96,7 @@ "ldr w8, [x28, #728]", "msr nzcv, x8", "ldr x8, [x28, #40]", - "str xzr, [x28, #1184]", + "str xzr, [x28, #1056]", "orr x5, x0, x1, lsl #12" ] } diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index d6c37e418d..77642efcfd 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -46,8 +46,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -100,12 +100,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -169,8 +169,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -223,12 +223,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -292,8 +292,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -346,12 +346,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -421,8 +421,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -475,12 +475,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -515,11 +515,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -558,8 +558,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -612,12 +612,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -681,8 +681,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -735,12 +735,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -804,8 +804,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -858,12 +858,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -927,8 +927,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -981,12 +981,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1054,12 +1054,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1127,12 +1127,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1200,12 +1200,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1273,12 +1273,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1346,12 +1346,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1419,12 +1419,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1492,12 +1492,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1565,12 +1565,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1638,12 +1638,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1711,12 +1711,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1784,12 +1784,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1857,12 +1857,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1930,12 +1930,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2003,12 +2003,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2076,12 +2076,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2149,12 +2149,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2223,12 +2223,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2301,12 +2301,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2380,12 +2380,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2459,12 +2459,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2538,12 +2538,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2617,12 +2617,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2696,12 +2696,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2775,12 +2775,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2855,12 +2855,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2894,11 +2894,11 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -2942,12 +2942,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2982,10 +2982,10 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3028,12 +3028,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3068,11 +3068,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3115,12 +3115,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3155,11 +3155,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3202,12 +3202,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3242,11 +3242,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3289,12 +3289,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3329,11 +3329,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3376,12 +3376,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3416,11 +3416,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3463,12 +3463,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3503,11 +3503,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3550,12 +3550,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3623,12 +3623,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3696,12 +3696,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3769,12 +3769,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3842,12 +3842,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3915,12 +3915,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3988,12 +3988,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4061,12 +4061,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4134,12 +4134,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4207,12 +4207,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4280,12 +4280,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4353,12 +4353,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4426,12 +4426,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4499,12 +4499,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4572,12 +4572,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4645,12 +4645,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4718,12 +4718,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4791,12 +4791,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4864,12 +4864,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4937,12 +4937,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5010,12 +5010,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5083,12 +5083,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5156,12 +5156,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5229,12 +5229,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5302,12 +5302,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5375,12 +5375,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5448,12 +5448,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5521,12 +5521,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5594,12 +5594,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5667,12 +5667,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5740,12 +5740,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5813,12 +5813,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5882,8 +5882,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5913,10 +5913,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -5955,10 +5955,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1304]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6019,10 +6019,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1304]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6048,11 +6048,11 @@ "ldr x27, [x28, #760]", "fmov s2, s0", "str s2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6065,7 +6065,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -6110,7 +6110,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -6121,7 +6121,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -6130,7 +6130,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -6146,7 +6146,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -6202,7 +6202,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -6220,10 +6220,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6243,10 +6243,10 @@ "ldr q2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6266,10 +6266,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6289,10 +6289,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6312,10 +6312,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6335,10 +6335,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6358,10 +6358,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6381,10 +6381,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6620,12 +6620,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6673,7 +6673,7 @@ "mov x21, v2.d[1]", "ubfx x21, x21, #15, #1", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", @@ -6695,10 +6695,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8000000000000000", "mov w22, #0x3fff", @@ -6718,10 +6718,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8afe", "movk x21, #0xcd1b, lsl #16", @@ -6744,10 +6744,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf0bc", "movk x21, #0x5c17, lsl #16", @@ -6770,10 +6770,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xc235", "movk x21, #0x2168, lsl #16", @@ -6796,10 +6796,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf799", "movk x21, #0xfbcf, lsl #16", @@ -6822,10 +6822,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ac", "movk x21, #0xd1cf, lsl #16", @@ -6848,10 +6848,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", @@ -6893,10 +6893,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1456]", + "ldr x3, [x28, #1328]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6934,11 +6934,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -6970,12 +6970,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1560]", + "ldr x5, [x28, #1432]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7016,10 +7016,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #768]", @@ -7047,10 +7047,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1464]", + "ldr x3, [x28, #1336]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7096,11 +7096,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -7132,12 +7132,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1568]", + "ldr x5, [x28, #1440]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7178,10 +7178,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #768]", @@ -7209,10 +7209,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1496]", + "ldr x3, [x28, #1368]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7263,10 +7263,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1504]", + "ldr x3, [x28, #1376]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7336,12 +7336,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1576]", + "ldr x5, [x28, #1448]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7435,12 +7435,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1584]", + "ldr x5, [x28, #1456]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7480,11 +7480,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -7520,12 +7520,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v4.d[0]", "umov w4, v4.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7576,12 +7576,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1560]", + "ldr x5, [x28, #1432]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7645,10 +7645,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1472]", + "ldr x3, [x28, #1344]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7689,10 +7689,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #768]", @@ -7720,10 +7720,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1480]", + "ldr x3, [x28, #1352]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7774,10 +7774,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1488]", + "ldr x3, [x28, #1360]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7845,10 +7845,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1448]", + "ldr x3, [x28, #1320]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7916,12 +7916,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1592]", + "ldr x5, [x28, #1464]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7985,10 +7985,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1480]", + "ldr x3, [x28, #1352]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8054,10 +8054,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1488]", + "ldr x3, [x28, #1360]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8123,8 +8123,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8177,12 +8177,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8246,8 +8246,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8300,12 +8300,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8369,8 +8369,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8423,12 +8423,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8498,8 +8498,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8552,12 +8552,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8592,11 +8592,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8635,8 +8635,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8689,12 +8689,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8758,8 +8758,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8812,12 +8812,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8881,8 +8881,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8935,12 +8935,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9004,8 +9004,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9058,12 +9058,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9836,12 +9836,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9876,15 +9876,15 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9900,10 +9900,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "mov w22, #0x0", @@ -9966,10 +9966,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1352]", + "ldr x3, [x28, #1224]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9995,11 +9995,11 @@ "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10038,10 +10038,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10102,10 +10102,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10131,11 +10131,11 @@ "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10152,10 +10152,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -10173,11 +10173,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10894,13 +10894,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x37f", - "strh w21, [x28, #1152]", + "strh w21, [x28, #1024]", "strb w20, [x28, #747]", "strb w20, [x28, #744]", "strb w20, [x28, #745]", "strb w20, [x28, #746]", "strb w20, [x28, #750]", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "fucomi st0, st0": { @@ -10940,12 +10940,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11017,12 +11017,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11094,12 +11094,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11171,12 +11171,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11248,12 +11248,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11325,12 +11325,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11402,12 +11402,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11479,12 +11479,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11556,12 +11556,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11633,12 +11633,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11710,12 +11710,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11787,12 +11787,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11864,12 +11864,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11941,12 +11941,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12018,12 +12018,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12095,12 +12095,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12168,8 +12168,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12222,12 +12222,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12291,8 +12291,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12345,12 +12345,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12414,8 +12414,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12468,12 +12468,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12543,8 +12543,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12597,12 +12597,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12637,11 +12637,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -12680,8 +12680,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12734,12 +12734,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12803,8 +12803,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12857,12 +12857,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12926,8 +12926,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12980,12 +12980,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13049,8 +13049,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13103,12 +13103,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13178,12 +13178,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13251,12 +13251,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13324,12 +13324,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13397,12 +13397,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13470,12 +13470,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13543,12 +13543,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13616,12 +13616,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13689,12 +13689,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13764,12 +13764,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13837,12 +13837,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13910,12 +13910,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13983,12 +13983,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14056,12 +14056,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14129,12 +14129,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14202,12 +14202,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14275,12 +14275,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14350,12 +14350,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14423,12 +14423,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14496,12 +14496,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14569,12 +14569,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14642,12 +14642,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14715,12 +14715,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14788,12 +14788,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14861,12 +14861,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14936,12 +14936,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15009,12 +15009,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15082,12 +15082,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15155,12 +15155,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15228,12 +15228,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15301,12 +15301,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15374,12 +15374,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15447,12 +15447,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15522,12 +15522,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15595,12 +15595,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15668,12 +15668,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15741,12 +15741,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15814,12 +15814,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15887,12 +15887,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15960,12 +15960,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16033,12 +16033,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16108,12 +16108,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16181,12 +16181,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16254,12 +16254,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16327,12 +16327,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16400,12 +16400,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16473,12 +16473,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16546,12 +16546,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16619,12 +16619,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16688,8 +16688,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16719,10 +16719,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -16761,10 +16761,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1360]", + "ldr x3, [x28, #1232]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16790,11 +16790,11 @@ "ldr x27, [x28, #760]", "mov x21, x0", "str x21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16833,10 +16833,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16897,10 +16897,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16926,11 +16926,11 @@ "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "str d2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16943,7 +16943,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -16988,7 +16988,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -17058,7 +17058,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1152]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -17072,7 +17072,7 @@ "orr x22, x22, x25, lsl #10", "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", @@ -17168,13 +17168,13 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -17207,11 +17207,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -17224,10 +17224,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -17239,11 +17239,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -17255,11 +17255,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -17271,11 +17271,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -17287,11 +17287,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -17303,11 +17303,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -17319,11 +17319,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -17459,11 +17459,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17483,10 +17483,10 @@ "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", "str q2, [x0, #768]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17505,11 +17505,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17528,11 +17528,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17551,11 +17551,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17574,11 +17574,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17597,11 +17597,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17620,11 +17620,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17668,12 +17668,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17746,12 +17746,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17825,12 +17825,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17904,12 +17904,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17983,12 +17983,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18062,12 +18062,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18141,12 +18141,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18220,12 +18220,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18300,12 +18300,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18339,11 +18339,11 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18387,12 +18387,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18427,10 +18427,10 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18473,12 +18473,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18513,11 +18513,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18560,12 +18560,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18600,11 +18600,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18647,12 +18647,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18687,11 +18687,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18734,12 +18734,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18774,11 +18774,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18821,12 +18821,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18861,11 +18861,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18908,12 +18908,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18948,11 +18948,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18991,8 +18991,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19045,12 +19045,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19114,8 +19114,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19168,12 +19168,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19237,8 +19237,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19291,12 +19291,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19366,8 +19366,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19420,12 +19420,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19460,11 +19460,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -19503,8 +19503,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19557,12 +19557,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19626,8 +19626,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19680,12 +19680,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19749,8 +19749,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19803,12 +19803,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19872,8 +19872,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19926,12 +19926,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19999,12 +19999,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20031,11 +20031,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20081,12 +20081,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20113,10 +20113,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20161,12 +20161,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20193,11 +20193,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20242,12 +20242,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20274,11 +20274,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20323,12 +20323,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20355,11 +20355,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20404,12 +20404,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20436,11 +20436,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20485,12 +20485,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20517,11 +20517,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20566,12 +20566,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20598,11 +20598,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20647,12 +20647,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20679,11 +20679,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20729,12 +20729,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20761,10 +20761,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20809,12 +20809,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20841,11 +20841,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20890,12 +20890,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20922,11 +20922,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20971,12 +20971,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21003,11 +21003,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21052,12 +21052,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21084,11 +21084,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21133,12 +21133,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21165,11 +21165,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21214,12 +21214,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21246,11 +21246,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21296,12 +21296,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21336,15 +21336,15 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -21389,12 +21389,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21421,11 +21421,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21471,12 +21471,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21503,10 +21503,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21551,12 +21551,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21583,11 +21583,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21632,12 +21632,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21664,11 +21664,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21713,12 +21713,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21745,11 +21745,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21794,12 +21794,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21826,11 +21826,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21875,12 +21875,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21907,11 +21907,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21956,12 +21956,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21988,11 +21988,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22039,12 +22039,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22071,11 +22071,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22121,12 +22121,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22153,10 +22153,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22201,12 +22201,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22233,11 +22233,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22282,12 +22282,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22314,11 +22314,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22363,12 +22363,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22395,11 +22395,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22444,12 +22444,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22476,11 +22476,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22525,12 +22525,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22557,11 +22557,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22606,12 +22606,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22638,11 +22638,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22689,12 +22689,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22721,11 +22721,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22771,12 +22771,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22803,10 +22803,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22851,12 +22851,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22883,11 +22883,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22932,12 +22932,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22964,11 +22964,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23013,12 +23013,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23045,11 +23045,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23094,12 +23094,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23126,11 +23126,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23175,12 +23175,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23207,11 +23207,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23256,12 +23256,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23288,11 +23288,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23339,12 +23339,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23371,11 +23371,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23421,12 +23421,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23453,10 +23453,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23501,12 +23501,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23533,11 +23533,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23582,12 +23582,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23614,11 +23614,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23663,12 +23663,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23695,11 +23695,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23744,12 +23744,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23776,11 +23776,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23825,12 +23825,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23857,11 +23857,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23906,12 +23906,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23938,11 +23938,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23960,10 +23960,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "mov w22, #0x0", @@ -24026,10 +24026,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", + "ldr x3, [x28, #1216]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24055,11 +24055,11 @@ "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24098,10 +24098,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24162,10 +24162,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24191,11 +24191,11 @@ "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24211,10 +24211,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -24241,10 +24241,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1520]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24308,10 +24308,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1512]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24341,11 +24341,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24504,12 +24504,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24543,10 +24543,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24590,12 +24590,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24628,10 +24628,10 @@ "rmif x23, #63, #nzCv", "rmif x24, #62, #nZcv", "eor w26, w22, #0x1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24674,12 +24674,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24713,10 +24713,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24759,12 +24759,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24798,10 +24798,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24844,12 +24844,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24883,10 +24883,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24929,12 +24929,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24968,10 +24968,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25014,12 +25014,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25053,10 +25053,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25099,12 +25099,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25138,10 +25138,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25184,12 +25184,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25223,10 +25223,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25270,12 +25270,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25308,10 +25308,10 @@ "rmif x23, #63, #nzCv", "rmif x24, #62, #nZcv", "eor w26, w22, #0x1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25354,12 +25354,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25393,10 +25393,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25439,12 +25439,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25478,10 +25478,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25524,12 +25524,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25563,10 +25563,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25609,12 +25609,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25648,10 +25648,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25694,12 +25694,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25733,10 +25733,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -25779,12 +25779,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25818,10 +25818,10 @@ "rmif x23, #62, #nZcv", "mov w22, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 770663bd18..77cc349dc9 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -92,10 +92,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -677,10 +677,10 @@ "strb w24, [x28, #750]", "strb w21, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -710,10 +710,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -743,10 +743,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -776,10 +776,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -809,10 +809,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -842,10 +842,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -875,10 +875,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -908,10 +908,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -1505,10 +1505,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1538,11 +1538,11 @@ "ldr d2, [x0, #768]", "fcvt s2, d2", "str s2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -1563,7 +1563,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1608,7 +1608,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -1627,7 +1627,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -1636,7 +1636,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1652,7 +1652,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -1708,7 +1708,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -1726,10 +1726,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1749,10 +1749,10 @@ "ldr d2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1772,10 +1772,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1795,10 +1795,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1818,10 +1818,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1841,10 +1841,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1864,10 +1864,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1887,10 +1887,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -2117,7 +2117,7 @@ "mov x21, v2.d[0]", "lsr x21, x21, #63", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "mov w21, #0x1", "and w20, w20, #0x1", @@ -2141,10 +2141,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x3ff0000000000000", "fmov d2, x21", @@ -2162,10 +2162,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xa372", "movk x21, #0x979, lsl #16", @@ -2186,10 +2186,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x82fe", "movk x21, #0x652b, lsl #16", @@ -2210,10 +2210,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x2d18", "movk x21, #0x5444, lsl #16", @@ -2234,10 +2234,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ff", "movk x21, #0x509f, lsl #16", @@ -2258,10 +2258,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x39ef", "movk x21, #0xfefa, lsl #16", @@ -2282,10 +2282,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", @@ -2327,8 +2327,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1632]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1504]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2364,11 +2364,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -2402,8 +2402,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1640]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1512]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2442,10 +2442,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", @@ -2474,8 +2474,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1616]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1488]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2517,11 +2517,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -2555,8 +2555,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1624]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1496]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2595,10 +2595,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", @@ -2655,8 +2655,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1656]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1528]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2750,8 +2750,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1648]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1520]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2789,11 +2789,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -2830,8 +2830,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1640]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1512]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2884,10 +2884,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", @@ -2916,8 +2916,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1600]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2967,8 +2967,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1608]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3054,8 +3054,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1664]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1536]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3118,8 +3118,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1600]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3184,8 +3184,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1608]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3293,10 +3293,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4094,15 +4094,15 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4118,10 +4118,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "scvtf d2, w21", @@ -4140,11 +4140,11 @@ "ldr d2, [x0, #768]", "fcvtzs w21, d2", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4176,11 +4176,11 @@ "frinti d0, d2", "fcvtzs w21, d0", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4218,10 +4218,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4249,10 +4249,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -4292,8 +4292,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4323,11 +4323,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -5051,13 +5051,13 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1154]" + "strb w21, [x28, #1026]" ] }, "fucomi st0, st0": { @@ -5437,10 +5437,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6393,10 +6393,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -6413,11 +6413,11 @@ "ldr d2, [x0, #768]", "fcvtzs x21, d2", "str x21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6445,11 +6445,11 @@ "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", "str d2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6471,8 +6471,8 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -6517,7 +6517,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -6549,10 +6549,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6608,10 +6608,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6667,10 +6667,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6726,10 +6726,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6785,10 +6785,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6844,10 +6844,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6903,10 +6903,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6963,10 +6963,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7003,7 +7003,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1152]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -7017,7 +7017,7 @@ "orr x22, x22, x25, lsl #10", "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", @@ -7092,8 +7092,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7151,8 +7151,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7210,8 +7210,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7269,8 +7269,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7328,8 +7328,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7387,8 +7387,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7446,8 +7446,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7505,8 +7505,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7537,13 +7537,13 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -7576,11 +7576,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -7593,10 +7593,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -7608,11 +7608,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -7624,11 +7624,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -7640,11 +7640,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -7656,11 +7656,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -7672,11 +7672,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -7688,11 +7688,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -7828,11 +7828,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7852,10 +7852,10 @@ "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", "str q2, [x0, #768]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7874,11 +7874,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7897,11 +7897,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7920,11 +7920,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7943,11 +7943,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7966,11 +7966,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7989,11 +7989,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8223,10 +8223,10 @@ "strb w24, [x28, #750]", "strb w21, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8256,10 +8256,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8289,10 +8289,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8322,10 +8322,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8355,10 +8355,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8388,10 +8388,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8421,10 +8421,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8454,10 +8454,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8544,10 +8544,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8635,11 +8635,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8662,10 +8662,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8687,11 +8687,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8713,11 +8713,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8739,11 +8739,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8765,11 +8765,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8791,11 +8791,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8817,11 +8817,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8843,11 +8843,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8870,10 +8870,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8895,11 +8895,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8921,11 +8921,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8947,11 +8947,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8973,11 +8973,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8999,11 +8999,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9025,11 +9025,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9061,15 +9061,15 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9091,11 +9091,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9118,10 +9118,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9143,11 +9143,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9169,11 +9169,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9195,11 +9195,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9221,11 +9221,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9247,11 +9247,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9273,11 +9273,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9301,11 +9301,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9328,10 +9328,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9353,11 +9353,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9379,11 +9379,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9405,11 +9405,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9431,11 +9431,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9457,11 +9457,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9483,11 +9483,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9511,11 +9511,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9538,10 +9538,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9563,11 +9563,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9589,11 +9589,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9615,11 +9615,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9641,11 +9641,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9667,11 +9667,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9693,11 +9693,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9721,11 +9721,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9748,10 +9748,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9773,11 +9773,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9799,11 +9799,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9825,11 +9825,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9851,11 +9851,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9877,11 +9877,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9903,11 +9903,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9925,10 +9925,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "sxth x21, w21", @@ -9948,11 +9948,11 @@ "ldr d2, [x0, #768]", "fcvtzs x21, d2", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9984,11 +9984,11 @@ "frinti d0, d2", "fcvtzs x21, d0", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10004,10 +10004,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -10034,10 +10034,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1520]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10088,10 +10088,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10154,8 +10154,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10206,10 +10206,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1512]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10239,11 +10239,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10383,10 +10383,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10410,10 +10410,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10437,10 +10437,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10464,10 +10464,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10491,10 +10491,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10518,10 +10518,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10545,10 +10545,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10572,10 +10572,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10599,10 +10599,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10626,10 +10626,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10653,10 +10653,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10680,10 +10680,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10707,10 +10707,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10734,10 +10734,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10761,10 +10761,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10788,10 +10788,10 @@ "cset w26, vc", "axflag", "cfinv", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index fd48d8529d..ec9a319041 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -624,7 +624,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2096]", + "ldr q2, [x28, #1968]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index cc5cada2de..4b37479f68 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -315,7 +315,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2224]", + "ldr q2, [x28, #2096]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -325,7 +325,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2240]", + "ldr q2, [x28, #2112]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -344,7 +344,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2256]", + "ldr q2, [x28, #2128]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -364,7 +364,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2272]", + "ldr q2, [x28, #2144]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -383,7 +383,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2288]", + "ldr q2, [x28, #2160]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -393,7 +393,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2304]", + "ldr q2, [x28, #2176]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -462,7 +462,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1848]", + "ldr x0, [x28, #1720]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 546ed94366..575000327d 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2674,50 +2674,38 @@ "Comment": "0x8e" }, "mov es, ax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 6, "Comment": "0x8e", "ExpectedArm64ASM": [ "uxth w20, w4", "strh w20, [x28, #136]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #152]" ] }, "mov ss, ax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 6, "Comment": "0x8e", "ExpectedArm64ASM": [ "uxth w20, w4", "strh w20, [x28, #140]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #160]" ] }, "mov ds, ax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 6, "Comment": "0x8e", "ExpectedArm64ASM": [ "uxth w20, w4", "strh w20, [x28, #142]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #164]" ] }, diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 8cf91f239b..e3e66c46ec 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -3052,7 +3052,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2352]", + "ldr x3, [x28, #2224]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3063,7 +3063,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2368]", + "ldr x3, [x28, #2240]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3124,7 +3124,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2360]", + "ldr x3, [x28, #2232]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3137,7 +3137,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2376]", + "ldr x3, [x28, #2248]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 9905b09c5d..6f07b271dd 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -19,19 +19,15 @@ ] }, "pop es": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x07", "ExpectedArm64ASM": [ "ldr w20, [x8]", "add x8, x8, #0x4 (4)", "strh w20, [x28, #136]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #152]" ] }, @@ -52,19 +48,15 @@ ] }, "pop ss": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x17", "ExpectedArm64ASM": [ "ldr w20, [x8]", "add x8, x8, #0x4 (4)", "strh w20, [x28, #140]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #160]" ] }, @@ -77,19 +69,15 @@ ] }, "pop ds": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x1f", "ExpectedArm64ASM": [ "ldr w20, [x8]", "add x8, x8, #0x4 (4)", "strh w20, [x28, #142]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #164]" ] }, diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 2c13ad430c..31e3755c11 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -23,7 +23,7 @@ "Comment": "0x0f 0x0b", "ExpectedArm64ASM": [ "mov w20, #0x0", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "movups xmm0, xmm0": { @@ -646,7 +646,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2192]", + "ldr q3, [x28, #2064]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -657,7 +657,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2192]", + "ldr q3, [x28, #2064]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -1041,7 +1041,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x28, #784]", - "ldr x0, [x28, #1800]", + "ldr x0, [x28, #1672]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #768]" @@ -1052,7 +1052,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "ldr x0, [x28, #1800]", + "ldr x0, [x28, #1672]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #768]" @@ -1111,7 +1111,7 @@ "Comment": "0x0f 0x77", "ExpectedArm64ASM": [ "mov w20, #0x0", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "movd eax, mm0": { @@ -1297,19 +1297,15 @@ ] }, "pop fs": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xa1", "ExpectedArm64ASM": [ "ldr x20, [x8]", "add x8, x8, #0x8 (8)", "strh w20, [x28, #146]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #176]" ] }, @@ -1696,19 +1692,15 @@ ] }, "pop gs": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xa9", "ExpectedArm64ASM": [ "ldr x20, [x8]", "add x8, x8, #0x8 (8)", "strh w20, [x28, #144]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #168]" ] }, @@ -3386,7 +3378,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1824]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3395,7 +3387,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1824]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3407,7 +3399,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1824]", + "ldr x0, [x28, #1696]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index ada76b153d..c911bee932 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -1332,7 +1332,7 @@ "ExpectedInstructionCount": 58, "Comment": "GROUP15 0x0F 0xAE /0", "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1346,7 +1346,7 @@ "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", "strh w20, [x4, #2]", - "ldrb w20, [x28, #1154]", + "ldrb w20, [x28, #1026]", "strb w20, [x4, #4]", "ldr q2, [x28, #768]", "str q2, [x4, #32]", @@ -1411,7 +1411,7 @@ "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1424,7 +1424,7 @@ "strb w23, [x28, #746]", "strb w20, [x28, #750]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "ldr q2, [x4, #32]", "str q2, [x28, #768]", "ldr q2, [x4, #48]", @@ -1549,7 +1549,7 @@ "ubfx x22, x20, #0, #1", "cbnz x22, #+0x8", "b #+0x84", - "ldrh w22, [x28, #1152]", + "ldrh w22, [x28, #1024]", "strh w22, [x21]", "mov w22, #0x0", "ldrb w23, [x28, #747]", @@ -1563,7 +1563,7 @@ "orr x22, x22, x25, lsl #10", "orr x22, x22, x30, lsl #14", "strh w22, [x21, #2]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "strb w22, [x21, #4]", "ldr q2, [x28, #768]", "str q2, [x21, #32]", @@ -1634,7 +1634,7 @@ "cbnz x22, #+0x8", "b #+0x84", "ldrh w22, [x20]", - "strh w22, [x28, #1152]", + "strh w22, [x28, #1024]", "ldrh w22, [x20, #2]", "ubfx w23, w22, #11, #3", "strb w23, [x28, #747]", @@ -1647,7 +1647,7 @@ "strb w25, [x28, #746]", "strb w22, [x28, #750]", "ldrb w22, [x20, #4]", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "ldr q2, [x20, #32]", "str q2, [x28, #768]", "ldr q2, [x20, #48]", @@ -1667,13 +1667,13 @@ "b #+0x4c", "mov w22, #0x0", "mov w23, #0x37f", - "strh w23, [x28, #1152]", + "strh w23, [x28, #1024]", "strb w22, [x28, #747]", "strb w22, [x28, #744]", "strb w22, [x28, #745]", "strb w22, [x28, #746]", "strb w22, [x28, #750]", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "movi v2.2d, #0x0", "str q2, [x28, #768]", "str q2, [x28, #784]", diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index 7cbc2234b4..ebc5e692de 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -42,8 +42,8 @@ "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64", "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64", "mov w1, w5", - "ldr x0, [x28, #1240]", - "ldr x2, [x28, #1256]", + "ldr x0, [x28, #1112]", + "ldr x2, [x28, #1128]", "blr x2", "ldr w4, [x28, #728]", "msr nzcv, x4", @@ -85,7 +85,7 @@ "str w0, [x28, #728]", "str x8, [x28, #40]", "mov w0, #0x100", - "str x0, [x28, #1184]", + "str x0, [x28, #1056]", "sub sp, sp, #0x10 (16)", "mov w8, #0xa8", "mov x0, sp", @@ -96,7 +96,7 @@ "ldr w8, [x28, #728]", "msr nzcv, x8", "ldr x8, [x28, #40]", - "str xzr, [x28, #1184]", + "str xzr, [x28, #1056]", "orr x5, x0, x1, lsl #12" ] }, diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index 31cd7b51cc..28c6981829 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -17,19 +17,15 @@ ] }, "pop fs": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xa1", "ExpectedArm64ASM": [ "ldr w20, [x8]", "add x8, x8, #0x4 (4)", "strh w20, [x28, #146]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #176]" ] }, @@ -42,19 +38,15 @@ ] }, "pop gs": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xa9", "ExpectedArm64ASM": [ "ldr w20, [x8]", "add x8, x8, #0x4 (4)", "strh w20, [x28, #144]", "ubfx w20, w20, #3, #13", - "add x0, x28, x20, lsl #3", - "ldr x20, [x0, #896]", - "lsr x21, x20, #32", - "and w22, w21, #0xff000000", - "orr w20, w22, w20, lsr #16", - "bfi w20, w21, #16, #8", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #896]", "str w20, [x28, #168]" ] } diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 712ebcf50f..162204941e 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -522,7 +522,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1816]", + "ldr x0, [x28, #1688]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -536,7 +536,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1816]", + "ldr x0, [x28, #1688]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1014,7 +1014,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2160]", + "ldr q2, [x28, #2032]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 6a223b739c..a4fa5d02a7 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -354,7 +354,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1808]", + "ldr x0, [x28, #1680]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 147427e2f6..da29314b7d 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -296,7 +296,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1800]", + "ldr x0, [x28, #1672]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -452,7 +452,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2128]", + "ldr q2, [x28, #2000]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 652074f6e6..f8d057ec79 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -2755,7 +2755,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1824]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2824,7 +2824,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1824]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2893,7 +2893,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1824]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -4338,7 +4338,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2160]", + "ldr q2, [x28, #2032]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4349,7 +4349,7 @@ "Map 1 0b01 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1720]", + "ldr x0, [x28, #1592]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.d, z17.d, z2.d" @@ -4361,7 +4361,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2128]", + "ldr q2, [x28, #2000]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4372,7 +4372,7 @@ "Map 1 0b11 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1704]", + "ldr x0, [x28, #1576]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.s, z17.s, z2.s" diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 5bf2590f70..d0caa9970d 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1575,7 +1575,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2096]", + "ldr q2, [x28, #1968]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index e83ecbffaa..94612c74d9 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -4799,7 +4799,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2208]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -4812,7 +4812,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2208]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 245ba23545..5e4f88b6f0 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -45,8 +45,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -99,12 +99,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -168,8 +168,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -222,12 +222,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -291,8 +291,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -345,12 +345,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -420,8 +420,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -474,12 +474,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -514,11 +514,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -557,8 +557,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -611,12 +611,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -680,8 +680,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -734,12 +734,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -803,8 +803,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -857,12 +857,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -926,8 +926,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -980,12 +980,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1053,12 +1053,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1126,12 +1126,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1199,12 +1199,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1272,12 +1272,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1345,12 +1345,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1418,12 +1418,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1491,12 +1491,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1564,12 +1564,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1637,12 +1637,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1710,12 +1710,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1783,12 +1783,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1856,12 +1856,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1929,12 +1929,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2002,12 +2002,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2075,12 +2075,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2148,12 +2148,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2222,12 +2222,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2300,12 +2300,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2379,12 +2379,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2458,12 +2458,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2537,12 +2537,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2616,12 +2616,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2695,12 +2695,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2774,12 +2774,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2854,12 +2854,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2893,11 +2893,11 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -2941,12 +2941,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2981,10 +2981,10 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3027,12 +3027,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3067,11 +3067,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3114,12 +3114,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3154,11 +3154,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3201,12 +3201,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3241,11 +3241,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3288,12 +3288,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3328,11 +3328,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3375,12 +3375,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3415,11 +3415,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3462,12 +3462,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3502,11 +3502,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -3549,12 +3549,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3622,12 +3622,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3695,12 +3695,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3768,12 +3768,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3841,12 +3841,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3914,12 +3914,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3987,12 +3987,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4060,12 +4060,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4133,12 +4133,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4206,12 +4206,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4279,12 +4279,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4352,12 +4352,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4425,12 +4425,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4498,12 +4498,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4571,12 +4571,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4644,12 +4644,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4717,12 +4717,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4790,12 +4790,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4863,12 +4863,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4936,12 +4936,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5009,12 +5009,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5082,12 +5082,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5155,12 +5155,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5228,12 +5228,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5301,12 +5301,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5374,12 +5374,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5447,12 +5447,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5520,12 +5520,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5593,12 +5593,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5666,12 +5666,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5739,12 +5739,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5812,12 +5812,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5881,8 +5881,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1288]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5912,10 +5912,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -5954,10 +5954,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1304]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6018,10 +6018,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1304]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6047,11 +6047,11 @@ "ldr x27, [x28, #760]", "fmov s2, s0", "str s2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6064,7 +6064,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -6109,7 +6109,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -6120,7 +6120,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -6129,7 +6129,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -6145,7 +6145,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -6201,7 +6201,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -6219,10 +6219,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6242,10 +6242,10 @@ "ldr q2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6265,10 +6265,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6288,10 +6288,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6311,10 +6311,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6334,10 +6334,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6357,10 +6357,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6380,10 +6380,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -6619,12 +6619,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6672,7 +6672,7 @@ "mov x21, v2.d[1]", "ubfx x21, x21, #15, #1", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", @@ -6694,10 +6694,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8000000000000000", "mov w22, #0x3fff", @@ -6717,10 +6717,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8afe", "movk x21, #0xcd1b, lsl #16", @@ -6743,10 +6743,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf0bc", "movk x21, #0x5c17, lsl #16", @@ -6769,10 +6769,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xc235", "movk x21, #0x2168, lsl #16", @@ -6795,10 +6795,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf799", "movk x21, #0xfbcf, lsl #16", @@ -6821,10 +6821,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ac", "movk x21, #0xd1cf, lsl #16", @@ -6847,10 +6847,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", @@ -6892,10 +6892,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1456]", + "ldr x3, [x28, #1328]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6933,11 +6933,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -6969,12 +6969,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1560]", + "ldr x5, [x28, #1432]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7015,10 +7015,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #768]", @@ -7046,10 +7046,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1464]", + "ldr x3, [x28, #1336]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7095,11 +7095,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -7131,12 +7131,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1568]", + "ldr x5, [x28, #1440]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7177,10 +7177,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #768]", @@ -7208,10 +7208,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1496]", + "ldr x3, [x28, #1368]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7262,10 +7262,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1504]", + "ldr x3, [x28, #1376]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7335,12 +7335,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1576]", + "ldr x5, [x28, #1448]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7434,12 +7434,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1584]", + "ldr x5, [x28, #1456]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7479,11 +7479,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -7519,12 +7519,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v4.d[0]", "umov w4, v4.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7575,12 +7575,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1560]", + "ldr x5, [x28, #1432]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7644,10 +7644,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1472]", + "ldr x3, [x28, #1344]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7688,10 +7688,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #768]", @@ -7719,10 +7719,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1480]", + "ldr x3, [x28, #1352]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7773,10 +7773,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1488]", + "ldr x3, [x28, #1360]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7844,10 +7844,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1448]", + "ldr x3, [x28, #1320]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7915,12 +7915,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1592]", + "ldr x5, [x28, #1464]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7984,10 +7984,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1480]", + "ldr x3, [x28, #1352]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8053,10 +8053,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1488]", + "ldr x3, [x28, #1360]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8122,8 +8122,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8176,12 +8176,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8245,8 +8245,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8299,12 +8299,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8368,8 +8368,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8422,12 +8422,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8497,8 +8497,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8551,12 +8551,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8591,11 +8591,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8634,8 +8634,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8688,12 +8688,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8757,8 +8757,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8811,12 +8811,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8880,8 +8880,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8934,12 +8934,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9003,8 +9003,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1440]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9057,12 +9057,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9835,12 +9835,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9875,15 +9875,15 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9899,10 +9899,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "mov w22, #0x0", @@ -9965,10 +9965,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1352]", + "ldr x3, [x28, #1224]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9994,11 +9994,11 @@ "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10037,10 +10037,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10101,10 +10101,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10130,11 +10130,11 @@ "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10151,10 +10151,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -10172,11 +10172,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10893,13 +10893,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x37f", - "strh w21, [x28, #1152]", + "strh w21, [x28, #1024]", "strb w20, [x28, #747]", "strb w20, [x28, #744]", "strb w20, [x28, #745]", "strb w20, [x28, #746]", "strb w20, [x28, #750]", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "fucomi st0, st0": { @@ -10939,12 +10939,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11017,12 +11017,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11095,12 +11095,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11173,12 +11173,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11251,12 +11251,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11329,12 +11329,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11407,12 +11407,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11485,12 +11485,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11563,12 +11563,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11641,12 +11641,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11719,12 +11719,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11797,12 +11797,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11875,12 +11875,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11953,12 +11953,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12031,12 +12031,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12109,12 +12109,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12183,8 +12183,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12237,12 +12237,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12306,8 +12306,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12360,12 +12360,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12429,8 +12429,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12483,12 +12483,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12558,8 +12558,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12612,12 +12612,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12652,11 +12652,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -12695,8 +12695,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12749,12 +12749,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12818,8 +12818,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12872,12 +12872,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12941,8 +12941,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12995,12 +12995,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13064,8 +13064,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13118,12 +13118,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13193,12 +13193,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13266,12 +13266,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13339,12 +13339,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13412,12 +13412,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13485,12 +13485,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13558,12 +13558,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13631,12 +13631,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13704,12 +13704,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13779,12 +13779,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13852,12 +13852,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13925,12 +13925,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13998,12 +13998,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14071,12 +14071,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14144,12 +14144,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14217,12 +14217,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14290,12 +14290,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14365,12 +14365,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14438,12 +14438,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14511,12 +14511,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14584,12 +14584,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14657,12 +14657,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14730,12 +14730,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14803,12 +14803,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14876,12 +14876,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14951,12 +14951,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15024,12 +15024,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15097,12 +15097,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15170,12 +15170,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15243,12 +15243,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15316,12 +15316,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15389,12 +15389,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15462,12 +15462,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15537,12 +15537,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15610,12 +15610,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15683,12 +15683,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15756,12 +15756,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15829,12 +15829,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15902,12 +15902,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15975,12 +15975,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16048,12 +16048,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16123,12 +16123,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16196,12 +16196,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16269,12 +16269,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16342,12 +16342,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16415,12 +16415,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16488,12 +16488,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16561,12 +16561,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16634,12 +16634,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16703,8 +16703,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16734,10 +16734,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]" @@ -16776,10 +16776,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1360]", + "ldr x3, [x28, #1232]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16805,11 +16805,11 @@ "ldr x27, [x28, #760]", "mov x21, x0", "str x21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16848,10 +16848,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16912,10 +16912,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16941,11 +16941,11 @@ "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "str d2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16958,7 +16958,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -17003,7 +17003,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -17073,7 +17073,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1152]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -17087,7 +17087,7 @@ "orr x22, x22, x25, lsl #10", "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", @@ -17183,13 +17183,13 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -17222,11 +17222,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -17239,10 +17239,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -17254,11 +17254,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -17270,11 +17270,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -17286,11 +17286,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -17302,11 +17302,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -17318,11 +17318,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -17334,11 +17334,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -17474,11 +17474,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17498,10 +17498,10 @@ "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", "str q2, [x0, #768]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17520,11 +17520,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17543,11 +17543,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17566,11 +17566,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17589,11 +17589,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17612,11 +17612,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17635,11 +17635,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -17683,12 +17683,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17761,12 +17761,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17840,12 +17840,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17919,12 +17919,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17998,12 +17998,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18077,12 +18077,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18156,12 +18156,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18235,12 +18235,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18315,12 +18315,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18354,11 +18354,11 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18402,12 +18402,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18442,10 +18442,10 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18488,12 +18488,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18528,11 +18528,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18575,12 +18575,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18615,11 +18615,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18662,12 +18662,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18702,11 +18702,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18749,12 +18749,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18789,11 +18789,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18836,12 +18836,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18876,11 +18876,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -18923,12 +18923,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18963,11 +18963,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -19006,8 +19006,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19060,12 +19060,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19129,8 +19129,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19183,12 +19183,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19252,8 +19252,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19306,12 +19306,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19381,8 +19381,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19435,12 +19435,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19475,11 +19475,11 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -19518,8 +19518,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19572,12 +19572,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19641,8 +19641,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19695,12 +19695,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19764,8 +19764,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19818,12 +19818,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19887,8 +19887,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "sxth w1, w21", - "ldrh w0, [x28, #1152]", - "ldr x2, [x28, #1432]", + "ldrh w0, [x28, #1024]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19941,12 +19941,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20014,12 +20014,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20046,11 +20046,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20096,12 +20096,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20128,10 +20128,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20176,12 +20176,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20208,11 +20208,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20257,12 +20257,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20289,11 +20289,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20338,12 +20338,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20370,11 +20370,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20419,12 +20419,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20451,11 +20451,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20500,12 +20500,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20532,11 +20532,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20581,12 +20581,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1528]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20613,11 +20613,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20662,12 +20662,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20694,11 +20694,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20744,12 +20744,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20776,10 +20776,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20824,12 +20824,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20856,11 +20856,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20905,12 +20905,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20937,11 +20937,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -20986,12 +20986,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21018,11 +21018,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21067,12 +21067,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21099,11 +21099,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21148,12 +21148,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21180,11 +21180,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21229,12 +21229,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1544]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21261,11 +21261,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21311,12 +21311,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21351,15 +21351,15 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -21404,12 +21404,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21436,11 +21436,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21486,12 +21486,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21518,10 +21518,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21566,12 +21566,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21598,11 +21598,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21647,12 +21647,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21679,11 +21679,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21728,12 +21728,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21760,11 +21760,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21809,12 +21809,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21841,11 +21841,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21890,12 +21890,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21922,11 +21922,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -21971,12 +21971,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22003,11 +22003,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22054,12 +22054,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22086,11 +22086,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22136,12 +22136,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22168,10 +22168,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22216,12 +22216,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22248,11 +22248,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22297,12 +22297,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22329,11 +22329,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22378,12 +22378,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22410,11 +22410,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22459,12 +22459,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22491,11 +22491,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22540,12 +22540,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22572,11 +22572,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22621,12 +22621,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1536]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22653,11 +22653,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22704,12 +22704,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22736,11 +22736,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22786,12 +22786,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22818,10 +22818,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22866,12 +22866,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22898,11 +22898,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -22947,12 +22947,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22979,11 +22979,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23028,12 +23028,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23060,11 +23060,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23109,12 +23109,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23141,11 +23141,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23190,12 +23190,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23222,11 +23222,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23271,12 +23271,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23303,11 +23303,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23354,12 +23354,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23386,11 +23386,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23436,12 +23436,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23468,10 +23468,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23516,12 +23516,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23548,11 +23548,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23597,12 +23597,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23629,11 +23629,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23678,12 +23678,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23710,11 +23710,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23759,12 +23759,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23791,11 +23791,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23840,12 +23840,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23872,11 +23872,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23921,12 +23921,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1552]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23953,11 +23953,11 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23975,10 +23975,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "mov w22, #0x0", @@ -24041,10 +24041,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", + "ldr x3, [x28, #1216]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24070,11 +24070,11 @@ "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24113,10 +24113,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24177,10 +24177,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24206,11 +24206,11 @@ "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24226,10 +24226,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -24256,10 +24256,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1520]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24323,10 +24323,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1512]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24356,11 +24356,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -24519,12 +24519,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24558,10 +24558,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24606,12 +24606,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24644,10 +24644,10 @@ "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", "eor w26, w22, #0x1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24691,12 +24691,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24730,10 +24730,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24777,12 +24777,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24816,10 +24816,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24863,12 +24863,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24902,10 +24902,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24949,12 +24949,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24988,10 +24988,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25035,12 +25035,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25074,10 +25074,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25121,12 +25121,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25160,10 +25160,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25207,12 +25207,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25246,10 +25246,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25294,12 +25294,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25332,10 +25332,10 @@ "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", "eor w26, w22, #0x1", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25379,12 +25379,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25418,10 +25418,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25465,12 +25465,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25504,10 +25504,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25551,12 +25551,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25590,10 +25590,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25637,12 +25637,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25676,10 +25676,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25723,12 +25723,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25762,10 +25762,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -25809,12 +25809,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -25848,10 +25848,10 @@ "orr w22, w22, w23, lsl #30", "mov w23, #0x1", "eor w26, w21, #0x1", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 91758fdc2b..3b11084fb9 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -93,10 +93,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -687,10 +687,10 @@ "strb w24, [x28, #750]", "strb w21, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -721,10 +721,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -755,10 +755,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -789,10 +789,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -823,10 +823,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -857,10 +857,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -891,10 +891,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -925,10 +925,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -1522,10 +1522,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1555,11 +1555,11 @@ "ldr d2, [x0, #768]", "fcvt s2, d2", "str s2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -1580,7 +1580,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1625,7 +1625,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -1644,7 +1644,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -1653,7 +1653,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1669,7 +1669,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -1725,7 +1725,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1152]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -1743,10 +1743,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1766,10 +1766,10 @@ "ldr d2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1789,10 +1789,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1812,10 +1812,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1835,10 +1835,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1858,10 +1858,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1881,10 +1881,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -1904,10 +1904,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -2135,7 +2135,7 @@ "mov x21, v2.d[0]", "lsr x21, x21, #63", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "mov w21, #0x1", "and w20, w20, #0x1", @@ -2159,10 +2159,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x3ff0000000000000", "fmov d2, x21", @@ -2180,10 +2180,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xa372", "movk x21, #0x979, lsl #16", @@ -2204,10 +2204,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x82fe", "movk x21, #0x652b, lsl #16", @@ -2228,10 +2228,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x2d18", "movk x21, #0x5444, lsl #16", @@ -2252,10 +2252,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ff", "movk x21, #0x509f, lsl #16", @@ -2276,10 +2276,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x39ef", "movk x21, #0xfefa, lsl #16", @@ -2300,10 +2300,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", @@ -2345,8 +2345,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1632]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1504]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2382,11 +2382,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -2420,8 +2420,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1640]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1512]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2460,10 +2460,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", @@ -2492,8 +2492,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1616]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1488]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2535,11 +2535,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -2573,8 +2573,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1624]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1496]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2613,10 +2613,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", @@ -2673,8 +2673,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1656]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1528]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2768,8 +2768,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1648]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1520]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2807,11 +2807,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", @@ -2848,8 +2848,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1640]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1512]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2902,10 +2902,10 @@ "mov w21, #0x1", "sub w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w22, [x28, #747]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", @@ -2934,8 +2934,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1600]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2985,8 +2985,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1608]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3072,8 +3072,8 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1664]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1536]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3136,8 +3136,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1600]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3202,8 +3202,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1608]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3313,10 +3313,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4115,15 +4115,15 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4139,10 +4139,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "scvtf d2, w21", @@ -4161,11 +4161,11 @@ "ldr d2, [x0, #768]", "fcvtzs w21, d2", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4197,11 +4197,11 @@ "frinti d0, d2", "fcvtzs w21, d0", "str w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4239,10 +4239,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4270,10 +4270,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -4313,8 +4313,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4344,11 +4344,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -5072,13 +5072,13 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1154]" + "strb w21, [x28, #1026]" ] }, "fucomi st0, st0": { @@ -5556,10 +5556,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6512,10 +6512,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", "str d2, [x0, #768]" @@ -6532,11 +6532,11 @@ "ldr d2, [x0, #768]", "fcvtzs x21, d2", "str x21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6564,11 +6564,11 @@ "add x0, x28, x20, lsl #4", "ldr d2, [x0, #768]", "str d2, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6590,8 +6590,8 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1152]", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -6636,7 +6636,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1154]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -6668,10 +6668,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6727,10 +6727,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6786,10 +6786,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6845,10 +6845,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6904,10 +6904,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6963,10 +6963,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7022,10 +7022,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7082,10 +7082,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7122,7 +7122,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1152]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -7136,7 +7136,7 @@ "orr x22, x22, x25, lsl #10", "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", @@ -7211,8 +7211,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7270,8 +7270,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7329,8 +7329,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7388,8 +7388,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7447,8 +7447,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7506,8 +7506,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7565,8 +7565,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7624,8 +7624,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7656,13 +7656,13 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1152]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -7695,11 +7695,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -7712,10 +7712,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -7727,11 +7727,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -7743,11 +7743,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -7759,11 +7759,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -7775,11 +7775,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -7791,11 +7791,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -7807,11 +7807,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1154]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -7947,11 +7947,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7971,10 +7971,10 @@ "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", "str q2, [x0, #768]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -7993,11 +7993,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8016,11 +8016,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8039,11 +8039,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8062,11 +8062,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8085,11 +8085,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8108,11 +8108,11 @@ "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", "str q2, [x0, #768]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8351,10 +8351,10 @@ "strb w24, [x28, #750]", "strb w21, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8385,10 +8385,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8419,10 +8419,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8453,10 +8453,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8487,10 +8487,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8521,10 +8521,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8555,10 +8555,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8589,10 +8589,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8681,10 +8681,10 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8772,11 +8772,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8799,10 +8799,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8824,11 +8824,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8850,11 +8850,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8876,11 +8876,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8902,11 +8902,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8928,11 +8928,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8954,11 +8954,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8980,11 +8980,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9007,10 +9007,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9032,11 +9032,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9058,11 +9058,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9084,11 +9084,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9110,11 +9110,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9136,11 +9136,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9162,11 +9162,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9199,15 +9199,15 @@ "strb w24, [x28, #750]", "strb w22, [x28, #745]", "strb w23, [x28, #746]", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9229,11 +9229,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9256,10 +9256,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9281,11 +9281,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9307,11 +9307,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9333,11 +9333,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9359,11 +9359,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9385,11 +9385,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9411,11 +9411,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9439,11 +9439,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9466,10 +9466,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9491,11 +9491,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9517,11 +9517,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9543,11 +9543,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9569,11 +9569,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9595,11 +9595,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9621,11 +9621,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9649,11 +9649,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9676,10 +9676,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9701,11 +9701,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9727,11 +9727,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9753,11 +9753,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9779,11 +9779,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9805,11 +9805,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9831,11 +9831,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9859,11 +9859,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9886,10 +9886,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9911,11 +9911,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9937,11 +9937,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9963,11 +9963,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9989,11 +9989,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10015,11 +10015,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10041,11 +10041,11 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1154]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10063,10 +10063,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "sxth x21, w21", @@ -10086,11 +10086,11 @@ "ldr d2, [x0, #768]", "fcvtzs x21, d2", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10122,11 +10122,11 @@ "frinti d0, d2", "fcvtzs x21, d0", "strh w21, [x4]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10142,10 +10142,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1154]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -10172,10 +10172,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1520]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10226,10 +10226,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10292,8 +10292,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1152]", - "ldr x1, [x28, #1296]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10344,10 +10344,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1152]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1512]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10377,11 +10377,11 @@ "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1154]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10526,10 +10526,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10559,10 +10559,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10592,10 +10592,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10625,10 +10625,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10658,10 +10658,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10691,10 +10691,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10724,10 +10724,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10757,10 +10757,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10790,10 +10790,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10823,10 +10823,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10856,10 +10856,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10889,10 +10889,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10922,10 +10922,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10955,10 +10955,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10988,10 +10988,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11021,10 +11021,10 @@ "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", "eor w26, w24, #0x1", - "ldrb w23, [x28, #1154]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1154]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]",