verible.filelist

verilog\eko.srcs\design\gcc_phat\gcc_phat_core.v
verilog\eko.srcs\design\gcc_phat\magnitude_0.v
verilog\eko.srcs\design\gcc_phat\multiply_0.v
verilog\eko.srcs\design\gcc_phat\normalize_0.v
verilog\eko.srcs\design\gcc_phat\scale_0.v
verilog\eko.srcs\design\gcc_phat\shift_0.v
verilog\eko.srcs\design\i2s\i2s_recv_3pairs.v
verilog\eko.srcs\design\i2s\i2s_recv.v
verilog\eko.srcs\design\top\top_basic.v
verilog\eko.srcs\design\upstream\upstream_hub.v
verilog\eko.srcs\design\upstream\vad_upstream_hub.v
verilog\eko.srcs\ips\clk_wiz_0\clk_wiz_0_clk_wiz.v
verilog\eko.srcs\ips\clk_wiz_0\clk_wiz_0_sim_netlist.v
verilog\eko.srcs\ips\clk_wiz_0\clk_wiz_0.v
verilog\eko.srcs\ips\cordic_0\cordic_0_sim_netlist.v
verilog\eko.srcs\ips\cordic_1\cordic_1_sim_netlist.v
verilog\eko.srcs\ips\cordic_2\cordic_2_sim_netlist.v
verilog\eko.srcs\ips\ila_i2s_0\hdl\ila_v6_2_syn_rfs.v
verilog\eko.srcs\ips\ila_i2s_0\hdl\ltlib_v1_0_vl_rfs.v
verilog\eko.srcs\ips\ila_i2s_0\hdl\xsdbm_v3_0_vl_rfs.v
verilog\eko.srcs\ips\ila_i2s_0\hdl\xsdbs_v1_0_vl_rfs.v
verilog\eko.srcs\ips\ila_i2s_0\ila_i2s_0_sim_netlist.v
verilog\eko.srcs\ips\ila_i2s_0\sim\ila_i2s_0.v
verilog\eko.srcs\ips\ila_i2s_0\synth\ila_i2s_0.v
verilog\eko.srcs\ips\slice_0\hdl\axis_infrastructure_v1_1_vl_rfs.v
verilog\eko.srcs\ips\slice_0\hdl\axis_register_slice_v1_1_vl_rfs.v
verilog\eko.srcs\ips\slice_0\sim\slice_0.v
verilog\eko.srcs\ips\slice_0\slice_0_sim_netlist.v
verilog\eko.srcs\ips\slice_0\synth\slice_0.v
verilog\eko.srcs\ips\upstream_bram_0\sim\upstream_bram_0.v
verilog\eko.srcs\ips\upstream_bram_0\simulation\blk_mem_gen_v8_4.v
verilog\eko.srcs\ips\upstream_bram_0\upstream_bram_0_sim_netlist.v
verilog\eko.srcs\ips\xfft_0\xfft_0_sim_netlist.v
verilog\eko.srcs\ips\xfft_1\xfft_1_sim_netlist.v
verilog\eko.srcs\testbench\tb_gcc_phat_core.v
verilog\eko.srcs\testbench\tb_i2s_recv.v
verilog\eko.srcs\testbench\tb_magnitude_0.v
verilog\eko.srcs\testbench\tb_multiply_0.v
verilog\eko.srcs\testbench\tb_normalize_0.v
verilog\eko.srcs\testbench\tb_scale_0.v
verilog\eko.srcs\testbench\tb_shift_0.v
verilog\eko.srcs\testbench\tb_upstream_hub.v
verilog\eko.srcs\testbench\tb_vad_upstream_hub.v
verilog\eko.srcs\testbench\tb_xfft_0.v