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Increase TLB size to 64 CI #117: Commit be3f3b1 pushed by Timmmm
July 4, 2024 15:30 24m 9s user/timh/bigger_tlb_2
user/timh/bigger_tlb_2
July 4, 2024 15:30 24m 9s
Remove redundant CSR privilege checks CI #116: Commit f5b67c6 pushed by Timmmm
July 4, 2024 15:25 24m 8s user/timh/redundant_access_checks
user/timh/redundant_access_checks
July 4, 2024 15:25 24m 8s
Fix TLB bug CI #115: Commit 76282a9 pushed by Timmmm
July 4, 2024 15:25 23m 39s user/timh/tlb_fix
user/timh/tlb_fix
July 4, 2024 15:25 23m 39s
Use physical addresses for LR/SC reservations CI #114: Commit 085b37a pushed by Timmmm
July 4, 2024 15:24 23m 19s user/timh/physical_reservation_address
user/timh/physical_reservation_address
July 4, 2024 15:24 23m 19s
Use bool <-> bit mappings from riscv_types.sail CI #113: Commit dcf8d01 pushed by Timmmm
July 4, 2024 15:24 23m 20s user/timh/bool_mappings
user/timh/bool_mappings
July 4, 2024 15:24 23m 20s
Add support for HPM counters CI #112: Commit a880990 pushed by Timmmm
July 4, 2024 15:24 23m 25s user/timh/hpmcounters
user/timh/hpmcounters
July 4, 2024 15:24 23m 25s
Implement Zicbom, Zicboz (cbo.flush, cbo.inval, cbo.zero) CI #111: Commit c1f1520 pushed by Timmmm
July 4, 2024 15:23 23m 12s user/timh/cbo
user/timh/cbo
July 4, 2024 15:23 23m 12s
Publish test results Publish test results #110: completed by Timmmm
June 19, 2024 11:16 13s
June 19, 2024 11:16 13s
Use physical addresses for LR/SC reservations CI #110: Commit 11e63e7 pushed by Timmmm
June 19, 2024 10:52 23m 41s user/timh/physical_reservation_address
user/timh/physical_reservation_address
June 19, 2024 10:52 23m 41s
Publish test results Publish test results #109: completed by Timmmm
June 18, 2024 17:25 14s
June 18, 2024 17:25 14s
Fix consecutive builds of the OCaml emulator CI #109: Commit 634d2c5 pushed by Timmmm
June 18, 2024 17:01 23m 16s user/timh/sail_file_permissions
user/timh/sail_file_permissions
June 18, 2024 17:01 23m 16s
Publish test results Publish test results #108: completed by Timmmm
June 18, 2024 16:07 18s
June 18, 2024 16:07 18s
Publish test results Publish test results #107: completed by Timmmm
June 18, 2024 16:06 17s
June 18, 2024 16:06 17s
Publish test results Publish test results #106: completed by Timmmm
June 18, 2024 16:05 13s
June 18, 2024 16:05 13s
Publish test results Publish test results #105: completed by Timmmm
June 18, 2024 16:02 23s
June 18, 2024 16:02 23s
Increase TLB size to 64 CI #108: Commit 3f5b7f4 pushed by Timmmm
June 18, 2024 15:43 23m 30s user/timh/bigger_tlb_2
user/timh/bigger_tlb_2
June 18, 2024 15:43 23m 30s
Increase TLB size to 64 CI #107: Commit 51970a6 pushed by Timmmm
June 18, 2024 15:42 24m 38s user/timh/bigger_tlb_2
user/timh/bigger_tlb_2
June 18, 2024 15:42 24m 38s
Remove redundant CSR privilege checks CI #106: Commit 50b6448 pushed by Timmmm
June 18, 2024 15:41 24m 13s user/timh/redundant_access_checks
user/timh/redundant_access_checks
June 18, 2024 15:41 24m 13s
Fix TLB bug CI #105: Commit ff1515d pushed by Timmmm
June 18, 2024 15:38 23m 46s user/timh/tlb_fix
user/timh/tlb_fix
June 18, 2024 15:38 23m 46s
Publish test results Publish test results #104: completed by Timmmm
June 14, 2024 14:32 13s
June 14, 2024 14:32 13s
Implement Zicbom, Zicboz (cbo.flush, cbo.inval, cbo.zero) CI #104: Commit 3dfd09f pushed by Timmmm
June 14, 2024 14:08 23m 50s user/timh/cbo
user/timh/cbo
June 14, 2024 14:08 23m 50s
Publish test results Publish test results #103: completed by Timmmm
June 12, 2024 10:42 21s
June 12, 2024 10:42 21s
Use bool <-> bit mappings from riscv_types.sail CI #103: Commit 25e7827 pushed by Timmmm
June 12, 2024 10:19 23m 7s user/timh/bool_mappings
user/timh/bool_mappings
June 12, 2024 10:19 23m 7s
Publish test results Publish test results #102: completed by Timmmm
June 11, 2024 21:22 17s
June 11, 2024 21:22 17s
Publish test results Publish test results #101: completed by Timmmm
June 11, 2024 21:19 13s
June 11, 2024 21:19 13s