How can I get Verilog/VHDL files of the converted model using FINN compiler?

[jaafar87]

Hello, I went through the tutorials and I was able to run the network examples using Jupyter. I would like to know how can I get the Verilog/VHDL files of the compiled network from finn compilation flow.
Second question, how can I run simulation through finn flow?
Third question, in case I want to add custom logic along with the network, how can I generate the bitstream? please note that the custom logic will not impact the network itself, it will manipulate the input image before loading the image to the network.

Thank you very much in advance for your help and looking forward for your reply.

[maltanar]

Hi @jaafar87 , the vast majority of the hardware generated by FINN is built with Vivado High-Level Synthesis (HLS) so in many cases, HLS is responsible for translating the C++ descriptions from finn-hlslib into Verilog/VHDL. If you look under the temporary build folder (by default under /tmp/finn_dev_<username>) after running HLS IP generation with FINN, you'll notice many folders with names like code_gen_ipgen_<layername>_xxx. If you navigate into these folders, you can find the generated HDL under a path that looks something like code_gen_ipgen_Lookup_0_52_qf7c3/project_Lookup_0/sol1/syn/verilog. Alternatively, after the IP stitching stage, you can find a vivado_stitch_proj_xxx under the temporary build folder, under that you'll see a all_verilog_srcs.txt that points to all the Verilog files used by all the layers in the design.

For verification examples, please have a look at this notebook: https://github.com/Xilinx/finn/blob/dev/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb -- alternatively, if you are using the new build_dataflow system without any custom steps, you can specify the verify_* options: https://finn.readthedocs.io/en/latest/source_code/finn.builder.html#finn.builder.build_dataflow_config.DataflowBuildConfig.verify_expected_output_npy

For integration with custom logic, if the custom logic is either before or after (not in the middle) of the neural net, I would recommend using Vivado IP Integrator (IPI) to put the FINN-generated IP block (with AXI stream input-output) together with your custom logic. This discussion has some helpful links for that: #387 (comment)