Stitch additional IP

[btwbtw01]

Hi,
I want to add compression IP for activation compression. After accelerator finishes computing, we will compress the activation to reduce DRAM access power. In the next iteration, we will compute the rest of the layer.
Suppose CNN has 8 layers, the FINN compiles 4 layers with MO architecture.
Here is the diagram.


Sorry I have asked this question before and the answer is here https://github.com/Xilinx/finn-examples/blob/main/build/README.md
but I need more detail.
As I know, FINN compiler will convert the convolution function into convolution HLS and stitched them up like this.

Then the IP directly turned into bitstream, but how can we add additional IP and stitch it. I don't have to modify the compiler like this. #385 Am I right?

By the way, can we try to compile architecture like computing layer by layer sequentially?
Below is diagram

Thanks!!!