FINN v0.9 released

[auphelia]

FINN release v0.9

The next FINN release is out! We are happy to announce FINN v0.9 today!

Next to the exciting new features you can check out on main, there is also other news:
@mmrahorovic is the new maintainer of finn-examples!

Here are some highlights of FINN v0.9:

• First steps to harden FINN building blocks
• Support for dynamic feature map dimensions
• Improvement for automatic FIFO sizing
• Board support
• Other new features

First steps to harden FINN building blocks

Some of the FINN building blocks have been around for a long time and have proven their efficiency. So, we started the effort to move these blocks from HLS to RTL to further improve the implementation and also the FINN compiler itself. Thanks to @fpjentzsch (University of Paderborn), we now not only have an RTL implementation of the ConvolutionInputGenerator that covers all function variants in the finn-hlslib but he also improved the resources and the latency of that component. You can check out the Verilog code here. Next to this new RTL component, we also have an RTL implementation of the FMPadding operator. The new RTL components exist next to the old HLS operators and are marked with an "_rtl" and you can use it by setting the builder argument force_rtl_conv_inp_gen to True. More detailed documentation on the new building blocks will follow!

Hardening the ConvolutionInputGenerator together with the FMPadding node enabled us to overcome FINN’s previous limitation to 1D or square input sizes.

And one additional new exciting feature could be implemented:

Support for dynamic feature map dimensions

Neural networks in applications such as semantic segmentation with fully convolutional networks need to handle different image sizes (J. Long et al., “Fully Convolutional Networks for Semantic Segmentation”, in arXiv:1411.4038). FINN does now support dynamic feature map sizes for convolution and pooling layers, by enabling the user to re-program the RTL components during runtime!

Through an AXI-Lite interface the layer can be reconfigured with 15 different parameters that describe the kernel size, stride and feature map size of convolution and pooling layers. For an example on how to make use of this feature, please have a look at this test in FINN.
Also, for this feature, thanks a lot to @fpjentzsch (University of Paderborn) for his contributions!

Improvement for automatic FIFO sizing

Long-time FINN users will know that running the automatic FIFO sizing in the compiler even though it leads to great results, can take a long time to complete. We are happy to announce that with this release, we have multiple improvements on the FIFO sizing flow. The biggest change is for linear topologies, here we introduce a new way of determining the FIFO sizes based on characterization functions. The functions indicate the read-write activity on each input-output stream per cycle for a given period (set by a throughput target), from that we can obtain the FIFO sizes. In addition to offering this new FIFO sizing approach for linear topologies, we also accelerated the old approach by implementing a pure C++ Verilator simulation.

Thanks to @hleblevec (IMT Atlantique), we now also have a transformation which allows the insertion of FIFO depths larger than the maximum allowed by Vivado (32k), by implementing a chain of FIFOs. This is especially valuable for topologies with long skip connections. The same mechanism can also be used to break down non-power-of-2 sized FIFOs into smaller ones for resource savings.

Board support

With this release, we also verified the support of Alveo cards again and, thanks to @patrickgeel (Delft University of Technology), added a new board to the supported boards list: KV260 (Kria Adaptive System-on-Modules)

Other New Features

• Additional layer types
  • 1D Downsample
  • 1D Upsample
  • StreamingEltwise layer
• Improvements on builder:
  • Enable arbitrary batch size in builder verification flow
  • New builder flag “verbose” to control build_dataflow verbosity
• Extension to existing layers:
  • Decoupled mode for VVAU
  • Lookup implementation over a table stored in AXI-accessible memory and input bounds checking