About SIMD and MW

[wanglu4042]

Hi, when I used the 'finn.transformation.fpgadataflow.create_stitched_ip.CreateStitchedIP（fpgapart、clk_ns、ip_name
='finn_design'、vitis=False、signature=[] ）' API, and also when I followed the example to build 'Stitched IP, out-of-context synth and rtlsim Performance' for my own network, like this:

As I was doing both, I ran into this problem, like this:

It says my SIMD should >= MW/1024, and I set SIMD = 16 for 'MatrixVectorActivation_4' when I did not use the 'CreateStitchedIP',like this:

In this part, the implement succeeded, but I want to know more about how FINN works, see more code.
So I did what I said in the beginning, but I tried both of the model, one is SIMD=1 and another is SIMD=16, they can not pass the HLS synthesis.
How can I build stitched ip and fix this problem?
I do have a solution in my mind that I can change the network to make MW < 1024, but that maybe cause other problems,
could you give me another solution?
I did the implement of my model on PYNQ-Z2, but I want to see the ip in Vivado, and I also want to know can I change the HLS code
which FINN wrote, so I can maybe do a little change to let the FPGA works faster?
Looking forward to your reply!
Thanks