diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td index f57f3fb10d..77d6881113 100644 --- a/include/aie/Dialect/AIE/IR/AIEOps.td +++ b/include/aie/Dialect/AIE/IR/AIEOps.td @@ -1258,7 +1258,8 @@ def AIE_BufferOp: AIE_Op<"buffer", [ ins Index:$tile, OptionalAttr:$sym_name, OptionalAttr:$address, - OptionalAttr:$initial_value + OptionalAttr:$initial_value, + OptionalAttr:$mem_bank ); let results = (outs AnyMemRef:$buffer); diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index 6c71eb2ecf..dd87f98a8c 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -25,6 +25,11 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { }]; let constructor = "xilinx::AIE::createAIEAssignBufferAddressesPass()"; + + let options = [ + Option<"clBasicAlloc", "basic-alloc", "bool", /*default=*/"false", + "Flag to enable the basic sequential allocation scheme (not bank-aware)."> + ]; } def AIEAssignLockIDs : Pass<"aie-assign-lock-ids", "DeviceOp"> { diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 21f557d93c..b260e0d275 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -12,7 +12,6 @@ #include "aie/Dialect/AIE/Transforms/AIEPasses.h" #include "mlir/IR/Attributes.h" -#include "mlir/Pass/Pass.h" #include "llvm/ADT/Twine.h" @@ -22,12 +21,349 @@ using namespace mlir; using namespace xilinx; using namespace xilinx::AIE; +//===----------------------------------------------------------------------===// +// BasicAllocation : sequential alloc from largest to smallest +//===----------------------------------------------------------------------===// +LogicalResult checkAndPrintOverflow(TileOp tile, int address, + int maxDataMemorySize, int stacksize, + SmallVector buffers) { + if (address > maxDataMemorySize) { + InFlightDiagnostic error = + tile.emitOpError("allocated buffers exceeded available memory\n"); + auto ¬e = error.attachNote() << "MemoryMap:\n"; + auto printbuffer = [&](StringRef name, int address, int size) { + note << "\t" << name << " \t" + << ": 0x" << llvm::utohexstr(address) << "-0x" + << llvm::utohexstr(address + size - 1) << " \t(" << size + << " bytes)\n"; + }; + if (stacksize > 0) + printbuffer("(stack)", 0, stacksize); + else + error << "(no stack allocated)\n"; + + for (auto buffer : buffers) { + assert(buffer.getAddress().has_value() && + "buffer must have address assigned"); + printbuffer(buffer.name(), buffer.getAddress().value(), + buffer.getAllocationSize()); + } + return failure(); + } + return success(); +} + +LogicalResult basicAllocation(TileOp &tile) { + auto device = tile->getParentOfType(); + if (!device) + return failure(); + + const auto &targetModel = getTargetModel(tile); + int maxDataMemorySize = 0; + if (tile.isMemTile()) + maxDataMemorySize = targetModel.getMemTileSize(); + else + maxDataMemorySize = targetModel.getLocalMemorySize(); + + SmallVector buffers; + // Collect all the buffers for this tile. + device.walk([&](BufferOp buffer) { + if (buffer.getTileOp() == tile) + buffers.push_back(buffer); + }); + // Sort by allocation size. + std::sort(buffers.begin(), buffers.end(), [](BufferOp a, BufferOp b) { + return a.getAllocationSize() > b.getAllocationSize(); + }); + + // Address range owned by the MemTile is 0x80000. + // Address range owned by the tile is 0x8000 in + // AIE1 and 0x10000 in AIE2, but we need room at + // the bottom for stack. + int stacksize = 0; + int address = 0; + if (auto core = tile.getCoreOp()) { + stacksize = core.getStackSize(); + address += stacksize; + } + + for (auto buffer : buffers) { + if (buffer.getAddress()) + buffer->emitWarning("Overriding existing address"); + buffer.setAddress(address); + address += buffer.getAllocationSize(); + } + + // Sort by smallest address before printing memory map. + std::sort(buffers.begin(), buffers.end(), [](BufferOp a, BufferOp b) { + assert(a.getAddress().has_value() && "buffer must have address assigned"); + assert(b.getAddress().has_value() && "buffer must have address assigned"); + return a.getAddress().value() < b.getAddress().value(); + }); + // Check if memory was exceeded on any bank and print debug info. + return checkAndPrintOverflow(tile, address, maxDataMemorySize, stacksize, + buffers); +} + +//===----------------------------------------------------------------------===// +// SimpleBankAwareAllocation : round-robin each alloc over available banks +//===----------------------------------------------------------------------===// +typedef struct BankLimits { + int64_t startAddr; + int64_t endAddr; +} BankLimits; + +// TODO: add to target model +int getNumBanks(TileOp tile) { + if (tile.isMemTile()) + return 1; + else + return 4; +} + +// Function that given a number of banks and their size, computes +// the start and end addresses for each bank and fills in the entry +// in the bankLimits vector. +void fillBankLimits(int numBanks, int bankSize, + std::vector &bankLimits) { + for (int i = 0; i < numBanks; i++) { + auto startAddr = bankSize * i; + auto endAddr = bankSize * (i + 1); + bankLimits.push_back({startAddr, endAddr}); + } +} + +// Function that sets the address attribute of the given buffer to +// the given start_addr. It also updates the entry in the +// nextAddrInBanks for the corresponding bank. +void setAndUpdateAddressInBank(BufferOp buffer, int64_t start_addr, + int64_t end_addr, + std::vector &nextAddrInBanks) { + // Fixme: alignment + buffer.setAddress(start_addr); + nextAddrInBanks[buffer.getMemBank().value()] = end_addr; +} + +// Function that checks whether the given buffer already has a set address +// attribute. If it does, it finds in which bank the buffer is and checks +// whether there is enough space left for it. If there is the function +// returns true and if not, the function emits a warning that the address +// will be overwritten and returns false (which will cause the buffer to be +// added to the list of buffers without addresses, to be completed later on). +bool checkAndAddBufferWithAddress(BufferOp buffer, int numBanks, + std::vector &nextAddrInBanks, + std::vector &bankLimits) { + if (auto addrAttr = buffer->getAttrOfType("address")) { + int addr = addrAttr.getInt(); + for (int i = 0; i < numBanks; i++) { + if (bankLimits[i].startAddr <= addr && addr < bankLimits[i].endAddr) { + if (addr >= nextAddrInBanks[i]) { + nextAddrInBanks[i] = addr + buffer.getAllocationSize(); + buffer.setMemBank(i); + } else { + buffer->emitWarning("Overriding existing address"); + return false; + } + } + } + return true; + } + return false; +} + +// Function that checks whether the given buffer already has a set mem_bank +// attribute. If it does, it checks whether there is enough space left for +// it. If there is, it sets the buffer's address field and if not, the +// function emits a warning that the mem_bank will be overwritten and returns +// false (which will cause the buffer to be added to the list of buffers +// without addresses, to be completed later on). +bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, + std::vector &nextAddrInBanks, + std::vector &bankLimits) { + if (auto memBankAttr = buffer->getAttrOfType("mem_bank")) { + int mem_bank = memBankAttr.getInt(); + int64_t startAddr = nextAddrInBanks[mem_bank]; + int64_t endAddr = startAddr + buffer.getAllocationSize(); + if (endAddr <= bankLimits[mem_bank].endAddr) { + setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); + } else { + buffer->emitWarning("Overriding existing mem_bank"); + return false; + } + return true; + } + return false; +} + +// Function that given a buffer will iterate over all the memory banks +// starting from the given index to try and find a bank with enough +// space. If it does, it will set the buffer's address and mem_bank +// attributes and update the nextAddrInBanks vector. +// If it does not find one with enough space, it will allocate the +// buffer in the last checked bank (this will be picked up during +// overflow error checking). Finally, the function returns the index +// of the next bank to search (which should be given to subsequent +// calls of this function to ensure a round-robin allocation scheme +// over the available banks). +int setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, + std::vector &nextAddrInBanks, + std::vector &bankLimits) { + int bankIndex = startBankIndex; + for (int i = 0; i < numBanks; i++) { + int64_t startAddr = nextAddrInBanks[bankIndex]; + int64_t endAddr = startAddr + buffer.getAllocationSize(); + if (endAddr <= bankLimits[bankIndex].endAddr || i == numBanks - 1) { + buffer.setMemBank(bankIndex); + setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); + bankIndex++; + break; + } + bankIndex++; + } + bankIndex %= numBanks; + return bankIndex; +} + +LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, + SmallVector allBuffers, + std::vector &nextAddrInBanks, + std::vector &bankLimits) { + bool foundOverflow = false; + std::vector overflow_banks; + for (int i = 0; i < numBanks; i++) { + if (nextAddrInBanks[i] > bankLimits[i].endAddr) { + foundOverflow = true; + overflow_banks.push_back(i); + } + } + if (foundOverflow) { + InFlightDiagnostic error = + tile.emitOpError("allocated buffers exceeded available memory\n"); + auto ¬e = error.attachNote() << "Error in bank(s) : "; + for (auto bank : overflow_banks) + note << bank << " "; + note << "\n"; + note << "MemoryMap:\n"; + auto printbuffer = [&](StringRef name, int address, int size) { + note << "\t" + << "\t" << name << " \t" + << ": 0x" << llvm::utohexstr(address) << "-0x" + << llvm::utohexstr(address + size - 1) << " \t(" << size + << " bytes)\n"; + }; + for (int i = 0; i < numBanks; i++) { + note << "\t" + << "bank : " << i << "\t" + << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" + << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; + if (i == 0) { + if (stacksize > 0) + printbuffer("(stack)", 0, stacksize); + else + error << "(no stack allocated)\n"; + } + for (auto buffer : allBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + } + return failure(); + } + return success(); +} + +LogicalResult simpleBankAwareAllocation(TileOp tile) { + auto device = tile->getParentOfType(); + if (!device) + return failure(); + + std::vector + nextAddrInBanks; // each entry is the next address available for use + // for that bank + // (e.g. nextAddrInBanks[tile_0][1] = next available + // address in bank 1 for tile_0) + std::vector bankLimits; // the entries contain pairs of start and + // end addresses for each bank + + const auto &targetModel = getTargetModel(tile); + int maxDataMemorySize = 0; + if (tile.isMemTile()) + maxDataMemorySize = targetModel.getMemTileSize(); + else + maxDataMemorySize = targetModel.getLocalMemorySize(); + + int numBanks = getNumBanks(tile); + int bankSize = maxDataMemorySize / numBanks; + + // Address range owned by the MemTile is 0x80000. + // Address range owned by the tile is 0x8000 in + // AIE1 and 0x10000 in AIE2, but we need room at + // the bottom for stack. + int stacksize = 0; + for (int i = 0; i < numBanks; i++) + nextAddrInBanks.push_back(bankSize * i); + if (auto core = tile.getCoreOp()) { + stacksize = core.getStackSize(); + nextAddrInBanks[0] += stacksize; + } + fillBankLimits(numBanks, bankSize, bankLimits); + + SmallVector buffersToAlloc; + SmallVector allBuffers; + // Collect all the buffers for this tile. + device.walk([&](BufferOp buffer) { + if (buffer.getTileOp() == tile) + allBuffers.push_back(buffer); + }); + // If possible, the buffers with an already specified address will not + // be overwritten (the available address range of the bank the buffers + // are in will start AFTER the specified adress + buffer size). + // Buffers with a specified mem_bank will be assigned first, after + // the above. + for (auto buffer : allBuffers) { + if (buffer.getTileOp() == tile) { + bool has_addr = checkAndAddBufferWithAddress(buffer, numBanks, + nextAddrInBanks, bankLimits); + bool has_bank = checkAndAddBufferWithMemBank(buffer, numBanks, + nextAddrInBanks, bankLimits); + if (!has_addr && !has_bank) + buffersToAlloc.push_back(buffer); + } + } + + // Sort by largest allocation size before allocating. + std::sort(buffersToAlloc.begin(), buffersToAlloc.end(), + [](BufferOp a, BufferOp b) { + return a.getAllocationSize() > b.getAllocationSize(); + }); + + // Set addresses for remaining buffers. + int bankIndex = 0; + for (auto buffer : buffersToAlloc) + bankIndex = setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, + bankLimits); + + // Sort by smallest address before printing memory map. + std::sort(allBuffers.begin(), allBuffers.end(), [](BufferOp a, BufferOp b) { + assert(a.getAddress().has_value() && "buffer must have address assigned"); + assert(b.getAddress().has_value() && "buffer must have address assigned"); + return a.getAddress().value() < b.getAddress().value(); + }); + // Check if memory was exceeded on any bank and print debug info. + return checkAndPrintOverflow(tile, numBanks, stacksize, allBuffers, + nextAddrInBanks, bankLimits); +} + struct AIEAssignBufferAddressesPass : AIEAssignBufferAddressesBase { + void getDependentDialects(DialectRegistry ®istry) const override { registry.insert(); registry.insert(); } + void runOnOperation() override { DeviceOp device = getOperation(); OpBuilder builder = OpBuilder::atBlockEnd(device.getBody()); @@ -42,63 +378,16 @@ struct AIEAssignBufferAddressesPass } }); - for (auto tile : device.getOps()) { - const auto &targetModel = getTargetModel(tile); - int maxDataMemorySize = 0; - if (tile.isMemTile()) - maxDataMemorySize = targetModel.getMemTileSize(); - else - maxDataMemorySize = targetModel.getLocalMemorySize(); - SmallVector buffers; - // Collect all the buffers for this tile. - device.walk([&](BufferOp buffer) { - if (buffer.getTileOp() == tile) - buffers.push_back(buffer); - }); - // Sort by allocation size. - std::sort(buffers.begin(), buffers.end(), [](BufferOp a, BufferOp b) { - return a.getAllocationSize() > b.getAllocationSize(); - }); - - // Address range owned by the MemTile is 0x80000. - // Address range owned by the tile is 0x8000, - // but we need room at the bottom for stack. - int stacksize = 0; - int address = 0; - if (auto core = tile.getCoreOp()) { - stacksize = core.getStackSize(); - address += stacksize; + // Select allocation scheme + if (clBasicAlloc) { + for (auto tile : device.getOps()) { + if (auto res = basicAllocation(tile); res.failed()) + return signalPassFailure(); } - - for (auto buffer : buffers) { - if (buffer.getAddress()) - buffer->emitWarning("Overriding existing address"); - buffer.setAddress(address); - address += buffer.getAllocationSize(); - } - - if (address > maxDataMemorySize) { - InFlightDiagnostic error = - tile.emitOpError("allocated buffers exceeded available memory\n"); - auto ¬e = error.attachNote() << "MemoryMap:\n"; - auto printbuffer = [&](StringRef name, int address, int size) { - note << "\t" << name << " \t" - << ": 0x" << llvm::utohexstr(address) << "-0x" - << llvm::utohexstr(address + size - 1) << " \t(" << size - << " bytes)\n"; - }; - if (stacksize > 0) - printbuffer("(stack)", 0, stacksize); - else - error << "(no stack allocated)\n"; - - for (auto buffer : buffers) { - assert(buffer.getAddress().has_value() && - "buffer must have address assigned"); - printbuffer(buffer.name(), buffer.getAddress().value(), - buffer.getAllocationSize()); - } - return signalPassFailure(); + } else { + for (auto tile : device.getOps()) { + if (auto res = simpleBankAwareAllocation(tile); res.failed()) + return signalPassFailure(); } } } diff --git a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp index 4fba2496c1..762d60607f 100644 --- a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp +++ b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp @@ -378,7 +378,8 @@ struct AIEObjectFifoStatefulTransformPass builder.getUnknownLoc(), elemType, creation_tile, builder.getStringAttr(op.name().str() + "_buff_" + std::to_string(of_elem_index)), - /*address*/ nullptr, /*initial_value*/ nullptr); + /*address*/ nullptr, /*initial_value*/ nullptr, + /*mem_bank*/ nullptr); buffers.push_back(buff); } of_elem_index++; diff --git a/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp b/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp index af93742ee5..15f1ca7347 100644 --- a/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp +++ b/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp @@ -125,7 +125,8 @@ struct AIECreateCoresPass : public AIECreateCoresBase { coreBufTypes.push_back({t, i}); BufferOp buf = builder.create( builder.getUnknownLoc(), t, tile, /*sym_name*/ nullptr, - /*address*/ nullptr, /*initial_value*/ nullptr); + /*address*/ nullptr, /*initial_value*/ nullptr, + /*mem_bank*/ nullptr); buffers[callOperands[i]] = buf; operand.replaceAllUsesWith(buf.getResult()); } diff --git a/programming_examples/ml/bottleneck/run.lit b/programming_examples/ml/bottleneck/run.lit index 7d6f2abcc4..c6cb946c19 100644 --- a/programming_examples/ml/bottleneck/run.lit +++ b/programming_examples/ml/bottleneck/run.lit @@ -7,6 +7,6 @@ // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -DUINT8_ACT -c %S/../../../aie_kernels/aie2/conv2dk3.cc -o conv2dk3.o // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -DINT8_ACT -c %S/../../../aie_kernels/aie2/conv2dk1_skip.cc -o conv2dk1_skip.o // RUN: %python %S/aie2.py | aie-opt -cse -canonicalize -o ./aie.mlir -// RUN: %python aiecc.py --xbridge --aie-generate-cdo --aie-generate-npu --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt ./aie.mlir +// RUN: %python aiecc.py --xbridge --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt ./aie.mlir // RUN: %run_on_npu %python %S/test.py -x aie.xclbin -i insts.txt -k MLIR_AIE | FileCheck %s // CHECK: PASS! \ No newline at end of file diff --git a/programming_examples/vision/color_detect/Makefile b/programming_examples/vision/color_detect/Makefile index 5bc10e013d..5f7190af1b 100755 --- a/programming_examples/vision/color_detect/Makefile +++ b/programming_examples/vision/color_detect/Makefile @@ -41,7 +41,7 @@ build/aie2_lineBased_8b_${COLORDETECT_WIDTH}.mlir: ${srcdir}/aie2_colorDetect.py build/final_${COLORDETECT_WIDTH}.xclbin: build/aie2_lineBased_8b_${COLORDETECT_WIDTH}.mlir build/rgba2hue.cc.o build/threshold.cc.o build/combined_bitwiseOR_gray2rgba_bitwiseAND.a mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) ${targetname}.exe: ${srcdir}/test.cpp diff --git a/programming_examples/vision/color_threshold/Makefile b/programming_examples/vision/color_threshold/Makefile index b90228b96f..740ae6bc0c 100644 --- a/programming_examples/vision/color_threshold/Makefile +++ b/programming_examples/vision/color_threshold/Makefile @@ -34,7 +34,7 @@ build/aie2_${COLORTHRESHOLD_WIDTH}.mlir: ${srcdir}/aie2_colorThreshold.py build/final_${COLORTHRESHOLD_WIDTH}.xclbin: build/aie2_${COLORTHRESHOLD_WIDTH}.mlir build/threshold.cc.o mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) ${targetname}.exe: ${srcdir}/test.cpp diff --git a/programming_examples/vision/edge_detect/Makefile b/programming_examples/vision/edge_detect/Makefile index 19ae0cd24f..19e1ccd734 100755 --- a/programming_examples/vision/edge_detect/Makefile +++ b/programming_examples/vision/edge_detect/Makefile @@ -41,7 +41,7 @@ build/aie2_lineBased_8b_${EDGEDETECT_WIDTH}.mlir: ${srcdir}/aie2_edgeDetect.py build/final_${EDGEDETECT_WIDTH}.xclbin: build/aie2_lineBased_8b_${EDGEDETECT_WIDTH}.mlir build/rgba2gray.cc.o build/gray2rgba.cc.o build/filter2d.cc.o build/threshold.cc.o build/addWeighted.cc.o build/combined_gray2rgba_addWeighted.a mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) ${targetname}.exe: ${srcdir}/test.cpp diff --git a/programming_examples/vision/vision_passthrough/Makefile b/programming_examples/vision/vision_passthrough/Makefile index e7a6d310a5..e86aac2f99 100644 --- a/programming_examples/vision/vision_passthrough/Makefile +++ b/programming_examples/vision/vision_passthrough/Makefile @@ -34,7 +34,7 @@ build/passThrough.cc.o: passThrough.cc build/final_${PASSTHROUGH_WIDTH}.xclbin: build/aie2_lineBased_8b_${PASSTHROUGH_WIDTH}.mlir build/passThrough.cc.o mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) ${targetname}.exe: ${srcdir}/test.cpp diff --git a/python/compiler/aiecc/cl_arguments.py b/python/compiler/aiecc/cl_arguments.py index a407dda971..cbfb5edcd3 100644 --- a/python/compiler/aiecc/cl_arguments.py +++ b/python/compiler/aiecc/cl_arguments.py @@ -138,6 +138,13 @@ def parse_args(args=None): action="store_false", help="Disable linking of AIE code", ) + parser.add_argument( + "--basic-alloc-scheme", + dest="basic_alloc_scheme", + default=False, + action="store_true", + help="Use basic memory allocation scheme for AIE buffer address assignment", + ) parser.add_argument( "--aie-generate-airbin", dest="airbin", diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index 35a268d245..04439a8d9b 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -35,7 +35,7 @@ from aie.ir import Context, Location, Module from aie.passmanager import PassManager -INPUT_WITH_ADDRESSES_PIPELINE = ( +INPUT_WITH_SWITCHBOXES_PIPELINE = ( Pipeline() .lower_affine() .add_pass("aie-canonicalize-device") @@ -49,8 +49,7 @@ .add_pass("aie-lower-cascade-flows") .add_pass("aie-lower-broadcast-packet") .add_pass("aie-create-packet-flows") - .add_pass("aie-lower-multicast") - .add_pass("aie-assign-buffer-addresses"), + .add_pass("aie-lower-multicast"), ) .convert_scf_to_cf() ) @@ -986,15 +985,37 @@ async def run_flow(self): "[green] MLIR compilation:", total=1, command="1 Worker" ) - file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") - pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE.materialize(module=True) + file_with_switchboxes = self.prepend_tmp("input_with_switchboxes.mlir") + pass_pipeline = INPUT_WITH_SWITCHBOXES_PIPELINE.materialize(module=True) run_passes( pass_pipeline, self.mlir_module_str, - file_with_addresses, + file_with_switchboxes, self.opts.verbose, ) + file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") + if opts.basic_alloc_scheme: + do_run( + [ + "aie-opt", + "--aie-assign-buffer-addresses=basic-alloc", + file_with_switchboxes, + "-o", + file_with_addresses, + ], + ) + else: + do_run( + [ + "aie-opt", + "--aie-assign-buffer-addresses", + file_with_switchboxes, + "-o", + file_with_addresses, + ], + ) + cores = generate_cores_list(await read_file_async(file_with_addresses)) t = do_run( [ diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir new file mode 100644 index 0000000000..77b7996d76 --- /dev/null +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -0,0 +1,39 @@ +//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory +// CHECK: Error in bank(s) : 3 +// CHECK: MemoryMap: +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: (stack) : 0x0-0x3FF (1024 bytes) +// CHECK: c : 0x400-0x41F (32 bytes) +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: a : 0x2000-0x200F (16 bytes) +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: bank : 3 0x6000-0x7FFF +// CHECK: b : 0x6000-0xDFFF (32768 bytes) + +module @test { + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end + } + aie.core(%3) { + aie.end + } + } +} diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir new file mode 100644 index 0000000000..7c639528d4 --- /dev/null +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -0,0 +1,27 @@ +//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory +// CHECK: Error in bank(s) : 0 +// CHECK: MemoryMap: +// CHECK: bank : 0 0x0-0x7FFFF +// CHECK: a : 0x0-0x80E7F (528000 bytes) + + +module @test { + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> + aie.memtile_dma(%0) { + aie.end + } + } +} diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir new file mode 100644 index 0000000000..aee7b03b91 --- /dev/null +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -0,0 +1,22 @@ +//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> + +module @test { + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> + aie.memtile_dma(%0) { + aie.end + } + } +} diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir new file mode 100644 index 0000000000..84812a14c8 --- /dev/null +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -0,0 +1,32 @@ +//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-assign-buffer-addresses %s | FileCheck %s +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> + +module @test { + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end + } + aie.core(%3) { + aie.end + } + } +} diff --git a/test/assign-buffer-addresses/error.mlir b/test/assign-buffer-addresses/basic_alloc_error.mlir similarity index 92% rename from test/assign-buffer-addresses/error.mlir rename to test/assign-buffer-addresses/basic_alloc_error.mlir index 901481da18..9c2d85f4f3 100644 --- a/test/assign-buffer-addresses/error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory // CHECK: (stack) : 0x0-0x3FF (1024 bytes) // CHECK: b : 0x400-0x83FF (32768 bytes) diff --git a/test/assign-buffer-addresses/memtile_error.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir similarity index 88% rename from test/assign-buffer-addresses/memtile_error.mlir rename to test/assign-buffer-addresses/basic_alloc_memtile_error.mlir index 029e256896..b179f8e842 100644 --- a/test/assign-buffer-addresses/memtile_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory module @test { diff --git a/test/assign-buffer-addresses/memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir similarity index 89% rename from test/assign-buffer-addresses/memtile_simple.mlir rename to test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index 4e7562476c..ef468d1e63 100644 --- a/test/assign-buffer-addresses/memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> module @test { diff --git a/test/assign-buffer-addresses/simple.mlir b/test/assign-buffer-addresses/basic_alloc_simple.mlir similarity index 93% rename from test/assign-buffer-addresses/simple.mlir rename to test/assign-buffer-addresses/basic_alloc_simple.mlir index 917c7d03c5..51254e4f41 100644 --- a/test/assign-buffer-addresses/simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses %s | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="basic-alloc" %s | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir index d0a78ee4ae..02a31927cc 100755 --- a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir +++ b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark01_DDR_SHIM_fill_rate { diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir index 19dfcf5f9e..00c411181b 100755 --- a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir +++ b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark_02_LM2DDR { diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir index ed6b8b84cd..f5d92661d8 100755 --- a/test/benchmarks/03_Flood_DDR/aie.mlir +++ b/test/benchmarks/03_Flood_DDR/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark03_Flood_DDR { diff --git a/test/dialect/AIE/badbuffer-ve2802.mlir b/test/dialect/AIE/badbuffer-ve2802.mlir index 686a2ee19c..41f5e4f46d 100644 --- a/test/dialect/AIE/badbuffer-ve2802.mlir +++ b/test/dialect/AIE/badbuffer-ve2802.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // Row 2 is a memtile, not a coretile. // CHECK: error{{.*}}'aie.buffer' op in Column 1 and Row 2 is accessed from an unreachable tile in Column 1 and Row 3 diff --git a/test/dialect/AIE/badbuffer.mlir b/test/dialect/AIE/badbuffer.mlir index 2f593e459f..8917a2d361 100644 --- a/test/dialect/AIE/badbuffer.mlir +++ b/test/dialect/AIE/badbuffer.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.buffer' op in Column 1 and Row 1 is accessed from an unreachable tile in Column 4 and Row 4 module @test { diff --git a/test/dialect/AIE/badconnect.mlir b/test/dialect/AIE/badconnect.mlir index 1c89f08af7..8527fec614 100644 --- a/test/dialect/AIE/badconnect.mlir +++ b/test/dialect/AIE/badconnect.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}} 'aie.connect' op source index cannot be less than zero module { diff --git a/test/dialect/AIE/badcore.mlir b/test/dialect/AIE/badcore.mlir index 0e282f94e2..1993b40081 100644 --- a/test/dialect/AIE/badcore.mlir +++ b/test/dialect/AIE/badcore.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.core' op failed to verify that op exists in a core tile module @test { diff --git a/test/dialect/AIE/badcore2.mlir b/test/dialect/AIE/badcore2.mlir index 7505327981..20d6b2e92a 100644 --- a/test/dialect/AIE/badcore2.mlir +++ b/test/dialect/AIE/badcore2.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.core' op failed to verify that op exists in a core tile module @test { diff --git a/test/dialect/AIE/badlock-vc1902.mlir b/test/dialect/AIE/badlock-vc1902.mlir index 780b3fccc7..0b871e892e 100644 --- a/test/dialect/AIE/badlock-vc1902.mlir +++ b/test/dialect/AIE/badlock-vc1902.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.lock' op lock assigned invalid id (maximum is 15) module @test { %t1 = aie.tile(1, 1) diff --git a/test/dialect/AIE/badlock-ve2802.mlir b/test/dialect/AIE/badlock-ve2802.mlir index 657570ad0f..90e8109cfe 100644 --- a/test/dialect/AIE/badlock-ve2802.mlir +++ b/test/dialect/AIE/badlock-ve2802.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.lock' op lock assigned invalid id (maximum is 63) module @test { aie.device(xcve2802) { diff --git a/test/dialect/AIE/badlockdma.mlir b/test/dialect/AIE/badlockdma.mlir index 9e79e66559..38b08dd795 100644 --- a/test/dialect/AIE/badlockdma.mlir +++ b/test/dialect/AIE/badlockdma.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.lock' op in Column 4 and Row 4 is accessed from an unreachable tile in Column 1 and Row 1 module @test { %t1 = aie.tile(1, 1) diff --git a/test/dialect/AIE/badlockfunc.mlir b/test/dialect/AIE/badlockfunc.mlir index df345d3498..06ca188bb7 100644 --- a/test/dialect/AIE/badlockfunc.mlir +++ b/test/dialect/AIE/badlockfunc.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.lock' op is accessed outside of a tile module @test { %t1 = aie.tile(1, 1) diff --git a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir index 79eead4431..22115e3e51 100644 --- a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir +++ b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.buffer' op in Column 3 and Row 1 is accessed from an unreachable tile in Column 1 and Row 1 // memtiles can only access neighboring memtiles diff --git a/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir b/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir index d4c9eaa330..69c0bc54dc 100644 --- a/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir +++ b/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.connect' op source bundle FIFO not supported module { diff --git a/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir b/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir index 0540fcd7ca..a7f71c9d61 100644 --- a/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir +++ b/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.connect' op source bundle DMA not supported module { diff --git a/test/dialect/AIE/badtile-ve2802.mlir b/test/dialect/AIE/badtile-ve2802.mlir index 4cd7856bf9..1ed7dc4bc2 100644 --- a/test/dialect/AIE/badtile-ve2802.mlir +++ b/test/dialect/AIE/badtile-ve2802.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.tile' op column index (50) must be less than the number of columns in the device (38) module @test { diff --git a/test/dialect/AIE/badtile.mlir b/test/dialect/AIE/badtile.mlir index 1b96f7ae56..0888b6f1e5 100644 --- a/test/dialect/AIE/badtile.mlir +++ b/test/dialect/AIE/badtile.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.tile' op attribute 'col' failed to satisfy constraint: 32-bit signless integer attribute whose minimum value is 0 module @test { diff --git a/test/dialect/AIE/badtile2.mlir b/test/dialect/AIE/badtile2.mlir index 2c2aa27116..fae09db62c 100644 --- a/test/dialect/AIE/badtile2.mlir +++ b/test/dialect/AIE/badtile2.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.tile' op column index (50) must be less than the number of columns in the device (50) module @test { diff --git a/test/dialect/AIE/badtiledma.mlir b/test/dialect/AIE/badtiledma.mlir index cb41a6114b..22ca8bdc71 100644 --- a/test/dialect/AIE/badtiledma.mlir +++ b/test/dialect/AIE/badtiledma.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.use_lock' op used in a DMA block that have multiple locks. module @test { diff --git a/test/dialect/AIE/badtiledma2.mlir b/test/dialect/AIE/badtiledma2.mlir index d15d1d7879..9ffed81fc9 100644 --- a/test/dialect/AIE/badtiledma2.mlir +++ b/test/dialect/AIE/badtiledma2.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.dma_bd' op Core tile DMAs can only access a buffer in the same tile. module @test { diff --git a/test/dialect/AIE/badtiledma3.mlir b/test/dialect/AIE/badtiledma3.mlir index 5af6a3cfc6..bab4484672 100644 --- a/test/dialect/AIE/badtiledma3.mlir +++ b/test/dialect/AIE/badtiledma3.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s +// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s // CHECK: error{{.*}}'aie.use_lock' op can only access a lock in the same tile module @test { diff --git a/test/npu-xrt/add_one_using_dma/run.lit b/test/npu-xrt/add_one_using_dma/run.lit index a137e2e4ae..35aa0b374d 100644 --- a/test/npu-xrt/add_one_using_dma/run.lit +++ b/test/npu-xrt/add_one_using_dma/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/matrix_multiplication_using_dma/run.lit b/test/npu-xrt/matrix_multiplication_using_dma/run.lit index 850baf0a7d..c6a0f7a6ea 100644 --- a/test/npu-xrt/matrix_multiplication_using_dma/run.lit +++ b/test/npu-xrt/matrix_multiplication_using_dma/run.lit @@ -4,7 +4,7 @@ // REQUIRES: ryzen_ai, chess // // RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/mm.cc -o ./mm.o -// RUN: %python aiecc.py --xbridge --aie-generate-cdo --aie-generate-npu --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --xbridge --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index 129edb9e68..c28f87e766 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -18,18 +18,18 @@ // CHECK: after core start // CHECK: DMA [7, 3] // CHECK: BD 0 valid (Next BD: 1) -// CHECK: Transferring 2 32 bit words to/from byte address 000C00 +// CHECK: Transferring 2 32 bit words to/from byte address 006000 // CHECK: Acquires lock 0 with value 0 Releases lock 0 with value 1 currently Acquired 1 // CHECK: BD 1 valid (Last BD) // CHECK: * Current BD for mm2s channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 000C10 +// CHECK: Transferring 2 32 bit words to/from byte address 006010 // CHECK: Acquires lock 1 with value 0 Releases lock 1 with value 1 currently Acquired 1 // CHECK: BD 2 valid (Next BD: 3) -// CHECK: Transferring 2 32 bit words to/from byte address 000C20 +// CHECK: Transferring 2 32 bit words to/from byte address 006020 // CHECK: Acquires lock 2 with value 0 Releases lock 2 with value 1 currently Acquired 1 // CHECK: BD 3 valid (Last BD) // CHECK: * Current BD for s2mm channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 000C30 +// CHECK: Transferring 2 32 bit words to/from byte address 006030 // CHECK: Acquires lock 3 with value 0 Releases lock 3 with value 1 currently Acquired 1 // CHECK: Lock 0: Acquired 1 // CHECK: Lock 1: Acquired 1 diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index 28f5dd04e4..df46768688 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -22,21 +22,21 @@ // CHECK: DMA [7, 3] AIE2 mm2s0 IDLE // CHECK: DMA [7, 3] AIE2 mm2s1 IDLE // CHECK: BD 0 valid (Next BD: 1) -// CHECK: Transferring 2 32 bit words to/from byte address 000C00 +// CHECK: Transferring 2 32 bit words to/from byte address 00C000 // CHECK: Acquires lock 0 with value -1 // CHECK: Releases lock 1 with value 1 // CHECK: BD 1 valid (Last BD) // CHECK: * Current BD for mm2s channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 000C10 +// CHECK: Transferring 2 32 bit words to/from byte address 00C010 // CHECK: Acquires lock 0 with value -1 // CHECK: Releases lock 1 with value 1 // CHECK: BD 2 valid (Next BD: 3) -// CHECK: Transferring 2 32 bit words to/from byte address 000C20 +// CHECK: Transferring 2 32 bit words to/from byte address 00C020 // CHECK: Acquires lock 2 with value -1 // CHECK: Releases lock 3 with value 1 // CHECK: BD 3 valid (Last BD) // CHECK: * Current BD for s2mm channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 000C30 +// CHECK: Transferring 2 32 bit words to/from byte address 00C030 // CHECK: Acquires lock 2 with value -1 // CHECK: Releases lock 3 with value 1 // CHECK: Core [7, 3] AIE2 locks are: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0