diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td
index 8d7dc897a7..b4101b4406 100644
--- a/include/aie/Dialect/AIE/IR/AIEOps.td
+++ b/include/aie/Dialect/AIE/IR/AIEOps.td
@@ -1384,7 +1384,7 @@ def AIE_GetStreamOp: AIE_Op<"get_stream", [
   let extraClassDeclaration = [{
     bool isWideStream() { return getStreamValue().getType().isInteger(128); }
     bool isFloatStream() {
-      return getStreamValue().getType().isa<mlir::FloatType>();
+      return llvm::isa<mlir::FloatType>(getStreamValue().getType());
     }
   }];
 }
@@ -1407,7 +1407,7 @@ def AIE_PutStreamOp: AIE_Op<"put_stream", [HasParent<"CoreOp">]> {
   let extraClassDeclaration = [{
     bool isWideStream() { return getStreamValue().getType().isInteger(128); }
     bool isFloatStream() {
-      return getStreamValue().getType().isa<mlir::FloatType>();
+      return llvm::isa<mlir::FloatType>(getStreamValue().getType());
     }
   }];
 }
@@ -1920,24 +1920,21 @@ def AIE_ObjectFifoRegisterProcessOp: AIE_Op<"objectfifo.register_process", []> {
     ObjectFifoCreateOp getObjectFifo();
 
     mlir::DenseIntElementsAttr getAcquirePattern() {
-      return getAcquirePatternTensor()
+      return llvm::cast<mlir::DenseIntElementsAttr>(getAcquirePatternTensor()
           .getDefiningOp<mlir::arith::ConstantOp>()
-          .getValue()
-          .cast<mlir::DenseIntElementsAttr>();
+          .getValue());
     }
 
     mlir::DenseIntElementsAttr getReleasePattern() {
-      return getReleasePatternTensor()
+      return llvm::cast<mlir::DenseIntElementsAttr>(getReleasePatternTensor()
           .getDefiningOp<mlir::arith::ConstantOp>()
-          .getValue()
-          .cast<mlir::DenseIntElementsAttr>();
+          .getValue());
     }
 
     int getProcessLength() {
-      return getLength()
+      return llvm::cast<mlir::IntegerAttr>(getLength()
           .getDefiningOp<mlir::arith::ConstantOp>()
-          .getValue()
-          .cast<mlir::IntegerAttr>()
+          .getValue())
           .getInt();
     }
   }];
diff --git a/include/aie/Dialect/AIE/IR/AIETypes.td b/include/aie/Dialect/AIE/IR/AIETypes.td
index 135cd97751..75c049b85a 100644
--- a/include/aie/Dialect/AIE/IR/AIETypes.td
+++ b/include/aie/Dialect/AIE/IR/AIETypes.td
@@ -17,11 +17,11 @@ include "aie/Dialect/AIE/IR/AIEAttrs.td"
 include "mlir/IR/AttrTypeBase.td"
 
 def AIE_ObjectFifoType :
-    DialectType<AIE_Dialect, CPred<"$_self.isa<AIEObjectFifoType>()">,
+    DialectType<AIE_Dialect, CPred<"llvm::isa<AIEObjectFifoType>($_self)">,
                 "AIE objectFifo type">;
 
 def AIE_ObjectFifoSubviewType :
-    DialectType<AIE_Dialect, CPred<"$_self.isa<AIEObjectFifoSubviewType>()">,
+    DialectType<AIE_Dialect, CPred<"llvm::isa<AIEObjectFifoSubviewType>($_self)">,
                 "AIE ObjectFifoSubview type">;
 
 def AIE_Type : AnyTypeOf<[AIE_ObjectFifoType, AIE_ObjectFifoSubviewType]>;
diff --git a/include/aie/Dialect/AIE/Transforms/AIENormalizeAddressSpaces.td b/include/aie/Dialect/AIE/Transforms/AIENormalizeAddressSpaces.td
index 2ce97b3652..3a3f539093 100644
--- a/include/aie/Dialect/AIE/Transforms/AIENormalizeAddressSpaces.td
+++ b/include/aie/Dialect/AIE/Transforms/AIENormalizeAddressSpaces.td
@@ -18,7 +18,7 @@ include "mlir/IR/PatternBase.td"
 
 def toDefaultAddressSpace : NativeCodeCall<"TypeAttr::get(memRefToDefaultAddressSpace($0.getValue()))">;
 def hasNonDefaultAddressSpace : Constraint<
-    CPred<"$0.getValue().cast<mlir::MemRefType>().getMemorySpace() != 0">,
+    CPred<"llvm::cast<mlir::MemRefType>($0.getValue()).getMemorySpace() != 0">,
     "has non-default address space">;
 def : Pat<
         /*pattern*/ (MemRef_GlobalOp $sym_name, $sym_visibility, $type, $initial_value, $constant, $attrs),
diff --git a/include/aie/Dialect/AIEVec/AIEVecUtils.h b/include/aie/Dialect/AIEVec/AIEVecUtils.h
index 410e8dd7e2..477a3306e9 100644
--- a/include/aie/Dialect/AIEVec/AIEVecUtils.h
+++ b/include/aie/Dialect/AIEVec/AIEVecUtils.h
@@ -46,7 +46,7 @@ inline mlir::VectorType createVectorType(unsigned lanes,
 
 // Return the size (in bits) of the underlying element type of the vector
 inline int32_t getElementSizeInBits(mlir::VectorType type) {
-  return type.cast<mlir::ShapedType>().getElementTypeBitWidth();
+  return llvm::cast<mlir::ShapedType>(type).getElementTypeBitWidth();
 }
 
 // Return the number of lanes along the vectorized dimension for the vector
@@ -147,7 +147,7 @@ flattenedStridedExpr(llvm::ArrayRef<int64_t> sizes,
 
 // Construct a linearized affine expression for the upd op.
 inline mlir::AffineExpr constructLinearizedAffineExprForUPDOp(UPDOp updOp) {
-  auto memRefType = updOp.getSource().getType().cast<mlir::MemRefType>();
+  auto memRefType = llvm::cast<mlir::MemRefType>(updOp.getSource().getType());
   mlir::MLIRContext *context = memRefType.getContext();
 
   llvm::SmallVector<mlir::AffineExpr, 8> exprVec;
@@ -164,7 +164,8 @@ inline mlir::AffineExpr constructLinearizedAffineExprForUPDOp(UPDOp updOp) {
 
       for (auto index : apOf.getMapOperands())
         if (auto cIdx = index.getDefiningOp<mlir::arith::ConstantOp>()) {
-          auto idxVal = cIdx.getValue().cast<mlir::IntegerAttr>().getValue();
+          auto idxVal =
+              llvm::cast<mlir::IntegerAttr>(cIdx.getValue()).getValue();
           unsigned idx = idxVal.getSExtValue();
           indexExprs.push_back(getAffineConstantExpr(idx, context));
         } else {
@@ -176,7 +177,7 @@ inline mlir::AffineExpr constructLinearizedAffineExprForUPDOp(UPDOp updOp) {
 
       exprVec.push_back(map.getResult(0).replaceDims(indexExprs));
     } else if (auto cOp = value.getDefiningOp<mlir::arith::ConstantOp>()) {
-      auto idxVal = cOp.getValue().cast<mlir::IntegerAttr>().getValue();
+      auto idxVal = llvm::cast<mlir::IntegerAttr>(cOp.getValue()).getValue();
       unsigned idx = idxVal.getSExtValue();
       exprVec.push_back(getAffineConstantExpr(idx, context));
     } else {
diff --git a/lib/CAPI/Dialects.cpp b/lib/CAPI/Dialects.cpp
index 680a50f977..7f69cdb92c 100644
--- a/lib/CAPI/Dialects.cpp
+++ b/lib/CAPI/Dialects.cpp
@@ -25,12 +25,12 @@ MLIR_DEFINE_CAPI_DIALECT_REGISTRATION(XLLVM, xllvm, xilinx::xllvm::XLLVMDialect)
 //===---------------------------------------------------------------------===//
 
 bool aieTypeIsObjectFifoType(MlirType type) {
-  return unwrap(type).isa<xilinx::AIE::AIEObjectFifoType>();
+  return llvm::isa<xilinx::AIE::AIEObjectFifoType>(unwrap(type));
 }
 
 MlirType aieObjectFifoTypeGet(MlirType type) {
   return wrap(xilinx::AIE::AIEObjectFifoType::get(
-      unwrap(type).cast<mlir::MemRefType>()));
+      llvm::cast<mlir::MemRefType>(unwrap(type))));
 }
 
 //===---------------------------------------------------------------------===//
@@ -38,10 +38,10 @@ MlirType aieObjectFifoTypeGet(MlirType type) {
 //===---------------------------------------------------------------------===//
 
 bool aieTypeIsObjectFifoSubviewType(MlirType type) {
-  return unwrap(type).isa<xilinx::AIE::AIEObjectFifoSubviewType>();
+  return llvm::isa<xilinx::AIE::AIEObjectFifoSubviewType>(unwrap(type));
 }
 
 MlirType aieObjectFifoSubviewTypeGet(MlirType type) {
   return wrap(xilinx::AIE::AIEObjectFifoSubviewType::get(
-      unwrap(type).cast<mlir::MemRefType>()));
+      llvm::cast<mlir::MemRefType>(unwrap(type))));
 }
diff --git a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp
index 0e3943e8bf..2d4c4ae32a 100644
--- a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp
+++ b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp
@@ -416,7 +416,7 @@ class MulElemOpConversion
     unsigned lhsBitWidth = lhsScaTy.getIntOrFloatBitWidth();
 
     // Integer types
-    if (lhsScaTy.isa<IntegerType>()) {
+    if (llvm::isa<IntegerType>(lhsScaTy)) {
       if (lhsBitWidth == 8) {
         return {DecodedMulElemOp::Kind::I8_I8_I32_32x1x2x1,
                 aiev2_mul_mac_compute_control(
@@ -842,7 +842,7 @@ class SRSOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::SRSOp> {
     int resultVectorSize = resultBitWidth * resultLanes;
 
     // Integer types
-    if (resultScaTy.isa<IntegerType>()) {
+    if (llvm::isa<IntegerType>(resultScaTy)) {
       // create constant for sign
       auto signCst = rewriter.create<LLVM::ConstantOp>(
           loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
@@ -1251,7 +1251,7 @@ class BroadcastScalarOpConversion
     unsigned resultBitWidth = resultScaTy.getIntOrFloatBitWidth();
 
     // Integer types
-    if (resultScaTy.isa<IntegerType>()) {
+    if (llvm::isa<IntegerType>(resultScaTy)) {
       Value src = adaptor.getSource();
       Type srcType = src.getType();
       unsigned srcBitWidth = srcType.getIntOrFloatBitWidth();
@@ -1324,7 +1324,7 @@ class ShiftOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::ShiftOp> {
     Value shiftOp = nullptr;
     SmallVector<Value> operands(
         {adaptor.getLhs(), adaptor.getRhs(), stepCst, adaptor.getShift()});
-    if (resultScaTy.isa<IntegerType>()) {
+    if (llvm::isa<IntegerType>(resultScaTy)) {
       // Integer types
       shiftOp = rewriter.create<xllvm::VectorShiftI512I512IntrOp>(
           loc, VectorType::get({16}, rewriter.getI32Type()),
diff --git a/lib/Dialect/AIE/IR/AIEDialect.cpp b/lib/Dialect/AIE/IR/AIEDialect.cpp
index a9e80b44b1..04a5d7df5a 100644
--- a/lib/Dialect/AIE/IR/AIEDialect.cpp
+++ b/lib/Dialect/AIE/IR/AIEDialect.cpp
@@ -275,7 +275,7 @@ static OptionalParseResult aieTypeParser(DialectAsmParser &parser,
       return failure();
 
     // Check that the type is a MemRef type.
-    if (!elementType.isa<MemRefType>()) {
+    if (!llvm::isa<MemRefType>(elementType)) {
       parser.emitError(typeLoc, "element type for an objectFifo must be "
                                 "a MemRefType, got: ")
           << elementType;
@@ -297,7 +297,7 @@ static OptionalParseResult aieTypeParser(DialectAsmParser &parser,
       return failure();
 
     // Check that the type is a MemRefType.
-    if (!elementType.isa<MemRefType>()) {
+    if (!llvm::isa<MemRefType>(elementType)) {
       parser.emitError(typeLoc, "element type for a subview must be "
                                 "a MemRefType, got: ")
           << elementType;
@@ -340,14 +340,14 @@ Type AIEDialect::parseType(DialectAsmParser &parser) const {
 
 /// Print an instance of a type registered to the AIE dialect.
 void AIEDialect::printType(Type type, DialectAsmPrinter &printer) const {
-  if (type.isa<AIEObjectFifoType>()) {
-    auto objectFifoType = type.cast<AIEObjectFifoType>();
+  if (llvm::isa<AIEObjectFifoType>(type)) {
+    auto objectFifoType = llvm::cast<AIEObjectFifoType>(type);
     printer << "objectfifo<";
     printer << objectFifoType.getElementType();
     printer << '>';
 
-  } else if (type.isa<AIEObjectFifoSubviewType>()) {
-    auto subviewType = type.cast<AIEObjectFifoSubviewType>();
+  } else if (llvm::isa<AIEObjectFifoSubviewType>(type)) {
+    auto subviewType = llvm::cast<AIEObjectFifoSubviewType>(type);
     printer << "objectfifosubview<";
     printer << subviewType.getElementType();
     printer << '>';
@@ -561,7 +561,7 @@ LogicalResult ObjectFifoLinkOp::verify() {
   if (isJoin()) {
     ObjectFifoCreateOp fifoOut = getOutputObjectFifos()[0];
     auto elemType =
-        fifoOut.getElemType().cast<AIEObjectFifoType>().getElementType();
+        llvm::cast<AIEObjectFifoType>(fifoOut.getElemType()).getElementType();
     int64_t outputSize = 1;
     for (auto dim : elemType.getShape())
       outputSize *= dim;
@@ -569,7 +569,7 @@ LogicalResult ObjectFifoLinkOp::verify() {
     int inputSize = 0;
     for (auto fifoIn : getInputObjectFifos()) {
       auto elemType =
-          fifoIn.getElemType().cast<AIEObjectFifoType>().getElementType();
+          llvm::cast<AIEObjectFifoType>(fifoIn.getElemType()).getElementType();
       int64_t nextInputSize = 1;
       for (int64_t dim : elemType.getShape())
         nextInputSize *= dim;
@@ -592,7 +592,7 @@ LogicalResult ObjectFifoLinkOp::verify() {
     }
 
     auto elemType =
-        fifoIn.getElemType().cast<AIEObjectFifoType>().getElementType();
+        llvm::cast<AIEObjectFifoType>(fifoIn.getElemType()).getElementType();
     int64_t inputSize = 1;
     for (auto dim : elemType.getShape())
       inputSize *= dim;
@@ -611,7 +611,7 @@ LogicalResult ObjectFifoLinkOp::verify() {
       }
 
       auto elemType =
-          fifoOut.getElemType().cast<AIEObjectFifoType>().getElementType();
+          llvm::cast<AIEObjectFifoType>(fifoOut.getElemType()).getElementType();
       int64_t nextOutputSize = 1;
       for (int64_t dim : elemType.getShape())
         nextOutputSize *= dim;
@@ -744,9 +744,11 @@ LogicalResult ObjectFifoAcquireOp::verify() {
   }
 
   auto objFifoElem =
-      getObjectFifo().getElemType().cast<AIEObjectFifoType>().getElementType();
+      llvm::cast<AIEObjectFifoType>(getObjectFifo().getElemType())
+          .getElementType();
   auto objFifoSubviewElem =
-      getResult().getType().cast<AIEObjectFifoSubviewType>().getElementType();
+      llvm::cast<AIEObjectFifoSubviewType>(getResult().getType())
+          .getElementType();
   if (objFifoElem != objFifoSubviewElem)
     return emitOpError(
         "ObjectFifo element and ObjectFifoSubview element must match.\n");
@@ -1275,7 +1277,7 @@ TileOp CoreOp::getTileOp() { return cast<TileOp>(getTile().getDefiningOp()); }
 //===----------------------------------------------------------------------===//
 
 int64_t BufferOp::getAllocationSize() {
-  auto type = getType().cast<MemRefType>();
+  auto type = llvm::cast<MemRefType>(getType());
   return type.getNumElements() * type.getElementTypeBitWidth() / 8;
 }
 
diff --git a/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp b/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp
index 4b70adca03..7c1c079be6 100644
--- a/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp
+++ b/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp
@@ -395,7 +395,7 @@ struct AIEBufferToStandard : OpConversionPattern<BufferOp> {
   matchAndRewrite(BufferOp buffer, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.setInsertionPointToStart(module.getBody());
-    auto t = buffer.getType().cast<MemRefType>();
+    auto t = llvm::cast<MemRefType>(buffer.getType());
     int col = llvm::cast<TileOp>(buffer.getTile().getDefiningOp()).getCol();
     int row = llvm::cast<TileOp>(buffer.getTile().getDefiningOp()).getRow();
     auto symName = buffer.name().getValue();
diff --git a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp
index b9c1a522f8..806275a8e9 100644
--- a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp
+++ b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp
@@ -312,8 +312,8 @@ struct AIEObjectFifoStatefulTransformPass
       return;
 
     std::vector<BufferOp> buffers;
-    auto fifo = op.getElemType().cast<AIEObjectFifoType>();
-    auto elemType = fifo.getElementType().cast<MemRefType>();
+    auto fifo = llvm::cast<AIEObjectFifoType>(op.getElemType());
+    auto elemType = llvm::cast<MemRefType>(fifo.getElementType());
     int numElem = op.size();
     int of_elem_index = 0; // used to give objectFifo elements a symbolic name
 
@@ -337,16 +337,14 @@ struct AIEObjectFifoStatefulTransformPass
         if (op.name() != fifoIn.name())
           return;
       } else {
-        auto fifoInType = linkOp->getInputObjectFifos()[0]
-                              .getElemType()
-                              .cast<AIEObjectFifoType>();
-        auto elemInType = fifoInType.getElementType().cast<MemRefType>();
+        auto fifoInType = llvm::cast<AIEObjectFifoType>(
+            linkOp->getInputObjectFifos()[0].getElemType());
+        auto elemInType = llvm::cast<MemRefType>(fifoInType.getElementType());
         int inSize = elemInType.getNumElements();
 
-        auto fifoOutType = linkOp->getOutputObjectFifos()[0]
-                               .getElemType()
-                               .cast<AIEObjectFifoType>();
-        auto elemOutType = fifoOutType.getElementType().cast<MemRefType>();
+        auto fifoOutType = llvm::cast<AIEObjectFifoType>(
+            linkOp->getOutputObjectFifos()[0].getElemType());
+        auto elemOutType = llvm::cast<MemRefType>(fifoOutType.getElementType());
 
         if (int outSize = elemOutType.getNumElements(); inSize >= outSize) {
           if (op.name() != fifoIn.name())
@@ -492,8 +490,8 @@ struct AIEObjectFifoStatefulTransformPass
     int acqNum = 1;
     int relNum = 1;
 
-    auto fifo = op.getElemType().cast<AIEObjectFifoType>();
-    auto elemType = fifo.getElementType().cast<MemRefType>();
+    auto fifo = llvm::cast<AIEObjectFifoType>(op.getElemType());
+    auto elemType = llvm::cast<MemRefType>(fifo.getElementType());
     int len = elemType.getNumElements();
 
     // search for the buffers/locks (based on if this objFifo has a link)
@@ -648,8 +646,8 @@ struct AIEObjectFifoStatefulTransformPass
     if (numBlocks == 0)
       return;
 
-    auto fifo = op.getElemType().cast<AIEObjectFifoType>();
-    auto elemType = fifo.getElementType().cast<MemRefType>();
+    auto fifo = llvm::cast<AIEObjectFifoType>(op.getElemType());
+    auto elemType = llvm::cast<MemRefType>(fifo.getElementType());
     int lenOut = elemType.getNumElements();
     int acqNum = 1;
     int relNum = 1;
@@ -672,8 +670,9 @@ struct AIEObjectFifoStatefulTransformPass
             relNum = linkOp->getFifoIns().size();
           } else {
             for (auto fifoIn : linkOp->getInputObjectFifos()) {
-              auto fifoType = fifoIn.getElemType().cast<AIEObjectFifoType>();
-              auto elemType = fifoType.getElementType().cast<MemRefType>();
+              auto fifoType =
+                  llvm::cast<AIEObjectFifoType>(fifoIn.getElemType());
+              auto elemType = llvm::cast<MemRefType>(fifoType.getElementType());
               if (fifoIn.name() == op.name())
                 break;
               extraOffset += elemType.getNumElements();
@@ -687,8 +686,9 @@ struct AIEObjectFifoStatefulTransformPass
             relNum = linkOp->getFifoOuts().size();
           } else {
             for (auto fifoOut : linkOp->getOutputObjectFifos()) {
-              auto fifoType = fifoOut.getElemType().cast<AIEObjectFifoType>();
-              auto elemType = fifoType.getElementType().cast<MemRefType>();
+              auto fifoType =
+                  llvm::cast<AIEObjectFifoType>(fifoOut.getElemType());
+              auto elemType = llvm::cast<MemRefType>(fifoType.getElementType());
               if (fifoOut.name() == op.name())
                 break;
               extraOffset += elemType.getNumElements();
@@ -696,9 +696,10 @@ struct AIEObjectFifoStatefulTransformPass
           }
         } else {
           if (target != op) {
-            auto targetFifo = target.getElemType().cast<AIEObjectFifoType>();
+            auto targetFifo =
+                llvm::cast<AIEObjectFifoType>(target.getElemType());
             auto targetElemType =
-                targetFifo.getElementType().cast<MemRefType>();
+                llvm::cast<MemRefType>(targetFifo.getElementType());
             lenOut = targetElemType.getNumElements();
           }
         }
@@ -1225,7 +1226,7 @@ struct AIEObjectFifoStatefulTransformPass
         }
 
         builder.setInsertionPointAfter(createOp);
-        auto datatype = createOp.getElemType().cast<AIEObjectFifoType>();
+        auto datatype = llvm::cast<AIEObjectFifoType>(createOp.getElemType());
         auto consumerObjFifoSize =
             builder.getIntegerAttr(builder.getI32Type(), consumerDepth);
         // rename and replace split objectFifo
@@ -1596,8 +1597,8 @@ struct AIEObjectFifoStatefulTransformPass
       auto sym_name = createOp.getName();
       createOp->setAttr(SymbolTable::getSymbolAttrName(),
                         builder.getStringAttr("__erase_" + sym_name));
-      auto memrefType =
-          createOp.getElemType().cast<AIEObjectFifoType>().getElementType();
+      auto memrefType = llvm::cast<AIEObjectFifoType>(createOp.getElemType())
+                            .getElementType();
       builder.create<memref::GlobalOp>(builder.getUnknownLoc(), sym_name,
                                        builder.getStringAttr("public"),
                                        memrefType, nullptr, false, nullptr);
diff --git a/lib/Dialect/AIEVec/IR/AIEVecOps.cpp b/lib/Dialect/AIEVec/IR/AIEVecOps.cpp
index 07714b271b..4799207b8f 100644
--- a/lib/Dialect/AIEVec/IR/AIEVecOps.cpp
+++ b/lib/Dialect/AIEVec/IR/AIEVecOps.cpp
@@ -18,6 +18,7 @@
 #include "mlir/IR/TypeUtilities.h"
 #include "mlir/Transforms/FoldUtils.h"
 
+using namespace llvm;
 using namespace mlir;
 using namespace xilinx;
 using namespace xilinx::aievec;
@@ -281,10 +282,10 @@ LogicalResult SRSOp::verify() {
   unsigned stypeWidth = stype.getIntOrFloatBitWidth();
   unsigned atypeWidth = atype.getIntOrFloatBitWidth();
 
-  if (atype.isa<IntegerType>() && stypeWidth >= atypeWidth)
+  if (isa<IntegerType>(atype) && stypeWidth >= atypeWidth)
     return emitError("the element type of source accumulator must be "
                      "wider than that of the result vector");
-  else if (atype.isa<FloatType>() && stypeWidth != 16 &&
+  else if (isa<FloatType>(atype) && stypeWidth != 16 &&
            stypeWidth != atypeWidth)
     return emitError("the element type of source accumulator must be "
                      "same as the result vector");
@@ -345,7 +346,7 @@ OpFoldResult UPSOp::fold(FoldAdaptor adaptor) {
   auto srcDefOp = getSource().getDefiningOp();
   if (!srcDefOp)
     return nullptr;
-  auto srsOp = dyn_cast<SRSOp>(srcDefOp);
+  auto srsOp = llvm::dyn_cast<SRSOp>(srcDefOp);
   if (!srsOp)
     return nullptr;
   return srsOp.getSource();
@@ -652,13 +653,13 @@ void aievec::FMAOp::print(OpAsmPrinter &p) {
 template <typename T>
 LogicalResult verifyMulFMAOp(T op) {
   // Verify the types
-  auto lhsType = op.getLhs().getType().template dyn_cast<VectorType>();
-  auto rhsType = op.getRhs().getType().template dyn_cast<VectorType>();
+  auto lhsType = llvm::dyn_cast<VectorType>(op.getLhs().getType());
+  auto rhsType = llvm::dyn_cast<VectorType>(op.getRhs().getType());
 
   if (!lhsType || !rhsType)
     return op.emitError("requires vector type");
 
-  auto resultType = op.getResult().getType().template dyn_cast<VectorType>();
+  auto resultType = llvm::dyn_cast<VectorType>(op.getResult().getType());
   if (!resultType)
     return op.emitError("requires vector type");
 
@@ -694,15 +695,15 @@ LogicalResult verifyMulFMAOp(T op) {
                         "operand vectors must match");
 
   // The datatype of accumulator must always be greater width
-  if (atype.isa<IntegerType>()) {
-    if (!ltype.isa<IntegerType>())
+  if (isa<IntegerType>(atype)) {
+    if (!isa<IntegerType>(ltype))
       return op.emitError("Integer result must have integer operands");
 
     if (ltypeWidth >= atypeWidth || rtypeWidth >= atypeWidth)
       return op.emitError("the element type of accumulator must have "
                           "wider width than that of the operand vectors");
-  } else if (atype.isa<FloatType>()) {
-    if (!ltype.isa<FloatType>())
+  } else if (isa<FloatType>(atype)) {
+    if (!isa<FloatType>(ltype))
       return op.emitError("Floating point result must have "
                           "floating point operands");
 
@@ -851,13 +852,13 @@ void aievec::FMAElemOp::print(OpAsmPrinter &p) {
 template <typename T>
 LogicalResult verifyMulFMAElemOp(T op) {
   // Verify the types
-  auto lhsType = op.getLhs().getType().template dyn_cast<VectorType>();
-  auto rhsType = op.getRhs().getType().template dyn_cast<VectorType>();
+  auto lhsType = llvm::dyn_cast<VectorType>(op.getLhs().getType());
+  auto rhsType = llvm::dyn_cast<VectorType>(op.getRhs().getType());
 
   if (!lhsType || !rhsType)
     return op.emitError("requires vector type");
 
-  auto resultType = op.getResult().getType().template dyn_cast<VectorType>();
+  auto resultType = llvm::dyn_cast<VectorType>(op.getResult().getType());
 
   if (!resultType)
     return op.emitError("requires vector type");
@@ -887,15 +888,15 @@ LogicalResult verifyMulFMAElemOp(T op) {
                         "operand vectors must match");
 
   // The integer datatype of accumulator must always be greater width
-  if (atype.isa<IntegerType>()) {
-    if (!ltype.isa<IntegerType>())
+  if (isa<IntegerType>(atype)) {
+    if (!isa<IntegerType>(ltype))
       return op.emitError("Integer result must have integer operands");
 
     if (ltypeWidth >= atypeWidth || rtypeWidth >= atypeWidth)
       return op.emitError("the element type of accumulator must have "
                           "wider width than that of the operand vectors");
-  } else if (atype.isa<FloatType>()) {
-    if (!ltype.isa<FloatType>())
+  } else if (isa<FloatType>(atype)) {
+    if (!isa<FloatType>(ltype))
       return op.emitError("Floating point result must have "
                           "floating point operands");
   }
@@ -1016,9 +1017,9 @@ void aievec::SubOp::print(OpAsmPrinter &p) {
 template <typename T>
 LogicalResult verifyAddSubOp(T op) {
   // Verify the types
-  auto resultType = op.getResult().getType().template dyn_cast<VectorType>();
-  auto lhsType = op.getLhs().getType().template dyn_cast<VectorType>();
-  auto rhsType = op.getRhs().getType().template dyn_cast<VectorType>();
+  auto resultType = llvm::dyn_cast<VectorType>(op.getResult().getType());
+  auto lhsType = llvm::dyn_cast<VectorType>(op.getLhs().getType());
+  auto rhsType = llvm::dyn_cast<VectorType>(op.getRhs().getType());
 
   if (!lhsType || !rhsType || !resultType)
     return op.emitError("requires vector type");
@@ -1191,7 +1192,7 @@ ConcatOp::inferReturnTypes(MLIRContext *, std::optional<Location>,
   }
   inferredReturnTypes.push_back(VectorType::get(
       {totalLength},
-      srcs[0].getType().dyn_cast<VectorType>().getElementType()));
+      llvm::dyn_cast<VectorType>(srcs[0].getType()).getElementType()));
   return success();
 }
 
@@ -1418,8 +1419,8 @@ void UnpackOp::print(OpAsmPrinter &p) { printPackUnpackOp<UnpackOp>(p, *this); }
 template <typename T>
 LogicalResult verifyPackUnpackOp(T op) {
   // Verify the types
-  auto sourceType = op.getSource().getType().template dyn_cast<VectorType>();
-  auto resultType = op.getResult().getType().template dyn_cast<VectorType>();
+  auto sourceType = llvm::dyn_cast<VectorType>(op.getSource().getType());
+  auto resultType = llvm::dyn_cast<VectorType>(op.getResult().getType());
   if (!sourceType || !resultType)
     return op.emitError("requires vector type");
 
@@ -1727,8 +1728,8 @@ void aievec::FMAConvOp::print(OpAsmPrinter &p) {
 template <typename T>
 LogicalResult verifyMulFMAConvOp(T op) {
   // Verify the types
-  auto lhsType = op.getLhs().getType().template dyn_cast<VectorType>();
-  auto rhsType = op.getRhs().getType().template dyn_cast<VectorType>();
+  auto lhsType = llvm::dyn_cast<VectorType>(op.getLhs().getType());
+  auto rhsType = llvm::dyn_cast<VectorType>(op.getRhs().getType());
 
   if (!lhsType || !rhsType)
     return op.emitError("requires vector type");
@@ -1740,7 +1741,7 @@ LogicalResult verifyMulFMAConvOp(T op) {
     return op.emitError(
         "M and N should be larger than 0 and 2*M should be no less than M+N-1");
 
-  auto resultType = op.getResult().getType().template dyn_cast<VectorType>();
+  auto resultType = llvm::dyn_cast<VectorType>(op.getResult().getType());
 
   if (!resultType)
     return op.emitError("requires vector type");
@@ -1756,8 +1757,8 @@ LogicalResult verifyMulFMAConvOp(T op) {
     return op.emitError("The element type of lhs and rhs "
                         "operand vectors must match");
 
-  if (!ltype.isa<IntegerType>() || !rtype.isa<IntegerType>() ||
-      !atype.isa<IntegerType>()) {
+  if (!isa<IntegerType>(ltype) || !isa<IntegerType>(rtype) ||
+      !isa<IntegerType>(atype)) {
     return op.emitError("requires integer type");
   }
 
diff --git a/lib/Dialect/AIEVec/Transforms/AIEVecOptimizations.cpp b/lib/Dialect/AIEVec/Transforms/AIEVecOptimizations.cpp
index a1bf38b169..db4b5c6150 100644
--- a/lib/Dialect/AIEVec/Transforms/AIEVecOptimizations.cpp
+++ b/lib/Dialect/AIEVec/Transforms/AIEVecOptimizations.cpp
@@ -30,6 +30,7 @@
 
 #define DEBUG_TYPE "aievec-optimize"
 
+using namespace llvm;
 using namespace mlir;
 using namespace arith;
 using namespace vector;
@@ -60,7 +61,7 @@ static bool canFoldAIEShiftAndBroadcast(aievec::BroadcastOp op,
   if (!shiftOp)
     return false;
 
-  VectorType vType = shiftOp->getResult(0).getType().cast<VectorType>();
+  VectorType vType = cast<VectorType>(shiftOp->getResult(0).getType());
   int32_t elemSize = getElementSizeInBits(vType);
   auto constOp = cast<arith::ConstantOp>(shiftOp.getShift().getDefiningOp());
   int32_t shiftBytes = cast<IntegerAttr>(constOp.getValue()).getInt();
@@ -184,7 +185,7 @@ struct FoldAIEShiftAndBroadcast
       return failure();
     }
 
-    VectorType resultType = bcastOp.getResult().getType().cast<VectorType>();
+    VectorType resultType = cast<VectorType>(bcastOp.getResult().getType());
 
     rewriter.replaceOpWithNewOp<aievec::BroadcastOp>(bcastOp, resultType,
                                                      shiftOp.getLhs(), idx);
diff --git a/lib/Dialect/AIEVec/Transforms/AIEVectorize.cpp b/lib/Dialect/AIEVec/Transforms/AIEVectorize.cpp
index dbe9022288..19da8bf6f2 100644
--- a/lib/Dialect/AIEVec/Transforms/AIEVectorize.cpp
+++ b/lib/Dialect/AIEVec/Transforms/AIEVectorize.cpp
@@ -30,6 +30,7 @@
 
 #include "llvm/ADT/SmallSet.h"
 
+using namespace llvm;
 using namespace mlir;
 using namespace arith;
 using namespace vector;
@@ -58,23 +59,23 @@ struct VectState {
   SmallVector<IntervalReuse *, 16> reuseIntervals;
   // Map from a transfer_read operation to the IntervalReuse object it belongs
   // to.
-  DenseMap<Operation *, IntervalReuse *> opToIntervalMap;
+  mlir::DenseMap<Operation *, IntervalReuse *> opToIntervalMap;
   // Map from a transfer_read operation to its linearized access expression.
   // Linearized expression for access A[i][j], where A is of dimensionality MxN
   // is (i*N+j). We assume that the innermost dimension is the vectorized
   // dimension.
-  DenseMap<Operation *, AffineExpr> linearizedAccess;
+  mlir::DenseMap<Operation *, AffineExpr> linearizedAccess;
   // A map from an index (of array access) to an expr dim map (e.g., i->d0). We
   // need this to create the correct linearized expressions for all the array
   // accesses in the function.
-  DenseMap<Value, AffineExpr> indexToExprDimMap;
+  mlir::DenseMap<Value, AffineExpr> indexToExprDimMap;
   // For each transfer_read operation, a map from its container basic block to
   // the enclosing for/while loops. This helps us identify two instructions
   // that are nested together, even if they belong to different basic blocks.
-  DenseMap<Block *, SmallVector<Operation *, 8>> blockToEnclosingLoops;
+  mlir::DenseMap<Block *, SmallVector<Operation *, 8>> blockToEnclosingLoops;
   // This is specific to 8x8 scheme. For an 8x8 scheme, every mul/fma is
   // replaced by two mul/fmas in AIE dialect. So we keep track of the pair.
-  DenseMap<Operation *, Operation *> pairedOp;
+  mlir::DenseMap<Operation *, Operation *> pairedOp;
   // If we fuse a representative mul/fma op with another fma op to exploit the
   // column topology of the AIE intrinsic, then cache, for the representative
   // op, the compile-time constant access distance between their two operands.
@@ -82,9 +83,9 @@ struct VectState {
   // between the first(second) operands of the representative op and the the
   // fused op(s). This access distance will be used to compute the xstep/zstep
   // attribute.
-  DenseMap<Operation *, std::pair<int32_t, int32_t>> opToColOffsets;
+  mlir::DenseMap<Operation *, std::pair<int32_t, int32_t>> opToColOffsets;
   // Map from the sext op to the def op of the sext operand.
-  DenseMap<Operation *, Operation *> sextTruncDefMap;
+  mlir::DenseMap<Operation *, Operation *> sextTruncDefMap;
   // A set of operations that are msc (fmsub) ops. We do not differentiate
   // between mac and msc ops at vector dialect level. The only op in vector
   // dialect is just FMA op.
@@ -180,7 +181,7 @@ static AIEVecAttributes getVectorStats(VectorType type) {
 
 // Get the vector stats for an operation's result.
 static AIEVecAttributes getResultVecStats(Operation *op, unsigned idx = 0) {
-  auto vtype = op->getResult(idx).getType().cast<VectorType>();
+  auto vtype = cast<VectorType>(op->getResult(idx).getType());
   return getVectorStats(vtype);
 }
 
@@ -196,7 +197,7 @@ static AIEVecAttributes getOperandVecStats(Operation *op, VectState *state,
                                            unsigned idx = 0) {
   assert(op->getNumOperands() > idx);
   Operation *defOp = getOperandDefOp(state, op, idx);
-  auto vtype = defOp->getResult(0).getType().cast<VectorType>();
+  auto vtype = cast<VectorType>(defOp->getResult(0).getType());
   auto ret = getVectorStats(vtype);
   // if the defining op is a transfer read, get the extent read from source
   if (auto readOp = dyn_cast<TransferReadOp>(defOp)) {
@@ -219,12 +220,12 @@ static std::pair<int32_t, int32_t> getNumRowsAndCols(Operation *op,
   Operation *right = getOperandDefOp(state, op, 1);
 
   // Get the number of lanes
-  auto vtype = op->getResult(0).getType().cast<VectorType>();
+  auto vtype = cast<VectorType>(op->getResult(0).getType());
   int32_t lanes = getVectorLaneSize(vtype);
 
   // Get the data sizes for left and right operands
-  auto ltype = left->getResult(0).getType().cast<VectorType>();
-  auto rtype = right->getResult(0).getType().cast<VectorType>();
+  auto ltype = cast<VectorType>(left->getResult(0).getType());
+  auto rtype = cast<VectorType>(right->getResult(0).getType());
   int32_t lsize = getElementSizeInBits(ltype);
   int32_t rsize = getElementSizeInBits(rtype);
 
@@ -312,9 +313,9 @@ static bool isSimpleVectIntrinsic(Operation *Op, VectState *state) {
                      lstat.elementType == rstat.elementType &&
                      vstat.elementType == rstat.elementType;
   bool noSplat = !lstat.isSplat && !rstat.isSplat;
-  bool noFloat = !vstat.elementType.isa<FloatType>() &&
-                 !lstat.elementType.isa<FloatType>() &&
-                 !rstat.elementType.isa<FloatType>();
+  bool noFloat = !isa<FloatType>(vstat.elementType) &&
+                 !isa<FloatType>(lstat.elementType) &&
+                 !isa<FloatType>(rstat.elementType);
 
   return sizeMatches && noSplat && (isSubOrAddOp || noFloat);
 }
@@ -334,15 +335,15 @@ static bool isWellFormedVectorOp(Operation *Op) {
 
   // Check 1. all the operands and results must be vector types
   for (auto val : operandsAndResults) {
-    if (!val.getType().isa<VectorType>())
+    if (!isa<VectorType>(val.getType()))
       return false;
   }
 
-  auto refType = operandsAndResults.back().getType().cast<VectorType>();
+  auto refType = cast<VectorType>(operandsAndResults.back().getType());
   Type scalarType = refType.getElementType();
   unsigned refSize = getVectorLaneSize(refType);
   for (auto val : operandsAndResults) {
-    auto vtype = val.getType().cast<VectorType>();
+    auto vtype = cast<VectorType>(val.getType());
     // Check 2. All the vector sizes must be same
     if (refSize != getVectorLaneSize(vtype))
       return false;
@@ -361,17 +362,11 @@ static bool writesToAccumulator(Operation *op) {
   if (!isAIEOp(op))
     return false;
   if (auto mulOp = dyn_cast<aievec::MulOp>(op))
-    return mulOp.getResult()
-        .getType()
-        .cast<VectorType>()
-        .getElementType()
-        .isa<IntegerType>();
+    return isa<IntegerType>(
+        cast<VectorType>(mulOp.getResult().getType()).getElementType());
   if (auto fmaOp = dyn_cast<aievec::FMAOp>(op))
-    return fmaOp.getResult()
-        .getType()
-        .cast<VectorType>()
-        .getElementType()
-        .isa<IntegerType>();
+    return isa<IntegerType>(
+        cast<VectorType>(fmaOp.getResult().getType()).getElementType());
 
   return isa<aievec::FMAElemOp, aievec::MulElemOp, aievec::FMAConvOp,
              aievec::MulConvOp, aievec::UPSOp>(op);
@@ -431,7 +426,7 @@ static AffineExpr constructLinearizedAffineExpr(TransferReadOp readOp,
 
   SmallVector<Value, 4> indices(readOp.getIndices().begin(),
                                 readOp.getIndices().end());
-  auto memRefType = readOp.getSource().getType().cast<MemRefType>();
+  auto memRefType = cast<MemRefType>(readOp.getSource().getType());
   MLIRContext *context = memRefType.getContext();
 
   SmallVector<AffineExpr, 8> exprVec;
@@ -452,7 +447,7 @@ static AffineExpr constructLinearizedAffineExpr(TransferReadOp readOp,
       // (i.e., loop index), we create a unique dim expr.
       for (auto index : apOf.getMapOperands()) {
         if (auto cIdx = index.getDefiningOp<arith::ConstantOp>()) {
-          auto idxVal = cIdx.getValue().cast<IntegerAttr>().getValue();
+          auto idxVal = cast<IntegerAttr>(cIdx.getValue()).getValue();
           unsigned idx = idxVal.getSExtValue();
           indexExprs.push_back(getAffineConstantExpr(idx, context));
         } else {
@@ -468,7 +463,7 @@ static AffineExpr constructLinearizedAffineExpr(TransferReadOp readOp,
     // If the index is an arith constant (e.g., A[3]), create an affine expr
     // from the constant value.
     else if (auto cOp = value.getDefiningOp<arith::ConstantOp>()) {
-      auto idxVal = cOp.getValue().cast<IntegerAttr>().getValue();
+      auto idxVal = cast<IntegerAttr>(cOp.getValue()).getValue();
       unsigned idx = idxVal.getSExtValue();
       exprVec.push_back(getAffineConstantExpr(idx, context));
     }
@@ -547,7 +542,7 @@ static aievec::SRSOp generateSRSOp(Value source, Type scalarType,
          "srs source should write to accumulator");
 
   // Get the number of lanes
-  unsigned lanes = getVectorLaneSize(accType.cast<VectorType>());
+  unsigned lanes = getVectorLaneSize(cast<VectorType>(accType));
   // Now generate the new vector type for the SRS intrinsic
   VectorType srsType = createVectorType(lanes, scalarType);
 
@@ -567,7 +562,7 @@ static aievec::UPSOp generateUPSOp(Value source, VectState *state,
                                    Location loc) {
   Type sourceType = source.getType();
   Type accType =
-      getVectorOpDestType(sourceType.cast<VectorType>(), state->aieml);
+      getVectorOpDestType(cast<VectorType>(sourceType), state->aieml);
   assert(!writesToAccumulator(source.getDefiningOp()) &&
          "ups source should not be accumulator");
 
@@ -582,7 +577,7 @@ static aievec::UPSOp generateUPSOp(Value source, VectState *state,
 // Generate and return a Broadcast op.
 static aievec::BroadcastOp generateBroadcastOp(Value source, int8_t idx,
                                                VectState *state, Location loc) {
-  auto type = source.getType().cast<VectorType>();
+  auto type = cast<VectorType>(source.getType());
   // Create a new Broadcast instruction
   auto broadcastOp =
       state->builder.create<aievec::BroadcastOp>(loc, type, source, idx);
@@ -597,11 +592,11 @@ static aievec::ConcatOp generateConcatOp(SmallVector<Value> &sources,
                                          VectorType concatType = nullptr) {
   assert(sources.size() > 1 && "must concat at least two vectors");
 
-  auto vecType = sources.back().getType().cast<VectorType>();
+  auto vecType = cast<VectorType>(sources.back().getType());
 
   assert([&] {
     for (auto source : sources) {
-      auto type = source.getType().cast<VectorType>();
+      auto type = cast<VectorType>(source.getType());
       if (type != vecType) {
         printf("sources of concat op not of same type\n");
         return false;
@@ -636,7 +631,7 @@ static aievec::SelectOp generateSelectOp(Value xbuff, AIEOpAttributes &opAttr,
   assert(opAttr.start.size() == opAttr.offset.size() &&
          opAttr.start.size() == 2);
 
-  auto xtype = xbuff.getType().cast<VectorType>();
+  auto xtype = cast<VectorType>(xbuff.getType());
   // Verify that lanes is <= xtype lanes
   assert(lanes <= getVectorLaneSize(xtype));
   // Create the result type
@@ -656,7 +651,7 @@ static aievec::SelectOp generateSelectOp(Value xbuff, AIEOpAttributes &opAttr,
 // output, and idx defines which part of source is extracted.
 static aievec::ExtOp generateExtOp(Value source, unsigned lanes, int8_t idx,
                                    VectState *state, Location loc) {
-  auto stype = source.getType().cast<VectorType>();
+  auto stype = cast<VectorType>(source.getType());
   // Verify that lanes*idx is <= stype lanes
   assert(lanes * (idx + 1) <= getVectorLaneSize(stype));
   // Create the result type
@@ -674,7 +669,7 @@ static aievec::ExtOp generateExtOp(Value source, unsigned lanes, int8_t idx,
 static aievec::PackOp generatePackOp(Value source, VectState *state,
                                      Location loc) {
   // Create the result type
-  auto stype = source.getType().cast<VectorType>();
+  auto stype = cast<VectorType>(source.getType());
   unsigned lanes = getVectorLaneSize(stype);
   Type i8Type = IntegerType::get(source.getContext(), 8);
   VectorType resultType = createVectorType(lanes, i8Type);
@@ -719,10 +714,10 @@ static aievec::SubOp generateSubOp(Operation *Op, AIEOpAttributes &opAttr,
 static aievec::ShiftOp generateShiftOp(Value lhs, Value rhs, int32_t shiftBytes,
                                        VectState *state, Location loc,
                                        VectorType resType = nullptr) {
-  auto vecType = rhs.getType().cast<VectorType>();
+  auto vecType = cast<VectorType>(rhs.getType());
 
   assert([&] {
-    auto type = lhs.getType().cast<VectorType>();
+    auto type = cast<VectorType>(lhs.getType());
     if (type != vecType) {
       printf("lhs and rhs do not have same type\n");
       return false;
@@ -747,7 +742,7 @@ static aievec::ShiftOp generateShiftOp(Value lhs, Value rhs, int32_t shiftBytes,
 static aievec::ShuffleOp generateShuffleOp(Value source, VectState *state,
                                            Location loc, unsigned mode,
                                            VectorType resType = nullptr) {
-  auto vecType = source.getType().cast<VectorType>();
+  auto vecType = cast<VectorType>(source.getType());
 
   if (!resType) {
     unsigned lanes = 512 / getElementSizeInBits(vecType);
@@ -778,9 +773,9 @@ static Operation *generateMulOrFMAConvOpForInt8(Operation *Op,
   Value rhs = state->sextTruncDefMap.count(Op->getOperand(0).getDefiningOp())
                   ? Op->getOperand(0).getDefiningOp()->getOperand(0)
                   : Op->getOperand(0);
-  auto vType = lhs.getType().cast<VectorType>();
+  auto vType = cast<VectorType>(lhs.getType());
   Type stype = vType.getElementType();
-  auto itype = stype.cast<IntegerType>();
+  auto itype = cast<IntegerType>(stype);
   unsigned width = itype.getWidth() <= 8 ? 32 : 64;
   int32_t M = 32;
   int32_t N = 8;
@@ -855,15 +850,12 @@ static Operation *generateFMAOp(vector::FMAOp fmaOp, AIEOpAttributes &opAttr,
 
   // We need to generate a UPS op for the integer and AIEML path if the
   // accumulator is coming from a vector register.
-  bool isInt = fmaOp.getLhs()
-                   .getType()
-                   .cast<VectorType>()
-                   .getElementType()
-                   .isa<IntegerType>();
+  bool isInt = isa<IntegerType>(
+      cast<VectorType>(fmaOp.getLhs().getType()).getElementType());
 
   Operation *xfmaOp;
   if (state->aieml &&
-      getVectorSizeInBits(rhs.getType().cast<VectorType>()) == 512) {
+      getVectorSizeInBits(cast<VectorType>(rhs.getType())) == 512) {
     if (!writesToAccumulator(acc.getDefiningOp())) {
       acc = generateUPSOp(acc, state, fmaOp->getLoc());
       LLVM_DEBUG(llvm::dbgs()
@@ -935,8 +927,8 @@ static Operation *generateMulOp(T mulOp, AIEOpAttributes &opAttr,
   assert(opAttr.start.size() == opAttr.offset.size() &&
          opAttr.start.size() == 2);
 
-  Type opType = getVectorOpDestType(mulOp.getType().template cast<VectorType>(),
-                                    state->aieml);
+  Type opType =
+      getVectorOpDestType(cast<VectorType>(mulOp.getType()), state->aieml);
 
   // If the lhs operand vector is not >= twice the rhs operand vector, then use
   // concat operator.
@@ -974,8 +966,8 @@ static Operation *generateMulOp(T mulOp, AIEOpAttributes &opAttr,
 // otherwise.
 static aievec::UPDOp
 generateUPDOp(TransferReadOp readOp,
-              DenseMap<std::tuple<IntervalReuse *, int32_t, int32_t>,
-                       std::pair<aievec::UPDOp, int8_t>> &memToUpdMap,
+              mlir::DenseMap<std::tuple<IntervalReuse *, int32_t, int32_t>,
+                             std::pair<aievec::UPDOp, int8_t>> &memToUpdMap,
               Region &region, VectState *state) {
   // Get the read access extent and interval of this read operation
   IntervalReuse *iv = state->getIntervalForOperation(readOp);
@@ -988,7 +980,7 @@ generateUPDOp(TransferReadOp readOp,
   // Create the upd vector type. To do so, we need the underlying element type.
   // We can divide the interval size by that to get the number of lanes in the
   // result vector of upd op.
-  auto vecType = readOp.getVector().getType().cast<VectorType>();
+  auto vecType = cast<VectorType>(readOp.getVector().getType());
   Type elementType = vecType.getElementType();
   int32_t elementSizeInBits = getElementSizeInBits(vecType);
   int intervalWidthInBytes = intervalWidth / elementSizeInBits;
@@ -1113,7 +1105,7 @@ static int32_t computeVecorizedLoopStepSize(Operation *op, VectState *state) {
     return 1;
 
   int32_t step = 0;
-  auto vectorType = readOp.getResult().getType().cast<VectorType>();
+  auto vectorType = cast<VectorType>(readOp.getResult().getType());
   SmallVector<Value, 4> indices(readOp.getIndices().begin(),
                                 readOp.getIndices().end());
   assert(vectorType && !indices.empty());
@@ -1166,7 +1158,7 @@ int32_t computeStartInAIEVec(Operation *op, VectState *state) {
   auto readOp = cast<TransferReadOp>(op);
 
   // Get the scalar element type's size in bits
-  auto vtype = readOp.getVector().getType().cast<VectorType>();
+  auto vtype = cast<VectorType>(readOp.getVector().getType());
   int32_t scalarSizeInBits = getElementSizeInBits(vtype);
 
   // Get the linearized access expr for this read
@@ -1279,8 +1271,8 @@ static bool canFuseMulAndAddOrSubIntoFMAOp(Operation *Op, VectState *state) {
          "Failed to find the three operands of the FMA op");
 
   // Check 5. All lhs, rhs, and acc must be vector types
-  if (!lhs.getType().isa<VectorType>() || !rhs.getType().isa<VectorType>() ||
-      !acc.getType().isa<VectorType>())
+  if (!isa<VectorType>(lhs.getType()) || !isa<VectorType>(rhs.getType()) ||
+      !isa<VectorType>(acc.getType()))
     return false;
 
   // Check 6. All the ops should belong to the same block, otherwise we might
@@ -1290,17 +1282,16 @@ static bool canFuseMulAndAddOrSubIntoFMAOp(Operation *Op, VectState *state) {
     return false;
 
   // Check 7. All the vector sizes must be same
-  auto lhsType = lhs.getType().cast<VectorType>();
-  auto rhsType = rhs.getType().cast<VectorType>();
+  auto lhsType = cast<VectorType>(lhs.getType());
+  auto rhsType = cast<VectorType>(rhs.getType());
   VectorType accType = state->sextTruncDefMap.count(
                            acc.getDefiningOp()->getOperand(0).getDefiningOp())
-                           ? acc.getDefiningOp()
-                                 ->getOperand(0)
-                                 .getDefiningOp()
-                                 ->getOperand(0)
-                                 .getType()
-                                 .cast<VectorType>()
-                           : acc.getType().cast<VectorType>();
+                           ? cast<VectorType>(acc.getDefiningOp()
+                                                  ->getOperand(0)
+                                                  .getDefiningOp()
+                                                  ->getOperand(0)
+                                                  .getType())
+                           : cast<VectorType>(acc.getType());
 
   unsigned lhsVecSize = getVectorLaneSize(lhsType);
   unsigned rhsVecSize = getVectorLaneSize(rhsType);
@@ -1955,8 +1946,8 @@ static void generateSchemeBasedMulOrFMAOp(Operation *Op, VectState *state) {
   Value rhs = state->sextTruncDefMap.count(Op->getOperand(1).getDefiningOp())
                   ? Op->getOperand(1).getDefiningOp()->getOperand(0)
                   : Op->getOperand(1);
-  int32_t xbits = getElementSizeInBits(lhs.getType().cast<VectorType>());
-  int32_t zbits = getElementSizeInBits(rhs.getType().cast<VectorType>());
+  int32_t xbits = getElementSizeInBits(cast<VectorType>(lhs.getType()));
+  int32_t zbits = getElementSizeInBits(cast<VectorType>(rhs.getType()));
   Scheme scheme(lanes, cols, xbits, zbits);
 
   // First check if this operation requires simple vector operation, and not an
@@ -2104,7 +2095,7 @@ static bool canFuseMulFMAOpsForInt16(Operation *Op) {
   auto curOp = cast<aievec::FMAOp>(Op);
 
   // Check 2. Element type should be int16
-  auto vType = Op->getOperand(1).getType().cast<VectorType>();
+  auto vType = cast<VectorType>(Op->getOperand(1).getType());
   Type stype = vType.getElementType();
   auto itype = llvm::dyn_cast<IntegerType>(stype);
 
@@ -2223,7 +2214,7 @@ static void fuseMulFMAOpsForInt16(Operation *Op, VectState *state) {
     zStart = stoi(static_cast<std::string>(defOp.getStart(1)));
   }
 
-  auto vType = Op->getOperand(1).getType().cast<VectorType>();
+  auto vType = cast<VectorType>(Op->getOperand(1).getType());
   int32_t shiftBytes = zStart * getElementSizeInBits(vType) / 8;
 
   auto defOp = mulOp ? mulOp : fmaOp;
@@ -2235,7 +2226,7 @@ static void fuseMulFMAOpsForInt16(Operation *Op, VectState *state) {
     concatRhs = generateShiftOp(concatRhs, concatRhs, shiftBytes, state, loc);
 
   Type stype = vType.getElementType();
-  auto itype = stype.cast<IntegerType>();
+  auto itype = cast<IntegerType>(stype);
   unsigned width = itype.getWidth() <= 8 ? 32 : 64;
   Type ctype = IntegerType::get(itype.getContext(), width);
   Type opType = VectorType::get(vType.getShape(), ctype);
@@ -2439,13 +2430,13 @@ static void insertUPDOpsInLoop(affine::AffineForOp forOp, VectState *state) {
   // should be loaded into the AIE vec, and the value indicates the UPD op
   // achieving that. The value also has an 8-bit field, whose first/second bit
   // is set if upd op idx=0/idx=1 is already created for this interval.
-  DenseMap<std::tuple<IntervalReuse *, int32_t, int32_t>,
-           std::pair<aievec::UPDOp, int8_t>>
+  mlir::DenseMap<std::tuple<IntervalReuse *, int32_t, int32_t>,
+                 std::pair<aievec::UPDOp, int8_t>>
       memToUpdMap;
   // A map from a read operation to its corresponding UPD operation. The idea
   // is that multiple read ops will derive from the same bigger vector
   // register.
-  DenseMap<Operation *, aievec::UPDOp> readOpToUpdMap;
+  mlir::DenseMap<Operation *, aievec::UPDOp> readOpToUpdMap;
   // Iterate over all the transfer_read ops within this loop
   Region &region = forOp.getRegion();
   for (TransferReadOp readOp : region.getOps<TransferReadOp>()) {
@@ -2488,7 +2479,7 @@ static void insertSRSOp(Operation *Op, VectState *state) {
 
   // Given an accumulator, one can use different srs intrinsic to generate
   // different output types. Create a map from SRS output type to the SRS op.
-  DenseMap<Type, aievec::SRSOp> typeToSRSOpMap;
+  mlir::DenseMap<Type, aievec::SRSOp> typeToSRSOpMap;
 
   // Set the insertion point for the AIE dialect SRS op
   state->builder.setInsertionPointAfter(Op);
@@ -2506,7 +2497,7 @@ static void insertSRSOp(Operation *Op, VectState *state) {
     MemRefType memRefType = nullptr;
     if (auto writeOp = dyn_cast<TransferWriteOp>(user)) {
       // Get the element type from the memref output
-      memRefType = writeOp.getSource().getType().cast<MemRefType>();
+      memRefType = cast<MemRefType>(writeOp.getSource().getType());
       scalarType = memRefType.getElementType();
     } else
       scalarType = getElementTypeOrSelf(*user->getResultTypes().begin());
@@ -2518,19 +2509,15 @@ static void insertSRSOp(Operation *Op, VectState *state) {
         // Generate an AIE-ML cast op for the case that result vector width less
         // or equal that source vector width
         if (state->aieml && memRefType &&
-            Op->getOperand(0)
-                    .getType()
-                    .cast<VectorType>()
+            cast<VectorType>(Op->getOperand(0).getType())
                     .getElementType()
                     .getIntOrFloatBitWidth() == 8 &&
-            Op->getResult(0)
-                    .getType()
-                    .cast<VectorType>()
+            cast<VectorType>(Op->getResult(0).getType())
                     .getElementType()
                     .getIntOrFloatBitWidth() ==
                 scalarType.getIntOrFloatBitWidth()) {
           unsigned lanes =
-              getVectorLaneSize(Op->getResult(0).getType().cast<VectorType>());
+              getVectorLaneSize(cast<VectorType>(Op->getResult(0).getType()));
           VectorType castType = createVectorType(lanes, scalarType);
           aievec::CastOp castOp = generateCastOp(Op->getResult(0), castType,
                                                  false, state, Op->getLoc());
@@ -2802,7 +2789,7 @@ static void computeReuse(TransferReadOp readOp, VectState *state) {
     }
   }
 
-  auto vecType = readOp.getVector().getType().cast<VectorType>();
+  auto vecType = cast<VectorType>(readOp.getVector().getType());
   if (state->aieml && (getVectorSizeInBits(vecType) == 512 ||
                        getElementSizeInBits(vecType) == 8)) {
     minVecSize *= 2;
@@ -2837,7 +2824,7 @@ static void computeReuse(TransferReadOp readOp, VectState *state) {
 }
 
 static LogicalResult isUnalignedLoad(TransferReadOp readOp, VectState *state) {
-  auto vectorType = readOp.getResult().getType().cast<VectorType>();
+  auto vectorType = cast<VectorType>(readOp.getResult().getType());
   unsigned lanes = getVectorLaneSize(vectorType);
 
   AffineExpr linearAccess = constructLinearizedAffineExpr(readOp, state);
@@ -2845,7 +2832,7 @@ static LogicalResult isUnalignedLoad(TransferReadOp readOp, VectState *state) {
     return success();
   }
 
-  auto memRefType = readOp.getSource().getType().cast<MemRefType>();
+  auto memRefType = cast<MemRefType>(readOp.getSource().getType());
   MLIRContext *context = memRefType.getContext();
   ArrayRef<int64_t> sizes = memRefType.getShape();
   int numDims = sizes.size();
diff --git a/lib/Dialect/AIEVec/Transforms/DynamicSizeNoImplicitBroadcast.cpp b/lib/Dialect/AIEVec/Transforms/DynamicSizeNoImplicitBroadcast.cpp
index 69ab7e4f83..7b750a67cd 100644
--- a/lib/Dialect/AIEVec/Transforms/DynamicSizeNoImplicitBroadcast.cpp
+++ b/lib/Dialect/AIEVec/Transforms/DynamicSizeNoImplicitBroadcast.cpp
@@ -27,6 +27,7 @@
 
 #define DEBUG_TYPE "dynamic-size-no-implicit-broadcast"
 
+using namespace llvm;
 using namespace mlir;
 using namespace xilinx;
 using namespace xilinx::aievec;
@@ -68,8 +69,7 @@ struct DynamicSizeNoImplicitBroadcastPattern : RewritePattern {
 
     // If ConstantOp is 1 for Integer/Index, replace cmpiOp as constant 0
     auto constantOp = cast<arith::ConstantOp>(rhsOp);
-    if (constantOp.getValue().cast<IntegerAttr>().getValue().getZExtValue() !=
-        1)
+    if (cast<IntegerAttr>(constantOp.getValue()).getValue().getZExtValue() != 1)
       return failure();
 
     // Check the DimOp's input is a dynamic dim from the given index
@@ -78,7 +78,7 @@ struct DynamicSizeNoImplicitBroadcastPattern : RewritePattern {
       return failure();
 
     auto index =
-        constIndexOp.getValue().cast<IntegerAttr>().getValue().getZExtValue();
+        cast<IntegerAttr>(constIndexOp.getValue()).getValue().getZExtValue();
     auto inputDimType = dyn_cast<ShapedType>(lhsOp->getOperand(0).getType());
     if (!inputDimType || !inputDimType.isDynamicDim(index))
       return failure();
diff --git a/lib/Dialect/AIEVec/Transforms/IntervalReuse.cpp b/lib/Dialect/AIEVec/Transforms/IntervalReuse.cpp
index 3d7023b60e..e36b2faf90 100644
--- a/lib/Dialect/AIEVec/Transforms/IntervalReuse.cpp
+++ b/lib/Dialect/AIEVec/Transforms/IntervalReuse.cpp
@@ -17,6 +17,7 @@
 
 #include "llvm/Support/Debug.h"
 
+using namespace llvm;
 using namespace mlir;
 using namespace xilinx::aievec;
 
@@ -25,8 +26,8 @@ using namespace xilinx::aievec;
 // Return true if the read operation is enclosed with the same loop nests as
 // the other read operations belonging to this IntervalReuse object.
 bool IntervalReuse::sameEnclosingLoops(
-    Operation *op,
-    DenseMap<Block *, SmallVector<Operation *, 8>> &blockToEnclosingLoops) {
+    Operation *op, mlir::DenseMap<Block *, SmallVector<Operation *, 8>>
+                       &blockToEnclosingLoops) {
   // Assert that there are some existing read operations in the interval
   assert(!extentMap.empty() &&
          "interval must have at least one read operation");
@@ -122,7 +123,8 @@ int32_t IntervalReuse::getIntervalWidth(Operation *op) {
 // If all these conditions are met, there is a potential data reuse.
 bool IntervalReuse::potentialReuse(
     vector::TransferReadOp readOp, AffineExpr invariantBase,
-    DenseMap<Block *, SmallVector<Operation *, 8>> &blockToEnclosingLoops) {
+    mlir::DenseMap<Block *, SmallVector<Operation *, 8>>
+        &blockToEnclosingLoops) {
   return sameMemRef(readOp.getSource()) &&
          sameInvariantIndices(invariantBase) &&
          sameEnclosingLoops(readOp, blockToEnclosingLoops);
@@ -136,7 +138,7 @@ bool IntervalReuse::potentialReuse(
 static std::pair<int32_t, int32_t>
 computeAccessExtent(vector::TransferReadOp readOp, int32_t offset,
                     int32_t loopStepSize, bool isSplat, unsigned minVecSize) {
-  VectorType vType = readOp.getResult().getType().cast<VectorType>();
+  VectorType vType = cast<VectorType>(readOp.getResult().getType());
   unsigned vecSize = getVectorLaneSize(vType);
   int32_t elementSizeInBits = getElementSizeInBits(vType);
   // Create chunks greater in size than minVecSize
@@ -163,8 +165,8 @@ computeAccessExtent(vector::TransferReadOp readOp, int32_t offset,
 // so align the access extents to at least 128-bit boundary.
 void IntervalReuse::insertInterval(
     vector::TransferReadOp readOp,
-    DenseMap<Operation *, IntervalReuse *> &opToIntervalMap, int32_t offset,
-    int32_t loopStepSize, bool isSplat, unsigned minVecSize) {
+    mlir::DenseMap<Operation *, IntervalReuse *> &opToIntervalMap,
+    int32_t offset, int32_t loopStepSize, bool isSplat, unsigned minVecSize) {
   // Get the vector-size-aligned lower and upper bounds for the vector read
   std::pair<int32_t, int32_t> bound =
       computeAccessExtent(readOp, offset, loopStepSize, isSplat, minVecSize);
diff --git a/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp b/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp
index 91bd39b652..9297ef9d0f 100644
--- a/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp
+++ b/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp
@@ -36,6 +36,7 @@
 
 #define DEBUG_TYPE "lower-vector-to-aievec"
 
+using namespace llvm;
 using namespace mlir;
 using namespace arith;
 using namespace vector;
@@ -1033,7 +1034,7 @@ struct LowerVectorAddOrSubOpToAIEVecAddElemOrSubElemOp
     unsigned laneSize = getVectorLaneSize(resultType);
 
     // Integer cases
-    if (scalarType.isa<IntegerType>()) {
+    if (isa<IntegerType>(scalarType)) {
       if (!laneSizeElWidthPairSet.count(
               std::make_pair(laneSize, resultElWidth)))
         return failure();
@@ -1772,17 +1773,29 @@ struct ComputeExpOpByLUTPattern : OpConversionPattern<math::ExpOp> {
         &moduleOp.getRegion().getBlocks().front());
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
-    SmallVector<Value> expOperands = {adaptor.getOperand()};
-
     rewriter.setInsertionPoint(expOp);
-    Type accType = getVectorOpDestType(srcType, /*AIEML =*/true);
-    auto funcOp = rewriter.create<emitc::CallOpaqueOp>(
-        expOp.getLoc(), TypeRange{accType}, "getExpBf16", nullptr, nullptr,
-        expOperands);
+
+    auto v16bf16OpaqueTy =
+        emitc::OpaqueType::get(rewriter.getContext(), "v16bfloat16");
+    auto opaquedOperand =
+        rewriter
+            .create<UnrealizedConversionCastOp>(expOp.getLoc(), v16bf16OpaqueTy,
+                                                adaptor.getOperand())
+            .getResult(0);
+    SmallVector<Value> expOperands = {opaquedOperand};
+
+    Type accTypeNative = getVectorOpDestType(srcType, /*AIEML =*/true);
+    Type v16accf32OpaqueTy =
+        emitc::OpaqueType::get(rewriter.getContext(), "v16accfloat");
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        expOp.getLoc(), TypeRange{v16accf32OpaqueTy}, "getExpBf16", nullptr,
+        nullptr, expOperands);
+    auto resCastOp = rewriter.create<UnrealizedConversionCastOp>(
+        expOp.getLoc(), accTypeNative, callOp.getResults());
     auto shiftParamOp = rewriter.create<arith::ConstantOp>(
         expOp.getLoc(), rewriter.getI32IntegerAttr(0));
     rewriter.replaceOpWithNewOp<aievec::SRSOp>(
-        expOp, srcType, funcOp.getResult(0), shiftParamOp.getResult());
+        expOp, srcType, resCastOp.getResult(0), shiftParamOp.getResult());
 
     return success();
   }
@@ -1815,7 +1828,7 @@ struct ComputeInvOpByLUTPattern : OpConversionPattern<arith::DivFOp> {
 
     auto constOp = dyn_cast<arith::ConstantOp>(divOp.getLhs().getDefiningOp());
     if (!constOp ||
-        constOp.getValue().cast<FloatAttr>().getValue().convertToDouble() !=
+        cast<FloatAttr>(constOp.getValue()).getValue().convertToDouble() !=
             1.0f)
       return failure();
 
@@ -1825,13 +1838,17 @@ struct ComputeInvOpByLUTPattern : OpConversionPattern<arith::DivFOp> {
         &moduleOp.getRegion().getBlocks().front());
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
-    SmallVector<Value> invOperands = {adaptor.getRhs()};
     auto truncOp = cast<arith::TruncFOp>(*divOp->getUsers().begin());
 
     rewriter.setInsertionPoint(truncOp);
-    rewriter.replaceOpWithNewOp<emitc::CallOpaqueOp>(
-        truncOp, TypeRange{truncOp.getResult().getType()}, "getInvBf16",
-        nullptr, nullptr, invOperands);
+    Type bf16OpaqueTy =
+        emitc::OpaqueType::get(rewriter.getContext(), "bfloat16");
+    SmallVector<Value> invOperands = {adaptor.getRhs()};
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        truncOp.getLoc(), bf16OpaqueTy, "getInvBf16", nullptr, nullptr,
+        invOperands);
+    rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
+        truncOp, TypeRange{truncOp.getResult().getType()}, callOp.getResults());
     rewriter.eraseOp(divOp);
 
     return success();
@@ -1865,10 +1882,19 @@ struct ComputeTanhOpByLUTPattern : OpConversionPattern<math::TanhOp> {
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
     rewriter.setInsertionPoint(tanhOp);
-    SmallVector<Value> tanhOperands = {adaptor.getOperand()};
-    rewriter.replaceOpWithNewOp<emitc::CallOpaqueOp>(
-        tanhOp, TypeRange{tanhOp.getResult().getType()}, "getTanhBf16", nullptr,
-        nullptr, tanhOperands);
+    Type v16bf16OpaqueTy =
+        emitc::OpaqueType::get(rewriter.getContext(), "v16bfloat16");
+    auto opaquedOperand =
+        rewriter
+            .create<UnrealizedConversionCastOp>(
+                tanhOp.getLoc(), v16bf16OpaqueTy, adaptor.getOperand())
+            .getResult(0);
+    SmallVector<Value> tanhOperands = {opaquedOperand};
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        tanhOp.getLoc(), v16bf16OpaqueTy, "getTanhBf16", nullptr, nullptr,
+        tanhOperands);
+    rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
+        tanhOp, TypeRange{tanhOp.getResult().getType()}, callOp.getResults());
 
     return success();
   }
@@ -1902,10 +1928,24 @@ struct ComputeSqrtOpPattern : OpConversionPattern<math::SqrtOp> {
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
     rewriter.setInsertionPoint(sqrtOp);
-    SmallVector<Value> sqrtOperands = {adaptor.getOperand()};
-    rewriter.replaceOpWithNewOp<emitc::CallOpaqueOp>(
-        sqrtOp, TypeRange{sqrtOp.getResult().getType()}, "getSqrtBf16", nullptr,
+    Type vLNbf16OpaqueTy;
+    if (laneSize == 16)
+      vLNbf16OpaqueTy =
+          emitc::OpaqueType::get(rewriter.getContext(), "v16bfloat16");
+    else
+      vLNbf16OpaqueTy =
+          emitc::OpaqueType::get(rewriter.getContext(), "v32bfloat16");
+    auto opaquedOperand =
+        rewriter
+            .create<UnrealizedConversionCastOp>(
+                sqrtOp.getLoc(), vLNbf16OpaqueTy, adaptor.getOperand())
+            .getResult(0);
+    SmallVector<Value> sqrtOperands = {opaquedOperand};
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        sqrtOp.getLoc(), TypeRange{vLNbf16OpaqueTy}, "getSqrtBf16", nullptr,
         nullptr, sqrtOperands);
+    rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
+        sqrtOp, TypeRange{sqrtOp.getResult().getType()}, callOp.getResults());
 
     return success();
   }
@@ -1939,10 +1979,24 @@ struct ComputeRsqrtOpPattern : OpConversionPattern<math::RsqrtOp> {
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
     rewriter.setInsertionPoint(rsqrtOp);
-    SmallVector<Value> rsqrtOperands = {adaptor.getOperand()};
-    rewriter.replaceOpWithNewOp<emitc::CallOpaqueOp>(
-        rsqrtOp, TypeRange{rsqrtOp.getResult().getType()}, "getRsqrtBf16",
-        nullptr, nullptr, rsqrtOperands);
+    Type vLNbf16OpaqueTy;
+    if (laneSize == 16)
+      vLNbf16OpaqueTy =
+          emitc::OpaqueType::get(rewriter.getContext(), "v16bfloat16");
+    else
+      vLNbf16OpaqueTy =
+          emitc::OpaqueType::get(rewriter.getContext(), "v32bfloat16");
+    auto opaquedOperand =
+        rewriter
+            .create<UnrealizedConversionCastOp>(
+                rsqrtOp.getLoc(), vLNbf16OpaqueTy, adaptor.getOperand())
+            .getResult(0);
+    SmallVector<Value> rsqrtOperands = {opaquedOperand};
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        rsqrtOp.getLoc(), TypeRange{vLNbf16OpaqueTy}, "getRsqrtBf16", nullptr,
+        nullptr, rsqrtOperands);
+    rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
+        rsqrtOp, TypeRange{rsqrtOp.getResult().getType()}, callOp.getResults());
 
     return success();
   }
@@ -1976,10 +2030,24 @@ struct ComputeErfOpPattern : OpConversionPattern<math::ErfOp> {
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
     rewriter.setInsertionPoint(erfOp);
-    SmallVector<Value> erfOperands = {adaptor.getOperand()};
-    rewriter.replaceOpWithNewOp<emitc::CallOpaqueOp>(
-        erfOp, TypeRange{erfOp.getResult().getType()}, "getErfBf16", nullptr,
+    Type vLNbf16OpaqueTy;
+    if (laneSize == 16)
+      vLNbf16OpaqueTy =
+          emitc::OpaqueType::get(rewriter.getContext(), "v16bfloat16");
+    else
+      vLNbf16OpaqueTy =
+          emitc::OpaqueType::get(rewriter.getContext(), "v32bfloat16");
+    auto opaquedOperand =
+        rewriter
+            .create<UnrealizedConversionCastOp>(erfOp.getLoc(), vLNbf16OpaqueTy,
+                                                adaptor.getOperand())
+            .getResult(0);
+    SmallVector<Value> erfOperands = {opaquedOperand};
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        erfOp.getLoc(), TypeRange{vLNbf16OpaqueTy}, "getErfBf16", nullptr,
         nullptr, erfOperands);
+    rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
+        erfOp, TypeRange{erfOp.getResult().getType()}, callOp.getResults());
 
     return success();
   }
@@ -1995,6 +2063,15 @@ struct ComputeAbsOpPattern : OpConversionPattern<SrcOpTy> {
   LogicalResult
   matchAndRewrite(SrcOpTy absOp, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
+    auto vecTy = dyn_cast<VectorType>(absOp.getOperand().getType());
+    if (!vecTy)
+      return failure();
+
+    Type elemTy = vecTy.getElementType();
+
+    unsigned laneSize = getVectorLaneSize(vecTy);
+    unsigned elWidth = elemTy.getIntOrFloatBitWidth();
+
     StringRef includeName = "vec_math.h";
     auto moduleOp = absOp->template getParentOfType<mlir::ModuleOp>();
     rewriter.setInsertionPointToStart(
@@ -2002,10 +2079,28 @@ struct ComputeAbsOpPattern : OpConversionPattern<SrcOpTy> {
     rewriter.create<emitc::IncludeOp>(moduleOp.getLoc(), includeName, false);
 
     rewriter.setInsertionPoint(absOp);
-    SmallVector<Value> absOperands = {adaptor.getOperand()};
-    rewriter.replaceOpWithNewOp<emitc::CallOpaqueOp>(
-        absOp, TypeRange{absOp.getResult().getType()}, "getAbs", nullptr,
-        nullptr, absOperands);
+    std::ostringstream typeName;
+    typeName << "v" << laneSize;
+    if (isa<FloatType>(elemTy)) {
+      if (elWidth == 16)
+        typeName << "bfloat16";
+      else
+        typeName << "float";
+    } else
+      typeName << "int" << elWidth;
+    Type vecOpaqueTy =
+        emitc::OpaqueType::get(rewriter.getContext(), typeName.str());
+    auto opaquedOperand =
+        rewriter
+            .create<UnrealizedConversionCastOp>(absOp.getLoc(), vecOpaqueTy,
+                                                adaptor.getOperand())
+            .getResult(0);
+    SmallVector<Value> absOperands = {opaquedOperand};
+    auto callOp = rewriter.create<emitc::CallOpaqueOp>(
+        absOp.getLoc(), TypeRange{vecOpaqueTy}, "getAbs", nullptr, nullptr,
+        absOperands);
+    rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
+        absOp, TypeRange{absOp.getResult().getType()}, callOp.getResults());
 
     return success();
   }
@@ -2882,7 +2977,7 @@ static void configureAIEVecCommonLegalizations(ConversionTarget &target,
       auto constOp =
           dyn_cast<arith::ConstantOp>(divfOp.getLhs().getDefiningOp());
       if (!constOp ||
-          constOp.getValue().cast<FloatAttr>().getValue().convertToDouble() !=
+          cast<FloatAttr>(constOp.getValue()).getValue().convertToDouble() !=
               1.0f)
         return true;
     } else {
@@ -3257,11 +3352,11 @@ static void configureAIEVecV2Legalizations(ConversionTarget &target,
         unsigned elWidth = scalarType.getIntOrFloatBitWidth();
         unsigned laneSize = getVectorLaneSize(vType);
 
-        if (scalarType.isa<IntegerType>() &&
+        if (isa<IntegerType>(scalarType) &&
             !laneSizeElWidthPairSet.count(std::make_pair(laneSize, elWidth)))
           return true;
 
-        if (scalarType.isa<FloatType>() && laneSize != 16 && laneSize != 32)
+        if (isa<FloatType>(scalarType) && laneSize != 16 && laneSize != 32)
           return true;
 
         return false;
diff --git a/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp b/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp
index 15f1ca7347..95d66e60bf 100644
--- a/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp
+++ b/lib/Dialect/AIEX/Transforms/AIECreateCores.cpp
@@ -113,8 +113,8 @@ struct AIECreateCoresPass : public AIECreateCoresBase<AIECreateCoresPass> {
         for (unsigned i = 0; i < callOperands.size(); i++) {
           Value operand = callOperands[i]; // Should be produced by an AllocOp
           MemRefType t = nullptr;
-          if (operand.getType().isa<MemRefType>()) {
-            t = operand.getType().cast<MemRefType>();
+          if (llvm::isa<MemRefType>(operand.getType())) {
+            t = llvm::cast<MemRefType>(operand.getType());
           } else if (operand.getType().isIntOrFloat()) {
             // promote scalar type to memref type
             int64_t shape[1] = {1};
diff --git a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp
index 47502ad43e..df35d3ba88 100644
--- a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp
+++ b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp
@@ -260,7 +260,7 @@ static bool skippedOp(Operation *op, CppEmitter &emitter,
             // If the underlying element types are float, then we do not really
             // need an srs op if source of srsOp has only one use.
             Value source = srsOp.getSource();
-            if (!emitter.aieml() && eltType.isa<FloatType>() &&
+            if (!emitter.aieml() && llvm::isa<FloatType>(eltType) &&
                 source.getDefiningOp()->hasOneUse()) {
               StringRef srcName = emitter.getOrCreateName(source);
               emitter.setName(srsOp->getResult(0), srcName);
@@ -276,7 +276,7 @@ static bool skippedOp(Operation *op, CppEmitter &emitter,
             // If the underlying element types are float, then we do not really
             // need a ups op if the source accumulator has only one use.
             Value source = upsOp.getSource();
-            if (!emitter.aieml() && eltType.isa<FloatType>() &&
+            if (!emitter.aieml() && llvm::isa<FloatType>(eltType) &&
                 source.getDefiningOp()->hasOneUse()) {
               StringRef srcName = emitter.getOrCreateName(source);
               emitter.setName(upsOp->getResult(0), srcName);
@@ -316,6 +316,17 @@ static bool skippedOp(Operation *op, CppEmitter &emitter,
             emitter.setName(castOp.getResult(), srcName);
             return true;
           })
+          // skip op 7: ignore unrealized conversion casts. These will come
+          //            from non-C types interfacing with emitc for math ops.
+          .Case<UnrealizedConversionCastOp>([&](auto uccOp) {
+            auto inputs = uccOp.getInputs();
+            auto outputs = uccOp.getOutputs();
+            if (inputs.size() > 1 || inputs.size() > 1)
+              return false;
+            StringRef inputName = emitter.getOrCreateName(inputs[0]);
+            emitter.setName(outputs[0], inputName);
+            return true;
+          })
           .Default([&](Operation *) { return false; });
 
   // Ops whose strong liveness must be determined
@@ -348,7 +359,7 @@ static LogicalResult parseMemRefDynamicDims(CppEmitter &emitter,
       auto indexOp = dyn_cast<arith::ConstantOp>(op.getIndex().getDefiningOp());
       assert(indexOp && "Failed to get the index value of dimOp");
       // Get the constant index value
-      APInt idxVal = indexOp.getValue().cast<IntegerAttr>().getValue();
+      APInt idxVal = llvm::cast<IntegerAttr>(indexOp.getValue()).getValue();
       unsigned index = idxVal.getZExtValue();
       // Assign a printable name to the result
       StringRef name = emitter.getOrCreateName(result, "m");
@@ -459,8 +470,8 @@ static std::pair<bool, int64_t> getTripCount(scf::ForOp forOp) {
   auto lb = forOp.getLowerBound().getDefiningOp<arith::ConstantOp>();
   if (auto ub = forOp.getUpperBound().getDefiningOp<arith::ConstantOp>();
       lb && ub) {
-    APInt ubValue = ub.getValue().cast<IntegerAttr>().getValue();
-    APInt lbValue = lb.getValue().cast<IntegerAttr>().getValue();
+    APInt ubValue = llvm::cast<IntegerAttr>(ub.getValue()).getValue();
+    APInt lbValue = llvm::cast<IntegerAttr>(lb.getValue()).getValue();
     return std::make_pair(true,
                           ubValue.getSExtValue() - lbValue.getSExtValue());
   }
@@ -470,7 +481,7 @@ static std::pair<bool, int64_t> getTripCount(scf::ForOp forOp) {
 // Get the loop step size of the for operator
 static std::pair<bool, int64_t> getStep(scf::ForOp forOp) {
   if (auto step = forOp.getStep().getDefiningOp<arith::ConstantOp>()) {
-    APInt stepValue = step.getValue().cast<IntegerAttr>().getValue();
+    APInt stepValue = llvm::cast<IntegerAttr>(step.getValue()).getValue();
     return std::make_pair(true, stepValue.getSExtValue());
   }
   return std::make_pair(false, 0);
@@ -575,7 +586,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPDOp updOp) {
 
   raw_indented_ostream &os = emitter.ostream();
   Value result = updOp.getResult();
-  auto resultType = result.getType().cast<VectorType>();
+  auto resultType = llvm::cast<VectorType>(result.getType());
   int32_t vecSizeInBits = getVectorSizeInBits(resultType);
   int32_t elementSizeInBits = getElementSizeInBits(resultType);
 
@@ -685,13 +696,13 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) {
   if (!emitter.hasValueInScope(source))
     return failure();
 
-  auto accType = upsOp.getResult().getType().cast<VectorType>();
+  auto accType = llvm::cast<VectorType>(upsOp.getResult().getType());
   unsigned lanes = getVectorLaneSize(accType);
   Type eltType = accType.getElementType();
 
   // If the underlying element types are float, then we do not really need a
   // ups op. We can simply generate an assignment
-  if (!emitter.aieml() && eltType.isa<FloatType>()) {
+  if (!emitter.aieml() && llvm::isa<FloatType>(eltType)) {
     os << emitter.getOrCreateName(source);
     return success();
   }
@@ -742,7 +753,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
     return failure();
 
   // Get the datatype of the source and result vector
-  auto resType = castOp->getResult(0).getType().cast<VectorType>();
+  auto resType = llvm::cast<VectorType>(castOp->getResult(0).getType());
   Type eltType = resType.getElementType();
   unsigned lanes = getVectorLaneSize(resType);
 
@@ -750,14 +761,14 @@ static LogicalResult printOperation(CppEmitter &emitter,
 
   unsigned width;
   if (isResAcc) {
-    if (eltType.isa<FloatType>())
+    if (llvm::isa<FloatType>(eltType))
       os << "v" << lanes << "accfloat";
     else {
       width = getElementSizeInBits(resType);
       os << "v" << lanes << "acc" << width;
     }
-  } else if (eltType.isa<FloatType>()) {
-    width = eltType.cast<FloatType>().getWidth();
+  } else if (llvm::isa<FloatType>(eltType)) {
+    width = llvm::cast<FloatType>(eltType).getWidth();
     os << "v" << lanes;
     if (width == 16)
       os << "bfloat16";
@@ -800,8 +811,8 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) {
   Value shift = srsOp.getShift();
 
   // Get the datatype of the source accumulator and result vector
-  auto accType = srsOp.getSource().getType().cast<VectorType>();
-  auto resType = srsOp->getResult(0).getType().cast<VectorType>();
+  auto accType = llvm::cast<VectorType>(srsOp.getSource().getType());
+  auto resType = llvm::cast<VectorType>(srsOp->getResult(0).getType());
   Type eltType = accType.getElementType();
   unsigned lanes = getVectorLaneSize(resType);
 
@@ -817,7 +828,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) {
 
   // If the underlying element types are float, then we do not really need an
   // srs op. We can simply generate an assignment
-  if (eltType.isa<FloatType>()) {
+  if (llvm::isa<FloatType>(eltType)) {
     if (emitter.aieml()) {
       if (unsigned width = getElementSizeInBits(resType); width == 32)
         os << "srs";
@@ -856,7 +867,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) {
   os << "(";
   os << emitter.getOrCreateName(source);
   os << ", ";
-  if (srsOp.getShift().getType().cast<IntegerType>().getWidth() != 32)
+  if (llvm::cast<IntegerType>(srsOp.getShift().getType()).getWidth() != 32)
     os << "(int32_t)";
   os << emitter.getOrCreateName(shift);
   os << ")";
@@ -895,7 +906,8 @@ static LogicalResult
 printOperation(CppEmitter &emitter,
                aievec::BroadcastScalarOp broadcastScalarOp) {
   auto source = broadcastScalarOp.getSource();
-  auto resType = broadcastScalarOp.getResult().getType().cast<VectorType>();
+  auto resType =
+      llvm::cast<VectorType>(broadcastScalarOp.getResult().getType());
   unsigned width = getElementSizeInBits(resType);
   unsigned lanes = getVectorLaneSize(resType);
   raw_indented_ostream &os = emitter.ostream();
@@ -906,7 +918,7 @@ printOperation(CppEmitter &emitter,
 
   Type eltType = resType.getElementType();
   os << "broadcast_to_v";
-  if (eltType.isa<IntegerType>()) {
+  if (llvm::isa<IntegerType>(eltType)) {
     os << lanes << "int";
     os << width;
   } else if (width == 16)
@@ -932,7 +944,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::ExtOp extOp) {
   if (!emitter.hasValueInScope(source))
     return failure();
 
-  auto resType = extOp.getResult().getType().cast<VectorType>();
+  auto resType = llvm::cast<VectorType>(extOp.getResult().getType());
   Type eltType = resType.getElementType();
   unsigned lanes = getVectorLaneSize(resType);
   unsigned resWidth = getElementSizeInBits(resType);
@@ -940,7 +952,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::ExtOp extOp) {
   // Print the version of ext for aie-ml
   if (emitter.aieml()) {
     os << "extract_v" << std::to_string(lanes);
-    if (eltType.isa<IntegerType>())
+    if (llvm::isa<IntegerType>(eltType))
       os << "int" << std::to_string(resWidth);
     else if (resWidth == 16)
       os << "bfloat16";
@@ -1065,7 +1077,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
     return failure();
 
   // Determine if we want to geneate select32, or select16, or select8
-  auto xbuffType = selectOp.getXbuff().getType().cast<VectorType>();
+  auto xbuffType = llvm::cast<VectorType>(selectOp.getXbuff().getType());
   int32_t elementSizeInBits = getElementSizeInBits(xbuffType);
   assert(elementSizeInBits == 16 || elementSizeInBits == 32 ||
          elementSizeInBits == 64);
@@ -1128,7 +1140,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
     return failure();
 
   // Determine the flavor of result
-  auto sourceType = packOp.getSource().getType().cast<VectorType>();
+  auto sourceType = llvm::cast<VectorType>(packOp.getSource().getType());
   Type scalarType = sourceType.getElementType();
   os << (scalarType.isUnsignedInteger() ? "upack" : "pack");
   os << "(";
@@ -1303,18 +1315,18 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::MulOp mulOp) {
 
   std::string opname;
   // Create opname based on the result type
-  auto resType = mulOp.getResult().getType().cast<VectorType>();
+  auto resType = llvm::cast<VectorType>(mulOp.getResult().getType());
   Type eltType = resType.getElementType();
   if (!simpleScheme) {
     if (auto iType = llvm::dyn_cast<IntegerType>(eltType)) {
       if (iType.getWidth() == 80)
         opname = "l";
-    } else if (eltType.isa<FloatType>())
+    } else if (llvm::isa<FloatType>(eltType))
       opname = "fp";
   }
 
   opname += "mul";
-  if (!simpleScheme && !eltType.isa<FloatType>())
+  if (!simpleScheme && !llvm::isa<FloatType>(eltType))
     opname += std::to_string(getVectorLaneSize(resType));
 
   raw_indented_ostream &os = emitter.ostream();
@@ -1348,7 +1360,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
   std::string opname = "mul_elem";
 
   // Create opname based on the source type
-  auto lhsType = mulElemOp.getLhs().getType().cast<VectorType>();
+  auto lhsType = llvm::cast<VectorType>(mulElemOp.getLhs().getType());
   Type eltType = lhsType.getElementType();
   int32_t lsize = getElementSizeInBits(lhsType);
   auto iType = llvm::dyn_cast<IntegerType>(eltType);
@@ -1360,7 +1372,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
       opname += "_32";
     else if (lsize == 8)
       opname += "_32_2";
-  } else if (eltType.isa<FloatType>()) {
+  } else if (llvm::isa<FloatType>(eltType)) {
     if (lsize == 32)
       opname += "_16";
     else if (lsize == 16)
@@ -1398,7 +1410,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
     return failure();
 
   // Create opname based on the source type
-  auto lhsType = mulConvOp.getLhs().getType().cast<VectorType>();
+  auto lhsType = llvm::cast<VectorType>(mulConvOp.getLhs().getType());
   Type eltType = lhsType.getElementType();
   int32_t lsize = getElementSizeInBits(lhsType);
   auto iType = llvm::dyn_cast<IntegerType>(eltType);
@@ -1450,10 +1462,10 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::AddOp addOp) {
     return failure();
 
   // Get the scalar type of result vector
-  auto resultType = addOp.getResult().getType().cast<VectorType>();
+  auto resultType = llvm::cast<VectorType>(addOp.getResult().getType());
   unsigned lanes = getVectorLaneSize(resultType);
   Type elementType = resultType.getElementType();
-  bool floatType = elementType.isa<FloatType>();
+  bool floatType = llvm::isa<FloatType>(elementType);
 
   // Detemine if the add scheme is simple or complex
 
@@ -1504,10 +1516,10 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SubOp subOp) {
     return failure();
 
   // Get the scalar type of result vector
-  auto resultType = subOp.getResult().getType().cast<VectorType>();
+  auto resultType = llvm::cast<VectorType>(subOp.getResult().getType());
   unsigned lanes = getVectorLaneSize(resultType);
   Type elementType = resultType.getElementType();
-  bool floatType = elementType.isa<FloatType>();
+  bool floatType = llvm::isa<FloatType>(elementType);
 
   // Detemine if the sub scheme is simple or complex
 
@@ -1801,18 +1813,18 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::FMAOp fmaOp) {
 
   std::string opname;
   // Create opname based on the result type
-  auto resType = fmaOp.getResult().getType().cast<VectorType>();
+  auto resType = llvm::cast<VectorType>(fmaOp.getResult().getType());
   Type eltType = resType.getElementType();
   if (!simpleScheme) {
     if (auto iType = llvm::dyn_cast<IntegerType>(eltType)) {
       if (iType.getWidth() == 80)
         opname = "l";
-    } else if (eltType.isa<FloatType>())
+    } else if (llvm::isa<FloatType>(eltType))
       opname = "fp";
   }
 
   opname += fmaOp.getFmsub() ? "msc" : "mac";
-  if (!simpleScheme && !eltType.isa<FloatType>())
+  if (!simpleScheme && !llvm::isa<FloatType>(eltType))
     opname += std::to_string(getVectorLaneSize(resType));
 
   raw_indented_ostream &os = emitter.ostream();
@@ -1851,7 +1863,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
 
   std::string opname = fmaElemOp.getFmsub() ? "msc_elem" : "mac_elem";
   // Create opname based on the lhs and rhs type
-  auto lhsType = fmaElemOp.getLhs().getType().cast<VectorType>();
+  auto lhsType = llvm::cast<VectorType>(fmaElemOp.getLhs().getType());
   Type eltType = lhsType.getElementType();
   int32_t lsize = getElementSizeInBits(lhsType);
   auto iType = llvm::dyn_cast<IntegerType>(eltType);
@@ -1863,7 +1875,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
       opname += "_32";
     else if (lsize == 8)
       opname += "_32_2";
-  } else if (eltType.isa<FloatType>()) {
+  } else if (llvm::isa<FloatType>(eltType)) {
     if (lsize == 32)
       opname += "_16";
     else if (lsize == 16)
@@ -1908,7 +1920,7 @@ static LogicalResult printOperation(CppEmitter &emitter,
 
   std::string opname = fmaConvOp.getFmsub() ? "msc_conv" : "mac_conv";
   // Create opname based on the lhs and rhs type
-  auto lhsType = fmaConvOp.getLhs().getType().cast<VectorType>();
+  auto lhsType = llvm::cast<VectorType>(fmaConvOp.getLhs().getType());
   Type eltType = lhsType.getElementType();
   int32_t lsize = getElementSizeInBits(lhsType);
   auto iType = llvm::dyn_cast<IntegerType>(eltType);
@@ -1980,10 +1992,10 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::CmpOp cmpOp) {
     return failure();
 
   os << "(";
-  auto vType = lhs.getType().cast<VectorType>();
+  auto vType = llvm::cast<VectorType>(lhs.getType());
 
   if (Type eltType = vType.getElementType();
-      eltType.isa<IntegerType>() &&
+      llvm::isa<IntegerType>(eltType) &&
       (pred == "ult" || pred == "ule" || pred == "ugt" || pred == "uge")) {
     unsigned lanes = getVectorLaneSize(vType);
     unsigned width = getElementSizeInBits(vType);
@@ -2948,7 +2960,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) {
       printInt(iAttr.getValue(), shouldMapToUnsigned(iType.getSignedness()));
       return success();
     }
-    if (iAttr.getType().dyn_cast<IndexType>()) {
+    if (llvm::dyn_cast<IndexType>(iAttr.getType())) {
       printInt(iAttr.getValue(), false);
       return success();
     }
@@ -2964,7 +2976,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) {
         os << '}';
         return success();
       }
-      if (tType.getElementType().dyn_cast<IndexType>()) {
+      if (llvm::dyn_cast<IndexType>(tType.getElementType())) {
         os << '{';
         interleaveComma(dense, os,
                         [&](const APInt &val) { printInt(val, false); });
@@ -3021,7 +3033,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) {
         }
         return success();
       }
-      if (vType.getElementType().dyn_cast<IndexType>()) {
+      if (llvm::dyn_cast<IndexType>(vType.getElementType())) {
         os << '{';
         interleaveComma(dense, os,
                         [&](const APInt &val) { printInt(val, false); });