From b673fd2fb89f49a0ca88dd52adf909835ffe09e7 Mon Sep 17 00:00:00 2001 From: jamestcl-amd Date: Tue, 28 May 2024 13:37:48 -0700 Subject: [PATCH 1/5] Add vmin intr op to xllvm --- .../aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td b/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td index 2442a51c1d..f7409ce172 100644 --- a/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td +++ b/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td @@ -351,4 +351,49 @@ def VectorMaxLtBf16IntrOp : Arguments<(ins VectorOfLengthAndType<[32], [BF16]>:$lhs, VectorOfLengthAndType<[32], [BF16]>:$rhs)>; +// ----- MIN ELEMENT ----- + +def VectorMinGe8IntrOp : + AIEVec2_IntrOp<"vmin.ge8", + [TypeIs<"res", + LLVM_StructOf<[ + VectorOfLengthAndType<[64], [I8]>, + I32]> + >], /*numResults=*/2>, + Arguments<(ins VectorOfLengthAndType<[64], [I8]>:$lhs, + VectorOfLengthAndType<[64], [I8]>:$rhs, + I32:$cmp)> ; + +def VectorMinGe16IntrOp : + AIEVec2_IntrOp<"vmin.ge16", + [TypeIs<"res", + LLVM_StructOf<[ + VectorOfLengthAndType<[32], [I16]>, + I32]> + >], /*numResults=*/2>, + Arguments<(ins VectorOfLengthAndType<[32], [I16]>:$lhs, + VectorOfLengthAndType<[32], [I16]>:$rhs, + I32:$cmp)> ; + +def VectorMinGe32IntrOp : + AIEVec2_IntrOp<"vmin.ge32", + [TypeIs<"res", + LLVM_StructOf<[ + VectorOfLengthAndType<[16], [I32]>, + I32]> + >], /*numResults=*/2>, + Arguments<(ins VectorOfLengthAndType<[16], [I32]>:$lhs, + VectorOfLengthAndType<[16], [I32]>:$rhs, + I32:$cmp)> ; + +def VectorMinGeBf16IntrOp : + AIEVec2_IntrOp<"vmin.gebf16", + [TypeIs<"res", + LLVM_StructOf<[ + VectorOfLengthAndType<[32], [BF16]>, + I32]> + >], /*numResults=*/2>, + Arguments<(ins VectorOfLengthAndType<[32], [BF16]>:$lhs, + VectorOfLengthAndType<[32], [BF16]>:$rhs)> ; + #endif // AIE_DIALECT_XLLVM_IR_XLLVMAIE2INTROPS_TD From 2e7f63e4bd4abe70a8788e1f13205c289cd55084 Mon Sep 17 00:00:00 2001 From: jamestcl-amd Date: Tue, 28 May 2024 13:38:13 -0700 Subject: [PATCH 2/5] Add vmin intr op translation to external llvm test --- test/Target/LLVMIR/aievec.mlir | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/test/Target/LLVMIR/aievec.mlir b/test/Target/LLVMIR/aievec.mlir index ddcea0a721..a084f4f2a3 100644 --- a/test/Target/LLVMIR/aievec.mlir +++ b/test/Target/LLVMIR/aievec.mlir @@ -432,4 +432,51 @@ llvm.func @vmax_ltbf16(%lhs: vector<32xbf16>, %rhs: vector<32xbf16>) -> vector<3 llvm.return %1 : vector<32xbf16> } +// -- MIN ELEMENT -- + +// CHECK-LABEL: <64 x i8> @vmin_ge8 +llvm.func @vmin_ge8(%lhs: vector<64xi8>, %rhs: vector<64xi8>, %pred: i32) -> vector<64xi8> { + // CHECK: call { <64 x i8>, i32 } @llvm.aie2.vmin.ge8( + // CHECK-SAME: <64 x i8> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, i32 %{{[0-9]+}}) + %0 = "xllvm.intr.aie2.vmin.ge8"(%lhs, %rhs, %pred) : + (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, i32)> + %1 = llvm.extractvalue %0[0] : !llvm.struct<(vector<64xi8>, i32)> + llvm.return %1 : vector<64xi8> +} + +// CHECK-LABEL: <32 x i16> @vmin_ge16 +llvm.func @vmin_ge16(%lhs: vector<32xi16>, %rhs: vector<32xi16>, %pred: i32) -> vector<32xi16> { + // CHECK: call { <32 x i16>, i32 } @llvm.aie2.vmin.ge16( + // CHECK-SAME: <32 x i16> %{{[0-9]+}}, <32 x i16> %{{[0-9]+}}, i32 %{{[0-9]+}}) + %0 = "xllvm.intr.aie2.vmin.ge16"(%lhs, %rhs, %pred) : + (vector<32xi16>, vector<32xi16>, i32) -> !llvm.struct<(vector<32xi16>, i32)> + %1 = llvm.extractvalue %0[0] : !llvm.struct<(vector<32xi16>, i32)> + llvm.return %1 : vector<32xi16> +} + +// CHECK-LABEL: <16 x i32> @vmin_ge32 +llvm.func @vmin_ge32(%lhs: vector<16xi32>, %rhs: vector<16xi32>, %pred: i32) -> vector<16xi32> { + // CHECK: call { <16 x i32>, i32 } @llvm.aie2.vmin.ge32( + // CHECK-SAME: <16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}}, i32 %{{[0-9]+}}) + %0 = "xllvm.intr.aie2.vmin.ge32"(%lhs, %rhs, %pred) : + (vector<16xi32>, vector<16xi32>, i32) -> !llvm.struct<(vector<16xi32>, i32)> + %1 = llvm.extractvalue %0[0] : !llvm.struct<(vector<16xi32>, i32)> + llvm.return %1 : vector<16xi32> +} + +// CHECK-LABEL: <32 x bfloat> @vmin_gebf16 +llvm.func @vmin_gebf16(%lhs: vector<32xbf16>, %rhs: vector<32xbf16>) -> vector<32xbf16> { + // CHECK: call { <32 x bfloat>, i32 } @llvm.aie2.vmin.gebf16( + // CHECK-SAME: <32 x bfloat> %{{[0-9]+}}, <32 x bfloat> %{{[0-9]+}}) + %0 = "xllvm.intr.aie2.vmin.gebf16"(%lhs, %rhs) : + (vector<32xbf16>, vector<32xbf16>) -> !llvm.struct<(vector<32xbf16>, i32)> + %1 = llvm.extractvalue %0[0] : !llvm.struct<(vector<32xbf16>, i32)> + llvm.return %1 : vector<32xbf16> +} + // CHECK-LABEL: declare { <32 x bfloat>, i32 } @llvm.aie2.vmax.ltbf16(<32 x bfloat>, <32 x bfloat>) + +// CHECK-LABEL: declare { <64 x i8>, i32 } @llvm.aie2.vmin.ge8(<64 x i8>, <64 x i8>, i32) +// CHECK-LABEL: declare { <32 x i16>, i32 } @llvm.aie2.vmin.ge16(<32 x i16>, <32 x i16>, i32) +// CHECK-LABEL: declare { <16 x i32>, i32 } @llvm.aie2.vmin.ge32(<16 x i32>, <16 x i32>, i32) +// CHECK-LABEL: declare { <32 x bfloat>, i32 } @llvm.aie2.vmin.gebf16(<32 x bfloat>, <32 x bfloat>) From a2947151a05ebef64c496e7ddd39654b3e5bd3c4 Mon Sep 17 00:00:00 2001 From: jamestcl-amd Date: Tue, 28 May 2024 13:38:54 -0700 Subject: [PATCH 3/5] Conversion pattern from aievec.min to vmin xllvm intr op --- lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp | 94 ++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp index 9c1c3d5bd5..1ad5b1492e 100644 --- a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp +++ b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp @@ -1498,6 +1498,99 @@ class BroadcastOpConversion } }; +class MinOpConversion : public mlir::ConvertOpToLLVMPattern { +public: + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(aievec::MinOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + + VectorType resultType = cast(op.getResult().getType()); + Type resultScaTy = resultType.getElementType(); + unsigned resultBitWidth = resultScaTy.getIntOrFloatBitWidth(); + int resultLanes = getVectorLaneSize(resultType); + int resultVectorSize = resultBitWidth * resultLanes; + + if (resultVectorSize != 512) { + op.emitWarning() << "aievec.min conversion with " << resultVectorSize + << "-bit result is not supported.\n"; + return failure(); + } + + // create xllvm intrinsic + Value minOp = nullptr; + if (llvm::isa(resultScaTy)) { + // create constant for cmp + auto cmpCst = rewriter.create( + loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0)); + SmallVector operands{adaptor.getLhs(), adaptor.getRhs(), cmpCst}; + if (resultBitWidth == 8) { + minOp = rewriter.create( + loc, + mlir::LLVM::LLVMStructType::getLiteral( + rewriter.getContext(), + {VectorType::get({64}, rewriter.getI8Type()), + rewriter.getI32Type()}), + forceCastOperandsToSignature( + rewriter, loc, operands, + {VectorType::get({64}, rewriter.getI8Type()), + VectorType::get({64}, rewriter.getI8Type()), + rewriter.getI32Type()})); + } else if (resultBitWidth == 16) { + minOp = rewriter.create( + loc, + mlir::LLVM::LLVMStructType::getLiteral( + rewriter.getContext(), + {VectorType::get({32}, rewriter.getI16Type()), + rewriter.getI32Type()}), + forceCastOperandsToSignature( + rewriter, loc, operands, + {VectorType::get({32}, rewriter.getI16Type()), + VectorType::get({32}, rewriter.getI16Type()), + rewriter.getI32Type()})); + } else if (resultBitWidth == 32) { + minOp = rewriter.create( + loc, + mlir::LLVM::LLVMStructType::getLiteral( + rewriter.getContext(), + {VectorType::get({16}, rewriter.getI32Type()), + rewriter.getI32Type()}), + forceCastOperandsToSignature( + rewriter, loc, operands, + {VectorType::get({16}, rewriter.getI32Type()), + VectorType::get({16}, rewriter.getI32Type()), + rewriter.getI32Type()})); + } + } else { + if (resultBitWidth == 16) { + minOp = rewriter.create( + loc, + mlir::LLVM::LLVMStructType::getLiteral( + rewriter.getContext(), + {VectorType::get({32}, rewriter.getBF16Type()), + rewriter.getI32Type()}), + forceCastOperandsToSignature( + rewriter, loc, {adaptor.getLhs(), adaptor.getRhs()}, + {VectorType::get({32}, rewriter.getBF16Type()), + VectorType::get({32}, rewriter.getBF16Type())})); + } + } + + if (!minOp) { + op.emitError() << "aievec.min conversion is not supported.\n"; + return failure(); + } + + // create llvm.extractvalue for the first element in the LLVMStruct + rewriter.replaceOpWithNewOp(op, minOp, + /*position=*/0); + + return success(); + } +}; + class BroadcastScalarOpConversion : public mlir::ConvertOpToLLVMPattern { public: @@ -1939,6 +2032,7 @@ void populateAIEVecToLLVMConversionPatterns( BroadcastScalarOpConversion, FMAElemOpConversion, MatMulOpConversion, + MinOpConversion, ShiftOpConversion, ExtractElemOpConversion, FoldAIECastOps>(converter); From 84550c93fe826f40df5c46f760dd871570f323a7 Mon Sep 17 00:00:00 2001 From: jamestcl-amd Date: Tue, 28 May 2024 13:39:53 -0700 Subject: [PATCH 4/5] Add lit test coverage for the aievec.min conversion pattern --- test/Conversion/AIEVecToLLVM/test-min.mlir | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 test/Conversion/AIEVecToLLVM/test-min.mlir diff --git a/test/Conversion/AIEVecToLLVM/test-min.mlir b/test/Conversion/AIEVecToLLVM/test-min.mlir new file mode 100644 index 0000000000..48ebc00d1b --- /dev/null +++ b/test/Conversion/AIEVecToLLVM/test-min.mlir @@ -0,0 +1,62 @@ +// RUN: aie-opt %s -split-input-file -convert-aievec-to-llvm | FileCheck %s + +func.func @i8_min(%arg0 : vector<64xi8>) -> vector<64xi8> { + %0 = aievec.min %arg0, %arg0 : vector<64xi8> + return %0 : vector<64xi8> +} + +// CHECK-LABEL: @i8_min +// CHECK-SAME: %[[ARG0:.*]]: vector<64xi8> +// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 +// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge8"( +// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) : +// CHECK-SAME: (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, i32)> +// CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<64xi8>, i32)> +// CHECK-NEXT: return %[[RES]] : vector<64xi8> + +// ----- + +func.func @i16_min(%arg0 : vector<32xi16>) -> vector<32xi16> { + %0 = aievec.min %arg0, %arg0 : vector<32xi16> + return %0 : vector<32xi16> +} + +// CHECK-LABEL: @i16_min +// CHECK-SAME: %[[ARG0:.*]]: vector<32xi16> +// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 +// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge16"( +// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) : +// CHECK-SAME: (vector<32xi16>, vector<32xi16>, i32) -> !llvm.struct<(vector<32xi16>, i32)> +// CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<32xi16>, i32)> +// CHECK-NEXT: return %[[RES]] : vector<32xi16> + +// ----- + +func.func @i32_min(%arg0 : vector<16xi32>) -> vector<16xi32> { + %0 = aievec.min %arg0, %arg0 : vector<16xi32> + return %0 : vector<16xi32> +} + +// CHECK-LABEL: @i32_min +// CHECK-SAME: %[[ARG0:.*]]: vector<16xi32> +// CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 +// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge32"( +// CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) : +// CHECK-SAME: (vector<16xi32>, vector<16xi32>, i32) -> !llvm.struct<(vector<16xi32>, i32)> +// CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<16xi32>, i32)> +// CHECK-NEXT: return %[[RES]] : vector<16xi32> + +// ----- + +func.func @bf16_min(%arg0 : vector<32xbf16>) -> vector<32xbf16> { + %0 = aievec.min %arg0, %arg0 : vector<32xbf16> + return %0 : vector<32xbf16> +} + +// CHECK-LABEL: @bf16_min +// CHECK-SAME: %[[ARG0:.*]]: vector<32xbf16> +// CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.gebf16"( +// CHECK-SAME: %[[ARG0]], %[[ARG0]]) : +// CHECK-SAME: (vector<32xbf16>, vector<32xbf16>) -> !llvm.struct<(vector<32xbf16>, i32)> +// CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<32xbf16>, i32)> +// CHECK-NEXT: return %[[RES]] : vector<32xbf16> From 62c643a0ef166bdca584349784b027acb31f60fc Mon Sep 17 00:00:00 2001 From: jamestcl-amd Date: Wed, 29 May 2024 14:43:16 -0700 Subject: [PATCH 5/5] Address review comments --- .../aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td | 2 +- lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp | 8 +++++-- test/Conversion/AIEVecToLLVM/test-min.mlir | 24 ++++++++++++++++--- test/Target/LLVMIR/aievec.mlir | 8 +++---- 4 files changed, 32 insertions(+), 10 deletions(-) diff --git a/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td b/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td index f7409ce172..5806847e0c 100644 --- a/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td +++ b/include/aie/Dialect/XLLVM/IR/XLLVMAIE2IntrOps.td @@ -358,7 +358,7 @@ def VectorMinGe8IntrOp : [TypeIs<"res", LLVM_StructOf<[ VectorOfLengthAndType<[64], [I8]>, - I32]> + VectorOfLengthAndType<[2], [I32]>]> >], /*numResults=*/2>, Arguments<(ins VectorOfLengthAndType<[64], [I8]>:$lhs, VectorOfLengthAndType<[64], [I8]>:$rhs, diff --git a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp index 1ad5b1492e..dc3674f17e 100644 --- a/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp +++ b/lib/Conversion/AIEVecToLLVM/AIEVecToLLVM.cpp @@ -1513,6 +1513,7 @@ class MinOpConversion : public mlir::ConvertOpToLLVMPattern { int resultLanes = getVectorLaneSize(resultType); int resultVectorSize = resultBitWidth * resultLanes; + // aievec.min op has the AllTypesMatch constraint on lhs/rhs/res if (resultVectorSize != 512) { op.emitWarning() << "aievec.min conversion with " << resultVectorSize << "-bit result is not supported.\n"; @@ -1532,7 +1533,7 @@ class MinOpConversion : public mlir::ConvertOpToLLVMPattern { mlir::LLVM::LLVMStructType::getLiteral( rewriter.getContext(), {VectorType::get({64}, rewriter.getI8Type()), - rewriter.getI32Type()}), + VectorType::get({2}, rewriter.getI32Type())}), forceCastOperandsToSignature( rewriter, loc, operands, {VectorType::get({64}, rewriter.getI8Type()), @@ -1579,7 +1580,10 @@ class MinOpConversion : public mlir::ConvertOpToLLVMPattern { } if (!minOp) { - op.emitError() << "aievec.min conversion is not supported.\n"; + // We have checked the lhs/rhs/res to be 512-bit vectors. Hence, a + // possible failure here is due to unsupported element datatype. + op.emitWarning() << "aievec.min conversion fails due to unsupported " + "element data type.\n"; return failure(); } diff --git a/test/Conversion/AIEVecToLLVM/test-min.mlir b/test/Conversion/AIEVecToLLVM/test-min.mlir index 48ebc00d1b..4930d639c9 100644 --- a/test/Conversion/AIEVecToLLVM/test-min.mlir +++ b/test/Conversion/AIEVecToLLVM/test-min.mlir @@ -1,4 +1,4 @@ -// RUN: aie-opt %s -split-input-file -convert-aievec-to-llvm | FileCheck %s +// RUN: aie-opt %s -split-input-file -convert-aievec-to-llvm -verify-diagnostics | FileCheck %s func.func @i8_min(%arg0 : vector<64xi8>) -> vector<64xi8> { %0 = aievec.min %arg0, %arg0 : vector<64xi8> @@ -10,8 +10,8 @@ func.func @i8_min(%arg0 : vector<64xi8>) -> vector<64xi8> { // CHECK: %[[CST:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK-NEXT: %[[VMIN:.*]] = "xllvm.intr.aie2.vmin.ge8"( // CHECK-SAME: %[[ARG0]], %[[ARG0]], %[[CST]]) : -// CHECK-SAME: (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, i32)> -// CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<64xi8>, i32)> +// CHECK-SAME: (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, vector<2xi32>)> +// CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<64xi8>, vector<2xi32>)> // CHECK-NEXT: return %[[RES]] : vector<64xi8> // ----- @@ -60,3 +60,21 @@ func.func @bf16_min(%arg0 : vector<32xbf16>) -> vector<32xbf16> { // CHECK-SAME: (vector<32xbf16>, vector<32xbf16>) -> !llvm.struct<(vector<32xbf16>, i32)> // CHECK-NEXT: %[[RES:.*]] = llvm.extractvalue %[[VMIN]][0] : !llvm.struct<(vector<32xbf16>, i32)> // CHECK-NEXT: return %[[RES]] : vector<32xbf16> + +// ----- + +func.func @invalid_i4_min(%arg0 : vector<128xi4>) -> vector<128xi4> { + // expected-warning @+2 {{aievec.min conversion fails due to unsupported element data type.}} + // expected-error @+1 {{failed to legalize operation 'aievec.min' that was explicitly marked illegal}} + %0 = aievec.min %arg0, %arg0 : vector<128xi4> + return %0 : vector<128xi4> +} + +// ----- + +func.func @invalid_i8_min(%arg0 : vector<128xi8>) -> vector<128xi8> { + // expected-warning @+2 {{aievec.min conversion with 1024-bit result is not supported.}} + // expected-error @+1 {{failed to legalize operation 'aievec.min' that was explicitly marked illegal}} + %0 = aievec.min %arg0, %arg0 : vector<128xi8> + return %0 : vector<128xi8> +} diff --git a/test/Target/LLVMIR/aievec.mlir b/test/Target/LLVMIR/aievec.mlir index a084f4f2a3..5285cd833c 100644 --- a/test/Target/LLVMIR/aievec.mlir +++ b/test/Target/LLVMIR/aievec.mlir @@ -436,11 +436,11 @@ llvm.func @vmax_ltbf16(%lhs: vector<32xbf16>, %rhs: vector<32xbf16>) -> vector<3 // CHECK-LABEL: <64 x i8> @vmin_ge8 llvm.func @vmin_ge8(%lhs: vector<64xi8>, %rhs: vector<64xi8>, %pred: i32) -> vector<64xi8> { - // CHECK: call { <64 x i8>, i32 } @llvm.aie2.vmin.ge8( + // CHECK: call { <64 x i8>, <2 x i32> } @llvm.aie2.vmin.ge8( // CHECK-SAME: <64 x i8> %{{[0-9]+}}, <64 x i8> %{{[0-9]+}}, i32 %{{[0-9]+}}) %0 = "xllvm.intr.aie2.vmin.ge8"(%lhs, %rhs, %pred) : - (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, i32)> - %1 = llvm.extractvalue %0[0] : !llvm.struct<(vector<64xi8>, i32)> + (vector<64xi8>, vector<64xi8>, i32) -> !llvm.struct<(vector<64xi8>, vector<2xi32>)> + %1 = llvm.extractvalue %0[0] : !llvm.struct<(vector<64xi8>, vector<2xi32>)> llvm.return %1 : vector<64xi8> } @@ -476,7 +476,7 @@ llvm.func @vmin_gebf16(%lhs: vector<32xbf16>, %rhs: vector<32xbf16>) -> vector<3 // CHECK-LABEL: declare { <32 x bfloat>, i32 } @llvm.aie2.vmax.ltbf16(<32 x bfloat>, <32 x bfloat>) -// CHECK-LABEL: declare { <64 x i8>, i32 } @llvm.aie2.vmin.ge8(<64 x i8>, <64 x i8>, i32) +// CHECK-LABEL: declare { <64 x i8>, <2 x i32> } @llvm.aie2.vmin.ge8(<64 x i8>, <64 x i8>, i32) // CHECK-LABEL: declare { <32 x i16>, i32 } @llvm.aie2.vmin.ge16(<32 x i16>, <32 x i16>, i32) // CHECK-LABEL: declare { <16 x i32>, i32 } @llvm.aie2.vmin.ge32(<16 x i32>, <16 x i32>, i32) // CHECK-LABEL: declare { <32 x bfloat>, i32 } @llvm.aie2.vmin.gebf16(<32 x bfloat>, <32 x bfloat>)