From 3b5b11da6bdc9bb103ad68165186ef1602aaadb8 Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Thu, 6 Jun 2024 17:42:28 -0700 Subject: [PATCH 1/6] Add Peano wheel Peano is open source. Use it. --- .github/workflows/buildAndTestRyzenAI.yml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/.github/workflows/buildAndTestRyzenAI.yml b/.github/workflows/buildAndTestRyzenAI.yml index 248e3aab57..5ca9fb5da0 100644 --- a/.github/workflows/buildAndTestRyzenAI.yml +++ b/.github/workflows/buildAndTestRyzenAI.yml @@ -93,16 +93,21 @@ jobs: # forever when configuring. Set the time to some arbitrary stamp in the past just to be safe. find mlir -exec touch -a -m -t 201108231405.14 {} \; + pip -q download llvm-aie \ + -f https://github.com/Xilinx/llvm-aie/releases/expanded_assets/nightly + unzip -q llvm-aie*.whl + mkdir build pushd build - export PATH=/opt/Xilinx/Vitis/2023.2/bin:/opt/Xilinx/Vitis/2023.2/aietools/bin:$PATH + export PATH=$VITIS/bin:$VITIS/aietools/bin:$PATH cmake .. -G Ninja \ -DPython3_EXECUTABLE=$(which python) \ -DLLVM_EXTERNAL_LIT=$(which lit) \ -DCMAKE_INSTALL_PREFIX=$PWD/../mlir_aie \ -DCMAKE_MODULE_PATH=$PWD/../cmake/modulesXilinx \ -DMLIR_DIR=$PWD/../mlir/lib/cmake/mlir \ + -DPEANO_INSTALL_DIR=$PWD/../llvm-aie \ $CMAKE_ARGS ninja install @@ -150,6 +155,10 @@ jobs: # forever when configuring. Set the time to some arbitrary stamp in the past just to be safe. find mlir -exec touch -a -m -t 201108231405.14 {} \; + pip -q download llvm-aie \ + -f https://github.com/Xilinx/llvm-aie/releases/expanded_assets/nightly + unzip -q llvm-aie*.whl + mkdir build pushd build @@ -160,6 +169,7 @@ jobs: -DCMAKE_INSTALL_PREFIX=$PWD/../mlir_aie \ -DCMAKE_MODULE_PATH=$PWD/../cmake/modulesXilinx \ -DMLIR_DIR=$PWD/../mlir/lib/cmake/mlir \ + -DPEANO_INSTALL_DIR=$PWD/../llvm-aie \ $CMAKE_ARGS ninja install From b558c4bbacad8b2139f8fb4642f1b21bf2ef4f35 Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Thu, 6 Jun 2024 17:58:53 -0700 Subject: [PATCH 2/6] fix filename --- .github/workflows/buildAndTestRyzenAI.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/buildAndTestRyzenAI.yml b/.github/workflows/buildAndTestRyzenAI.yml index 5ca9fb5da0..9086204ffe 100644 --- a/.github/workflows/buildAndTestRyzenAI.yml +++ b/.github/workflows/buildAndTestRyzenAI.yml @@ -95,7 +95,7 @@ jobs: pip -q download llvm-aie \ -f https://github.com/Xilinx/llvm-aie/releases/expanded_assets/nightly - unzip -q llvm-aie*.whl + unzip -q llvm_aie*.whl mkdir build pushd build From d98e3b2f885b37cb21c88dbc7b542d67d7455a05 Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Thu, 6 Jun 2024 18:06:03 -0700 Subject: [PATCH 3/6] fixup --- .github/workflows/buildAndTestRyzenAI.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/buildAndTestRyzenAI.yml b/.github/workflows/buildAndTestRyzenAI.yml index 9086204ffe..17dde515c1 100644 --- a/.github/workflows/buildAndTestRyzenAI.yml +++ b/.github/workflows/buildAndTestRyzenAI.yml @@ -157,7 +157,7 @@ jobs: pip -q download llvm-aie \ -f https://github.com/Xilinx/llvm-aie/releases/expanded_assets/nightly - unzip -q llvm-aie*.whl + unzip -q llvm_aie*.whl mkdir build pushd build From 3e2f04f3e8db2ef57c27a1bea01a5744aae119ff Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Fri, 12 Jul 2024 00:48:18 +0000 Subject: [PATCH 4/6] Add missing test guards --- test/npu-xrt/matrix_transpose/aie2.py | 2 +- test/npu-xrt/nd_memcpy_transforms/aie2.py | 2 +- test/unit_tests/aie/31_stream_core/aie.mlir | 2 +- .../aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir | 1 + .../bf16_float_add_reduce/bf16_float_add_reduce.mlir | 1 + .../aievec_tests/bf16_softmax/bf16_softmax.mlir | 1 + .../aievec_tests/bf16_softmax_2/bf16_softmax.mlir | 1 + .../aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir | 1 + .../float_add_reduce/float_add_reduce.mlir | 1 + .../float_max_reduce/float_max_reduce.mlir | 1 + .../float_min_reduce/float_min_reduce.mlir | 1 + .../floatxfloat_max_elem/floatxfloat_max_elem.mlir | 1 + .../floatxfloat_min_elem/floatxfloat_min_elem.mlir | 1 + .../aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir | 1 + .../aievec_tests/i16_abs_v32_2/i16_abs.mlir | 1 + .../aievec_tests/i16_add_reduce/i16_add_reduce.mlir | 1 + .../i16_i32_add_reduce/i16_i32_add_reduce.mlir | 1 + .../aievec_tests/i16xi16_sel/i16xi16_sel.mlir | 1 + .../i16xi16_sel_unsigned_cmp.mlir | 1 + .../aievec_tests/i32_abs_v16_2/i32_abs.mlir | 1 + .../aievec_tests/i32_add_reduce/i32_add_reduce.mlir | 1 + .../aievec_tests/i32xi32_sel/i32xi32_sel.mlir | 1 + .../i32xi32_sel_unsigned_cmp.mlir | 1 + test/unit_tests/aievec_tests/i8_abs_v64_2/i8_abs.mlir | 1 + .../aievec_tests/i8_add_reduce/i8_add_reduce.mlir | 1 + .../i8_i32_add_reduce/i8_i32_add_reduce.mlir | 1 + test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir | 1 + .../chess_compiler_tests/00_itsalive/aie.mlir | 1 - .../01_precompiled_core_function/aie.mlir | 2 +- .../02_precompiled_kernel/aie.mlir | 2 +- .../03_cascade_core_functions/aie.mlir | 2 +- .../chess_compiler_tests/04_shim_dma_kernel/aie.mlir | 2 +- .../05_shim_dma_core_function/aie.mlir | 2 +- .../07_shim_dma_core_function_with_loop/aie.mlir | 2 +- .../chess_compiler_tests/08_tile_locks/aie.mlir | 2 +- test/unit_tests/chess_compiler_tests/lit.local.cfg | 11 +++++++++++ .../chess_compiler_tests_aie2/00_itsalive/aie.mlir | 1 - .../01_precompiled_core_function/aie.mlir | 2 +- .../02_precompiled_kernel/aie.mlir | 2 +- .../03_cascade_core_functions/aie.mlir | 2 +- .../04_shim_dma_kernel/aie.mlir | 2 +- .../05_shim_dma_core_function/aie.mlir | 2 +- .../07_shim_dma_core_function_with_loop/aie.mlir | 1 - .../chess_compiler_tests_aie2/08_tile_locks/aie.mlir | 2 +- .../09_memtile_locks/aie.mlir | 2 +- .../chess_compiler_tests_aie2/lit.local.cfg | 11 +++++++++++ 46 files changed, 63 insertions(+), 20 deletions(-) create mode 100755 test/unit_tests/chess_compiler_tests/lit.local.cfg create mode 100755 test/unit_tests/chess_compiler_tests_aie2/lit.local.cfg diff --git a/test/npu-xrt/matrix_transpose/aie2.py b/test/npu-xrt/matrix_transpose/aie2.py index 6ee3c853d3..e95db67d5b 100644 --- a/test/npu-xrt/matrix_transpose/aie2.py +++ b/test/npu-xrt/matrix_transpose/aie2.py @@ -5,7 +5,7 @@ # # (c) Copyright 2024 AMD Inc. -# REQUIRES: ryzen_ai +# REQUIRES: ryzen_ai, chess # # RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/kernel.cc -o ./kernel.o # RUN: %python %S/aie2.py > ./aie2.mlir diff --git a/test/npu-xrt/nd_memcpy_transforms/aie2.py b/test/npu-xrt/nd_memcpy_transforms/aie2.py index 634ec08a8b..1dc30ad47f 100644 --- a/test/npu-xrt/nd_memcpy_transforms/aie2.py +++ b/test/npu-xrt/nd_memcpy_transforms/aie2.py @@ -5,7 +5,7 @@ # # (c) Copyright 2024 AMD Inc. -# REQUIRES: ryzen_ai +# REQUIRES: ryzen_ai, chess # # RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/kernel.cc -o ./kernel.o # RUN: %python %S/aie2.py > ./aie2.mlir diff --git a/test/unit_tests/aie/31_stream_core/aie.mlir b/test/unit_tests/aie/31_stream_core/aie.mlir index 2565b350be..99250e0ef5 100644 --- a/test/unit_tests/aie/31_stream_core/aie.mlir +++ b/test/unit_tests/aie/31_stream_core/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: peano, !hsa +// REQUIRES: peano, chess, !hsa // RUN: %PYTHON aiecc.py --aiesim --no-xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir index a8350e2f3d..2bdffec779 100644 --- a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir index 9bde9636b5..be27ab5d66 100644 --- a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/bf16_softmax/bf16_softmax.mlir b/test/unit_tests/aievec_tests/bf16_softmax/bf16_softmax.mlir index b7c6f21151..aecd66bc22 100644 --- a/test/unit_tests/aievec_tests/bf16_softmax/bf16_softmax.mlir +++ b/test/unit_tests/aievec_tests/bf16_softmax/bf16_softmax.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. -c %aie_runtime_lib%/AIE2/lut_based_ops.cpp -o lut_based_ops.cpp.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. -c dut.cc -o dut.cc.o diff --git a/test/unit_tests/aievec_tests/bf16_softmax_2/bf16_softmax.mlir b/test/unit_tests/aievec_tests/bf16_softmax_2/bf16_softmax.mlir index 55c787e4d1..d3963a3a68 100644 --- a/test/unit_tests/aievec_tests/bf16_softmax_2/bf16_softmax.mlir +++ b/test/unit_tests/aievec_tests/bf16_softmax_2/bf16_softmax.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. -c %aie_runtime_lib%/AIE2/lut_based_ops.cpp -o lut_based_ops.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIEARCH__=20 -D__AIENGINE__ -I. -c dut.cc -o dut.o diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir index cbd8e40706..73158771df 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir index 3f44b5f81e..cec43dff2f 100644 --- a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir index 97450ec225..9ad9f4dc74 100644 --- a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir index a63e9207eb..a8b888d792 100644 --- a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir index 918809704d..c956e8ecd2 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir index 7fc4736606..235780b822 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir index d2ca288cca..b1254b6609 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i16_abs_v32_2/i16_abs.mlir b/test/unit_tests/aievec_tests/i16_abs_v32_2/i16_abs.mlir index 02ff34e209..bf397b1275 100644 --- a/test/unit_tests/aievec_tests/i16_abs_v32_2/i16_abs.mlir +++ b/test/unit_tests/aievec_tests/i16_abs_v32_2/i16_abs.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIE_ARCH__=20 -D__AIENGINE__ -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIE_ARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir index 10799400ac..df6573af29 100644 --- a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir index df8606da2b..c87572146d 100644 --- a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir index b9850b9de8..854c76bacb 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir index 4114c44a1b..b321a2c7d3 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i32_abs_v16_2/i32_abs.mlir b/test/unit_tests/aievec_tests/i32_abs_v16_2/i32_abs.mlir index 0fd4554181..521c4d449d 100644 --- a/test/unit_tests/aievec_tests/i32_abs_v16_2/i32_abs.mlir +++ b/test/unit_tests/aievec_tests/i32_abs_v16_2/i32_abs.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIE_ARCH__=20 -D__AIENGINE__ -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIE_ARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir index 234e9807aa..9b4e4f90ad 100644 --- a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir index 25a8f5063b..76ddef7756 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir index 2ca5370791..c77521eb9f 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i8_abs_v64_2/i8_abs.mlir b/test/unit_tests/aievec_tests/i8_abs_v64_2/i8_abs.mlir index 0839fd2179..96cedad2b6 100644 --- a/test/unit_tests/aievec_tests/i8_abs_v64_2/i8_abs.mlir +++ b/test/unit_tests/aievec_tests/i8_abs_v64_2/i8_abs.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIE_ARCH__=20 -D__AIENGINE__ -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I%aie_runtime_lib%/AIE2 -I %aietools/include -D__AIE_ARCH__=20 -D__AIENGINE__ -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir index 946d81fe72..26dc64e40c 100644 --- a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir index 5b5cccbec0..fe4a0459b6 100644 --- a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir index eab08d1831..861d5db4b8 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir @@ -1,3 +1,4 @@ +// REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64" --convert-vector-to-aievec="aie-target=aie2" -lower-affine | aie-translate -aie2=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. -c dut.cc -o dut.o // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc work/dut.o diff --git a/test/unit_tests/chess_compiler_tests/00_itsalive/aie.mlir b/test/unit_tests/chess_compiler_tests/00_itsalive/aie.mlir index 9b388d7985..89201e71d6 100644 --- a/test/unit_tests/chess_compiler_tests/00_itsalive/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/00_itsalive/aie.mlir @@ -8,7 +8,6 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license // REQUIRES: peano // RUN: %PYTHON aiecc.py --no-unified --xchesscc --xbridge %s // RUN: %PYTHON aiecc.py --unified --xchesscc --xbridge %s diff --git a/test/unit_tests/chess_compiler_tests/01_precompiled_core_function/aie.mlir b/test/unit_tests/chess_compiler_tests/01_precompiled_core_function/aie.mlir index 6aa0dea828..6a3d28b439 100644 --- a/test/unit_tests/chess_compiler_tests/01_precompiled_core_function/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/01_precompiled_core_function/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --xbridge --xchesscc %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests/02_precompiled_kernel/aie.mlir b/test/unit_tests/chess_compiler_tests/02_precompiled_kernel/aie.mlir index 8d9e593936..0d5e363723 100644 --- a/test/unit_tests/chess_compiler_tests/02_precompiled_kernel/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/02_precompiled_kernel/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: xchesscc_wrapper aie +l aie.mlir.prj/core_1_3.bcf %S/kernel.cc -o custom_1_3.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests/03_cascade_core_functions/aie.mlir b/test/unit_tests/chess_compiler_tests/03_cascade_core_functions/aie.mlir index f7058f1c9d..3da941947c 100644 --- a/test/unit_tests/chess_compiler_tests/03_cascade_core_functions/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/03_cascade_core_functions/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir b/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir index e91eac6dd6..7d89b95368 100644 --- a/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: xchesscc_wrapper aie +l aie.mlir.prj/core_7_3.bcf %S/kernel.cc -o custom_7_3.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir b/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir index 6a97ff3db9..b0d088e2a0 100644 --- a/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir b/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir index 6ce83815d6..0d654c4c16 100644 --- a/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // clang -O2 --target=aie -c %S/kernel.cc -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index c28f87e766..0d0371258d 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -9,7 +9,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: aie.mlir.prj/aiesim.sh | FileCheck %s diff --git a/test/unit_tests/chess_compiler_tests/lit.local.cfg b/test/unit_tests/chess_compiler_tests/lit.local.cfg new file mode 100755 index 0000000000..ea280c1d7c --- /dev/null +++ b/test/unit_tests/chess_compiler_tests/lit.local.cfg @@ -0,0 +1,11 @@ +# +# This file is licensed under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +# +# Copyright (C) 2024, Advanced Micro Devices, Inc. + +config.unsupported = [] + +if not "chess" in config.available_features: + config.unsupported = True diff --git a/test/unit_tests/chess_compiler_tests_aie2/00_itsalive/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/00_itsalive/aie.mlir index ac78980548..d6ae2a0c09 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/00_itsalive/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/00_itsalive/aie.mlir @@ -8,7 +8,6 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license // REQUIRES: peano // RUN: %PYTHON aiecc.py --no-unified --xchesscc --xbridge %s // RUN: %PYTHON aiecc.py --unified --xchesscc --xbridge %s diff --git a/test/unit_tests/chess_compiler_tests_aie2/01_precompiled_core_function/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/01_precompiled_core_function/aie.mlir index 1e8eddcbcf..5c02d9bcf9 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/01_precompiled_core_function/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/01_precompiled_core_function/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie2 -c %S/kernel.cc // RUN: %PYTHON aiecc.py -v --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests_aie2/02_precompiled_kernel/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/02_precompiled_kernel/aie.mlir index 28127efa6c..d5f8928036 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/02_precompiled_kernel/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/02_precompiled_kernel/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: xchesscc_wrapper aie2 +l aie.mlir.prj/core_1_3.bcf %S/kernel.cc -o custom_1_3.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests_aie2/03_cascade_core_functions/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/03_cascade_core_functions/aie.mlir index 1dd02738aa..701985a3b3 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/03_cascade_core_functions/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/03_cascade_core_functions/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie2 -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir index a2dbedf747..46e1085856 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir @@ -9,7 +9,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: xchesscc_wrapper aie2 +l aie.mlir.prj/core_7_3.bcf %S/kernel.cc -o custom_7_3.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir index feba4e23eb..ea207f445a 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir @@ -9,7 +9,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: xchesscc_wrapper aie2 -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir index de3345fadb..e79ce28706 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir @@ -9,7 +9,6 @@ //===----------------------------------------------------------------------===// // clang -O2 --target=aie -c %S/kernel.cc -// REQUIRES: valid_xchess_license // RUN: xchesscc_wrapper aie2 -c %S/kernel.cc // RUN: %PYTHON aiecc.py --aiesim --chesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index df46768688..0846b45e17 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -9,7 +9,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s diff --git a/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir index 30b7813950..d11aa1b990 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir @@ -9,7 +9,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: valid_xchess_license, !hsa +// REQUIRES: !hsa // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s diff --git a/test/unit_tests/chess_compiler_tests_aie2/lit.local.cfg b/test/unit_tests/chess_compiler_tests_aie2/lit.local.cfg new file mode 100755 index 0000000000..ea280c1d7c --- /dev/null +++ b/test/unit_tests/chess_compiler_tests_aie2/lit.local.cfg @@ -0,0 +1,11 @@ +# +# This file is licensed under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +# +# Copyright (C) 2024, Advanced Micro Devices, Inc. + +config.unsupported = [] + +if not "chess" in config.available_features: + config.unsupported = True From aa3053214a8fe64a8dff56ff5b949d782cb94b2a Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Fri, 12 Jul 2024 20:44:03 +0000 Subject: [PATCH 5/6] Limit test parallelism --- test/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 0c0b94d415..2b4be7de2c 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -114,6 +114,6 @@ set(TEST_DEPENDS add_lit_testsuite(check-aie "Running the aie regression tests" ${CMAKE_CURRENT_BINARY_DIR} DEPENDS ${TEST_DEPENDS} - ARGS "-sv --timeout 600" + ARGS "-sv --timeout 600 -j 3" ) set_target_properties(check-aie PROPERTIES FOLDER "Tests") From 2d68e3c49af76d73bdf09d3842004f75c881de88 Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Wed, 7 Aug 2024 23:34:02 +0000 Subject: [PATCH 6/6] disable Vitis --- .github/workflows/buildAndTestRyzenAI.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/buildAndTestRyzenAI.yml b/.github/workflows/buildAndTestRyzenAI.yml index 17dde515c1..51e460de46 100644 --- a/.github/workflows/buildAndTestRyzenAI.yml +++ b/.github/workflows/buildAndTestRyzenAI.yml @@ -38,7 +38,8 @@ concurrency: env: DEBIAN_FRONTEND: noninteractive XILINXD_LICENSE_FILE: /opt/xilinx/Xilinx.lic - VITIS: /opt/Xilinx/Vitis/2023.2 + VITIS: /none + #/opt/Xilinx/Vitis/2023.2 CMAKE_ARGS: | -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \ -DCMAKE_C_COMPILER_LAUNCHER=ccache \