diff --git a/sim/spice/full_spice_sim.cir b/sim/spice/full_spice_sim.cir index 9844f9b..f920be2 100644 --- a/sim/spice/full_spice_sim.cir +++ b/sim/spice/full_spice_sim.cir @@ -32,9 +32,6 @@ xtt + uio_in2 + uio_in3 + uio_in4 -+ uio_in5 -+ uio_in6 -+ uio_in7 + uio_oe0 + uio_oe1 + uio_oe2 @@ -54,6 +51,7 @@ xtt + uo_out5 + uo_out6 + vcca ++ ua3 + ui_in3 + ua2 + ui_in5 @@ -63,11 +61,13 @@ xtt + ua1 + uo_out7 + ui_in0 ++ uio_in7 + uo_out2 + uo_out1 ++ uio_in6 + uio_out0 ++ uio_in5 + ui_in2 -+ ua3 + ui_in4 + 0 + vcc @@ -87,7 +87,9 @@ CBpin boutpin GND 5p Rua0pin ua0pin GND 1000k RRpin routpin GND 1000k RGpin goutpin GND 1000k -RBpin boutpin GND 1000k +* This is the 'external' pull-up resistor for the blue SEGDAC's VoutB: +RBpin boutpin vcc 1650 +* RBpin boutpin GND 1000k **** End of the DAC and its subcircuits. Begin test circuit **** @@ -130,15 +132,15 @@ vcca vcca 0 {vapwr} * Vin6 ui_in6 GND PULSE 0.0 {vcc} 120n {rise} {fall} {h6} {p6} * Vin7 ui_in7 GND PULSE 0.0 {vcc} 120n {rise} {fall} {h0} {p0} -* * --- MODE 2: BARS (div-2): -* Vin0 ui_in0 GND dc {vcc} -* Vin1 ui_in1 GND dc 0.0 -* Vin2 ui_in2 GND dc {vcc} -* Vin3 ui_in3 GND dc 0.0 -* Vin4 ui_in4 GND dc 0.0 -* Vin5 ui_in5 GND dc {vcc} -* Vin6 ui_in6 GND dc 0.0 -* Vin7 ui_in7 GND dc 0.0 +* --- MODE 2: BARS (div-2): +Vin0 ui_in0 GND dc {vcc} +Vin1 ui_in1 GND dc 0.0 +Vin2 ui_in2 GND dc {vcc} +Vin3 ui_in3 GND dc 0.0 +Vin4 ui_in4 GND dc 0.0 +Vin5 ui_in5 GND dc {vcc} +Vin6 ui_in6 GND dc 0.0 +Vin7 ui_in7 GND dc 0.0 * * --- MODE 5: XOR2: * Vin0 ui_in0 GND dc 0.0 @@ -150,15 +152,15 @@ vcca vcca 0 {vapwr} * Vin6 ui_in6 GND dc {vcc} * Vin7 ui_in7 GND dc 0.0 -* --- MODE 1: RAMP, on all 3 channels" -Vin0 ui_in0 GND dc {vcc} -Vin1 ui_in1 GND dc {vcc} -Vin2 ui_in2 GND dc 0.0 -Vin3 ui_in3 GND dc 0.0 -Vin4 ui_in4 GND dc {vcc} -Vin5 ui_in5 GND dc 0.0 -Vin6 ui_in6 GND dc 0.0 -Vin7 ui_in7 GND dc 0.0 +* * --- MODE 1: RAMP, on all 3 channels" +* Vin0 ui_in0 GND dc {vcc} +* Vin1 ui_in1 GND dc {vcc} +* Vin2 ui_in2 GND dc 0.0 +* Vin3 ui_in3 GND dc 0.0 +* Vin4 ui_in4 GND dc {vcc} +* Vin5 ui_in5 GND dc 0.0 +* Vin6 ui_in6 GND dc 0.0 +* Vin7 ui_in7 GND dc 0.0 * * Digital clock signal * aclock 0 clk clock diff --git a/sim/spice/mixed.cir b/sim/spice/mixed.cir index 74a94c5..3d18da3 100644 --- a/sim/spice/mixed.cir +++ b/sim/spice/mixed.cir @@ -35,6 +35,9 @@ adut * -- in turn that means you'll need to ensure the `.subckt csdac_nom_parax ...` * port list matches what the instances of csdac_nom_parax expect. +.include "../../mag/segdac.sim.spice" +.include "../../mag/thermo2bit.sim.spice" + * This is the model of estimated TT08 pin loading: .include "tt08pin.spice" @@ -52,10 +55,14 @@ Rvsync vsync GND 10000000 Rhblank hblank GND 10000000 Rvblank vblank GND 10000000 +* NOTE: VbiasR is pulled slightly by being an output, making VnegR slightly different from VnegG. + Xua0pin ua0pin VbiasR GND vcca tt08pin XRpin routpin VnegR GND vcca tt08pin XGpin goutpin VnegG GND vcca tt08pin -XBpin boutpin VnegB GND vcca tt08pin +XBpin boutpin VoutB GND vcca tt08pin +* NOTE: VoutB is the odd one out (instead of VnegB) because the blue channel's +* implementation is different (i.e. using segdac instead of csdac_nom)... * Additional pin loading: Cua0pin ua0pin GND 5p @@ -65,7 +72,8 @@ CBpin boutpin GND 5p Rua0pin ua0pin GND 1000k RRpin routpin GND 1000k RGpin goutpin GND 1000k -RBpin boutpin GND 1000k +* This is the 'external' pull-up resistor for the blue SEGDAC's VoutB: +RBpin boutpin vcc 1650 XR_dac vcc GND + rn7 r7 rn6 r6 rn5 r5 rn4 r4 rn3 r3 rn2 r2 rn1 r1 rn0 r0 @@ -77,15 +85,40 @@ XG_dac vcc GND + VbiasG VnegG VposG + csdac_nom_parax -XB_dac vcc GND -+ bn7 b7 bn6 b6 bn5 b5 bn4 b4 bn3 b3 bn2 b2 bn1 b1 bn0 b0 -+ VbiasB VnegB VposB -+ csdac_nom_parax +* This is the blue channel's SEGDAC: +* NOTE: +* - uio_in[5..7] are bias1..3 +* - VoutB is the output of the CURRENT, and it needs an (external) +* pull-up resistor to convert it to a voltage; 1k-2k should do it. +* - VbiasB is unused by the circuit, but recorded simulation debugging. +Xsegdac_0 vcc GND ++ uio_in5 uio_in6 uio_in7 ++ sa1 sa2 sa3 ++ VbiasB ++ VoutB ++ sb1 sb2 sb3 ++ sc1 sc2 sc3 ++ sd1 sd2 sd3 ++ segdac_parax + + +* These are the four 2bit-to-unary decoders, connected to the +* blue channel's negative output bits (bn0..7): +Xthermo_a bn0 bn1 sa3 vcc GND sa1 sa2 thermo2bit_parax +Xthermo_b bn2 bn3 sb3 vcc GND sb1 sb2 thermo2bit_parax +Xthermo_c bn4 bn5 sc3 vcc GND sc1 sc2 thermo2bit_parax +Xthermo_d bn6 bn7 sd3 vcc GND sd1 sd2 thermo2bit_parax + +* XB_dac vcc GND +* + bn7 b7 bn6 b6 bn5 b5 bn4 b4 bn3 b3 bn2 b2 bn1 b1 bn0 b0 +* + VbiasB VnegB VposB +* + csdac_nom_parax **** End of the DAC and its subcircuits. Begin test circuit **** .param vcc=1.8 vcc vcc 0 {vcc} + .param vapwr=3.3 vcca vcca 0 {vapwr} @@ -136,26 +169,26 @@ Vreset rst_n GND PULSE {vcc} 0.0 10n 1n 1n 80n 34m * Vin6 ui_in6 GND dc 0.0 * Vin7 ui_in7 GND dc 0.0 -* * --- MODE 5: XOR2, starting line 32: -* Vin0 ui_in0 GND dc 0.0 -* Vin1 ui_in1 GND dc {vcc} -* Vin2 ui_in2 GND dc 0.0 -* Vin3 ui_in3 GND dc {vcc} -* Vin4 ui_in4 GND dc {vcc} -* Vin5 ui_in5 GND dc 0.0 -* Vin6 ui_in6 GND dc {vcc} -* Vin7 ui_in7 GND dc 0.0 - -* --- MODE 1: RAMP, on all 3 channels" -Vin0 ui_in0 GND dc {vcc} +* --- MODE 5: XOR2, starting line 32: +Vin0 ui_in0 GND dc 0.0 Vin1 ui_in1 GND dc {vcc} Vin2 ui_in2 GND dc 0.0 -Vin3 ui_in3 GND dc 0.0 +Vin3 ui_in3 GND dc {vcc} Vin4 ui_in4 GND dc {vcc} Vin5 ui_in5 GND dc 0.0 -Vin6 ui_in6 GND dc 0.0 +Vin6 ui_in6 GND dc {vcc} Vin7 ui_in7 GND dc 0.0 +* * --- MODE 1: RAMP, on all 3 channels: +* Vin0 ui_in0 GND dc {vcc} +* Vin1 ui_in1 GND dc {vcc} +* Vin2 ui_in2 GND dc 0.0 +* Vin3 ui_in3 GND dc 0.0 +* Vin4 ui_in4 GND dc {vcc} +* Vin5 ui_in5 GND dc 0.0 +* Vin6 ui_in6 GND dc 0.0 +* Vin7 ui_in7 GND dc 0.0 + * * --- Mode 1: RAMP: Ramp generator with primary=X, secondary=Y, fade=frame# --- * Vin0 ui_in0 GND dc 0.0 ; Primary... * Vin1 ui_in1 GND dc 0.0 ; ...= 0 (Red primary, Green secondary, Blue fade) @@ -166,13 +199,24 @@ Vin7 ui_in7 GND dc 0.0 * Vin6 ui_in6 GND dc 0.0 ; ...= 011 (XOR) * Vin7 ui_in7 GND dc 0.0 ; Timing = 0 (standard VGA) +* Select a mid-range bias voltage for the blue channel's SEGDAC: +Vuio_in5 uio_in5 GND dc 0.0 ; ENABLE bias1. +Vuio_in6 uio_in6 GND dc {vcc} ; Disable bias2. +Vuio_in7 uio_in7 GND dc {vcc} ; Disable bias3. + .control + * NOTE: VoutB is the odd one out (instead of VnegB) because the blue channel's + * implementation is different (i.e. using segdac instead of csdac_nom)... save + vcc vcca + VposR VnegR VbiasR + VposG VnegG VbiasG - + VposB VnegB VbiasB + + VoutB VbiasB + + sa1 sa2 sa3 + + sb1 sb2 sb3 + + sc1 sc2 sc3 + + sd1 sd2 sd3 + ua0pin routpin goutpin boutpin + hsync vsync + r7 r6 r5 r4 r3 r2 r1 r0 @@ -217,7 +261,11 @@ Vin7 ui_in7 GND dc 0.0 + vcc vcca + VposR VnegR VbiasR + VposG VnegG VbiasG - + VposB VnegB VbiasB + + VoutB VbiasB + + sa1 sa2 sa3 + + sb1 sb2 sb3 + + sc1 sc2 sc3 + + sd1 sd2 sd3 + ua0pin routpin goutpin boutpin + hsync vsync + r7 r6 r5 r4 r3 r2 r1 r0 diff --git a/xschem/render.py b/xschem/render.py index 3051901..21eee69 100644 --- a/xschem/render.py +++ b/xschem/render.py @@ -31,8 +31,9 @@ # scale_max = 1.80 # --- tt08-vga-fun csdac_nom range: --- -scale_min = 0.83 -scale_max = 1.80 +# NOTE: These figures are now an array, to allow a different scale for each channel (R,G,B): +scale_min = [0.83, 0.83, 0.63] +scale_max = [1.80, 1.80, 1.80] # # --- Typical amplified outputs: --- # scale_min = 0.30 @@ -107,8 +108,12 @@ def pwlerp(time_points, output_values, interval=0.1): # -- Raw (unbuffered) DAC output: # scale_min = 0.00 # scale_max = 1.67 -sr = scale_max-scale_min -transform = lambda c: int(255*max(0,min(1,(c-scale_min)/sr))) +srr = scale_max[0]-scale_min[0] +srg = scale_max[1]-scale_min[1] +srb = scale_max[2]-scale_min[2] +transform_r = lambda c: int(255*max(0,min(1,(c-scale_min[0])/srr))) +transform_g = lambda c: int(255*max(0,min(1,(c-scale_min[1])/srg))) +transform_b = lambda c: int(255*max(0,min(1,(c-scale_min[2])/srb))) # -- Buffered DAC output: # scale_min = 0.3 # scale_max = 1.4 @@ -130,9 +135,9 @@ def pwlerp(time_points, output_values, interval=0.1): n = min(n,r,g,b) x = max(x,r,g,b) # Now scale them to the 0..255 range: - r = transform(r) - g = transform(g) - b = transform(b) + r = transform_r(r) + g = transform_g(g) + b = transform_b(b) f.write(f'{r} {g} {b} ') if i % 800 == 799: f.write('\n') # breakpoint() diff --git a/xschem/simulation/tb_segdac.spice b/xschem/simulation/tb_segdac.spice index de6ccd0..866f8b0 100644 --- a/xschem/simulation/tb_segdac.spice +++ b/xschem/simulation/tb_segdac.spice @@ -10,8 +10,8 @@ XSC vcc_nom vss sc3 n5 sc2 sc1 n4 thermo2bit XSD vcc_nom vss sd3 n7 sd2 sd1 n6 thermo2bit x2 vout net1 vss tt08pin C1 vout vss 3p m=1 -XR1 net1 net2 vss sky130_fd_pr__res_high_po_5p73 L=28 mult=1 m=1 VCurrent vcc_nom net2 0 +R1 net2 vout 1.65k m=1 **** begin user architecture code @@ -188,31 +188,31 @@ XM3 Vbias bias3 vcc vcc sky130_fd_pr__pfet_01v8 L=2 W=0.5 nf=1 ad='int((nf+1)/2) *.iopin VCC *.iopin VSS *.opin s1 -R1 s2 b1 0 m=1 -XM1 net1 b0 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMA1 net1 b0 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net1 b0 net2 VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMA3 net1 b0 net2 VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM3 net1 b1 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMA2 net1 b1 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM4 net2 b1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMA4 net2 b1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 s3 net1 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMA5 s3 net1 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM6 s3 net1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMA6 s3 net1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 s1 net3 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMO5 s1 net3 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 s1 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMO6 s1 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM7 net4 b0 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMO1 net4 b0 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net3 b1 net4 VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMO2 net3 b1 net4 VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net3 b0 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMO3 net3 b0 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net3 b1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' +XMO4 net3 b1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' + ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +R1 b1 s2 sky130_fd_pr__res_generic_m4 W=1 L=1 m=1 .ends diff --git a/xschem/simulation/tb_segdac_pex.spice b/xschem/simulation/tb_segdac_pex.spice new file mode 100644 index 0000000..33224a6 --- /dev/null +++ b/xschem/simulation/tb_segdac_pex.spice @@ -0,0 +1,277 @@ +** sch_path: /home/anton/projects/tt08-vga-fun/xschem/tb_segdac_pex.sch +**.subckt tb_segdac_pex +Vvcc1 vcc1 GND 1.8 +Vvss vss GND 0 +Vvccnom vcc1 vcc_nom 0 +x1 sa1 vcc_nom sa2 vss sa3 net1 sb1 sb2 Vbias sb3 sc1 sc2 sc3 sd1 sd2 sd3 vss vcc_nom vcc_nom segdac +XSA vcc_nom vss sa3 n1 sa2 sa1 n0 thermo2bit +XSB vcc_nom vss sb3 n3 sb2 sb1 n2 thermo2bit +XSC vcc_nom vss sc3 n5 sc2 sc1 n4 thermo2bit +XSD vcc_nom vss sd3 n7 sd2 sd1 n6 thermo2bit +x2 vout net1 vss tt08pin +C1 vout vss 3p m=1 +VCurrent vcc_nom net2 0 +R1 net2 vout 1.65k m=1 +Vvccpex vcc1 vcc_pex 0 +x3 vcc_pex vss vss vcc_pex vcc_pex sa1_pex sa2_pex sa3_pex Vbias_pex net3 sb1_pex sb2_pex sb3_pex sc1_pex sc2_pex sc3_pex sd1_pex ++ sd2_pex sd3_pex segdac_parax +XSA1 n0 n1 sa3_pex vcc_pex vss sa1_pex sa2_pex thermo2bit_parax +XSB1 n2 n3 sb3_pex vcc_pex vss sb1_pex sb2_pex thermo2bit_parax +XSC1 n4 n5 sc3_pex vcc_pex vss sc1_pex sc2_pex thermo2bit_parax +XSD1 n6 n7 sd3_pex vcc_pex vss sd1_pex sd2_pex thermo2bit_parax +x4 vout_pex net3 vss tt08pin +C2 vout_pex vss 3p m=1 +VCurrentpex vcc_pex net4 0 +R2 net4 vout_pex 1.65k m=1 +**** begin user architecture code + + + +.param singlebits=0 +.IF (singlebits == 1) +* Mode to just test each binary-weighted level: +Vxp0 p0 GND pulse 0v 1.8v 1u 1n 1n 1u 10u +Vxp1 p1 GND pulse 0v 1.8v 2u 1n 1n 1u 10u +Vxp2 p2 GND pulse 0v 1.8v 3u 1n 1n 1u 10u +Vxp3 p3 GND pulse 0v 1.8v 4u 1n 1n 1u 10u +Vxp4 p4 GND pulse 0v 1.8v 5u 1n 1n 1u 10u +Vxp5 p5 GND pulse 0v 1.8v 6u 1n 1n 1u 10u +Vxp6 p6 GND pulse 0v 1.8v 7u 1n 1n 1u 10u +Vxp7 p7 GND pulse 0v 1.8v 8u 1n 1n 1u 10u +Vxn0 n0 GND pulse 1.8v 0v 1u 1n 1n 1u 10u +Vxn1 n1 GND pulse 1.8v 0v 2u 1n 1n 1u 10u +Vxn2 n2 GND pulse 1.8v 0v 3u 1n 1n 1u 10u +Vxn3 n3 GND pulse 1.8v 0v 4u 1n 1n 1u 10u +Vxn4 n4 GND pulse 1.8v 0v 5u 1n 1n 1u 10u +Vxn5 n5 GND pulse 1.8v 0v 6u 1n 1n 1u 10u +Vxn6 n6 GND pulse 1.8v 0v 7u 1n 1n 1u 10u +Vxn7 n7 GND pulse 1.8v 0v 8u 1n 1n 1u 10u +.ELSEIF (singlebits == 0) +* Mode to test full 0..255 trange: +Vxp0 p0 GND pulse 1.8v 0v 0n 1n 1n 39n 80n +Vxp1 p1 GND pulse 1.8v 0v 0n 1n 1n 79n 160n +Vxp2 p2 GND pulse 1.8v 0v 0n 1n 1n 159n 320n +Vxp3 p3 GND pulse 1.8v 0v 0n 1n 1n 319n 640n +Vxp4 p4 GND pulse 1.8v 0v 0n 1n 1n 639n 1280n +Vxp5 p5 GND pulse 1.8v 0v 0n 1n 1n 1279n 2560n +Vxp6 p6 GND pulse 1.8v 0v 0n 1n 1n 2559n 5120n +Vxp7 p7 GND pulse 1.8v 0v 0n 1n 1n 5119n 10240n +Vxn0 n0 GND pulse 0v 1.8v 0n 1n 1n 39n 80n +Vxn1 n1 GND pulse 0v 1.8v 0n 1n 1n 79n 160n +Vxn2 n2 GND pulse 0v 1.8v 0n 1n 1n 159n 320n +Vxn3 n3 GND pulse 0v 1.8v 0n 1n 1n 319n 640n +Vxn4 n4 GND pulse 0v 1.8v 0n 1n 1n 639n 1280n +Vxn5 n5 GND pulse 0v 1.8v 0n 1n 1n 1279n 2560n +Vxn6 n6 GND pulse 0v 1.8v 0n 1n 1n 2559n 5120n +Vxn7 n7 GND pulse 0v 1.8v 0n 1n 1n 5119n 10240n +.ENDIF + +.options savecurrents +.control + + * If using Monte Carlo, change to repeat to (say) 5: + repeat 1 + save all + tran 1n 12.8u + write tb_segdac_pex.raw + + i(vvss) vcc1 vbias vout i(vvccnom) i(vcurrent) + + p0 p1 p2 p3 p4 p5 p6 p7 + + sa1 sa2 sa3 + + sb1 sb2 sb3 + + sc1 sc2 sc3 + + sd1 sd2 sd3 + + vbias_pex vout_pex i(vvccpex) i(vcurrentpex) + + p0 p1 p2 p3 p4 p5 p6 p7 + + sa1_pex sa2_pex sa3_pex + + sb1_pex sb2_pex sb3_pex + + sc1_pex sc2_pex sc3_pex + + sd1_pex sd2_pex sd3_pex + + * + i(voutload) + set appendwrite + reset + end + +* save all +* *reset +* *alterparam MPW=4 +* *alterparam MMW=4 +* tran 1n 12.8u +* write 11.raw i(vvcc) i(vvss) vpos vneg vbias + +* set appendwrite +* alterparam MPW=4 +* alterparam MMW=4 +* reset +* tran 1n 12.8u +* write 11.raw i(vvcc) i(vvss) vpos vneg vbias + +.endc + + + + +.lib /home/anton/.volare/sky130A/libs.tech/ngspice/sky130.lib.spice tt +.include /home/anton/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice + +**** end user architecture code +**.ends + +* expanding symbol: segdac.sym # of pins=19 +** sym_path: /home/anton/projects/tt08-vga-fun/xschem/segdac.sym +** sch_path: /home/anton/projects/tt08-vga-fun/xschem/segdac.sch +.subckt segdac sa1 vcc sa2 vss sa3 Vout sb1 sb2 Vbias sb3 sc1 sc2 sc3 sd1 sd2 sd3 bias1 bias2 bias3 +*.iopin vcc +*.iopin vss +*.opin Vout +*.opin Vbias +*.ipin sa1 +*.ipin sa2 +*.ipin sa3 +*.ipin sb1 +*.ipin sb2 +*.ipin sb3 +*.ipin sc1 +*.ipin sc2 +*.ipin sc3 +*.ipin sd1 +*.ipin sd2 +*.ipin sd3 +*.ipin bias1 +*.ipin bias2 +*.ipin bias3 +XMmirror Vbias Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.5 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMia1 net1 Vbias vss vss sky130_fd_pr__nfet_01v8 L=5 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMia2 net2 Vbias vss vss sky130_fd_pr__nfet_01v8 L=5 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMia3 net3 Vbias vss vss sky130_fd_pr__nfet_01v8 L=5 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsa1 Vout sa1 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsa2 Vout sa2 net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsa3 Vout sa3 net3 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMib1 net4 Vbias vss vss sky130_fd_pr__nfet_01v8 L=1.2 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMib2 net5 Vbias vss vss sky130_fd_pr__nfet_01v8 L=1.2 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMib3 net6 Vbias vss vss sky130_fd_pr__nfet_01v8 L=1.2 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsb1 Vout sb1 net4 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsb2 Vout sb2 net5 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsb3 Vout sb3 net6 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMic1 net7 Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMic2 net8 Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMic3 net9 Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsc1 Vout sc1 net7 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsc2 Vout sc2 net8 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsc3 Vout sc3 net9 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMid1 net10 Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.3 W=2.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMid2 net11 Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.3 W=2.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMid3 net12 Vbias vss vss sky130_fd_pr__nfet_01v8 L=0.3 W=2.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsd1 Vout sd1 net10 vss sky130_fd_pr__nfet_01v8 L=0.2 W=3.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsd2 Vout sd2 net11 vss sky130_fd_pr__nfet_01v8 L=0.2 W=3.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMsd3 Vout sd3 net12 vss sky130_fd_pr__nfet_01v8 L=0.2 W=3.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XM1 Vbias bias1 vcc vcc sky130_fd_pr__pfet_01v8 L=0.5 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XM2 Vbias bias2 vcc vcc sky130_fd_pr__pfet_01v8 L=1 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XM3 Vbias bias3 vcc vcc sky130_fd_pr__pfet_01v8 L=2 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +.ends + + +* expanding symbol: thermo2bit.sym # of pins=7 +** sym_path: /home/anton/projects/tt08-vga-fun/xschem/thermo2bit.sym +** sch_path: /home/anton/projects/tt08-vga-fun/xschem/thermo2bit.sch +.subckt thermo2bit VCC VSS s3 b1 s2 s1 b0 +*.ipin b1 +*.opin s2 +*.ipin b0 +*.opin s3 +*.iopin VCC +*.iopin VSS +*.opin s1 +XMA1 net1 b0 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMA3 net1 b0 net2 VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMA2 net1 b1 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMA4 net2 b1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMA5 s3 net1 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMA6 s3 net1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMO5 s1 net3 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMO6 s1 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMO1 net4 b0 VCC VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMO2 net3 b1 net4 VCC sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMO3 net3 b0 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XMO4 net3 b1 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +R1 b1 s2 sky130_fd_pr__res_generic_m4 W=1 L=1 m=1 +.ends + + +* expanding symbol: tt08pin.sym # of pins=3 +** sym_path: /home/anton/projects/tt08-vga-fun/xschem/tt08pin.sym +** sch_path: /home/anton/projects/tt08-vga-fun/xschem/tt08pin.sch +.subckt tt08pin pin mod VGND +*.iopin pin +*.iopin VGND +*.iopin mod +R1 net1 pin 1 m=1 +C1 pin VGND 1p m=1 +L1 net2 net1 1n m=1 +V1 VAPWR VGND 3.3 +C2 net2 VGND 2p m=1 +R2 net3 net2 50 m=1 +XM2 net3 VGND mod VAPWR sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=100 nf=20 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XM1 net3 VAPWR mod VGND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=60 nf=12 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 +XM4 net3 VAPWR VGND VAPWR sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=100 nf=20 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=15 m=15 +XM3 net3 VGND VGND VGND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=60 nf=12 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=15 m=15 +C3 mod VGND 250f m=1 +.ends + + +* expanding symbol: segdac_parax.sym # of pins=19 +** sym_path: /home/anton/projects/tt08-vga-fun/xschem/segdac.sym +.include /home/anton/projects/tt08-vga-fun/mag/segdac.sim.spice + +* expanding symbol: thermo2bit_parax.sym # of pins=7 +** sym_path: /home/anton/projects/tt08-vga-fun/xschem/thermo2bit.sym +.include /home/anton/projects/tt08-vga-fun/mag/thermo2bit.sim.spice +.GLOBAL GND +.GLOBAL vss +.GLOBAL VGND +.GLOBAL VAPWR +.end diff --git a/xschem/tb_segdac.sch b/xschem/tb_segdac.sch index ec41a65..5a890e4 100644 --- a/xschem/tb_segdac.sch +++ b/xschem/tb_segdac.sch @@ -122,12 +122,14 @@ N 740 -840 760 -840 { lab=vcc_nom} N 520 -780 520 -720 { lab=#net1} -N 520 -780 620 -780 { -lab=#net1} N 620 -840 680 -840 { lab=#net2} N 230 -570 250 -570 { lab=vcc_nom} +N 620 -780 680 -780 { +lab=vout} +N 680 -780 680 -720 { +lab=vout} C {devices/vsource.sym} 550 -920 0 0 {name=Vvcc1 value="1.8" savecurrent=false} C {devices/lab_pin.sym} 550 -950 0 0 {name=p1 sig_type=std_logic lab=vcc1} C {devices/gnd.sym} 550 -890 0 0 {name=l2 lab=GND} @@ -288,13 +290,12 @@ footprint=1206 device="ceramic capacitor"} C {devices/gnd.sym} 770 -660 0 0 {name=l5 lab=vss} C {devices/lab_pin.sym} 760 -840 0 1 {name=p58 sig_type=std_logic lab=vcc_nom} -C {sky130_fd_pr/res_high_po_5p73.sym} 620 -810 0 0 {name=R1 -L=28 -model=res_high_po_5p73 -spiceprefix=X -mult=1} -C {devices/gnd.sym} 600 -810 1 0 {name=l7 lab=vss} C {devices/vsource.sym} 710 -840 1 0 {name=VCurrent value=0 savecurrent=false} C {devices/gnd.sym} 210 -570 0 0 {name=l3 lab=vss} C {devices/lab_pin.sym} 400 -860 2 1 {name=p3 sig_type=std_logic lab=vcc_nom} C {devices/lab_pin.sym} 250 -570 2 0 {name=p57 sig_type=std_logic lab=vcc_nom} +C {devices/res.sym} 620 -810 0 0 {name=R1 +value=1.65k +footprint=1206 +device=resistor +m=1} diff --git a/xschem/tb_segdac_pex.sch b/xschem/tb_segdac_pex.sch new file mode 100644 index 0000000..92c573a --- /dev/null +++ b/xschem/tb_segdac_pex.sch @@ -0,0 +1,472 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +B 2 920 -980 2420 -90 {flags=graph +y1=-0.019 +y2=1.9 +ypos1=0 +ypos2=2 +divy=20 +subdivy=0 +unity=1 +x1=0 +x2=1.28e-05 +divx=20 +subdivx=1 +xlabmag=1.0 +ylabmag=1.0 + + +dataset=-1 +unitx=1 +logx=0 +logy=0 +rainbow=1 + + + + + + + + + + + + +color="7 7 7 7 11 11 11 11" +node="\\"o; vout\\" +\\"bR; vbias\\" +\\"tmA;i(vvccnom) 1000 *\\" +\\"xmA;i(vcurrent) 1000 *\\" +\\"Po; vout_pex\\" +\\"PbR; vbias_pex\\" +\\"PtmA;i(vvccpex) 1000 *\\" +\\"PxmA;i(vcurrentpex) 1000 *\\""} +T {TT_MODELS is set to use +'tt_mm' (for Monte Carlo) +instead of just 'tt'. +Use 'repeat' >1 +in COMMANDS2 to make +use of this.} 250 -1000 0 0 0.3 0.3 {} +T {Introduce random variation +in VCC for Monte Carlo by +setting power supply to: + +1.8 trrandom(1 15us 0s 100mV 0mV)} 610 -960 0 0 0.3 0.3 {} +T {This is csdac_nom.sch (fixed, nominal). +There is also csdac.sch (parametric).} 390 -510 0 0 0.3 0.3 {} +T {This is csdac_nom.sch (fixed, nominal). +There is also csdac.sch (parametric).} 2850 -420 0 0 0.3 0.3 {} +N 500 -40 550 -40 { +lab=p0} +N 500 -60 550 -60 { +lab=p1} +N 380 -760 450 -760 { +lab=Vbias} +N 50 -820 80 -820 { +lab=sa1} +N 50 -800 80 -800 { +lab=sa2} +N 50 -780 80 -780 { +lab=sa3} +N 50 -760 80 -760 { +lab=sb1} +N 50 -740 80 -740 { +lab=sb2} +N 50 -720 80 -720 { +lab=sb3} +N 50 -700 80 -700 { +lab=sc1} +N 50 -680 80 -680 { +lab=sc2} +N 50 -660 80 -660 { +lab=sc3} +N 50 -640 80 -640 { +lab=sd1} +N 50 -620 80 -620 { +lab=sd2} +N 50 -600 80 -600 { +lab=sd3} +N 400 -860 400 -820 { +lab=vcc_nom} +N 380 -820 400 -820 { +lab=vcc_nom} +N 380 -800 420 -800 { +lab=vss} +N 420 -800 420 -680 { +lab=vss} +N 100 -40 120 -40 { +lab=vcc_nom} +N 500 -160 550 -160 { +lab=p2} +N 500 -180 550 -180 { +lab=p3} +N 100 -160 120 -160 { +lab=vcc_nom} +N 500 -280 550 -280 { +lab=p4} +N 500 -300 550 -300 { +lab=p5} +N 100 -280 120 -280 { +lab=vcc_nom} +N 100 -400 120 -400 { +lab=vcc_nom} +N 500 -420 550 -420 { +lab=p7} +N 500 -400 550 -400 { +lab=p6} +N 380 -780 520 -780 { +lab=#net1} +N 680 -720 820 -720 { +lab=vout} +N 740 -840 760 -840 { +lab=vcc_nom} +N 520 -780 520 -720 { +lab=#net1} +N 620 -840 680 -840 { +lab=#net2} +N 230 -570 250 -570 { +lab=vcc_nom} +N 620 -780 680 -780 { +lab=vout} +N 680 -780 680 -720 { +lab=vout} +N 2840 -760 2910 -760 { +lab=Vbias_pex} +N 2510 -820 2540 -820 { +lab=sa1_pex} +N 2510 -800 2540 -800 { +lab=sa2_pex} +N 2510 -780 2540 -780 { +lab=sa3_pex} +N 2510 -760 2540 -760 { +lab=sb1_pex} +N 2510 -740 2540 -740 { +lab=sb2_pex} +N 2510 -720 2540 -720 { +lab=sb3_pex} +N 2510 -700 2540 -700 { +lab=sc1_pex} +N 2510 -680 2540 -680 { +lab=sc2_pex} +N 2510 -660 2540 -660 { +lab=sc3_pex} +N 2510 -640 2540 -640 { +lab=sd1_pex} +N 2510 -620 2540 -620 { +lab=sd2_pex} +N 2510 -600 2540 -600 { +lab=sd3_pex} +N 2860 -860 2860 -820 { +lab=vcc_pex} +N 2840 -820 2860 -820 { +lab=vcc_pex} +N 2840 -800 2880 -800 { +lab=vss} +N 2880 -800 2880 -680 { +lab=vss} +N 2560 -40 2580 -40 { +lab=vcc_pex} +N 2560 -160 2580 -160 { +lab=vcc_pex} +N 2560 -280 2580 -280 { +lab=vcc_pex} +N 2560 -400 2580 -400 { +lab=vcc_pex} +N 2840 -780 2980 -780 { +lab=#net3} +N 3140 -720 3280 -720 { +lab=vout_pex} +N 3200 -840 3220 -840 { +lab=vcc_pex} +N 2980 -780 2980 -720 { +lab=#net3} +N 3080 -840 3140 -840 { +lab=#net4} +N 2690 -570 2710 -570 { +lab=vcc_pex} +N 3080 -780 3140 -780 { +lab=vout_pex} +N 3140 -780 3140 -720 { +lab=vout_pex} +C {devices/vsource.sym} 550 -920 0 0 {name=Vvcc1 value="1.8" savecurrent=false} +C {devices/lab_pin.sym} 550 -950 0 0 {name=p1 sig_type=std_logic lab=vcc1} +C {devices/gnd.sym} 550 -890 0 0 {name=l2 lab=GND} +C {devices/simulator_commands.sym} 130 -990 0 1 {name=COMMANDS2 +simulator=ngspice +only_toplevel=false +value=" +.param singlebits=0 +.IF (singlebits == 1) +* Mode to just test each binary-weighted level: +Vxp0 p0 GND pulse 0v 1.8v 1u 1n 1n 1u 10u +Vxp1 p1 GND pulse 0v 1.8v 2u 1n 1n 1u 10u +Vxp2 p2 GND pulse 0v 1.8v 3u 1n 1n 1u 10u +Vxp3 p3 GND pulse 0v 1.8v 4u 1n 1n 1u 10u +Vxp4 p4 GND pulse 0v 1.8v 5u 1n 1n 1u 10u +Vxp5 p5 GND pulse 0v 1.8v 6u 1n 1n 1u 10u +Vxp6 p6 GND pulse 0v 1.8v 7u 1n 1n 1u 10u +Vxp7 p7 GND pulse 0v 1.8v 8u 1n 1n 1u 10u +Vxn0 n0 GND pulse 1.8v 0v 1u 1n 1n 1u 10u +Vxn1 n1 GND pulse 1.8v 0v 2u 1n 1n 1u 10u +Vxn2 n2 GND pulse 1.8v 0v 3u 1n 1n 1u 10u +Vxn3 n3 GND pulse 1.8v 0v 4u 1n 1n 1u 10u +Vxn4 n4 GND pulse 1.8v 0v 5u 1n 1n 1u 10u +Vxn5 n5 GND pulse 1.8v 0v 6u 1n 1n 1u 10u +Vxn6 n6 GND pulse 1.8v 0v 7u 1n 1n 1u 10u +Vxn7 n7 GND pulse 1.8v 0v 8u 1n 1n 1u 10u +.ELSEIF (singlebits == 0) +* Mode to test full 0..255 trange: +Vxp0 p0 GND pulse 1.8v 0v 0n 1n 1n 39n 80n +Vxp1 p1 GND pulse 1.8v 0v 0n 1n 1n 79n 160n +Vxp2 p2 GND pulse 1.8v 0v 0n 1n 1n 159n 320n +Vxp3 p3 GND pulse 1.8v 0v 0n 1n 1n 319n 640n +Vxp4 p4 GND pulse 1.8v 0v 0n 1n 1n 639n 1280n +Vxp5 p5 GND pulse 1.8v 0v 0n 1n 1n 1279n 2560n +Vxp6 p6 GND pulse 1.8v 0v 0n 1n 1n 2559n 5120n +Vxp7 p7 GND pulse 1.8v 0v 0n 1n 1n 5119n 10240n +Vxn0 n0 GND pulse 0v 1.8v 0n 1n 1n 39n 80n +Vxn1 n1 GND pulse 0v 1.8v 0n 1n 1n 79n 160n +Vxn2 n2 GND pulse 0v 1.8v 0n 1n 1n 159n 320n +Vxn3 n3 GND pulse 0v 1.8v 0n 1n 1n 319n 640n +Vxn4 n4 GND pulse 0v 1.8v 0n 1n 1n 639n 1280n +Vxn5 n5 GND pulse 0v 1.8v 0n 1n 1n 1279n 2560n +Vxn6 n6 GND pulse 0v 1.8v 0n 1n 1n 2559n 5120n +Vxn7 n7 GND pulse 0v 1.8v 0n 1n 1n 5119n 10240n +.ENDIF + +.options savecurrents +.control + + * If using Monte Carlo, change to repeat to (say) 5: + repeat 1 + save all + tran 1n 12.8u + write tb_segdac_pex.raw + + i(vvss) vcc1 vbias vout i(vvccnom) i(vcurrent) + + p0 p1 p2 p3 p4 p5 p6 p7 + + sa1 sa2 sa3 + + sb1 sb2 sb3 + + sc1 sc2 sc3 + + sd1 sd2 sd3 + + vbias_pex vout_pex i(vvccpex) i(vcurrentpex) + + p0 p1 p2 p3 p4 p5 p6 p7 + + sa1_pex sa2_pex sa3_pex + + sb1_pex sb2_pex sb3_pex + + sc1_pex sc2_pex sc3_pex + + sd1_pex sd2_pex sd3_pex + + * + i(voutload) + set appendwrite + reset + end + +* save all +* *reset +* *alterparam MPW=4 +* *alterparam MMW=4 +* tran 1n 12.8u +* write 11.raw i(vvcc) i(vvss) vpos vneg vbias + +* set appendwrite +* alterparam MPW=4 +* alterparam MMW=4 +* reset +* tran 1n 12.8u +* write 11.raw i(vvcc) i(vvss) vpos vneg vbias + +.endc +"} +C {devices/gnd.sym} 470 -890 0 0 {name=l6 lab=GND} +C {devices/launcher.sym} 1010 -50 0 0 {name=h5 +descr="load waves" +tclcommand="xschem raw_read $netlist_dir/tb_segdac_pex.raw tran" +} +C {devices/vsource.sym} 470 -920 0 0 {name=Vvss value=0 savecurrent=false} +C {devices/lab_pin.sym} 470 -950 0 0 {name=p42 sig_type=std_logic lab=vss} +C {devices/code.sym} 130 -990 0 0 {name=TT_MODELS +only_toplevel=true +format="tcleval( @value )" +value=" +.lib $::SKYWATER_MODELS/sky130.lib.spice tt +.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice +" +spice_ignore=false} +C {devices/lab_pin.sym} 500 -420 2 1 {name=p4 sig_type=std_logic lab=p7} +C {devices/lab_pin.sym} 500 -400 2 1 {name=p9 sig_type=std_logic lab=p6} +C {devices/lab_pin.sym} 500 -300 2 1 {name=p11 sig_type=std_logic lab=p5} +C {devices/lab_pin.sym} 500 -280 2 1 {name=p12 sig_type=std_logic lab=p4} +C {devices/lab_pin.sym} 500 -180 2 1 {name=p13 sig_type=std_logic lab=p3} +C {devices/lab_pin.sym} 500 -160 2 1 {name=p14 sig_type=std_logic lab=p2} +C {devices/lab_pin.sym} 500 -60 2 1 {name=p15 sig_type=std_logic lab=p1} +C {devices/lab_pin.sym} 500 -40 2 1 {name=p16 sig_type=std_logic lab=p0} +C {devices/lab_pin.sym} 100 -460 2 1 {name=p17 sig_type=std_logic lab=n7} +C {devices/lab_pin.sym} 100 -440 2 1 {name=p18 sig_type=std_logic lab=n6} +C {devices/lab_pin.sym} 100 -340 2 1 {name=p19 sig_type=std_logic lab=n5} +C {devices/lab_pin.sym} 100 -320 2 1 {name=p20 sig_type=std_logic lab=n4} +C {devices/lab_pin.sym} 100 -220 2 1 {name=p21 sig_type=std_logic lab=n3} +C {devices/lab_pin.sym} 100 -200 2 1 {name=p22 sig_type=std_logic lab=n2} +C {devices/lab_pin.sym} 100 -100 2 1 {name=p39 sig_type=std_logic lab=n1} +C {devices/lab_pin.sym} 100 -80 2 1 {name=p40 sig_type=std_logic lab=n0} +C {devices/vsource.sym} 750 -490 0 0 {name=Vvccnom value=0 savecurrent=false} +C {devices/lab_pin.sym} 750 -460 0 0 {name=p49 sig_type=std_logic lab=vcc_nom} +C {devices/lab_pin.sym} 750 -520 0 0 {name=p51 sig_type=std_logic lab=vcc1} +C {segdac.sym} 230 -710 0 0 {name=x1} +C {devices/lab_pin.sym} 50 -820 0 0 {name=p6 lab=sa1} +C {devices/lab_pin.sym} 50 -800 0 0 {name=p23 lab=sa2} +C {devices/lab_pin.sym} 50 -780 0 0 {name=p25 lab=sa3} +C {devices/lab_pin.sym} 50 -760 0 0 {name=p27 lab=sb1} +C {devices/lab_pin.sym} 50 -740 0 0 {name=p28 lab=sb2} +C {devices/lab_pin.sym} 450 -760 0 1 {name=p29 lab=Vbias} +C {devices/lab_pin.sym} 50 -720 0 0 {name=p30 lab=sb3} +C {devices/lab_pin.sym} 50 -700 0 0 {name=p31 lab=sc1} +C {devices/lab_pin.sym} 50 -680 0 0 {name=p32 lab=sc2} +C {devices/lab_pin.sym} 50 -660 0 0 {name=p33 lab=sc3} +C {devices/lab_pin.sym} 50 -640 0 0 {name=p34 lab=sd1} +C {devices/lab_pin.sym} 50 -620 0 0 {name=p35 lab=sd2} +C {devices/lab_pin.sym} 50 -600 0 0 {name=p36 lab=sd3} +C {thermo2bit.sym} 200 -40 0 0 {name=XSA + + +} +C {devices/lab_pin.sym} 300 -60 2 0 {name=p5 lab=sa1} +C {devices/lab_pin.sym} 300 -80 2 0 {name=p7 lab=sa2} +C {devices/lab_pin.sym} 300 -100 2 0 {name=p8 lab=sa3} +C {devices/lab_pin.sym} 100 -40 0 0 {name=p26 sig_type=std_logic lab=vcc_nom} +C {thermo2bit.sym} 200 -160 0 0 {name=XSB + + +} +C {devices/lab_pin.sym} 100 -160 0 0 {name=p46 sig_type=std_logic lab=vcc_nom} +C {thermo2bit.sym} 200 -280 0 0 {name=XSC + + +} +C {devices/lab_pin.sym} 100 -280 0 0 {name=p43 sig_type=std_logic lab=vcc_nom} +C {thermo2bit.sym} 200 -400 0 0 {name=XSD + + +} +C {devices/lab_pin.sym} 100 -400 0 0 {name=p38 sig_type=std_logic lab=vcc_nom} +C {devices/lab_pin.sym} 300 -180 2 0 {name=p44 lab=sb1} +C {devices/lab_pin.sym} 300 -200 2 0 {name=p47 lab=sb2} +C {devices/lab_pin.sym} 300 -220 2 0 {name=p48 lab=sb3} +C {devices/lab_pin.sym} 300 -300 2 0 {name=p50 lab=sc1} +C {devices/lab_pin.sym} 300 -320 2 0 {name=p52 lab=sc2} +C {devices/lab_pin.sym} 300 -340 2 0 {name=p53 lab=sc3} +C {devices/lab_pin.sym} 300 -420 2 0 {name=p54 lab=sd1} +C {devices/lab_pin.sym} 300 -440 2 0 {name=p55 lab=sd2} +C {devices/lab_pin.sym} 300 -460 2 0 {name=p56 lab=sd3} +C {devices/gnd.sym} 420 -680 0 0 {name=l1 lab=vss} +C {devices/lab_pin.sym} 280 -400 0 1 {name=p10 sig_type=std_logic lab=vss} +C {devices/lab_pin.sym} 280 -280 0 1 {name=p24 sig_type=std_logic lab=vss} +C {devices/lab_pin.sym} 280 -160 0 1 {name=p37 sig_type=std_logic lab=vss} +C {devices/lab_pin.sym} 280 -40 0 1 {name=p41 sig_type=std_logic lab=vss} +C {tt08pin.sym} 600 -700 0 0 {name=x2} +C {devices/gnd.sym} 680 -680 0 0 {name=l4 lab=vss} +C {devices/lab_pin.sym} 820 -720 0 1 {name=p45 lab=vout} +C {devices/capa.sym} 770 -690 0 0 {name=C1 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {devices/gnd.sym} 770 -660 0 0 {name=l5 lab=vss} +C {devices/lab_pin.sym} 760 -840 0 1 {name=p58 sig_type=std_logic lab=vcc_nom} +C {devices/vsource.sym} 710 -840 1 0 {name=VCurrent value=0 savecurrent=false} +C {devices/gnd.sym} 210 -570 0 0 {name=l3 lab=vss} +C {devices/lab_pin.sym} 400 -860 2 1 {name=p3 sig_type=std_logic lab=vcc_nom} +C {devices/lab_pin.sym} 250 -570 2 0 {name=p57 sig_type=std_logic lab=vcc_nom} +C {devices/res.sym} 620 -810 0 0 {name=R1 +value=1.65k +footprint=1206 +device=resistor +m=1} +C {devices/lab_pin.sym} 2560 -460 2 1 {name=p66 sig_type=std_logic lab=n7} +C {devices/lab_pin.sym} 2560 -440 2 1 {name=p67 sig_type=std_logic lab=n6} +C {devices/lab_pin.sym} 2560 -340 2 1 {name=p68 sig_type=std_logic lab=n5} +C {devices/lab_pin.sym} 2560 -320 2 1 {name=p69 sig_type=std_logic lab=n4} +C {devices/lab_pin.sym} 2560 -220 2 1 {name=p70 sig_type=std_logic lab=n3} +C {devices/lab_pin.sym} 2560 -200 2 1 {name=p71 sig_type=std_logic lab=n2} +C {devices/lab_pin.sym} 2560 -100 2 1 {name=p72 sig_type=std_logic lab=n1} +C {devices/lab_pin.sym} 2560 -80 2 1 {name=p73 sig_type=std_logic lab=n0} +C {devices/vsource.sym} 3210 -400 0 0 {name=Vvccpex value=0 savecurrent=false} +C {devices/lab_pin.sym} 3210 -370 0 0 {name=p74 sig_type=std_logic lab=vcc_pex} +C {devices/lab_pin.sym} 3210 -430 0 0 {name=p75 sig_type=std_logic lab=vcc1} +C {segdac.sym} 2690 -710 0 0 {name=x3 +schematic=segdac_parax.sim +spice_sym_def="tcleval(.include [file normalize ../mag/segdac.sim.spice])" +tclcommand="textwindow [file normalize ../mag/segdac.sim.spice]"} +C {devices/lab_pin.sym} 2910 -760 0 1 {name=p81 lab=Vbias_pex} +C {devices/lab_pin.sym} 2510 -820 0 0 {name=p76 lab=sa1_pex} +C {devices/lab_pin.sym} 2510 -800 0 0 {name=p77 lab=sa2_pex} +C {devices/lab_pin.sym} 2510 -780 0 0 {name=p78 lab=sa3_pex} +C {devices/lab_pin.sym} 2510 -760 0 0 {name=p79 lab=sb1_pex} +C {devices/lab_pin.sym} 2510 -740 0 0 {name=p80 lab=sb2_pex} +C {devices/lab_pin.sym} 2510 -720 0 0 {name=p82 lab=sb3_pex} +C {devices/lab_pin.sym} 2510 -700 0 0 {name=p83 lab=sc1_pex} +C {devices/lab_pin.sym} 2510 -680 0 0 {name=p84 lab=sc2_pex} +C {devices/lab_pin.sym} 2510 -660 0 0 {name=p85 lab=sc3_pex} +C {devices/lab_pin.sym} 2510 -640 0 0 {name=p86 lab=sd1_pex} +C {devices/lab_pin.sym} 2510 -620 0 0 {name=p87 lab=sd2_pex} +C {devices/lab_pin.sym} 2510 -600 0 0 {name=p88 lab=sd3_pex} +C {thermo2bit.sym} 2660 -40 0 0 {name=XSA1 +schematic=thermo2bit_parax.sim +spice_sym_def="tcleval(.include [file normalize ../mag/thermo2bit.sim.spice])" +tclcommand="textwindow [file normalize ../mag/thermo2bit.sim.spice]"} +C {devices/lab_pin.sym} 2760 -60 2 0 {name=p89 lab=sa1_pex} +C {devices/lab_pin.sym} 2760 -80 2 0 {name=p90 lab=sa2_pex} +C {devices/lab_pin.sym} 2760 -100 2 0 {name=p91 lab=sa3_pex} +C {devices/lab_pin.sym} 2560 -40 0 0 {name=p92 sig_type=std_logic lab=vcc_pex} +C {thermo2bit.sym} 2660 -160 0 0 {name=XSB1 +schematic=thermo2bit_parax.sim +spice_sym_def="tcleval(.include [file normalize ../mag/thermo2bit.sim.spice])" +tclcommand="textwindow [file normalize ../mag/thermo2bit.sim.spice]"} +C {devices/lab_pin.sym} 2560 -160 0 0 {name=p93 sig_type=std_logic lab=vcc_pex} +C {thermo2bit.sym} 2660 -280 0 0 {name=XSC1 +schematic=thermo2bit_parax.sim +spice_sym_def="tcleval(.include [file normalize ../mag/thermo2bit.sim.spice])" +tclcommand="textwindow [file normalize ../mag/thermo2bit.sim.spice]"} +C {devices/lab_pin.sym} 2560 -280 0 0 {name=p94 sig_type=std_logic lab=vcc_pex} +C {thermo2bit.sym} 2660 -400 0 0 {name=XSD1 +schematic=thermo2bit_parax.sim +spice_sym_def="tcleval(.include [file normalize ../mag/thermo2bit.sim.spice])" +tclcommand="textwindow [file normalize ../mag/thermo2bit.sim.spice]"} +C {devices/lab_pin.sym} 2560 -400 0 0 {name=p95 sig_type=std_logic lab=vcc_pex} +C {devices/lab_pin.sym} 2760 -180 2 0 {name=p96 lab=sb1_pex} +C {devices/lab_pin.sym} 2760 -200 2 0 {name=p97 lab=sb2_pex} +C {devices/lab_pin.sym} 2760 -220 2 0 {name=p98 lab=sb3_pex} +C {devices/lab_pin.sym} 2760 -300 2 0 {name=p99 lab=sc1_pex} +C {devices/lab_pin.sym} 2760 -320 2 0 {name=p100 lab=sc2_pex} +C {devices/lab_pin.sym} 2760 -340 2 0 {name=p101 lab=sc3_pex} +C {devices/lab_pin.sym} 2760 -420 2 0 {name=p102 lab=sd1_pex} +C {devices/lab_pin.sym} 2760 -440 2 0 {name=p103 lab=sd2_pex} +C {devices/lab_pin.sym} 2760 -460 2 0 {name=p104 lab=sd3_pex} +C {devices/gnd.sym} 2880 -680 0 0 {name=l7 lab=vss} +C {devices/lab_pin.sym} 2740 -400 0 1 {name=p105 sig_type=std_logic lab=vss} +C {devices/lab_pin.sym} 2740 -280 0 1 {name=p106 sig_type=std_logic lab=vss} +C {devices/lab_pin.sym} 2740 -160 0 1 {name=p107 sig_type=std_logic lab=vss} +C {devices/lab_pin.sym} 2740 -40 0 1 {name=p108 sig_type=std_logic lab=vss} +C {tt08pin.sym} 3060 -700 0 0 {name=x4} +C {devices/gnd.sym} 3140 -680 0 0 {name=l8 lab=vss} +C {devices/lab_pin.sym} 3280 -720 0 1 {name=p109 lab=vout_pex} +C {devices/capa.sym} 3230 -690 0 0 {name=C2 +m=1 +value=3p +footprint=1206 +device="ceramic capacitor"} +C {devices/gnd.sym} 3230 -660 0 0 {name=l9 lab=vss} +C {devices/lab_pin.sym} 3220 -840 0 1 {name=p110 sig_type=std_logic lab=vcc_pex} +C {devices/vsource.sym} 3170 -840 1 0 {name=VCurrentpex value=0 savecurrent=false} +C {devices/gnd.sym} 2670 -570 0 0 {name=l10 lab=vss} +C {devices/lab_pin.sym} 2860 -860 2 1 {name=p111 sig_type=std_logic lab=vcc_pex} +C {devices/lab_pin.sym} 2710 -570 2 0 {name=p112 sig_type=std_logic lab=vcc_pex} +C {devices/res.sym} 3080 -810 0 0 {name=R2 +value=1.65k +footprint=1206 +device=resistor +m=1}