diff --git a/.github/workflows/docs.yaml b/.github/workflows/docs.yaml new file mode 100644 index 0000000..75ca2b7 --- /dev/null +++ b/.github/workflows/docs.yaml @@ -0,0 +1,17 @@ +name: docs + +on: + push: + workflow_dispatch: + +jobs: + docs: + runs-on: ubuntu-latest + steps: + - name: Checkout repo + uses: actions/checkout@v4 + with: + submodules: recursive + + - name: Build docs + uses: TinyTapeout/tt-gds-action/docs@tt08 diff --git a/.github/workflows/gds.yaml b/.github/workflows/gds.yaml new file mode 100644 index 0000000..8e08fe2 --- /dev/null +++ b/.github/workflows/gds.yaml @@ -0,0 +1,44 @@ +name: gds + +on: + push: + workflow_dispatch: + +jobs: + gds: + runs-on: ubuntu-latest + steps: + - name: checkout repo + uses: actions/checkout@v4 + with: + submodules: recursive + + - name: Read top module name + uses: mikefarah/yq@v4 + id: top_module + with: + cmd: echo TOP_MODULE=`yq '.project.top_module' info.yaml` > $GITHUB_OUTPUT + + - name: Create and publish the GDS artifact + uses: TinyTapeout/tt-gds-action/custom_gds@tt08 + with: + top_module: ${{ steps.top_module.outputs.TOP_MODULE }} + gds_path: gds/${{ steps.top_module.outputs.TOP_MODULE }}.gds + lef_path: lef/${{ steps.top_module.outputs.TOP_MODULE }}.lef + verilog_path: src/project.v + + precheck: + needs: gds + runs-on: ubuntu-latest + steps: + - name: Run Tiny Tapeout Precheck + uses: TinyTapeout/tt-gds-action/precheck@tt08 + + viewer: + needs: gds + runs-on: ubuntu-latest + permissions: + pages: write # to deploy to Pages + id-token: write # to verify the deployment originates from an appropriate source + steps: + - uses: TinyTapeout/tt-gds-action/viewer@tt08 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e62b85d --- /dev/null +++ b/.gitignore @@ -0,0 +1,11 @@ +.DS_Store +.idea +.vscode +*.vcd +runs +tt_submission +src/user_config.tcl +test/sim_build +test/__pycache__/ +test/results.xml +test/gate_level_netlist.v diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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A single tile is about 167x108 uM. + tiles: "1x2" # Valid values for analog projects: 1x2, 2x2 + + # How many analog pins does your project use? + analog_pins: 2 # Valid values: 0 to 6 + uses_3v3: false # Set to true if your project uses 3.3V (VAPWR) in addition to 1.8V (VDPWR) + + # Your top module name must start with "tt_um_". Make it unique by including your github username: + top_module: "tt_um_example" + + # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: + source_files: + - "project.v" + +# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. +pinout: + # Inputs + ui[0]: "" + ui[1]: "" + ui[2]: "" + ui[3]: "" + ui[4]: "" + ui[5]: "" + ui[6]: "" + ui[7]: "" + + # Outputs + uo[0]: "" + uo[1]: "" + uo[2]: "" + uo[3]: "" + uo[4]: "" + uo[5]: "" + uo[6]: "" + uo[7]: "" + + # Bidirectional pins + uio[0]: "" + uio[1]: "" + uio[2]: "" + uio[3]: "" + uio[4]: "" + uio[5]: "" + uio[6]: "" + uio[7]: "" + + # Analog pins - make sure to also set "analog_pins" above, else the pins won't be connected + ua[0]: "" + ua[1]: "" + ua[2]: "" + ua[3]: "" + ua[4]: "" + ua[5]: "" + +# Do not change! +yaml_version: 6 diff --git a/src/project.v b/src/project.v new file mode 100644 index 0000000..eeedfb5 --- /dev/null +++ b/src/project.v @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Your Name + * SPDX-License-Identifier: Apache-2.0 + */ + +`default_nettype none + +module tt_um_example ( + input wire VGND, + input wire VDPWR, // 1.8v power supply +// input wire VAPWR, // 3.3v power supply + input wire [7:0] ui_in, // Dedicated inputs + output wire [7:0] uo_out, // Dedicated outputs + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + inout wire [7:0] ua, // Analog pins, only ua[5:0] can be used + input wire ena, // always 1 when the design is powered, so you can ignore it + input wire clk, // clock + input wire rst_n // reset_n - low to reset +); + +endmodule diff --git a/test/requirements.txt b/test/requirements.txt new file mode 100644 index 0000000..6bb0f28 --- /dev/null +++ b/test/requirements.txt @@ -0,0 +1,2 @@ +pytest==8.1.1 +cocotb==1.8.1