From 97fe642723cec3a3835e9ef95c4447915e8d39b2 Mon Sep 17 00:00:00 2001 From: Yemao Date: Wed, 7 Feb 2018 23:41:34 +0800 Subject: [PATCH] plat: xr871 init version for AliOS-Things(Github) --- board/xr871evb/board.c | 260 ++ board/xr871evb/board.h | 10 + board/xr871evb/k_config.h | 224 ++ board/xr871evb/xr871evb.mk | 61 + example/alinkapp/alinkapp.mk | 2 +- platform/arch/arm/armv7m/gcc/m4/port_s.S | 4 +- platform/mcu/xr871/aos/aos.c | 77 + platform/mcu/xr871/aos/aos.h | 14 + platform/mcu/xr871/aos/aos.mk | 23 + platform/mcu/xr871/aos/aos_impl.c | 85 + platform/mcu/xr871/aos/cli_ext/cli_ext.c | 9 + platform/mcu/xr871/aos/cli_ext/cli_mem.c | 80 + platform/mcu/xr871/aos/cli_ext/cli_upgrade.c | 25 + platform/mcu/xr871/aos/hal/fota_port.c | 186 ++ platform/mcu/xr871/aos/hal/hal.c | 84 + platform/mcu/xr871/aos/hal/soc/adc.c | 112 + platform/mcu/xr871/aos/hal/soc/flash.c | 221 ++ platform/mcu/xr871/aos/hal/soc/gpio.c | 263 ++ platform/mcu/xr871/aos/hal/soc/i2c.c | 249 ++ platform/mcu/xr871/aos/hal/soc/pwm.c | 84 + platform/mcu/xr871/aos/hal/soc/rtc.c | 99 + platform/mcu/xr871/aos/hal/soc/sd.c | 174 ++ platform/mcu/xr871/aos/hal/soc/timer.c | 93 + platform/mcu/xr871/aos/hal/soc/uart.c | 196 ++ platform/mcu/xr871/aos/hal/soc/wdg.c | 74 + platform/mcu/xr871/aos/hal/wifi.c | 184 ++ platform/mcu/xr871/aos/hal/wifi_port.c | 584 ++++ platform/mcu/xr871/aos/hal/wifi_port.h | 65 + platform/mcu/xr871/aos/soc_impl.c | 35 + platform/mcu/xr871/bin/xr871/boot.bin | Bin 0 -> 31208 bytes platform/mcu/xr871/bin/xr871/net.bin | Bin 0 -> 287000 bytes platform/mcu/xr871/bin/xr871/net_ap.bin | Bin 0 -> 254664 bytes platform/mcu/xr871/bin/xr871/wlan_bl.bin | Bin 0 -> 2308 bytes platform/mcu/xr871/bin/xr871/wlan_fw.bin | Bin 0 -> 132180 bytes platform/mcu/xr871/bin/xr871/wlan_sdd.bin | Bin 0 -> 744 bytes platform/mcu/xr871/image-alinkapp-xz.cfg | 16 + platform/mcu/xr871/image-alinkapp.cfg | 16 + platform/mcu/xr871/image-douglasapp.cfg | 16 + platform/mcu/xr871/image-xip.cfg | 16 + platform/mcu/xr871/image-xplayerapp.cfg | 16 + platform/mcu/xr871/image-yts-xz.cfg | 16 + platform/mcu/xr871/image.cfg | 15 + platform/mcu/xr871/include/aos/hal/adc_priv.h | 33 + .../include/audio/manager/audio_manager.h | 58 + .../mcu/xr871/include/audio/pcm/audio_pcm.h | 70 + platform/mcu/xr871/include/compiler.h | 83 + platform/mcu/xr871/include/console/console.h | 65 + platform/mcu/xr871/include/driver/chip/chip.h | 166 ++ .../driver/chip/flashchip/flash_chip.h | 234 ++ .../mcu/xr871/include/driver/chip/hal_adc.h | 215 ++ .../mcu/xr871/include/driver/chip/hal_audio.h | 61 + .../mcu/xr871/include/driver/chip/hal_ccm.h | 308 +++ .../mcu/xr871/include/driver/chip/hal_chip.h | 59 + .../mcu/xr871/include/driver/chip/hal_clock.h | 112 + .../mcu/xr871/include/driver/chip/hal_cmsis.h | 35 + .../mcu/xr871/include/driver/chip/hal_codec.h | 172 ++ .../xr871/include/driver/chip/hal_crypto.h | 414 +++ .../mcu/xr871/include/driver/chip/hal_csi.h | 230 ++ .../mcu/xr871/include/driver/chip/hal_def.h | 82 + .../mcu/xr871/include/driver/chip/hal_dma.h | 276 ++ .../mcu/xr871/include/driver/chip/hal_dmic.h | 281 ++ .../mcu/xr871/include/driver/chip/hal_efuse.h | 93 + .../mcu/xr871/include/driver/chip/hal_flash.h | 142 + .../include/driver/chip/hal_flashcache.h | 141 + .../xr871/include/driver/chip/hal_flashctrl.h | 458 ++++ .../xr871/include/driver/chip/hal_global.h | 48 + .../mcu/xr871/include/driver/chip/hal_gpio.h | 414 +++ .../mcu/xr871/include/driver/chip/hal_i2c.h | 190 ++ .../mcu/xr871/include/driver/chip/hal_i2s.h | 523 ++++ .../mcu/xr871/include/driver/chip/hal_irrx.h | 133 + .../mcu/xr871/include/driver/chip/hal_irtx.h | 209 ++ .../mcu/xr871/include/driver/chip/hal_mbox.h | 160 ++ .../mcu/xr871/include/driver/chip/hal_nvic.h | 85 + .../mcu/xr871/include/driver/chip/hal_prcm.h | 637 +++++ .../mcu/xr871/include/driver/chip/hal_pwm.h | 285 ++ .../mcu/xr871/include/driver/chip/hal_rtc.h | 206 ++ .../mcu/xr871/include/driver/chip/hal_spi.h | 482 ++++ .../xr871/include/driver/chip/hal_spinlock.h | 71 + .../mcu/xr871/include/driver/chip/hal_timer.h | 187 ++ .../mcu/xr871/include/driver/chip/hal_uart.h | 290 ++ .../mcu/xr871/include/driver/chip/hal_util.h | 50 + .../xr871/include/driver/chip/hal_wakeup.h | 155 ++ .../mcu/xr871/include/driver/chip/hal_wdg.h | 127 + .../mcu/xr871/include/driver/chip/hal_xip.h | 60 + .../mcu/xr871/include/driver/chip/ir_nec.h | 199 ++ .../xr871/include/driver/chip/sdmmc/card.h | 210 ++ .../include/driver/chip/sdmmc/hal_sdhost.h | 114 + .../xr871/include/driver/chip/sdmmc/sdmmc.h | 486 ++++ .../xr871/include/driver/chip/system_chip.h | 49 + .../mcu/xr871/include/driver/cmsis/core_cm3.h | 1650 ++++++++++++ .../mcu/xr871/include/driver/cmsis/core_cm4.h | 1802 +++++++++++++ .../xr871/include/driver/cmsis/core_cmFunc.h | 637 +++++ .../xr871/include/driver/cmsis/core_cmInstr.h | 880 +++++++ .../xr871/include/driver/cmsis/core_cmSimd.h | 697 +++++ platform/mcu/xr871/include/driver/hal_board.h | 67 + platform/mcu/xr871/include/driver/hal_dev.h | 94 + platform/mcu/xr871/include/efpg/efpg.h | 75 + platform/mcu/xr871/include/fs/fatfs/ff.h | 365 +++ .../xr871/include/kernel/os/YunOS/os_common.h | 68 + .../xr871/include/kernel/os/YunOS/os_errno.h | 45 + .../xr871/include/kernel/os/YunOS/os_mutex.h | 115 + .../xr871/include/kernel/os/YunOS/os_queue.h | 135 + .../include/kernel/os/YunOS/os_semaphore.h | 126 + .../xr871/include/kernel/os/YunOS/os_thread.h | 128 + .../xr871/include/kernel/os/YunOS/os_time.h | 87 + .../xr871/include/kernel/os/YunOS/os_timer.h | 169 ++ platform/mcu/xr871/include/kernel/os/os.h | 43 + .../mcu/xr871/include/kernel/os/os_common.h | 39 + .../mcu/xr871/include/kernel/os/os_errno.h | 39 + .../mcu/xr871/include/kernel/os/os_mutex.h | 40 + .../mcu/xr871/include/kernel/os/os_queue.h | 39 + .../xr871/include/kernel/os/os_semaphore.h | 39 + .../mcu/xr871/include/kernel/os/os_thread.h | 39 + .../mcu/xr871/include/kernel/os/os_time.h | 39 + .../mcu/xr871/include/kernel/os/os_timer.h | 39 + platform/mcu/xr871/include/libc/errno.h | 180 ++ .../mcu/xr871/include/libc/sys/features.h | 100 + platform/mcu/xr871/include/net/lwip/arch/cc.h | 153 ++ .../mcu/xr871/include/net/lwip/lwipopts.h | 2341 +++++++++++++++++ .../mcu/xr871/include/net/lwip/lwippools.h | 12 + .../mcu/xr871/include/net/udhcp/usr_dhcpd.h | 51 + .../mcu/xr871/include/net/wlan/ethernetif.h | 59 + platform/mcu/xr871/include/net/wlan/wlan.h | 132 + .../mcu/xr871/include/net/wlan/wlan_airkiss.h | 89 + .../mcu/xr871/include/net/wlan/wlan_defs.h | 488 ++++ .../include/net/wlan/wlan_smart_config.h | 75 + platform/mcu/xr871/include/pm/pm.h | 226 ++ platform/mcu/xr871/include/sys/defs.h | 82 + .../mcu/xr871/include/sys/ducc/ducc_addr.h | 62 + .../mcu/xr871/include/sys/ducc/ducc_app.h | 146 + .../mcu/xr871/include/sys/ducc/ducc_net.h | 123 + platform/mcu/xr871/include/sys/endian.h | 234 ++ platform/mcu/xr871/include/sys/fdcm.h | 57 + platform/mcu/xr871/include/sys/image.h | 141 + platform/mcu/xr871/include/sys/interrupt.h | 159 ++ platform/mcu/xr871/include/sys/io.h | 74 + platform/mcu/xr871/include/sys/list.h | 584 ++++ platform/mcu/xr871/include/sys/mbuf.h | 41 + platform/mcu/xr871/include/sys/mbuf_0.h | 157 ++ platform/mcu/xr871/include/sys/mbuf_1.h | 244 ++ platform/mcu/xr871/include/sys/ota.h | 105 + platform/mcu/xr871/include/sys/param.h | 68 + platform/mcu/xr871/include/sys/queue.h | 694 +++++ platform/mcu/xr871/include/sys/xr_debug.h | 355 +++ platform/mcu/xr871/include/sys/xr_util.h | 48 + platform/mcu/xr871/include/types.h | 36 + platform/mcu/xr871/include/version.h | 43 + platform/mcu/xr871/include/xz/decompress.h | 45 + platform/mcu/xr871/include/xz/xz.h | 286 ++ platform/mcu/xr871/lib/libamr/libamr.a | Bin 0 -> 252734 bytes platform/mcu/xr871/lib/libamr/libamr.mk | 8 + platform/mcu/xr871/lib/libamren/libamren.a | Bin 0 -> 936122 bytes platform/mcu/xr871/lib/libamren/libamren.mk | 8 + platform/mcu/xr871/lib/libmp3/libmp3.a | Bin 0 -> 461652 bytes platform/mcu/xr871/lib/libmp3/libmp3.mk | 8 + platform/mcu/xr871/mkimage.mk | 57 + platform/mcu/xr871/pack/.keep | 0 .../mcu/xr871/project/common/board/board.c | 147 ++ .../mcu/xr871/project/common/board/board.h | 66 + .../xr871/project/common/board/board_common.c | 79 + .../xr871/project/common/board/board_common.h | 48 + .../xr871/project/common/board/board_debug.h | 69 + .../board/xr871_evb_main/board_config.c | 399 +++ .../board/xr871_evb_main/board_config.h | 83 + platform/mcu/xr871/project/common/cmd/cmd.h | 81 + .../mcu/xr871/project/common/cmd/cmd_adc.c | 407 +++ .../mcu/xr871/project/common/cmd/cmd_adc.h | 43 + .../xr871/project/common/cmd/cmd_airkiss.c | 122 + .../xr871/project/common/cmd/cmd_airkiss.h | 43 + .../mcu/xr871/project/common/cmd/cmd_arp.c | 91 + .../mcu/xr871/project/common/cmd/cmd_arp.h | 43 + .../mcu/xr871/project/common/cmd/cmd_audio.c | 369 +++ .../mcu/xr871/project/common/cmd/cmd_audio.h | 64 + .../xr871/project/common/cmd/cmd_broadcast.c | 264 ++ .../xr871/project/common/cmd/cmd_broadcast.h | 44 + .../mcu/xr871/project/common/cmd/cmd_ce.c | 808 ++++++ .../mcu/xr871/project/common/cmd/cmd_ce.h | 43 + .../mcu/xr871/project/common/cmd/cmd_cedarx.c | 532 ++++ .../mcu/xr871/project/common/cmd/cmd_cedarx.h | 46 + .../mcu/xr871/project/common/cmd/cmd_clock.c | 103 + .../mcu/xr871/project/common/cmd/cmd_clock.h | 43 + .../mcu/xr871/project/common/cmd/cmd_debug.h | 64 + .../mcu/xr871/project/common/cmd/cmd_defs.h | 72 + .../mcu/xr871/project/common/cmd/cmd_dhcpd.c | 139 + .../mcu/xr871/project/common/cmd/cmd_dhcpd.h | 43 + .../mcu/xr871/project/common/cmd/cmd_echo.c | 36 + .../mcu/xr871/project/common/cmd/cmd_echo.h | 43 + .../mcu/xr871/project/common/cmd/cmd_efpg.c | 162 ++ .../mcu/xr871/project/common/cmd/cmd_efpg.h | 43 + .../mcu/xr871/project/common/cmd/cmd_etf.c | 46 + .../mcu/xr871/project/common/cmd/cmd_etf.h | 43 + .../mcu/xr871/project/common/cmd/cmd_flash.c | 293 +++ .../mcu/xr871/project/common/cmd/cmd_flash.h | 43 + .../mcu/xr871/project/common/cmd/cmd_fs.c | 461 ++++ .../mcu/xr871/project/common/cmd/cmd_fs.h | 43 + .../mcu/xr871/project/common/cmd/cmd_heap.c | 51 + .../mcu/xr871/project/common/cmd/cmd_heap.h | 43 + .../mcu/xr871/project/common/cmd/cmd_httpc.c | 509 ++++ .../mcu/xr871/project/common/cmd/cmd_httpc.h | 43 + .../mcu/xr871/project/common/cmd/cmd_httpd.c | 83 + .../mcu/xr871/project/common/cmd/cmd_httpd.h | 43 + .../mcu/xr871/project/common/cmd/cmd_i2c.c | 508 ++++ .../mcu/xr871/project/common/cmd/cmd_i2c.h | 43 + .../xr871/project/common/cmd/cmd_ifconfig.c | 71 + .../xr871/project/common/cmd/cmd_ifconfig.h | 43 + .../mcu/xr871/project/common/cmd/cmd_iperf.c | 81 + .../mcu/xr871/project/common/cmd/cmd_iperf.h | 43 + .../mcu/xr871/project/common/cmd/cmd_irrx.c | 128 + .../mcu/xr871/project/common/cmd/cmd_irrx.h | 50 + .../mcu/xr871/project/common/cmd/cmd_irtx.c | 184 ++ .../mcu/xr871/project/common/cmd/cmd_irtx.h | 52 + .../mcu/xr871/project/common/cmd/cmd_mem.c | 226 ++ .../mcu/xr871/project/common/cmd/cmd_mem.h | 43 + .../mcu/xr871/project/common/cmd/cmd_mqtt.c | 559 ++++ .../mcu/xr871/project/common/cmd/cmd_mqtt.h | 43 + .../mcu/xr871/project/common/cmd/cmd_netcmd.c | 38 + .../mcu/xr871/project/common/cmd/cmd_netcmd.h | 43 + .../mcu/xr871/project/common/cmd/cmd_nopoll.c | 892 +++++++ .../mcu/xr871/project/common/cmd/cmd_nopoll.h | 43 + .../mcu/xr871/project/common/cmd/cmd_ota.c | 94 + .../mcu/xr871/project/common/cmd/cmd_ota.h | 43 + .../mcu/xr871/project/common/cmd/cmd_ping.c | 110 + .../mcu/xr871/project/common/cmd/cmd_ping.h | 43 + .../mcu/xr871/project/common/cmd/cmd_pm.c | 161 ++ .../mcu/xr871/project/common/cmd/cmd_pm.h | 43 + .../mcu/xr871/project/common/cmd/cmd_pwm.c | 704 +++++ .../mcu/xr871/project/common/cmd/cmd_pwm.h | 43 + .../mcu/xr871/project/common/cmd/cmd_rtc.c | 282 ++ .../mcu/xr871/project/common/cmd/cmd_rtc.h | 43 + .../mcu/xr871/project/common/cmd/cmd_sd.c | 565 ++++ .../mcu/xr871/project/common/cmd/cmd_sd.h | 50 + .../project/common/cmd/cmd_smart_config.c | 123 + .../project/common/cmd/cmd_smart_config.h | 43 + .../mcu/xr871/project/common/cmd/cmd_sntp.c | 79 + .../mcu/xr871/project/common/cmd/cmd_sntp.h | 43 + .../xr871/project/common/cmd/cmd_sysinfo.c | 334 +++ .../xr871/project/common/cmd/cmd_sysinfo.h | 43 + .../mcu/xr871/project/common/cmd/cmd_timer.c | 248 ++ .../mcu/xr871/project/common/cmd/cmd_timer.h | 43 + .../mcu/xr871/project/common/cmd/cmd_uart.c | 385 +++ .../mcu/xr871/project/common/cmd/cmd_uart.h | 43 + .../xr871/project/common/cmd/cmd_upgrade.c | 94 + .../xr871/project/common/cmd/cmd_upgrade.h | 44 + .../mcu/xr871/project/common/cmd/cmd_util.c | 195 ++ .../mcu/xr871/project/common/cmd/cmd_util.h | 115 + .../mcu/xr871/project/common/cmd/cmd_wdg.c | 139 + .../mcu/xr871/project/common/cmd/cmd_wdg.h | 43 + .../mcu/xr871/project/common/cmd/cmd_wlan.c | 1041 ++++++++ .../mcu/xr871/project/common/cmd/cmd_wlan.h | 47 + .../mcu/xr871/project/common/cmd/tls/client.c | 274 ++ .../xr871/project/common/cmd/tls/cmd_tls.c | 177 ++ .../xr871/project/common/cmd/tls/cmd_tls.h | 42 + .../project/common/cmd/tls/custom_certs.c | 29 + .../mcu/xr871/project/common/cmd/tls/server.c | 300 +++ .../mcu/xr871/project/common/cmd/tls/tls.c | 83 + .../mcu/xr871/project/common/cmd/tls/tls.h | 115 + .../project/common/framework/ctrl_msg_debug.h | 73 + .../project/common/framework/fwk_debug.h | 71 + .../xr871/project/common/framework/img_ctrl.c | 78 + .../xr871/project/common/framework/img_ctrl.h | 43 + .../project/common/framework/img_ctrl_debug.h | 73 + .../xr871/project/common/framework/net_ctrl.c | 432 +++ .../xr871/project/common/framework/net_ctrl.h | 93 + .../project/common/framework/net_ctrl_debug.h | 75 + .../xr871/project/common/framework/net_sys.c | 158 ++ .../project/common/framework/platform_init.c | 259 ++ .../project/common/framework/platform_init.h | 45 + .../common/framework/sys_ctrl/container.c | 246 ++ .../common/framework/sys_ctrl/container.h | 47 + .../common/framework/sys_ctrl/event_queue.c | 245 ++ .../common/framework/sys_ctrl/event_queue.h | 55 + .../common/framework/sys_ctrl/observer.c | 194 ++ .../common/framework/sys_ctrl/observer.h | 83 + .../common/framework/sys_ctrl/publisher.c | 212 ++ .../common/framework/sys_ctrl/publisher.h | 63 + .../common/framework/sys_ctrl/sys_ctrl.c | 139 + .../common/framework/sys_ctrl/sys_ctrl.h | 89 + .../xr871/project/common/framework/sysinfo.c | 222 ++ .../xr871/project/common/framework/sysinfo.h | 127 + .../project/common/framework/sysinfo_debug.h | 71 + .../project/common/startup/gcc/exception.c | 231 ++ .../project/common/startup/gcc/retarget.c | 90 + .../common/startup/gcc/retarget_main.c | 59 + .../common/startup/gcc/retarget_stdout.c | 132 + .../project/common/startup/gcc/startup.S | 581 ++++ platform/mcu/xr871/project/main/main.c | 36 + platform/mcu/xr871/project/main/prj_config.h | 105 + platform/mcu/xr871/project/project.mk | 24 + .../src/audio/audio_manager/audio_manager.c | 223 ++ .../src/audio/audio_manager/audio_manager.mk | 8 + .../mcu/xr871/src/audio/audio_pcm/audio_pcm.c | 468 ++++ .../xr871/src/audio/audio_pcm/audio_pcm.mk | 8 + .../Cdx2.0Plugin/include/AudioDec_Decode.h | 123 + .../cedarx/Cdx2.0Plugin/include/CDX_Common.h | 45 + .../Cdx2.0Plugin/include/CDX_Fileformat.h | 107 + .../Cdx2.0Plugin/include/GetAudio_format.h | 184 ++ .../Cdx2.0Plugin/include/PostProcessCom.h | 39 + .../src/cedarx/Cdx2.0Plugin/include/STTypes.h | 152 ++ .../Cdx2.0Plugin/include/TouchToStretch.h | 45 + .../Cdx2.0Plugin/include/ad_cedarlib_com.h | 142 + .../cedarx/Cdx2.0Plugin/include/adecoder.h | 438 +++ .../cedarx/Cdx2.0Plugin/include/auGaincom.h | 15 + .../cedarx/Cdx2.0Plugin/include/aumixcom.h | 32 + .../include/cedar_abs_packet_hdr.h | 63 + .../src/cedarx/Cdx2.0Plugin/include/log.h | 119 + .../cedarx/Cdx2.0Plugin/include/rw_data_api.h | 31 + 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| 7 + .../xr871/src/net/udhcp/samples/simple.script | 39 + .../xr871/src/net/udhcp/samples/udhcpd.conf | 116 + platform/mcu/xr871/src/net/udhcp/script.c | 228 ++ platform/mcu/xr871/src/net/udhcp/script.h | 6 + .../mcu/xr871/src/net/udhcp/serverpacket.c | 428 +++ .../mcu/xr871/src/net/udhcp/serverpacket.h | 11 + platform/mcu/xr871/src/net/udhcp/socket.c | 211 ++ platform/mcu/xr871/src/net/udhcp/socket.h | 9 + platform/mcu/xr871/src/net/udhcp/udhcp.mk | 25 + platform/mcu/xr871/src/net/udhcp/udhcpc.8 | 208 ++ platform/mcu/xr871/src/net/udhcp/udhcpd.8 | 17 + .../mcu/xr871/src/net/udhcp/udhcpd.conf.5 | 164 ++ platform/mcu/xr871/src/net/udhcp/usr_dhcpd.c | 333 +++ .../mcu/xr871/src/net/wlan/airkiss/airkiss.h | 236 ++ .../xr871/src/net/wlan/airkiss/airkiss_ack.c | 151 ++ .../src/net/wlan/airkiss/airkiss_discover.c | 314 +++ .../xr871/src/net/wlan/airkiss/airkiss_main.c | 261 ++ platform/mcu/xr871/src/net/wlan/ethernetif.c | 529 ++++ .../net/wlan/smartconfig/smart_config_ack.c | 170 ++ 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platform/mcu/xr871/src/xz/xz_dec_stream.c | 821 ++++++ platform/mcu/xr871/src/xz/xz_lzma2.h | 204 ++ platform/mcu/xr871/src/xz/xz_private.h | 156 ++ platform/mcu/xr871/src/xz/xz_stream.h | 62 + platform/mcu/xr871/tools/calc_flash_offs | 43 + platform/mcu/xr871/tools/mkimage | Bin 0 -> 45880 bytes platform/mcu/xr871/tools/mkimage.exe | Bin 0 -> 22016 bytes platform/mcu/xr871/tools/phoenixMC.exe | Bin 0 -> 2555904 bytes platform/mcu/xr871/tools/phoenixMC_Linux | Bin 0 -> 98009 bytes platform/mcu/xr871/tools/xz64 | Bin 0 -> 68648 bytes platform/mcu/xr871/xr871-xip.ld | 221 ++ platform/mcu/xr871/xr871.ld | 170 ++ platform/mcu/xr871/xr871.mk | 106 + 589 files changed, 109777 insertions(+), 3 deletions(-) create mode 100644 board/xr871evb/board.c create mode 100644 board/xr871evb/board.h create mode 100644 board/xr871evb/k_config.h create mode 100644 board/xr871evb/xr871evb.mk create mode 100644 platform/mcu/xr871/aos/aos.c create mode 100644 platform/mcu/xr871/aos/aos.h create mode 100644 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create mode 100644 platform/mcu/xr871/xr871.ld create mode 100644 platform/mcu/xr871/xr871.mk diff --git a/board/xr871evb/board.c b/board/xr871evb/board.c new file mode 100644 index 0000000000..b770d832a4 --- /dev/null +++ b/board/xr871evb/board.c @@ -0,0 +1,260 @@ + +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_adc.h" +#include "aos/hal/adc_priv.h" +#include "hal/soc/soc.h" +#include +#include + +/* + 0x0 0x100000 + |--------------------------|--------------------------| + |bootloader(32K) |ota cfg(32K) | + |--------------------------|--------------------------| + |application |ota | + | | | + | | | + | | | + | | | + | | | + | | | + | | | + | | | + |--------------------------|--------------------------| + | |PARAM1(4K) | + |--------------------------|--------------------------| + | |PARAM2(4K) | + |--------------------------|--------------------------| + | |PARAM3(4K) | + |--------------------------|--------------------------| + |SYSINFO(4K) |PARAM4(4K) | + |--------------------------|--------------------------| + */ + +#define SPI_FLASH_CAPACITY 0x200000UL //total capacity +#define OTA_2ND_SEQ_START 0x100000UL //according to image-xip-xz.cfg file + +/* Logic partition on flash devices */ +const hal_logic_partition_t hal_partitions[] = +{ + [HAL_PARTITION_BOOTLOADER] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "Bootloader", + .partition_start_addr = 0x0, + .partition_length = 0x8000, //32k bytes + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS, + }, + [HAL_PARTITION_PARAMETER_1] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "PARAMETER1", + .partition_start_addr = SPI_FLASH_CAPACITY - 4 * 0x1000, + .partition_length = 0x1000, // 4k bytes + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN, + }, + [HAL_PARTITION_PARAMETER_2] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "PARAMETER2", + .partition_start_addr = SPI_FLASH_CAPACITY - 3 * 0x1000, + .partition_length = 0x1000, //4k bytes + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN, + }, + [HAL_PARTITION_APPLICATION] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "Application", + .partition_start_addr = 0x8000, // from 32k bytes + .partition_length = (SPI_FLASH_CAPACITY/2) - 0x8000 - 4 * 0x1000, + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN, + }, + [HAL_PARTITION_OTA_TEMP] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "OTA Storage", + .partition_start_addr = OTA_2ND_SEQ_START + 0x8000, + .partition_length = (SPI_FLASH_CAPACITY/2) - 0x8000 - 4 * 0x1000, + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN, + }, + [HAL_PARTITION_PARAMETER_3] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "PARAMETER3", + .partition_start_addr = SPI_FLASH_CAPACITY - 2 * 0x1000, + .partition_length = 0x1000, //4k bytes + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN, + }, + [HAL_PARTITION_PARAMETER_4] = + { + .partition_owner = HAL_FLASH_EMBEDDED, + .partition_description = "PARAMETER4", + .partition_start_addr = SPI_FLASH_CAPACITY - 1 * 0x1000, + .partition_length = 0x1000, //4k bytes + .partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN, + }, +}; + +#define BOARD_AKEY (1) //adc key ch 1 +#define BOARD_DKEY0 (6) //dkey 0 +#define BOARD_DKEY1 (7) //dkey 1 + +struct board_dkey { + gpio_dev_t gpio; + uint64_t time; +}; +static struct board_dkey board_dkeys[2]; + +static void board_dkey_irq_callback(void* arg) +{ + struct board_dkey *key = arg; + uint32_t level; + uint64_t diff; + uint16_t key_code; + + hal_gpio_input_get(key, &level); + //printf("key[%d] event: %d\n", key->gpio.port, level); + + if (level == 0 && key->time == 0) { + key->time = aos_now_ms(); + } else { + diff = aos_now_ms() - key->time; + if (key->gpio.port == BOARD_DKEY0) + key_code = CODE_BOOT; + if (key->gpio.port == BOARD_DKEY1) + key_code = CODE_VOLUME; + + if (diff > 6000) { /*long long press */ + key->time = 0; + aos_post_event(EV_KEY, key_code, VALUE_KEY_LLTCLICK); + } else if (diff > 2000) { /* long press */ + key->time = 0; + aos_post_event(EV_KEY, key_code, VALUE_KEY_LTCLICK); + } else if (diff > 40) { /* short press */ + key->time = 0; + aos_post_event(EV_KEY, key_code, VALUE_KEY_CLICK); + } + } +} + +void dkey_init(void) +{ + printf("gpio key init...\n"); + memset(&board_dkeys[0], 0, sizeof(struct board_dkey)); + board_dkeys[0].gpio.port = BOARD_DKEY0; + hal_gpio_enable_irq(&board_dkeys[0].gpio, IRQ_TRIGGER_BOTH_EDGES, board_dkey_irq_callback, &board_dkeys[0]); + + memset(&board_dkeys[1], 0, sizeof(struct board_dkey)); + board_dkeys[1].gpio.port = BOARD_DKEY1; + hal_gpio_enable_irq(&board_dkeys[1].gpio, IRQ_TRIGGER_BOTH_EDGES, board_dkey_irq_callback, &board_dkeys[1]); +} + +struct board_akey { + adc_dev_t adc; + uint64_t time; + uint32_t sample_count; + uint32_t avg_val; +}; +static struct board_akey board_adc_key; +#define AKEY12_DOWN_TOGETHER_VOL (300) +#define AKEY1_DOWN_VOL (1000) // 0.5V +#define AKEY2_DOWN_VOL (2000) // 1.05V +#define AKEY3_DOWN_VOL (3000) // 1.65V +#define AKEY_UP_VOL (3800) + +static void board_akey_irq_callback(void* arg) +{ + struct board_akey *akey = arg; + adc_priv_config_t *adc_priv_cfg = (adc_priv_config_t *)akey->adc.priv; + uint32_t level; + uint64_t diff; + uint16_t key_code; + + hal_adc_value_get(&akey->adc, &level, 0xffffffff); + + if (level < AKEY3_DOWN_VOL) { + if (akey->sample_count == 0 && akey->time == 0) { + akey->avg_val = 0; + akey->time = aos_now_ms(); + } + akey->avg_val += level; + akey->sample_count++; + if (akey->sample_count == 10) { + HAL_ADC_ConfigChannel(akey->adc.port, ADC_SELECT_ENABLE, + ADC_IRQMODE_HIGH, adc_priv_cfg->irqlow, adc_priv_cfg->irqhigh); + } + } else if (level > AKEY_UP_VOL) { + HAL_ADC_ConfigChannel(akey->adc.port, ADC_SELECT_ENABLE, + ADC_IRQMODE_LOW, adc_priv_cfg->irqlow, adc_priv_cfg->irqhigh); + diff = aos_now_ms() - akey->time; + // akey up, calc the average voltage + akey->avg_val = akey->avg_val / akey->sample_count; + printf("avg %d, count %d\n", akey->avg_val, akey->sample_count); + if (akey->avg_val < AKEY12_DOWN_TOGETHER_VOL) { + key_code = CODE_ELINK; + } else if (akey->avg_val < AKEY1_DOWN_VOL) { + key_code = CODE_NEXT; + } else if (akey->avg_val < AKEY2_DOWN_VOL) { + key_code = CODE_RECORD_PRE; + } else if (akey->avg_val < AKEY3_DOWN_VOL) { + key_code = CODE_PLAY_PAUSE; + } + + if (diff > 6000) { /*long long press */ + akey->time = 0; + akey->sample_count = 0; + aos_post_event(EV_KEY, key_code, VALUE_KEY_LLTCLICK); + } else if (diff > 2000) { /* long press */ + akey->time = 0; + akey->sample_count = 0; + aos_post_event(EV_KEY, key_code, VALUE_KEY_LTCLICK); + } else if (diff > 40) { /* short press */ + akey->time = 0; + akey->sample_count = 0; + aos_post_event(EV_KEY, key_code, VALUE_KEY_CLICK); + } + } +} + +int adc_key_init(void) +{ + HAL_Status status = HAL_ERROR; + ADC_InitParam initParam; + uint32_t akey_low_vol = 1650 + 100; // 1650mV + uint32_t akey_high_vol = 3000; // 3000mV + static adc_priv_config_t adc_priv_cfg = {0}; + + initParam.delay = 10; + initParam.freq = 500000; // default 500K clock for adc controller + status = HAL_ADC_Init(&initParam); + if (status != HAL_OK) { + printf("[adc_init]: adc init error\n"); + return -1; + } + + memset(&board_adc_key, 0, sizeof(struct board_akey)); + board_adc_key.adc.port = BOARD_AKEY; + board_adc_key.adc.config.sampling_cycle = 500000; // nothing + board_adc_key.adc.priv = &adc_priv_cfg; + adc_priv_cfg.irqmode = ADC_IRQMODE_LOW; + adc_priv_cfg.irqlow = AKEY3_DOWN_VOL; // x/4096 == vol / 2.5 + adc_priv_cfg.irqhigh = AKEY_UP_VOL; + adc_priv_cfg.irq_callback = board_akey_irq_callback; + adc_priv_cfg.arg = &board_adc_key; + hal_adc_init(&board_adc_key.adc); + + status = HAL_ADC_Start_Conv_IT(); + if (status != HAL_OK) { + printf("[adc_init]: ADC it mode start error %d\n", status); + return; + } + return 0; +} + +void board_init(void) +{ + printf("xr871evb board init...\n"); + dkey_init(); + adc_key_init(); + return; +} diff --git a/board/xr871evb/board.h b/board/xr871evb/board.h new file mode 100644 index 0000000000..64377dfbc3 --- /dev/null +++ b/board/xr871evb/board.h @@ -0,0 +1,10 @@ +#define HARDWARE_REVISION "V1.0" +#define MODEL "XR871" + +#ifdef BOOTLOADER +#define STDIO_UART 0 +#define STDIO_UART_BUADRATE 115200 +#else +#define STDIO_UART 0 +#define STDIO_UART_BUADRATE 115200 +#endif diff --git a/board/xr871evb/k_config.h b/board/xr871evb/k_config.h new file mode 100644 index 0000000000..910a2a56fa --- /dev/null +++ b/board/xr871evb/k_config.h @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef CONFIG_H +#define CONFIG_H + +/* chip level conf */ +#ifndef RHINO_CONFIG_LITTLE_ENDIAN +#define RHINO_CONFIG_LITTLE_ENDIAN 1 +#endif +#ifndef RHINO_CONFIG_CPU_STACK_DOWN +#define RHINO_CONFIG_CPU_STACK_DOWN 1 +#endif + +/* kernel feature conf */ +#ifndef RHINO_CONFIG_SEM +#define RHINO_CONFIG_SEM 1 +#endif +#ifndef RHINO_CONFIG_QUEUE +#define RHINO_CONFIG_QUEUE 1 +#endif +#ifndef RHINO_CONFIG_TASK_SEM +#define RHINO_CONFIG_TASK_SEM 1 +#endif +#ifndef RHINO_CONFIG_EVENT_FLAG +#define RHINO_CONFIG_EVENT_FLAG 1 +#endif +#ifndef RHINO_CONFIG_TIMER +#define RHINO_CONFIG_TIMER 1 +#endif +#ifndef RHINO_CONFIG_BUF_QUEUE +#define RHINO_CONFIG_BUF_QUEUE 1 +#endif +#ifndef RHINO_CONFIG_MM_BLK +#define RHINO_CONFIG_MM_BLK 1 +#endif +#ifndef RHINO_CONFIG_MM_DEBUG +#define RHINO_CONFIG_MM_DEBUG 1 +#endif +#ifndef RHINO_CONFIG_MM_TLF +#define RHINO_CONFIG_MM_TLF 1 +#endif +#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE +#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192 +#endif +#define K_MM_STATISTIC 1 +#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT +#define RHINO_CONFIG_MM_MAXMSIZEBIT 19 +#endif +#ifndef RHINO_CONFIG_GCC_RETADDR +#define RHINO_CONFIG_GCC_RETADDR 1 +#endif +#ifndef RHINO_CONFIG_MM_LEAKCHECK +#define RHINO_CONFIG_MM_LEAKCHECK 0 +#endif +#ifndef RHINO_CONFIG_RINGBUF_VENDOR +#define RHINO_CONFIG_RINGBUF_VENDOR 0 +#endif + +#ifndef RHINO_CONFIG_KOBJ_SET +#define RHINO_CONFIG_KOBJ_SET 1 +#endif + +/* kernel task conf */ +#ifndef RHINO_CONFIG_TASK_SUSPEND +#define RHINO_CONFIG_TASK_SUSPEND 1 +#endif +#ifndef RHINO_CONFIG_TASK_INFO +#define RHINO_CONFIG_TASK_INFO 1 +#endif +#ifndef RHINO_CONFIG_TASK_DEL +#define RHINO_CONFIG_TASK_DEL 1 +#endif + +#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK +#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1 +#endif + +#ifndef RHINO_CONFIG_TASK_WAIT_ABORT +#define RHINO_CONFIG_TASK_WAIT_ABORT 1 +#endif +#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK +#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1 +#endif +#ifndef RHINO_CONFIG_SCHED_RR +#define RHINO_CONFIG_SCHED_RR 1 +#endif +#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT +#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50 +#endif +#ifndef RHINO_CONFIG_PRI_MAX +#define RHINO_CONFIG_PRI_MAX 62 +#endif +#ifndef RHINO_CONFIG_USER_PRI_MAX +#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2) +#endif + +/* kernel workqueue conf */ +//#ifndef RHINO_CONFIG_WORKQUEUE +#define RHINO_CONFIG_WORKQUEUE 1 +//#endif +#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE +#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768 +#endif + +/* kernel mm_region conf */ +#ifndef RHINO_CONFIG_MM_REGION_MUTEX +#define RHINO_CONFIG_MM_REGION_MUTEX 0 +#endif + +/* kernel timer&tick conf */ +#ifndef RHINO_CONFIG_HW_COUNT +#define RHINO_CONFIG_HW_COUNT 0 +#endif +#ifndef RHINO_CONFIG_TICK_TASK +#define RHINO_CONFIG_TICK_TASK 0 +#endif + +#if (RHINO_CONFIG_TICK_TASK > 0) +#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE +#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256 +#endif +#ifndef RHINO_CONFIG_TICK_TASK_PRI +#define RHINO_CONFIG_TICK_TASK_PRI 1 +#endif +#endif + +#ifndef RHINO_CONFIG_TICKLESS +#define RHINO_CONFIG_TICKLESS 0 +#endif +#ifndef RHINO_CONFIG_TICKS_PER_SECOND +#define RHINO_CONFIG_TICKS_PER_SECOND 100 +#endif +/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */ +#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY +#define RHINO_CONFIG_TICK_HEAD_ARRAY 8 +#endif + +/*must reserve enough stack size for timer cb will consume*/ +#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE +#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300 +#endif +#ifndef RHINO_CONFIG_TIMER_RATE +#define RHINO_CONFIG_TIMER_RATE 1 +#endif +#ifndef RHINO_CONFIG_TIMER_TASK_PRI +#define RHINO_CONFIG_TIMER_TASK_PRI 5 +#endif + +/* kernel intrpt conf */ +#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET +#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0 +#endif +#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK +#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0 +#endif +#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL +#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u +#endif +#ifndef RHINO_CONFIG_INTRPT_GUARD +#define RHINO_CONFIG_INTRPT_GUARD 0 +#endif + +/* kernel dyn alloc conf */ +#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC +#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1 +#endif + +#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0) +#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG +#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30 +#endif +#ifndef RHINO_CONFIG_K_DYN_TASK_STACK +#define RHINO_CONFIG_K_DYN_TASK_STACK 256 +#endif +#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI +#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6 +#endif +#endif + +/* kernel idle conf */ +#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE +#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200 +#endif + +/* kernel hook conf */ +#ifndef RHINO_CONFIG_USER_HOOK +#define RHINO_CONFIG_USER_HOOK 0 +#endif + +/* kernel stats conf */ +#ifndef RHINO_CONFIG_SYSTEM_STATS +#define RHINO_CONFIG_SYSTEM_STATS 1 +#endif +#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS +#define RHINO_CONFIG_DISABLE_SCHED_STATS 0 +#endif +#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS +#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0 +#endif +#ifndef RHINO_CONFIG_CPU_USAGE_STATS +#define RHINO_CONFIG_CPU_USAGE_STATS 0 +#endif +#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI +#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2) +#endif +#ifndef RHINO_CONFIG_TASK_SCHED_STATS +#define RHINO_CONFIG_TASK_SCHED_STATS 0 +#endif +#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK +#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256 +#endif + +#ifndef RHINO_CONFIG_CPU_NUM +#define RHINO_CONFIG_CPU_NUM 1 +#endif + +/* kernel trace conf */ +#ifndef RHINO_CONFIG_TRACE +#define RHINO_CONFIG_TRACE 0 +#endif + +#endif /* CONFIG_H */ diff --git a/board/xr871evb/xr871evb.mk b/board/xr871evb/xr871evb.mk new file mode 100644 index 0000000000..609fb8894e --- /dev/null +++ b/board/xr871evb/xr871evb.mk @@ -0,0 +1,61 @@ +############################################################################### +# +# The MIT License +# Copyright (c) 2016 MXCHIP Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is furnished +# to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +# IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +############################################################################### + +NAME := board_xr871evb + +JTAG := jlink + +MODULE := XR871EVB +HOST_ARCH := Cortex-M4 +HOST_MCU_FAMILY := xr871 + +$(NAME)_SOURCES := board.c + +GLOBAL_INCLUDES += . +GLOBAL_DEFINES += STDIO_UART=0 + +CURRENT_TIME = $(shell /bin/date +%Y%m%d.%H%M) +define get-os-version +"AOS-R"-$(CURRENT_TIME) +endef + +CONFIG_SYSINFO_OS_VERSION := $(call get-os-version) + +$(warning $(CONFIG_SYSINFO_OS_VERSION)) + +CONFIG_SYSINFO_PRODUCT_MODEL := ALI_AOS_XR871 +CONFIG_SYSINFO_DEVICE_NAME := XR871 +$(warning ${CONFIG_SYSINFO_OS_VERSION}) + +GLOBAL_CFLAGS += -DSYSINFO_OS_VERSION=\"$(CONFIG_SYSINFO_OS_VERSION)\" +GLOBAL_CFLAGS += -DSYSINFO_PRODUCT_MODEL=\"$(CONFIG_SYSINFO_PRODUCT_MODEL)\" +GLOBAL_CFLAGS += -DSYSINFO_DEVICE_NAME=\"$(CONFIG_SYSINFO_DEVICE_NAME)\" +GLOBAL_CFLAGS += -DSYSINFO_ARCH=\"$(HOST_ARCH)\" +GLOBAL_CFLAGS += -DSYSINFO_MCU=\"$(HOST_MCU_FAMILY)\" +GLOBAL_CFLAGS += -DSYSINFO_BOARD=\"$(MODULE)\" + +GLOBAL_LDFLAGS += -L $(SOURCE_ROOT)/board/xr871evb + +# Extra build image +EXTRA_TARGET_MAKEFILES += $(MAKEFILES_PATH)/aos_standard_targets.mk +EXTRA_TARGET_MAKEFILES += $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/mkimage.mk diff --git a/example/alinkapp/alinkapp.mk b/example/alinkapp/alinkapp.mk index c687540fa5..0d951695fb 100644 --- a/example/alinkapp/alinkapp.mk +++ b/example/alinkapp/alinkapp.mk @@ -19,7 +19,7 @@ endif ifneq (,$(filter linux,$(HOST_MCU_FAMILY))) gateway ?= 0 else -ifneq (,$(filter stm32f4xx,$(HOST_MCU_FAMILY))) +ifneq (,$(filter stm32f4xx xr871,$(HOST_MCU_FAMILY))) gateway ?= 0 else gateway ?= 1 diff --git a/platform/arch/arm/armv7m/gcc/m4/port_s.S b/platform/arch/arm/armv7m/gcc/m4/port_s.S index d4c8c5404a..00513d99ed 100644 --- a/platform/arch/arm/armv7m/gcc/m4/port_s.S +++ b/platform/arch/arm/armv7m/gcc/m4/port_s.S @@ -123,7 +123,7 @@ PendSV_Handler: @save context #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) - VSTMFD R0!, {D8 - D15} + VSTMDB R0!, {D8 - D15} #endif SUBS R0, R0, #0x24 @@ -149,7 +149,7 @@ _pendsv_handler_nosave: ADDS R0, R0, #0x24 #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) - VLDMFD R0!, {D8 - D15} + VLDMIA R0!, {D8 - D15} #endif @return stack = PSP diff --git a/platform/mcu/xr871/aos/aos.c b/platform/mcu/xr871/aos/aos.c new file mode 100644 index 0000000000..b2efaa11ce --- /dev/null +++ b/platform/mcu/xr871/aos/aos.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#include +#include +#include +#include +#include + +#define AOS_START_STACK 2048 + +ktask_t *g_aos_init; + +extern void board_init(void); +extern void aos_cli_ext_init(void); +extern int application_start(int argc, char **argv); + +#include "net/wlan/wlan.h" + +static void wifi_join(char* ssid, char* psk) +{ + wlan_sta_set(ssid, strlen(psk), psk); + wlan_sta_enable(); +} + +static void aos_system_init(void) +{ + int i; + + soc_driver_init(); + + printf("aos_init now...\n"); + + soc_system_init(); + + hal_init_post(); + + //wifi_join("\"AW2\"", "\"1qaz@WSX\""); + //wifi_join("\"MI\"", "\"xiaomi123\""); + //wifi_join("\"mao\"", "\"11111111\""); + //wifi_join("\"mao\"", NULL); + + board_init(); + + vfs_init(); + vfs_device_init(); + +#ifdef CONFIG_AOS_FATFS_SUPPORT + /* if enable the macro, please also enable CONFIG_AOS_FATFS_SUPPORT_MMC + * and include , add modules.fs.fatfs to component dependence + */ + fatfs_register(); +#endif + + aos_cli_init(); + aos_cli_ext_init(); + aos_kv_init(); + aos_loop_init(); + + aos_framework_init(); + + application_start(0, NULL); +} + +void aos_startup(void) +{ + soc_sys_mem_init(); + + soc_systick_init(); + + krhino_init(); + + krhino_task_dyn_create(&g_aos_init, "aos-init", 0, 10, 0, AOS_START_STACK, aos_system_init, 1); + + krhino_start(); +} diff --git a/platform/mcu/xr871/aos/aos.h b/platform/mcu/xr871/aos/aos.h new file mode 100644 index 0000000000..0238422356 --- /dev/null +++ b/platform/mcu/xr871/aos/aos.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef AOS_H +#define AOS_H + +void soc_driver_init(void); + +void soc_system_init(void); + +void aos_startup(void); + +#endif /* AOS_H */ diff --git a/platform/mcu/xr871/aos/aos.mk b/platform/mcu/xr871/aos/aos.mk new file mode 100644 index 0000000000..c3657febb2 --- /dev/null +++ b/platform/mcu/xr871/aos/aos.mk @@ -0,0 +1,23 @@ +NAME := aos + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := aos.c \ + aos_impl.c \ + soc_impl.c \ + hal/soc/adc.c \ + hal/soc/flash.c \ + hal/soc/gpio.c \ + hal/soc/i2c.c \ + hal/soc/pwm.c \ + hal/soc/rtc.c \ + hal/soc/sd.c \ + hal/soc/timer.c \ + hal/soc/uart.c \ + hal/soc/wdg.c \ + hal/fota_port.c \ + hal/wifi_port.c \ + hal/wifi.c \ + hal/hal.c \ + cli_ext/cli_ext.c \ + cli_ext/cli_mem.c \ + cli_ext/cli_upgrade.c \ No newline at end of file diff --git a/platform/mcu/xr871/aos/aos_impl.c b/platform/mcu/xr871/aos/aos_impl.c new file mode 100644 index 0000000000..8358d3beb3 --- /dev/null +++ b/platform/mcu/xr871/aos/aos_impl.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#include + +#if (RHINO_CONFIG_TASK_STACK_CUR_CHECK > 0) +size_t soc_get_cur_sp(void) +{ + volatile size_t dummy = (size_t)&dummy; + return dummy; +} +#endif + +#if (RHINO_CONFIG_HW_COUNT > 0) +void soc_hw_timer_init(void) +{ +} + +hr_timer_t soc_hr_hw_cnt_get(void) +{ + return 0; +} + +lr_timer_t soc_lr_hw_cnt_get(void) +{ + return 0; +} +#endif /* RHINO_CONFIG_HW_COUNT */ + +#if (RHINO_CONFIG_INTRPT_GUARD > 0) +void soc_intrpt_guard(void) +{ +} +#endif + +#if (RHINO_CONFIG_INTRPT_STACK_REMAIN_GET > 0) +size_t soc_intrpt_stack_remain_get(void) +{ + return 0; +} +#endif + +#if (RHINO_CONFIG_INTRPT_STACK_OVF_CHECK > 0) +void soc_intrpt_stack_ovf_check(void) +{ +} +#endif + +#if (RHINO_CONFIG_DYNTICKLESS > 0) +void soc_tick_interrupt_set(tick_t next_ticks,tick_t elapsed_ticks) +{ +} + +tick_t soc_elapsed_ticks_get(void) +{ + return 0; +} +#endif + +#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0) +extern void *heap_start; +extern void *heap_len; +k_mm_region_t g_mm_region[] = {{(uint8_t *)&heap_start, (size_t)&heap_len}}; +int g_region_num = sizeof(g_mm_region) / sizeof(k_mm_region_t); + + +void soc_sys_mem_init(void) +{ + extern void *heap_start; + extern void *heap_len; + + g_mm_region[0].start = &heap_start; + g_mm_region[0].len = &heap_len; + g_region_num = 1; +} + + +#endif + +void soc_err_proc(kstat_t err) +{ +} + +krhino_err_proc_t g_err_proc = soc_err_proc; diff --git a/platform/mcu/xr871/aos/cli_ext/cli_ext.c b/platform/mcu/xr871/aos/cli_ext/cli_ext.c new file mode 100644 index 0000000000..d5c9731292 --- /dev/null +++ b/platform/mcu/xr871/aos/cli_ext/cli_ext.c @@ -0,0 +1,9 @@ + +extern void cli_cmd_add_upgrade(void); +extern void cli_cmd_add_mem(void); + +void aos_cli_ext_init(void) +{ + cli_cmd_add_upgrade(); + cli_cmd_add_mem(); +} diff --git a/platform/mcu/xr871/aos/cli_ext/cli_mem.c b/platform/mcu/xr871/aos/cli_ext/cli_mem.c new file mode 100644 index 0000000000..998e6105fd --- /dev/null +++ b/platform/mcu/xr871/aos/cli_ext/cli_mem.c @@ -0,0 +1,80 @@ + +#include +#include "driver/chip/hal_chip.h" + +#define readl(addr) (*((volatile unsigned long *)(addr))) +#define writel(v, addr) (*((volatile unsigned long *)(addr)) = (unsigned long)(v)) + +static void hexdump(char* msg, uint32_t addr, uint32_t len) +{ + int i; + printf("%s:", msg); + for (i = 0; i < len; i += 4) { + if (i % 16 == 0) { + printf("\n"); + printf("%08x: ", addr + i); + } + printf("%08x ", readl(addr + i)); + } + printf("\n"); +} + +static void handle_mem_cmd(char *pwbuf, int blen, int argc, char **argv) +{ + uint32_t addr; + uint32_t len; + uint32_t val; + uint32_t op = 0; + + if (argc < 3) { + printf("cmd_mem: Wrong Arguments\n"); + return; + } + if (strcmp(argv[1], "read") == 0) { + op = 0; + } else if (strcmp(argv[1], "write") == 0) { + op = 1; + } else if (strcmp(argv[1], "dump") == 0) { + op = 2; + } + + addr = strtoul(argv[2], NULL, 16); + /* check alignment */ + if (addr & 0x1) { + printf("** addr is not aligned !!\n"); + return; + } + + if (op == 0) { + val = readl(addr); + printf("read: [0x%x]:: 0x%08x", addr, val); + } else if (op == 1) { + if (argc < 4) { + printf("** Wrong Arguments !!\n"); + return; + } + val = strtoul(argv[3], NULL, 16); + writel(val, addr); + printf("write: [0x%x]: 0x%08x", addr, val); + } else { + if (argc < 4) { + len = 256; + } else { + len = strtoul(argv[3], NULL, 10); + } + hexdump("dump", addr, len); + } + printf("\n"); + return ; +} + +static struct cli_command ncmd = { + .name = "mem", + .help = "mem [read addr | write addr val | dump addr len]", + .function = handle_mem_cmd, +}; + +void cli_cmd_add_mem(void) +{ + aos_cli_register_command(&ncmd); +} diff --git a/platform/mcu/xr871/aos/cli_ext/cli_upgrade.c b/platform/mcu/xr871/aos/cli_ext/cli_upgrade.c new file mode 100644 index 0000000000..fa3ee73405 --- /dev/null +++ b/platform/mcu/xr871/aos/cli_ext/cli_upgrade.c @@ -0,0 +1,25 @@ + +#include +#include "driver/chip/hal_chip.h" +#include "driver/chip/system_chip.h" +#include "net/wlan/wlan.h" + +static void handle_upgrade_cmd(char *pwbuf, int blen, int argc, char **argv) +{ + net_sys_stop(); + SystemDeInit(SYSTEM_DEINIT_FLAG_RESET_CLK); + HAL_PRCM_SetCPUABootFlag(PRCM_CPUA_BOOT_FROM_SYS_UPDATE); + *((volatile unsigned long*)0xE000ED08) = 0; + *((volatile unsigned long*)0xE000ED0C) = 0x05fa0001; +} + +static struct cli_command ncmd = { + .name = "upgrade", + .help = "upgrade", + .function = handle_upgrade_cmd, +}; + +void cli_cmd_add_upgrade(void) +{ + aos_cli_register_command(&ncmd); +} diff --git a/platform/mcu/xr871/aos/hal/fota_port.c b/platform/mcu/xr871/aos/hal/fota_port.c new file mode 100644 index 0000000000..16b9a67d81 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/fota_port.c @@ -0,0 +1,186 @@ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include "sys/image.h" +#include "sys/ota.h" + +#define OTA_DEBUG_ON 0 +#define OTA_ERROR_ON 0 + +#if OTA_DEBUG_ON +#define OTA_DEBUG(...) do { \ + printf("[ota debug]: "); \ + printf(__VA_ARGS__); \ + } while (0) +#else +#define OTA_DEBUG(...) +#endif + +#if OTA_ERROR_ON +#define OTA_ERROR(...) do { \ + printf("[ota error]: "); \ + printf(__VA_ARGS__); \ + } while (0) +#else +#define OTA_ERROR(...) +#endif + +typedef struct +{ + uint32_t dst_adr; + uint32_t src_adr; + uint32_t siz; + uint16_t crc; +} __attribute__((packed)) ota_hdl_t; + +typedef struct +{ + uint32_t ota_len; + uint32_t ota_crc; +} ota_reboot_info_t; + +static ota_reboot_info_t ota_info; + +static CRC16_Context contex; +hal_partition_t ota_partition = HAL_PARTITION_OTA_TEMP; + +static int xr871_ota_init(hal_ota_module_t *m, void *something) +{ + hal_logic_partition_t *partition_info; + + image_seq_t seq; + ota_cfg_t cfg; + + OTA_DEBUG("xr871_ota_init enter\n"); + + if (ota_read_cfg(&cfg) != OTA_STATUS_OK) + OTA_ERROR("ota read cfg failed\n"); + + if (((cfg.image == OTA_IMAGE_1ST) && (cfg.state == OTA_STATE_VERIFIED)) + || ((cfg.image == OTA_IMAGE_2ND) && (cfg.state == OTA_STATE_UNVERIFIED))) { + seq = IMAGE_SEQ_1ST; + } else if (((cfg.image == OTA_IMAGE_2ND) && (cfg.state == OTA_STATE_VERIFIED)) + || ((cfg.image == OTA_IMAGE_1ST) && (cfg.state == OTA_STATE_UNVERIFIED))) { + seq = IMAGE_SEQ_2ND; + } else { + OTA_ERROR("invalid image %d, state %d\n", cfg.image, cfg.state); + seq = IMAGE_SEQ_1ST; + } + + OTA_DEBUG("image seq %d\n", seq); + + if (seq == IMAGE_SEQ_1ST) { + ota_partition = HAL_PARTITION_OTA_TEMP; + partition_info = hal_flash_get_info( HAL_PARTITION_OTA_TEMP ); + hal_flash_erase(HAL_PARTITION_OTA_TEMP, 0 ,partition_info->partition_length); + } + else if (seq == OTA_IMAGE_2ND) { + ota_partition = HAL_PARTITION_APPLICATION; + partition_info = hal_flash_get_info( HAL_PARTITION_APPLICATION); + hal_flash_erase(HAL_PARTITION_APPLICATION, 0 ,partition_info->partition_length); + } + ota_info.ota_len = 0; + + //CRC16_Init( &contex ); + memset(&ota_info, 0 , sizeof ota_info); + + OTA_DEBUG("xr871_ota_init exit\n"); + return 0; +} + + +static int xr871_ota_write(hal_ota_module_t *m, volatile uint32_t* off_set, uint8_t* in_buf ,uint32_t in_buf_len) +{ + int ret = 0; + unsigned int _off_set = 0; + + OTA_DEBUG("xr871_ota_write enter\n"); + + if (ota_info.ota_len + in_buf_len < 0x8000) { + //do nothing + } + else if(ota_info.ota_len >= 0x8000) + { + _off_set = ota_info.ota_len -0x8000; + ret = hal_flash_write(ota_partition, &_off_set, in_buf, in_buf_len); + } + else { + int rem; + + rem = ota_info.ota_len + in_buf_len - 0x8000; + _off_set = 0; + + ret = hal_flash_write(ota_partition, &_off_set, &in_buf[in_buf_len-rem], rem); + } + + ota_info.ota_len += in_buf_len; + + //CRC16_Update( &contex, in_buf, in_buf_len); + + OTA_DEBUG(" &_off_set 0x %08x, %d\n", _off_set ,ota_info.ota_len); + + OTA_DEBUG("xr871_ota_write exit\n"); + + return ret; +} + +static int xr871_ota_read(hal_ota_module_t *m, volatile uint32_t* off_set, uint8_t* out_buf, uint32_t out_buf_len) +{ + uint32_t temp; + + OTA_DEBUG("xr871_ota_read enter\n"); + + temp = *off_set; + + if (ota_partition == HAL_PARTITION_OTA_TEMP) { + temp += 0x8000; + } + + hal_flash_read(ota_partition, &temp, out_buf, out_buf_len); + + *off_set += out_buf_len; + OTA_DEBUG("xr871_ota_read exit\n"); + + return 0; +} + +static int xr871_ota_set_boot(hal_ota_module_t *m, void *something) +{ + ota_cfg_t ota_cfg; + uint8_t parti = *(uint8_t *)something; + //CRC16_Final( &contex, &ota_info.ota_crc ); + OTA_DEBUG("xr871 set boot\n"); + + if (ota_partition == HAL_PARTITION_OTA_TEMP) { + ota_cfg.image = 2; + } + else { + ota_cfg.image = 1; + } + + ota_cfg.state = OTA_STATE_UNVERIFIED; + ota_write_cfg(&ota_cfg); + ota_set_size(ota_info.ota_len); + if (ota_verify_image(OTA_VERIFY_NONE, NULL) != OTA_STATUS_OK) { + OTA_DEBUG("xr871 set boot fail\n"); + } + + /* reboot */ + hal_reboot(); + + return 0; +} + +struct hal_ota_module_s xr871_ota_module = { + .init = xr871_ota_init, + .ota_write = xr871_ota_write, + .ota_read = xr871_ota_read, + .ota_set_boot = xr871_ota_set_boot, +}; diff --git a/platform/mcu/xr871/aos/hal/hal.c b/platform/mcu/xr871/aos/hal/hal.c new file mode 100644 index 0000000000..e90730bacc --- /dev/null +++ b/platform/mcu/xr871/aos/hal/hal.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "hal/soc/soc.h" +#include "hal/wifi.h" +#include "hal/ota.h" + +#include "sys/interrupt.h" + +#include "board.h" + +extern int errno; +wdg_dev_t wdg; +uart_dev_t uart_0; +sd_dev_t sd_dev; + +extern hal_wifi_module_t sim_aos_wifi_xr871; +extern hal_ota_module_t xr871_ota_module; + +void hal_init(void) +{ + // init uart + uart_0.port = STDIO_UART; + uart_0.config.baud_rate = STDIO_UART_BUADRATE; + uart_0.config.data_width = DATA_WIDTH_8BIT; + uart_0.config.parity = NO_PARITY; + uart_0.config.stop_bits = STOP_BITS_1; + uart_0.config.flow_control = FLOW_CONTROL_DISABLED; + printf("uart_0.port:%d\n",uart_0.port); + hal_uart_init(&uart_0); +} + +void hal_init_post(void) +{ + // init wifi + hal_wifi_register_module(&sim_aos_wifi_xr871); + hal_wifi_init(); + + hal_ota_register_module(&xr871_ota_module); +} + +void hal_boot(hal_partition_t partition) +{ + uint32_t addr; + + intc_deinit(); + + addr = hal_flash_get_info(partition)->partition_start_addr; + __asm volatile ("BX %0" : : "r" (addr) ); +} + +void hal_reboot(void) +{ + HAL_WDG_Reboot(); +} + diff --git a/platform/mcu/xr871/aos/hal/soc/adc.c b/platform/mcu/xr871/aos/hal/soc/adc.c new file mode 100644 index 0000000000..b02156e99a --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/adc.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file hal/soc/adc.h + * @brief adc HAL + * @version since 5.5.0 + */ + +#include "hal/soc/soc.h" +#include "driver/chip/hal_adc.h" +#include "aos/hal/adc_priv.h" + +/**@biref Initialises an ADC interface + * + * Prepares an ADC hardware interface for sampling + * + * @param adc : the interface which should be initialised + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_adc_init(adc_dev_t *adc) +{ + HAL_Status status = HAL_ERROR; + adc_priv_config_t *adc_priv_cfg = (adc_priv_config_t*)adc->priv; + + status = HAL_ADC_ConfigChannel(adc->port, ADC_SELECT_ENABLE, + adc_priv_cfg->irqmode, adc_priv_cfg->irqlow, adc_priv_cfg->irqhigh); + if (status != HAL_OK) { + printf("[hal_adc]: ADC ch %d config error %d\n", adc->port, status); + return -1; + } + + status = HAL_ADC_EnableIRQCallback(adc->port, adc_priv_cfg->irq_callback, adc_priv_cfg->arg); + if (status != HAL_OK) { + printf("[hal_adc]: ADC ch %d IRQ Enable error %d\n", adc->port, status); + return -1; + } + + return 0; +} + + +/**@biref Takes a single sample from an ADC interface + * + * Takes a single sample from an ADC interface + * + * @param adc : the interface which should be sampled + * @param output : pointer to a variable which will receive the sample + * @param timeout : ms timeout + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_adc_value_get(adc_dev_t *adc, void *output, uint32_t timeout) +{ + *(uint32_t*)output = HAL_ADC_GetValue(adc->port); + return 0; +} + + +/**@biref De-initialises an ADC interface + * + * @abstract Turns off an ADC hardware interface + * + * @param adc : the interface which should be de-initialised + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_adc_finalize(adc_dev_t *adc) +{ + HAL_Status status = HAL_ERROR; + + status = HAL_ADC_ConfigChannel(adc->port, ADC_SELECT_DISABLE, 0, 0, 0); + if (status != HAL_OK) { + printf("[hal_adc]: ADC ch config error %d\n", status); + } + + status = HAL_ADC_DisableIRQCallback(adc->port); + if (status != HAL_OK) { + printf("[hal_adc]: ADC ch cb disable error %d\n", status); + } + return 0; +} + diff --git a/platform/mcu/xr871/aos/hal/soc/flash.c b/platform/mcu/xr871/aos/hal/soc/flash.c new file mode 100644 index 0000000000..69763d7f7b --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/flash.c @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "hal/soc/soc.h" +#include "mico_rtos.h" + +#include "driver/chip/hal_chip.h" + +#define XR871_FLASH PRJCONF_IMG_FLASH + +extern wdg_dev_t wdg; + +#if 0 + +#define FIQMASK_REG_NAME_R "faultmask" +#define FIQMASK_REG_NAME_W "faultmask" + +/* + * Save the current interrupt enable state & disable FIQs + */ +static __always_inline unsigned long xr_fiq_save(void) +{ + unsigned long flags; + + __asm volatile( + "mrs %0, " FIQMASK_REG_NAME_R "\n" + "cpsid f" + : "=r" (flags) : : "memory", "cc"); + return flags; +} + +/* + * restore saved FIQ state + */ +static __always_inline void xr_fiq_restore(unsigned long flags) +{ + __asm volatile( + "msr " FIQMASK_REG_NAME_W ", %0" + : + : "r" (flags) + : "memory", "cc"); +} + +#define GLOBAL_INT_DECLARATION() uint32_t fiq_tmp, irq_tmp +#define GLOBAL_INT_DISABLE() do{\ + fiq_tmp = xr_fiq_save();\ + irq_tmp = xr_irq_save();\ + }while(0) + + +#define GLOBAL_INT_RESTORE() do{ \ + xr_fiq_restore(fiq_tmp);\ + xr_irq_restore(irq_tmp);\ + }while(0) +#else +#define GLOBAL_INT_DECLARATION() +#define GLOBAL_INT_DISABLE() +#define GLOBAL_INT_RESTORE() +#endif + +#define SECTOR_SIZE 0x1000 /* 4 K/sector */ + +extern const hal_logic_partition_t hal_partitions[]; + +hal_logic_partition_t *hal_flash_get_info(hal_partition_t in_partition) +{ + hal_logic_partition_t *logic_partition; + + logic_partition = (hal_logic_partition_t *)&hal_partitions[ in_partition ]; + + return logic_partition; +} + +int32_t hal_flash_erase(hal_partition_t in_partition, uint32_t off_set, uint32_t size) +{ + uint32_t addr; + uint32_t start_addr, end_addr; + hal_logic_partition_t *partition_info; + +#ifdef CONFIG_AOS_KV_MULTIPTN_MODE + if (in_partition == CONFIG_AOS_KV_PTN) { + if (off_set >= CONFIG_AOS_KV_PTN_SIZE) { + in_partition = CONFIG_AOS_KV_SECOND_PTN; + off_set -= CONFIG_AOS_KV_PTN_SIZE; + } + } +#endif + + + GLOBAL_INT_DECLARATION(); + + partition_info = hal_flash_get_info( in_partition ); + + if(size + off_set > partition_info->partition_length) + return -1; + + start_addr = (partition_info->partition_start_addr + off_set) & (~0xFFF); + end_addr = (partition_info->partition_start_addr + off_set + size - 1) & (~0xFFF); + + for(addr = start_addr; addr <= end_addr; addr += SECTOR_SIZE) + { + hal_wdg_reload(&wdg); + GLOBAL_INT_DISABLE(); + //flash_ctrl(CMD_FLASH_ERASE_SECTOR, &addr); + //printf("flash_ctrl: addr=0x%08x\n", addr); + flash_erase(XR871_FLASH, addr, SECTOR_SIZE); + GLOBAL_INT_RESTORE(); + } + hal_wdg_reload(&wdg); + + return 0; +} + +int32_t hal_flash_write(hal_partition_t in_partition, uint32_t *off_set, const void *in_buf , uint32_t in_buf_len) +{ + uint32_t start_addr; + hal_logic_partition_t *partition_info; + +#ifdef CONFIG_AOS_KV_MULTIPTN_MODE + if (in_partition == CONFIG_AOS_KV_PTN) { + if ((*off_set) >= CONFIG_AOS_KV_PTN_SIZE) { + in_partition = CONFIG_AOS_KV_SECOND_PTN; + *off_set = (*off_set) - CONFIG_AOS_KV_PTN_SIZE; + } + } +#endif + + GLOBAL_INT_DECLARATION(); + + partition_info = hal_flash_get_info( in_partition ); + + if(off_set == NULL || in_buf == NULL || *off_set + in_buf_len > partition_info->partition_length) + return -1; + + start_addr = partition_info->partition_start_addr + *off_set; + + hal_wdg_reload(&wdg); + GLOBAL_INT_DISABLE(); + //flash_write(in_buf, in_buf_len, start_addr); + //printf("flash_write: addr=0x%08x,len=%d\n", start_addr, in_buf_len); + flash_write(XR871_FLASH, start_addr, in_buf, in_buf_len); + GLOBAL_INT_RESTORE(); + hal_wdg_reload(&wdg); + + *off_set += in_buf_len; + + return 0; +} + +int32_t hal_flash_read(hal_partition_t in_partition, uint32_t *off_set, void *out_buf, uint32_t out_buf_len) +{ + uint32_t start_addr; + hal_logic_partition_t *partition_info; + +#ifdef CONFIG_AOS_KV_MULTIPTN_MODE + if (in_partition == CONFIG_AOS_KV_PTN) { + if ((*off_set) >= CONFIG_AOS_KV_PTN_SIZE) { + in_partition = CONFIG_AOS_KV_SECOND_PTN; + *off_set = (*off_set) - CONFIG_AOS_KV_PTN_SIZE; + } + } +#endif + + GLOBAL_INT_DECLARATION(); + + partition_info = hal_flash_get_info( in_partition ); + + if(off_set == NULL || out_buf == NULL || *off_set + out_buf_len > partition_info->partition_length) + return -1; + + start_addr = partition_info->partition_start_addr + *off_set; + + hal_wdg_reload(&wdg); + GLOBAL_INT_DISABLE(); + //flash_read(out_buf, out_buf_len, start_addr); + //printf("flash_read: addr=0x%08x,len=%d\n", start_addr, out_buf_len); + flash_read(XR871_FLASH, start_addr, out_buf, out_buf_len); + GLOBAL_INT_RESTORE(); + hal_wdg_reload(&wdg); + + *off_set += out_buf_len; + + return 0; +} + +int32_t hal_flash_enable_secure(hal_partition_t partition, uint32_t off_set, uint32_t size) +{ + return 0; +} + +int32_t hal_flash_dis_secure(hal_partition_t partition, uint32_t off_set, uint32_t size) +{ + return 0; +} diff --git a/platform/mcu/xr871/aos/hal/soc/gpio.c b/platform/mcu/xr871/aos/hal/soc/gpio.c new file mode 100644 index 0000000000..e27718c355 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/gpio.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "hal/soc/soc.h" +#include "driver/chip/hal_gpio.h" + +static GPIO_InitParam gpios[GPIOA_PIN_NUM]; +static GPIO_IrqParam eints[GPIOA_PIN_NUM]; +/**@brief Initialises a GPIO pin + * + * @note Prepares a GPIO pin for use. + * + * @param gpio : the gpio pin which should be initialised + * @param configuration : A structure containing the required + * gpio configuration + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_init(gpio_dev_t *gpio) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + memset(&gpios[gpio->port], 0, sizeof(GPIO_InitParam)); + gpios[gpio->port].driving = GPIO_DRIVING_LEVEL_2; + switch (gpio->config) { + case INPUT_HIGH_IMPEDANCE: + gpios[gpio->port].mode = GPIOx_Pn_F7_DISABLE; + case INPUT_PULL_UP: + gpios[gpio->port].mode = GPIOx_Pn_F0_INPUT; + gpios[gpio->port].pull = GPIO_PULL_UP; + case INPUT_PULL_DOWN: + gpios[gpio->port].mode = GPIOx_Pn_F0_INPUT; + gpios[gpio->port].pull = GPIO_PULL_DOWN; + break; + case OUTPUT_OPEN_DRAIN_PULL_UP: + gpios[gpio->port].mode = GPIOx_Pn_F1_OUTPUT; + gpios[gpio->port].pull = GPIO_PULL_UP; + break; + case OUTPUT_PUSH_PULL: + gpios[gpio->port].mode = GPIOx_Pn_F1_OUTPUT;; + gpios[gpio->port].pull = GPIO_PULL_NONE; + break; + case OUTPUT_OPEN_DRAIN_NO_PULL: + gpios[gpio->port].pull = GPIO_PULL_NONE; + gpios[gpio->port].mode = GPIOx_Pn_F1_OUTPUT;; + break; + default: + break; + } + HAL_GPIO_Init(GPIO_PORT_A, gpio->port, &gpios[gpio->port]); + return 0; + } + printf("[hal_gpio]: gpio[%d] init failed\n", gpio ? gpio->port : -1); + return -1; +} + +/**@brief Sets an output GPIO pin high + * + * @note Using this function on a gpio pin which is set to input mode is undefined. + * + * @param gpio : the gpio pin which should be set high + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_output_high(gpio_dev_t *gpio) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + HAL_GPIO_WritePin(GPIO_PORT_A, gpio->port, GPIO_PIN_HIGH); + return 0; + } + printf("[hal_gpio]: gpio[%d] output highlevel failed\n", gpio ? gpio->port : -1); + return -1; +} + + +/**@brief Sets an output GPIO pin low + * + * @note Using this function on a gpio pin which is set to input mode is undefined. + * + * @param gpio : the gpio pin which should be set low + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_output_low(gpio_dev_t *gpio) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + HAL_GPIO_WritePin(GPIO_PORT_A, gpio->port, GPIO_PIN_LOW); + return 0; + } + printf("[hal_gpio]: gpio[%d] output lowlevel failed\n", gpio ? gpio->port : -1); + return -1; +} + +/** Trigger an output GPIO pin + * + * Trigger an output GPIO pin's output. Using this function on a + * gpio pin which is set to input mode is undefined. + * + * @param gpio : the gpio pin which should be set low + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_output_toggle(gpio_dev_t *gpio) +{ + // TODO: + return -1; +} + +/**@brief Get the state of an input GPIO pin + * + * @note Get the state of an input GPIO pin. Using this function on a + * gpio pin which is set to output mode will return an undefined value. + * + * @param gpio : the gpio pin which should be read + * @param value : gpio value + * @return 0 : on success + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_input_get(gpio_dev_t *gpio, uint32_t *value) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + *value = HAL_GPIO_ReadPin(GPIO_PORT_A, gpio->port); + return 0; + } + printf("[hal_gpio]: gpio[%d] get input value failed\n", gpio ? gpio->port : -1); + return -1; +} + + +/**@brief Enables an interrupt trigger for an input GPIO pin + * + * @note Enables an interrupt trigger for an input GPIO pin. + * Using this function on a gpio pin which is set to + * output mode is undefined. + * + * @param gpio : the gpio pin which will provide the interrupt trigger + * @param trigger : the type of trigger (rising/falling edge) + * @param handler : a function pointer to the interrupt handler + * @param arg : an argument that will be passed to the + * interrupt handler + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_enable_irq(gpio_dev_t *gpio, gpio_irq_trigger_t trigger, + gpio_irq_handler_t handler, void *arg) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + GPIO_InitParam param = {0}; + + memset(&eints[gpio->port], 0, sizeof(GPIO_IrqParam)); + + param.driving = GPIO_DRIVING_LEVEL_1; + param.mode = GPIOx_Pn_F6_EINT; + param.pull = GPIO_PULL_UP; + HAL_GPIO_Init(GPIO_PORT_A, gpio->port, ¶m); + + if (trigger == IRQ_TRIGGER_RISING_EDGE) { + eints[gpio->port].event = GPIO_IRQ_EVT_RISING_EDGE; + } else if (trigger == IRQ_TRIGGER_FALLING_EDGE) { + eints[gpio->port].event = GPIO_IRQ_EVT_FALLING_EDGE; + } else if (trigger == IRQ_TRIGGER_BOTH_EDGES) { + eints[gpio->port].event = GPIO_IRQ_EVT_BOTH_EDGE; + } + eints[gpio->port].callback = handler; + eints[gpio->port].arg = arg; + HAL_GPIO_EnableIRQ(GPIO_PORT_A, gpio->port, &eints[gpio->port]); + return 0; + } + printf("[hal_gpio]: gpio[%d] enable irq failed\n", gpio ? gpio->port : -1); + return -1; +} + + +/**@brief Disables an interrupt trigger for an input GPIO pin + * + * @note Disables an interrupt trigger for an input GPIO pin. + * Using this function on a gpio pin which has not been set up + * using @ref hal_gpio_input_irq_enable is undefined. + * + * @param gpio : the gpio pin which provided the interrupt trigger + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_disable_irq(gpio_dev_t *gpio) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + HAL_GPIO_DisableIRQ(GPIO_PORT_A, gpio->port); + memset(&eints[gpio->port], 0, sizeof(GPIO_IrqParam)); + return 0; + } + + printf("[hal_gpio]: gpio[%d] disable irq failed\n", gpio ? gpio->port : -1); + return -1; +} + + +/**@brief Disables an interrupt trigger for an input GPIO pin + * + * @note Disables an interrupt trigger for an input GPIO pin. + * Using this function on a gpio pin which has not been set up + * using @ref hal_gpio_input_irq_enable is undefined. + * + * @param gpio : the gpio pin which provided the interrupt trigger + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_clear_irq(gpio_dev_t *gpio) +{ + return 0; +} + + +/**@brief DeInitialises a GPIO pin + * + * @note Set a GPIO pin in default state. + * + * @param gpio : the gpio pin which should be deinitialised + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_gpio_finalize(gpio_dev_t *gpio) +{ + if (gpio && gpio->port < GPIOA_PIN_NUM) { + HAL_GPIO_DeInit(GPIO_PORT_A, gpio->port); + memset(&gpios[gpio->port], 0, sizeof(GPIO_InitParam)); + return 0; + } + return -1; +} diff --git a/platform/mcu/xr871/aos/hal/soc/i2c.c b/platform/mcu/xr871/aos/hal/soc/i2c.c new file mode 100644 index 0000000000..5f05660872 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/i2c.c @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#include +#include "hal/soc/soc.h" +#include "driver/chip/hal_i2c.h" + +/**@brief Initialises an I2C interface + * @note Prepares an I2C hardware interface for communication as a master or slave + * + * @param device : the device for which the i2c port should be initialised + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2c_init(i2c_dev_t *i2c) +{ + I2C_InitParam initParam = {0}; + HAL_Status status = HAL_ERROR; + I2C_ID id; + + if (i2c == NULL) { + return -1; + } + if (i2c->config.address_width == 7) { + initParam.addrMode = I2C_ADDR_MODE_7BIT; + } else if (i2c->config.address_width == 10) { + initParam.addrMode = I2C_ADDR_MODE_10BIT; + } else { + return -1; + } + + initParam.clockFreq = i2c->config.freq; + if (i2c->port == 0) { + id = I2C0_ID; + } else if (i2c->port == 1) { + id = I2C1_ID; + } else { + return -1; + } + + status = HAL_I2C_Init(id, &initParam); + if (status != HAL_OK) { + printf("IIC init error %d\n", status); + return -1; + } + return 0; +} + + +/**@brief i2c master send + * @param i2c : the i2c device + * @param dev_addr : device address + * @param data : i2c send data + * @param size : i2c send data size + * @param timeout : timeout in ms + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2c_master_send(i2c_dev_t *i2c, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout) +{ + HAL_Status status = HAL_ERROR; + I2C_ID id; + + if (i2c == NULL) { + return -1; + } + if (i2c->port == 0) { + id = I2C0_ID; + } else if (i2c->port == 1) { + id = I2C1_ID; + } else { + return -1; + } + status = HAL_I2C_Master_Transmit_IT(id, (uint16_t)dev_addr, data, (uint32_t)size); + if (status != HAL_OK) { + printf("hal_i2c_master_send error %d\n", status); + return -1; + } + return 0; +} + + +/**@brief i2c master recv + * + * @param i2c : the i2c device + * @param dev_addr : device address + * @param data : i2c receive data + * @param size : i2c receive data size + * @param timeout : timeout in ms + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2c_master_recv(i2c_dev_t *i2c, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout) +{ + HAL_Status status = HAL_ERROR; + I2C_ID id; + + if (i2c == NULL) { + return -1; + } + if (i2c->port == 0) { + id = I2C0_ID; + } else if (i2c->port == 1) { + id = I2C1_ID; + } else { + return -1; + } + status = HAL_I2C_Master_Receive_IT(id, (uint16_t)dev_addr, data, (uint32_t)size); + if (status != HAL_OK) { + printf("hal_i2c_master_recv error %d\n", status); + return -1; + } + return 0; +} + +/**@brief hal_i2C_slave_send + * + * @param i2c : the i2c device + * @param data : i2c slave send data + * @param size : i2c slave send data size + * @param timeout : timeout in ms + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2C_slave_send(i2c_dev_t *i2c, uint8_t *data, uint16_t size, uint32_t timeout) +{ + //TODO: + return -1; +} + + +/**@brief Initialises an I2C interface + * + * @param i2c : tthe i2c device + * @param data : i2c slave receive data + * @param size : i2c slave receive data size + * @param timeout : timeout in ms + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2c_slave_recv(i2c_dev_t *i2c, uint8_t *data, uint16_t size, uint32_t timeout) +{ + //TODO: + return -1; +} + + +/**@brief i2c mem write + * + * @param i2c : the i2c device + * @param dev_addr : device address + * @param mem_addr : mem address + * @param mem_addr_size : mem address + * @param data : i2c master send data + * @param size : i2c master send data size + * @param timeout : timeout in ms + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2c_mem_write(i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, + uint16_t size, uint32_t timeout) +{ + HAL_Status status = HAL_ERROR; + I2C_ID id; + + if (i2c == NULL) { + return -1; + } + if (i2c->port == 0) { + id = I2C0_ID; + } else if (i2c->port == 1) { + id = I2C1_ID; + } else { + return -1; + } + //FIXUP: mem addr from uint16_t to uint8_t + status = HAL_I2C_Master_Transmit_Mem_IT(id, dev_addr, (uint8_t)mem_addr & 0xff, data, (uint32_t)size); + if (status != HAL_OK) { + printf("hal_i2c_mem_write error %d\n", status); + return -1; + } + return 0; +} + +/**@brief i2c master mem read + * @param i2c : the i2c device + * @param dev_addr : device address + * @param mem_addr : mem address + * @param mem_addr_size : mem address + * @param data : i2c master send data + * @param size : i2c master send data size + * @param timeout : timeout in ms + * @return 0 : on success. + * @return EIO : if an error occurred during initialisation + */ +int32_t hal_i2c_mem_read(i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, + uint16_t size, uint32_t timeout) +{ + HAL_Status status = HAL_ERROR; + I2C_ID id; + + if (i2c == NULL) { + return -1; + } + if (i2c->port == 0) { + id = I2C0_ID; + } else if (i2c->port == 1) { + id = I2C1_ID; + } else { + return -1; + } + //FIXUP: mem addr from uint16_t to uint8_t + status = HAL_I2C_Master_Receive_Mem_IT(id, dev_addr, (uint8_t)mem_addr & 0xff, data, (uint32_t)size); + if (status != HAL_OK) { + printf("hal_i2c_mem_read error %d\n", status); + return -1; + } + return 0; +} + +/**@brief Deinitialises an I2C device + * + * @param device : the i2c device + * @return 0 : on success. + * @return EIO : if an error occurred during deinitialisation + */ +int32_t hal_i2c_finalize(i2c_dev_t *i2c) +{ + HAL_Status status = HAL_ERROR; + I2C_ID id; + + if (i2c == NULL) { + return -1; + } + if (i2c->port == 0) { + id = I2C0_ID; + } else if (i2c->port == 1) { + id = I2C1_ID; + } else { + return -1; + } + status = HAL_I2C_DeInit(id); + if (status != HAL_OK) { + printf("IIC deinit error %d\n", status); + return -1; + } + return 0; +} diff --git a/platform/mcu/xr871/aos/hal/soc/pwm.c b/platform/mcu/xr871/aos/hal/soc/pwm.c new file mode 100644 index 0000000000..4214a5d84d --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/pwm.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/** + * @file hal/soc/pwm.c + * @brief PWM HAL + * @version since 5.5.0 + */ + +#include "hal/soc/soc.h" +#include "driver/chip/hal_pwm.h" + +/**@brief Initialises a PWM pin + * + * @note Prepares a Pulse-Width Modulation pin for use. + * Does not start the PWM output (use @ref MicoPwmStart). + * + * @param pwm : the PWM device + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_pwm_init(pwm_dev_t *pwm) +{ + HAL_Status status = HAL_ERROR; + PWM_ClkParam clk_param = {0}; + PWM_ChInitParam ch_param = {0}; + int max_duty_ratio = 0; + + clk_param.clk = PWM_CLK_HOSC; + clk_param.div = PWM_SRC_CLK_DIV_1; + status = HAL_PWM_GroupClkCfg(pwm->port/2, &clk_param); + if (status != HAL_OK) + printf("[hal_pwm]: PWM ch %d clk config error\n", pwm->port); + + ch_param.hz = pwm->config.freq; + ch_param.mode = PWM_CYCLE_MODE; + ch_param.polarity = PWM_HIGHLEVE; + max_duty_ratio = HAL_PWM_ChInit(pwm->port, &ch_param); + if (max_duty_ratio == -1) + printf("[hal_pwm]: PWM ch %d init error\n", pwm->port); + + status = HAL_PWM_ChSetDutyRatio(pwm->port, pwm->config.duty_cycle); + if (status != HAL_OK) + printf("[hal_pwm]: PWM ch %d set duty ratio error\n", pwm->port); + + return 0; +} + + +/**@brief Starts PWM output on a PWM interface + * + * @note Starts Pulse-Width Modulation signal output on a PWM pin + * + * @param pwm : the PWM device + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_pwm_start(pwm_dev_t *pwm) +{ + HAL_Status status = HAL_ERROR; + status = HAL_PWM_EnableCh(pwm->port, PWM_CYCLE_MODE, 1); + if (status != HAL_OK) { + printf("[hal_pwm]: PWM ch %d start error\n", pwm->port); + return -1; + } + return 0; +} + + +/**@brief Stops output on a PWM pin + * + * @note Stops Pulse-Width Modulation signal output on a PWM pin + * + * @param pwm : the PWM device + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_pwm_stop(pwm_dev_t *pwm) +{ + HAL_PWM_ChDeinit(pwm->port); + return -1; +} + diff --git a/platform/mcu/xr871/aos/hal/soc/rtc.c b/platform/mcu/xr871/aos/hal/soc/rtc.c new file mode 100644 index 0000000000..76c9c6b391 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/rtc.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal/soc/soc.h" +#include "mico_rtos.h" +#include "driver/chip/hal_rtc.h" + +#define RTC_START_YEAR (1970) +/**@brief This function will initialize the on board CPU real time clock + * + * @note This function should be called by MICO system when initializing clocks, so + * It is not needed to be called by application + * @param rtc : rtc device + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_rtc_init(rtc_dev_t *rtc) +{ + +} + +/**@brief This function will return the value of time read from the on board CPU real time clock. Time value must be given in the format of + * the structure hal_rtc_time_t + * @param rtc : rtc device + * @param time : pointer to a time structure + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_rtc_get_time(rtc_dev_t *rtc, rtc_time_t *time) +{ + if (time != NULL) { + uint8_t isLeapYear, year, month, mday; + RTC_WeekDay wday; + uint8_t hour, minute, second; + + HAL_RTC_GetYYMMDD(&isLeapYear, &year, &month, &mday); + HAL_RTC_GetDDHHMMSS(&wday, &hour, &minute, &second); + + time->year = year; + time->month = month; + time->date = mday; + time->hr = hour; + time->min = minute; + time->sec = second; + printf("[hal_rtc]: get time %d-%d-%d, %d:%d:%d\n", + year, month, mday, hour, minute, second); + return 0; + } else + return -1; +} + +/**@brief This function will set MCU RTC time to a new value. Time value must be given in the format of + * the structure hal_rtc_time_t + * @param rtc : rtc device + * @param time : pointer to a time structure + * + * @return 0 : on success. + * @return EIO : if an error occurred with any step + */ +int32_t hal_rtc_set_time(rtc_dev_t *rtc, const rtc_time_t *time) +{ + if (time != NULL) { + uint8_t isLeapYear = !(time->year % 400) || (!(time->year % 4) && (time->year % 100)); + HAL_RTC_SetYYMMDD(isLeapYear, time->year, time->month, time->date); + HAL_RTC_SetDDHHMMSS(RTC_WDAY_TUESDAY, time->hr, time->min, time->sec); // Fixup: weakday + printf("[hal_rtc]: set time %d-%d-%d, %d:%d:%d\n", + time->year + RTC_START_YEAR, time->month, time->date, + time->hr, time->min, time->sec); + } else + return -1; +} + diff --git a/platform/mcu/xr871/aos/hal/soc/sd.c b/platform/mcu/xr871/aos/hal/soc/sd.c new file mode 100644 index 0000000000..23445757e3 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/sd.c @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "hal/soc/soc.h" +#include "hal/soc/sd.h" +#include "driver/chip/hal_def.h" +#include "driver/chip/sdmmc/hal_sdhost.h" +#include "driver/chip/sdmmc/sdmmc.h" + +static struct mmc_card card; +static hal_sd_info_t sd_info; +static int sd_initialize = 0; + +/**@brief Initialises a sd interface +* +* @param sd : the interface which should be initialised +* @param config : sd configuration structure +* +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_init(sd_dev_t *sd) +{ + int32_t ret; + SDC_InitTypeDef sdc_param = {0}; + + if (!sd_initialize) { + memset(&card, 0, sizeof(struct mmc_card)); + memset(&sd_info, 0, sizeof(hal_sd_info_t)); + + sd->port = 0; + HAL_SDC_Init(sd->port, &sdc_param); + + ret = mmc_rescan(&card, sd->port); + if (ret != 0) { + printf("[hal_sd]: init sd failed\n"); + return -1; + } + sd_initialize = 1; + } + + sd->config.bus_wide = card.bus_width; + if (card.state & MMC_STATE_HIGHSPEED) + sd->config.freq = 50000000; + else + sd->config.freq = 25000000; + sd->priv = (void*)&card; + sd_info.blk_size = 512; + sd_info.blk_nums = card.csd.capacity/512; + + return 0; +} + + +/**@brief read sd blocks +* +* @param sd : the interface which should be initialised +* @param data : pointer to the buffer which will store incoming data +* @param blk_addr : sd blk addr +* @param blks : sd blks +* @param timeout : timeout in milisecond +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_blks_read(sd_dev_t *sd, uint8_t *data, uint32_t blk_addr, uint32_t blks, uint32_t timeout) +{ + int32_t ret; + ret = mmc_block_read(sd->priv, data, blk_addr, blks); + + return ret; +} + +/**@brief write sd blocks +* +* @param sd : the interface which should be initialised +* @param data : pointer to the buffer which will store incoming data +* @param blk_addr : sd blk addr +* @param blks : sd blks +* @param timeout : timeout in milisecond +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_blks_write(sd_dev_t *sd, uint8_t *data, uint32_t blk_addr, uint32_t blks, uint32_t timeout) +{ + int32_t ret; + ret = mmc_block_write(sd->priv, data, blk_addr, blks); + + return ret; +} + +/**@brief erase sd blocks +* +* @param sd : the interface which should be initialised +* @param blk_start_addr : sd blocks start addr +* @param blk_end_addr : sd blocks end addr +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_erase(sd_dev_t *sd, uint32_t blk_start_addr, uint32_t blk_end_addr) +{ + //TODO: + return 0; +} + +/**@brief get sd state +* +* @param sd : the interface which should be initialised +* @param stat : pointer to the buffer which will store incoming data +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_stat_get(sd_dev_t *sd, hal_sd_stat *stat) +{ + *stat = SD_STAT_TRANSFER; + return 0; +} + +/**@brief get sd info +* +* @param sd : the interface which should be initialised +* @param stat : pointer to the buffer which will store incoming data +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_info_get(sd_dev_t *sd, hal_sd_info_t *info) +{ + info->blk_size = sd_info.blk_size; + info->blk_nums = sd_info.blk_nums; + return 0; +} + +/**@brief Deinitialises a sd interface +* +* @param sd : the interface which should be initialised +* @return 0 : on success. +* @return EIO : if an error occurred with any step +*/ +int32_t hal_sd_finalize(sd_dev_t *sd) +{ + sd_initialize = 0; + if (!card.host) + return 0; + + mmc_card_deinit(&card); + HAL_SDC_Deinit(0); + return 0; +} diff --git a/platform/mcu/xr871/aos/hal/soc/timer.c b/platform/mcu/xr871/aos/hal/soc/timer.c new file mode 100644 index 0000000000..240362afc4 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/timer.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "driver/chip/hal_timer.h" + +/** + * @brief init a hardware timer + * @param tmr timer struct + * @param period micro seconds for repeat timer trigger + * @param auto_reoad set to 0, if you just need oneshot timer + * @param cb callback to be triggered after useconds + * @ch timer channel + * @param arg passed to cb + * @note period auto auto auto + * *-------|--------|--------|--------| + */ +int32_t hal_timer_init(timer_dev_t *tmr) +{ + HAL_Status status = HAL_ERROR; + TIMER_InitParam param = {0}; + TIMER_ID timer_id; + + if (tmr->port == TIMER0_ID) { + timer_id = TIMER0_ID; + } else if (tmr->port == TIMER0_ID) { + timer_id = TIMER1_ID; + } else { + printf("[timer]: init error, wrong port %d\n", tmr->port); + return; + } + param.arg = tmr->config.arg; + param.callback = tmr->config.cb; + param.cfg = HAL_TIMER_MakeInitCfg(TIMER_MODE_REPEAT, + TIMER_CLK_SRC_HFCLK, TIMER_CLK_PRESCALER_4); + param.isEnableIRQ = 1; + param.period = 6000 * tmr->config.period; //each cycle is 6us + + status = HAL_TIMER_Init(timer_id, ¶m); + if (status != HAL_OK) { + printf("timer int error %d\n", status); + } +} + +/** + * @brief init a hardware timer + * @param None + * @retval 0 == success + * EIO == failure + */ +int32_t hal_timer_start(timer_dev_t *tmr) +{ + HAL_TIMER_Start(tmr->port); + return 0; +} + +/** + * @brief stop a hardware timer + * @param tmr timer struct + * @param cb callback to be triggered after useconds + * @param arg passed to cb + */ +void hal_timer_stop(timer_dev_t *tmr) +{ + HAL_TIMER_Stop(tmr->port); +} diff --git a/platform/mcu/xr871/aos/hal/soc/uart.c b/platform/mcu/xr871/aos/hal/soc/uart.c new file mode 100644 index 0000000000..1ee38b7ef0 --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/uart.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal/soc/soc.h" +#include "aos/kernel.h" +#include "driver/chip/hal_chip.h" +#include "board_config.h" + +#define MAX_UART_NUM 2 +#define UART_FIFO_SIZE 64 + +enum _uart_status_e +{ + _UART_STATUS_CLOSED = 0, + _UART_STATUS_OPENED, +}; + +typedef struct +{ + uint8_t uart; + uint8_t status; + aos_mutex_t tx_mutex; + kbuf_queue_t *bufque; +} _uart_drv_t; + +static _uart_drv_t _uart_drv[MAX_UART_NUM]; + +static void uart_rx_callback(void* arg) +{ + uint8_t rx_byte; + uart_dev_t* uart = (uart_dev_t*)arg; + _uart_drv_t *pdrv = &_uart_drv[uart->port]; + UART_T *uart_i = HAL_UART_GetInstance(uart->port); + uint32_t rx_cnt = HAL_UART_GetRxFIFOLevel(uart_i); + + while (rx_cnt --) { + rx_byte = HAL_UART_GetRxData(uart_i); + krhino_buf_queue_send(pdrv->bufque, &rx_byte, 1); + } +} + +int32_t hal_uart_init(uart_dev_t *uart) +{ + int32_t ret = -1; + _uart_drv_t *pdrv = &_uart_drv[uart->port]; + + printf("%s: Humble test enter, port = %d\n", __func__, uart->port); + if (uart != NULL) { + _uart_drv_t *pdrv = &_uart_drv[uart->port]; + UART_InitParam board_uart_param = { + .baudRate = 115200, + .parity = UART_PARITY_NONE, + .stopBits = UART_STOP_BITS_1, + .dataBits = UART_DATA_BITS_8, + .isAutoHwFlowCtrl = 0 + }; + + if (pdrv->status == _UART_STATUS_CLOSED) { + // convert uart parameters + board_uart_param.baudRate = uart->config.baud_rate; + if (uart->config.parity == ODD_PARITY) { + board_uart_param.parity = UART_PARITY_ODD; + } else if (uart->config.parity == EVEN_PARITY) { + board_uart_param.parity = UART_PARITY_EVEN; + } + if (uart->config.stop_bits == STOP_BITS_2) { + board_uart_param.stopBits = UART_STOP_BITS_2; + } + switch (uart->config.data_width) { + case DATA_WIDTH_5BIT: + board_uart_param.dataBits = UART_DATA_BITS_5; + break; + case DATA_WIDTH_6BIT: + board_uart_param.dataBits = UART_DATA_BITS_6; + break; + case DATA_WIDTH_7BIT: + board_uart_param.dataBits = UART_DATA_BITS_7; + break; + case DATA_WIDTH_8BIT: + board_uart_param.dataBits = UART_DATA_BITS_8; + break; + default: + board_uart_param.dataBits = UART_DATA_BITS_8; + break; + } + if (uart->config.flow_control != FLOW_CONTROL_DISABLED) + board_uart_param.isAutoHwFlowCtrl = 1; + + ret = HAL_UART_Init(uart->port, &board_uart_param); + if (ret == 0) { + kstat_t stat; + // create tx mutex + stat = krhino_buf_queue_dyn_create(&pdrv->bufque, "cli", UART_FIFO_SIZE , 1); + if(stat != RHINO_SUCCESS) { + HAL_UART_DeInit(uart->port); + return stat; + } + aos_mutex_new(&pdrv->tx_mutex); + HAL_UART_EnableRxCallback(uart->port, uart_rx_callback, uart); + pdrv->status = _UART_STATUS_OPENED; + } + } + } + + printf("%s: exit\n", __func__); + return ret; +} + +int32_t hal_uart_finalize(uart_dev_t *uart) +{ + int32_t ret = -1; + _uart_drv_t *pdrv = &_uart_drv[uart->port]; + + printf("%s: enter, port = %d\n", __func__, uart->port); + if (pdrv->status == _UART_STATUS_OPENED) { + aos_mutex_free(&pdrv->tx_mutex); + krhino_buf_queue_dyn_del(pdrv->bufque); + ret = HAL_UART_DeInit(uart->port); + pdrv->status = _UART_STATUS_CLOSED; + } + + printf("%s: exit\n", __func__); + return ret; +} + +int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout) +{ + int32_t ret = -1; + _uart_drv_t *pdrv = &_uart_drv[uart->port]; + + if (pdrv->status == _UART_STATUS_OPENED) { + aos_mutex_lock(&pdrv->tx_mutex, timeout); + ret = HAL_UART_Transmit_Poll(uart->port, data, size); + aos_mutex_unlock(&pdrv->tx_mutex); + } + return ret; +} + +int32_t hal_uart_recv(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t *recv_size, uint32_t timeout) +{ + kstat_t ret = -1; + _uart_drv_t *pdrv = &_uart_drv[uart->port]; + + if (pdrv->status == _UART_STATUS_OPENED) { + uint32_t readlen = 0; + uint32_t totallen = 0; + while (1) { + ret = krhino_buf_queue_recv(pdrv->bufque, timeout, data, &readlen); + if (ret != RHINO_SUCCESS) { + if (recv_size) { + *recv_size = totallen; + } + return -1; + } + if (readlen == 0) { + break; + } + totallen += readlen; + data += readlen; + if (totallen >= expect_size) { + break; + } + } + if (recv_size) { + *recv_size = totallen; + } + } + + return 0; +} diff --git a/platform/mcu/xr871/aos/hal/soc/wdg.c b/platform/mcu/xr871/aos/hal/soc/wdg.c new file mode 100644 index 0000000000..b78b43bd8e --- /dev/null +++ b/platform/mcu/xr871/aos/hal/soc/wdg.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal/soc/soc.h" +#include "driver/chip/hal_wdg.h" + +int32_t hal_wdg_init(wdg_dev_t *wdg) +{ + + WDG_InitParam param; + WDG_Timeout timeout_tbl[]={WDG_TIMEOUT_500MS,WDG_TIMEOUT_1SEC,WDG_TIMEOUT_2SEC,WDG_TIMEOUT_3SEC, + WDG_TIMEOUT_4SEC,WDG_TIMEOUT_5SEC,WDG_TIMEOUT_6SEC,WDG_TIMEOUT_6SEC, + WDG_TIMEOUT_8SEC,WDG_TIMEOUT_8SEC,WDG_TIMEOUT_10SEC,WDG_TIMEOUT_10SEC, + WDG_TIMEOUT_12SEC,WDG_TIMEOUT_12SEC,WDG_TIMEOUT_14SEC,WDG_TIMEOUT_14SEC, + WDG_TIMEOUT_16SEC}; + int32_t tbl_size; + + + tbl_size = sizeof(timeout_tbl)/sizeof(timeout_tbl[0]); + int pos = wdg->config.timeout > 500 ? (wdg->config.timeout/1000) : 0; + if (pos < tbl_size) { + param.timeout = timeout_tbl[pos]; + } + else { + param.timeout = timeout_tbl[tbl_size-1]; + } + printf("*********hal_wdg_init timeout:%d",param.timeout); + param.event = WDG_EVT_RESET; + + HAL_WDG_Init(¶m); + HAL_WDG_Start(); + + return 0; +} + +void hal_wdg_reload(wdg_dev_t *wdg) +{ + HAL_WDG_Feed(); +} + +int32_t hal_wdg_finalize(wdg_dev_t *wdg) +{ + HAL_WDG_Stop(); + + HAL_WDG_DeInit(); + + return 0; +} diff --git a/platform/mcu/xr871/aos/hal/wifi.c b/platform/mcu/xr871/aos/hal/wifi.c new file mode 100644 index 0000000000..40e7aeba7e --- /dev/null +++ b/platform/mcu/xr871/aos/hal/wifi.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "common.h" +#include "wifi_port.h" + + +static int wifi_init(hal_wifi_module_t *m) +{ + return xr871_wlan_init(); +} + +static void wifi_get_mac_addr(hal_wifi_module_t *m, uint8_t *mac) +{ + xr871_wlan_get_mac_addr(mac); +} + +static int wifi_start(hal_wifi_module_t *m, hal_wifi_init_type_t *init_para) +{ + int ret; + + ret = xr871_wlan_start(init_para); + + return ret; +} + +static int wifi_start_adv(hal_wifi_module_t *m, hal_wifi_init_type_adv_t *init_para_adv) +{ + int ret; + + ret = xr871_wlan_start_adv(init_para_adv); + + return ret; +} + +static int get_ip_stat(hal_wifi_module_t *m, hal_wifi_ip_stat_t *out_net_para, hal_wifi_type_t wifi_type) +{ + int ret; + + ret = xr871_wlan_get_ip_stat(out_net_para, wifi_type); + + return ret; +} + +static int get_link_stat(hal_wifi_module_t *m, hal_wifi_link_stat_t *out_stat) +{ + int ret; + + ret = xr871_wlan_get_link_stat(out_stat); + + return ret; +} + +static void start_scan(hal_wifi_module_t *m) +{ + xr871_wlan_start_scan(); +} + +static void start_scan_adv(hal_wifi_module_t *m) +{ + xr871_wlan_start_adv_scan(); +} + +static int power_off(hal_wifi_module_t *m) +{ + return xr871_wlan_power_off(); +} + +static int power_on(hal_wifi_module_t *m) +{ + return xr871_wlan_power_on(); +} + +static int suspend(hal_wifi_module_t *m) +{ + return xr871_wlan_suspend(); +} + +static int suspend_station(hal_wifi_module_t *m) +{ + return xr871_wlan_suspend_station(); +} + +static int suspend_soft_ap(hal_wifi_module_t *m) +{ + return xr871_wlan_suspend_softap(); +} + +static int set_channel(hal_wifi_module_t *m, int ch) +{ + return xr871_wlan_set_channel(ch); +} + +static void start_monitor(hal_wifi_module_t *m) +{ + xr871_wlan_start_monitor(); +} + +static void stop_monitor(hal_wifi_module_t *m) +{ + xr871_wlan_stop_monitor(); +} + +static void register_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn) +{ + xr871_wlan_register_monitor_cb(fn); +} + +static void register_wlan_mgnt_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn) +{ + xr871_wlan_register_mgnt_monitor_cb(fn); +} + +static int wlan_send_80211_raw_frame(hal_wifi_module_t *m, uint8_t *buf, int len) +{ + return xr871_wlan_send_80211_raw_frame(buf, len - 4); // len-4=exclude FCS +} + +static void start_debug_mode(hal_wifi_module_t *m) +{ + xr871_wlan_start_debug_mode(); +} + +static void stop_debug_mode(hal_wifi_module_t *m) +{ + xr871_wlan_stop_debug_mode(); +} + +hal_wifi_module_t sim_aos_wifi_xr871 = { + .base.name = "sim_aos_wifi_xr871", + .init = wifi_init, + .get_mac_addr = wifi_get_mac_addr, + .start = wifi_start, + .start_adv = wifi_start_adv, + .get_ip_stat = get_ip_stat, + .get_link_stat = get_link_stat, + .start_scan = start_scan, + .start_scan_adv = start_scan_adv, + .power_off = power_off, + .power_on = power_on, + .suspend = suspend, + .suspend_station = suspend_station, + .suspend_soft_ap = suspend_soft_ap, + .set_channel = set_channel, + .start_monitor = start_monitor, + .stop_monitor = stop_monitor, + .register_monitor_cb = register_monitor_cb, + .register_wlan_mgnt_monitor_cb = register_wlan_mgnt_monitor_cb, + .wlan_send_80211_raw_frame = wlan_send_80211_raw_frame, + .start_debug_mode = start_debug_mode, + .stop_debug_mode = stop_debug_mode +}; + diff --git a/platform/mcu/xr871/aos/hal/wifi_port.c b/platform/mcu/xr871/aos/hal/wifi_port.c new file mode 100644 index 0000000000..125a68356b --- /dev/null +++ b/platform/mcu/xr871/aos/hal/wifi_port.c @@ -0,0 +1,584 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "net/wlan/wlan.h" +#include "net_ctrl.h" +#include "wifi_port.h" +#include "sysinfo.h" +#include "kernel/os/os.h" +#include "common/framework/sys_ctrl/sys_ctrl.h" + +#define WIFI_DEBUG(...) do { \ + printf("[wifi_port]: "); \ + printf(__VA_ARGS__); \ + } while (0) + +#define MAX_SCAN_RESULTS 10 + +extern struct netif *g_wlan_netif; + +static wlan_monitor_rx_cb g_monitor_cb; +static int g_network_up = 0; + +static enum scan_type { + SCAN_TYPE_NORMAL, + SCAN_TYPE_ADVANCE +} g_scan_type = SCAN_TYPE_NORMAL; + +void xr871_wlan_msg_process(uint32_t event, uint32_t data) +{ + struct netif *nif = g_wlan_netif; + uint16_t type = EVENT_SUBTYPE(event); + + WIFI_DEBUG("%s msg (%u, %u)\n", __func__, type, data); + switch (type) { + case NET_CTRL_MSG_WLAN_CONNECTED: + break; + case NET_CTRL_MSG_WLAN_SCAN_SUCCESS: + if (g_scan_type == SCAN_TYPE_NORMAL) + xr871_scan_compeleted_event(); + if (g_scan_type == SCAN_TYPE_ADVANCE) + xr871_scan_adv_compeleted_event(); + break; + case NET_CTRL_MSG_WLAN_CONNECT_FAILED: + xr871_connect_fail_event(); + break; + case NET_CTRL_MSG_NETWORK_UP: + if (wlan_if_get_mode(nif) == WLAN_MODE_STA) { + xr871_ip_got_event(); + } + g_network_up = 1; + xr871_stat_chg_event(); + break; + case NET_CTRL_MSG_NETWORK_DOWN: + g_network_up = 0; + xr871_stat_chg_event(); + break; + case NET_CTRL_MSG_WLAN_DISCONNECTED: + case NET_CTRL_MSG_WLAN_SCAN_FAILED: + case NET_CTRL_MSG_WLAN_4WAY_HANDSHAKE_FAILED: + WIFI_DEBUG("do nothing msg (%u, %u)\n", type, data); + break; + default: + WIFI_DEBUG("unknown msg (%u, %u)\n", type, data); + break; + } +} + +int xr871_wlan_init(void) +{ + // create network event listener + observer_base *ob; + + WIFI_DEBUG("wlan init, register network observer\n"); + ob = sys_callback_observer_create(CTRL_MSG_TYPE_NETWORK, + NET_CTRL_MSG_ALL, + xr871_wlan_msg_process); + if (ob == NULL) + return -1; + if (sys_ctrl_attach(ob) != 0) + return -1; + + WIFI_DEBUG("xr871 wifi init success!!\n"); + return 0; +} + +void xr871_wlan_get_mac_addr(uint8_t *mac) +{ + struct sysinfo *info = sysinfo_get();; + + WIFI_DEBUG("wlan get mac address\n"); + memcpy(mac, info->mac_addr, 6); + WIFI_DEBUG("MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); +} + +int xr871_wlan_start(hal_wifi_init_type_t *init_para) +{ + int ret = 0; + int ssid_len = strlen(init_para->wifi_ssid); + int psk_len = strlen(init_para->wifi_key); + + WIFI_DEBUG("wlan start, mode %d\n", init_para->wifi_mode); + + if (ssid_len > 32) + ssid_len = 32; + switch (init_para->wifi_mode) { + case STATION: /* STA */ + WIFI_DEBUG("station start, ssid %s, key %s\n", + init_para->wifi_ssid, init_para->wifi_key); + net_switch_mode(WLAN_MODE_STA); + wlan_sta_disable(); + if (psk_len > 0) { + wlan_sta_set(init_para->wifi_ssid, ssid_len, init_para->wifi_key); + } + else { + wlan_sta_set(init_para->wifi_ssid, ssid_len, NULL); + } + wlan_sta_enable(); + break; + + case SOFT_AP: /* AP */ + WIFI_DEBUG("hostap start, ssid %s, key %s\n", + init_para->wifi_ssid, init_para->wifi_key); + net_switch_mode(WLAN_MODE_HOSTAP); + wlan_ap_disable(); + wlan_ap_set(init_para->wifi_ssid, ssid_len, init_para->wifi_key); + wlan_ap_enable(); + break; + + default: + WIFI_DEBUG("error wifi mode\n"); + break; + } + + return ret; +} + +int xr871_wlan_start_adv(hal_wifi_init_type_adv_t *init_para_adv) +{ + int ssid_len = strlen(init_para_adv->ap_info.ssid); + int psk_len = strlen(init_para_adv->key); + WIFI_DEBUG("wlan start advance\n"); + if (ssid_len > 32) + ssid_len = 32; + net_switch_mode(WLAN_MODE_STA); + wlan_sta_disable(); + if (psk_len > 0) { + wlan_sta_set(init_para_adv->ap_info.ssid, ssid_len, init_para_adv->key); + } + else { + wlan_sta_set(init_para_adv->ap_info.ssid, ssid_len, NULL); + } + wlan_sta_enable(); + + return 0; +} + +int xr871_wlan_get_ip_stat(hal_wifi_ip_stat_t *out_net_para, + hal_wifi_type_t wifi_type) +{ + struct netif *nif = g_wlan_netif; + + if (nif == NULL || out_net_para == NULL) { + return -1; + } + + xr871_wlan_get_mac_addr(out_net_para->mac); /* mac */ + if (netif_is_up(nif) && netif_is_link_up(nif)) { + inet_ntoa_r(nif->ip_addr, out_net_para->ip, sizeof(out_net_para->ip)); /* ip */ + inet_ntoa_r(nif->gw, out_net_para->gate, sizeof(out_net_para->gate)); /* gate */ + inet_ntoa_r(nif->netmask, out_net_para->mask, sizeof(out_net_para->mask)); /* mask */ + WIFI_DEBUG("%c%c%d up, address:%s gateway:%s netmask:%s", + nif->name[0], nif->name[1], nif->num, + out_net_para->ip, out_net_para->gate, out_net_para->mask); + } else { + WIFI_DEBUG("%c%c%d down", nif->name[0], nif->name[1], nif->num); + return -1; + } + + /* dhcp */ + /* dns */ + /* broadcastip */ + if (wifi_type == STATION) { + + } else if (wifi_type == SOFT_AP) { + + } + + return 0; +} + +int xr871_wlan_get_link_stat(hal_wifi_link_stat_t *out_stat) +{ + wlan_sta_states_t state; + wlan_sta_ap_t ap; + + WIFI_DEBUG("wlan get link stat\n"); + if (out_stat == NULL) { + return -1; + } + memset(out_stat, 0, sizeof(hal_wifi_link_stat_t)); + + /* is_connected */ + wlan_sta_state(&state); + if (state == WLAN_STA_STATE_CONNECTED) { + wlan_sta_ap_info(&ap); + out_stat->is_connected = 1; + out_stat->wifi_strength = ap.rssi; + out_stat->channel = ap.channel; + memcpy(out_stat->ssid, ap.ssid.ssid, sizeof(ap.ssid.ssid_len)); + memcpy(out_stat->bssid, ap.bssid, sizeof(out_stat->bssid)); + + WIFI_DEBUG("======= link state =======\n"); + WIFI_DEBUG("connect :\n", out_stat->is_connected); + WIFI_DEBUG("strength :\n", out_stat->wifi_strength); + WIFI_DEBUG("ssid :%-32.32s\n", out_stat->ssid); + WIFI_DEBUG("bssid %02x:%02x:%02x:%02x:%02x:%02x\n", + out_stat->bssid[0], out_stat->bssid[1], out_stat->bssid[2], + out_stat->bssid[3], out_stat->bssid[4], out_stat->bssid[5]); + WIFI_DEBUG("channel :%d\n", out_stat->channel); + + } else { + WIFI_DEBUG("Request link state in HostAP mode ???\n"); + out_stat->is_connected = 0; + } + + return 0; +} + +void xr871_wlan_start_scan(void) +{ + WIFI_DEBUG("wlan start normal scan\n"); + g_scan_type = SCAN_TYPE_NORMAL; + + wlan_sta_scan_once(); +} + +void xr871_wlan_start_adv_scan(void) +{ + WIFI_DEBUG("wlan start advance scan\n"); + g_scan_type = SCAN_TYPE_ADVANCE; + + wlan_sta_scan_once(); +} + +int xr871_wlan_power_off(void) +{ + WIFI_DEBUG("wlan power off\n"); + net_sys_stop(); + return 0; +} + +int xr871_wlan_power_on(void) +{ + WIFI_DEBUG("wlan power on\n"); + net_sys_start(WLAN_MODE_STA); + return 0; +} + +int xr871_wlan_suspend(void) +{ + struct netif *nif = g_wlan_netif; + + WIFI_DEBUG("wlan suspend\n"); + if (nif != NULL) { + enum wlan_mode mode = wlan_if_get_mode(nif); + if (mode == WLAN_MODE_HOSTAP) { + wlan_ap_disable(); + } + if (mode == WLAN_MODE_STA) { + wlan_sta_disable(); + } + if (mode == WLAN_MODE_MONITOR) { + } + } + return 0; +} + +int xr871_wlan_suspend_station(void) +{ + WIFI_DEBUG("wlan station suspend\n"); + wlan_sta_disable(); + return 0; +} + +int xr871_wlan_suspend_softap(void) +{ + WIFI_DEBUG("wlan softap suspend\n"); + wlan_ap_disable(); + return 0; +} + +int xr871_wlan_set_channel(int ch) +{ + struct netif *nif = g_wlan_netif; + + WIFI_DEBUG("wlan set monitor channel %d\n", ch); + return wlan_monitor_set_channel(nif, ch); +} + +void xr871_wlan_start_monitor(void) +{ + struct netif *nif = g_wlan_netif; + + WIFI_DEBUG("wlan start monitor mode, nif %p, cb %p\n", nif, g_monitor_cb); + + if (nif) { + wlan_monitor_set_rx_cb(nif, g_monitor_cb); + net_switch_mode(WLAN_MODE_MONITOR); + } +} + +void xr871_wlan_stop_monitor(void) +{ + struct netif *nif = g_wlan_netif; + + WIFI_DEBUG("wlan stop monitor mode\n"); + if (nif) { + wlan_monitor_set_rx_cb(nif, NULL); + } +} + +void xr871_wlan_register_monitor_cb(monitor_data_cb_t fn) +{ + WIFI_DEBUG("wlan register monitor callback: %p\n", fn); + g_monitor_cb = (wlan_monitor_rx_cb)fn; +} + +void xr871_wlan_register_mgnt_monitor_cb(monitor_data_cb_t fn) +{ + WIFI_DEBUG("wlan register manage monitor callback: %p\n", fn); + g_monitor_cb = (wlan_monitor_rx_cb)fn; +} + +int xr871_wlan_send_80211_raw_frame(uint8_t *buf, int len) +{ + WIFI_DEBUG("send raw frame(not support now)\n"); + + // dump raw frame data + if (0) + { + uint32_t i = 0; + printf("dump frame data:\n"); + for (i = 0; i < len; i++) { + printf("%02x ", buf[i]); + if ((i % 32) == 31) + printf("\n"); + } + printf("\n"); + } + return 0; +} + +void xr871_wlan_start_debug_mode(void) +{ + WIFI_DEBUG("start wifi debug mode\n"); +} + +void xr871_wlan_stop_debug_mode(void) +{ + WIFI_DEBUG("stop wifi debug mode\n"); +} + +void xr871_connect_fail_event(int err, void *arg) +{ + hal_wifi_module_t *m = hal_wifi_get_default_module(); + + WIFI_DEBUG("handle connect fail event\n"); + + if (m != NULL && m->ev_cb != NULL && m->ev_cb->connect_fail != NULL) { + m->ev_cb->connect_fail(m, err, arg); + } +} + +void xr871_ip_got_event(void) +{ + hal_wifi_module_t *m = hal_wifi_get_default_module(); + + WIFI_DEBUG("handle ip got event\n"); + if (m != NULL && m->ev_cb != NULL && m->ev_cb->ip_got != NULL) { + hal_wifi_ip_stat_t net = {0}; + xr871_wlan_get_ip_stat(&net, STATION); + m->ev_cb->ip_got(m, &net, NULL); + } +} + +void xr871_stat_chg_event(void) +{ + hal_wifi_module_t *m = hal_wifi_get_default_module(); + struct netif *nif = g_wlan_netif; + + WIFI_DEBUG("handle state change event\n"); + + if (nif != NULL && m != NULL && m->ev_cb != NULL && m->ev_cb->stat_chg != NULL) { + hal_wifi_event_t stat; + enum wlan_mode mode = wlan_if_get_mode(nif); + if (mode == WLAN_MODE_STA) { + stat = netif_is_link_up(nif) ? NOTIFY_STATION_UP : NOTIFY_STATION_DOWN; + } else if (mode == WLAN_MODE_HOSTAP) { + stat = netif_is_link_up(nif) ? NOTIFY_AP_UP : NOTIFY_AP_DOWN; + } + m->ev_cb->stat_chg(m, stat, NULL); + } +} + +static const uint32_t channel_freq_tbl[] = { + 2412, 2417, 2422, 2427, 2432, 2437, 2442, 2447, 2452, 2457, 2462, 2467, 2472 +}; + +static int32_t freq_to_chan(int32_t freq) +{ + int32_t i; + uint32_t chs = sizeof(channel_freq_tbl)/sizeof(channel_freq_tbl[0]); + + for (i = 0; i < chs && freq != channel_freq_tbl[i]; i++); + if(i == chs) { + return -1; + } + + return i + 1; +} + +static char rssi_to_ap_power(int32_t rssi) +{ + char ap_power = rssi * 100L / 128; + + if (ap_power > 100) { + ap_power = 100; + } + + return ap_power; +} + +void xr871_scan_compeleted_event(enum scan_type type) +{ + hal_wifi_module_t *m = hal_wifi_get_default_module(); + hal_wifi_scan_result_t result = {0}; + wlan_sta_scan_results_t scan_results = {0}; + int ret; + + scan_results.ap = malloc(MAX_SCAN_RESULTS * sizeof(wlan_sta_ap_t)); + if (scan_results.ap != NULL) { + scan_results.size = MAX_SCAN_RESULTS; + ret = wlan_sta_scan_result(&scan_results); + if (ret == 0) { + result.ap_num = scan_results.num; + result.ap_list = malloc(result.ap_num * sizeof(*(result.ap_list))); + + WIFI_DEBUG("scan result: ap_num: %d, ap %p, ap_list %p\n", result.ap_num, + scan_results.ap, result.ap_list); + + if (result.ap_list != NULL) { + int i; + + for (i = 0; i < scan_results.num; i++) { + memset(result.ap_list[i].ssid, 0, sizeof(result.ap_list[i].ssid)); + memcpy(result.ap_list[i].ssid, scan_results.ap[i].ssid.ssid, + scan_results.ap[i].ssid.ssid_len); + result.ap_list[i].ap_power = rssi_to_ap_power(scan_results.ap[i].rssi); + + WIFI_DEBUG("#%-2d: ssid: %-32.32s ap_power: %d\n", i+1, + result.ap_list[i].ssid, result.ap_list[i].ap_power); + } + + if (m->ev_cb != NULL && m->ev_cb->scan_compeleted != NULL) { + m->ev_cb->scan_compeleted(m, &result, NULL); + } + + free(result.ap_list); + } + } + + free(scan_results.ap); + } +} + +void xr871_scan_adv_compeleted_event(enum scan_type type) +{ + hal_wifi_module_t *m = hal_wifi_get_default_module(); + hal_wifi_scan_result_adv_t result = {0}; + wlan_sta_scan_results_t scan_results = {0}; + wlan_sta_config_t config = {0}; + int kmgt, cipher; + int ret; + + scan_results.ap = malloc(MAX_SCAN_RESULTS * sizeof(wlan_sta_ap_t)); + if (scan_results.ap != NULL) { + scan_results.size = MAX_SCAN_RESULTS; + ret = wlan_sta_scan_result(&scan_results); + if (ret == 0) { + result.ap_num = scan_results.num; + result.ap_list = malloc(result.ap_num * sizeof(*(result.ap_list))); + + WIFI_DEBUG("scan result: ap_num: %d\n", result.ap_num); + + if (result.ap_list != NULL) { + int i; + + for (i = 0; i < scan_results.num; i++) { + result.ap_list[i].ap_power = rssi_to_ap_power(scan_results.ap[i].rssi); + result.ap_list[i].channel = freq_to_chan(scan_results.ap[i].freq); + memset(result.ap_list[i].ssid, 0, sizeof(result.ap_list[i].ssid)); + memcpy(result.ap_list[i].ssid, scan_results.ap[i].ssid.ssid, + scan_results.ap[i].ssid.ssid_len); + memcpy(result.ap_list[i].bssid, scan_results.ap[i].bssid, + sizeof(result.ap_list[i].bssid)); + + config.field = WLAN_STA_FIELD_KEY_MGMT; + if (wlan_sta_get_config(&config) != 0) { + WIFI_DEBUG("***error, get config failed\n"); + } + if (config.u.key_mgmt = WPA_KEY_MGMT_NONE) { + result.ap_list[i].security = SECURITY_TYPE_NONE; + } else { + // Fixup: + WIFI_DEBUG("***warning, temp security impl\n"); + result.ap_list[i].security = SECURITY_TYPE_WPA2_MIXED; + } + + WIFI_DEBUG("#%-2d: ssid: %-32.32s ap_power: %d, ch %d, security %d " + "bssid: %02x:%02x:%02x:%02x:%02x:%02x", + i+1, + result.ap_list[i].ssid, result.ap_list[i].ap_power, + result.ap_list[i].channel, result.ap_list[i].security, + result.ap_list[i].bssid[0], result.ap_list[i].bssid[1], + result.ap_list[i].bssid[2], result.ap_list[i].bssid[3], + result.ap_list[i].bssid[4], result.ap_list[i].bssid[5]); + } + + if (m->ev_cb != NULL && m->ev_cb->scan_compeleted != NULL) { + m->ev_cb->scan_compeleted(m, &result, NULL); + } + + free(result.ap_list); + } + } + + free(scan_results.ap); + } +} + +void xr871_para_chg_event(void) +{ + WIFI_DEBUG("%s To Do\n", __func__); +} + +void xr871_fatal_err_event(void *arg) +{ + WIFI_DEBUG("%s To Do\n", __func__); +} + diff --git a/platform/mcu/xr871/aos/hal/wifi_port.h b/platform/mcu/xr871/aos/hal/wifi_port.h new file mode 100644 index 0000000000..cc29ded98a --- /dev/null +++ b/platform/mcu/xr871/aos/hal/wifi_port.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _WIFI_PORT_H_ +#define _WIFI_PORT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int xr871_wlan_init(void); +void xr871_wlan_get_mac_addr(uint8_t *mac); +int xr871_wlan_start(hal_wifi_init_type_t *init_para); +int xr871_wlan_start_adv(hal_wifi_init_type_adv_t *init_para_adv); +int xr871_wlan_get_ip_stat(hal_wifi_ip_stat_t *out_net_para, hal_wifi_type_t wifi_type); +int xr871_wlan_get_link_stat(hal_wifi_link_stat_t *out_stat); +void xr871_wlan_start_scan(void); +void xr871_wlan_start_adv_scan(void); +int xr871_wlan_power_off(void); +int xr871_wlan_power_on(void); +int xr871_wlan_suspend(void); +int xr871_wlan_suspend_station(void); +int xr871_wlan_suspend_softap(void); +int xr871_wlan_set_channel(int ch); +void xr871_wlan_start_monitor(void); +void xr871_wlan_stop_monitor(void); +void xr871_wlan_register_monitor_cb(monitor_data_cb_t fn); +void xr871_wlan_register_mgnt_monitor_cb(monitor_data_cb_t fn); +int xr871_wlan_send_80211_raw_frame(uint8_t *buf, int len); +void xr871_wlan_start_debug_mode(void); +void xr871_wlan_stop_debug_mode(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _WIFI_PORT_H_ */ diff --git a/platform/mcu/xr871/aos/soc_impl.c b/platform/mcu/xr871/aos/soc_impl.c new file mode 100644 index 0000000000..3ad7468dcb --- /dev/null +++ b/platform/mcu/xr871/aos/soc_impl.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#include +#include +#include +#include + +void soc_driver_init() +{ + hal_init(); + + printf("soc_driver_init done\n"); +} + +void soc_system_init() +{ + printf("%s %d\n", __func__, __LINE__); + platform_init(); +} + +void soc_systick_init() +{ + /* enable system tick */ + extern uint32_t SystemCoreClock; + SysTick_Config(SystemCoreClock/RHINO_CONFIG_TICKS_PER_SECOND); +} + +void SysTick_Handler(void) +{ + krhino_intrpt_enter(); + krhino_tick_proc(); + krhino_intrpt_exit(); +} diff --git a/platform/mcu/xr871/bin/xr871/boot.bin b/platform/mcu/xr871/bin/xr871/boot.bin new file mode 100644 index 0000000000000000000000000000000000000000..70e851cbe35518d6c616a6a55e0735c8d3f60337 GIT binary patch literal 31208 zcmdSCdwf*Y)i=J+IdjVmCJEpqBycj5z>q{72x0u@kSfuM4!EgF4_w>A@vFA>wRpsl_5JTqKcE?TEj8wFcW0L|n!^ZV{I69|a4 z&*%4h|M-Q^p0m$6d#}Cr+H0@1_S$P72+7PCa=DSShY%* zNQ8K+IP8nHD1dblBosTE5gV$EcFu zj{M*a@+-nK!lH{08#y@?R_*8H>;dgwrYI+%+Rw_54|Di^bJ*%*O^=6@E!=*BYl?-H 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z>!ZCUAob{9HShwE?Zs^m;%?}%|JW~iK=v!!M|+(>`bq!TPS!^}3#6V6_-i0;&rtL} z0q%jnb1_EG4B&syILvwW8t!?+V&2PFVH0RVIto8-$NL3dONezoly^h>j>De~ut&Yo zSnSKg6%jpFEFb<9*QRi>>$%fH%rFU&@e%HG3qmpLCoO~UcWp}#u%kNq+S{nL+rVf$z=6u;T@lm2~$L1BGtuUhBO zWB+-ge;-Hv91mq%<%k`QFUO1HX2TAS<5}Q$$Cu;Haqk3@2jm0w$Pe;_e4!rsLmrV& zlkrY_tdH{m{i7b|2ey~< z1?LSL%5xrx2C`qK18J`c$a$v$NIy9rvAwL1^A!7!dYr%5ucv?Y-=2`!|`I={KL@rlmBO7pL`;ZCj!Y&^3en3PNO_|^&*ht zJRQjKKMSND`NX&xJH$`&KN@NBojhIxWc-kiwATqe@``*Se_0>-$#|n4`Odi6JcLX$ zpZi&k<*7$~+UW$+F72}(*2j8TKlSJjS`8e(?2j9u755NP)5Bb6I zXS`95d}7?R-{s&Z`M>BL2j9u#Gvw<>=qvD%_85=k75T(CWqsr)n*=v$Qng~mw6PW;We|#rf(iwFi$oNx zZdBX|em1ULbWvPb?J}i)km9NZi@30wMf?%*6I-Zx-td&u4;pyJi=!_%$0w@AaS?)^&)ald;w;)4Y}=ZjICWZYbgQJsfmxl=yQ26O>g`K8 zk%Zmtgd^RyGZe9%fivfw?14lHkH`0{L z`;@@SO`fjW&Z7ElPHQ80WPrE)VhxzIs&{_{_ank+1Jj=6OBYK$0 zs(6ciz7*St00S#w9@EI^rT(kwN_kMf*K)ja&^KfOk5aTC;p0ig#+2eLd3SHBe8;@v z(MiRJ$kU@LpSYk{ODi5G&$y!U+X=;`4#kJb`!TKZ*oxx3x-yKAS8P_b#rk0qe$@}2 f@H}KRVEWs + +//#define inline inline +#define __inline inline +#define __inline__ inline + +#ifdef __always_inline +#undef __always_inline /* already defined in */ +#define __always_inline inline __attribute__((always_inline)) +#endif + +#ifndef __noinline +#define __noinline __attribute__((__noinline__)) +#endif + +#define __packed __attribute__((__packed__)) +#define __asm asm +#define __weak __attribute__((weak)) + +#else +#error "Compiler not supported." +#endif + +#endif /* _COMPILER_H_ */ diff --git a/platform/mcu/xr871/include/console/console.h b/platform/mcu/xr871/include/console/console.h new file mode 100644 index 0000000000..0f1b642db0 --- /dev/null +++ b/platform/mcu/xr871/include/console/console.h @@ -0,0 +1,65 @@ +/** + * @file console.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CONSOLE_CONSOLE_H_ +#define _CONSOLE_CONSOLE_H_ + +#include "driver/chip/hal_uart.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief type define of console command executing function */ +typedef void (*console_cmd_exec_func)(char *cmd); + +typedef struct console_param { + UART_ID uart_id; /* console's uart ID */ + console_cmd_exec_func cmd_exec; /* console command executing function */ +} console_param_t; + +int console_start(console_param_t *param); +void console_stop(void); + +int console_write(uint8_t *buf, int32_t len); + +void console_disable(void); +void console_enable(void); +UART_ID console_get_uart_id(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _CONSOLE_CONSOLE_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/chip.h b/platform/mcu/xr871/include/driver/chip/chip.h new file mode 100644 index 0000000000..0e6c83dc1a --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/chip.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_CHIP_H_ +#define _DRIVER_CHIP_CHIP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Configuration of the Cortex-M4/3 Processor and Core Peripherals + */ + +#ifdef __CONFIG_CPU_CM4F +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#else +#define __CM3_REV 0x0201 /*!< Core revision r2p1 */ +#define __FPU_PRESENT 0 /*!< FPU present */ +#endif + +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __NVIC_PRIO_BITS 3 /*!< uses 3 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum { + /* Cortex-M4/3 Processor Exceptions Numbers*/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + + /* Specific Interrupt Numbers */ + DMA_IRQn = 0, + GPIOA_IRQn = 1, + SDC_IRQn = 2, + MBOX_A_IRQn = 3, + UART0_IRQn = 4, + UART1_IRQn = 5, + SPI0_IRQn = 6, + SPI1_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + WDG_IRQn = 10, + TIMER0_IRQn = 11, + TIMER1_IRQn = 12, + RTC_SEC_ALARM_IRQn = 13, + RTC_WDAY_ALARM_IRQn = 14, + CSI_IRQn = 15, + I2S_IRQn = 16, + PWM_ECT_IRQn = 17, + CE_IRQn = 18, + GPADC_IRQn = 19, + GPIOB_IRQn = 20, + DMIC_IRQn = 21, + IRRX_IRQn = 22, + IRTX_IRQn = 23, + + MBOX_N_IRQn = 24, + A_WAKEUP_IRQn = 25, + FLASHC_IRQn = 26, + N_UART_IRQn = 27, + MAX_IRQn, /* keep last */ +} IRQn_Type; + +#define NVIC_PERIPH_IRQ_NUM MAX_IRQn +#define NVIC_PERIPH_IRQ_OFFSET 16 +#if (MAX_IRQn <= 32) +#define NVIC_PERIPH_IRQ_MASK0 ((1 << MAX_IRQn) - 1) +#else +#define NVIC_PERIPH_IRQ_MASK0 (0xffffffff) +#define NVIC_PERIPH_IRQ_MASK1 ((1 << (MAX_IRQn - 32)) - 1) +#endif +#define NVIC_VECTOR_TABLE_SIZE (NVIC_PERIPH_IRQ_OFFSET + NVIC_PERIPH_IRQ_NUM) + +#ifdef __CONFIG_CPU_CM4F +#include "driver/cmsis/core_cm4.h" +#else +#include "driver/cmsis/core_cm3.h" +#endif + +/*!< Peripheral memory map */ +#define PERIPH_BASE (0x40000000U) + +#define DMA_BASE (PERIPH_BASE + 0x00001000) +#define SDIO_BASE (PERIPH_BASE + 0x00002000) +#define CE_BASE (PERIPH_BASE + 0x00004000) +#define SPI0_BASE (PERIPH_BASE + 0x00005000) +#define SPI1_BASE (PERIPH_BASE + 0x00006000) +#define DCMI_BASE (PERIPH_BASE + 0x00007000) +#define SPINLOCK_BASE (PERIPH_BASE + 0x00008000) +#define MBOX_A_BASE (PERIPH_BASE + 0x00009000) +#define SYSCTL_BASE (PERIPH_BASE + 0x0000A000) +#define FLASH_CTRL_BASE (PERIPH_BASE + 0x0000B000) +#define FLASH_CACHE_BASE (PERIPH_BASE + 0x0000C000) +#define PRCM_BASE (PERIPH_BASE + 0x00040000) +#define CCM_BASE (PERIPH_BASE + 0x00040400) +#define TIMER_BASE (PERIPH_BASE + 0x00040800) +#define UART0_BASE (PERIPH_BASE + 0x00040C00) +#define UART1_BASE (PERIPH_BASE + 0x00041000) +#define RTC_BASE (PERIPH_BASE + 0x00041800) +#define I2C0_BASE (PERIPH_BASE + 0x00041c00) +#define I2C1_BASE (PERIPH_BASE + 0x00042000) +#define DMIC_BASE (PERIPH_BASE + 0x00042400) +#define PWM_BASE (PERIPH_BASE + 0x00042800) +#define I2S_BASE (PERIPH_BASE + 0x00042C00) +#define GPADC_BASE (PERIPH_BASE + 0x00043000) +#define IRTX_BASE (PERIPH_BASE + 0x00043400) +#define IRRX_BASE (PERIPH_BASE + 0x00043800) +#define SID_BASE (PERIPH_BASE + 0x00043C00) +#define GPIOA_CTRL_BASE (PERIPH_BASE + 0x00050000) +#define GPIOB_CTRL_BASE (PERIPH_BASE + 0x00050024) +#define GPIOA_IRQ_BASE (PERIPH_BASE + 0x00050200) +#define GPIOB_IRQ_BASE (PERIPH_BASE + 0x00050220) + +#define MBOX_N_BASE (0xA0003000U) +#define UARTN_BASE (0xA0042000U) + +/* Value of the External oscillator in Hz */ +#define HOSC_CLOCK_24M (24U * 1000U * 1000U) +#define HOSC_CLOCK_26M (26U * 1000U * 1000U) +#define HOSC_CLOCK_40M (40U * 1000U * 1000U) +#define HOSC_CLOCK_52M (52U * 1000U * 1000U) + +#define LOSC_CLOCK (32768U) + +#define SYS_PLL_CLOCK (960U * 1000U * 1000U) +#define SYS_LFCLOCK LOSC_CLOCK + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_CHIP_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/flashchip/flash_chip.h b/platform/mcu/xr871/include/driver/chip/flashchip/flash_chip.h new file mode 100644 index 0000000000..f4b104a6f0 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/flashchip/flash_chip.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FLASH_CHIP_H_ +#define FLASH_CHIP_H_ + +#include +#include +#include "types.h" + +typedef struct FlashChipBase FlashChipBase; +typedef struct FlashDrvierBase FlashDrvierBase; +typedef struct XipDriverBase XipDriverBase; + +typedef struct InstructionField +{ + uint32_t data; + uint8_t *pdata; + uint32_t len; + uint32_t line; +} InstructionField; + +typedef int (*FlashDrvIface)(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + +typedef enum FlashReadMode +{ + FLASH_READ_NORMAL_MODE = 1 << 0, /*!< cmd: 1 line, addr + dummy: 1 line, data: 1 line, freq can't too high */ + FLASH_READ_FAST_MODE = 1 << 1, /*!< cmd: 1 line, addr + dummy: 1 line, data: 1 line */ + FLASH_READ_DUAL_O_MODE = 1 << 2, /*!< cmd: 1 line, addr + dummy: 1 line, data: 2 line */ + FLASH_READ_DUAL_IO_MODE = 1 << 3, /*!< cmd: 1 line, addr + dummy: 2 line, data: 2 line */ + FLASH_READ_QUAD_O_MODE = 1 << 4, /*!< cmd: 1 line, addr + dummy: 1 line, data: 4 line */ + FLASH_READ_QUAD_IO_MODE = 1 << 5, /*!< cmd: 1 line, addr + dummy: 4 line, data: 4 line */ + FLASH_READ_QPI_MODE = 1 << 6, /*!< cmd: 4 line, addr + dummy: 4 line, data: 4 line */ +} FlashReadMode; + +typedef enum FlashEraseMode +{ + FLASH_ERASE_NOSUPPORT = 0, + FLASH_ERASE_4KB = 1 << 12, /*!< 4KB erase mode, command: 0x20 , esize: 4096 */ + FLASH_ERASE_32KB = 1 << 15, /*!< 32KB erase mode, command: 0x52 , esize: 32768 */ + FLASH_ERASE_64KB = 1 << 16, /*!< 64KB erase mode, command: 0xD8 , esize: 65536 */ + FLASH_ERASE_CHIP = 1 << 1, /*!< chip erase mode, command: 0xC7 *///0xC7, +} FlashEraseMode; + +typedef enum FlashStatus +{ + FLASH_STATUS1 = 1 << 0, /*!< flash status 1 */ + FLASH_STATUS2 = 1 << 1, /*!< flash status 2 */ + FLASH_STATUS3 = 1 << 2, /*!< flash status 3 */ +} FlashStatus; + +typedef enum FlashPageProgramMode +{ + FLASH_PAGEPROGRAM = 1 << 0, /*!< page program */ + FLASH_QUAD_PAGEPROGRAM = 1 << 1, /*!< quad page program */ +} FlashPageProgramMode; + +typedef enum FlashLockMode +{ + FlashLockMode_NOTHING /*!< nothing to support for now */ + /*TODO: tbc...*/ +} FlashLockMode; + +struct FlashChipBase +{ + /* + attribute + */ + uint32_t mJedec; + uint32_t mMaxFreq; + uint32_t mMaxReadFreq; //no need? + uint32_t mSize; + uint32_t mCsEn; //no need? + uint32_t mPageSize; //256bytes + + uint32_t mEraseSizeSupport; + uint16_t mReadStausSupport; + uint8_t mWriteStatusSupport; + uint8_t mPageProgramSupport; + uint16_t mReadSupport; + uint16_t mLockSupport; + + uint16_t mFlashStatus; + uint8_t mDummyCount; + + struct FlashDrvierBase *mDriver; + struct XipDriverBase *mXip; + + /* + private interface + */ + void (*writeEnable)(FlashChipBase *base); + void (*writeDisable)(FlashChipBase *base); + int (*readStatus)(FlashChipBase *base, FlashStatus status, uint8_t *data); + int (*writeStatus)(FlashChipBase *base, FlashStatus status, uint8_t *data); + int (*erase)(FlashChipBase *base, FlashEraseMode mode, uint32_t addr); //block count is realized in Flash erase. + int (*suspendErasePageprogram)(FlashChipBase *base); + int (*resumeErasePageprogram)(FlashChipBase *base); + int (*powerDown)(FlashChipBase *base); + int (*releasePowerDown)(FlashChipBase *base); + int (*jedecID)(FlashChipBase *base, uint32_t *data); + int (*enableQPIMode)(FlashChipBase *base); + int (*disableQPIMode)(FlashChipBase *base); +// int (*enableReset)(FlashChipBase *base); + int (*reset)(FlashChipBase *base); + int (*uniqueID)(FlashChipBase *base, uint8_t uid[8]); + int (*pageProgram)(FlashChipBase *base, FlashPageProgramMode mode, uint32_t addr, uint8_t *data, uint32_t size); + int (*read)(FlashChipBase *base, FlashReadMode mode, uint32_t addr, uint8_t *data, uint32_t size); + // tbc... + + int (*driverWrite)(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + int (*driverRead)(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + int (*xipDriverCfg)(FlashChipBase *base, FlashReadMode mode); + + /* + public interface + */ + int (*setFreq)(FlashChipBase *base, uint32_t freq); + int (*switchReadMode)(FlashChipBase *base, FlashReadMode mode); + int (*enableXIP)(FlashChipBase *base); + int (*disableXIP)(FlashChipBase *base); + int (*isBusy)(FlashChipBase *base); + int (*control)(FlashChipBase *base, int op, void *param); + FlashEraseMode (*minEraseSize)(FlashChipBase *base); +}; + +typedef enum DefaultFlashControlCmds +{ + DEFAULT_FLASH_SET_QPI_READ_P5P4, +} DefaultFlashControlCmds; + +/* + Default Flash Chip Interface +*/ +void defaultWriteEnable(FlashChipBase *base); + +void defaultWriteDisable(FlashChipBase *base); + +int defaultReadStatus(FlashChipBase *base, FlashStatus status, uint8_t *data); + +int defaultWriteStatus(FlashChipBase *base, FlashStatus reg, uint8_t *status); + +int defaultErase(FlashChipBase *base, FlashEraseMode mode, uint32_t addr); + +int defaultSuspendErasePageprogram(FlashChipBase *base); + +int defaultResumeErasePageprogram(FlashChipBase *base); + +int defaultPowerDown(FlashChipBase *base); + +int defaultReleasePowerDown(FlashChipBase *base); + +int defaultGetJedecID(FlashChipBase *base, uint32_t *data); + +int defaultEnableQPIMode(FlashChipBase *base); + +int defaultDisableQPIMode(FlashChipBase *base); + +int defaultEnableReset(FlashChipBase *base); + +int defaultReset(FlashChipBase *base); + +int defaultGetUniqueID(FlashChipBase *, uint8_t uid[8]); + +int defaultPageProgram(FlashChipBase *base, FlashPageProgramMode mode, uint32_t addr, uint8_t *data, uint32_t size); + +int defaultRead(FlashChipBase *base, FlashReadMode mode, uint32_t addr, uint8_t *data, uint32_t size); + +int defaultDriverWrite(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + +int defaultDriverRead(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + +int defaultSetFreq(FlashChipBase *base, uint32_t freq); + +int defaultSwitchReadMode(FlashChipBase *base, FlashReadMode mode); + +int defaultEnableXIP(FlashChipBase *base); + +int defaultDisableXIP(FlashChipBase *base); + +int defaultIsBusy(FlashChipBase *base); + +int defaultControl(FlashChipBase *base, int op, void *param); + +FlashEraseMode defaultGetMinEraseSize(FlashChipBase *base); + +int defaultXipDriverCfg(FlashChipBase *base, FlashReadMode mode); + + +typedef struct FlashChipCtor +{ + uint32_t mJedecId; + + FlashChipBase *(*create)(uint32_t arg); + int (*init)(FlashChipBase *); + int (*destory)(FlashChipBase *); +} FlashChipCtor; + +FlashChipBase *FlashChipCreate(FlashDrvierBase *driver); +int FlashChipDestroy(FlashChipBase *base); + + +/* + Flash Chip Debug +*/ +#define PCHECK(p) + +#endif /* FLASH_CHIP_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_adc.h b/platform/mcu/xr871/include/driver/chip/hal_adc.h new file mode 100644 index 0000000000..813746981d --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_adc.h @@ -0,0 +1,215 @@ +/** + * @file hal_adc.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_ADC_H_ +#define _DRIVER_CHIP_HAL_ADC_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ADC channel definition + */ +typedef enum { + ADC_CHANNEL_0 = 0, + ADC_CHANNEL_1 = 1, + ADC_CHANNEL_2 = 2, + ADC_CHANNEL_3 = 3, + ADC_CHANNEL_4 = 4, + ADC_CHANNEL_5 = 5, + ADC_CHANNEL_6 = 6, + ADC_CHANNEL_7 = 7, + ADC_CHANNEL_8 = 8, + ADC_CHANNEL_NUM = 9 +} ADC_Channel; + +/** + * @brief ADC register block structure + */ +typedef struct { + __IO uint32_t SAMPLE_RATE; /* offset: 0x00, GPADC sample rate configure register */ + __IO uint32_t CTRL; /* offset: 0x04, GPADC control Register */ + __IO uint32_t CMP_SEL_EN; /* offset: 0x08, GPADC compare and select enable register */ + __IO uint32_t FIFO_CTRL; /* offset: 0x0C, GPADC FIFO interrupt control register */ + __IO uint32_t FIFO_STATUS; /* offset: 0x10, GPADC FIFO interrupt status register */ + __IO uint32_t FIFO_DATA; /* offset: 0x14, GPADC FIFO data register */ + __IO uint32_t CALIB_DATA; /* offset: 0x18, GPADC calibration data register */ + __IO uint32_t RESERVED0; + __IO uint32_t LOW_CONFIG; /* offset: 0x20, GPADC data low interrupt configure register */ + __IO uint32_t HIGH_CONFIG; /* offset: 0x24, GPADC data high interrupt configure register */ + __IO uint32_t DATA_CONFIG; /* offset: 0x28, GPADC data interrupt configure register */ + __IO uint32_t RESERVED1; + __IO uint32_t LOW_STATUS; /* offset: 0x30, GPADC data low interrupt status register */ + __IO uint32_t HIGH_STATUS; /* offset: 0x34, GPADC data high interrupt status register */ + __IO uint32_t DATA_STATUS; /* offset: 0x38, GPADC data interrupt status register */ + __IO uint32_t RESERVED2; + __IO uint32_t CMP_DATA[ADC_CHANNEL_NUM]; /* offset: 0x40, GPADC CH n compare data register */ + __IO uint32_t RESERVED3[7]; + __I uint32_t DATA[ADC_CHANNEL_NUM]; /* offset: 0x80, GPADC CH n data register */ +} ADC_T; + +#define ADC ((ADC_T *)GPADC_BASE) /* address: 0x40043000 */ + +/* ADC->SAMPLE_RATE */ +#define ADC_FS_DIV_SHIFT 16 +#define ADC_FS_DIV_MASK (0xFFFFU << ADC_FS_DIV_SHIFT) + +#define ADC_TACQ_SHIFT 0 +#define ADC_TACQ_MASK (0xFFFFU << ADC_TACQ_SHIFT) + +/* ADC->CTRL */ +#define ADC_FIRST_DELAY_SHIFT 24 +#define ADC_FIRST_DELAY_MASK (0xFFU << ADC_FIRST_DELAY_SHIFT) + +#define ADC_OP_BIAS_SHIFT 20 +#define ADC_OP_BIAS_MASK (0x3U << ADC_OP_BIAS_SHIFT) + +#define ADC_WORK_MODE_SHIFT 18 +#define ADC_WORK_MODE_MASK (0x3U << ADC_WORK_MODE_SHIFT) +typedef enum { + ADC_SINGLE_CONV = 0U, + ADC_SINGLE_CYCLE = 1U, + ADC_CONTI_CONV = 2U, + ADC_BURST_CONV = 3U +} ADC_WorkMode; + +#define ADC_CALIB_EN_BIT HAL_BIT(17) +#define ADC_EN_BIT HAL_BIT(16) +#define ADC_VBAT_EN_BIT HAL_BIT(4) +#define ADC_LDO_EN_BIT HAL_BIT(0) + +/* ADC->CMP_SEL_EN */ +#define ADC_CMP_EN_SHIFT 16 +#define ADC_CMP_EN_MASK (0x1FFU << ADC_CMP_EN_SHIFT) + +#define ADC_SEL_EN_SHIFT 0 +#define ADC_SEL_EN_MASK (0x1FFU << ADC_SEL_EN_SHIFT) + +/* + * ADC->LOW_CONFIG + * ADC->HIGH_CONFIG + * ADC->DATA_CONFIG + */ +#define ADC_LOW_IRQ_MASK 0x1FFU +#define ADC_HIGH_IRQ_MASK 0x1FFU +#define ADC_DATA_IRQ_MASK 0x1FFU + +/* + * ADC->LOW_STATUS + * ADC->HIGH_STATUS + * ADC->DATA_STATUS + */ +#define ADC_LOW_PENDING_MASK 0x1FFU +#define ADC_HIGH_PENDING_MASK 0x1FFU +#define ADC_DATA_PENDING_MASK 0x1FFU + +/* ADC->CMP_DATA */ +#define ADC_HIGH_DATA_SHIFT 16 +#define ADC_HIGH_DATA_MASK (0xFFFU << ADC_HIGH_DATA_SHIFT) + +#define ADC_LOW_DATA_SHIFT 0 +#define ADC_LOW_DATA_MASK (0xFFFU << ADC_LOW_DATA_SHIFT) + +/* ADC->DATA */ +#define ADC_DATA_MASK 0xFFFU + +/******************************************************************************/ + +/** + * @brief ADC channel initialization parameters + */ +typedef struct { + uint32_t freq; /* ADC sample frequency */ + uint8_t delay; /* the number of delayed samples in first conversion */ +} ADC_InitParam; + +/** + * @brief ADC channel selected state definition + */ +typedef enum { + ADC_SELECT_DISABLE = 0, + ADC_SELECT_ENABLE = 1 +} ADC_Select; + +/** + * @brief ADC interrupt mode definition + */ +typedef enum { + ADC_IRQ_NONE = 0, + ADC_IRQ_DATA = 1, + ADC_IRQ_LOW = 2, + ADC_IRQ_HIGH = 3, + ADC_IRQ_LOW_DATA = 4, + ADC_IRQ_HIGH_DATA = 5, + ADC_IRQ_LOW_HIGH = 6, + ADC_IRQ_LOW_HIGH_DATA = 7 +} ADC_IRQMode; + +/** + * @brief ADC interrupt state definition + */ +typedef enum { + ADC_NO_IRQ = 0, + ADC_DATA_IRQ = 1, + ADC_LOW_IRQ = 2, + ADC_HIGH_IRQ = 3, + ADC_LOW_DATA_IRQ = 4, + ADC_HIGH_DATA_IRQ = 5 +} ADC_IRQState; + +/** @brief Type define of ADC interrupt callback function */ +typedef void (*ADC_IRQCallback)(void *arg); + +HAL_Status HAL_ADC_Init(ADC_InitParam *initParam); +HAL_Status HAL_ADC_DeInit(void); + +HAL_Status HAL_ADC_Conv_Polling(ADC_Channel chan, uint32_t *data, uint32_t msec); + +HAL_Status HAL_ADC_EnableIRQCallback(ADC_Channel chan, ADC_IRQCallback cb, void *arg); +HAL_Status HAL_ADC_DisableIRQCallback(ADC_Channel chan); + +HAL_Status HAL_ADC_ConfigChannel(ADC_Channel chan, ADC_Select select, ADC_IRQMode mode, uint32_t lowValue, uint32_t highValue); +HAL_Status HAL_ADC_Start_Conv_IT(void); +HAL_Status HAL_ADC_Stop_Conv_IT(void); +ADC_IRQState HAL_ADC_GetIRQState(ADC_Channel chan); +uint32_t HAL_ADC_GetValue(ADC_Channel chan); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_ADC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_audio.h b/platform/mcu/xr871/include/driver/chip/hal_audio.h new file mode 100644 index 0000000000..b90a02ed31 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_audio.h @@ -0,0 +1,61 @@ +/** + * @file hal_audio.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HAL_AUDIO_H_H +#define HAL_AUDIO_H_H + +typedef enum { + DAIFMT_CBM_CFM, /*(codec clk & FRM master) use((i2s slave))*/ + DAIFMT_CBS_CFM, /*(codec clk slave & FRM master) not use*/ + DAIFMT_CBM_CFS, /*(codec clk master & frame slave) not use*/ + DAIFMT_CBS_CFS, /*(codec clk & FRM slave) use(i2s master)*/ +} PCM_ClkMode; + +typedef enum { + DAIFMT_I2S, /*(standard i2s format). use*/ + DAIFMT_RIGHT_J, /*(right justfied format).*/ + DAIFMT_LEFT_J, /*(left justfied format) */ + DAIFMT_DSP_A, /*(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use*/ + DAIFMT_DSP_B, /*(pcm. MSB is available on 1nd BCLK rising edge after LRC rising*/ +} PCM_TranFmt; + +typedef enum { + DAIFMT_NB_NF, /*(normal bit clock + frame) use*/ + DAIFMT_NB_IF, /*(normal BCLK + inv FRM) */ + DAIFMT_IB_NF, /*(invert BCLK + nor FRM) use*/ + DAIFMT_IB_IF, /*(invert BCLK + FRM)*/ +} PCM_SignalInv; + + +#endif diff --git a/platform/mcu/xr871/include/driver/chip/hal_ccm.h b/platform/mcu/xr871/include/driver/chip/hal_ccm.h new file mode 100644 index 0000000000..382e86848a --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_ccm.h @@ -0,0 +1,308 @@ +/** + * @file hal_board.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CCM_H_ +#define _DRIVER_CHIP_HAL_CCM_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief CCM (Clock Control Module) register block structure + */ +typedef struct +{ + __IO uint32_t CPU_BUS_CLKCFG; /* offset: 0x00, CPU bus clock configure register */ + __IO uint32_t BUS_PERIPH_CLK_CTRL; /* offset: 0x04, Bus device clock gating control Register */ + __IO uint32_t BUS_PERIPH_RST_CTRL; /* offset: 0x08, Bus device reset control register */ + uint32_t RESERVED0[5]; + __IO uint32_t SPI0_MCLK_CTRL; /* offset: 0x20, SPI0 clock control register */ + __IO uint32_t SPI1_MCLK_CTRL; /* offset: 0x24, SPI1 clock control register */ + __IO uint32_t SDC_MCLK_CTRL; /* offset: 0x28, SDC clock control register */ + __IO uint32_t CE_MCLK_CTRL; /* offset: 0x2C, CE clock control register */ + __IO uint32_t CSI_OCLK_CTRL; /* offset: 0x30, CSI output clock control register */ + __IO uint32_t DAUDIO_MCLK_CTRL; /* offset: 0x34, Digital audio clock control register */ + __IO uint32_t IRRX_MCLK_CTRL; /* offset: 0x38, IRRX clock control register */ + __IO uint32_t IRTX_MCLK_CTRL; /* offset: 0x3C, IRTX clock control register */ + __IO uint32_t SYSTICK_REFCLK_CTRL; /* offset: 0x40, System tick reference clock register */ + __IO uint32_t SYSTICK_CALIB_CTRL; /* offset: 0x44, System tick clock calibration register */ + __IO uint32_t DMIC_MCLK_CTRL; /* offset: 0x48, DMIC clock control register */ + __IO uint32_t GPADC_MCLK_CTRL; /* offset: 0x4C, GPADC clock control register */ + __IO uint32_t CSI_MCLK_CTRL; /* offset: 0x50, CSI module clock control register */ + __IO uint32_t FLASHC_MCLK_CTRL; /* offset: 0x54, Flash controller clock control register */ +} CCM_T; + +#define CCM ((CCM_T *)CCM_BASE) /* address: 0x40040400 */ + +/* + * Bit field definition of CCM->CPU_BUS_CLKCFG + */ +#define CCM_AHB2_CLK_DIV_SHIFT 8 /* R/W */ +#define CCM_AHB2_CLK_DIV_MASK (0x3U << CCM_AHB2_CLK_DIV_SHIFT) +typedef enum { + CCM_AHB2_CLK_DIV_1 = (0x0U << CCM_AHB2_CLK_DIV_SHIFT), + CCM_AHB2_CLK_DIV_2 = (0x1U << CCM_AHB2_CLK_DIV_SHIFT), + CCM_AHB2_CLK_DIV_3 = (0x2U << CCM_AHB2_CLK_DIV_SHIFT), + CCM_AHB2_CLK_DIV_4 = (0x3U << CCM_AHB2_CLK_DIV_SHIFT) +} CCM_AHB2ClkDiv; + +#define CCM_APB_CLK_SRC_SHIFT 4 /* R/W */ +#define CCM_APB_CLK_SRC_MASK (0x3U << CCM_APB_CLK_SRC_SHIFT) +typedef enum { + CCM_APB_CLK_SRC_HFCLK = (0x0U << CCM_APB_CLK_SRC_SHIFT), + CCM_APB_CLK_SRC_LFCLK = (0x1U << CCM_APB_CLK_SRC_SHIFT), + CCM_APB_CLK_SRC_AHB2CLK = (0x2U << CCM_APB_CLK_SRC_SHIFT) +} CCM_APBClkSrc; + +#define CCM_APB_CLK_DIV_SHIFT 0 /* R/W */ +#define CCM_APB_CLK_DIV_MASK (0x3U << CCM_APB_CLK_DIV_SHIFT) +typedef enum { + CCM_APB_CLK_DIV_1 = (0x0U << CCM_APB_CLK_DIV_SHIFT), + CCM_APB_CLK_DIV_2 = (0x1U << CCM_APB_CLK_DIV_SHIFT), + CCM_APB_CLK_DIV_4 = (0x2U << CCM_APB_CLK_DIV_SHIFT), + CCM_APB_CLK_DIV_8 = (0x3U << CCM_APB_CLK_DIV_SHIFT) +} CCM_APBClkDiv; + +/* + * Bit field definition of + * - CCM->BUS_PERIPH_CLK_CTRL + * - CCM->BUS_PERIPH_RST_CTRL + */ +typedef enum { + CCM_BUS_PERIPH_BIT_GPIO = HAL_BIT(27), /* R/W, only valid for clock, not for reset */ + CCM_BUS_PERIPH_BIT_DMIC = HAL_BIT(26), /* R/W */ + CCM_BUS_PERIPH_BIT_GPADC = HAL_BIT(25), /* R/W */ + CCM_BUS_PERIPH_BIT_IRRX = HAL_BIT(24), /* R/W */ + CCM_BUS_PERIPH_BIT_IRTX = HAL_BIT(23), /* R/W */ + CCM_BUS_PERIPH_BIT_DAUDIO = HAL_BIT(22), /* R/W */ + CCM_BUS_PERIPH_BIT_PWM = HAL_BIT(21), /* R/W */ + CCM_BUS_PERIPH_BIT_I2C1 = HAL_BIT(19), /* R/W */ + CCM_BUS_PERIPH_BIT_I2C0 = HAL_BIT(18), /* R/W */ + CCM_BUS_PERIPH_BIT_UART1 = HAL_BIT(17), /* R/W */ + CCM_BUS_PERIPH_BIT_UART0 = HAL_BIT(16), /* R/W */ + CCM_BUS_PERIPH_BIT_MSGBOX = HAL_BIT(8), /* R/W */ + CCM_BUS_PERIPH_BIT_SPINLOCK = HAL_BIT(7), /* R/W */ + CCM_BUS_PERIPH_BIT_DMA = HAL_BIT(6), /* R/W */ + CCM_BUS_PERIPH_BIT_CSI = HAL_BIT(5), /* R/W */ + CCM_BUS_PERIPH_BIT_SDC0 = HAL_BIT(4), /* R/W */ + CCM_BUS_PERIPH_BIT_FLASHC = HAL_BIT(3), /* R/W */ + CCM_BUS_PERIPH_BIT_CE = HAL_BIT(2), /* R/W */ + CCM_BUS_PERIPH_BIT_SPI1 = HAL_BIT(1), /* R/W */ + CCM_BUS_PERIPH_BIT_SPI0 = HAL_BIT(0) /* R/W */ +} CCM_BusPeriphBit; + +/* + * Bit field definition of CLK enable + * - for SPI0, SP1, SDC, CE, CSI, DAUDIO, IRRX, IRTX, SYSTICK, DMIC, GPADC, CSI_OUT + */ +#define CCM_PERIPH_CLK_EN_BIT HAL_BIT(31) /* R/W */ + +/* + * Bit field definition of CLK source + * - AHB peripheral: SPI0, SP1, SDC, CE, CSI, CSI_OUT + * - APB peripheral: IRRX, IRTX, SYSTICK, GPADC + */ +#define CCM_PERIPH_CLK_SRC_SHIFT 24 /* R/W */ +#define CCM_PERIPH_CLK_SRC_MASK (0x3U << CCM_PERIPH_CLK_SRC_SHIFT) + +typedef enum { + CCM_AHB_PERIPH_CLK_SRC_HFCLK = (0x0U << CCM_PERIPH_CLK_SRC_SHIFT), + CCM_AHB_PERIPH_CLK_SRC_DEVCLK = (0x1U << CCM_PERIPH_CLK_SRC_SHIFT), +} CCM_AHBPeriphClkSrc; + +typedef enum { + CCM_APB_PERIPH_CLK_SRC_HFCLK = (0x0U << CCM_PERIPH_CLK_SRC_SHIFT), + CCM_APB_PERIPH_CLK_SRC_LFCLK = (0x1U << CCM_PERIPH_CLK_SRC_SHIFT) +} CCM_APBPeriphClkSrc; + +/* + * Bit field definition of CLK divider N, M + * - for SPI0, SP1, SDC, CE, CSI, IRRX, IRTX, SYSTICK, GPADC, CSI_OUT + */ +#define CCM_PERIPH_CLK_DIV_N_SHIFT 16 /* R/W */ +#define CCM_PERIPH_CLK_DIV_N_MASK (0x3U << CCM_PERIPH_CLK_DIV_N_SHIFT) +typedef enum { + CCM_PERIPH_CLK_DIV_N_1 = (0U << CCM_PERIPH_CLK_DIV_N_SHIFT), + CCM_PERIPH_CLK_DIV_N_2 = (1U << CCM_PERIPH_CLK_DIV_N_SHIFT), + CCM_PERIPH_CLK_DIV_N_4 = (2U << CCM_PERIPH_CLK_DIV_N_SHIFT), + CCM_PERIPH_CLK_DIV_N_8 = (3U << CCM_PERIPH_CLK_DIV_N_SHIFT) +} CCM_PeriphClkDivN; + +#define CCM_PERIPH_CLK_DIV_M_SHIFT 0 /* R/W */ +#define CCM_PERIPH_CLK_DIV_M_MASK (0xFU << CCM_PERIPH_CLK_DIV_M_SHIFT) +typedef enum { + CCM_PERIPH_CLK_DIV_M_1 = (0U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_2 = (1U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_3 = (2U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_4 = (3U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_5 = (4U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_6 = (5U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_7 = (6U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_8 = (7U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_9 = (8U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_10 = (9U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_11 = (10U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_12 = (11U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_13 = (12U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_14 = (13U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_15 = (14U << CCM_PERIPH_CLK_DIV_M_SHIFT), + CCM_PERIPH_CLK_DIV_M_16 = (15U << CCM_PERIPH_CLK_DIV_M_SHIFT) +} CCM_PeriphClkDivM; + +#define CCM_PERIPH_CLK_PARAM_MASK (CCM_PERIPH_CLK_SRC_MASK | \ + CCM_PERIPH_CLK_DIV_N_MASK | \ + CCM_PERIPH_CLK_DIV_M_MASK) + +/* CCM->SPI0_MCLK_CTRL */ + +/* CCM->SPI1_MCLK_CTRL */ + +/* CCM->SDC_MCLK_CTRL */ + +/* CCM->CE_MCLK_CTRL */ + +/* CCM->CSI_OCLK_CTRL */ + +/* + * Bit field definition of CCM->DAUDIO_MCLK_CTRL + */ +#define CCM_DAUDIO_MCLK_SRC_SHIFT 0 /* R/W */ +#define CCM_DAUDIO_MCLK_SRC_MASK (0x3U << CCM_DAUDIO_MCLK_SRC_SHIFT) +typedef enum { + CCM_DAUDIO_MCLK_SRC_8X = (0x0U << CCM_DAUDIO_MCLK_SRC_SHIFT), + CCM_DAUDIO_MCLK_SRC_4X = (0x1U << CCM_DAUDIO_MCLK_SRC_SHIFT), + CCM_DAUDIO_MCLK_SRC_2X = (0x2U << CCM_DAUDIO_MCLK_SRC_SHIFT), + CCM_DAUDIO_MCLK_SRC_1X = (0x3U << CCM_DAUDIO_MCLK_SRC_SHIFT) +} CCM_DAudioClkSrc; + +/* CCM->IRRX_MCLK_CTRL */ + +/* CCM->IRTX_MCLK_CTRL */ + +/* CCM->SYSTICK_REFCLK_CTRL */ + +/* + * Bit field definition of CCM->SYSTICK_CALIB_CTRL + */ +#define CCM_SYSTICK_NOREF_BIT HAL_BIT(25) /* R/W */ +#define CCM_SYSTICK_SKEW_BIT HAL_BIT(24) /* R/W */ +#define CCM_SYSTICK_TENMS_SHIFT 0 /* R/W */ +#define CCM_SYSTICK_TENMS_MASK (0xFFFFFFU << CCM_SYSTICK_TENMS_SHIFT) + +/* CCM->DMIC_MCLK_CTRL */ + +/* CCM->DMIC_MCLK_CTRL */ + +/* CCM->CSI_MCLK_CTRL */ + +/* CCM->FLASHC_MCLK_CTRL */ + +/******************************************************************************/ + +void HAL_CCM_BusSetClock(CCM_AHB2ClkDiv AHB2Div, CCM_APBClkSrc APBSrc, CCM_APBClkDiv APBDiv); +uint32_t HAL_CCM_BusGetAHB1Clock(void); +uint32_t HAL_CCM_BusGetAHB2Clock(void); +uint32_t HAL_CCM_BusGetAPBClock(void); + +void HAL_CCM_BusEnablePeriphClock(uint32_t periphMask); +void HAL_CCM_BusDisablePeriphClock(uint32_t periphMask); +void HAL_CCM_BusDisableAllPeriphClock(void); +void HAL_CCM_BusForcePeriphReset(uint32_t periphMask); +void HAL_CCM_BusReleasePeriphReset(uint32_t periphMask); +void HAL_CCM_BusForceAllPeriphReset(void); + +void HAL_CCM_SPI0_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_SPI0_EnableMClock(void); +void HAL_CCM_SPI0_DisableMClock(void); +void HAL_CCM_SPI1_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_SPI1_EnableMClock(void); +void HAL_CCM_SPI1_DisableMClock(void); + +void HAL_CCM_SDC_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_SDC_EnableMClock(void); +void HAL_CCM_SDC_DisableMClock(void); + +void HAL_CCM_CE_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_CE_EnableMClock(void); +void HAL_CCM_CE_DisableMClock(void); + +void HAL_CCM_CSI_SetOutClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_CSI_EnableOutClock(void); +void HAL_CCM_CSI_DisableOutClock(void); + +void HAL_CCM_DAUDIO_SetMClock(CCM_DAudioClkSrc src); +void HAL_CCM_DAUDIO_EnableMClock(void); +void HAL_CCM_DAUDIO_DisableMClock(void); + +void HAL_CCM_IRRX_SetMClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_IRRX_EnableMClock(void); +void HAL_CCM_IRRX_DisableMClock(void); +void HAL_CCM_IRTX_SetMClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_IRTX_EnableMClock(void); +void HAL_CCM_IRTX_DisableMClock(void); + +void HAL_CCM_SYSTICK_SetRefClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_SYSTICK_EnableRefClock(void); +void HAL_CCM_SYSTICK_DisableRefClock(void); +void HAL_CCM_SYSTICK_EnableRef(void); +void HAL_CCM_SYSTICK_DisableRef(void); +void HAL_CCM_SYSTICK_EnableSkew(void); +void HAL_CCM_SYSTICK_DisableSkew(void); +void HAL_CCM_SYSTICK_SetTENMS(uint32_t cnt); + +void HAL_CCM_DMIC_EnableMClock(void); +void HAL_CCM_DMIC_DisableMClock(void); + +void HAL_CCM_GPADC_SetMClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_GPADC_EnableMClock(void); +void HAL_CCM_GPADC_DisableMClock(void); + +void HAL_CCM_CSI_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_CSI_EnableMClock(void); +void HAL_CCM_CSI_DisableMClock(void); + +void HAL_CCM_FLASHC_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM); +void HAL_CCM_FLASHC_EnableMClock(void); +void HAL_CCM_FLASHC_DisableMClock(void); + +void HAL_CCM_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_CCM_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_chip.h b/platform/mcu/xr871/include/driver/chip/hal_chip.h new file mode 100644 index 0000000000..b81da08368 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_chip.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CHIP_H_ +#define _DRIVER_CHIP_HAL_CHIP_H_ + +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_nvic.h" +#include "driver/chip/hal_clock.h" +#include "driver/chip/hal_ccm.h" +#include "driver/chip/hal_prcm.h" +#include "driver/chip/hal_dma.h" +#include "driver/chip/hal_crypto.h" +#include "driver/chip/hal_efuse.h" +#include "driver/chip/hal_rtc.h" +#include "driver/chip/hal_timer.h" +#include "driver/chip/hal_wdg.h" +#include "driver/chip/hal_mbox.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_uart.h" +#include "driver/chip/hal_i2c.h" +#include "driver/chip/hal_adc.h" +#include "driver/chip/hal_spi.h" +#include "driver/chip/hal_pwm.h" +#include "driver/chip/hal_i2s.h" +#include "driver/chip/hal_dmic.h" +#include "driver/chip/hal_csi.h" +#include "driver/chip/hal_irtx.h" +#include "driver/chip/hal_irrx.h" +#include "driver/chip/sdmmc/hal_sdhost.h" +#include "driver/chip/hal_flash.h" + +#endif /* _DRIVER_CHIP_HAL_CHIP_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_clock.h b/platform/mcu/xr871/include/driver/chip/hal_clock.h new file mode 100644 index 0000000000..3751a4a3c7 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_clock.h @@ -0,0 +1,112 @@ +/** + * @file hal_clock.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CLOCK_H_ +#define _DRIVER_CHIP_HAL_CLOCK_H_ + +#include "driver/chip/hal_prcm.h" +#include "driver/chip/hal_ccm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get HF clock, which is the value of external high frequency oscillator + * @return HF clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetHFClock(void) +{ + return HAL_PRCM_GetHFClock(); +} + +/** + * @brief Get LF clock, which is the value of low frequence oscillator + * @return LF clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetLFClock(void) +{ + return SYS_LFCLOCK; +} + +/** + * @brief Get CPU clock + * @return CPU clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetCPUClock(void) +{ + return HAL_PRCM_GetCPUAClk(); +} + +/** + * @brief Get Device clock + * @return Device clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetDevClock(void) +{ + return HAL_PRCM_GetDevClock(); +} + +/** + * @brief Get AHB1 clock + * @return AHB1 clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetAHB1Clock(void) +{ + return HAL_CCM_BusGetAHB1Clock(); +} + +/** + * @brief Get AHB2 clock + * @return AHB2 clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetAHB2Clock(void) +{ + return HAL_CCM_BusGetAHB2Clock(); +} + +/** + * @brief Get APB clock + * @return APB clock in Hz + */ +__STATIC_INLINE uint32_t HAL_GetAPBClock(void) +{ + return HAL_CCM_BusGetAPBClock(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_CLOCK_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_cmsis.h b/platform/mcu/xr871/include/driver/chip/hal_cmsis.h new file mode 100644 index 0000000000..5719254c94 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_cmsis.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CMSIS_H_ +#define _DRIVER_CHIP_HAL_CMSIS_H_ + +#include "driver/chip/chip.h" + +#endif /* _DRIVER_CHIP_HAL_CMSIS_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_codec.h b/platform/mcu/xr871/include/driver/chip/hal_codec.h new file mode 100644 index 0000000000..d9ae91d3b1 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_codec.h @@ -0,0 +1,172 @@ +/** + * @file hal_codec.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CODEC_H_ +#define _DRIVER_CHIP_HAL_CODEC_H_ + +#include +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_i2c.h" +#include "driver/chip/hal_audio.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief The param for PA control. + */ +typedef struct { + GPIO_Port ctrl_port; + GPIO_Pin ctrl_pin; + GPIO_PinState ctrl_on_state; + GPIO_PinState ctrl_off_state; +} SPK_Param; + +/** + * @brief Audio device structures definition. + */ +typedef enum { + AUDIO_DEVICE_HEADPHONE = 1, /*!< Headphone */ + AUDIO_DEVICE_SPEAKER, /*!< Speaker */ + AUDIO_DEVICE_HEADPHONEMIC, /*!< Headphone Mic */ + AUDIO_DEVICE_MAINMIC, /*!< Main Mic */ + AUDIO_DEVICE_NONE /*!< none */ +} AUDIO_Device; + +/** + * @brief Audio volume gain structures definition. + */ +typedef enum { + VOLUME_LEVEL0, + VOLUME_LEVEL1, + VOLUME_LEVEL2, + VOLUME_LEVEL3, + VOLUME_LEVEL4, + VOLUME_LEVEL5, + VOLUME_LEVEL6, + VOLUME_LEVEL7, + VOLUME_LEVEL8, + VOLUME_LEVEL9, + VOLUME_LEVEL10, + VOLUME_LEVEL11, + VOLUME_LEVEL12, + VOLUME_LEVEL13, + VOLUME_LEVEL14, + VOLUME_LEVEL15, + VOLUME_LEVEL16, + VOLUME_LEVEL17, + VOLUME_LEVEL18, + VOLUME_LEVEL19, + VOLUME_LEVEL20, + VOLUME_LEVEL21, + VOLUME_LEVEL22, + VOLUME_LEVEL23, + VOLUME_LEVEL24, + VOLUME_LEVEL25, + VOLUME_LEVEL26, + VOLUME_LEVEL27, + VOLUME_LEVEL28, + VOLUME_LEVEL29, + VOLUME_LEVEL30, + VOLUME_LEVEL31, + VOLUME_MAX_LEVEL = VOLUME_LEVEL31, +} Vollevel; + +/** + * @brief Pcm communication parameters + */ +typedef struct { + PCM_ClkMode clkMode; /*!< Specifies the pcm clk mode */ + PCM_TranFmt transferFormat; /*!< Specifies the pcm operating mode */ + PCM_SignalInv signalInterval; /*!< Specifies the pcm Clock Polarity */ + uint32_t slotWidth; /*!< Specifies the pcm slot width */ + uint32_t wordWidth; /*!< Specifies the data format for the communication */ + uint32_t freqIn; /*!< Specifies the external input clock frequency */ + uint32_t freqOut; /*!< Specifies the clock the module work properly */ + uint32_t pllId; +} DAI_FmtParam; + +/** + * @brief Codec Gain parameters + */ +typedef struct { + uint8_t speaker_double_used; /*!< Flag of speaker case (double or single) */ + uint8_t double_speaker_val; /*!< Volume gain of double speaker */ + uint8_t single_speaker_val; /*!< Volume gain of single speaker */ + uint8_t headset_val; /*!< Volume gain of headset */ + uint8_t mainmic_val; /*!< Volume gain of main mic */ + uint8_t headsetmic_val; /*!< Volume gain of headset mic */ +} CODEC_InitParam; + +/** + * @brief Data format Init parameters + */ +typedef struct { + uint32_t sampleRate; /*!< Sample rate for the stream data */ + AUDIO_Device audioDev; /*!< Audio device to play or capture */ + DAI_FmtParam *fmtParam; /*!< Parameters for Pcm transfer initialization */ +} DATA_Param; + +typedef int32_t (*hw_write)(I2C_ID i2cId, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size); +typedef int32_t (*hw_read)(I2C_ID i2cId, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size); + +/** + * @brief CODEC Param Init structure definition + */ +typedef struct { + uint8_t *name; /*!< Name of specific codec */ + hw_write write; /*!< I2C write function */ + hw_read read; /*!< I2C read function */ + CODEC_InitParam *param; /*!< Parameters for codec gain initialization */ + uint8_t i2cId; /*!< Index of I2C for control codec */ +} CODEC_Param; + +HAL_Status HAL_CODEC_DeInit(); +HAL_Status HAL_CODEC_Init(const CODEC_Param *param); +HAL_Status HAL_CODEC_Close(uint32_t dir); +HAL_Status HAL_CODEC_Open(DATA_Param *param); +HAL_Status HAL_CODEC_VOLUME_LEVEL_Set(AUDIO_Device dev,int volume); +HAL_Status HAL_CODEC_ROUTE_Set(AUDIO_Device dev); +HAL_Status HAL_CODEC_Mute(AUDIO_Device dev, uint32_t mute); +HAL_Status HAL_CODEC_Trigger(AUDIO_Device dev, uint32_t on); +uint32_t HAL_CODEC_MUTE_STATUS_Get(); +HAL_Status HAL_CODEC_MUTE_STATUS_Init(int status); +HAL_Status HAL_CODEC_INIT_VOLUME_Set(AUDIO_Device dev,int volume); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_CODEC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_crypto.h b/platform/mcu/xr871/include/driver/chip/hal_crypto.h new file mode 100644 index 0000000000..274c1d5017 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_crypto.h @@ -0,0 +1,414 @@ +/** + * @file hal_crypto.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CRYPTO_H_ +#define _DRIVER_CHIP_HAL_CRYPTO_H_ + +#include +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_dma.h" +#include "sys/xr_debug.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct +{ + __IO uint32_t CTL; /*!< CRYP Control Register, Address offset: 0x00 */ +// __IO uint32_t KEY0; /*!< CRYP Input Key 0/PRNG Seed 0 Register, Address offset: 0x04 */ +// __IO uint32_t KEY1; /*!< CRYP Input Key 1/PRNG Seed 1 Register, Address offset: 0x08 */ +// __IO uint32_t KEY2; /*!< CRYP Input Key 2/PRNG Seed 2 Register, Address offset: 0x0C */ +// __IO uint32_t KEY3; /*!< CRYP Input Key 3/PRNG Seed 3 Register, Address offset: 0x10 */ +// __IO uint32_t KEY4; /*!< CRYP Input Key 4/PRNG Seed 4 Register, Address offset: 0x14 */ +// __IO uint32_t KEY5; /*!< CRYP Input Key 5/PRNG Seed 5 Register, Address offset: 0x18 */ +// __IO uint32_t KEY6; /*!< CRYP Input Key 6/PRNG Seed 6 Register, Address offset: 0x1C */ +// __IO uint32_t KEY7; /*!< CRYP Input Key 7/PRNG Seed 7 Register, Address offset: 0x20 */ + __IO uint32_t KEY[8]; +// __IO uint32_t IV0; /*!< CRYP Initialization Vector 0 Register, Address offset: 0x24 */ +// __IO uint32_t IV1; /*!< CRYP Initialization Vector 1 Register, Address offset: 0x28 */ +// __IO uint32_t IV2; /*!< CRYP Initialization Vector 2 Register, Address offset: 0x2C */ +// __IO uint32_t IV3; /*!< CRYP Initialization Vector 3 Register, Address offset: 0x30 */ + __IO uint32_t IV[4]; +// __IO uint32_t CNT0; /*!< CRYP Counter 0 Register, Address offset: 0x34 */ +// __IO uint32_t CNT1; /*!< CRYP Counter 1 Register, Address offset: 0x38 */ +// __IO uint32_t CNT2; /*!< CRYP Counter 2 Register, Address offset: 0x3C */ +// __IO uint32_t CNT3; /*!< CRYP Counter 3 Register, Address offset: 0x40 */ + __IO uint32_t CNT[4]; + __IO uint32_t FCSR; /*!< CRYP FIFO Control/Status Register, Address offset: 0x44 */ + __IO uint32_t ICSR; /*!< CRYP Interrupt Control/Status Register, Address offset: 0x48 */ + __I uint32_t MD0; /*!< CRYP Message Digest 0/PRNG Data 0 Register, Address offset: 0x4C */ + __I uint32_t MD1; /*!< CRYP Message Digest 1/PRNG Data 1 Register, Address offset: 0x50 */ + __I uint32_t MD2; /*!< CRYP Message Digest 2/PRNG Data 2 Register, Address offset: 0x54 */ + __I uint32_t MD3; /*!< CRYP Message Digest 3/PRNG Data 3 Register, Address offset: 0x58 */ + __I uint32_t MD4; /*!< CRYP Message Digest 4/PRNG Data 4 Register, Address offset: 0x5C */ + __IO uint32_t CTS_LEN; /*!< CRYP AES-CTS txt Length Register, Address offset: 0x60 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x64-0x6C */ + __IO uint32_t CRC_POLY; /*!< CRYP CRC Poly Register, Address offset: 0x70 */ + __IO uint32_t CRC_RESULT; /*!< CRYP CRC Result Register, Address offset: 0x74 */ + uint32_t RESERVED2[10]; /*!< Reserved, 0x78-0x9C */ + __I uint32_t MD5; /*!< CRYP SHA256 Message Digest Data 5 Register, Address offset: 0xA0 */ + __I uint32_t MD6; /*!< CRYP SHA256 Message Digest Data 6 Register, Address offset: 0xA4 */ + __I uint32_t MD7; /*!< CRYP SHA256 Message Digest Data 7 Register, Address offset: 0xA8 */ + uint32_t RESERVED3[85]; /*!< Reserved, 0xAC-0x1FC */ + __O uint32_t RXFIFO; /*!< CRYP RX FIFO input Register, Address offset: 0x200 */ + __I uint32_t TXFIFO; /*!< CRYP TX FIFO output Register, Address offset: 0x204 */ + +} CE_T; + +#define CE ((CE_T *)CE_BASE) + +/* + * @brief SPI Global Control Register + */ +#define CE_CTL_CRC_XOR_OUT_SHIFT (31) +#define CE_CTL_CRC_XOR_OUT_MASK (0x1U << CE_CTL_CRC_XOR_OUT_SHIFT) + +#define CE_CTL_CRC_REF_OUT_SHIFT (30) +#define CE_CTL_CRC_REF_OUT_MASK (0x1U << CE_CTL_CRC_REF_OUT_SHIFT) + +#define CE_CTL_CRC_REF_IN_SHIFT (29) +#define CE_CTL_CRC_REF_IN_MASK (0x1U << CE_CTL_CRC_REF_IN_SHIFT) + +#define CE_CTL_CRC_INIT_SHIFT (28) +#define CE_CTL_CRC_INIT_MASK (0x1U << CE_CTL_CRC_INIT_SHIFT) + +#define CE_CTL_KEY_SEL_SHIFT (24) +#define CE_CTL_KEY_SEL_MASK (0xFU << CE_CTL_KEY_SEL_SHIFT) +typedef enum { + CE_CTL_KEYSOURCE_INPUT = 0 << CE_CTL_KEY_SEL_SHIFT, /*!< key from input(normal mode) */ + CE_CTL_KEYSOURCE_SID = 1 << CE_CTL_KEY_SEL_SHIFT, /*!< key from SID */ + CE_CTL_KEYSOURCE_INTERNAL0 = 3 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL1 = 4 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL2 = 5 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL3 = 6 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL4 = 7 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL5 = 8 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL6 = 9 << CE_CTL_KEY_SEL_SHIFT, /*!< Not support for now */ + CE_CTL_KEYSOURCE_INTERNAL7 = 10 << CE_CTL_KEY_SEL_SHIFT /*!< Not support for now */ +} CE_CTL_KeySource; + +#define CE_CTL_PRNG_MODE_SHIFT (15) +#define CE_CTL_PRNG_MODE_MASK (0x1U << CE_CTL_PRNG_MODE_SHIFT) + +#define CE_CTL_CRC_CONT_SHIFT (15) +#define CE_CTL_CRC_CONT_MASK (0x1U << CE_CTL_CRC_CONT_SHIFT) + +#define CE_CTL_IV_MODE_SHIFT (14) +#define CE_CTL_IV_MODE_MASK (0x1U << CE_CTL_IV_MODE_SHIFT) +typedef enum { + CE_CTL_IVMODE_SHA_MD5_FIPS180 = 0 << CE_CTL_IV_MODE_SHIFT, /*!< IV in FIPS-180 defined */ + CE_CTL_IVMODE_SHA_MD5_INPUT = 1 << CE_CTL_IV_MODE_SHIFT /*!< IV from input */ +} CE_CTL_IvMode_SHA_MD5; + +#define CE_CTL_OP_MODE_SHIFT (12) +#define CE_CTL_OP_MODE_MASK (0x3U << CE_CTL_OP_MODE_SHIFT) +typedef enum { + CE_CTL_CRYPT_MODE_ECB = 0 << CE_CTL_OP_MODE_SHIFT, /*!< Crypto mode: ECB mode */ + CE_CTL_CRYPT_MODE_CBC = 1 << CE_CTL_OP_MODE_SHIFT, /*!< Crypto mode: CBC mode */ + CE_CTL_CRYPT_MODE_CTR = 2 << CE_CTL_OP_MODE_SHIFT, /*!< Crypto mode: CTR mode, only AES can support */ + CE_CTL_CRYPT_MODE_CTS = 3 << CE_CTL_OP_MODE_SHIFT /*!< Crypto mode: CTS mode, not support for now */ +} CE_CTL_Crypto_Mode; + +#define CE_CTL_CTR_WIDTH_SHIFT (10) +#define CE_CTL_CTR_WIDTH_MASK (0x3U << CE_CTL_CTR_WIDTH_SHIFT) +typedef enum { + CE_CTL_CTRWITDH_16BITS = 0 << CE_CTL_CTR_WIDTH_SHIFT, /*!< CTR mode counter size: 16 bits */ + CE_CTL_CTRWITDH_32BITS = 1 << CE_CTL_CTR_WIDTH_SHIFT, /*!< CTR mode counter size: 32 bits */ + CE_CTL_CTRWITDH_64BITS = 2 << CE_CTL_CTR_WIDTH_SHIFT, /*!< CTR mode counter size: 64 bits */ + CE_CTL_CTRWITDH_128BITS = 3 << CE_CTL_CTR_WIDTH_SHIFT /*!< CTR mode counter size: 128 bits */ +} CE_CTL_CtrWidth; + +#define CE_CTL_AES_KEY_SIZE_SHIFT (8) +#define CE_CTL_AES_KEY_SIZE_MASK (0x3U << CE_CTL_AES_KEY_SIZE_SHIFT) +typedef enum { + CE_CTL_AES_KEYSIZE_128BITS = 0 << CE_CTL_AES_KEY_SIZE_SHIFT, /*!< AES type: AES128 */ + CE_CTL_AES_KEYSIZE_192BITS = 1 << CE_CTL_AES_KEY_SIZE_SHIFT, /*!< AES type: AES192 */ + CE_CTL_AES_KEYSIZE_256BITS = 2 << CE_CTL_AES_KEY_SIZE_SHIFT /*!< AES type: AES256 */ +} CE_CTL_AES_KeySize; + +#define CE_CTL_OP_DIR_SHIFT (7) +#define CE_CTL_OP_DIR_MASK (0x1U << CE_CTL_OP_DIR_SHIFT) +typedef enum { + CE_CRYPT_OP_ENCRYPTION = 0 << CE_CTL_OP_DIR_SHIFT, /*!< Encryption operation */ + CE_CRYPT_OP_DECRYPTION = 1 << CE_CTL_OP_DIR_SHIFT /*!< Decryption operation */ +} CE_Crypto_Op; + +#define CE_CTL_METHOD_SHIFT (4) +#define CE_CTL_METHOD_MASK (0x7U << CE_CTL_METHOD_SHIFT) +typedef enum { + CE_CTL_METHOD_AES = 0 << CE_CTL_METHOD_SHIFT, /*!< AES */ + CE_CTL_METHOD_DES = 1 << CE_CTL_METHOD_SHIFT, /*!< DES */ + CE_CTL_METHOD_3DES = 2 << CE_CTL_METHOD_SHIFT, /*!< 3DES */ + CE_CTL_METHOD_SHA1 = 3 << CE_CTL_METHOD_SHIFT, /*!< SHA1 */ + CE_CTL_METHOD_MD5 = 4 << CE_CTL_METHOD_SHIFT, /*!< MD5 */ + CE_CTL_METHOD_PRNG = 5 << CE_CTL_METHOD_SHIFT, /*!< PRNG */ + CE_CTL_METHOD_SHA256 = 6 << CE_CTL_METHOD_SHIFT, /*!< SHA256 */ + CE_CTL_METHOD_CRC = 7 << CE_CTL_METHOD_SHIFT /*!< CRC */ +} CE_CTL_Method; + +#define CE_CTL_CRC_WIDTH_SHIFT (3) +#define CE_CTL_CRC_WIDTH_MASK (0x1U << CE_CTL_CRC_WIDTH_SHIFT) +typedef enum { + CE_CTL_CRC_WIDTH_16BITS = 0 << CE_CTL_CRC_WIDTH_SHIFT, /*!< CRC type: 16bits CRC */ + CE_CTL_CRC_WIDTH_32BITS = 1 << CE_CTL_CRC_WIDTH_SHIFT /*!< CRC type: 32bits CRC */ +} CE_CTL_CRC_Width; + +#define CE_CTL_END_BIT_SHIFT (2) +#define CE_CTL_END_BIT_MASK (0x1U << CE_CTL_END_BIT_SHIFT) + +#define CE_CTL_PRNG_START_SHIFT (1) +#define CE_CTL_PRNG_START_MASK (0x1U << CE_CTL_PRNG_START_SHIFT) + +#define CE_CTL_ENABLE_SHIFT (0) +#define CE_CTL_ENABLE_MASK (0x1U << CE_CTL_ENABLE_SHIFT) + + +#define CE_FCSR_RXFIFO_STATUS_SHIFT (30) +#define CE_FCSR_RXFIFO_STATUS_MASK (0x1U << CE_FCSR_RXFIFO_STATUS_SHIFT) + +#define CE_FCSR_RXFIFO_EMP_CNT_SHIFT (24) +#define CE_FCSR_RXFIFO_EMP_CNT_MASK (0x3FU << CE_FCSR_RXFIFO_EMP_CNT_SHIFT) +#define CE_FCSR_RXFIFO_EMP_CNT_VMASK (0x3FU) + +#define CE_FCSR_TXFIFO_STATUS_SHIFT (22) +#define CE_FCSR_TXFIFO_STATUS_MASK (0x1U << CE_FCSR_TXFIFO_STATUS_SHIFT) + +#define CE_FCSR_TXFIFO_AVA_CNT_SHIFT (16) +#define CE_FCSR_TXFIFO_AVA_CNT_MASK (0x3FU << CE_FCSR_TXFIFO_AVA_CNT_SHIFT) +#define CE_FCSR_TXFIFO_AVA_CNT_VMASK (0x3FU) + +#define CE_FCSR_RXFIFO_INT_TRIG_LEVEL_SHIFT (8) +#define CE_FCSR_RXFIFO_INT_TRIG_LEVEL_MASK (0x1FU << CE_FCSR_RXFIFO_INT_TRIG_LEVEL_SHIFT) + +#define CE_FCSR_TXFIFO_INT_TRIG_LEVEL_SHIFT (0) +#define CE_FCSR_TXFIFO_INT_TRIG_LEVEL_MASK (0x1FU << CE_FCSR_TXFIFO_INT_TRIG_LEVEL_SHIFT) + + +#define CE_ICSR_HASH_CRC_END_SHIFT (11) +#define CE_ICSR_HASH_CRC_END_MASK (0x1U << CE_ICSR_HASH_CRC_END_SHIFT) + +#define CE_ICSR_RXFIFO_EMP_SHIFT (10) +#define CE_ICSR_RXFIFO_EMP_MASK (0x1U << CE_ICSR_RXFIFO_EMP_SHIFT) + +#define CE_ICSR_TXFIFO_AVA_SHIFT (8) +#define CE_ICSR_TXFIFO_AVA_MASK (0x1U << CE_ICSR_TXFIFO_AVA_SHIFT) + +#define CE_ICSR_DRQ_ENABLE_SHIFT (4) +#define CE_ICSR_DRQ_ENABLE_MASK (0x1U << CE_ICSR_DRQ_ENABLE_SHIFT) + +#define CE_ICSR_HASH_CRC_END_INT_EN_SHIFT (3) +#define CE_ICSR_HASH_CRC_END_INT_EN_MASK (0x1U << CE_ICSR_HASH_CRC_END_INT_EN_SHIFT) + +#define CE_ICSR_RXFIFO_EMP_INT_EN_SHIFT (2) +#define CE_ICSR_RXFIFO_EMP_INT_EN_MASK (0x1U << CE_ICSR_RXFIFO_EMP_INT_EN_SHIFT) + +#define CE_ICSR_TXFIFO_AVA_INT_EN_SHIFT (0) +#define CE_ICSR_TXFIFO_AVA_INT_EN_MASK (0x1U << CE_ICSR_TXFIFO_AVA_INT_EN_SHIFT) + + +#define CE_3DES_KEY_COUNT (6) +#define CE_DES_KEY_COUNT (2) + + +/************************ public **************************************/ +#define CE_WAIT_TIME (4000) + +/* + * @brief aes/des/3des + * @notice Only support ECB & CBC mode. CTR & CTS mode have hardware bug. + */ +typedef enum { + CE_CRYPT_MODE_ECB = CE_CTL_CRYPT_MODE_ECB, /*!< Crypto Mode: ECB mode */ + CE_CRYPT_MODE_CBC = CE_CTL_CRYPT_MODE_CBC /*!< Crypto Mode: CBC mode */ +} CE_Crypto_Mode; + +typedef CE_CTL_KeySource CE_Crypto_KeySrc; +typedef CE_CTL_AES_KeySize CE_AES_KeySize; + +#define AES_BLOCK_SIZE (16) +#define DES_BLOCK_SIZE (8) +#define DES3_BLOCK_SIZE (8) + +typedef struct { + struct { + CE_Crypto_Mode mode; /*!< ECB & CBC */ + struct { + uint8_t iv[16]; /*!< initialization value, same as a block size which is 16 bytes */ +#ifdef CE_CTR_MODE + uint8_t cnt[16]; +#endif + }; +#ifdef CE_CTR_MODE + CE_CTL_CtrWidth width; +#endif + }; + + struct { + CE_Crypto_KeySrc src; /*!< key source */ + uint8_t key[32]; /*!< key */ + CE_CTL_AES_KeySize keysize; /*!< AES key size according to AES type like AES128 */ + }; +} CE_AES_Config; + +typedef struct { + struct { + CE_Crypto_Mode mode; /*!< ECB & CBC */ + union { + uint8_t iv[8]; /*!< initialization value, same as a block size which is 8 bytes */ +#ifdef CE_CTR_MODE + uint8_t cnt[8]; +#endif + }; +#ifdef CE_CTR_MODE + CE_CTL_CtrWidth width; +#endif + }; + + struct { + CE_Crypto_KeySrc src; /*!< key source */ + uint8_t key[8]; /*!< key */ + }; +} CE_DES_Config; + +typedef struct { + struct { + CE_Crypto_Mode mode; /*!< ECB & CBC */ + union { + uint8_t iv[8]; /*!< initialization value, same as a block size which is 8 bytes */ +#ifdef CE_CTR_MODE + uint8_t cnt[8]; +#endif + }; +#ifdef CE_CTR_MODE + CE_CTL_CtrWidth width; +#endif + }; + + struct { + CE_Crypto_KeySrc src; /*!< key source */ + uint8_t key[24]; /*!< key */ + }; +} CE_3DES_Config; + + +typedef struct { + uint8_t word[4]; + uint8_t word_size; +} CE_Fifo_Align; + +/* + * @brief crc + */ +typedef enum { + CE_CRC16_IBM, /*!< x16+x15+x2+1, poly 0x8005, init 0x0000, refin-true, refout-true, xorout-0x0000 */ + CE_CRC16_MAXIM, /*!< x16+x15+x2+1, poly 0x8005, init 0x0000, refin-true, refout-true, xorout-0xffff */ + CE_CRC16_USB, /*!< x16+x15+x2+1, poly 0x8005, init 0xffff, refin-true, refout-true, xorout-0xffff */ + CE_CRC16_MODBUS, /*!< x16+x15+x2+1, poly 0x8005, init 0xffff, refin-true, refout-true, xorout-0x0000 */ + CE_CRC16_CCITT, /*!< x16+x15+x5+1, poly 0x1021, init 0x0000, refin-true, refout-true, xorout-0x0000 */ + CE_CRC16_CCITT_1, /*!< x16+x15+x5+1, poly 0x1021, init 0xffff, refin-false, refout-false, xorout-0x0000 */ + CE_CRC16_X25, /*!< x16+x15+x5+1, poly 0x1021, init 0xffff, refin-true, refout-true, xorout-0xffff */ + CE_CRC16_XMODEM, /*!< x16+x15+x5+1, poly 0x1021, init 0x0000, refin-false, refout-false, xorout-0x0000 */ + CE_CRC16_DNP, /*!< x16+x13+x12+x11+x10+x8+x6+x5+x2+1, poly 0x3d65, init 0x0000, refin-true, refout-true, xorout-0xffff */ + CE_CRC32, /*!< x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1, poly 0x04c11db7, init 0xffffffff, refin-true, refout-true, xorout-0xffffffff */ + CE_CRC32_MPEG2, /*!< x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1, poly 0x04c11db7, init 0xffffffff, refin-false, refout-false, xorout-0x00000000 */ +} CE_CRC_Types; + +typedef struct { + uint64_t total_size; + struct { + uint8_t word[4]; + uint8_t word_size; + }; + + CE_CRC_Types type; + uint32_t crc; +} CE_CRC_Handler; + +/* + * @brief md5/sha1/sha256 + */ +typedef CE_CTL_IvMode_SHA_MD5 CE_Hash_IVsrc; + +#define CE_MD5_IV_SIZE (4) +#define CE_SHA1_IV_SIZE (5) +#define CE_SHA256_IV_SIZE (8) + +typedef struct { + uint64_t total_size; + struct { + uint8_t word[4]; + uint8_t word_size; + }; +} CE_MD5_Handler, CE_SHA1_Handler, CE_SHA256_Handler; + + +/********************************** Public Interface *************************************/ +HAL_Status HAL_CE_Init(); +HAL_Status HAL_CE_Deinit(); + +HAL_Status HAL_AES_Encrypt(CE_AES_Config *aes, uint8_t *plain, uint8_t *cipher, uint32_t size); +HAL_Status HAL_AES_Decrypt(CE_AES_Config *aes, uint8_t *cipher, uint8_t *plain, uint32_t size); + +HAL_Status HAL_DES_Encrypt(CE_DES_Config *des, uint8_t *plain, uint8_t *cipher, uint32_t size); +HAL_Status HAL_DES_Decrypt(CE_DES_Config *des, uint8_t *cipher, uint8_t *plain, uint32_t size); + +HAL_Status HAL_3DES_Encrypt(CE_3DES_Config *des, uint8_t *plain, uint8_t *cipher, uint32_t size); +HAL_Status HAL_3DES_Decrypt(CE_3DES_Config *des, uint8_t *cipher, uint8_t *plain, uint32_t size); + +HAL_Status HAL_CRC_Init(CE_CRC_Handler *hdl, CE_CRC_Types type, uint32_t total_size); +HAL_Status HAL_CRC_Append(CE_CRC_Handler *hdl, uint8_t *data, uint32_t size); +HAL_Status HAL_CRC_Finish(CE_CRC_Handler *hdl, uint32_t *crc); + +HAL_Status HAL_MD5_Init(CE_MD5_Handler *hdl, CE_Hash_IVsrc src, uint32_t iv[4]); +HAL_Status HAL_MD5_Append(CE_MD5_Handler *hdl, uint8_t *data, uint32_t size); +HAL_Status HAL_MD5_Finish(CE_MD5_Handler *hdl, uint32_t digest[4]); + +HAL_Status HAL_SHA1_Init(CE_SHA1_Handler *hdl, CE_Hash_IVsrc src, uint32_t iv[5]); +HAL_Status HAL_SHA1_Append(CE_SHA1_Handler *hdl, uint8_t *data, uint32_t size); +HAL_Status HAL_SHA1_Finish(CE_SHA1_Handler *hdl, uint32_t digest[5]); + +HAL_Status HAL_SHA256_Init(CE_SHA256_Handler *hdl, CE_Hash_IVsrc src, uint32_t iv[8]); +HAL_Status HAL_SHA256_Append(CE_SHA256_Handler *hdl, uint8_t *data, uint32_t size); +HAL_Status HAL_SHA256_Finish(CE_SHA256_Handler *hdl, uint32_t digest[8]); + +HAL_Status HAL_PRNG_Generate(uint8_t *random, uint32_t size); + + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_CRYPTO_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_csi.h b/platform/mcu/xr871/include/driver/chip/hal_csi.h new file mode 100644 index 0000000000..f38c751b65 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_csi.h @@ -0,0 +1,230 @@ +/** + * @file hal_csi.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_CSI_H_ +#define _DRIVER_CHIP_HAL_CSI_H_ + +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_ccm.h" +#include "driver/chip/hal_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The register for CSI. + */ +typedef struct { + __IO uint32_t CSI_EN_REG; /*!< 0x00 CSI enable register*/ + __IO uint32_t CSI_CFG_REG; /*!< 0x04 CSI configuration register*/ + __IO uint32_t CSI_CAP_REG; /*!< 0x08 CSI capture control register*/ + __IO uint32_t CSI_SCALE_REG; /*!< 0x0c CSI scale */ + uint32_t RESERVED1[6]; + __IO uint32_t CSI_BUF_CTL_REG; /*!< 0x28 CSI output buffer control register*/ + __IO uint32_t CSI_BUF_STA_REG; /*!< 0x2c CSI status register*/ + __IO uint32_t CSI_INT_EN_REG; /*!< 0x30 CSI interrupt enable register*/ + __IO uint32_t CSI_INT_STA_REG; /*!< 0x34 CSI interrupt size register*/ + uint32_t RESERVED2[2]; + __IO uint32_t CSI_HSIZE_REG; /*!< 0x40 CSI horizontal size register*/ + uint32_t RESERVED3[1]; + __IO uint32_t CSI_BF_LEN_REG; /*!< 0x48 CSI line buffer length register*/ + __IO uint32_t CSI_TRUE_DATA_NUM;/*!< 0x4c CSI true data number of fifo sram register*/ + __IO uint32_t CSI_JPEG_MOD_SEL; /*!< 0x50 CSI JPEG Mode select register*/ +}CSI_T ; + + +#define CSI ((CSI_T *)DCMI_BASE) + +#define CSI_FIFO_A (DCMI_BASE + 0X800) +#define CSI_FIFO_B (DCMI_BASE + 0XA00) + +#define CSI_EN HAL_BIT(0) +#define CSI_CFG_INPUT_FORMAT ((uint32_t)0x00700000) +#define CSI_CFG_SYNC_SIGNAL_POL ((uint32_t)0x00000007) +#define CSI_CAP_MODE ((uint32_t)0x00000003) + +#define CSI_VER_MASK ((uint32_t)0x0F000000) +#define CSI_HER_MASK ((uint32_t)0x000000FF) + +#define LUM_STATIS ((uint32_t)0xFFFFFF00) + +#define CSI_INTERRUPT_CLEAR ((uint32_t)0x000003FF) + +#define CSI_SIZE_REG ((uint32_t)0xFFFFFFFF) + +#define CSI_LUM_LEN ((uint32_t)0x00001FFF) +#define CSI_VALID_DATA_LEN ((uint32_t)0x000003FF) + +/** + * @brief Set CSI clock. + */ +typedef struct { + CCM_AHBPeriphClkSrc clk; /*!< The source clock for CSI */ + CCM_PeriphClkDivN divN; /*!< CSI sourec clock division */ + CCM_PeriphClkDivM divM; /*!< CSI sourec clock division + The division result = divN * divM*/ +} CSI_Clk; + +/** + * @brief CSI clock configure. + */ +typedef struct { + CSI_Clk src_Clk; /*!< Set CSI clock */ +} CSI_Config; + +/** + * @brief Enable or disable func. + */ +typedef enum { + CSI_DISABLE, /*!< Enable*/ + CSI_ENABLE, /*!< Disable*/ +}CSI_CTRL; + +/** + * @brief Sync signal polarity. + */ +typedef enum { + CSI_NEGATIVE, /*!< Negative*/ + CSI_POSITIVE, /*!< Positive*/ +}CSI_SYNC_SIGNAL_POLARITY; + +/** + * @brief Configure CSI sync signal polarity. + */ +typedef struct { + CSI_SYNC_SIGNAL_POLARITY vsync; /*!< Set the polarity for vsync signal */ + CSI_SYNC_SIGNAL_POLARITY herf; /*!< Set the polarity for herf signal */ + CSI_SYNC_SIGNAL_POLARITY p_Clk; /*!< Set the polarity for pclk signal */ +} CSI_Sync_Signal; + +/** + * @brief CSI capture mode. + */ +typedef enum { + CSI_STILL_MODE, /*!< Capture one picture;When a picturee capture done, you need restart capture */ + CSI_VIDEO_MODE, /*!< Continuous capture of images, shoot video*/ +} CSI_CAPTURE_MODE; + +/** + * @brief The FIFO used for cache data. + */ +typedef enum { + CSI_FIFO_0_A, /*!< FIFO A */ + CSI_FIFO_0_B, /*!< FIFO B */ +}CSI_FIFO; + +/** + * @brief CSI module status. + */ +typedef enum { + CSI_FREE, /*!< The CSI module is free*/ + CSI_BUSY, /*!< The CSI module is running*/ +} CSI_RUN_STA; + +/** + * @brief CSI moudle Current operating status + */ +typedef struct { + uint32_t luminance; /*!< luminance statistics*/ + CSI_RUN_STA video_Mode; /*!< video mode status*/ + CSI_RUN_STA still_Mode; /*!< still mode status*/ +} CSI_Status; + +/** + * @brief Sets the size of the captured image. + */ +typedef struct { + uint16_t hor_start; /*!< Start capture position, unit byte.*/ + uint16_t hor_len; /*!< The picture one row contains the number of data(not number of pixel), unit byte.*/ +} CSI_Picture_Size; + + +/** + * @brief The CSI interrupt flag. + */ +typedef enum { + CSI_CAPTURE_DONE_IRQ = HAL_BIT(0), /*!< When the picture capture done, trigger this flag.*/ + CSI_FRAME_DONE_IRQ = HAL_BIT(1), /*!< When capture the frame done signal, trigger this flag.*/ + CSI_FIFO_0_OVERFLOW_IRQ = HAL_BIT(2), /*!< When FIFO is overflow, trigger this flag.*/ + CSI_ALL_FIFO_OVERFLOW_IRQ = HAL_BIT(6), /*!< When all FIFO is overflow, trigger this flag.*/ + CSI_VSYNC_IRQ = HAL_BIT(7), /*!< When capture the vsync signal, trigger this flag.*/ + CSI_FIFO_0_A_READY_IRQ = HAL_BIT(8), /*!< The CSI_FIFO_A is ready for read, trigger this flag.*/ + CSI_FIFO_0_B_READY_IRQ = HAL_BIT(9), /*!< The CSI_FIFO_B is ready for read, trigger this flag.*/ +} CSI_INTERRUPT_SIGNAL; + +/** + * @brief The number of bytes in the FIFO. + */ +typedef struct { + uint16_t FIFO_0_A_Data_Len; /*!< The number of bytes in the FIFO_A.*/ + uint16_t FIFO_0_B_Data_Len; /*!< The number of bytes in the FIFO_B.*/ +}CSI_FIFO_Data_Len; + +/** + * @brief Callback. + */ +typedef struct { + void *arg; + void(*callBack)(void *arg); +}CSI_Call_Back; + +HAL_Status HAL_CSI_Config(CSI_Config *param); +void HAL_CSI_DeInit(void); + +void HAL_CSI_Sync_Signal_Polarity_Cfg(CSI_Sync_Signal *signal); +void HAL_CSI_Capture_Enable(CSI_CAPTURE_MODE mode , CSI_CTRL ctrl); +void HAL_CSI_Interval_Capture_Cfg(uint8_t ver_mask, uint16_t hor_mask); + +void HAL_CSI_Selection_Next_FIFO (CSI_FIFO fifo_num); +CSI_FIFO HAL_CSI_Current_FIFO(); +void HAL_CSI_Double_FIFO_Mode_Enable(CSI_CTRL ctrl); + +CSI_Status HAL_CSI_Status(); +void HAL_CSI_Interrupt_Cfg(CSI_INTERRUPT_SIGNAL irq_signel, CSI_CTRL ctrl); +__IO uint32_t HAL_CSI_Interrupt_Sta(); +void HAL_CSI_Interrupt_Clear(); + +HAL_Status HAL_CSI_Set_Picture_Size(CSI_Picture_Size *size); +CSI_FIFO_Data_Len HAL_CSI_FIFO_Data_Len(); +void HAL_CIS_JPEG_Mode_Enable(CSI_CTRL ctrl); +void HAL_CSI_Interrupt_Enable(CSI_Call_Back *cb, CSI_CTRL ctrl); +void HAL_CSI_Moudle_Enalbe(CSI_CTRL ctrl); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_CSI_H_ */ + diff --git a/platform/mcu/xr871/include/driver/chip/hal_def.h b/platform/mcu/xr871/include/driver/chip/hal_def.h new file mode 100644 index 0000000000..c851111f2e --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_def.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_DEF_H_ +#define _DRIVER_CHIP_HAL_DEF_H_ + +#include "driver/chip/chip.h" +#include "kernel/os/os_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Bitwise operation + */ +#define HAL_BIT(pos) (1U << (pos)) + +#define HAL_SET_BIT(reg, mask) ((reg) |= (mask)) +#define HAL_CLR_BIT(reg, mask) ((reg) &= ~(mask)) +#define HAL_GET_BIT(reg, mask) ((reg) & (mask)) +#define HAL_GET_BIT_VAL(reg, shift, vmask) (((reg) >> (shift)) & (vmask)) + +#define HAL_MODIFY_REG(reg, clr_mask, set_mask) \ + ((reg) = (((reg) & (~(clr_mask))) | (set_mask))) + +/* + * Macros for accessing LSBs of a 32-bit register (little endian only) + */ +#define HAL_REG_32BIT(reg_addr) (*((__IO uint32_t *)(reg_addr))) +#define HAL_REG_16BIT(reg_addr) (*((__IO uint16_t *)(reg_addr))) +#define HAL_REG_8BIT(reg_addr) (*((__IO uint8_t *)(reg_addr))) + +/* Macro for counting the element number of an array */ +#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0])) + +/* Wait forever timeout value */ +#define HAL_WAIT_FOREVER OS_WAIT_FOREVER + +/** + * @brief HAL Status value + */ +typedef enum +{ + HAL_OK = 0, /* success */ + HAL_ERROR = -1, /* general error */ + HAL_BUSY = -2, /* device or resource busy */ + HAL_TIMEOUT = -3, /* wait timeout */ + HAL_INVALID = -4 /* invalid argument */ +} HAL_Status; + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_DEF_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_dma.h b/platform/mcu/xr871/include/driver/chip/hal_dma.h new file mode 100644 index 0000000000..43044f08c5 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_dma.h @@ -0,0 +1,276 @@ +/** + * @file hal_dma.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_DMA_H_ +#define _DRIVER_CHIP_HAL_DMA_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Options of supporting DMA half transfer complete IRQ */ +#define HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT 1 + +/** + * @brief DMA channel definition + */ +typedef enum { + DMA_CHANNEL_0 = 0U, + DMA_CHANNEL_1 = 1U, + DMA_CHANNEL_2 = 2U, + DMA_CHANNEL_3 = 3U, + DMA_CHANNEL_4 = 4U, + DMA_CHANNEL_5 = 5U, + DMA_CHANNEL_6 = 6U, + DMA_CHANNEL_7 = 7U, + DMA_CHANNEL_NUM = 8U, + DMA_CHANNEL_INVALID = DMA_CHANNEL_NUM +} DMA_Channel; + +/** + * @brief DMA channel register block structure + */ +typedef struct +{ + __IO uint32_t CTRL; /* offset: 0x00, DMA channel configuration register */ + __IO uint32_t SRC_ADDR; /* offset: 0x04, DMA channel source address register */ + __IO uint32_t DST_ADDR; /* offset: 0x08, DMA channel destination address register */ + __IO uint32_t BYTE_CNT; /* offset: 0x0C, DMA channel byte counter register */ + uint32_t RESERVED0[4]; +} DMA_CHANNEL_T; + +/** + * @brief DMA register block structure + */ +typedef struct +{ + __IO uint32_t IRQ_EN; /* offset: 0x00, DMA IRQ enable register */ + __IO uint32_t IRQ_STATUS; /* offset: 0x04, DMA IRQ status register */ + uint32_t RESERVED0[62]; + DMA_CHANNEL_T CHANNEL[DMA_CHANNEL_NUM]; /* offset: 0x100, DMA channels register blocks */ +} DMA_T; + +#define DMA ((DMA_T *)DMA_BASE) /* address: 0x40001000 */ + +/* + * Bit field definition of + * - DMA->IRQ_EN + * - DMA->IRQ_STATUS + */ +#define DMA_IRQ_TYPE_VMASK 0x3U +typedef enum { +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + DMA_IRQ_TYPE_HALF = HAL_BIT(0), +#endif + DMA_IRQ_TYPE_END = HAL_BIT(1), +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + DMA_IRQ_TYPE_BOTH = HAL_BIT(0) | HAL_BIT(1), +#endif +} DMA_IRQType; + +/* + * Bit field definition of DMA->CHANNEL[x].CTRL + */ +#define DMA_START_BIT HAL_BIT(31) /* R/W */ +#define DMA_BUSY_BIT HAL_BIT(30) /* R */ + +#define DMA_WORK_MODE_SHIFT 29 /* R/W */ +#define DMA_WORK_MODE_VMASK 0x1U +typedef enum { + DMA_WORK_MODE_SINGLE = 0U, /* one-shot DMA transfer */ + DMA_WORK_MODE_CIRCULAR = 1U /* repeat DMA transfer */ +} DMA_WorkMode; + +#define DMA_WAIT_CYCLE_SHIFT 26 /* R/W */ +#define DMA_WAIT_CYCLE_VMASK 0x7U +typedef enum { + DMA_WAIT_CYCLE_1 = 0U, + DMA_WAIT_CYCLE_2 = 1U, + DMA_WAIT_CYCLE_4 = 2U, + DMA_WAIT_CYCLE_8 = 3U, + DMA_WAIT_CYCLE_16 = 4U, + DMA_WAIT_CYCLE_32 = 5U, + DMA_WAIT_CYCLE_64 = 6U, + DMA_WAIT_CYCLE_128 = 7U +} DMA_WaitCycle; /* waiting cycles between two burst transaction */ + +#define DMA_DATA_WIDTH_VMASK 0x3U +typedef enum { + DMA_DATA_WIDTH_8BIT = 0U, + DMA_DATA_WIDTH_16BIT = 1U, + DMA_DATA_WIDTH_32BIT = 2U +} DMA_DataWidth; + +#define DMA_BURST_LEN_VMASK 0x1U +typedef enum { + DMA_BURST_LEN_1 = 0U, + DMA_BURST_LEN_4 = 1U +} DMA_BurstLen; + +#define DMA_ADDR_MODE_VMASK 0x1U +typedef enum { + DMA_ADDR_MODE_INC = 0U, /* address is increased when DMA transferring */ + DMA_ADDR_MODE_FIXED = 1U /* address is not changed when DMA transferring */ +} DMA_AddrMode; + +#define DMA_PERIPH_VMASK 0x1F +typedef enum { + DMA_PERIPH_SRAM = 0U, + DMA_PERIPH_SPI0 = 1U, + DMA_PERIPH_SPI1 = 2U, + DMA_PERIPH_UART0 = 3U, + DMA_PERIPH_UART1 = 4U, + DMA_PERIPH_CE = 5U, + DMA_PERIPH_DAUDIO = 6U, + DMA_PERIPH_FLASHC = 7U, + DMA_PERIPH_DMIC = 8U +} DMA_Periph; + +#define DMA_BYTE_CNT_MODE_SHIFT 15 /* R/W */ +#define DMA_BYTE_CNT_MODE_VMASK 0x1U +typedef enum { + DMA_BYTE_CNT_MODE_NORMAL = 0U, /* DMA->CHANNEL[x].BYTE_CNT is the data length of the DAM transfer */ + DMA_BYTE_CNT_MODE_REMAIN = 1U /* DMA->CHANNEL[x].BYTE_CNT is the length of the remaining data not transferred */ +} DMA_ByteCntMode; + +#define DMA_DST_DATA_WIDTH_SHIFT 24 /* R/W */ +#define DMA_DST_BURST_LEN_SHIFT 23 /* R/W */ +#define DMA_DST_ADDR_MODE_SHIFT 21 /* R/W */ +#define DMA_DST_PERIPH_SHIFT 16 /* R/W */ +#define DMA_SRC_DATA_WIDTH_SHIFT 8 /* R/W */ +#define DMA_SRC_BURST_LEN_SHIFT 7 /* R/W */ +#define DMA_SRC_ADDR_MODE_SHIFT 5 /* R/W */ +#define DMA_SRC_PERIPH_SHIFT 0 + +/* DMA->CHANNEL[x].SRC_ADDR */ + +/* DMA->CHANNEL[x].DST_ADDR */ + +/* DMA->CHANNEL[x].BYTE_CNT */ +#define DMA_BYTE_CNT_VMASK 0x3FFFF + +/* Maximum data length of one DMA transfer */ +#define DMA_DATA_MAX_LEN (128 * 1024U) + +/******************************************************************************/ + +/** @brief Type define of DMA IRQ callback function */ +typedef void (*DMA_IRQCallback)(void *arg); + +/** + * @brief DMA channel initialization parameters + */ +typedef struct { + uint32_t cfg; /* created by HAL_DMA_MakeInitCfg() */ + + DMA_IRQType irqType; /* DMA IRQ type to be enabled */ + DMA_IRQCallback endCallback; /* DMA transfer complete callback fucntion */ + void *endArg; /* argument of DMA transfer complete callback fucntion */ +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + DMA_IRQCallback halfCallback; /* DMA half transfer complete callback fucntion */ + void *halfArg; /* argument of DMA half transfer complete callback fucntion */ +#endif +} DMA_ChannelInitParam; + +/** + * @brief Make configuration value for DMA_ChannelInitParam::cfg + * @param[in] workMode DMA transfer working mode + * @param[in] waitCycle Waiting cycles between two DMA burst transaction + * @param[in] byteCntMode DMA byte count mode + * @arg DMA_BYTE_CNT_MODE_NORMAL In normal mode, DMA->CHANNEL[x].BYTE_CNT is + * not changed in the whole DMA transfer, and + * its value is the data length of the DAM + * transfer. + * @arg DMA_BYTE_CNT_MODE_REMAIN In remaining mode, DMA->CHANNEL[x].BYTE_CNT + * is decreased when DMA transferring, and its + * value is the length of the remaining data + * not transferred. + * @param[in] dstDataWidth Destination DMA transaction data width + * @param[in] dstBurstLen Destination DMA transaction burst length + * @param[in] dstAddrMode Destination DMA address mode + * @param[in] dstPeriph Destination DMA peripheral type + * @param[in] srcDataWidth Source DMA transaction data width + * @param[in] srcBurstLen Source DMA transaction burst length + * @param[in] srcAddrMode Source DMA address mode + * @param[in] srcPeriph Source DMA peripheral type + * @return configuration value for DMA_ChannelInitParam::cfg + * + * @note + * - A DMA transaction is not interruptible + * - A DMA transaction data length = data width * burst length + */ +__STATIC_INLINE uint32_t HAL_DMA_MakeChannelInitCfg(DMA_WorkMode workMode, + DMA_WaitCycle waitCycle, + DMA_ByteCntMode byteCntMode, + DMA_DataWidth dstDataWidth, + DMA_BurstLen dstBurstLen, + DMA_AddrMode dstAddrMode, + DMA_Periph dstPeriph, + DMA_DataWidth srcDataWidth, + DMA_BurstLen srcBurstLen, + DMA_AddrMode srcAddrMode, + DMA_Periph srcPeriph) +{ + return ((((uint32_t)workMode & DMA_WORK_MODE_VMASK) << DMA_WORK_MODE_SHIFT) | + (((uint32_t)waitCycle & DMA_WAIT_CYCLE_VMASK) << DMA_WAIT_CYCLE_SHIFT) | + (((uint32_t)byteCntMode & DMA_BYTE_CNT_MODE_VMASK) << DMA_BYTE_CNT_MODE_SHIFT) | + (((uint32_t)dstDataWidth & DMA_DATA_WIDTH_VMASK) << DMA_DST_DATA_WIDTH_SHIFT) | + (((uint32_t)dstBurstLen & DMA_BURST_LEN_VMASK) << DMA_DST_BURST_LEN_SHIFT) | + (((uint32_t)dstAddrMode & DMA_ADDR_MODE_VMASK) << DMA_DST_ADDR_MODE_SHIFT) | + (((uint32_t)dstPeriph & DMA_PERIPH_VMASK) << DMA_DST_PERIPH_SHIFT) | + (((uint32_t)srcDataWidth & DMA_DATA_WIDTH_VMASK) << DMA_SRC_DATA_WIDTH_SHIFT) | + (((uint32_t)srcBurstLen & DMA_BURST_LEN_VMASK) << DMA_SRC_BURST_LEN_SHIFT) | + (((uint32_t)srcAddrMode & DMA_ADDR_MODE_VMASK) << DMA_SRC_ADDR_MODE_SHIFT) | + (((uint32_t)srcPeriph & DMA_PERIPH_VMASK) << DMA_SRC_PERIPH_SHIFT)); +} + +DMA_Channel HAL_DMA_Request(void); +void HAL_DMA_Release(DMA_Channel chan); + +void HAL_DMA_Init(DMA_Channel chan, const DMA_ChannelInitParam *param); +void HAL_DMA_DeInit(DMA_Channel chan); + +void HAL_DMA_Start(DMA_Channel chan, uint32_t srcAddr, uint32_t dstAddr, uint32_t datalen); +void HAL_DMA_Stop(DMA_Channel chan); + +int HAL_DMA_IsBusy(DMA_Channel chan); +uint32_t HAL_DMA_GetByteCount(DMA_Channel chan); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_DMA_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_dmic.h b/platform/mcu/xr871/include/driver/chip/hal_dmic.h new file mode 100644 index 0000000000..cea09ee6ea --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_dmic.h @@ -0,0 +1,281 @@ +/** + * @file hal_dmic.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_DMIC_H_ +#define _DRIVER_CHIP_HAL_DMIC_H_ + +#include +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + __IO uint32_t DMIC_EN; /* DMIC enable control register Address offset: 0x0000 */ + __IO uint32_t DMIC_SR; /* DMIC sample rate register Adrress offset: 0x0004 */ + __IO uint32_t DMIC_CTR; /* DMIC control register Address offset: 0x0008 */ + __IO uint32_t RESERVED0; + __IO uint32_t DMIC_DATA; /* DMIC data register Address offset: 0x0010 */ + __IO uint32_t DMIC_INTC; /* DMIC interrupt control register Address offset: 0x0014 */ + __IO uint32_t DMIC_INTS; /* DMIC interrupt status register Address offset: 0x0018 */ + __IO uint32_t FIFO_CTR; /* DMIC FIFO control register Address offset: 0x001C */ + __I uint32_t FIFO_STA; /* DMIC FIFO status register Address offset: 0x0020 */ + __IO uint32_t CH_NUM; /* DMIC channel numbers register Address offset: 0x0024 */ + __IO uint32_t CH_MAP; /* DMIC channel mapping register Address offset: 0x0028 */ + __IO uint32_t DMIC_CNT; /* DMIC counter register Address offset: 0x002C */ + __IO uint32_t DATA0_DATA1_VOL_CTR; /* DATA0 and DATA1 volume control register Address offset: 0x0030 */ + __IO uint32_t DATA2_DATA3_VOL_CTR; /* High pass filter enable control register Address offset: 0x0034 */ + __IO uint32_t HPF_EN_CTR; /**/ + __IO uint32_t HPF_COEF_REG; /* High pass filter coef register Address offset: 0x003C */ + __IO uint32_t HPF_GAIN_REG; /* High pass filter gain register Address offset: 0x0040 */ +} DMIC_T; + +#define DMIC ((DMIC_T *)DMIC_BASE) + +/* + * Bits definition for DMIC_ECR register(0x0000) + */ +#define DMIC_ECR_DATA0_CHL_EN_BIT HAL_BIT(0) +#define DMIC_ECR_DATA0_CHR_EN_BIT HAL_BIT(1) +#define DMIC_ECR_DATA1_CHL_EN_BIT HAL_BIT(2) +#define DMIC_ECR_DATA1_CHR_EN_BIT HAL_BIT(3) +#define DMIC_ECR_DATA2_CHL_EN_BIT HAL_BIT(4) +#define DMIC_ECR_DATA2_CHR_EN_BIT HAL_BIT(5) +#define DMIC_ECR_DATA3_CHL_EN_BIT HAL_BIT(6) +#define DMIC_ECR_DATA3_CHR_EN_BIT HAL_BIT(7) +#define DMIC_ECR_GLOBE_EN HAL_BIT(8) + +/* + * Bits definition for DMIC_SRR register (0x0004) + */ +#define DMIC_SR_SHIFT (0) +#define DMIC_SR_MASK (0x7U << DMIC_SR_SHIFT) + +/** + * @brief Dmic sample rate definition + */ +typedef enum { + DMIC_SR48KHZ = (0X0U << DMIC_SR_SHIFT), + DMIC_SR44KHZ = (0X8U << DMIC_SR_SHIFT),/*44100*/ + DMIC_SR24KHZ = (0X2U << DMIC_SR_SHIFT), + DMIC_SR22KHZ = (0X9U << DMIC_SR_SHIFT),/*22050*/ + DMIC_SR12KHZ = (0X4U << DMIC_SR_SHIFT), + DMIC_SR11KHZ = (0XaU << DMIC_SR_SHIFT),/*11025*/ + DMIC_SR32KHZ = (0X1U << DMIC_SR_SHIFT), + DMIC_SR16KHZ = (0X3U << DMIC_SR_SHIFT), + DMIC_SR8KHZ = (0X5U << DMIC_SR_SHIFT), +} DMIC_SampleRate; + +/* + * Bits definition for DMIC_CTLR register (0X0008) + */ +#define DMIC_CTLR_OVERSAMPLE_RATE_SHIFT (0) +#define DMIC_CTLR_OVERSAMPLE_RATE_MASK (0x1U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT) +typedef enum { + DMIC_CTLR_OVERSAMPLE_RATE64 = (0X1U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT), + DMIC_CTLR_OVERSAMPLE_RATE128 = (0X0U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT), +} DMIC_OverSampleRate; + +#define DMIC_CTLR_DATA0_SWAP_BIT HAL_BIT(4) /* bit4, data0 left data and right data sweep enable */ +#define DMIC_CTLR_DATA1_SWAP_BIT HAL_BIT(5) /* bit5, data1 left data and right data sweep enable */ +#define DMIC_CTLR_DATA2_SWAP_BIT HAL_BIT(6) /* bit6, data2 left data and right data sweep enable */ +#define DMIC_CTLR_DATA3_SWAP_BIT HAL_BIT(7) /* bit7, data3 left data and right data sweep enable */ +#define DMIC_CTLR_DMICDFEN_BIT HAL_BIT(8) /* bit8, dmic fifo delay function for writing data after globe_en */ + +#define DMIC_CTLR_DMICFDT_SHIFT (9) +#define DMIC_CTLR_DMICFDT_MASK (0x3U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT) +typedef enum { + DMIC_CTLR_DMICFDT_5MS = (0X0U << DMIC_CTLR_DMICFDT_SHIFT), + DMIC_CTLR_DMICFDT_10MS = (0X1U << DMIC_CTLR_DMICFDT_SHIFT), + DMIC_CTLR_DMICFDT_200MS = (0X2U << DMIC_CTLR_DMICFDT_SHIFT), + DMIC_CTLR_DMICFDT_30MS = (0X3U << DMIC_CTLR_DMICFDT_SHIFT), +} DMIC_CtrlDmicFDT; + +/* + * Bits definition for DMIC_ICR register (0x14) + */ +#define DMIC_ICR_DATA_IRQ_EN_BIT HAL_BIT(0) /* bit0, dmic fifo data available irq enable */ +#define DMIC_ICR_OVERRUN_IRQ_EN_BIT HAL_BIT(1) /* bit1, dmic fifo fifo overrun irq enable */ +#define DMIC_ICR_FIFO_DRQ_EN_BIT HAL_BIT(2) /* bit2, dmic fifo data available drq enable */ + +/* + * Bits definition for DMIC_ISR register (0X18) + */ +#define DMIC_ISR_DATA_IRQ_PEND_BIT HAL_BIT(0) /* bit0, dmic fifo data available pending interrupt */ +#define DMIC_ISR_OVERRUN_IRQ_PEND_BIT HAL_BIT(1) /* bit1, dmic fifo fifo overrun pending interrupt */ + +/* + * Bits definition for DMIC_FIFOCR register(0X1C) + */ +#define DMIC_FIFOCR_TRG_LEVEL_SHIFT (0) +#define DMIC_FIFOCR_TRG_LEVEL_MASK (0xFFU << DMIC_FIFOCR_TRG_LEVEL_SHIFT) +#define DMIC_FIFOCR_TRG_LEVEL(n) ((n) << DMIC_FIFOCR_TRG_LEVEL_SHIFT) + +#define DMIC_FIFOCR_SAMPLE_RES_SHIFT (8) +#define DMIC_FIFOCR_SAMPLE_RES_MASK (0x1U << DMIC_FIFOCR_SAMPLE_RES_SHIFT) + +/** + * @brief sampling accuracy + */ +typedef enum { + DMIC_RES16BIT = (0X0U << DMIC_FIFOCR_SAMPLE_RES_SHIFT), + DMIC_RES24BIT = (0X1U << DMIC_FIFOCR_SAMPLE_RES_SHIFT), +} DMIC_FifoSampleRes; + +#define DMIC_FIFOCR_MODE_SHIFT (9) +#define DMIC_FIFOCR_MODE_MASK (0x1U << DMIC_FIFOCR_MODE_SHIFT) +typedef enum { + DMIC_FIFOCR_MODE0 = (0X0U << DMIC_FIFOCR_MODE_SHIFT), + DMIC_FIFOCR_MODE1 = (0X1U << DMIC_FIFOCR_MODE_SHIFT), +} DMIC_FifoMode; + +#define DMIC_FIFOCR_FIFO_FLUSH_BIT HAL_BIT(31) /* bit31, dmic fifo flush */ + +/* + * Bits definition for DMIC_FIFOSR register (0x20) + */ +#define DMIC_FIFOSR_DATA_CNT_SHIFT (0) +#define DMIC_FIFOSR_DATA_CNT_MASK (0xFFU << DMIC_FIFOSR_DATA_CNT_SHIFT) /* bit0:bit7, FIFO available sample world counter */ + +/* + * Bits definition for DMIC_CNR register + */ +#define DMIC_CH_NUM_SHIFT (0) +#define DMIC_CH_NUM_MASK (0X7U << DMIC_CH_NUM_SHIFT) +typedef enum { + DMIC_CH_NUM1 = (0X0U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM2 = (0X1U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM3 = (0X2U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM4 = (0X3U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM5 = (0X4U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM6 = (0X5U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM7 = (0X6U << DMIC_CH_NUM_SHIFT), + DMIC_CH_NUM8 = (0X7U << DMIC_CH_NUM_SHIFT), +} DMIC_ChannelNum; + +/* + * Bits definition for DMIC_CMR register(0x28) + */ +#define DMIC_CMR_CH0_MAP_SHIFT (0) +#define DMIC_CMR_CH0_MAP_MASK(m) (0X7U << 4*m) +#define DMIC_CMR_CH0_MAP(m) (m << 4*m) + +/* + * Bits definition for DMIC_VCR0 register (0X0030) + */ +#define DMIC_DATA0R_VOL_SHIFT (0) +#define DMIC_DATA0R_VOL_MASK (0xFFU << DMIC_DATA0R_VOL_SHIFT) +#define DMIC_DATA0R_VOL(n) (n << DMIC_DATA0R_VOL_SHIFT) + +#define DMIC_DATA0L_VOL_SHIFT (8) +#define DMIC_DATA0L_VOL_MASK (0xFFU << DMIC_DATA0L_VOL_SHIFT) +#define DMIC_DATA0L_VOL(n) (n << DMIC_DATA0L_VOL_SHIFT) + +#define DMIC_DATA1R_VOL_SHIFT (16) +#define DMIC_DATA1R_VOL_MASK (0xFFU << DMIC_DATA1R_VOL_SHIFT) + +#define DMIC_DATA1L_VOL_SHIFT (24) +#define DMIC_DATA1L_VOL_MASK (0xFFU << DMIC_DATA1L_VOL_SHIFT) + +/* + * Bits definition for DMIC_VCR1 register (0X0034) + */ +#define DMIC_DATA2R_VOL_SHIFT (0) +#define DMIC_DATA2R_VOL_MASK (0xFFU << DMIC_DATA2R_VOL_SHIFT) + +#define DMIC_DATA2L_VOL_SHIFT (8) +#define DMIC_DATA2L_VOL_MASK (0xFFU << DMIC_DATA2L_VOL_SHIFT) + +#define DMIC_DATA3R_VOL_SHIFT (16) +#define DMIC_DATA3R_VOL_MASK (0xFFU << DMIC_DATA3R_VOL_SHIFT) + +#define DMIC_DATA3L_VOL_SHIFT (24) +#define DMIC_DATA3L_VOL_MASK (0xFFU << DMIC_DATA3L_VOL_SHIFT) + +/* + * Bits definition for DMIC_HPFECR register (0X0038) + */ +#define DMIC_HPF_DATA0_CHL_EN_BIT HAL_BIT(0) /* bit0, data0 left channel enable */ +#define DMIC_HPF_DATA0_CHR_EN_BIT HAL_BIT(1) /* bit1, data0 right channel 1 enable */ +#define DMIC_HPF_DATA1_CHL_EN_BIT HAL_BIT(2) /* bit2, data1 left channel enable */ +#define DMIC_HPF_DATA1_CHR_EN_BIT HAL_BIT(3) /* bit3, data1 right channel 1 enable */ +#define DMIC_HPF_DATA2_CHL_EN_BIT HAL_BIT(4) /* bit4, data2 left channel enable */ +#define DMIC_HPF_DATA2_CHR_EN_BIT HAL_BIT(5) /* bit5, data2 right channel 1 enable */ +#define DMIC_HPF_DATA3_CHL_EN_BIT HAL_BIT(6) /* bit6, data3 left channel enable */ +#define DMIC_HPF_DATA3_CHR_EN_BIT HAL_BIT(7) /* bit7, data3 right channel 1 enable */ + +/** + * @brief Dmic low level hardware init structure definition + */ +typedef struct { + DMIC_CtrlDmicFDT delayTime; /*!< Specifies dmic fdt delay time. */ + DMIC_FifoMode fifoMode; /*!< Specifies dmic fifo mode. */ + uint32_t triggerLevel; /*!< Specifies the threshold for dmic fifo triggers. */ + uint32_t volumeGain; /*!< Specifies the dmic hardware gain. */ + bool hpfEnable; /*!< Specifies whether to enable hpf function. */ +} DMIC_HWParam; + +/** + * @brief Dmic data format init structure definition + */ +typedef struct { + DMIC_SampleRate sampleRate; /*!< Specifies the sampling rate of the stream. */ + DMIC_FifoSampleRes resolution; /*!< Specifies the sampling accuracy of the stream. */ + uint32_t channels; /*!< Specifies the number of the stream. */ + uint32_t bufSize; /*!< Specifies the buffer size of received data. */ +} DMIC_DataParam; + +/** + * @brief Dmic module init structure definition + */ +typedef struct { + DMIC_HWParam *hwParam; /*!< Dmic hardware init structure. */ +} DMIC_Param; + +HAL_Status HAL_DMIC_Init(DMIC_Param *param); +void HAL_DMIC_DeInit(); +HAL_Status HAL_DMIC_Open(DMIC_DataParam *param); +void HAL_DMIC_Close(); +HAL_Status HAL_DMIC_Suspend(); +HAL_Status HAL_DMIC_Resume(); +int32_t HAL_DMIC_Read_DMA(uint8_t *buf, uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_DMIC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_efuse.h b/platform/mcu/xr871/include/driver/chip/hal_efuse.h new file mode 100644 index 0000000000..dcb13f7f83 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_efuse.h @@ -0,0 +1,93 @@ +/** + * @file hal_efuse.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_EFUSE_H_ +#define _DRIVER_CHIP_HAL_EFUSE_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief EFUSE register block structure + */ +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t CTRL; /* offset: 0x0040 EFUSE program/read control register */ + uint32_t RESERVED1[3]; + __IO uint32_t PROGRAM_VALUE; /* offset: 0x0050 EFUSE program key value register */ + uint32_t RESERVED2[3]; + __I uint32_t READ_VALUE; /* offset: 0x0060 EFUSE read key value register */ + uint32_t RESERVED3[11]; + __IO uint32_t TIMING_CTRL; /* offset: 0x0090 EFUSE burned timing control register */ + __IO uint32_t DEBUG_REG; /* offset: 0x0094 EFUSE debug register */ +} EFUSE_T; + +#define EFUSE ((EFUSE_T *)SID_BASE) /* address: 0x40043C00 */ + +/* EFUSE->CTRL */ +#define EFUSE_CLK_GATE_EN_BIT HAL_BIT(28) + +#define EFUSE_INDEX_SHIFT 16 +#define EFUSE_INDEX_MASK ((0xFFU) << EFUSE_INDEX_SHIFT) + +#define EFUSE_OPERA_LOCK_SHIFT 8 +#define EFUSE_OPERA_LOCK_MASK ((0xFFU) << EFUSE_OPERA_LOCK_SHIFT) +#define EFUSE_OPERA_UNLOCK_VAL 0xACU + +#define EFUSE_HW_READ_STATUS_BIT HAL_BIT(2) +#define EFUSE_SW_READ_START_BIT HAL_BIT(1) +#define EFUSE_SW_PROG_START_BIT HAL_BIT(0) + +/* EFUSE->TIMING_CTRL */ +typedef enum { + EFUSE_TIMING_PARAM_24M = 0x63321190U, + EFUSE_TIMING_PARAM_26M = 0x63321190U, +} EFUSE_TimingParam; + +/******************************************************************************/ + +/** @brief The number of bits on chip EFUSE */ +#define HAL_EFUSE_BIT_NUM (2048) + +HAL_Status HAL_EFUSE_Read(uint32_t start_bit, uint32_t bit_num, uint8_t *data); +HAL_Status HAL_EFUSE_Write(uint32_t start_bit, uint32_t bit_num, uint8_t *data); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_EFUSE_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_flash.h b/platform/mcu/xr871/include/driver/chip/hal_flash.h new file mode 100644 index 0000000000..627edd4daf --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_flash.h @@ -0,0 +1,142 @@ +/** + * @file hal_flash.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HAL_FLASH_H_ +#define HAL_FLASH_H_ + +#include +#include +#include "flashchip/flash_chip.h" +#include "driver/chip/hal_spi.h" + +#define FLASH_FLASHC_ENABLE (1) +#define FLASH_SPI_ENABLE (!defined(__CONFIG_BOOTLOADER)) + +typedef struct FlashDrvierBase FlashDrvierBase; + +typedef HAL_Status (*FlashDriverFunc)(FlashDrvierBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + +struct FlashDrvierBase +{ + /* + attribute + */ + int dev; + uint32_t sizeToDma; + + /* + public interface + */ + FlashDriverFunc write; + FlashDriverFunc read; + HAL_Status (*open)(FlashDrvierBase *base); + HAL_Status (*close)(FlashDrvierBase *base); + HAL_Status (*setFreq)(FlashDrvierBase *base, uint32_t freq); + void (*msleep)(FlashDrvierBase *base, uint32_t ms); + void (*destroy)(FlashDrvierBase *); +}; + +FlashDrvierBase *FlashDriverCreator(int driver); +int FlashDriverDestory(FlashDrvierBase *base); + +/* + Flash Board Config +*/ +enum FlashBoardType +{ +#if FLASH_FLASHC_ENABLE + FLASH_DRV_FLASHC, /*!< flash controller driver */ +#endif +#if FLASH_SPI_ENABLE + FLASH_DRV_SPI /*!< spi driver */ +#endif +}; + +typedef struct FlashcBoardCfg +{ + uint32_t clk; /*!< flash clock */ +} FlashcBoardCfg; + +typedef struct SpiBoardCfg +{ + uint32_t clk; /*!< flash clock */ + SPI_Port port; /*!< spi port */ + SPI_CS cs; /*!< cs pin */ +} SpiBoardCfg; + +typedef struct FlashBoardCfg +{ + enum FlashBoardType type; /*!< flash driver */ + FlashReadMode mode; /*!< read mode to flash */ + union { + FlashcBoardCfg flashc; /*!< flash driver controller configuration. Notice!! flashc support all read mode */ + SpiBoardCfg spi; /*!< spi driver configuration. Notice!! spi only support normal read, fast read, dual output mode */ + }; +} FlashBoardCfg; + + +/* + Flash Global Interface +*/ +typedef struct FlashDev FlashDev; + +typedef enum FlashControlCmd +{ + FLASH_GET_MIN_ERASE_SIZE, + /*TODO: tbc...*/ +} FlashControlCmd; + +HAL_Status HAL_Flash_Init(uint32_t flash); + +HAL_Status HAL_Flash_Deinit(uint32_t flash); + +HAL_Status HAL_Flash_Open(uint32_t flash, uint32_t timeout_ms); + +HAL_Status HAL_Flash_Close(uint32_t flash); + +HAL_Status HAL_Flash_Control(uint32_t flash, FlashControlCmd attr, uint32_t arg); + +HAL_Status HAL_Flash_Overwrite(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size); + +HAL_Status HAL_Flash_Write(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size); + +HAL_Status HAL_Flash_Read(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size); + +HAL_Status HAL_Flash_Erase(uint32_t flash, FlashEraseMode blk_size, uint32_t addr, uint32_t blk_cnt); + +HAL_Status HAL_Flash_MemoryOf(uint32_t flash, FlashEraseMode size, uint32_t addr, uint32_t *start); + +int HAL_Flash_Check(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size); + +#endif /* HAL_FLASH_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_flashcache.h b/platform/mcu/xr871/include/driver/chip/hal_flashcache.h new file mode 100644 index 0000000000..8733c533b4 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_flashcache.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_FLASHCACHE_H_ +#define _DRIVER_CHIP_HAL_FLASHCACHE_H_ + +#include +#include "driver/chip/hal_def.h" +#include "sys/xr_debug.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + __IO uint32_t COM_CTRL; /* , Address offset: */ + __IO uint32_t PREFETCH_CTRL; + __IO uint32_t PREFETCH_START_ADDR; /* , Address offset: */ + __IO uint32_t IV_PREFETCH_CTRL; /* , Address offset: */ + __IO uint32_t IV_ADDR[16]; /* , Address offset: */ + __IO uint32_t INDIRECT_JUMP_ADDR[16]; /* , Address offset: */ + __IO uint32_t MIN_ADDR; /* , Address offset: */ + __IO uint32_t MAX_ADDR; /* , Address offset: */ + __IO uint32_t READ_BIAS_ADDR; /* , Address offset: */ + +} FLASH_CACHE_T; + + +#define FLASH_CACHE ((FLASH_CACHE_T *)FLASH_CACHE_BASE) + +/* + * @brief + */ +#define FLASH_CACHE_COM_CTRL_SIZE_SHIFT (0) +#define FLASH_CACHE_COM_CTRL_SIZE_MASK (0x1FFU << FLASH_CACHE_COM_CTRL_SIZE_SHIFT) + +#define FLASH_CACHE_PREFETCH_CTRL_SIZE_SHIFT (8) +#define FLASH_CACHE_PREFETCH_CTRL_SIZE_MASK (0xFFU << FLASH_CACHE_PREFETCH_CTRL_SIZE_SHIFT) + +#define FLASH_CACHE_PREFETCH_CTRL_BRANCH_SHIFT (4) +#define FLASH_CACHE_PREFETCH_CTRL_BRANCH_MASK (0x1U << FLASH_CACHE_PREFETCH_CTRL_BRANCH_SHIFT) + +#define FLASH_CACHE_PREFETCH_CTRL_STOP_SHIFT (0) +#define FLASH_CACHE_PREFETCH_CTRL_STOP_MASK (0x1U << FLASH_CACHE_PREFETCH_CTRL_STOP_SHIFT) + +typedef enum { + FLASH_CACHE_PREFETCH_ENABLE = 0, + FLASH_CACHE_PREFETCH_DISABLE = 1 +} Flash_Cache_Prefetch; + +#define FLASH_CACHE_PREFETCH_START_ADDR_SHIFT (0) +#define FLASH_CACHE_PREFETCH_START_ADDR_MASK (0xFFFFFFU << FLASH_CACHE_PREFETCH_START_ADDR_SHIFT) + +#define FLASH_CACHE_IV_PREFETCH_CTRL_RELEASE_SHIFT (12) +#define FLASH_CACHE_IV_PREFETCH_CTRL_RELEASE_MASK (0x1U << FLASH_CACHE_IV_PREFETCH_CTRL_RELEASE_SHIFT) + +#define FLASH_CACHE_IV_PREFETCH_CTRL_IV_NUM_SHIFT (4) +#define FLASH_CACHE_IV_PREFETCH_CTRL_IV_NUM_MASK (0xFU << FLASH_CACHE_IV_PREFETCH_CTRL_IV_NUM_SHIFT) + +#define FLASH_CACHE_IV_PREFETCH_CTRL_ENABLE_SHIFT (0) +#define FLASH_CACHE_IV_PREFETCH_CTRL_ENABLE_MASK (0x1U << FLASH_CACHE_IV_PREFETCH_CTRL_ENABLE_SHIFT) + +#define FLASH_CACHE_IV_ADDR_SHIFT (0) +#define FLASH_CACHE_IV_ADDR_MASK (0xFFFFFFU << FLASH_CACHE_IV_ADDR_SHIFT) + +#define FLASH_CACHE_INDIRECT_JUMP_ADDR_SHIFT (0) +#define FLASH_CACHE_INDIRECT_JUMP_ADDR_MASK (0xFFFFFFU << FLASH_CACHE_INDIRECT_JUMP_ADDR_SHIFT) + +#define FLASH_CACHE_MIN_ADDR_SHIFT (0) +#define FLASH_CACHE_MIN_ADDR_MASK (0xFFFFFFFFU << FLASH_CACHE_MIN_ADDR_SHIFT) + +#define FLASH_CACHE_MAX_ADDR_SHIFT (0) +#define FLASH_CACHE_MAX_ADDR_MASK (0xFFFFFFFFU << FLASH_CACHE_MAX_ADDR_SHIFT) + +#define FLASH_CACHE_READ_BIAS_ADDR_SHIFT (0) +#define FLASH_CACHE_READ_BIAS_ADDR_MASK (0xFFFFFFU << FLASH_CACHE_READ_BIAS_ADDR_SHIFT) + + +#define FLASH_ROM_START_ADDR (0x10000000U) +#define FLASH_ROM_END_ADDR (0x101FFFFFU) + +#define CACHE_LINE_MAX (0x1FF) +#define CACHE_START_ADDR (FLASH_ROM_START_ADDR) +#define CACHE_END_ADDR (FLASH_ROM_END_ADDR) + + + +typedef struct { +// uint32_t cache_size; /* in bytes */ + uint32_t addr_bias; /* bias from flash */ +} FlashCache_Config; + +typedef struct { +// uint32_t prefetch_cache_size; /* in bytes, recommended size is no more than FlashCache_Config.cache_size */ + bool prefetch_2nd_branch; + uint32_t addr_prefetch_start; +} FlashCache_PrefetchConfig; + +typedef struct { + struct { + uint32_t addr_interrupt_vector; + uint32_t addr_interrupt_cb; + } prefetch_interrupt[16]; +} FlashCache_PrefetchIntConfig; + + +HAL_Status Hal_FlashCache_Init(FlashCache_Config *cfg); +HAL_Status Hal_FlashCache_Deinit(); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_FLASHCACHE_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_flashctrl.h b/platform/mcu/xr871/include/driver/chip/hal_flashctrl.h new file mode 100644 index 0000000000..b829c12d7f --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_flashctrl.h @@ -0,0 +1,458 @@ +/** + * @file hal_flashctrl.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HAL_FLASHCTRL_H_ +#define __HAL_FLASHCTRL_H_ + +#include +#include +#include "driver/chip/hal_def.h" +#include "sys/xr_debug.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + __IO uint32_t COMMON_CFG; /* , Address offset: 0x000 */ + __IO uint32_t I_CMD_CFG; /* , Address offset: 0x004 */ + __IO uint32_t I_DUMMY_H; /* , Address offset: 0x008 */ + __IO uint32_t I_DUMMY_L; /* , Address offset: 0x00C */ + __IO uint32_t I_CS_WAIT; /* , Address offset: 0x010 */ + __IO uint32_t I_IO_WAIT;//CMD_WAIT; /* , Address offset: 0x014 */ + __IO uint32_t RESERVE0[2]; + __IO uint32_t FLASH_COMMON_CFG; /* , Address offset: 0x020 */ + __I uint32_t XIP_EXEC; /* , Address offset: 0x024 */ + + __IO uint32_t COMMON_ADD_CFG; /* , Address offset: 0x028 */ + __IO uint32_t S_CMD_CFG; /* , Address offset: 0x02C */ + __IO uint32_t S_ADDR_CFG; /* , Address offset: 0x030 */ + __IO uint32_t S_WR_NUM; /* , Address offset: 0x034 */ + __IO uint32_t S_RD_NUM; /* , Address offset: 0x038 */ + __IO uint32_t S_DUMMY_H; /* , Address offset: 0x03C */ + __IO uint32_t S_DUMMY_L; /* , Address offset: 0x040 */ + __IO uint32_t FIFO_TRIG_LEVEL; /* , Address offset: 0x044 */ + __I uint32_t FIFO_STATUS; /* , Address offset: 0x048 */ + __IO uint32_t S_IO_WAIT; /* , Address offset: 0x04C */ + __I uint32_t WRAP_MODE; /* , Address offset: 0x050 */ + __IO uint32_t START_SEND; /* , Address offset: 0x054 */ + __IO uint32_t INT_EN; /* , Address offset: 0x058 */ + __IO uint32_t INT_STA; /* , Address offset: 0x05C */ + __IO uint32_t RESERVE1[40]; + __IO uint32_t S_WDATA; /* , Address offset: 0x100 */ + __IO uint32_t RESERVE2[63]; + /* (0X200 - 0X100) * 4 / 16 -1 = 63*/ + __I uint32_t S_RDATA; /* , Address offset: 0x200 */ +} FLASH_CTRL_T; + + + +#define FLASH_CTRL ((FLASH_CTRL_T *)FLASH_CTRL_BASE) + +/* + * @brief + */ +#define FC_CC_CONT_EN_SHIFT (20) +#define FC_CC_CONT_EN_MASK (0x1U << FC_CC_CONT_EN_SHIFT) + +#define FC_CC_IO1_SHIFT (16) +#define FC_CC_IO1_MASK (0x3U << FC_CC_IO1_SHIFT) + +#define FC_CC_IO2_SHIFT (12) +#define FC_CC_IO2_MASK (0x3U << FC_CC_IO2_SHIFT) + +#define FC_CC_IO3_SHIFT (8) +#define FC_CC_IO3_MASK (0x3U << FC_CC_IO2_SHIFT) + +typedef enum { + FC_IO_OUTPUT_0, + FC_IO_OUTPUT_1, + FC_IO_OUTPUT_Z +} FC_Io_Output; + +#define FC_CC_PREFETCH_EN_SHIFT (4) +#define FC_CC_PREFETCH_EN_MASK (0x1U << FC_CC_PREFETCH_EN_SHIFT) + +#define FC_CC_IBUS_EN_SHIFT (0) +#define FC_CC_IBUS_EN_MASK (0x1U << FC_CC_IBUS_EN_SHIFT) + +#define FC_ICC_CMD_SHIFT (24) +#define FC_ICC_CMD_MASK (0xFFU << FC_ICC_CMD_SHIFT) + +#define FC_ICC_CMD_BIT_SHIFT (20) +#define FC_ICC_CMD_BIT_MASK (0x3U << FC_ICC_CMD_BIT_SHIFT) + +#define FC_ICC_ADDR_BIT_SHIFT (16) +#define FC_ICC_ADDR_BIT_MASK (0x3U << FC_ICC_ADDR_BIT_SHIFT) + +#define FC_ICC_DUMMY_BIT_SHIFT (12) +#define FC_ICC_DUMMY_BIT_MASK (0x3U << FC_ICC_DUMMY_BIT_SHIFT) + +#define FC_ICC_DUMMY_WIDTH_SHIFT (4) +#define FC_ICC_DUMMY_WIDTH_MASK (0x7FU << FC_ICC_DUMMY_WIDTH_SHIFT) + +#define FC_ICC_DATA_BIT_SHIFT (0) +#define FC_ICC_DATA_BIT_MASK (0x3U << FC_ICC_DATA_BIT_SHIFT) + +typedef enum { + FC_CYCLEBITS_0, + FC_CYCLEBITS_1, + FC_CYCLEBITS_2, + FC_CYCLEBITS_4 +} FC_CycleBits; + +#define FC_IDH_SHIFT (0) +#define FC_IDH_MASK (0xFFFFFFFFU << FC_IDH_SHIFT) + +#define FC_IDL_SHIFT (0) +#define FC_IDL_MASK (0xFFFFFFFFU << FC_IDL_SHIFT) + +#define FC_ICW_BEGIN_SHIFT (16) +#define FC_ICW_BEGIN_MASK (0xFFU << FC_ICW_BEGIN_SHIFT) + +#define FC_ICW_OVER_SHIFT (8) +#define FC_ICW_OVER_MASK (0xFFU << FC_ICW_OVER_SHIFT) + +#define FC_ICW_DESEL_SHIFT (0) +#define FC_ICW_DESEL_MASK (0xFFU << FC_ICW_DESEL_SHIFT) + +#define FC_IIW_CMD_SHIFT (16) +#define FC_IIW_CMD_MASK (0xFFU << FC_IIW_CMD_SHIFT) + +#define FC_IIW_ADDR_SHIFT (8) +#define FC_IIW_ADDR_MASK (0xFFU << FC_IIW_ADDR_SHIFT) + +#define FC_IIW_DUM_SHIFT (0) +#define FC_IIW_DUM_MASK (0xFFU << FC_IIW_DUM_SHIFT) + +#define FC_FCC_WAIT_DATA_SHIFT (12) +#define FC_FCC_WAIT_DATA_MASK (0x3U << FC_FCC_WAIT_DATA_SHIFT) + +#define FC_FCC_CS_SHIFT (8) +#define FC_FCC_CS_MASK (0x1U << FC_FCC_CS_SHIFT) + +typedef enum { + FC_TCTRL_CS_LOW_ENABLE = 0 << FC_FCC_CS_SHIFT, + FC_TCTRL_CS_HIGH_ENABLE = 1 << FC_FCC_CS_SHIFT +} FC_Cs; + +#define FC_FCC_FBS_SHIFT (4) +#define FC_FCC_FBS_MASK (0x1U << FC_FCC_FBS_SHIFT) + +typedef enum { + FC_TCTRL_FBS_MSB = 0 << FC_FCC_FBS_SHIFT, + FC_TCTRL_FBS_LSB = 1 << FC_FCC_FBS_SHIFT +} FC_TCTRL_Fbs; + +#define FC_FCC_CPOL_SHIFT (1) +#define FC_FCC_CPOL_MASK (0x1U << FC_FCC_CPOL_SHIFT) + +#define FC_FCC_CPHA_SHIFT (0) +#define FC_FCC_CPHA_MASK (0x1U << FC_FCC_CPHA_SHIFT) + +typedef enum { + FC_SCLK_Mode0 = 0 << FC_FCC_CPHA_SHIFT, + FC_SCLK_Mode1 = 1 << FC_FCC_CPHA_SHIFT, + FC_SCLK_Mode2 = 2 << FC_FCC_CPHA_SHIFT, + FC_SCLK_Mode3 = 3 << FC_FCC_CPHA_SHIFT +} FC_Sclk_Mode; + +#define FC_XE_SHIFT (0) +#define FC_XE_MASK (0x1U << FC_XE_SHIFT) + + +#define FC_CAC_CS_DESEL_WAIT_SHIFT (4) +#define FC_CAC_CS_DESEL_WAIT_MASK (0xFFU << FC_CAC_CS_DESEL_WAIT_SHIFT) + +#define FC_CAC_TX_FIFO_RESET_SHIFT (3) +#define FC_CAC_TX_FIFO_RESET_MASK (0x1U << FC_CAC_TX_FIFO_RESET_SHIFT) + +#define FC_CAC_RX_FIFO_RESET_SHIFT (2) +#define FC_CAC_RX_FIFO_RESET_MASK (0x1U << FC_CAC_RX_FIFO_RESET_SHIFT) + +#define FC_CAC_WRAP_EN_SHIFT (1) +#define FC_CAC_WRAP_EN_MASK (0x1U << FC_CAC_WRAP_EN_SHIFT) + +#define FC_CAC_ADDR_SIZE_MODE_SHIFT (0) +#define FC_CAC_ADDR_SIZE_MODE_MASK (0x1U << FC_CAC_ADDR_SIZE_MODE_SHIFT) + +typedef enum { + FC_ADDR_MODE_24BIT = 0 << FC_CAC_ADDR_SIZE_MODE_SHIFT, + FC_ADDR_MODE_32BIT = 1 << FC_CAC_ADDR_SIZE_MODE_SHIFT, +} FC_Addr_Mode; + +#define FC_SCC_CMD_SHIFT (24) +#define FC_SCC_CMD_MASK (0xFFU << FC_SCC_CMD_SHIFT) + +#define FC_SCC_CMD_BIT_SHIFT (20) +#define FC_SCC_CMD_BIT_MASK (0x3U << FC_SCC_CMD_BIT_SHIFT) + +#define FC_SCC_ADDR_BIT_SHIFT (16) +#define FC_SCC_ADDR_BIT_MASK (0x3U << FC_SCC_ADDR_BIT_SHIFT) + +#define FC_SCC_DUMMY_BIT_SHIFT (12) +#define FC_SCC_DUMMY_BIT_MASK (0x3U << FC_SCC_DUMMY_BIT_SHIFT) + +#define FC_SCC_DUMMY_DATA_BIT_SHIFT (4) +#define FC_SCC_DUMMY_DATA_BIT_MASK (0x3FU << FC_SCC_DUMMY_DATA_BIT_SHIFT) + +#define FC_SCC_DATA_BIT_SHIFT (0) +#define FC_SCC_DATA_BIT_MASK (0x3U << FC_SCC_DATA_BIT_SHIFT) + +#define FC_SAC_SHIFT (0) +#define FC_SAC_MASK (0xFFFFFFFFU << FC_SAC_SHIFT) + +#define FC_SWN_SHIFT (0) +#define FC_SWN_MASK (0xFFU << FC_SWN_SHIFT) + +#define FC_SRN_SHIFT (0) +#define FC_SRN_MASK (0xFFFFFFFFU << FC_SRN_SHIFT) + +#define FC_SDH_SHIFT (0) +#define FC_SDH_MASK (0xFFFFFFFFU << FC_SDH_SHIFT) + +#define FC_SDL_SHIFT (0) +#define FC_SDL_MASK (0xFFFFFFFFU << FC_SDL_SHIFT) + +#define FC_FTL_WR_FIFO_FULL_SHIFT (24) +#define FC_FTL_WR_FIFO_FULL_MASK (0xFFU << FC_FTL_WR_FIFO_FULL_SHIFT) + +#define FC_FTL_WR_FIFO_EMPTY_SHIFT (16) +#define FC_FTL_WR_FIFO_EMPTY_MASK (0xFFU << FC_FTL_WR_FIFO_EMPTY_SHIFT) + +#define FC_FTL_RD_FIFO_FULL_SHIFT (8) +#define FC_FTL_RD_FIFO_FULL_MASK (0xFFU << FC_FTL_RD_FIFO_FULL_SHIFT) + +#define FC_FTL_RD_FIFO_EMPTY_SHIFT (0) +#define FC_FTL_RD_FIFO_EMPTY_MASK (0xFFU << FC_FTL_RD_FIFO_EMPTY_SHIFT) + +#define FC_FS_STATUS_DGB_SHIFT (24) +#define FC_FS_STATUS_DGB_MASK (0xFU << FC_FS_STATUS_DGB_SHIFT) +#define FC_FS_STATUS_DGB_VMASK (0xFU) + +#define FC_FS_WR_BUF_VALID_SHIFT (23) +#define FC_FS_WR_BUF_VALID_MASK (0x1U << FC_FS_WR_BUF_VALID_SHIFT) + +#define FC_FS_WR_BUF_CNT_SHIFT (20) +#define FC_FS_WR_BUF_CNT_MASK (0x7U << FC_FS_WR_BUF_CNT_SHIFT) +#define FC_FS_WR_BUF_CNT_VMASK (0x7U) + +#define FC_FS_RD_BUF_VALID_SHIFT (19) +#define FC_FS_RD_BUF_VALID_MASK (0x1U << FC_FS_RD_BUF_VALID_SHIFT) + +#define FC_FS_RD_BUF_CNT_SHIFT (16) +#define FC_FS_RD_BUF_CNT_MASK (0x7U << FC_FS_RD_BUF_CNT_SHIFT) +#define FC_FS_RD_BUF_CNT_VMASK (0x7U) + +#define FC_FS_WR_FIFO_CNT_SHIFT (8) +#define FC_FS_WR_FIFO_CNT_MASK (0xFFU << FC_FS_WR_FIFO_CNT_SHIFT) +#define FC_FS_WR_FIFO_CNT_VMASK (0xFFU) + +#define FC_FS_RD_FIFO_CNT_SHIFT (0) +#define FC_FS_RD_FIFO_CNT_MASK (0xFFU << FC_FS_RD_FIFO_CNT_SHIFT) +#define FC_FS_RD_FIFO_CNT_VMASK (0xFFU) + +#define FC_SIW_CMD_SHIFT (16) +#define FC_SIW_CMD_MASK (0xFFU << FC_SIW_CMD_SHIFT) + +#define FC_SIW_ADDR_SHIFT (8) +#define FC_SIW_ADDR_MASK (0xFFU << FC_SIW_ADDR_SHIFT) + +#define FC_SIW_DUMMY_SHIFT (0) +#define FC_SIW_DUMMY_MASK (0xFFU << FC_SIW_DUMMY_SHIFT) + +#define FC_WM_SHIFT (0) +#define FC_WM_MASK (0x1U << FC_WM_SHIFT) + +#define FC_SS_SHIFT (0) +#define FC_SS_MASK (0x1U << FC_SS_SHIFT) + +#define FC_IE_CMPL_SHIFT (12) +#define FC_IE_CMPL_MASK (0x1U << FC_IE_CMPL_SHIFT) + +#define FC_IE_WR_FIFO_UNDERFLOW_SHIFT (11) +#define FC_IE_WR_FIFO_UNDERFLOW_MASK (0x1U << FC_IE_WR_FIFO_UNDERFLOW_SHIFT) + +#define FC_IE_WR_FIFO_OVERFLOW_SHIFT (10) +#define FC_IE_WR_FIFO_OVERFLOW_MASK (0x1U << FC_IE_WR_FIFO_OVERFLOW_SHIFT) + +#define FC_IE_RD_FIFO_UNDERFLOW_SHIFT (9) +#define FC_IE_RD_FIFO_UNDERFLOW_MASK (0x1U << FC_IE_RD_FIFO_UNDERFLOW_SHIFT) + +#define FC_IE_RD_FIFO_OVERFLOW_SHIFT (8) +#define FC_IE_RD_FIFO_OVERFLOW_MASK (0x1U << FC_IE_RD_FIFO_OVERFLOW_SHIFT) + +#define FC_IE_WR_FIFO_FULL_SHIFT (6) +#define FC_IE_WR_FIFO_FULL_MASK (0x1U << FC_IE_WR_FIFO_FULL_SHIFT) + +#define FC_IE_WR_FIFO_EMPTY_SHIFT (5) +#define FC_IE_WR_FIFO_EMPTY_MASK (0x1U << FC_IE_WR_FIFO_EMPTY_SHIFT) + +#define FC_IE_WR_FIFO_READY_SHIFT (4) +#define FC_IE_WR_FIFO_READY_MASK (0x1U << FC_IE_WR_FIFO_READY_SHIFT) + +#define FC_IE_RD_FIFO_FULL_SHIFT (2) +#define FC_IE_RD_FIFO_FULL_MASK (0x1U << FC_IE_RD_FIFO_FULL_SHIFT) + +#define FC_IE_RD_FIFO_EMPTY_SHIFT (1) +#define FC_IE_RD_FIFO_EMPTY_MASK (0x1U << FC_IE_RD_FIFO_EMPTY_SHIFT) + +#define FC_IE_RD_FIFO_READY_SHIFT (0) +#define FC_IE_RD_FIFO_READY_MASK (0x1U << FC_IE_RD_FIFO_READY_SHIFT) + +#define FC_IS_CMPL_SHIFT (12) +#define FC_IS_CMPL_MASK (0x1U << FC_IS_CMPL_SHIFT) + +#define FC_IS_WR_FIFO_UNDERFLOW_SHIFT (11) +#define FC_IS_WR_FIFO_UNDERFLOW_MASK (0x1U << FC_IS_WR_FIFO_UNDERFLOW_SHIFT) + +#define FC_IS_WR_FIFO_OVERFLOW_SHIFT (10) +#define FC_IS_WR_FIFO_OVERFLOW_MASK (0x1U << FC_IS_WR_FIFO_OVERFLOW_SHIFT) + +#define FC_IS_RD_FIFO_UNDERFLOW_SHIFT (9) +#define FC_IS_RD_FIFO_UNDERFLOW_MASK (0x1U << FC_IS_RD_FIFO_UNDERFLOW_SHIFT) + +#define FC_IS_RD_FIFO_OVERFLOW_SHIFT (8) +#define FC_IS_RD_FIFO_OVERFLOW_MASK (0x1U << FC_IS_RD_FIFO_OVERFLOW_SHIFT) + +#define FC_IS_WR_FIFO_FULL_SHIFT (6) +#define FC_IS_WR_FIFO_FULL_MASK (0x1U << FC_IS_WR_FIFO_FULL_SHIFT) + +#define FC_IS_WR_FIFO_EMPTY_SHIFT (5) +#define FC_IS_WR_FIFO_EMPTY_MASK (0x1U << FC_IS_WR_FIFO_EMPTY_SHIFT) + +#define FC_IS_WR_FIFO_READY_SHIFT (4) +#define FC_IS_WR_FIFO_READY_MASK (0x1U << FC_IS_WR_FIFO_READY_SHIFT) + +#define FC_IS_RD_FIFO_FULL_SHIFT (2) +#define FC_IS_RD_FIFO_FULL_MASK (0x1U << FC_IS_RD_FIFO_FULL_SHIFT) + +#define FC_IS_RD_FIFO_EMPTY_SHIFT (1) +#define FC_IS_RD_FIFO_EMPTY_MASK (0x1U << FC_IS_RD_FIFO_EMPTY_SHIFT) + +#define FC_IS_RD_FIFO_READY_SHIFT (0) +#define FC_IS_RD_FIFO_READY_MASK (0x1U << FC_IS_RD_FIFO_READY_SHIFT) + +#define FC_SW_SHIFT (0) +#define FC_SW_MASK (0xFFFFFFFFU << FC_SW_SHIFT) + +#define FC_SR_SHIFT (0) +#define FC_SR_MASK (0xFFFFFFFFU << FC_SR_SHIFT) + + +typedef struct { + uint8_t cs_begin; /*!< cs active to valid clk edge setup minimum time */ + uint8_t cs_over; /*!< valid clk edge to cs active hold minimum time */ + uint8_t cs_deselect; /*!< cs minimum deselect time after read */ + uint8_t cmd_over; + uint8_t addr_over; + uint8_t dummy_over; + uint8_t data; /*!< delay n half cycle */ +} Flash_Ctrl_DelayCycle; + +typedef enum { + XIP_MODE_NORMAL, + XIP_MODE_FAST, + XIP_MODE_DUAL_O, + XIP_MODE_DUAL_IO, + XIP_MODE_QUAD_O, + XIP_MODE_QUAD_IO +} XIP_Mode; + +typedef struct XIP_Instruction{ + uint8_t cmd; /*!< command */ + FC_CycleBits cmd_line; /*!< line mode of command */ + FC_CycleBits addr_line; /*!< line mode of address */ + FC_CycleBits dummy_line; /*!< line mode of dummy */ + FC_CycleBits data_line; /*!< line mode of data */ + uint32_t dum_btyes; /*!< dummy length */ +// uint32_t dummyh; +// uint32_t dummyl; +} XIP_Instruction; + +typedef struct { + uint32_t addr; /*!< XIP code started address in flash */ + uint32_t freq; /*!< flash working frequency */ + Flash_Ctrl_DelayCycle delay; /*!< board delay config */ + XIP_Instruction ins; /*!< XIP read instruction */ + bool cont_mode; /*!< continue mode or not */ +} XIP_Config; + +typedef struct Flashc_Config +{ + uint32_t freq; /*!< flash working frequency */ +// uint32_t t_shsl_ns; /*!< flash t_shsl parameter. for calculate the cs delay. */ +} Flashc_Config; + +typedef struct Flashc_Delay +{ + uint32_t t_shsl_ns; /*!< flash t_shsl parameter. for calculate the cs delay. */ +} Flashc_Delay; + +typedef struct FC_InstructionField +{ + uint8_t *pdata; /*!< instruction field: data */ + uint32_t len; /*!< instruction field: data len */ + FC_CycleBits line; /*!< instruction field: line mode */ +} FC_InstructionField; + +typedef enum Flashc_Commands +{ + /*TODO: tbc...*/ + Flashc_Commands_NOTHING +} Flashc_Commands; + +HAL_Status HAL_Flashc_Xip_Init(XIP_Config *cfg); +HAL_Status HAL_Flashc_Xip_Deinit(); +void HAL_Flashc_Xip_RawEnable(); +void HAL_Flashc_Xip_RawDisable(); +void HAL_Flashc_Xip_Enable(); +void HAL_Flashc_Xip_Disable(); + +HAL_Status HAL_Flashc_Init(const Flashc_Config *cfg); +HAL_Status HAL_Flashc_Deinit(); +HAL_Status HAL_Flashc_Open(); +HAL_Status HAL_Flashc_Close(); +HAL_Status HAL_Flashc_Control(Flashc_Commands op, void *arg); +HAL_Status HAL_Flashc_Write(FC_InstructionField *cmd, FC_InstructionField *addr, FC_InstructionField *dummy, FC_InstructionField *data, bool dma); +HAL_Status HAL_Flashc_Read(FC_InstructionField *cmd, FC_InstructionField *addr, FC_InstructionField *dummy, FC_InstructionField *data, bool dma); + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/platform/mcu/xr871/include/driver/chip/hal_global.h b/platform/mcu/xr871/include/driver/chip/hal_global.h new file mode 100644 index 0000000000..b73b7e4458 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_global.h @@ -0,0 +1,48 @@ +/** + * @file hal_global.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_GLOBAL_H_ +#define _DRIVER_CHIP_HAL_GLOBAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void HAL_GlobalInit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_GLOBAL_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_gpio.h b/platform/mcu/xr871/include/driver/chip/hal_gpio.h new file mode 100644 index 0000000000..1635684300 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_gpio.h @@ -0,0 +1,414 @@ +/** + * @file hal_gpio.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_GPIO_H_ +#define _DRIVER_CHIP_HAL_GPIO_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO control register block structure + */ +typedef struct { + __IO uint32_t MODE[4]; /* offset: 0x00, GPIO working mode configuration register */ + __IO uint32_t DATA; /* offset: 0x10, GPIO data register */ + __IO uint32_t DRIVING[2]; /* offset: 0x14, GPIO driving level register */ + __IO uint32_t PULL[2]; /* offset: 0x1C, GPIO pull type register */ +} GPIO_CTRL_T; + +/** + * @brief GPIO port definition + */ +typedef enum { + GPIO_PORT_A = 0U, + GPIO_PORT_B = 1U, + GPIO_PORT_NUM +} GPIO_Port; + +/** + * @brief GPIO working mode (function) definition + */ +typedef enum { + GPIOx_Pn_F0_INPUT = 0U, /* for all GPIO pins */ + GPIOx_Pn_F1_OUTPUT = 1U, /* for all GPIO pins */ + GPIOx_Pn_F6_EINT = 6U, /* for all GPIO pins */ + GPIOx_Pn_F7_DISABLE = 7U, /* for all GPIO pins */ + + GPIOA_P0_F2_SPI1_MOSI = 2U, + GPIOA_P0_F3_SD_CMD = 3U, + GPIOA_P0_F4_UART0_TX = 4U, + GPIOA_P0_F5_CSI_D0 = 5U, + GPIOA_P0_F6_EINTA0 = 6U, + + GPIOA_P1_F2_SPI1_MISO = 2U, + GPIOA_P1_F3_SD_DATA0 = 3U, + GPIOA_P1_F4_UART0_RX = 4U, + GPIOA_P1_F5_CSI_D1 = 5U, + GPIOA_P1_F6_EINTA1 = 6U, + + GPIOA_P2_F2_SPI1_CLK = 2U, + GPIOA_P2_F3_SD_CLK = 3U, + GPIOA_P2_F4_I2C1_SCL = 4U, + GPIOA_P2_F5_CSI_D2 = 5U, + GPIOA_P2_F6_EINTA2 = 6U, + + GPIOA_P3_F2_SPI1_CS0 = 2U, + GPIOA_P3_F3_SD_DATA1 = 3U, + GPIOA_P3_F4_I2C1_SDA = 4U, + GPIOA_P3_F5_CSI_D3 = 5U, + GPIOA_P3_F6_EINTA3 = 6U, + + GPIOA_P4_F2_UART1_CTS = 2U, + GPIOA_P4_F3_SD_DATA2 = 3U, + GPIOA_P4_F4_I2C0_SCL = 4U, + GPIOA_P4_F4_CSI_D4 = 5U, + GPIOA_P4_F6_EINTA4 = 6U, + + GPIOA_P5_F2_UART1_RTS = 2U, + GPIOA_P5_F3_SD_DATA3 = 3U, + GPIOA_P5_F4_I2C0_SDA = 4U, + GPIOA_P5_F5_CSI_D5 = 5U, + GPIOA_P5_F6_EINTA5 = 6U, + + GPIOA_P6_F2_UART1_TX = 2U, + GPIOA_P6_F3_SPI1_CS1 = 3U, + GPIOA_P6_F4_I2C0_SCL = 4U, + GPIOA_P6_F5_CSI_D6 = 5U, + GPIOA_P6_F6_EINTA6 = 6U, + + GPIOA_P7_F2_UART1_RX = 2U, + GPIOA_P7_F3_SPI1_CS2 = 3U, + GPIOA_P7_F4_I2C0_SDA = 4U, + GPIOA_P7_F5_CSI_D7 = 5U, + GPIOA_P7_F6_EINTA7 = 6U, + + GPIOA_P8_F2_ADC_CH0 = 2U, + GPIOA_P8_F3_PWM0_ECT0 = 3U, + GPIOA_P8_F4_I2C1_SCL = 4U, + GPIOA_P8_F5_CSI_PCLK = 5U, + GPIOA_P8_F6_EINTA8 = 6U, + + GPIOA_P9_F2_ADC_CH1 = 2U, + GPIOA_P9_F3_PWM1_ECT1 = 3U, + GPIOA_P9_F4_I2C1_SDA = 4U, + GPIOA_P9_F5_CSI_MCLK = 5U, + GPIOA_P9_F6_EINTA9 = 6U, + + GPIOA_P10_F2_ADC_CH2 = 2U, + GPIOA_P10_F3_PWM2_ECT2 = 3U, + GPIOA_P10_F4_DMIC_CLK = 4U, + GPIOA_P10_F5_CSI_HSYNC = 5U, + GPIOA_P10_F6_EINTA10 = 6U, + + GPIOA_P11_F2_ADC_CH3 = 2U, + GPIOA_P11_F3_PWM3_ECT3 = 3U, + GPIOA_P11_F4_DMIC_DATA = 4U, + GPIOA_P11_F5_CSI_VSYNC = 5U, + GPIOA_P11_F6_EINTA11 = 6U, + + GPIOA_P12_F2_ADC_CH4 = 2U, + GPIOA_P12_F3_PWM4_ECT4 = 3U, + GPIOA_P12_F4_I2S_MCLK = 4U, + GPIOA_P12_F5_IR_TX = 5U, + GPIOA_P12_F6_EINTA12 = 6U, + + GPIOA_P13_F2_ADC_CH5 = 2U, + GPIOA_P13_F3_PWM5_ECT5 = 3U, + GPIOA_P13_F4_I2S_BCLK = 4U, + GPIOA_P13_F6_EINTA13 = 6U, + + GPIOA_P14_F2_ADC_CH6 = 2U, + GPIOA_P14_F3_PWM6_ECT6 = 3U, + GPIOA_P14_F4_I2S_DI = 4U, + GPIOA_P14_F5_IR_RX = 5U, + GPIOA_P14_F6_EINTA14 = 6U, + + GPIOA_P15_F2_ADC_CH7 = 2U, + GPIOA_P15_F3_PWM7_ECT7 = 3U, + GPIOA_P15_F4_I2S_DO = 4U, + GPIOA_P15_F5_UART1_CTS = 5U, + GPIOA_P15_F6_EINTA15 = 6U, + + GPIOA_P16_F2_IR_TX = 2U, + GPIOA_P16_F3_IR_RX = 3U, + GPIOA_P16_F4_I2S_LRCLK = 4U, + GPIOA_P16_F5_UART1_RTS = 5U, + GPIOA_P16_F6_EINTA16 = 6U, + + GPIOA_P17_F2_I2C0_SCL = 2U, + GPIOA_P17_F3_IR_RX = 3U, + GPIOA_P17_F4_I2C1_SCL = 4U, + GPIOA_P17_F5_UART1_TX = 5U, + GPIOA_P17_F6_EINTA17 = 6U, + + GPIOA_P18_F2_I2C0_SDA = 2U, + GPIOA_P18_F3_IR_TX = 3U, + GPIOA_P18_F4_I2C1_SDA = 4U, + GPIOA_P18_F5_UART1_RX = 5U, + GPIOA_P18_F6_EINTA18 = 6U, + + GPIOA_P19_F2_NUART_CTS = 2U, + GPIOA_P19_F3_NSWD_TMS = 3U, + GPIOA_P19_F4_PWM0_ECT0 = 4U, + GPIOA_P19_F5_SPI1_MOSI = 5U, + GPIOA_P19_F6_EINTA19 = 6U, + + GPIOA_P20_F2_NUART_RTS = 2U, + GPIOA_P20_F3_NSWD_TCK = 3U, + GPIOA_P20_F4_PWM1_ECT1 = 4U, + GPIOA_P20_F5_SPI1_MISO = 5U, + GPIOA_P20_F6_EINTA20 = 6U, + + GPIOA_P21_F2_NUART_TX = 2U, + GPIOA_P21_F3_DMIC_CLK = 3U, + GPIOA_P21_F4_PWM2_ECT2 = 4U, + GPIOA_P21_F5_SPI1_CLK = 5U, + GPIOA_P21_F6_EINTA21 = 6U, + + GPIOA_P22_F2_NUART_RX = 2U, + GPIOA_P22_F3_DMIC_DATA = 3U, + GPIOA_P22_F4_PWM3_ECT3 = 4U, + GPIOA_P22_F5_SPI1_CS0 = 5U, + GPIOA_P22_F6_EINTA22 = 6U, + + GPIOB_P0_F2_UART0_TX = 2U, + GPIOB_P0_F3_JTAG_TMS = 3U, + GPIOB_P0_F4_PWM4_ECT4 = 4U, + GPIOB_P0_F5_SWD_TMS = 5U, + GPIOB_P0_F6_EINTB0 = 6U, + + GPIOB_P1_F2_UART0_RX = 2U, + GPIOB_P1_F3_JTAG_TCK = 3U, + GPIOB_P1_F4_PWM5_ECT5 = 4U, + GPIOB_P1_F5_SWD_TCK = 5U, + GPIOB_P1_F6_EINTB1 = 6U, + + GPIOB_P2_F2_SWD_TMS = 2U, + GPIOB_P2_F3_JTAG_TD0 = 3U, + GPIOB_P2_F4_PWM6_ECT6 = 4U, + GPIOB_P2_F5_FLASH_WP = 5U, + GPIOB_P2_F6_EINTB2 = 6U, + + GPIOB_P3_F2_SWD_TCK = 2U, + GPIOB_P3_F3_JTAG_TDI = 3U, + GPIOB_P3_F4_PWM7_ECT7 = 4U, + GPIOB_P3_F5_FLASH_HOLD = 5U, + GPIOB_P3_F6_EINTB3 = 6U, + + GPIOB_P4_F2_SPI0_MOSI = 2U, + GPIOB_P4_F3_SD_CMD = 3U, + GPIOB_P4_F5_FLASH_MOSI = 5U, + GPIOB_P4_F6_EINTB4 = 6U, + + GPIOB_P5_F2_SPI0_MISO = 2U, + GPIOB_P5_F3_SD_DATA0 = 3U, + GPIOB_P5_F5_FLASH_MISO = 5U, + GPIOB_P5_F6_EINTB5 = 6U, + + GPIOB_P6_F2_SPI0_CS0 = 2U, + GPIOB_P6_F5_FLASH_CS = 5U, + GPIOB_P6_F6_EINTB6 = 6U, + + GPIOB_P7_F2_SPI0_CLK = 2U, + GPIOB_P7_F3_SD_CLK = 3U, + GPIOB_P7_F5_FLASH_CLK = 5U, + GPIOB_P7_F6_EINTB7 = 6U, +} GPIO_WorkMode; + +/** + * @brief GPIO driving level definition + */ +typedef enum { + GPIO_DRIVING_LEVEL_0 = 0U, + GPIO_DRIVING_LEVEL_1 = 1U, + GPIO_DRIVING_LEVEL_2 = 2U, + GPIO_DRIVING_LEVEL_3 = 3U +} GPIO_DrivingLevel; + +/** + * @brief GPIO pull type definition + */ +typedef enum { + GPIO_PULL_NONE = 0U, + GPIO_PULL_UP = 1U, + GPIO_PULL_DOWN = 2U +} GPIO_PullType; + +/** + * @brief GPIO interrupt register block structure + */ +typedef struct { + __IO uint32_t IRQ_MODE[4]; /* offset: 0x00, GPIO interrupt configuration register */ + __IO uint32_t IRQ_EN; /* offset: 0x10, GPIO interrupt enable register */ + __IO uint32_t IRQ_STATUS; /* offset: 0x14, GPIO interrupt status register */ + __IO uint32_t IRQ_DEBOUNCE; /* offset: 0x18, GPIO interrupt debounce register */ +} GPIO_IRQ_T; + +/** + * @brief GPIO interrupt trigger event definition + */ +typedef enum { + GPIO_IRQ_EVT_RISING_EDGE = 0U, + GPIO_IRQ_EVT_FALLING_EDGE = 1U, + GPIO_IRQ_EVT_HIGH_LEVEL = 2U, + GPIO_IRQ_EVT_LOW_LEVEL = 3U, + GPIO_IRQ_EVT_BOTH_EDGE = 4U +} GPIO_IrqEvent; + +/* GPIO interrupt debounce value */ +#define GPIO_IRQ_DEB_CLK_SCALE_SHIFT 4 /* R/W */ +#define GPIO_IRQ_DEB_CLK_SCALE_MASK (0x7U << GPIO_IRQ_DEB_CLK_SCALE_SHIFT) + +#define GPIO_IRQ_DEB_CLK_SRC_SHIFT 0 /* R/W */ +#define GPIO_IRQ_DEB_CLK_SRC_MASK (0x1U << GPIO_IRQ_DEB_CLK_SRC_SHIFT) +typedef enum { + GPIO_IRQ_DEB_CLK_SRC_LFCLK = 0U, + GPIO_IRQ_DEB_CLK_SRC_HFCLK = 1U +} GPIO_IrqDebounceClkSrc; + +/******************************************************************************/ + +/** + * @brief GPIO pin state definition + */ +typedef enum { + GPIO_PIN_LOW = 0, + GPIO_PIN_HIGH = 1, +} GPIO_PinState; + +/** + * @brief GPIO pin number definition + * - GPIOA: pin [0:23] + * - GPIOB: pin [0:7] + */ +typedef enum { + GPIO_PIN_0 = 0U, + GPIO_PIN_1 = 1U, + GPIO_PIN_2 = 2U, + GPIO_PIN_3 = 3U, + GPIO_PIN_4 = 4U, + GPIO_PIN_5 = 5U, + GPIO_PIN_6 = 6U, + GPIO_PIN_7 = 7U, + GPIO_PIN_8 = 8U, + GPIO_PIN_9 = 9U, + GPIO_PIN_10 = 10U, + GPIO_PIN_11 = 11U, + GPIO_PIN_12 = 12U, + GPIO_PIN_13 = 13U, + GPIO_PIN_14 = 14U, + GPIO_PIN_15 = 15U, + GPIO_PIN_16 = 16U, + GPIO_PIN_17 = 17U, + GPIO_PIN_18 = 18U, + GPIO_PIN_19 = 19U, + GPIO_PIN_20 = 20U, + GPIO_PIN_21 = 21U, + GPIO_PIN_22 = 22U, + + GPIOA_PIN_NUM = 23U, + GPIOB_PIN_NUM = 8U +} GPIO_Pin; + +/** + * @brief Wakeup I/O of GPIO port A definition + */ +typedef enum { + WAKEUP_IO0 = GPIO_PIN_4, + WAKEUP_IO1 = GPIO_PIN_5, + WAKEUP_IO2 = GPIO_PIN_6, + WAKEUP_IO3 = GPIO_PIN_7, + WAKEUP_IO4 = GPIO_PIN_17, + WAKEUP_IO5 = GPIO_PIN_18, + WAKEUP_IO6 = GPIO_PIN_19, + WAKEUP_IO7 = GPIO_PIN_20, + WAKEUP_IO8 = GPIO_PIN_21, + WAKEUP_IO9 = GPIO_PIN_22, + WAKEUP_IO_MAX = 10, /* keep last */ +} WAKEUP_IO; + +/** + * @brief GPIO initialization parameters + */ +typedef struct { + GPIO_WorkMode mode; + GPIO_DrivingLevel driving; + GPIO_PullType pull; +} GPIO_InitParam; + +/** + * @brief GPIO pinmux configuration parameters + */ +typedef struct { + GPIO_Port port; + GPIO_Pin pin; + GPIO_InitParam config; +} GPIO_PinMuxParam; + +/** @brief Type define of GPIO IRQ callback function */ +typedef void (*GPIO_IRQCallback) (void *arg); + +/** + * @brief GPIO interrupt enable parameters + */ +typedef struct { + GPIO_IrqEvent event; + GPIO_IRQCallback callback; + void *arg; +} GPIO_IrqParam; + +void HAL_GPIO_Init(GPIO_Port port, GPIO_Pin pin, const GPIO_InitParam *param); +void HAL_GPIO_DeInit(GPIO_Port port, GPIO_Pin pin); + +void HAL_GPIO_WritePin(GPIO_Port port, GPIO_Pin pin, GPIO_PinState state); +GPIO_PinState HAL_GPIO_ReadPin(GPIO_Port port, GPIO_Pin pin); + +void HAL_GPIO_WritePort(GPIO_Port port, uint32_t portMask); +uint32_t HAL_GPIO_ReadPort(GPIO_Port port); + +void HAL_GPIO_EnableIRQ(GPIO_Port port, GPIO_Pin pin, const GPIO_IrqParam *param); +void HAL_GPIO_DisableIRQ(GPIO_Port port, GPIO_Pin pin); + +void HAL_GPIO_PinMuxConfig(const GPIO_PinMuxParam *param, uint32_t count); +void HAL_GPIO_PinMuxDeConfig(const GPIO_PinMuxParam *param, uint32_t count); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_GPIO_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_i2c.h b/platform/mcu/xr871/include/driver/chip/hal_i2c.h new file mode 100644 index 0000000000..bd5d2ef704 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_i2c.h @@ -0,0 +1,190 @@ +/** + * @file hal_i2c.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_I2C_H_ +#define _DRIVER_CHIP_HAL_I2C_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief I2C ID definition + */ +typedef enum { + I2C0_ID = 0, + I2C1_ID = 1, + I2C_NUM = 2 +} I2C_ID; + +/** + * @brief I2C register block structure + */ +typedef struct { + __IO uint32_t I2C_ADDR; /* offset: 0x00, I2C slave address register */ + __IO uint32_t I2C_XADDR; /* offset: 0x04, I2C extend slave address register */ + __IO uint32_t I2C_DATA; /* offset: 0x08, I2C data register */ + __IO uint32_t I2C_CTRL; /* offset: 0x0C, I2C control register */ + __I uint32_t I2C_STATUS; /* offset: 0x10, I2C status register */ + __IO uint32_t I2C_CLK_CTRL; /* offset: 0x14, I2C clock register */ + __IO uint32_t I2C_SOFT_RST; /* offset: 0x18, I2C software reset register */ + __IO uint32_t I2C_EFR; /* offset: 0x1C, I2C enhance feature register */ + __IO uint32_t I2C_LINE_CTRL; /* offset: 0x20, I2C line control register */ +} I2C_T; + +#define I2C0 ((I2C_T *)I2C0_BASE) /* address: 0x40041C00 */ +#define I2C1 ((I2C_T *)I2C1_BASE) /* address: 0x40042000 */ + +/* I2Cx->I2C_ADDR, R/W */ +#define I2C_SLAVE_ADDR_SHIFT 1 +#define I2C_SLAVE_ADDR_MASK (0x7FU << I2C_SLAVE_ADDR_SHIFT) + +#define I2C_GCE_BIT HAL_BIT(0) + +/* I2Cx->I2C_XADDR, R/W */ +#define I2C_SLAVE_XADDR_MASK 0xFFU + +/* I2Cx->I2C_DATA, R/W */ +#define I2C_DATA_MASK 0xFFU + +/* I2Cx->I2C_CTRL, R/W */ +#define I2C_IRQ_EN_BIT HAL_BIT(7) +#define I2C_BUS_EN_BIT HAL_BIT(6) +#define I2C_START_BIT HAL_BIT(5) +#define I2C_STOP_BIT HAL_BIT(4) +#define I2C_IRQ_FLAG_BIT HAL_BIT(3) +#define I2C_ACK_EN_BIT HAL_BIT(2) + +#define I2C_WR_CTRL_MASK (I2C_START_BIT | I2C_STOP_BIT | I2C_IRQ_FLAG_BIT) + +/* I2Cx->I2C_STATUS, R */ +#define I2C_STATUS_MASK 0xFFU + +typedef enum { + I2C_BUS_ERROR = 0x00U, /* bus error */ + I2C_START_TRAN = 0x08U, /* start condition transmitted */ + I2C_RE_START_TRAN = 0x10U, /* repeated start condition transmitted */ + I2C_ADDR_WR_TRAN_ACK = 0x18U, /* address + write bit transmitted, ACK received */ + I2C_ADDR_WR_TRAN_NACK = 0x20U, /* address + write bit transmitted, ACK not received */ + I2C_MASTER_DATA_TRAN_ACK = 0x28U, /* data byte transmitted in master mode, ACK received */ + I2C_MASTER_DATA_TRAN_NACK = 0x30U, /* data byte transmitted in master mode, ACK not received */ + I2C_ARB_LOST = 0x38U, /* arbitration lost in address or data byte */ + I2C_ADDR_RD_TRAN_ACK = 0x40U, /* address + read bit transmitted, ACK received */ + I2C_ADDR_RD_TRAN_NACK = 0x48U, /* address + read bit transmitted, ACK not received */ + I2C_MASTER_DATA_RECV_ACK = 0x50U, /* data byte received in master mode, ACK transmitted */ + I2C_MASTER_DATA_RECV_NACK = 0x58U, /* data byte received in master mode, ACK not transmitted */ + I2C_ADDR_WR_RECV_ACK = 0x60U, /* slave address + write bit received, ACK transmitted */ + I2C_ARB_LOST_ADDR_WR = 0x68U, /* arbitration lost in address as master, slave address + write bit received, ACK transmitted */ + I2C_GC_ADDR_RECV = 0x70U, /* general call adress received, ACK transmitted */ + I2C_ARB_LOST_GC_ADDR = 0x78U, /* arbitration lost in address as master, general call address received, ACK transmitted */ + I2C_DATA_RECV_SLAVE_ACK = 0x80U, /* data byte received after slave address received, ACK transmitted */ + I2C_DATA_RECV_SLAVE_NACK = 0x88U, /* data byte reveived after slave address received, ACK not transmitted */ + I2C_DATA_RECV_GC_ACK = 0x90U, /* data byte received after general call received, ACK transmitted */ + I2C_DATA_RECV_GC_NACK = 0x98U, /* data byte received after general call received, ACK not transmitted */ + I2C_STOP_RE_START_RECV = 0xA0U, /* stop or repeated start condition received in slave mode */ + I2C_ADDR_RD_RECV_ACK = 0xA8U, /* slave address + read bit received, ACK transmitted */ + I2C_ARB_LOST_ADDR_RD = 0xB0U, /* arbitration lost in address as master, slave address + read bit received, ACK transmitted */ + I2C_SLAVE_DATA_TRAN_ACK = 0xB8U, /* data byte transmitted in slave mode, ACK received */ + I2C_SLAVE_DATA_TRAN_NACK = 0xC0U, /* data byte transmitted in slave mode, ACK not received */ + I2C_SLAVE_LAST_TRAN_ACK = 0xC8U, /* last byte transmitted in slave mode, ACK received */ + I2C_SEC_ADDR_WR_ACK = 0xD0U, /* second address byte + write bit transmitted, ACK received */ + I2C_SEC_ADDR_WR_NACK = 0xD8U, /* second address byte + write bit transmitted, ACK not received */ + I2C_NO_STATUS_INFO = 0xF8U /* no relevant status information, IRQ_FLAG = 0 */ +} I2C_IRQStatus; + +/* I2Cx->I2C_CLK_CTRL, R/W */ +#define I2C_CLK_M_SHIFT 3 +#define I2C_CLK_M_MASK (0xFU << I2C_CLK_M_SHIFT) +#define I2C_CLK_M_MAX 15 + +#define I2C_CLK_N_SHIFT 0 +#define I2C_CLK_N_MASK (0x7U << I2C_CLK_N_SHIFT) +#define I2C_CLK_N_MAX 7 + +/* I2Cx->I2C_SOFT_RST, R/W */ +#define I2C_SOFT_RST_BIT HAL_BIT(0) + +/* I2Cx->I2C_EFR, R/W */ +#define I2C_DATA_BYTE_MASK 0x3U +typedef enum { + I2C_DATA_BYTE_0 = 0U, + I2C_DATA_BYTE_1 = 1U, + I2C_DATA_BYTE_2 = 2U, + I2C_DATA_BYTE_3 = 3U +} I2C_DataByte; + +/* I2Cx->I2C_LINE_CTRL, R/W */ +#define I2C_SCL_STATE_BIT HAL_BIT(5) +#define I2C_SDA_STATE_BIT HAL_BIT(4) +#define I2C_SCL_CTRL_BIT HAL_BIT(3) +#define I2C_SCL_CTRL_EN_BIT HAL_BIT(2) +#define I2C_SDA_CTRL_BIT HAL_BIT(1) +#define I2C_SDA_CTRL_EN_BIT HAL_BIT(0) + +/******************************************************************************/ + +/** + * @brief I2C addressing mode + */ +typedef enum { + I2C_ADDR_MODE_7BIT = 0U, /* 7-bit addressing mode */ + I2C_ADDR_MODE_10BIT = 1U /* 10-bit addressing mode */ +} I2C_AddrMode; + +/** + * @brief I2C initialization parameters + */ +typedef struct { + I2C_AddrMode addrMode; /* addressing mode */ + uint32_t clockFreq; /* clock frequency */ +} I2C_InitParam; + +HAL_Status HAL_I2C_Init(I2C_ID i2cID, const I2C_InitParam *initParam); +HAL_Status HAL_I2C_DeInit(I2C_ID i2cID); + +int32_t HAL_I2C_Master_Transmit_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t *buf, int32_t size); +int32_t HAL_I2C_Master_Receive_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t *buf, int32_t size); +int32_t HAL_I2C_Master_Transmit_Mem_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size); +int32_t HAL_I2C_Master_Receive_Mem_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size); + +int32_t HAL_I2C_SCCB_Master_Transmit_IT(I2C_ID i2cID, uint8_t devAddr, uint8_t subAddr, uint8_t *buf); +int32_t HAL_I2C_SCCB_Master_Receive_IT(I2C_ID i2cID, uint8_t devAddr, uint8_t subAddr, uint8_t *buf); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_I2C_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_i2s.h b/platform/mcu/xr871/include/driver/chip/hal_i2s.h new file mode 100644 index 0000000000..ee9198bcb5 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_i2s.h @@ -0,0 +1,523 @@ +/** + * @file hal_i2s.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_I2S_H_ +#define _DRIVER_CHIP_HAL_I2S_H_ + +#include +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_audio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Digital Audio Controller + */ +typedef struct +{ + __IO uint32_t DA_CTL; /* I2S Control Register, Address offset: 0x00 */ + __IO uint32_t DA_FMT0; /* I2S Format Register0, Address offset: 0x04 */ + __IO uint32_t DA_FMT1; /* I2S Format Register1, Address offset: 0x08 */ + __IO uint32_t DA_ISTA; /* I2S Interrupt Status Register, Address offset: 0x0C */ + uint32_t DA_RXFIFO; /* I2S RX FIFO Register, Address offset: 0x10 */ + __IO uint32_t DA_FCTL; /* I2S FIFO Control Register, Address offset: 0x14 */ + __I uint32_t DA_FSTA; /* I2S FIFO Stauts Register, Address offset: 0x18 */ + __IO uint32_t DA_INT; /* I2S DMA&Interrupt Control Register, Address offset: 0x1C */ + __O uint32_t DA_TXFIFO; /* I2S TX FIFO Register, Address offset: 0x20 */ + __IO uint32_t DA_CLKD; /* I2S Clock Divide Register, ddress offset: 0x24 */ + __IO uint32_t DA_TXCNT; /* I2S TX Sample Counter Register, Address offset: 0x28 */ + __IO uint32_t DA_RXCNT; /* I2S RX Sample Counter Register, Address offset: 0x2C */ + __IO uint32_t DA_CHCFG; /* I2S Channel Configuration Register, Address offset: 0x30 */ + __IO uint32_t DA_TX0CHSEL; /* I2S TX0 Channel Select Register, Address offset: 0x34 */ + __IO uint32_t DA_TX1CHSEL; /* I2S TX1 Channel Select Register, Address offset: 0x38 */ + __IO uint32_t DA_TX2CHSEL; /* I2S TX2 Channel Select Register, Address offset: 0x3C */ + __IO uint32_t DA_TX3CHSEL; /* I2S TX3 Channel Select Register, Address offset: 0x40 */ + __IO uint32_t DA_TX0CHMAP; /* I2S TX0 Channel Mapping Register, Address offset: 0x44 */ + __IO uint32_t DA_TX1CHMAP; /* I2S TX1 Channel Mapping Register, Address offset: 0x48 */ + __IO uint32_t DA_TX2CHMAP; /* I2S TX2 Channel Mapping Register, Address offset: 0x4C */ + __IO uint32_t DA_TX3CHMAP; /* I2S TX3 Channel Mapping Register, Address offset: 0x50 */ + __IO uint32_t DA_RXCHSEL; /* I2S RX Channel Select Register, Address offset: 0x54 */ + __IO uint32_t DA_RXCHMAP; /* I2S RX Channel Mapping Register, Address offset: 0x58 */ +} I2S_T; + +#define I2S ((I2S_T *)I2S_BASE) + +/* + * Bits definition for I2S_CTL Control Register (0X0000) + */ +#define I2S_GLOBE_EN_BIT HAL_BIT(0) +#define I2S_RX_EN_BIT HAL_BIT(1) +#define I2S_TX_EN_BIT HAL_BIT(2) +#define I2S_LOOP_TSET_EN_EN_BIT HAL_BIT(3) + +#define I2S_MODE_SEL_SHIFT (4) +#define I2S_MODE_SEL_MASK (0x3 << I2S_MODE_SEL_SHIFT) +typedef enum { + I2S_PCM_MODE = (0x0U << I2S_MODE_SEL_SHIFT), + I2S_LEFT_MODE = (0x1U << I2S_MODE_SEL_SHIFT), + I2S_RIGHT_MODE = (0x2U << I2S_MODE_SEL_SHIFT), + RESERVE_VAL = (0x3U << I2S_MODE_SEL_SHIFT) +} I2S_Mode; + +#define I2S_OUT_MUTE_SHIFT (6) +#define I2S_OUT_MUTE_MASK (0x1U << I2S_OUT_MUTE_SHIFT) +typedef enum { + I2S_NOR_TRANSFER = (0x0U << I2S_OUT_MUTE_SHIFT), + I2S_OUT_MUTE = (0x1U << I2S_OUT_MUTE_SHIFT), +} I2S_DoutMute; + +#define I2S_SDO0_EN_BIT HAL_BIT(8) + +#define I2S_LRCK_OUT_SHIFT (17) +#define I2S_LRCK_OUT_MASK (0x1U << I2S_LRCK_OUT_SHIFT) +typedef enum { + I2S_LRCK_INPUT = (0x0U << I2S_LRCK_OUT_SHIFT), + I2S_LRCK_OUTPUT = (0x1U << I2S_LRCK_OUT_SHIFT), +} I2S_LrckMode; + +#define I2S_BCLK_OUT_SHIFT (18) +#define I2S_BCLK_OUT_MASK (0x1U << I2S_BCLK_OUT_SHIFT) +typedef enum { + I2S_BCLK_INPUT = (0x0U << I2S_BCLK_OUT_SHIFT), + I2S_BCLK_OUTPUT = (0x1U << I2S_BCLK_OUT_SHIFT), +} I2S_BclkMode; + +/* + * Bits definition for I2S_FMT0 Format Register0(0x0004) + */ +#define I2S_SW_SEC_SHIFT (0) +#define I2S_SW_SEC_MASK (0x1U << I2S_SW_SEC_SHIFT) +typedef enum { + I2S_SLOT_WIDTH_BIT8 = (0x1U << I2S_SW_SEC_SHIFT), + I2S_SLOT_WIDTH_BIT12 = (0x2U << I2S_SW_SEC_SHIFT), + I2S_SLOT_WIDTH_BIT16 = (0x3U << I2S_SW_SEC_SHIFT), + I2S_SLOT_WIDTH_BIT20 = (0x4U << I2S_SW_SEC_SHIFT), + I2S_SLOT_WIDTH_BIT24 = (0x5U << I2S_SW_SEC_SHIFT), + I2S_SLOT_WIDTH_BIT28 = (0x6U << I2S_SW_SEC_SHIFT), + I2S_SLOT_WIDTH_BIT32 = (0x7U << I2S_SW_SEC_SHIFT), +} I2S_SlotWidth; + +#define I2S_EDGE_TRANSFER_SHIFT (3) +#define I2S_EDGE_TRANSFER_MASK (0x1U << I2S_EDGE_TRANSFER_SHIFT) +typedef enum { + I2S_SEC_NEGATIVE_EDGE = (0x0U << I2S_EDGE_TRANSFER_SHIFT), + I2S_SEC_POSITIVE_EDGE = (0x1U << I2S_EDGE_TRANSFER_SHIFT), +} I2S_EdgeTransfer; + +#define I2S_SR_SHIFT (4) +#define I2S_SR_MASK (0x7U << I2S_SR_SHIFT) +/** + * @brief sampling accuracy + */ +typedef enum { + I2S_SR8BIT = (0x1U << I2S_SR_SHIFT), + I2S_SR12BIT = (0x2U << I2S_SR_SHIFT), + I2S_SR16BIT = (0x3U << I2S_SR_SHIFT), + I2S_SR20BIT = (0x4U << I2S_SR_SHIFT), + I2S_SR24BIT = (0x5U << I2S_SR_SHIFT), + I2S_SR28BIT = (0x6U << I2S_SR_SHIFT), + I2S_SR32BIT = (0x7U << I2S_SR_SHIFT), +} I2S_SampleResolution; + +#define I2S_BCLK_POLARITY_SHIFT (7) +#define I2S_BCLK_POLARITY_MASK (0x1U << I2S_BCLK_POLARITY_SHIFT) +typedef enum { + I2S_SEC_NOR_MODE = (0x0U << I2S_BCLK_POLARITY_SHIFT), + I2S_SEC_INVERT_MODE = (0x1U << I2S_BCLK_POLARITY_SHIFT), +} I2S_BclkPolarity; + +#define I2S_LRCK_PERIOD_SHIFT (8) +#define I2S_LRCK_PERIOD_MASK (0x3FFU << I2S_LRCK_PERIOD_SHIFT) +#define I2S_LRCK_PERIOD(n) ((n-1) << I2S_LRCK_PERIOD_SHIFT) + +#define I2S_LRCK_POLARITY_SHIFT (19) +#define I2S_LRCK_POLARITY_MASK (0x1U << I2S_LRCK_POLARITY_SHIFT) +typedef enum { + I2S_LEFTCHANNEL_LRCKLOW = (0x0U << I2S_LRCK_POLARITY_SHIFT), + I2S_LEFTCHANNEL_LRCKHIGH = (0x1U << I2S_BCLK_POLARITY_SHIFT), +} I2S_LrckPolarity; + + +#define I2S_LRCK_WIDTH_SHIFT (30) +#define I2S_LRCK_WIDTH_MASK (0x1U << I2S_LRCK_WIDTH_SHIFT) +/** + * @brief frame mode + */ +typedef enum { + I2S_SHORT_FRAME = (0x0U << I2S_LRCK_WIDTH_SHIFT), + I2S_LONG_FRAME = (0x1U << I2S_LRCK_WIDTH_SHIFT), +} I2S_FrameMode; + +/* + * Bits definition for I2S_FMT1 Format Register1 (0X0008) + */ +#define I2S_PCM_TXMODE_SHIFT (0) +#define I2S_PCM_TXMODE_MASK (0x3U << I2S_PCM_TXMODE_SHIFT) +typedef enum { + I2S_TX_LINEAR_PCM = (0x0U << I2S_PCM_TXMODE_SHIFT), + I2S_TX_PCM_NOVAL = (0x1U << I2S_PCM_TXMODE_SHIFT), + I2S_TX_PCM_ULAW_BIT8 = (0x2U << I2S_PCM_TXMODE_SHIFT), + I2S_TX_PCM_ALAW_BIT8 = (0x3U << I2S_PCM_TXMODE_SHIFT), +} I2S_TXPDM; + +#define I2S_PCM_RXMODE_SHIFT (2) +#define I2S_PCM_RXMODE_MASK (0x3U << I2S_PCM_RXMODE_SHIFT) +typedef enum { + I2S_RX_LINEAR_PCM = (0U << I2S_PCM_RXMODE_SHIFT), + I2S_RX_PCM_NOVAL = (1U << I2S_PCM_RXMODE_SHIFT), + I2S_RX_PCM_ULAW_BIT8 = (2U << I2S_PCM_RXMODE_SHIFT), + I2S_RX_PCM_ALAW_BIT8 = (3U << I2S_PCM_RXMODE_SHIFT), +} I2S_RXPDM; + +#define I2S_SEXT_SHIFT (4) +#define I2S_SEXT_MASK (0x3U << I2S_SEXT_SHIFT) +typedef enum { + I2S_PADDING_LSB = (0x0U << I2S_SEXT_SHIFT), + I2S_SIGN_MSB = (0x1U << I2S_SEXT_SHIFT), + I2S_NO_SEXT_VAL = (0x2U << I2S_SEXT_SHIFT), + I2S_ZERO_SLOT = (0x3U << I2S_SEXT_SHIFT), +} I2S_SEXT; + +#define I2S_TX_MLS_SHIFT (6) +#define I2S_TX_MLS_MASK (0x1U << I2S_TX_MLS_SHIFT) +typedef enum { + I2S_TX_MSB_FIRST = (0x0U << I2S_TX_MLS_SHIFT), + I2S_TX_LSB_FIRST = (0x1U << I2S_TX_MLS_SHIFT), +} I2S_TxMLS; + +#define I2S_RX_MLS_SHIFT (7) +#define I2S_RX_MLS_MASK (0x1U << I2S_RX_MLS_SHIFT) +typedef enum { + I2S_RX_MSB_FIRST = (0x0U << I2S_RX_MLS_SHIFT), + I2S_RX_LSB_FIRST = (0x1U << I2S_RX_MLS_SHIFT), +} I2S_RxMLS; + +/* + * Bits definition for I2S_ISTA Interrupt Status Register + */ +#define I2S_RX_FIFO_AVABLE_IT_BIT HAL_BIT(0) +#define I2S_RX_FIFO_OVERRUN_IT_BIT HAL_BIT(1) +#define I2S_RX_FIFO_UNDERRUN_IT_BIT HAL_BIT(2) +#define I2S_TX_FIFO_EMPTY_IT_BIT HAL_BIT(4) +#define I2S_TX_FIFO_OVERRUN_IT_BIT HAL_BIT(5) +#define I2S_TX_FIFO_UNDERRUN_IT_BIT HAL_BIT(6) + +/* + * Bits definition for I2S_FCTL FIFO Control Register (0x0014) + */ +#define I2S_RX_FIFO_MODE_SHIFT (0) +#define I2S_RX_FIFO_MODE_MASK (0x3U << I2S_RX_FIFO_MODE_SHIFT) +typedef enum { + I2S_RX_FIFO_MODE0 = (0x0U << I2S_RX_FIFO_MODE_SHIFT), + I2S_RX_FIFO_MODE1 = (0x1U << I2S_RX_FIFO_MODE_SHIFT), + I2S_RX_FIFO_MODE2 = (0x2U << I2S_RX_FIFO_MODE_SHIFT), + I2S_RX_FIFO_MODE3 = (0x3U << I2S_RX_FIFO_MODE_SHIFT), +} I2S_RXOM; + +#define I2S_TX_FIFO_MODE_SHIFT (2) +#define I2S_TX_FIFO_MODE_MASK (0x1U << I2S_TX_FIFO_MODE_SHIFT) +typedef enum { + I2S_TX_FIFO_MODE0 = (0x0U << I2S_TX_FIFO_MODE_SHIFT), + I2S_TX_FIFO_MODE1 = (0x1U << I2S_TX_FIFO_MODE_SHIFT), +} I2S_TXIM; + +#define I2S_RXFIFO_LEVEL_SHIFT (4) +#define I2S_RXFIFO_LEVEL_MASK (0x3FU << I2S_RXFIFO_LEVEL_SHIFT) +#define I2S_RXFIFO_TRIGGER_LEVEL(n) ((n+1) << I2S_RXFIFO_LEVEL_SHIFT) + +#define I2S_TXFIFO_LEVEL_SHIFT (12) +#define I2S_TXFIFO_LEVEL_MASK (0x7FU << I2S_TXFIFO_LEVEL_SHIFT) +#define I2S_TXFIFO_TRIGGER_LEVEL(n) ((n+1) << I2S_TXFIFO_LEVEL_SHIFT) + +#define I2S_RXFIFO_RESET_BIT HAL_BIT(24) +#define I2S_TXFIFO_RESET_BIT HAL_BIT(25) +#define I2S_HUB_EN_BIT HAL_BIT(31) + +/* + * Bits definition for I2S_FSTA FIFO Status Register + */ +#define I2S_RXFIFO_CNT_SHIFT (0) +#define I2S_RXFIFO_CNT_MASK (0x7FU << I2S_RXFIFO_CNT_SHIFT) + +#define I2S_RXFIFO_AVAILABLE_BIT HAL_BIT(8) + +#define I2S_TXFIFO_EMPTY_SHIFT (16) +#define I2S_TXFIFO_EMPTY_MASK (0xFFU << I2S_TXFIFO_EMPTY_SHIFT) + +#define I2S_TXFIFO_EMPTY_BIT HAL_BIT(28) + +/* + * Bits definition for I2S_INT DMA&Interrupt Control Register (0x001c) + */ +#define I2S_RXFIFO_AVABLE_ITEN_BIT HAL_BIT(0) +#define I2S_RXFIFO_OVERRUN_ITEN_BIT HAL_BIT(1) +#define I2S_RXFIFO_UNDERRUN_ITEN_BIT HAL_BIT(2) +#define I2S_RXFIFO_DMA_ITEN_BIT HAL_BIT(3) +#define I2S_TXFIFO_EMPTY_ITEN_BIT HAL_BIT(4) +#define I2S_TXFIFO_OVERRUN_ITEN_BIT HAL_BIT(5) +#define I2S_TXFIFO_UNDERRUN_ITEN_BIT HAL_BIT(6) +#define I2S_TXFIFO_DMA_ITEN_BIT HAL_BIT(7) + +/* + * Bits definition for I2S_CLKD Clock Divide Register (0x24) + */ +#define I2S_MCLKDIV_SHIFT (0) +#define I2S_MCLKDIV_MASK (0xFU << I2S_MCLKDIV_SHIFT) /* MCLK divide ratio [3:0] */ +typedef enum { + I2S_MCLKDIV_1 = (0x1U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 1 */ + I2S_MCLKDIV_2 = (0x2U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 2 */ + I2S_MCLKDIV_4 = (0x3U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 4 */ + I2S_MCLKDIV_6 = (0x4U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 6 */ + I2S_MCLKDIV_8 = (0x5U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 8 */ + I2S_MCLKDIV_12 = (0x6U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 12 */ + I2S_MCLKDIV_16 = (0x7U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 16 */ + I2S_MCLKDIV_24 = (0x8U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 24 */ + I2S_MCLKDIV_32 = (0x9U << I2S_MCLKDIV_SHIFT), /* MCLK divide by 32 */ + I2S_MCLKDIV_48 = (0xAU << I2S_MCLKDIV_SHIFT), /* MCLK divide by 48 */ + I2S_MCLKDIV_64 = (0xBU << I2S_MCLKDIV_SHIFT), /* MCLK divide by 64 */ + I2S_MCLKDIV_96 = (0xCU << I2S_MCLKDIV_SHIFT), /* MCLK divide by 96 */ + I2S_MCLKDIV_128 = (0xDU << I2S_MCLKDIV_SHIFT), /* MCLK divide by 128 */ + I2S_MCLKDIV_176 = (0xEU << I2S_MCLKDIV_SHIFT), /* MCLK divide by 176 */ + I2S_MCLKDIV_192 = (0xFU << I2S_MCLKDIV_SHIFT), /* MCLK divide by 192 */ +} I2S_MCLKDIV; + +#define I2S_BCLKDIV_SHIFT (4) +#define I2S_BCLKDIV_MASK (0xFU << I2S_BCLKDIV_SHIFT) /* BCLK divide ratio [3:0] */ +typedef enum { + I2S_BCLKDIV_1 = (0x1U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 1 */ + I2S_BCLKDIV_2 = (0x2U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 2 */ + I2S_BCLKDIV_4 = (0x3U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 4 */ + I2S_BCLKDIV_6 = (0x4U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 6 */ + I2S_BCLKDIV_8 = (0x5U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 8 */ + I2S_BCLKDIV_12 = (0x6U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 12 */ + I2S_BCLKDIV_16 = (0x7U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 16 */ + I2S_BCLKDIV_24 = (0x8U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 24 */ + I2S_BCLKDIV_32 = (0x9U << I2S_BCLKDIV_SHIFT), /* BCLK divide by 32 */ + I2S_BCLKDIV_48 = (0xAU << I2S_BCLKDIV_SHIFT), /* BCLK divide by 48 */ + I2S_BCLKDIV_64 = (0xBU << I2S_BCLKDIV_SHIFT), /* BCLK divide by 64 */ + I2S_BCLKDIV_96 = (0xCU << I2S_BCLKDIV_SHIFT), /* BCLK divide by 96 */ + I2S_BCLKDIV_128 = (0xDU << I2S_BCLKDIV_SHIFT), /* BCLK divide by 128 */ + I2S_BCLKDIV_176 = (0xEU << I2S_BCLKDIV_SHIFT), /* BCLK divide by 176 */ + I2S_BCLKDIV_192 = (0xFU << I2S_BCLKDIV_SHIFT), /* BCLK divide by 192 */ +} I2S_BCLKDIV; + +#define I2S_MCLK_OUT_EN_BIT HAL_BIT(8) + +/* + * Bits definition for I2S_CHCFG Channel Configuration Register (0x30) + */ +#define I2S_TX_SLOT_NUM_SHIFT (0) +#define I2S_TX_SLOT_NUM_MASK (0x7U << I2S_TX_SLOT_NUM_SHIFT) +typedef enum { + I2S_TX_SLOT_NUM1 = (0x0U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM2 = (0x1U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM3 = (0x2U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM4 = (0x3U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM5 = (0x4U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM6 = (0x5U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM7 = (0x6U << I2S_TX_SLOT_NUM_SHIFT), + I2S_TX_SLOT_NUM8 = (0x7U << I2S_TX_SLOT_NUM_SHIFT), +} I2S_TxSlotNum; + +#define I2S_RX_SLOT_NUM_SHIFT (4) +#define I2S_RX_SLOT_NUM_MASK (0x7U << I2S_RX_SLOT_NUM_SHIFT) +typedef enum { + I2S_RX_SLOT_NUM1 = (0x0U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM2 = (0x1U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM3 = (0x2U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM4 = (0x3U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM5 = (0x4U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM6 = (0x5U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM7 = (0x6U << I2S_RX_SLOT_NUM_SHIFT), + I2S_RX_SLOT_NUM8 = (0x7U << I2S_RX_SLOT_NUM_SHIFT), +} I2S_RxSlotNum; + +#define I2S_TXN_STATE_SHIFT (8) +#define I2S_TXN_STATEMASK (0x1U << I2S_TXN_STATE_SHIFT) +typedef enum { + I2S_TRANSFER0 = (0x0U << I2S_TXN_STATE_SHIFT), + I2S_HIZ_STATE = (0x1U << I2S_TXN_STATE_SHIFT), +} I2S_TxnState; + +#define I2S_TX_SLOT_HIZ_SHIFT (9) +#define I2S_TX_SLOT_HIZ_MASK (0x1U << I2S_TX_SLOT_HIZ_SHIFT) +typedef enum { + I2S_NORMAL_MODE = (0x0U << I2S_RX_SLOT_NUM_SHIFT), + I2S_HI_Z_STATE = (0x1U << I2S_RX_SLOT_NUM_SHIFT), +} I2S_TxSlotHIZ; + +/* + * Bits definition for I2S_TXnCHSEL Channel Select Register (0X34) + */ +#define I2S_TXN_CHANNEL_SEL_SHIFT (0) +#define I2S_TXN_CHANNEL_SEL_MASK (0x7U << I2S_TXN_CHANNEL_SEL_SHIFT) +typedef enum { + I2S_TXN_CHANNEL_NUM1 = (0x0U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM2 = (0x1U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM3 = (0x2U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM4 = (0x3U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM5 = (0x4U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM6 = (0x5U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM7 = (0x6U << I2S_TXN_CHANNEL_SEL_SHIFT), + I2S_TXN_CHANNEL_NUM8 = (0x7U << I2S_TXN_CHANNEL_SEL_SHIFT), +} I2S_TxnChNum; + +#define I2S_TXN_CHANNEL_SLOT_ENABLE_SHIFT (4) +#define I2S_TXN_CHANNEL_SLOT_ENABLE_MASK (0xFFU << I2S_TXN_CHANNEL_SLOT_ENABLE_SHIFT) +#define I2S_TXN_CHANNEL_SLOTS_ENABLE(n) (((1 << n) -1) << I2S_TXN_CHANNEL_SLOT_ENABLE_SHIFT) +#define I2S_TXN_OFFSET_SHIFT (12) +#define I2S_TXN_OFFSET_MASK (0x1U << I2S_TXN_OFFSET_SHIFT) +typedef enum { + I2S_TX_NO_OFFSET = (0x0U << I2S_TXN_OFFSET_SHIFT), + I2S_TX_ONEBCLK_OFFSET = (0x1U << I2S_TXN_OFFSET_SHIFT), +} I2S_TxnOffset; + +/* + * Bits definition for I2S_TXnCHMAP Channel Mapping Register (0x44) + */ +#define I2S_TXN_CHX_MAP_MASK(m) (0x7U << (4*m)) +#define I2S_TXN_CHX_MAP(m) (m << 4*m) + +/* + * Bits definition for I2S_RXCHSEL Channel Mapping Register (0x54) + */ +#define I2S_RXN_CHANNEL_SEL_SHIFT 0 +#define I2S_RXN_CHANNEL_SEL_MASK (0x7U << I2S_RXN_CHANNEL_SEL_SHIFT) + +typedef enum { + I2S_RXN_CHANNEL_NUM1 = (0X0U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM2 = (0X1U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM3 = (0X2U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM4 = (0X3U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM5 = (0X4U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM6 = (0X5U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM7 = (0X6U << I2S_RXN_CHANNEL_SEL_SHIFT), + I2S_RXN_CHANNEL_NUM8 = (0X7U << I2S_RXN_CHANNEL_SEL_SHIFT), +} I2S_RxnChNum; + +#define I2S_RXN_OFFSET_SHIFT (12) +#define I2S_RXN_OFFSET_MASK (0x1U << I2S_RXN_OFFSET_SHIFT) +typedef enum { + I2S_RX_NO_OFFSET = (0x0U << I2S_RXN_OFFSET_SHIFT), + I2S_RX_ONEBCLK_OFFSET = (0x1U << I2S_RXN_OFFSET_SHIFT), +} I2S_RxnOffset; + +/* + * Bits definition for I2S_RXCHMAP Channel Mapping Register (0x58) + */ +#define I2S_RXN_CHX_MAP_MASK(m) (0x7U << (4*m)) +#define I2S_RXN_CHX_MAP(m) (m << (4*m)) + +/** + * @brief I2S sample rate definition + */ +typedef enum { + I2S_SR8K = 0, /* 8000Hz */ + I2S_SR12K = 1, /* 12000Hz */ + I2S_SR16K = 2, /* 16000Hz */ + I2S_SR24K = 3, /* 24000Hz */ + I2S_SR32K = 4, /* 32000Hz */ + I2S_SR48K = 5, /* 48000Hz */ + I2S_SR11K = 6, /* 11025Hz */ + I2S_SR22K = 7, /* 22050Hz */ + I2S_SR44K = 8, /* 44100Hz */ +} I2S_SampleRate; + +/** + * @brief stream direction + */ +typedef enum { + PLAYBACK, + RECORD, +} I2S_StreamDir; + +/** + * @brief i2s data init structure definition + */ +typedef struct { + I2S_SampleRate sampleRate; /*!< Specifies the sampling rate of the transmitted data. */ + I2S_StreamDir direction; /*!< Specifies the direction of the transmitted data. */ + I2S_SampleResolution resolution; /*!< Specifies the sampling accuracy of the transmitted data. */ + uint32_t channels; /*!< Specifies the number of channels to transmit data. */ + uint32_t bufSize; /*!< Specifies the buffer size of the transmitted data. */ +} I2S_DataParam; + +/** + * @brief external device clock structure definition + */ +typedef struct { + uint32_t clkSource; /*!< Specifies the clock frequency provided. */ + bool isDevclk; /*!< Specifies whether i2s provide an external device clock. */ +} DEV_Param; + +/** + * @brief I2S low level hardware init structure definition + */ +typedef struct { + bool i2sFormat; /*!< Specifies the I2S operating format. */ + PCM_ClkMode clkMode; /*!< Specifies the I2S clk mode. */ + PCM_TranFmt transferFormat; /*!< Specifies the I2S transfer format. */ + PCM_SignalInv signalInterval; /*!< Specifies the idle state of the I2S clock. */ + uint32_t lrckPeriod; /*!< Specifies The lrck division factor. */ + I2S_FrameMode frameMode; /*!< Specifies the frame format. */ + I2S_TxMLS txMsbFirst; /*!< Specifies high first pass or low first pass when transmission data. */ + I2S_RxMLS rxMsbFirst; /*!< Specifies high first pass or low first pass when receive data. */ + uint32_t txFifoLevel; /*!< Specifies the depth of tx Fifo. */ + uint32_t rxFifoLevel; /*!< Specifies the depth of rx Fifo. */ + DEV_Param codecClk; /*!< I2S MCLK parameters for external device */ +} I2S_HWParam; + +/** + * @brief I2S module init structure definition + */ +typedef struct { + I2S_HWParam *hwParam; /*!< I2S Hardware init structure. */ +} I2S_Param; + +HAL_Status HAL_I2S_Init(I2S_Param *param); +void HAL_I2S_DeInit(); +HAL_Status HAL_I2S_Open(I2S_DataParam *param); +HAL_Status HAL_I2S_Close(uint32_t dir); +int32_t HAL_I2S_Read_DMA(uint8_t *buf, uint32_t size); +int32_t HAL_I2S_Write_DMA(uint8_t *buf, uint32_t size); +void HAL_I2S_REG_DEBUG(); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_I2S_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_irrx.h b/platform/mcu/xr871/include/driver/chip/hal_irrx.h new file mode 100644 index 0000000000..5d9a8caf7b --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_irrx.h @@ -0,0 +1,133 @@ +/** + * @file hal_irrx.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_IRRX_H_ +#define _DRIVER_CHIP_HAL_IRRX_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Protocal supported. + * + * @note Only support NEC protocal now, rewrite IRRX_XXXPacket_Handler + * if you want support other protocals. + */ + +/** + * @brief select 32k clock as clk source definition. + * + * @note IR_CLK_32K_USED can be used only external 32768 crystal enabled. + */ +//#define IR_CLK_32K_USED 1 /* keep the same define in hal_irtx.h */ + +/** + * @brief IR Key Match definition. + * + * @note If defined IRRX_CHECK_ADDR_CODE, only addr_code(IRRX_ADDR_CODE) + * will be reported. + */ +//#define IRRX_CHECK_ADDR_CODE 1 +#define IRRX_ADDR_CODE (0x7f80) /* (addr|~addr) */ + +/** + * @brief IRRX use example: + * 1. define IR_CLK_32K_USED as ir clk source if 32k can be used when suspend. + * 2. define IRRX_CHECK_ADDR_CODE if you want to support only one ir remoter + * which addr is defined by IRRX_ADDR_CODE. + * +#include "driver/chip/hal_irrx.h" + +static void irrx_rxcplt_callback(uint32_t addr, uint32_t key) +{ + printf("received ir code addr:0x%02x key:0x%02x\n", addr, key); +} + +void main(const void *arg) +{ + IRRX_InitTypeDef irrx_param; + + irrx_param.PulsePolariyInvert = IRRX_RPPI_INVERT; + irrx_param.rxCpltCallback = &irrx_rxcplt_callback; + HAL_IRRX_Init(&irrx_param); +} + * + */ + +/* + * Bit field definition of IRRX configure register, receiver pulse polarity. + */ +typedef enum +{ + IRRX_RPPI_NONE = 0, + IRRX_RPPI_INVERT = HAL_BIT(2) +} IRRX_RppiTypeDef; + +struct IRRX_HandleDef; +typedef struct IRRX_HandleDef IRRX_HandleTypeDef; + +/** @brief Type define of IRRX IRQ callback function. */ +typedef void (*IRRX_RxCpltCallback)(uint32_t addr, uint32_t key); + +/** @brief IRRX initialization parameters. */ +typedef struct +{ + IRRX_RppiTypeDef PulsePolariyInvert; + IRRX_RxCpltCallback rxCpltCallback; +} IRRX_InitTypeDef; + +/** + * @brief Initializes the IRRX peripheral. + * @param param: + * @arg param->[in] The configuration information. + * @retval None. + */ +extern IRRX_HandleTypeDef *HAL_IRRX_Init(IRRX_InitTypeDef *param); + +/** + * @brief DeInitializes the IRRX peripheral. + * @param irrx: + * @arg irrx->[in] IRRX handler. + * @retval None. + */ +extern void HAL_IRRX_DeInit(IRRX_HandleTypeDef *irrx); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_IRRX_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_irtx.h b/platform/mcu/xr871/include/driver/chip/hal_irtx.h new file mode 100644 index 0000000000..f7ffdbf80f --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_irtx.h @@ -0,0 +1,209 @@ +/** + * @file hal_irtx.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_IRTX_H_ +#define _DRIVER_CHIP_HAL_IRTX_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief select 32k clock as clk source definition. + * + * @note IR_CLK_32K_USED can be used only external 32768 crystal enabled. + */ +//#define IR_CLK_32K_USED 1 /* keep the same define in hal_irrx.h */ + +/* + * @brief IRTX use example: + * 1 define IR_CLK_32K_USED as ir clk source if 32k can be used when suspend. + * + +#include "driver/chip/hal_irtx.h" +#include "driver/chip/ir_nec.h" + +void main(const void *arg) +{ + IRTX_InitTypeDef irtx_param; + IRTX_HandleTypeDef *irtx; + + irtx_param.PulsePolarity = IRTX_TPPI_NONE; + irtx_param.ModulateDutyLevel = IRTX_DRMC_TIME_1; + irtx_param.SendModeType = IRTX_TTS_NONE; //IRTX_TTS_CYCLICAL for cycle mode + irtx_param.CyclicalCnt = 3; //send 3 times if cycle mode +#if defined (IR_CLK_32K_USED) + irtx_param.IdleDurationCnt = IRTX_32K_NEC_IDC_VALUE; +#else + uint32_t clk = HAL_GetHFClock(); + + if (clk == HOSC_CLOCK_26M) { + irtx_param.IdleDurationCnt = IRTX_26M_NEC_IDC_VALUE; + } else if (clk == HOSC_CLOCK_24M) { + irtx_param.IdleDurationCnt = IRTX_24M_NEC_IDC_VALUE; + } else { + printf("%s unknow clk type(%d)!\n", __func__, clk); + } +#endif + + irtx_param.InternalModulation = IRTX_IMS_ENABLE; + irtx = HAL_IRTX_Init(&irtx_param); + + while (1) { + OS_Sleep(5); + // add=0x59, key=0x16 + HAL_IRTX_Transmit(irtx, IRTX_NEC_PROTO, IR_NEC_CODE(0x59, 0x16)); + } +} + * + */ + +/** + * @brief Add a new ir protocal. + * @note Define a new ir protocal in IRTX_ProtocalsDef and IRTX_PROTOS_FUN_INIT. + */ +typedef enum +{ + IRTX_NEC_PROTO = 0, + //IRTX_ITT_PROTO = 1, + IRTX_PROTO_NUM /* keep last */ +} IRTX_ProtocalsDef; + +typedef uint32_t (*IRTX_Proto_Code)(uint8_t *txBuff, uint32_t ir_tx_code); + +#define IRTX_PROTOS_FUN_INIT(handler) \ + do { \ + (handler)->Protos[IRTX_NEC_PROTO] = IRTX_NECPacket_Code; \ + /*(handler)->Protos[IRTX_ITT_PROTO] = IRTX_ITTPacket_Code;*/ \ + } while (0) + +/* + * @brief The high/low level modulated carrier duty ratio select. + * @note Bit field definition of IRTX Transmit Global register of bit5~6. + * DRMC_TIME_1 can trasmit longer, DRMC_TIME_3 has less power. + */ +typedef enum +{ + IRTX_DRMC_TIME_1 = (0), /* 1:1 */ + IRTX_DRMC_TIME_2 = (1<<5), /* 1:2 */ + IRTX_DRMC_TIME_3 = (2<<5), /* 1:3 */ + IRTX_DRMC_TIME_MASK = (3<<5) +} IRTX_DRMC_TIME; + +/* + * @brief Bit field definition of IRTX Transmit Global register of bit2. + * @note Transmit pulse polarity. + */ +typedef enum +{ + IRTX_TPPI_NONE = (0), + IRTX_TPPI_INVERT = (1<<2), + IRTX_TPPI_MASK = (1<<2) +} IRTX_TPPI_Type; + +/** + * @brief IRTX internal modulation signal enable. + * @note Select disable when connect tx/rx directly in test mode. + */ +typedef enum +{ + IRTX_IMS_DISABLE = (0), + IRTX_IMS_ENABLE = (1<<7) +} IRTX_IMS_Type; + +/* + * @bried Transmit mode select. + * + * @note Bit field definition of IRTX Transmit Control register of bit0, + * transmit type: signal or cyclical mode. + * The NEC repeat code start with S0 is 4.5mS not 2.25mS, for hardware + * not support change S0. + */ +typedef enum +{ + IRTX_TTS_NONE = (0), + IRTX_TTS_CYCLICAL = (1), + IRTX_TTS_MASK = (1) +} IRTX_TTS_Type; + +/** @brief IRTX initialization parameters. */ +typedef struct +{ + IRTX_DRMC_TIME ModulateDutyLevel; /* 1/3(less power cosumption) ~ 1/1(more tx lenght) */ + IRTX_TTS_Type SendModeType; /* signal or cyclical mode */ + uint32_t CyclicalCnt; /* count of cyclical mode */ + IRTX_TPPI_Type PulsePolarity; /* pulse polarity */ + IRTX_IMS_Type InternalModulation; /* internal modulation signal enable */ + uint32_t IdleDurationCnt; /* idle time for cyclical */ +} IRTX_InitTypeDef; + +struct IRTX_HandleDef; + +typedef struct IRTX_HandleDef IRTX_HandleTypeDef; + +/** + * @brief Send a code by IRTX peripheral. + * @param irtx: + * @arg irtx-> IRTX handler. + * @param protos_sel: + * @arg protos_sel->[in] The protocal used. + * @param ir_tx_code: + * @arg ir_tx_code->[in] The add and key(add|~addr|key|~key) will send. + * @retval None. + */ +extern void HAL_IRTX_Transmit(IRTX_HandleTypeDef *irtx, uint32_t protos_sel, uint32_t ir_tx_code); + +/** + * @brief Initializes the IRTX peripheral. + * @param param: + * @arg param->[in] The configuration information. + * @retval IRTX handler. + */ +extern IRTX_HandleTypeDef *HAL_IRTX_Init(IRTX_InitTypeDef *param); + +/** + * @brief DeInitializes the IRTX peripheral. + * @param irtx: + * @arg irtx->IRTX handler. + * @retval None. + */ +extern void HAL_IRTX_DeInit(IRTX_HandleTypeDef *irtx); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_IRTX_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_mbox.h b/platform/mcu/xr871/include/driver/chip/hal_mbox.h new file mode 100644 index 0000000000..21dd235426 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_mbox.h @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_MBOX_H_ +#define _DRIVER_CHIP_HAL_MBOX_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* queue index */ +typedef enum { + MBOX_QUEUE_0 = 0, + MBOX_QUEUE_1 = 1, + MBOX_QUEUE_2 = 2, + MBOX_QUEUE_3 = 3, + MBOX_QUEUE_4 = 4, + MBOX_QUEUE_5 = 5, + MBOX_QUEUE_6 = 6, + MBOX_QUEUE_7 = 7, + MBOX_QUEUE_NUM = 8 +} MBOX_Queue; + +typedef struct { + __IO uint32_t CTRL[2]; /* offset: 0x0000 */ + uint32_t RESERVED0[14]; + __IO uint32_t IRQ0_EN; /* offset: 0x0040 */ + uint32_t RESERVED1[3]; + __IO uint32_t IRQ0_STATUS; /* offset: 0x0050 */ + uint32_t RESERVED2[3]; + __IO uint32_t IRQ1_EN; /* offset: 0x0060 */ + uint32_t RESERVED3[3]; + __IO uint32_t IRQ1_STATUS; /* offset: 0x0070 */ + uint32_t RESERVED4[35]; + __I uint32_t FIFO_STATUS[MBOX_QUEUE_NUM]; /* offset: 0x0100 */ + uint32_t RESERVED5[8]; + __I uint32_t MSG_STATUS[MBOX_QUEUE_NUM]; /* offset: 0x0140 */ + uint32_t RESERVED6[8]; + __IO uint32_t MSG[MBOX_QUEUE_NUM]; /* offset: 0x0180 */ + uint32_t RESERVED7[8]; + __IO uint32_t DEBUG; /* offset: 0x01C0 */ +} MBOX_T; + +#define MBOX_A ((MBOX_T *)MBOX_A_BASE) +#define MBOX_N ((MBOX_T *)MBOX_N_BASE) + +/* user + * - MBOX_A: app core is MBOX_USER0, net core is MBOX_USER1 + * - MBOX_N: app core is MBOX_USER1, net core is MBOX_USER0 + */ +typedef enum { + MBOX_USER0 = 0, + MBOX_USER1 = 1, + MBOX_USER_NUM = 2 +} MBOX_User; + +/* direction */ +typedef enum { + MBOX_DIR_RX = 0, + MBOX_DIR_TX = 1, + MBOX_DIR_NUM = 2 +} MBOX_Direction; + +/* queue size */ +#define MBOX_QUEUE_SIZE 4 + +/* + * bit field definition of MBOX->FIFO_STATUS + */ +#define MBOX_QUEUE_FULL_BIT HAL_BIT(0) + +/* + * bit field definition of MBOX->MSG_STATUS + */ +#define MBOX_QUEUE_MSG_NUM_SHIFT 0 +#define MBOX_QUEUE_MSG_NUM_VMASK 0x7 + +/* MBOX->MSG */ + +/* + * bit field definition of MBOX->DEBUG + */ +#define MBOX_DEBUG_FIFO_CTRL_SHIFT 8 +#define MBOX_DEBUG_EN_BIT HAL_BIT(0) + +/******************************************************************************/ + +#define HAL_MBOX_PM_PATCH 1 + +void HAL_MBOX_Init(MBOX_T *mbox); +void HAL_MBOX_DeInit(MBOX_T *mbox); +void HAL_MBOX_QueueInit(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir); +void HAL_MBOX_QueueDeInit(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir); +void HAL_MBOX_QueueEnableIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir); +void HAL_MBOX_QueueDisableIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir); +int HAL_MBOX_QueueIsPendingIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir); +void HAL_MBOX_QueueClrPendingIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir); +#if HAL_MBOX_PM_PATCH +void HAL_MBOX_EnableIRQ(MBOX_T *mbox); +void HAL_MBOX_DisableIRQ(MBOX_T *mbox); +#endif + +int HAL_MBOX_QueueIsFull(MBOX_T *mbox, MBOX_Queue queue); +uint32_t HAL_MBOX_QueueGetMsgNum(MBOX_T *mbox, MBOX_Queue queue); +void HAL_MBOX_QueuePutMsg(MBOX_T *mbox, MBOX_Queue queue, uint32_t msg); +uint32_t HAL_MBOX_QueueGetMsg(MBOX_T *mbox, MBOX_Queue queue); + +__STATIC_INLINE void HAL_MBOX_QueueEnableFIFO(MBOX_T *mbox, MBOX_Queue queue) +{ + HAL_CLR_BIT(mbox->DEBUG, HAL_BIT((uint32_t)queue + MBOX_DEBUG_FIFO_CTRL_SHIFT)); +} + +__STATIC_INLINE void HAL_MBOX_QueueDisableFIFO(MBOX_T *mbox, MBOX_Queue queue) +{ + HAL_SET_BIT(mbox->DEBUG, HAL_BIT((uint32_t)queue + MBOX_DEBUG_FIFO_CTRL_SHIFT)); +} + +__STATIC_INLINE void HAL_MBOX_EnableDebugMode(MBOX_T *mbox) +{ + HAL_SET_BIT(mbox->DEBUG, MBOX_DEBUG_EN_BIT); +} + +__STATIC_INLINE void HAL_MBOX_DisableDebugMode(MBOX_T *mbox) +{ + HAL_CLR_BIT(mbox->DEBUG, MBOX_DEBUG_EN_BIT); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_MBOX_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_nvic.h b/platform/mcu/xr871/include/driver/chip/hal_nvic.h new file mode 100644 index 0000000000..b6de2041ab --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_nvic.h @@ -0,0 +1,85 @@ +/** + * @file hal_nvic.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_NVIC_H_ +#define _DRIVER_CHIP_HAL_NVIC_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for preempt priority, 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for preempt priority, 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for preempt priority, 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for preempt priority, 0 bits for subpriority */ + +/* Default NVIC priority grouping */ +#define NVIC_PRIORITYGROUP_DEFAULT NVIC_PRIORITYGROUP_3 + +/** + * @brief Default priority for all peripherals + * @note + * - Rang from 0 to 7 due to __NVIC_PRIO_BITS is 3 + * - Should be set to [1, 7], MUST not be set to 0 + */ +#define NVIC_PERIPHERAL_PRIORITY_DEFAULT (4) + +/** @brief Type define of NVIC interrupt handler */ +typedef void (*NVIC_IRQHandler) (void); + +void HAL_NVIC_SetIRQHandler(IRQn_Type IRQn, NVIC_IRQHandler handler); +NVIC_IRQHandler HAL_NVIC_GetIRQHandler(IRQn_Type IRQn); + +void HAL_NVIC_SetPriorityGrouping(uint32_t priorityGroup); +uint32_t HAL_NVIC_GetPriorityGrouping(void); + +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); + +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); + +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +int HAL_NVIC_IsPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); + +void HAL_NVIC_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_NVIC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_prcm.h b/platform/mcu/xr871/include/driver/chip/hal_prcm.h new file mode 100644 index 0000000000..db0fa429ec --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_prcm.h @@ -0,0 +1,637 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_PRCM_H_ +#define _DRIVER_CHIP_HAL_PRCM_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* prcm system module control */ +typedef struct { + __IO uint32_t SYS_DCDC_CTRL; /* offset: 0x0000, System DCDC control register */ + __IO uint32_t SYS_LDO_SW_CTRL; /* offset: 0x0004, System LDO and switch control register */ + __IO uint32_t SYS_LFCLK_CTRL; /* offset: 0x0008, System LFCLK control register */ + __IO uint32_t SYS_HOSC_CTRL; /* offset: 0x000C, System HOSC type register */ + __IO uint32_t SYS_RCOSC_CALIB_CTRL; /* offset: 0x0010, System RCOSC calibration control register */ + uint32_t RESERVED0[3]; + __IO uint32_t SYS_PLL_CTRL; /* offset: 0x0020, System PLL control register */ + __IO uint32_t SYS_CLK1_CTRL; /* offset: 0x0024, System clock 1 control register */ + __I uint32_t SYS_CLK2_CTRL; /* offset: 0x0028, System clock 2 control register */ + __I uint32_t SYS_CLK3_CTRL; /* offset: 0x002C, System clock 3 control register */ + __IO uint32_t AUD_PLL_CTRL; /* offset: 0x0030, Audio PLL control register */ + __IO uint32_t DEV_CLK_CTRL; /* offset: 0x0034, Device clock control register */ + uint32_t RESERVED1[3]; + __IO uint32_t AUD_PLL_BIAS; /* offset: 0x0044, Audio PLL bias register */ + uint32_t RESERVED2[3]; + __IO uint32_t AUD_PLL_PAT_CTRL; /* offset: 0x0054, Audio PLL pattern control register */ + __IO uint32_t DCXO_CTRL; /* offset: 0x0058, DCXO control register */ + uint32_t RESERVED3[9]; + __I uint32_t SYS1_CTRL; /* offset: 0x0080, System 1 control register */ + __IO uint32_t SYS1_STATUS; /* offset: 0x0084, System 1 status register */ + __IO uint32_t SYS2_CTRL; /* offset: 0x0088, System 2 control register */ + __I uint32_t SYS2_STATUS; /* offset: 0x008C, System 2 status register */ + __I uint32_t SYS3_CTRL; /* offset: 0x0090, System 3 control register */ + __I uint32_t SYS3_STATUS; /* offset: 0x0094, System 3 status register */ + __IO uint32_t SYS1_WAKEUP_CTRL; /* offset: 0x0098, System 1 wakeup control register */ + __I uint32_t SYS2_WAKEUP_CTRL; /* offset: 0x009C, System 2 wakeup control register */ + __IO uint32_t SYS1_SLEEP_CTRL; /* offset: 0x00A0, System 1 sleep control register */ + __I uint32_t SYS2_SLEEP_CTRL; /* offset: 0x00A4, System 2 sleep control register */ + __IO uint32_t DCXO_STABLE_REF_TIME; /* offset: 0x00A8, DCXO stable reference time register */ + __IO uint32_t DPLL_STABLE_REF_TIME; /* offset: 0x00AC, DPLL stable reference time register */ + __IO uint32_t LDO_STABLE_REF_TIME; /* offset: 0x00B0, LDO stable reference time register */ + __IO uint32_t DIG_SWITCH_REF_TIME; /* offset: 0x00B4, Digital switch reference time register */ + __IO uint32_t SRAM_VOLT_CTRL; /* offset: 0x00B8, SRAM voltage control register */ + __IO uint32_t BANDGAP_STABLE_REF_TIME; /* offset: 0x00BC, Band gap stable reference time register */ + __IO uint32_t DCDC_STABLE_REF_TIME; /* offset: 0x00C0, DCDC stable reference time register */ + uint32_t RESERVED4[15]; + __IO uint32_t CPUA_BOOT_FLAG; /* offset: 0x0100, CPUA boot flag register */ + __IO uint32_t CPUA_BOOT_ADDR; /* offset: 0x0104, CPUA boot address register */ + __IO uint32_t CPUA_BOOT_ARG; /* offset: 0x0108, CPUA boot argument register */ + __I uint32_t CPUN_BOOT_FLAG; /* offset: 0x010C, CPUN boot flag register */ + __I uint32_t CPUN_BOOT_ADDR; /* offset: 0x0110, CPUN boot address register */ + __I uint32_t CPUN_BOOT_ARG; /* offset: 0x0114, CPUN boot argument register */ + __IO uint32_t CPUA_PRIV_REG; /* offset: 0x0118, CPUA private register */ + uint32_t CPUN_PRIV_REG; /* offset: 0x011C, CPUN private register */ + __IO uint32_t CPUA_WAKE_TIMER_CNT; /* offset: 0x0120, CPUA wakeup timer counter register */ + __IO uint32_t CPUA_WAKE_TIMER_CMP; /* offset: 0x0124, CPUA wakeup timer value register */ + __I uint32_t CPUN_WAKE_TIMER_CNT; /* offset: 0x0128, CPUN wakeup timer counter register */ + __I uint32_t CPUN_WAKE_TIMER_CMP; /* offset: 0x012C, CPUN wakeup timer value register */ + __IO uint32_t CPUA_WAKE_IO_EN; /* offset: 0x0130, CPUA IO wakeup enable register */ + __IO uint32_t CPUA_WAKE_IO_MODE; /* offset: 0x0134, CPUA IO wakeup mode register */ + __IO uint32_t CPUA_WAKE_IO_STATUS; /* offset: 0x0138, CPUA IO wakeup status register */ + __IO uint32_t CPUA_WAKE_IO_HOLD; /* offset: 0x013C, CPUA IO hold control register */ + __IO uint32_t CPUA_WAKE_IO_GLOBAL_EN; /* offset: 0x0140, CPUA IO wakeup global enable register */ + __IO uint32_t CPUA_PRCM_REG; /* offset: 0x0144, CPUA PRCM register */ + uint32_t RESERVED6[46]; + __IO uint32_t DCDC_PARAM_CTRL; /* offset: 0x0200, DCDC parameter control register */ + __IO uint32_t ANA_BANDGAP; /* offset: 0x0204, Analog band gap control register */ + __I uint32_t CLK_LDO_PARAM; /* offset: 0x0208, Clock LDO parameter register */ + __IO uint32_t DIG_LDO_PARAM; /* offset: 0x020C, Digital LDO parameter register */ + __IO uint32_t DPLL_STATUS; /* offset: 0x0210, DPLL status register */ +} PRCM_T; + +#define PRCM ((PRCM_T *)PRCM_BASE) /* address: 0x40040000 */ + +/* + * bit field definition of PRCM->SYS_DCDC_CTRL + */ +#define PRCM_DCDC_VOLT_SHIFT 16 /* R/W */ +#define PRCM_DCDC_VOLT_MASK (0xFU << PRCM_DCDC_VOLT_SHIFT) +typedef enum { + PRCM_DCDC_VOLT_1V80 = (0x0U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V77 = (0x1U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V75 = (0x2U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V72 = (0x3U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V69 = (0x4U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V67 = (0x5U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V64 = (0x6U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V61 = (0x7U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V58 = (0x8U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V56 = (0x9U << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V53 = (0xAU << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V51 = (0xBU << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V48 = (0xCU << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V45 = (0xDU << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V43 = (0xEU << PRCM_DCDC_VOLT_SHIFT), + PRCM_DCDC_VOLT_1V40 = (0xFU << PRCM_DCDC_VOLT_SHIFT) +} PRCM_DCDCVolt; + +#define PRCM_DCDC_EN_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of PRCM->SYS_LDO_SW_CTRL + */ +#define PRCM_SYS3_SRAM_PWR3_EN_BIT HAL_BIT(15) /* R */ +#define PRCM_SYS3_PWR5_EN_BIT HAL_BIT(14) /* R */ +#define PRCM_SYS3_PWR4_EN_BIT HAL_BIT(13) /* R */ + +#define PRCM_SYS2_PWR3_EN_BIT HAL_BIT(12) /* R/W */ +#define PRCM_SYS2_SRAM_PWR2_EN_BIT HAL_BIT(11) /* R/W */ + +#define PRCM_SYS1_SRAM_PWR1_EN_BIT HAL_BIT(10) /* R */ +#define PRCM_SYS1_PWR2_EN_BIT HAL_BIT(9) /* R */ +#define PRCM_SYS1_PWR1_EN_BIT HAL_BIT(8) /* R */ + +#define PRCM_LDO1_VOLT_SHIFT 4 /* R/W */ +#define PRCM_LDO1_VOLT_MASK (0x7U << PRCM_LDO1_VOLT_SHIFT) +typedef enum { + PRCM_LDO1_VOLT_1V10 = (0x0U << PRCM_LDO1_VOLT_SHIFT), + PRCM_LDO1_VOLT_1V05 = (0x1U << PRCM_LDO1_VOLT_SHIFT), + PRCM_LDO1_VOLT_1V00 = (0x2U << PRCM_LDO1_VOLT_SHIFT), + PRCM_LDO1_VOLT_0V95 = (0x3U << PRCM_LDO1_VOLT_SHIFT), + PRCM_LDO1_VOLT_0V90 = (0x4U << PRCM_LDO1_VOLT_SHIFT) +} PRCM_LDO1Volt; + +#define PRCM_SRAM_LDO_EN_BIT HAL_BIT(2) /* R */ +#define PRCM_PLL_LDO_EN_BIT HAL_BIT(1) /* R/W */ +#define PRCM_LDO1_EN_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of PRCM->SYS_LFCLK_CTRL + */ +#define PRCM_LFCLK_EXT32K_EN_BIT HAL_BIT(31) /* R/W */ +#define PRCM_LFCLK_INTER32K_EN_BIT HAL_BIT(30) /* R/W */ + +#define PRCM_LFCLK_SRC_SHIFT 24 /* R/W */ +#define PRCM_LFCLK_SRC_MASK (0x1U << PRCM_LFCLK_SRC_SHIFT) +typedef enum { + PRCM_LFCLK_SRC_INTER32K = (0x0U << PRCM_LFCLK_SRC_SHIFT), + PRCM_LFCLK_SRC_EXT32K = (0x1U << PRCM_LFCLK_SRC_SHIFT) +} PRCM_LFCLKSrc; + +/* + * bit field definition of PRCM->SYS_HOSC_CTRL + */ +#define PRCM_HOSC_TYPE_SHIFT 0 /* R/W */ +#define PRCM_HOSC_TYPE_VMASK 0x3U +#define PRCM_HOSC_TYPE_MASK (PRCM_HOSC_TYPE_VMASK << PRCM_HOSC_TYPE_SHIFT) +typedef enum { + PRCM_HOSC_TYPE_26M = (0U << PRCM_HOSC_TYPE_SHIFT), + PRCM_HOSC_TYPE_40M = (1U << PRCM_HOSC_TYPE_SHIFT), + PRCM_HOSC_TYPE_24M = (2U << PRCM_HOSC_TYPE_SHIFT), + PRCM_HOSC_TYPE_52M = (3U << PRCM_HOSC_TYPE_SHIFT) +} PRCM_HOSCType; + +/* + * bit field definition of PRCM->SYS_RCOSC_CALIB_CTRL + */ +#define PRCM_RCOSC_CALIB_FREQ_SHIFT 8 /* R */ +#define PRCM_RCOSC_CALIB_FREQ_VMASK 0xFFFFFU + +#define PRCM_RCOSC_CALIB_EN_BIT HAL_BIT(0) /* R/W */ + +/* + * bit field definition of PRCM->SYS_PLL_CTRL + */ +#define PRCM_SYS_PLL_EN_BIT HAL_BIT(31) /* R/W */ + +#define PRCM_SYS_PLL_PARAM_SHIFT 0 +#define PRCM_SYS_PLL_PARAM_MASK 0x7FFFFFFFU +typedef enum { + PRCM_SYS_PLL_PARAM_HOSC24M = 0x00001141U, + PRCM_SYS_PLL_PARAM_HOSC26M = 0x0EC4F121U, + PRCM_SYS_PLL_PARAM_HOSC40M = 0x000010C1U, + PRCM_SYS_PLL_PARAM_HOSC52M = 0x07627091U +} PRCM_SysPLLParam; + +/* + * bit field definition of + * - PRCM->SYS_CLK1_CTRL (R/W) + * - PRCM->SYS_CLK2_CTRL (R) + * - PRCM->SYS_CLK3_CTRL (R) + */ +#define PRCM_SYS_CLK_EN_BIT HAL_BIT(31) /* R/W, R, R */ + +/* NB: the following bits are for SYS_CLK1_CTRL, SYS_CLK2_CTRL only */ +#define PRCM_CPU_CLK_SRC_SHIFT 16 /* R/W, R */ +#define PRCM_CPU_CLK_SRC_MASK (0x3 << PRCM_CPU_CLK_SRC_SHIFT) +typedef enum { + PRCM_CPU_CLK_SRC_HFCLK = (0x0U << PRCM_CPU_CLK_SRC_SHIFT), + PRCM_CPU_CLK_SRC_LFCLK = (0x1U << PRCM_CPU_CLK_SRC_SHIFT), + PRCM_CPU_CLK_SRC_SYSCLK = (0x2U << PRCM_CPU_CLK_SRC_SHIFT) +} PRCM_CPUClkSrc; + +/* NB: the following bits are for SYS_CLK1_CTRL, SYS_CLK2_CTRL only */ +#define PRCM_SYS_CLK_FACTOR_SHIFT 0 /* R/W */ +#define PRCM_SYS_CLK_FACTOR_VMASK 0xFU +#define PRCM_SYS_CLK_FACTOR_MASK (PRCM_SYS_CLK_FACTOR_VMASK << PRCM_SYS_CLK_FACTOR_SHIFT) +typedef enum { +// PRCM_SYS_CLK_FACTOR_960M = (0U << PRCM_SYS_CLK_FACTOR_SHIFT), +// PRCM_SYS_CLK_FACTOR_480M = (1U << PRCM_SYS_CLK_FACTOR_SHIFT), +// PRCM_SYS_CLK_FACTOR_320M = (2U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_240M = (3U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_192M = (4U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_160M = (5U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_137M = (6U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_120M = (7U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_107M = (8U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_96M = (9U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_87M = (10U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_80M = (11U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_74M = (12U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_69M = (13U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_64M = (14U << PRCM_SYS_CLK_FACTOR_SHIFT), + PRCM_SYS_CLK_FACTOR_60M = (15U << PRCM_SYS_CLK_FACTOR_SHIFT), +} PRCM_SysClkFactor; + +/* + * bit field definition of PRCM->AUD_PLL_CTRL + */ +#define PRCM_AUD_PLL_EN_BIT HAL_BIT(31) /* R/W */ + +#define PRCM_AUD_PLL_PARAM_SHIFT 0 +#define PRCM_AUD_PLL_PARAM_MASK 0x7FFFFFFFU +typedef enum { + PRCM_AUD_PLL24M_PARAM_HOSC13M = 0x8003780FU, + PRCM_AUD_PLL24M_PARAM_HOSC19M2 = 0x80037F18U, + PRCM_AUD_PLL24M_PARAM_HOSC24M = 0x80035514U, + PRCM_AUD_PLL24M_PARAM_HOSC26M = 0x8003781FU, + PRCM_AUD_PLL24M_PARAM_HOSC40M = 0x80033A17U, + PRCM_AUD_PLL24M_PARAM_HOSC50M = 0x8003381CU, + PRCM_AUD_PLL24M_PARAM_HOSC52M = 0x81030603U, + /*22.5792*/ + PRCM_AUD_PLL22M_PARAM_HOSC13M = 0x81031A03U, + PRCM_AUD_PLL22M_PARAM_HOSC19M2 = 0x80037E1AU, + PRCM_AUD_PLL22M_PARAM_HOSC24M = 0x80034E14U, + PRCM_AUD_PLL22M_PARAM_HOSC26M = 0x80034112U, + PRCM_AUD_PLL22M_PARAM_HOSC40M = 0x8003451EU, + PRCM_AUD_PLL22M_PARAM_HOSC50M = 0x8003371EU, + PRCM_AUD_PLL22M_PARAM_HOSC52M = 0x80032012U +} PRCM_AudPLLParam; + +/* + * bit field definition of PRCM->DEV_CLK_CTRL + */ +#define PRCM_DEV_CLK_FACTOR_SHIFT 0 /* R/W */ +#define PRCM_DEV_CLK_FACTOR_VMASK 0xFU +#define PRCM_DEV_CLK_FACTOR_MASK (PRCM_DEV_CLK_FACTOR_VMASK << PRCM_DEV_CLK_FACTOR_SHIFT) +typedef enum { +// PRCM_DEV_CLK_FACTOR_960M = (0U << PRCM_DEV_CLK_FACTOR_SHIFT), +// PRCM_DEV_CLK_FACTOR_480M = (1U << PRCM_DEV_CLK_FACTOR_SHIFT), +// PRCM_DEV_CLK_FACTOR_320M = (2U << PRCM_DEV_CLK_FACTOR_SHIFT), +// PRCM_DEV_CLK_FACTOR_240M = (3U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_192M = (4U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_160M = (5U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_137M = (6U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_120M = (7U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_107M = (8U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_96M = (9U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_87M = (10U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_80M = (11U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_74M = (12U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_69M = (13U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_64M = (14U << PRCM_DEV_CLK_FACTOR_SHIFT), + PRCM_DEV_CLK_FACTOR_60M = (15U << PRCM_DEV_CLK_FACTOR_SHIFT), +} PRCM_DevClkFactor; + +/* + * bit field definition of PRCM->AUD_PLL_BIAS + */ +#define PRCM_AUD_PLL_VCO_BIAS_SHIFT 24 /* R/W */ +#define PRCM_AUD_PLL_VCO_BIAS_MASK (0x1F << PRCM_AUD_PLL_VCO_BIAS_SHIFT) + +#define PRCM_AUD_PLL_CUR_BIAS_SHIFT 16 /* R/W */ +#define PRCM_AUD_PLL_CUR_BIAS_MASK (0x1F << PRCM_AUD_PLL_CUR_BIAS_SHIFT) + +/* + * bit field definition of PRCM->AUD_PLL_PAT_CTRL + */ +#define PRCM_AUD_DIG_DELT_PAT_EN_BIT HAL_BIT(31) /* R/W */ + +#define PRCM_AUD_PLL_PAT_PARAM_SHIFT 0 +#define PRCM_AUD_PLL_PAT_PARAM_MASK 0x7FFFFFFFU +typedef enum { + PRCM_AUD_PLL24M_PAT_PARAM_HOSC13M = 0x00000000U, + PRCM_AUD_PLL24M_PAT_PARAM_HOSC19M2 = 0x00000000U, + PRCM_AUD_PLL24M_PAT_PARAM_HOSC24M = 0x00000000U, + PRCM_AUD_PLL24M_PAT_PARAM_HOSC26M = 0x00000000U, + PRCM_AUD_PLL24M_PAT_PARAM_HOSC40M = 0x00000000U, + PRCM_AUD_PLL24M_PAT_PARAM_HOSC50M = 0x00000000U, + PRCM_AUD_PLL24M_PAT_PARAM_HOSC52M = 0xc0011FAAU, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC13M = 0xC0019468U, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC19M2 = 0x00000000U, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC24M = 0x00000000U, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC26M = 0x00000000U, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC40M = 0x00000000U, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC50M = 0x00000000U, + PRCM_AUD_PLL22M_PAT_PARAM_HOSC52M = 0x00000000U +} PRCM_AudPLLPatParam; + +/* + * bit field definition of PRCM->DCXO_CTRL + */ +#define PRCM_DCXO_EN_BIT HAL_BIT(31) /* R/W */ + +/* + * bit field definition of PRCM->SYS1_CTRL + */ +#define PRCM_CPUA_RESET_BIT HAL_BIT(1) /* R */ +#define PRCM_SYS1_RESET_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of PRCM->SYS1_STATUS + */ +#define PRCM_CPUN_DEEPSLEEP_LOCK_BIT HAL_BIT(3) /* R/W */ +#define PRCM_CPUA_SLEEP_STATUS_BIT HAL_BIT(2) /* R */ +#define PRCM_CPUA_DEEPSLEEP_STATUS_BIT HAL_BIT(1) /* R */ +#define PRCM_SYS1_ALIVE_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of PRCM->SYS2_CTRL + */ +#define PRCM_SYS2_ISOLATION_EN_BIT HAL_BIT(2) /* R/W */ +#define PRCM_CPUN_RESET_BIT HAL_BIT(1) /* R/W */ +#define PRCM_SYS2_RESET_BIT HAL_BIT(0) /* R/W */ + +/* + * bit field definition of PRCM->SYS2_STATUS + */ +#define PRCM_CPUA_DEEPSLEEP_LOCK_BIT HAL_BIT(3) /* R */ +#define PRCM_CPUN_SLEEP_STATUS_BIT HAL_BIT(2) /* R */ +#define PRCM_CPUN_DEEPSLEEP_STATUS_BIT HAL_BIT(1) /* R */ +#define PRCM_SYS2_ALIVE_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of PRCM->SYS3_CTRL + */ +#define PRCM_SYS3_RESET_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of PRCM->SYS3_STATUS + */ +#define PRCM_CPUW_SLEEP_STATUS_BIT HAL_BIT(2) /* R */ +#define PRCM_CPUW_DEEPSLEEP_STATUS_BIT HAL_BIT(1) /* R */ +#define PRCM_SYS3_ALIVE_BIT HAL_BIT(0) /* R */ + +/* + * bit field definition of + * - PRCM->SYS1_WAKEUP_CTRL (R/W) + * - PRCM->SYS2_WAKEUP_CTRL (R) + * - PRCM->SYS1_SLEEP_CTRL (R/W) + * - PRCM->SYS2_SLEEP_CTRL (R) + */ +#define PRCM_SYS_WS_PWR_VAL_KEEP 0U /* for all */ +#define PRCM_SYS_WS_PWR_VAL_ON 1U /* for PRCM->SYSx_WAKEUP_CTRL */ +#define PRCM_SYS_WS_PWR_VAL_OFF 1U /* for PRCM->SYSx_SLEEP_CTRL */ + +#define PRCM_SYS_WS_PWR_TYPE_LDO1 0U +#define PRCM_SYS_WS_PWR_TYPE_SYS1_PWR1 1U +#define PRCM_SYS_WS_PWR_TYPE_SYS1_PWR2 2U +#define PRCM_SYS_WS_PWR_TYPE_SYS1_SRAM_PWR1 3U +#define PRCM_SYS_WS_PWR_TYPE_SYS2_SRAM_PWR2 4U +#define PRCM_SYS_WS_PWR_TYPE_SYS2_PWR3 5U + +#define PRCM_SYS_WS_PWR_FLAG(val, type) ((val) << (type)) +#define PRCM_SYS_WS_PWR_FLAGS_MASK 0x3FU + +/* DCXO_STABLE_REF_TIME */ + +/* DPLL_STABLE_REF_TIME */ + +/* LDO_STABLE_REF_TIME */ + +/* DIG_SWITCH_REF_TIME */ + +/* + * bit field definition of PRCM->SRAM_VOLT_CTRL + */ +typedef enum { + PRCM_SRAM_VOLT_1V10 = 0U, + PRCM_SRAM_VOLT_1V00 = 1U, + PRCM_SRAM_VOLT_0V90 = 2U, + PRCM_SRAM_VOLT_0V80 = 3U, + PRCM_SRAM_VOLT_0V75 = 4U, + PRCM_SRAM_VOLT_0V70 = 5U, + PRCM_SRAM_VOLT_0V65 = 6U, + PRCM_SRAM_VOLT_0V60 = 7U +} PRCM_SRAMVolt; + +#define PRCM_SRAM_WORK_VOLT_SHIFT 16 /* R/W */ +#define PRCM_SRAM_WORK_VOLT_MASK (0x7U << PRCM_SRAM_WORK_VOLT_SHIFT) + +#define PRCM_SRAM_RETEN_VOLT_SHIFT 0 /* R/W */ +#define PRCM_SRAM_RETEN_VOLT_MASK (0x7U << PRCM_SRAM_RETEN_VOLT_SHIFT) + +/* BANDGAP_STABLE_REF_TIME */ +#define PRCM_BANDGAP_STABLE_REF_TIME_MASK 0x0FU + +/* DCDC_STABLE_REF_TIME */ +#define PRCM_LDOTOPWM_STABLE_RFE_TIME_SHIFT 16 /* R/W */ +#define PRCM_LDOTOPWM_STABLE_RFE_TIME_MASK 0x3FFU +#define PRCM_DCDC_STABLE_REF_TIME_MASK 0x3FU + +/* + * bit field definition of PRCM->CPUA_BOOT_FLAG + */ +#define PRCM_CPUA_BOOT_FLAG_WR_LOCK (0x429BU << 16) /* W */ + +#define PRCM_CPUA_BOOT_FLAG_SHIFT 0 /* R/W */ +#define PRCM_CPUA_BOOT_FLAG_MASK (0xFU << PRCM_CPUA_BOOT_FLAG_SHIFT) +typedef enum { + PRCM_CPUA_BOOT_FROM_COLD_RESET = (0U << PRCM_CPUA_BOOT_FLAG_SHIFT), + PRCM_CPUA_BOOT_FROM_DEEPSLEEP = (1U << PRCM_CPUA_BOOT_FLAG_SHIFT), + PRCM_CPUA_BOOT_FROM_SYS_UPDATE = (2U << PRCM_CPUA_BOOT_FLAG_SHIFT) +} PRCM_CPUABootFlag; + +/* PRCM->CPUA_BOOT_ADDR */ + +/* PRCM->CPUA_BOOT_ARG */ + +/* + * bit field definition of PRCM->CPUN_BOOT_FLAG + */ +#define PRCM_CPUN_BOOT_FLAG_WR_LOCK (0x429CU << 16) /* R */ + +#define PRCM_CPUN_BOOT_FLAG_SHIFT 0 /* R */ +#define PRCM_CPUN_BOOT_FLAG_MASK (0xFU << PRCM_CPUN_BOOT_FLAG_SHIFT) +typedef enum { + PRCM_CPUN_BOOT_FROM_COLD_RESET = (0 << PRCM_CPUN_BOOT_FLAG_SHIFT), + PRCM_CPUN_BOOT_FROM_DEEPSLEEP = (1 << PRCM_CPUN_BOOT_FLAG_SHIFT) +} PRCM_CPUNBootFlag; + +/* PRCM->CPUN_BOOT_ADDR */ + +/* PRCM->CPUN_BOOT_ARG */ + +/* PRCM->CPUA_PRIV_REG */ + +/* + * bit field definition of + * - PRCM->CPUA_WAKE_TIMER_CNT + * - PRCM->CPUN_WAKE_TIMER_CNT + */ +#define PRCM_CPUx_WAKE_TIMER_EN_BIT HAL_BIT(31) /* R/W */ +#define PRCM_CPUx_WAKE_TIMER_CUR_VAL_MASK 0x7FFFFFFFU /* R */ + +/* + * bit field definition of + * - PRCM->CPUA_WAKE_TIMER_CMP + * - PRCM->CPUN_WAKE_TIMER_CMP + */ +#define PRCM_CPUx_WAKE_TIMER_PENDING_BIT HAL_BIT(31) /* R/W */ +#define PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK 0x7FFFFFFFU /* R/W */ + +/* + * bit field definition of + * - PRCM->CPUA_WAKE_IO_EN + * - PRCM->CPUA_WAKE_IO_MODE + * - PRCM->CPUA_WAKE_IO_STATUS + * - PRCM->CPUA_WAKE_IO_HOLD + */ + +#define PRCM_WAKE_IO_MASK (0x3FFU) +typedef enum { + PRCM_WAKE_IO_0 = HAL_BIT(0), + PRCM_WAKE_IO_1 = HAL_BIT(1), + PRCM_WAKE_IO_2 = HAL_BIT(2), + PRCM_WAKE_IO_3 = HAL_BIT(3), + PRCM_WAKE_IO_4 = HAL_BIT(4), + PRCM_WAKE_IO_5 = HAL_BIT(5), + PRCM_WAKE_IO_6 = HAL_BIT(6), + PRCM_WAKE_IO_7 = HAL_BIT(7), + PRCM_WAKE_IO_8 = HAL_BIT(8), + PRCM_WAKE_IO_9 = HAL_BIT(9) +} PRCM_WakeIO; + +typedef enum { + PRCM_WAKE_IO_EVT_FALLING_EDGE = 0U, + PRCM_WAKE_IO_EVT_RISING_EDGE = 1U, +} PRCM_WakeIOEvent; + +/* + * bit field definition of PRCM->CPUA_WAKE_IO_GLOBAL_EN + */ +#define PRCM_WAKE_IO_GLOBAL_EN_BIT HAL_BIT(0) + +/* + * bit field definition of PRCM->CPUA_PRCM_REG + */ +#define PRCM_CPUA_PRCM_REG_BIT HAL_BIT(0) + +/* DCDC_PARAM_CTRL */ +#define PRCM_DCDC_BANDGAP_TRIM_SHIFT 25 +#define PRCM_DCDC_BANDGAP_TRIM_MASK (0xFU << PRCM_DCDC_BANDGAP_TRIM_SHIFT) + +/* ANA_BANDGAP */ + +/* CLK_LDO_PARAM */ + +/* DIG_LDO_PARAM */ +#define PRCM_DIG_LDO_BANDGAP_TRIM_SHIFT 8 +#define PRCM_DIG_LDO_BANDGAP_TRIM_MASK (0xFU << PRCM_DIG_LDO_BANDGAP_TRIM_SHIFT) + +/* DPLL_STATUS */ + +/******************************************************************************/ +void HAL_PRCM_SetDCDCVoltage(PRCM_DCDCVolt volt); +uint32_t HAL_PRCM_GetSysPowerEnableFlags(void); +void HAL_PRCM_EnableSys2Power(void); +void HAL_PRCM_DisableSys2Power(void); +void HAL_PRCM_SetLDO1Voltage(PRCM_LDO1Volt volt); +uint32_t HAL_PRCM_GetLDOEnableFlags(void); + +void HAL_PRCM_SetLFCLKSource(PRCM_LFCLKSrc src); +void HAL_PRCM_SetHOSCType(PRCM_HOSCType type); +uint32_t HAL_PRCM_GetHOSCType(void); +uint32_t HAL_PRCM_GetHFClock(void); +uint32_t HAL_PRCM_GetInter32KFreq(void); +uint32_t HAL_PRCM_EnableInter32KCalib(void); +uint32_t HAL_PRCM_DisableInter32KCalib(void); +#if 0 +void HAL_PRCM_SetSysPLLParam(PRCM_SysPLLParam param); +void HAL_PRCM_EnableSysPLL(void); +#else +void HAL_PRCM_SetSysPLL(PRCM_SysPLLParam param); +#endif +void HAL_PRCM_DisableSysPLL(void); +void HAL_PRCM_SetCPUAClk(PRCM_CPUClkSrc src, PRCM_SysClkFactor factor); +void HAL_PRCM_DisCLK1(PRCM_SysClkFactor factor); +uint32_t HAL_PRCM_GetCPUAClk(void); +void HAL_PRCM_SetAudioPLLParam(PRCM_AudPLLParam param); +void HAL_PRCM_EnableAudioPLL(void); +void HAL_PRCM_DisableAudioPLL(void); +void HAL_PRCM_SetDevClock(PRCM_DevClkFactor factor); +uint32_t HAL_PRCM_GetDevClock(void); +void HAL_PRCM_SetAudioPLLPatternParam(PRCM_AudPLLPatParam param); +void HAL_PRCM_EnableAudioPLLPattern(void); +void HAL_PRCM_DisableAudioPLLPattern(void); + +int HAL_PRCM_IsCPUAResetRelease(void); +int HAL_PRCM_IsSys1ResetRelease(void); +void HAL_PRCM_AllowCPUNDeepSleep(void); +void HAL_PRCM_DisallowCPUNDeepSleep(void); +int HAL_PRCM_IsCPUNDeepSleepAllowed(void); +int HAL_PRCM_IsCPUASleep(void); +int HAL_PRCM_IsCPUADeepSleep(void); +int HAL_PRCM_IsSys1Alive(void); + +void HAL_PRCM_DisableSys2(void); +void HAL_PRCM_EnableSys2Isolation(void); +void HAL_PRCM_DisableSys2Isolation(void); +void HAL_PRCM_ForceCPUNReset(void); +void HAL_PRCM_ReleaseCPUNReset(void); +int HAL_PRCM_IsCPUNReleased(void); +void HAL_PRCM_ForceSys2Reset(void); +void HAL_PRCM_ReleaseSys2Reset(void); + +int HAL_PRCM_IsCPUADeepSleepAllowed(void); +int HAL_PRCM_IsCPUNSleep(void); +int HAL_PRCM_IsCPUNDeepSleep(void); +int HAL_PRCM_IsSys2Alive(void); +int HAL_PRCM_IsSys3Alive(void); +void HAL_PRCM_SetSys1WakeupPowerFlags(uint32_t flags); +uint32_t HAL_PRCM_GetSys2WakeupPowerFlags(void); +uint32_t HAL_PRCM_GetSys1SleepPowerFlags(void); +void HAL_PRCM_SetSys1SleepPowerFlags(uint32_t flags); +uint32_t HAL_PRCM_GetSys2SleepPowerFlags(void); +void HAL_PRCM_SetSRAMVoltage(PRCM_SRAMVolt workVolt, PRCM_SRAMVolt retenVolt); +void HAL_PRCM_SetBANDGAPSTABLE_TIME(uint32_t time); +void HAL_PRCM_SetDCDCSTABLE_TIME(uint32_t time); +uint32_t HAL_PRCM_GetBANDGAPSTABLE_TIME(void); +uint32_t HAL_PRCM_GetDCDCSTABLE_TIME(void); +void HAL_PRCM_SetCPUABootFlag(PRCM_CPUABootFlag flag); +uint32_t HAL_PRCM_GetCPUABootFlag(void); +void HAL_PRCM_SetCPUABootAddr(uint32_t addr); +uint32_t HAL_PRCM_GetCPUABootAddr(void); +void HAL_PRCM_SetCPUABootArg(uint32_t arg); +uint32_t HAL_PRCM_GetCPUABootArg(void); +void HAL_PRCM_SetCPUAPrivateData(uint32_t data); +uint32_t HAL_PRCM_GetCPUAPrivateData(void); + +uint32_t HAL_PRCM_GetWakeupTimerEnable(void); +void HAL_PRCM_WakeupTimerEnable(void); +void HAL_PRCM_WakeupTimerDisable(void); +uint32_t HAL_PRCM_WakeupTimerGetCurrentValue(void); +uint32_t HAL_PRCM_GetWakeupTimerPending(void); +void HAL_PRCM_ClearWakeupTimerPending(void); +void HAL_PRCM_WakeupTimerSetCompareValue(uint32_t val); +uint32_t HAL_PRCM_WakeupTimerGetCompareValue(void); + +void HAL_PRCM_WakeupIOEnable(uint32_t ioMask); +void HAL_PRCM_WakeupIODisable(uint32_t ioMask); +void HAL_PRCM_WakeupIOSetRisingEvent(uint32_t ioMask); +void HAL_PRCM_WakeupIOSetFallingEvent(uint32_t ioMask); +uint32_t HAL_PRCM_WakeupIOGetEventStatus(void); +int HAL_PRCM_WakeupIOIsEventDetected(uint32_t ioMask); +void HAL_PRCM_WakeupIOClearEventDetected(uint32_t ioMask); +void HAL_PRCM_WakeupIOEnableCfgHold(uint32_t ioMask); +void HAL_PRCM_WakeupIODisableCfgHold(uint32_t ioMask); +void HAL_PRCM_WakeupIOEnableGlobal(void); +void HAL_PRCM_WakeupIODisableGlobal(void); +void HAL_PRCM_Start(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_PRCM_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_pwm.h b/platform/mcu/xr871/include/driver/chip/hal_pwm.h new file mode 100644 index 0000000000..da1992bd59 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_pwm.h @@ -0,0 +1,285 @@ +/** + * @file hal_pwm.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_PWM_H_ +#define _DRIVER_CHIP_HAL_PWM_H_ + +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_clock.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief PWM group id. + */ +typedef enum { + PWM_GROUP_0, /*!CTRL + */ +#define RTC_TEST_MODE_BIT HAL_BIT(31) +#define RTC_SIMULATION_BIT HAL_BIT(30) +#define RTC_WDAY_ALARM_HHMMSS_ACCESS_BIT HAL_BIT(2) +#define RTC_DDHHMMSS_ACCESS_BIT HAL_BIT(1) +#define RTC_YYMMDD_ACCESS_BIT HAL_BIT(0) + +/* + * Bit field definition of RTC->YYMMDD + */ +#define RTC_LEAP_YEAR_BIT HAL_BIT(24) + +#define RTC_YEAR_SHIFT 16 /* R/W, [0, 255] */ +#define RTC_YEAR_VMASK 0xFF +#define RTC_YEAR_MIN 0 +#define RTC_YEAR_MAX 255 + +#define RTC_MONTH_SHIFT 8 /* R/W, [1, 12] */ +#define RTC_MONTH_VMASK 0xF +#define RTC_MONTH_MIN 1 +#define RTC_MONTH_MAX 12 + +#define RTC_MDAY_SHIFT 0 /* R/W, [1, 31] */ +#define RTC_MDAY_VMASK 0x1F +#define RTC_MDAY_MIN 1 +#define RTC_MDAY_MAX 31 + +/* + * Bit field definition of RTC->DDHHMMSS + */ +#define RTC_WDAY_SHIFT 29 /* R/W */ +#define RTC_WDAY_VMASK 0x7 +typedef enum { + RTC_WDAY_MONDAY = 0U, + RTC_WDAY_TUESDAY = 1U, + RTC_WDAY_WEDNESDAY = 2U, + RTC_WDAY_THURSDAY = 3U, + RTC_WDAY_FRIDAY = 4U, + RTC_WDAY_SATURDAY = 5U, + RTC_WDAY_SUNDAY = 6U +} RTC_WeekDay; + +#define RTC_HOUR_SHIFT 16 /* R/W, [0, 23] */ +#define RTC_HOUR_VMASK 0x1F +#define RTC_HOUR_MIN 0 +#define RTC_HOUR_MAX 23 + +#define RTC_MINUTE_SHIFT 8 /* R/W, [0, 59] */ +#define RTC_MINUTE_VMASK 0x3F +#define RTC_MINUTE_MIN 0 +#define RTC_MINUTE_MAX 59 + +#define RTC_SECOND_SHIFT 0 /* R/W, [0, 59] */ +#define RTC_SECOND_VMASK 0x3F +#define RTC_SECOND_MIN 0 +#define RTC_SECOND_MAX 59 + +/* RTC->SEC_ALARM_LOAD_VAL */ + +/* RTC->SEC_ALARM_CUR_VAL */ + +/* RTC->SEC_ALARM_EN */ +#define RTC_SEC_ALARM_EN_BIT HAL_BIT(0) + +/* RTC->SEC_ALARM_IRQ_EN */ +#define RTC_SEC_ALARM_IRQ_EN_BIT HAL_BIT(0) + +/* RTC->SEC_ALARM_IRQ_STATUS */ +#define RTC_SEC_ALARM_IRQ_PENDING_BIT HAL_BIT(0) + +/* RTC->WDAY_ALARM_DDHHMMSS */ +#define RTC_WDAY_ALARM_HOUR_SHIFT 16 /* R/W, [0, 23] */ +#define RTC_WDAY_ALARM_HOUR_VMASK 0x1F + +#define RTC_WDAY_ALARM_MINUTE_SHIFT 8 /* R/W, [0, 59] */ +#define RTC_WDAY_ALARM_MINUTE_VMASK 0x3F + +#define RTC_WDAY_ALARM_SECOND_SHIFT 0 /* R/W, [0, 59] */ +#define RTC_WDAY_ALARM_SECOND_VMASK 0x3F + +/* RTC->WDAY_ALARM_EN */ +#define RTC_WDAY_ALARM_EN_BIT(wday) HAL_BIT(wday) /* day is RTC_WeekDay */ +#define RTC_WDAY_ALARM_EN_MASK 0x7F + +/* RTC->WDAY_ALARM_IRQ_EN */ +#define RTC_WDAY_ALARM_IRQ_EN_BIT HAL_BIT(0) + +/* RTC->WDAY_ALARM_IRQ_STATUS */ +#define RTC_WDAY_ALARM_IRQ_PENDING_BIT HAL_BIT(0) + +/******************************************************************************/ + +/** @brief Type define of RTC alarm IRQ callback function */ +typedef void (*RTC_AlarmIRQCallback) (void *arg); + +/** + * @brief RTC second alarm starting parameters + */ +typedef struct { + uint32_t alarmSeconds; /* RTC second alarm's count down value */ + RTC_AlarmIRQCallback callback; /* RTC second alarm IRQ callback function */ + void *arg; /* Argument of RTC second alarm IRQ callback function */ +} RTC_SecAlarmStartParam; + +/** + * @brief RTC weekday alarm starting parameters + */ +typedef struct { + uint8_t alarmHour; /* RTC weekday alarm's hour, [0, 23] */ + uint8_t alarmMinute; /* RTC weekday alarm's minute, [0, 59] */ + uint8_t alarmSecond; /* RTC weekday alarm's second, [0, 59] */ + uint8_t alarmWDayMask; /* RTC weekday alarm's weekday, bit mask of RTC_WDAY_ALARM_EN_BIT(RTC_WeekDay) */ + RTC_AlarmIRQCallback callback; /* RTC weekday alarm IRQ callback function */ + void *arg; /* Argument of RTC weekday alarm IRQ callback function */ +} RTC_WDayAlarmStartParam; + +void HAL_RTC_SetYYMMDD(uint8_t isLeapYear, uint8_t year, uint8_t month, uint8_t mday); +void HAL_RTC_SetDDHHMMSS(RTC_WeekDay wday, uint8_t hour, uint8_t minute, uint8_t second); + +void HAL_RTC_GetYYMMDD(uint8_t *isLeapYear, uint8_t *year, uint8_t *month, uint8_t *mday); +void HAL_RTC_GetDDHHMMSS(RTC_WeekDay *wday, uint8_t *hour, uint8_t *minute, uint8_t *second) ; + +void HAL_RTC_StartSecAlarm(const RTC_SecAlarmStartParam *param); +void HAL_RTC_StopSecAlarm(void); + +void HAL_RTC_StartWDayAlarm(const RTC_WDayAlarmStartParam *param); +void HAL_RTC_StopWDayAlarm(void); + +uint64_t HAL_RTC_GetFreeRunTime(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_RTC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_spi.h b/platform/mcu/xr871/include/driver/chip/hal_spi.h new file mode 100644 index 0000000000..f92af35026 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_spi.h @@ -0,0 +1,482 @@ +/** + * @file hal_spi.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_SPI_H_ +#define _DRIVER_CHIP_HAL_SPI_H_ + +#include +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_dma.h" +#include "driver/chip/hal_gpio.h" +#include "sys/xr_debug.h" + +#ifdef __cplusplus +extern "C" { +#endif +/********************** private ************************************/ + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __I uint32_t VER; /*!< SPI Version number Register, Address offset: 0x00 */ + __IO uint32_t CTRL; /*!< SPI Global Control Register, Address offset: 0x04 */ + __IO uint32_t TCTRL; /*!< SPI Transfer Control Register, Address offset: 0x08 */ + uint32_t RESERVED1[1]; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Control Register, Address offset: 0x10 */ + __IO uint32_t STA; /*!< SPI Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t FCTL; /*!< SPI FIFO Control Register, Address offset: 0x18 */ + __I uint32_t FST; /*!< SPI FIFO Status Register, Address offset: 0x1C */ + __IO uint32_t WAIT; /*!< SPI Wait Clock Counter Register, Address offset: 0x20 */ + __IO uint32_t CCTR; /*!< SPI Clock Rate Control Register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t BC; /*!< SPI Master mode Burst Control Register, Address offset: 0x30 */ + __IO uint32_t TC; /*!< SPI Master mode Transmit Counter Register, Address offset: 0x34 */ + __IO uint32_t BCC; /*!< SPI Burst Control Register, Address offset: 0x38 */ + uint32_t RESERVED3[19]; /*!< Reserved, Address offset: 0x3C-0x84 */ + __IO uint32_t NDMA_MODE_CTRL; /*!< SPI Nomal DMA Mode Control Regist Address offset: 0x88 */ + uint32_t RESERVED4[93]; /*!< Reserved, Address offset: 0x8C-0x1FC */ + __IO uint32_t TXD; /*!< SPI TX Date Register, Address offset: 0x200 */ + uint32_t RESERVED5[63]; /*!< Reserved, Address offset: 0x204-0x2FC */ + __I uint32_t RXD; /*!< SPI RX Date Register, Address offset: 0x300 */ +} SPI_T; + +/* + * @brief SPI Global Control Register + */ +#define SPI_CTRL_RST_SHIFT (31) +#define SPI_CTRL_RST_MASK (0x1U << SPI_CTRL_RST_SHIFT) + +#define SPI_CTRL_TP_EN_SHIFT (7) +#define SPI_CTRL_TP_EN_MASK (0x1U << SPI_CTRL_TP_EN_SHIFT) + +#define SPI_CTRL_MODE_SHIFT (1) +#define SPI_CTRL_MODE_MASK (0x1U << SPI_CTRL_MODE_SHIFT) +typedef enum { + SPI_CTRL_MODE_SLAVE = 0 << SPI_CTRL_MODE_SHIFT, + SPI_CTRL_MODE_MASTER = 1 << SPI_CTRL_MODE_SHIFT +} SPI_CTRL_Mode; + +#define SPI_CTRL_EN_SHIFT (0) +#define SPI_CTRL_EN_MASK (0x1U << SPI_CTRL_EN_SHIFT) +typedef enum { + SPI_CTRL_EN_DISABLE = 0 << SPI_CTRL_EN_SHIFT, + SPI_CTRL_EN_ENABLE = 1 << SPI_CTRL_EN_SHIFT +} SPI_CTRL_En; + + +/* + * @brief SPI Transfer Control Register + */ +#define SPI_TCTRL_XCH_SHIFT (31) +#define SPI_TCTRL_XCH_MASK (0x1U << SPI_TCTRL_XCH_SHIFT) +typedef enum { + SPI_TCTRL_XCH_IDLE = 0 << SPI_TCTRL_XCH_SHIFT, + SPI_TCTRL_XCH_START = 1 << SPI_TCTRL_XCH_SHIFT +} SPI_TCTRL_Xch; + +#define SPI_TCTRL_SDDM_SHIFT (14) +#define SPI_TCTRL_SDDM_MASK (0x0U << SPI_TCTRL_SDDM_SHIFT) +typedef enum { + SPI_TCTRL_SDDM_SEND_NODELAY = 0 << SPI_TCTRL_SDDM_SHIFT, + SPI_TCTRL_SDDM_SEND_DELAY = 1 << SPI_TCTRL_SDDM_SHIFT +} SPI_TCTRL_Sddm; + +#define SPI_TCTRL_SDM_SHIFT (13) +#define SPI_TCTRL_SDM_MASK (0x1U << SPI_TCTRL_SDM_SHIFT) +typedef enum { + SPI_TCTRL_SDM_SAMPLE_NODELAY = 1 << SPI_TCTRL_SDM_SHIFT, + SPI_TCTRL_SDM_SAMPLE_DELAY = 0 << SPI_TCTRL_SDM_SHIFT +} SPI_TCTRL_Sdm; + +#define SPI_TCTRL_FBS_SHIFT (12) +#define SPI_TCTRL_FBS_MASK (0x1U << SPI_TCTRL_FBS_SHIFT) +typedef enum { + SPI_TCTRL_FBS_MSB = 0 << SPI_TCTRL_FBS_SHIFT, + SPI_TCTRL_FBS_LSB = 1 << SPI_TCTRL_FBS_SHIFT +} SPI_TCTRL_Fbs; + +#define SPI_TCTRL_SDC_SHIFT (11) +#define SPI_TCTRL_SDC_MASK (0x1U << SPI_TCTRL_SDC_SHIFT) + +#define SPI_TCTRL_RPSM_SHIFT (10) +#define SPI_TCTRL_RPSM_MASK (0x1U << SPI_TCTRL_RPSM_SHIFT) + +#define SPI_TCTRL_DDB_SHIFT (9) +#define SPI_TCTRL_DDB_MASK (0x1U << SPI_TCTRL_DDB_SHIFT) + +#define SPI_TCTRL_DHB_SHIFT (8) +#define SPI_TCTRL_DHB_MASK (0x1U << SPI_TCTRL_DHB_SHIFT) +typedef enum { + SPI_TCTRL_DHB_FULL_DUPLEX = 0 << SPI_TCTRL_DHB_SHIFT, + SPI_TCTRL_DHB_HALF_DUPLEX = 1 << SPI_TCTRL_DHB_SHIFT +} SPI_TCTRL_DHB_Duplex; + +#define SPI_TCTRL_SS_LEVEL_SHIFT (7) +#define SPI_TCTRL_SS_LEVEL_MASK (0x1U << SPI_TCTRL_SS_LEVEL_SHIFT) + +#define SPI_TCTRL_SS_OWNER_SHIFT (6) +#define SPI_TCTRL_SS_OWNER_MASK (0x1U << SPI_TCTRL_SS_OWNER_SHIFT) +typedef enum { + SPI_TCTRL_SS_OWNER_CONTROLLER = 0 << SPI_TCTRL_SS_OWNER_SHIFT, + SPI_TCTRL_SS_OWNER_SOFTWARE = 1 << SPI_TCTRL_SS_OWNER_SHIFT +} SPI_TCTRL_SS_OWNER; + +#define SPI_TCTRL_SS_SEL_SHIFT (4) +#define SPI_TCTRL_SS_SEL_MASK (0x3U << SPI_TCTRL_SS_SEL_SHIFT) +typedef enum { + SPI_TCTRL_SS_SEL_SS0 = 0 << SPI_TCTRL_SS_SEL_SHIFT, + SPI_TCTRL_SS_SEL_SS1 = 1 << SPI_TCTRL_SS_SEL_SHIFT, + SPI_TCTRL_SS_SEL_SS2 = 2 << SPI_TCTRL_SS_SEL_SHIFT, + SPI_TCTRL_SS_SEL_SS3 = 3 << SPI_TCTRL_SS_SEL_SHIFT +} SPI_TCTRL_SS_Sel; + +#define SPI_TCTRL_SS_CTL_SHIFT (3) +#define SPI_TCTRL_SS_CTL_MASK (0x1U << SPI_TCTRL_SS_CTL_SHIFT) + +#define SPI_TCTRL_SPOL_SHIFT (2) +#define SPI_TCTRL_SPOL_MASK (0x1U << SPI_TCTRL_SPOL_SHIFT) + +#define SPI_TCTRL_CPOL_SHIFT (1) +#define SPI_TCTRL_CPOL_MASK (0x1U << SPI_TCTRL_CPOL_SHIFT) +typedef enum { + SPI_TCTRL_CPOL_HIGH = 0 << SPI_TCTRL_CPOL_SHIFT, + SPI_TCTRL_CPOL_LOW = 1 << SPI_TCTRL_CPOL_SHIFT +} SPI_TCTRL_Cpol; + +#define SPI_TCTRL_CPHA_SHIFT (0) +#define SPI_TCTRL_CPHA_MASK (0x1U << SPI_TCTRL_CPHA_SHIFT) +typedef enum { + SPI_TCTRL_CPHA_PHASE0 = 0 << SPI_TCTRL_CPHA_SHIFT, + SPI_TCTRL_CPHA_PHASE1 = 1 << SPI_TCTRL_CPHA_SHIFT +} SPI_TCTRL_Cpha; + +typedef enum { + SPI_SCLK_Mode0 = 0 << SPI_TCTRL_CPHA_SHIFT, + SPI_SCLK_Mode1 = 1 << SPI_TCTRL_CPHA_SHIFT, + SPI_SCLK_Mode2 = 2 << SPI_TCTRL_CPHA_SHIFT, + SPI_SCLK_Mode3 = 3 << SPI_TCTRL_CPHA_SHIFT +} SPI_SCLK_Mode; +/* + * @brief SPI Interrupt Control Register + */ +#define SPI_IER_SS_INT_EN_SHIFT (13) +#define SPI_IER_SS_INT_EN_MASK (0x1U << SPI_IER_SS_INT_EN_SHIFT) + +#define SPI_IER_TC_INT_EN_SHIFT (12) +#define SPI_IER_TC_INT_EN_MASK (0x1U << SPI_IER_TC_INT_EN_SHIFT) + +#define SPI_IER_TF_UDR_INT_EN_SHIFT (11) +#define SPI_IER_TF_UDR_INT_EN_MASK (0x1U << SPI_IER_TF_UDR_INT_EN_SHIFT) + +#define SPI_IER_TF_OVF_INT_EN_SHIFT (10) +#define SPI_IER_TF_OVF_INT_EN_MASK (0x1U << SPI_IER_TF_OVF_INT_EN_SHIFT) + +#define SPI_IER_RF_UDR_INT_EN_SHIFT (9) +#define SPI_IER_RF_UDR_INT_EN_MASK (0x1U << SPI_IER_RF_UDR_INT_EN_SHIFT) + +#define SPI_IER_RF_OVF_INT_EN_SHIFT (8) +#define SPI_IER_RF_OVF_INT_EN_MASK (0x1U << SPI_IER_RF_OVF_INT_EN_SHIFT) + +#define SPI_IER_TF_FUL_INT_EN_SHIFT (6) +#define SPI_IER_TF_FUL_INT_EN_MASK (0x1U << SPI_IER_TF_FUL_INT_EN_SHIFT) + +#define SPI_IER_TX_EMP_INT_EN_SHIFT (5) +#define SPI_IER_TX_EMP_INT_EN_MASK (0x1U << SPI_IER_TX_EMP_INT_EN_SHIFT) + +#define SPI_IER_TX_ERQ_INT_EN_SHIFT (4) +#define SPI_IER_TX_ERQ_INT_EN_MASK (0x1U << SPI_IER_TX_ERQ_INT_EN_SHIFT) + +#define SPI_IER_RF_FUL_INT_EN_SHIFT (2) +#define SPI_IER_RF_FUL_INT_EN_MASK (0x1U << SPI_IER_RF_FUL_INT_EN_SHIFT) + +#define SPI_IER_RX_EMP_INT_EN_SHIFT (1) +#define SPI_IER_RX_EMP_INT_EN_MASK (0x1U << SPI_IER_RX_EMP_INT_EN_SHIFT) + +#define SPI_IER_RF_RDY_INT_EN_SHIFT (0) +#define SPI_IER_RF_RDY_INT_EN_MASK (0x1U << SPI_IER_RF_RDY_INT_EN_SHIFT) + +/* + * @brief SPI Interrupt Status Register + */ +#define SPI_STA_SSI_SHIFT (13) +#define SPI_STA_SSI_MASK (0x1U << SPI_STA_SSI_SHIFT) + +#define SPI_STA_TC_SHIFT (12) +#define SPI_STA_TC_MASK (0x1U << SPI_STA_TC_SHIFT) + +#define SPI_STA_TF_UDF_SHIFT (11) +#define SPI_STA_TF_UDF_MASK (0x1U << SPI_STA_TF_UDF_SHIFT) + +#define SPI_STA_TF_OVF_SHIFT (10) +#define SPI_STA_TF_OVF_MASK (0x1U << SPI_STA_TF_OVF_SHIFT) + +#define SPI_STA_RX_UDF_SHIFT (9) +#define SPI_STA_RX_UDF_MASK (0x1U << SPI_STA_RX_UDF_SHIFT) + +#define SPI_STA_RX_OVF_SHIFT (8) +#define SPI_STA_RX_OVF_MASK (0x1U << SPI_STA_RX_OVF_SHIFT) + +#define SPI_STA_TX_FULL_SHIFT (6) +#define SPI_STA_TX_FULL_MASK (0x1U << SPI_STA_TX_FULL_SHIFT) + +#define SPI_STA_TX_EMP_SHIFT (5) +#define SPI_STA_TX_EMP_MASK (0x1U << SPI_STA_TX_EMP_SHIFT) + +#define SPI_STA_TX_READY_SHIFT (4) +#define SPI_STA_TX_READY_MASK (0x1U << SPI_STA_TX_READY_SHIFT) + +#define SPI_STA_RX_FULL_SHIFT (2) +#define SPI_STA_RX_FULL_MASK (0x1U << SPI_STA_RX_FULL_SHIFT) + +#define SPI_STA_RX_EMP_SHIFT (1) +#define SPI_STA_RX_EMP_MASK (0x1U << SPI_STA_RX_EMP_SHIFT) + +#define SPI_STA_RX_RDY_SHIFT (0) +#define SPI_STA_RX_RDY_MASK (0x1U << SPI_STA_RX_RDY_SHIFT) + +/* + * @brief SPI FIFO Control Register + */ +#define SPI_FCTL_TF_RST_SHIFT (31) +#define SPI_FCTL_TF_RST_MASK (0x1U << SPI_FCTL_TF_RST_SHIFT) + +#define SPI_FCTL_TF_TEST_EN_SHIFT (30) +#define SPI_FCTL_TF_TEST_EN_MASK (0x1U << SPI_FCTL_TF_TEST_EN_SHIFT) + +#define SPI_FCTL_TF_DRQ_EN_SHIFT (24) +#define SPI_FCTL_TF_DRQ_EN_MASK (0x1U << SPI_FCTL_TF_DRQ_EN_SHIFT) +#define SPI_FCTL_TF_DRQ_EN_BIT HAL_BIT(24) + +#define SPI_FCTL_TX_TRIG_LEVEL_SHIFT (16) +#define SPI_FCTL_TX_TRIG_LEVEL_MASK (0xFFU << SPI_FCTL_TX_TRIG_LEVEL_SHIFT) + +#define SPI_FCTL_RF_RST_SHIFT (15) +#define SPI_FCTL_RF_RST_MASK (0x1U << SPI_FCTL_RF_RST_SHIFT) + +#define SPI_FCTL_RF_TEST_SHIFT (14) +#define SPI_FCTL_RF_TEST_MASK (0x1U << SPI_FCTL_RF_TEST_SHIFT) + +#define SPI_FCTL_RF_DRQ_EN_SHIFT (8) +#define SPI_FCTL_RF_DRQ_EN_MASK (0x1U << SPI_FCTL_RF_DRQ_EN_SHIFT) + +#define SPI_FCTL_RX_TRIG_LEVEL_SHIFT (0) +#define SPI_FCTL_RX_TRIG_LEVEL_MASK (0xFFU << SPI_FCTL_RX_TRIG_LEVEL_SHIFT) + +/* + * @brief SPI FIFO Status Registe + */ +#define SPI_FST_TB_WR_SHIFT (31) +#define SPI_FST_TB_WR_MASK (0x1U << SPI_FST_TB_WR_SHIFT) + +#define SPI_FST_TB_CNT_SHIFT (28) +#define SPI_FST_TB_CNT_MASK (0x7U << SPI_FST_TB_CNT_SHIFT) + +#define SPI_FST_TF_CNT_SHIFT (16) +#define SPI_FST_TF_CNT_MASK (0xFFU << SPI_FST_TF_CNT_SHIFT) + +#define SPI_FST_RB_WR_SHIFT (15) +#define SPI_FST_RB_WR_MASK (0x1U << SPI_FST_RB_WR_SHIFT) + +#define SPI_FST_RB_CNT_SHIFT (12) +#define SPI_FST_RB_CNT_MASK (0x7U << SPI_FST_RB_CNT_SHIFT) + +#define SPI_FST_RF_CNT_SHIFT (0) +#define SPI_FST_RF_CNT_MASK (0xFFU << SPI_FST_RF_CNT_SHIFT) + +/* + * @brief SPI Wait Clock Counter Register + */ +#define SPI_WAIT_SWC_SHIFT (16) +#define SPI_WAIT_SWC_MASK (0xFU << SPI_WAIT_SWC_SHIFT) + +#define SPI_WAIT_WCC_SHIFT (0) +#define SPI_WAIT_WCC_MASK (0xFFFFU << SPI_WAIT_WCC_SHIFT) + +/* + * @brief SPI Clock Rate Control Register + */ +#define SPI_CCTR_DRS_SHIFT (12) +#define SPI_CCTR_DRS_MASK (0x1U << SPI_CCTR_DRS_SHIFT) +typedef enum { + SPI_CCTR_DRS_type_divRate1 = 0 << SPI_CCTR_DRS_SHIFT, + SPI_CCTR_DRS_type_divRate2 = 1 << SPI_CCTR_DRS_SHIFT +} SPI_CCTR_DRS_type; + +#define SPI_CCTR_CDR1_SHIFT (8) +#define SPI_CCTR_CDR1_MASK (0xFU << SPI_CCTR_CDR1_SHIFT) + +#define SPI_CCTR_CDR2_SHIFT (0) +#define SPI_CCTR_CDR2_MASK (0xFFU << SPI_CCTR_CDR2_SHIFT) + +/* + * @brief SPI Master mode Burst Control Register + */ +#define SPI_BC_MBC_SHIFT (0) +#define SPI_BC_MBC_MASK (0xFFFFFFU << SPI_BC_MBC_SHIFT) + +/* + * @brief SPI Master mode Transmit Counter Register + */ +#define SPI_TC_MWTC_SHIFT (0) +#define SPI_TC_MWTC_MASK (0xFFFFFFU << SPI_TC_MWTC_SHIFT) + +/* + * @brief SPI Burst Control Register + */ +#define SPI_BCC_DRM_SHIFT (28) +#define SPI_BCC_DRM_MASK (0x1U << SPI_BCC_DRM_SHIFT) + +#define SPI_BCC_DBC_SHIFT (24) +#define SPI_BCC_DBC_MASK (0xFU << SPI_BCC_DBC_SHIFT) + +#define SPI_BCC_STC_SHIFT (0) +#define SPI_BCC_STC_MASK (0xFFFFFFU << SPI_BCC_STC_SHIFT) + +/* + * @brief SPI Nomal DMA Mode Control Regist + */ +#define SPI_NDMA_MODE_CTRL_SHIFT (0) +#define SPI_NDMA_MODE_CTRL_MASK (0xFFU << SPI_NDMA_MODE_CTRL_SHIFT) + +/* + * @brief SPI TX Date Register + */ +#define SPI_TXD_SHIFT (0) +#define SPI_TXD_MASK (0xFFFFFFFFU << SPI_TXD_SHIFT) + +/* + * @brief SPI RX Date Register + */ +#define SPI_RXD_SHIFT (0) +#define SPI_RXD_MASK (0xFFFFFFFFU << SPI_RXD_SHIFT) + + +#define SPI_FIFO_SIZE (64) + +/************************ public **************************************/ +typedef enum { + SPI0 = 0, /*!< SPI0 controller */ + SPI1 = 1, /*!< SPI1 controller */ + SPI_NUM = 2 /*!< only support 2 SPI controller for now */ +} SPI_Port; + +typedef SPI_CTRL_Mode SPI_Mode; + +typedef SPI_TCTRL_Fbs SPI_FirstBit; + +typedef SPI_TCTRL_DHB_Duplex SPI_Duplex; + +typedef enum { + SPI_CS_MODE_AUTO, /*!< auto chip select mode */ + SPI_CS_MODE_MANUAL /*!< manual chip select mode */ +} SPI_CS_Mode; + +typedef SPI_TCTRL_SS_Sel SPI_CS; + +typedef SPI_SCLK_Mode SPI_SclkMode; + +typedef enum { + SPI_OPERATION_MODE_DMA, /*!< dma mode moving data */ + SPI_OPERATION_MODE_POLL /*!< cpu mode moving data */ +} SPI_Operation_Mode; + +typedef enum { + SPI_IO_MODE_NORMAL, /*!< MOSI to transmit data, MISO to receive data */ + SPI_IO_MODE_DUAL_RX, /*!< MOSI and MISO to receive data */ + SPI_IO_MODE_DUAL_TX, /*!< not support */ + SPI_IO_MODE_QUAD_RX, /*!< not support */ + SPI_IO_MODE_QUAD_TX /*!< not support */ +} SPI_IO_Mode; + +typedef enum { + SPI_ATTRIBUTION_IO_MODE +} SPI_Attribution; + +typedef struct { + SPI_Mode mode; /*!< SPI master mode or slave mode, only master mode for now */ + SPI_Operation_Mode opMode; /*!< dma mode or poll(cpu) mode */ + SPI_FirstBit firstBit; /*!< msb or lsb on line */ + uint32_t sclk; /*!< device sclk frequency */ + SPI_SclkMode sclkMode; /*!< device sclk mode */ +} SPI_Config; + +#define SPI_CONFIG_DEFAULT \ + { \ + .sclk = 6000000, \ + .sclkMode = SPI_SCLK_Mode0, \ + .firstBit = SPI_TCTRL_FBS_MSB, \ + .mode = SPI_CTRL_MODE_MASTER, \ + .opMode = SPI_OPERATION_MODE_POLL \ + } + +typedef struct { + SPI_Port port; /*!< spi port */ + SPI_CS cs; /*!< spi cs pin */ + SPI_Config config; /*!< spi device config */ +} SPI_Device; + +typedef struct { + uint32_t mclk; /*!< SPI main working frequency */ + bool cs_level; /*!< the cs voltage level of chip running */ +} SPI_Global_Config; + +/* + * @brief + * reset(not init) <--> ready(inited/closed) <--> busy(opened) <--> tx/rx/tx_rx(transmitting) + * + * each state --> error + */ +HAL_Status HAL_SPI_Init(SPI_Port port, const SPI_Global_Config *gconfig); +HAL_Status HAL_SPI_Deinit(SPI_Port port); +HAL_Status HAL_SPI_Receive(SPI_Port port, uint8_t *data, uint32_t size); +HAL_Status HAL_SPI_Transmit(SPI_Port port, uint8_t *data, uint32_t size); +HAL_Status HAL_SPI_TransmitReceive(SPI_Port port, uint8_t *tx_data, uint8_t *rx_data, uint32_t size); +HAL_Status HAL_SPI_Open(SPI_Port port, SPI_CS cs, SPI_Config *config, uint32_t msec); +HAL_Status HAL_SPI_Close(SPI_Port port); +HAL_Status HAL_SPI_CS(SPI_Port port, bool select); +HAL_Status HAL_SPI_Config(SPI_Port port, SPI_Attribution attr, uint32_t arg); +void HAL_SPI_Test(); +void HAL_SPI_TestByFlash(); + +#define SPI_MAX_WAIT_MS (2000) + +//#define SPI_SOURCE_CLK (24 * 1000 * 1000) + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_SPI_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_spinlock.h b/platform/mcu/xr871/include/driver/chip/hal_spinlock.h new file mode 100644 index 0000000000..a02687eb96 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_spinlock.h @@ -0,0 +1,71 @@ +/** + * @file hal_spinlock.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_SPINLOCK_H_ +#define _DRIVER_CHIP_HAL_SPINLOCK_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPINLOCK_SYSTATUS_REG (__IO uint32_t*) (SPINLOCK_BASE + 0X0) +#define SPINLOCK_STATUS_REG (__IO uint32_t*) (SPINLOCK_BASE + 0X10) +#define SPINLOCKN_LOCK_REG(n) (__IO uint32_t*) (SPINLOCK_BASE + 0X100 + (n) * 4) + +#define SPINLOCK_NUM (0X03 << 28) +#define IU0 HAL_BIT(8) +#define SPINLOCK_TAKEN HAL_BIT(0) + + +/** + * @brief spinlock info. + */ +typedef struct SPIN_Lock_t { + int lock; +} SPIN_Lock_t; + +HAL_Status HAL_SPIN_Init(); +HAL_Status HAL_SPIN_Deinit(); +HAL_Status HAL_SPIN_RequestLock(SPIN_Lock_t *lock); +HAL_Status HAL_SPIN_Lock(SPIN_Lock_t *lock); +HAL_Status HAL_SPIN_TryLock(SPIN_Lock_t *lock); +HAL_Status HAL_SPIN_Unlock(SPIN_Lock_t *lock); + +#ifdef __cplusplus +} +#endif + +#endif //_DRIVER_CHIP_HAL_SPINLOCK_H_ \ No newline at end of file diff --git a/platform/mcu/xr871/include/driver/chip/hal_timer.h b/platform/mcu/xr871/include/driver/chip/hal_timer.h new file mode 100644 index 0000000000..6a5a362b8e --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_timer.h @@ -0,0 +1,187 @@ +/** + * @file hal_timer.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_TIMER_H_ +#define _DRIVER_CHIP_HAL_TIMER_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Timer ID definition + */ +typedef enum { + TIMER0_ID = 0, + TIMER1_ID = 1, + TIMER_NUM = 2 +} TIMER_ID; + +/** + * @brief TIMERx register block structure + */ +typedef struct { + __IO uint32_t CTRL; /* offset: 0x00, Timer control register */ + __IO uint32_t LOAD_VAL; /* offset: 0x04, Timer load/interval value register */ + __I uint32_t CUR_VAL; /* offset: 0x08, Timer current value register */ + uint32_t RESERVED[1]; /* offset: 0x0C */ +} TIMERx_T; + +/** + * @brief TIMER register block structure + */ +typedef struct { + __IO uint32_t IRQ_EN; /* offset: 0x00, Timer IRQ enable register */ + __IO uint32_t IRQ_STATUS; /* offset: 0x04, Timer IRQ status register */ + uint32_t RESERVED[2]; /* offset: 0x08 */ + TIMERx_T TIMERx[TIMER_NUM]; /* offset: 0x10, TIMERx register block */ +} TIMER_T; + +#define TIMER ((TIMER_T *)TIMER_BASE) /* address: 0x40040800 */ + +/* + * Bit field definition of TIMER->TIMERx[x].CTRL + */ + +/* timer mode */ +#define TIMER_MODE_SHIFT 7 /* R/W */ +#define TIMER_MODE_MASK (0x1U << TIMER_MODE_SHIFT) +typedef enum { + TIMER_MODE_REPEAT = (0U << TIMER_MODE_SHIFT), + TIMER_MODE_ONCE = (1U << TIMER_MODE_SHIFT) +} TIMER_Mode; + +/* Timer clock prescaler */ +#define TIMER_CLK_PRESCALER_SHIFT 4 /* R/W */ +#define TIMER_CLK_PRESCALER_MASK (0x7U << TIMER_CLK_PRESCALER_SHIFT) +typedef enum { + TIMER_CLK_PRESCALER_1 = (0U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_2 = (1U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_4 = (2U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_8 = (3U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_16 = (4U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_32 = (5U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_64 = (6U << TIMER_CLK_PRESCALER_SHIFT), + TIMER_CLK_PRESCALER_128 = (7U << TIMER_CLK_PRESCALER_SHIFT) +} TIMER_ClkPrescaler; + +/* Timer clock source */ +#define TIMER_CLK_SRC_SHIFT 2 /* R/W */ +#define TIMER_CLK_SRC_MASK (0x3U << TIMER_CLK_SRC_SHIFT) +typedef enum { + TIMER_CLK_SRC_LFCLK = (0U << TIMER_CLK_SRC_SHIFT), + TIMER_CLK_SRC_HFCLK = (1U << TIMER_CLK_SRC_SHIFT) +} TIMER_ClkSrc; + +#define TIMER_RELOAD_BIT HAL_BIT(1) + +#define TIMER_START_BIT HAL_BIT(0) + +/* + * TIMER->TIMERx[x].LOAD_VAL + */ + +/* + * TIMER->TIMERx[x].CUR_VAL + */ + +/******************************************************************************/ + +/** @brief Type define of Timer IRQ callback function */ +typedef void (*TIMER_IRQCallback)(void *arg); + +/** + * @brief Timer initialization parameters + * + * @note Timer counts down from period to zero + * - counting interval = period / (clkSrc / clkPrescaler) + */ +typedef struct { + uint32_t cfg; /* Created by HAL_TIMER_MakeInitCfg() */ + uint32_t period; /* Hardware reload value */ + + int8_t isEnableIRQ; /* Enable IRQ or not when TIMER counts down to zero */ + TIMER_IRQCallback callback; /* TIMER IRQ callback function */ + void *arg; /* Argument of TIMER IRQ callback function */ +} TIMER_InitParam; + +/** + * @brief Make configuration value for TIMER_InitParam::cfg + * @param[in] mode Timer working mode + * @param[in] clkSrc Timer clock source + * @param[in] clkPrescaler Timer clock prescaler + * @return configuration value for TIMER_InitParam::cfg + */ +__STATIC_INLINE uint32_t HAL_TIMER_MakeInitCfg(TIMER_Mode mode, + TIMER_ClkSrc clkSrc, + TIMER_ClkPrescaler clkPrescaler) +{ + return (mode | clkSrc | clkPrescaler); +} + +/** + * @brief Get the current counting value of the specified timer + * @param[in] timerID ID of the specified Timer + * @return Current counting value of the specified timer + */ +__STATIC_INLINE uint32_t HAL_TIMER_GetCurrentValue(TIMER_ID timerID) +{ + return TIMER->TIMERx[timerID].CUR_VAL; +} + +HAL_Status HAL_TIMER_Init(TIMER_ID timerID, const TIMER_InitParam *param); +HAL_Status HAL_TIMER_DeInit(TIMER_ID timerID); + +void HAL_TIMER_Start(TIMER_ID timerID); +void HAL_TIMER_Stop(TIMER_ID timerID); + +/** + * @brief Pause the timer's counting, the current value of timer is kept + * @param[in] timerID ID of the specified timer + * @return None + */ +__STATIC_INLINE void HAL_TIMER_Pause(TIMER_ID timerID) +{ + HAL_TIMER_Stop(timerID); +} + +void HAL_TIMER_Continue(TIMER_ID timerID); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_TIMER_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_uart.h b/platform/mcu/xr871/include/driver/chip/hal_uart.h new file mode 100644 index 0000000000..378c9df001 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_uart.h @@ -0,0 +1,290 @@ +/** + * @file hal_uart.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_UART_H_ +#define _DRIVER_CHIP_HAL_UART_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief UART ID definition + */ +typedef enum { + UART0_ID = 0, + UART1_ID = 1, + UART_NUM = 2, + UART_INVALID_ID = UART_NUM +} UART_ID; + +/** + * @brief UART register block structure + */ +typedef struct { + union { + __I uint32_t RX_BUF; /* offset: 0x00, UART receive buffer register, 8-bit valid */ + __O uint32_t TX_HOLD; /* offset: 0x00, UART transmit holding register, 8-bit valid */ + __IO uint32_t DIV_LOW; /* offset: 0x00, UART divisor latch low register, 8-bit valid */ + } RBR_THR_DLL; /* offset: 0x00, UART receive buffer/transmit holding/divisor latch low register */ + union { + __IO uint32_t DIV_HIGH; /* offset: 0x04, UART divisor latch high register, 8-bit valid */ + __IO uint32_t IRQ_EN; /* offset: 0x04, UART interrupt enable register */ + } DLH_IER; /* offset: 0x04, UART divisor latch high/IRQ enable register */ + union { + __I uint32_t IRQ_ID; /* offset: 0x08, UART interrupt identity register */ + __O uint32_t FIFO_CTRL; /* offset: 0x08, UART FIFO control register */ + } IIR_FCR; /* offset: 0x08, UART interrupt identity/FIFO control register */ + __IO uint32_t LINE_CTRL; /* offset: 0x0C, UART line control register */ + __IO uint32_t MODEM_CTRL; /* offset: 0x10, UART modem control register */ + __I uint32_t LINE_STATUS; /* offset: 0x14, UART line status register */ + __I uint32_t MODEM_STATUS; /* offset: 0x18, UART modem stauts register */ + __IO uint32_t SCRATCH; /* offset: 0x1C, UART scratch register */ + uint32_t RESERVED1[23]; + __I uint32_t STATUS; /* offset: 0x7C, UART status register */ + __I uint32_t TX_FIFO_LEVEL; /* offset: 0x80, UART transmit FIFO level register */ + __I uint32_t RX_FIFO_LEVEL; /* offset: 0x84, UART receive FIFO level register */ + uint32_t RESERVED2[7]; + __IO uint32_t HALT; /* offset: 0xA4, UART halt register */ + uint32_t RESERVED3[9]; + __IO uint32_t TX_DELAY; /* offset: 0xCC, UART TX delay register */ + uint32_t RESERVED4[1]; + __IO uint32_t BAUD_DECT_CTRL; /* offset: 0xD4, UART baudrate detection control register */ + __IO uint32_t BAUD_DECT_VAL_LOW; /* offset: 0xD8, UART baudrate detection counter low register */ + __IO uint32_t BAUD_DECT_VAL_HIGH; /* offset: 0xDC, UART baudrate detection counter high register */ +} UART_T; + +#define UART0 ((UART_T *)UART0_BASE) /* address: 0x40040C00 */ +#define UART1 ((UART_T *)UART1_BASE) /* address: 0x40041000 */ + +/* UARTx->RBR_THR_DLL.RX_BUF, R */ +#define UART_RX_DATA_MASK 0xFFU + +/* UARTx->RBR_THR_DLL.TX_HOLD, W */ +#define UART_TX_DATA_MASK 0xFFU + +/* UARTx->RBR_THR_DLL.DIV_LOW, R/W */ +#define UART_DIV_LOW_MASK 0xFFU + +/* UARTx->DLH_IER.DIV_HIGH, R/W */ +#define UART_DIV_HIGH_MASK 0xFFU + +/* UARTx->DLH_IER.IRQ_EN, R/W */ +#define UART_TX_FIFO_TRIG_MODE_EN_BIT HAL_BIT(7) +#define UART_RS485_IRQ_EN_BIT HAL_BIT(4) +#define UART_MODEM_STATUS_IRQ_EN_BIT HAL_BIT(3) +#define UART_LINE_STATUS_IRQ_EN_BIT HAL_BIT(2) +#define UART_TX_READY_IRQ_EN_BIT HAL_BIT(1) +#define UART_RX_READY_IRQ_EN_BIT HAL_BIT(0) + +/* UARTx->IIR_FCR.IRQ_ID, R */ +#define UART_IID_SHIFT 0 +#define UART_IID_MASK (0xFU << UART_IID_SHIFT) +typedef enum { + UART_IID_MODEM_STATUS = (0x0U << UART_IID_SHIFT), + UART_IID_NONE = (0x1U << UART_IID_SHIFT), + UART_IID_TX_READY = (0x2U << UART_IID_SHIFT), + UART_IID_RS485 = (0x3U << UART_IID_SHIFT), + UART_IID_RX_READY = (0x4U << UART_IID_SHIFT), + UART_IID_LINE_STATUS = (0x6U << UART_IID_SHIFT), + UART_IID_BUSY_DETECT = (0x7U << UART_IID_SHIFT), + UART_IID_CHAR_TIMEOUT = (0xCU << UART_IID_SHIFT), +} UART_IIDType; + +/* UARTx->IIR_FCR.FIFO_CTRL, W */ +#define UART_RX_FIFO_TRIG_LEVEL_SHIFT 6 +#define UART_RX_FIFO_TRIG_LEVEL_MASK (0x3 << UART_RX_FIFO_TRIG_LEVEL_SHIFT) +typedef enum { + UART_RX_FIFO_TRIG_LEVEL_ONE_CHAR = (0x0 << UART_RX_FIFO_TRIG_LEVEL_SHIFT), + UART_RX_FIFO_TRIG_LEVEL_QUARTER_FULL = (0x1 << UART_RX_FIFO_TRIG_LEVEL_SHIFT), + UART_RX_FIFO_TRIG_LEVEL_HALF_FULL = (0x2 << UART_RX_FIFO_TRIG_LEVEL_SHIFT), + UART_RX_FIFO_TRIG_LEVEL_NEARLY_FULL = (0x3 << UART_RX_FIFO_TRIG_LEVEL_SHIFT), +} UART_RxFifoTrigLevel; + +#define UART_TX_FIFO_TRIG_LEVEL_SHIFT 4 +#define UART_TX_FIFO_TRIG_LEVEL_MASK (0x3 << UART_TX_FIFO_TRIG_LEVEL_SHIFT) +typedef enum { + UART_TX_FIFO_TRIG_LEVEL_EMPTY = (0x0 << UART_TX_FIFO_TRIG_LEVEL_SHIFT), + UART_TX_FIFO_TRIG_LEVEL_TWO_CHAR = (0x1 << UART_TX_FIFO_TRIG_LEVEL_SHIFT), + UART_TX_FIFO_TRIG_LEVEL_QUARTER_FULL = (0x2 << UART_TX_FIFO_TRIG_LEVEL_SHIFT), + UART_TX_FIFO_TRIG_LEVEL_HALF_FULL = (0x3 << UART_TX_FIFO_TRIG_LEVEL_SHIFT), +} UART_TxFifoTrigLevel; + +#define UART_DMA_MODE_SHIFT 3 +#define UART_DMA_MODE_MASK (1U << UART_DMA_MODE_SHIFT) +typedef enum { + UART_DMA_MODE_0 = (0U << UART_DMA_MODE_SHIFT), + UART_DMA_MODE_1 = (1U << UART_DMA_MODE_SHIFT) +} UART_DMAMode; + +#define UART_TX_FIFO_RESET_BIT HAL_BIT(2) +#define UART_RX_FIFO_RESET_BIT HAL_BIT(1) +#define UART_FIFO_EN_BIT HAL_BIT(0) + +/* UARTx->LINE_CTRL, R/W */ +#define UART_DIV_ACCESS_BIT HAL_BIT(7) +#define UART_BREAK_CTRL_BIT HAL_BIT(6) + +#define UART_PARITY_EN_BIT HAL_BIT(3) +#define UART_PARITY_SEL_SHIFT 4 +#define UART_PARITY_SEL_MASK (0x3U << UART_PARITY_SEL_SHIFT) +#define UART_PARITY_MASK (UART_PARITY_EN_BIT | UART_PARITY_SEL_MASK) +typedef enum { + UART_PARITY_NONE = 0U, + UART_PARITY_ODD = UART_PARITY_EN_BIT | (0x0U << UART_PARITY_SEL_SHIFT), + UART_PARITY_EVEN = UART_PARITY_EN_BIT | (0x1U << UART_PARITY_SEL_SHIFT) +} UART_Parity; + +#define UART_STOP_BITS_SHIFT 2 +#define UART_STOP_BITS_MASK (0x1U << UART_STOP_BITS_SHIFT) +typedef enum { + UART_STOP_BITS_1 = (0x0U << UART_STOP_BITS_SHIFT), + UART_STOP_BITS_2 = (0x1U << UART_STOP_BITS_SHIFT) +} UART_StopBits; /* UART_STOP_BITS_2 is 1.5 stop bits for UART_DATA_BITS_5 */ + +#define UART_DATA_BITS_SHIFT 0 +#define UART_DATA_BITS_MASK (0x3U << UART_DATA_BITS_SHIFT) +typedef enum { + UART_DATA_BITS_5 = (0x0U << UART_DATA_BITS_SHIFT), + UART_DATA_BITS_6 = (0x1U << UART_DATA_BITS_SHIFT), + UART_DATA_BITS_7 = (0x2U << UART_DATA_BITS_SHIFT), + UART_DATA_BITS_8 = (0x3U << UART_DATA_BITS_SHIFT) +} UART_DataBits; + +/* UARTx->MODEM_CTRL, R/W */ +#define UART_WORK_MODE_SHIFT 6 +#define UART_WORK_MODE_MASK (0x3U << UART_WORK_MODE_SHIFT) +typedef enum { + UART_WORK_MODE_UART = (0x0U << UART_WORK_MODE_SHIFT), + UART_WORK_MODE_IRDA = (0x1U << UART_WORK_MODE_SHIFT), + UART_WORK_MODE_RS485 = (0x2U << UART_WORK_MODE_SHIFT), +} UART_WorkMode; + +#define UART_AUTO_FLOW_CTRL_EN_BIT HAL_BIT(5) +#define UART_LOOP_BACK_EN_BIT HAL_BIT(4) +#define UART_RTS_ASSERT_BIT HAL_BIT(1) +#define UART_DTR_ASSERT_BIT HAL_BIT(0) + +/* UARTx->LINE_STATUS, R */ +#define UART_FIFO_ERROR_BIT HAL_BIT(7) +#define UART_TX_EMPTY_BIT HAL_BIT(6) +#define UART_TX_HOLD_EMPTY_BIT HAL_BIT(5) +#define UART_BREAK_IRQ_BIT HAL_BIT(4) +#define UART_FRAME_ERROR_BIT HAL_BIT(3) +#define UART_PARITY_ERROR_BIT HAL_BIT(2) +#define UART_OVERRUN_ERROR_BIT HAL_BIT(1) +#define UART_RX_READY_BIT HAL_BIT(0) +#define UART_LINE_STATUS_MASK 0xFFU + +/* UARTx->MODEM_STATUS, R */ +#define UART_CTS_ASSERTED_BIT HAL_BIT(4) +#define UART_DELTA_CTS_BIT HAL_BIT(0) +#define UART_MODEM_STATUS_MASK 0xF3U + +/* UARTx->STATUS, R */ +#define UART_RX_FIFO_FULL_BIT HAL_BIT(4) +#define UART_RX_FIFO_NOT_EMPTY_BIT HAL_BIT(3) +#define UART_TX_FIFO_EMPTY_BIT HAL_BIT(2) +#define UART_TX_FIFO_NOT_FULL_BIT HAL_BIT(1) +#define UART_BUSY_BIT HAL_BIT(0) +#define UART_STATUS_MASK 0x1FU + +/* UARTx->TX_FIFO_LEVEL, R */ +#define UART_TX_FIFO_LEVEL_SHIFT 0 +#define UART_TX_FIFO_LEVEL_VMASK 0x7FU + +/* UARTx->RX_FIFO_LEVEL, R */ +#define UART_RX_FIFO_LEVEL_SHIFT 0 +#define UART_RX_FIFO_LEVEL_VMASK 0x7FU + +/* UARTx->HALT, R/W */ +#define UART_DMA_PTE_TX_BIT HAL_BIT(7) +#define UART_DMA_PTE_RX_BIT HAL_BIT(6) + +#define UART_CHANGE_UPDATE_BIT HAL_BIT(2) +#define UART_CHANGE_AT_BUSY_BIT HAL_BIT(1) + +#define UART_HALT_TX_EN_BIT HAL_BIT(0) + +/******************************************************************************/ + +/** + * @brief UART initialization parameters + */ +typedef struct { + uint32_t baudRate; /* Baud rate, in bps */ + UART_Parity parity; /* Parity */ + UART_StopBits stopBits; /* Stop bits */ + UART_DataBits dataBits; /* Data bits */ + int8_t isAutoHwFlowCtrl; /* Enable auto hardware flow control or not */ +} UART_InitParam; + +/** @brief Type define of UART receive ready callback function */ +typedef void (*UART_RxReadyCallback) (void *arg); + +UART_T *HAL_UART_GetInstance(UART_ID uartID); +int HAL_UART_IsTxReady(UART_T *uart); +int HAL_UART_IsTxEmpty(UART_T *uart); +int HAL_UART_IsRxReady(UART_T *uart); +uint8_t HAL_UART_GetRxData(UART_T *uart); +void HAL_UART_PutTxData(UART_T *uart, uint8_t data); + +HAL_Status HAL_UART_Init(UART_ID uartID, const UART_InitParam *param); +HAL_Status HAL_UART_DeInit(UART_ID uartID); + +int32_t HAL_UART_Transmit_IT(UART_ID uartID, uint8_t *buf, int32_t size); +int32_t HAL_UART_Receive_IT(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec); + +HAL_Status HAL_UART_EnableRxCallback(UART_ID uartID, UART_RxReadyCallback cb, void *arg); +HAL_Status HAL_UART_DisableRxCallback(UART_ID uartID); + +HAL_Status HAL_UART_EnableTxDMA(UART_ID uartID); +HAL_Status HAL_UART_EnableRxDMA(UART_ID uartID); +HAL_Status HAL_UART_DisableTxDMA(UART_ID uartID); +HAL_Status HAL_UART_DisableRxDMA(UART_ID uartID); +int32_t HAL_UART_Transmit_DMA(UART_ID uartID, uint8_t *buf, int32_t size); +int32_t HAL_UART_Receive_DMA(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec); + +int32_t HAL_UART_Transmit_Poll(UART_ID uartID, uint8_t *buf, int32_t size); +int32_t HAL_UART_Receive_Poll(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec); + +void HAL_UART_SetBreakCmd(UART_ID uartID, int8_t isSet); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_UART_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_util.h b/platform/mcu/xr871/include/driver/chip/hal_util.h new file mode 100644 index 0000000000..feb5cd537b --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_util.h @@ -0,0 +1,50 @@ +/** + * @file hal_util.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_UTIL_H_ +#define _DRIVER_CHIP_HAL_UTIL_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void HAL_UDelay(uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_UTIL_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_wakeup.h b/platform/mcu/xr871/include/driver/chip/hal_wakeup.h new file mode 100644 index 0000000000..ddd6d85da7 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_wakeup.h @@ -0,0 +1,155 @@ +/** + * @file hal_wakeup.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_WAKEUP_H_ +#define _DRIVER_CHIP_HAL_WAKEUP_H_ + +#include "sys/io.h" + +#include "driver/chip/hal_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ignore the second set if the second set time is longer than the + * first time. + */ +//#define WAKEUP_TIMER_CHECK_TIME 1 + +/** @brief the minimum time of wakeup timer support, based on ms */ +#define WAKEUP_TIMER_MIN_TIME (10) + +/** + * @brief wakeup events. + * @note WKIO0~9 should define from BIT(0) to BIT(9). + */ +#ifdef __CONFIG_ARCH_APP_CORE +#define PM_WAKEUP_SRC_WKIO0 BIT(0 ) /* 0x00000001 */ +#define PM_WAKEUP_SRC_WKIO1 BIT(1 ) /* 0x00000002 */ +#define PM_WAKEUP_SRC_WKIO2 BIT(2 ) /* 0x00000004 */ +#define PM_WAKEUP_SRC_WKIO3 BIT(3 ) /* 0x00000008 */ +#define PM_WAKEUP_SRC_WKIO4 BIT(4 ) /* 0x00000010 */ +#define PM_WAKEUP_SRC_WKIO5 BIT(5 ) /* 0x00000020 */ +#define PM_WAKEUP_SRC_WKIO6 BIT(6 ) /* 0x00000040 */ +#define PM_WAKEUP_SRC_WKIO7 BIT(7 ) /* 0x00000080 */ +#define PM_WAKEUP_SRC_WKIO8 BIT(8 ) /* 0x00000100 */ +#define PM_WAKEUP_SRC_WKIO9 BIT(9 ) /* 0x00000200 */ +#endif +#define PM_WAKEUP_SRC_WKTIMER BIT(10) /* 0x00000400 */ +#define PM_WAKEUP_SRC_WKSEV BIT(11) /* 0x00000800 */ +#define PM_WAKEUP_SRC_NETCPU (PM_WAKEUP_SRC_WKSEV) /* 0x00000800 */ +#define PM_WAKEUP_SRC_DEVICES BIT(12) /* 0x00001000 */ + +/** + * @brief Get last wakeup event. + * retval Events defined in PM_WAKEUP_SRC_XX. + */ +extern uint32_t HAL_Wakeup_GetEvent(void); + +#ifdef __CONFIG_ARCH_APP_CORE +/** + * @brief Set IO hold. + * @note Set all IO hold before poweroff to prevent IO output low level voltage. + * @param hold_io: + * @arg hold_io-> IO hold mask. + * retval 0 if success or other if failed. + */ +extern int32_t HAL_Wakeup_SetIOHold(uint32_t hold_io); + +/** + * @brief Set wakeup IO enable and mode. + * @note This won't change IO config immediately, the enabled IO will be setted + * to input and wakeup mode before system enter lowpower mode. And the IO + * will be disabled after wakeup. So reinit IO if you want this IO used + * as other function. The IO will used as wakeup IO until be cleaned. + * @param pn: + * @arg pn-> 0~9. + * @param mode: + * @arg mode-> 0:negative edge, 1:positive edge. + * retval None. + */ +extern void HAL_Wakeup_SetIO(uint32_t pn, uint32_t mode); + +/** + * @brief Clear wakeup IO enable. + * @param pn: + * @arg pn-> 0~9. + * retval None. + */ +extern void HAL_Wakeup_ClrIO(uint32_t pn); +#endif + +/** + * @brief Set wakeup timer. + * @note This will config wakeup timer counting immediately, and this will be + * used only once. The wakeup timer will be disabled when time out no + * matter it wakeup system or not. Wakeup timer should be setted + * everytime if you want wake up system from suspend. + * @param count_32k: + * @arg count_32k-> counter to wakeup system based on 32k counter. from + * WAKEUP_TIMER_MIN_TIME*32(WAKEUP_TIMER_MIN_TIME mS) to 134217727(4194.303S). + * retval 0 if success or other if failed. + */ +extern int32_t HAL_Wakeup_SetTimer(uint32_t count_32k); + +/** + * @brief Set wakeup timer. + * @param ms: + * @arg ms-> counter to wakeup system based on ms. + * retval 0 if success or other if failed. + */ +#define HAL_Wakeup_SetTimer_mS(ms) HAL_Wakeup_SetTimer(ms*32) + +/** + * @brief Config and enable wakeup io. + * retval 0 if success or other if failed. + */ +extern int32_t HAL_Wakeup_SetSrc(void); + +/** @brief Disable wakeup io. */ +extern void HAL_Wakeup_ClrSrc(void); + +/** @brief Init wakeup IO and Timer as disable mode. */ +extern void HAL_Wakeup_Init(void); + +/** @brief Deinit wakeup IO and Timer. */ +extern void HAL_Wakeup_DeInit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_WAKEUP_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_wdg.h b/platform/mcu/xr871/include/driver/chip/hal_wdg.h new file mode 100644 index 0000000000..81faf3f40a --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_wdg.h @@ -0,0 +1,127 @@ +/** + * @file hal_wdg.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_WDG_H_ +#define _DRIVER_CHIP_HAL_WDG_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Watchdog register block structure + */ +typedef struct { + __IO uint32_t IRQ_EN; /* offset: 0xA0, Watchdog IRQ Enable Register */ + __IO uint32_t IRQ_STATUS; /* offset: 0xA4, Watchdog IRQ Status Register */ + uint32_t RESERVED0[2]; + __IO uint32_t CTRL; /* offset: 0xB0, Watchdog Control Register */ + __IO uint32_t CFG; /* offset: 0xB4, Watchdog Configuration Register */ + __IO uint32_t MODE; /* offset: 0xB8, Watchdog Mode Register */ + __IO uint32_t RESET_CTRL; /* offset: 0xBC, Watchdog Output Control Register */ +} WDG_T; + +#define WDG ((WDG_T *)(TIMER_BASE + 0xA0)) /* address: 0x400408A0 */ + +/* WDG->IRQ_EN */ +#define WDG_IRQ_EN_BIT HAL_BIT(0) + +/* WDG->IRQ_STATUS */ +#define WDG_IRQ_PENDING_BIT HAL_BIT(0) + +/* WDG->CFG */ +#define WDG_EVT_TYPE_SHIFT 0 +#define WDG_EVT_TYPE_MASK (0x3U << WDG_EVT_TYPE_SHIFT) +typedef enum { + WDG_EVT_RESET = (1U << WDG_EVT_TYPE_SHIFT), /* reset system */ + WDG_EVT_INTERRUPT = (2U << WDG_EVT_TYPE_SHIFT) /* trigger interrupt */ +} WDG_EventType; + +/* WDG->MODE */ +#define WDG_TIMEOUT_SHIFT 4 +#define WDG_TIMEOUT_MASK (0xF << WDG_TIMEOUT_SHIFT) +typedef enum { + WDG_TIMEOUT_500MS = (0U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_1SEC = (1U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_2SEC = (2U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_3SEC = (3U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_4SEC = (4U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_5SEC = (5U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_6SEC = (6U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_8SEC = (7U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_10SEC = (8U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_12SEC = (9U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_14SEC = (10U << WDG_TIMEOUT_SHIFT), + WDG_TIMEOUT_16SEC = (11U << WDG_TIMEOUT_SHIFT) +} WDG_Timeout; + +#define WDG_EN_BIT HAL_BIT(0) + +/* WDG->RESET_CTRL */ +#define WDG_RESET_CYCLE_SHIFT 0 +#define WDG_RESET_CYCLE_MASK (0x1F << WDG_RESET_CYCLE_SHIFT) +#define WDG_DEFAULT_RESET_CYCLE 0xA + +/******************************************************************************/ + +/** @brief Type define of watchdog IRQ callback function */ +typedef void (*WDG_IRQCallback) (void *arg); + +/** + * @brief Watchdog initialization parameters + */ +typedef struct { + WDG_EventType event; /* Watchdog trigger event type */ + WDG_Timeout timeout; /* Interval to trigger event after last feed */ + uint8_t resetCycle; /* Reset signal cycles, for WDG_EVT_RESET only. + Set to WDG_DEFAULT_RESET_CYCLE generally, its range is [0, 31] */ + WDG_IRQCallback callback; /* Watchdog IRQ callback fucntion, for WDG_EVT_INTERRUPT only */ + void *arg; /* Argument of Watchdog IRQ callback fucntion, for WDG_EVT_INTERRUPT only */ +} WDG_InitParam; + +HAL_Status HAL_WDG_Init(const WDG_InitParam *param); +HAL_Status HAL_WDG_DeInit(void); + +void HAL_WDG_Feed(void); +void HAL_WDG_Start(void); +void HAL_WDG_Stop(void); +void HAL_WDG_Reboot(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_WDG_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/hal_xip.h b/platform/mcu/xr871/include/driver/chip/hal_xip.h new file mode 100644 index 0000000000..3cbdb43a52 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/hal_xip.h @@ -0,0 +1,60 @@ +/** + * @file hal_xip.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HAL_XIP_H_ +#define HAL_XIP_H_ + +#include "driver/chip/hal_flashctrl.h" +#include "driver/chip/flashchip/flash_chip.h" + +//typedef struct XipDriverBase XipDriverBase; + +struct XipDriverBase +{ + int (*setCmd)(struct XipDriverBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); + int (*setDelay)(struct XipDriverBase *base, Flashc_Delay *delay); + int (*setAddr)(struct XipDriverBase *base, uint32_t addr); + int (*setContinue)(struct XipDriverBase *base, uint32_t continueMode, void *arg); + + XIP_Config mCfg; + uint32_t flash; + FlashDev *dev; +}; + + +HAL_Status HAL_Xip_Init(uint32_t flash, uint32_t xaddr); + +HAL_Status HAL_Xip_Deinit(void); + +#endif /* HAL_XIP_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/ir_nec.h b/platform/mcu/xr871/include/driver/chip/ir_nec.h new file mode 100644 index 0000000000..58423733e0 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/ir_nec.h @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_IR_NEC_H_ +#define _DRIVER_CHIP_IR_NEC_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * NEC protocal + * 8 bits addr, 8 bits cmd code. + * send addr and cmd code twice every time to improve reliable. + * pluse modulation time is long or short. + * 38KHz carrier frequency. + * bit time is 1.12ms or 2.25ms. + * send time is 68ms, send cycle is 110ms. + * ------------------------------------------------------------------------------ + * | Logical '1' | Logical '0' | Logical 'x' | + * ------------------------------------------------------------------------------ + * | 1(pulses) | 0 | 1(pulses) | 0 | 1(pulses) | - | + * ------------------------------------------------------------------------------ + * | 560uS | 1690uS | 560uS | 560uS | 560uS | | + * | 2.25mS | 1.12mS | | | + * ------------------------------------------------------------------------------ + * 1(pulses): f=38KHz, T=26.3us, N=560/26.3=21 + * + * example: send 0x59(10011010 LSB first) addr, 0x16(01101000 LSB first) cmd code. + * --------------------------------------------------------------------------------------------------------------------- + * | S1 | S0 |L1|L0|L0|L1|L1|L0|L1|L0|L0|L1|L1|L0|L0|L1|L0|L1|L0|L1|L1|L0|L1|L0|L0|L0|L1|L0|L0|L1|L0|L1|L1|L1| E1 | + * | 9mS |4.5mS|LSB MSB|LSB MSB|LSB MSB|LSB MSB|560uS| + * | Start | 0x59 Address | ~0x59 Address | 0x16 Command | ~0x16 Command | End | + * --------------------------------------------------------------------------------------------------------------------- + * the S0 of repeat code is 2.25mS. + */ + +#if defined (IR_CLK_32K_USED) +#define IRRX_32K_ACTIVE_T (0) /* ActionTreshold, Active Threshold */ +#define IRRX_32K_ACTIVE_T_C (0) /* SampleClock, Active Threshold Control, same with IRRX_ATHC_CLOCKUNIT_1 */ +#define IRRX_32K_L1_MIN (112) /* 112*30.5 = ~3.4ms, Lead1(9.0ms) Lead1R(4.5ms) > IR_L1_MIN */ +#define IRRX_32K_L0_MIN (56) /* 56*30.5 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > IR_L0_MIN */ +#define IRRX_32K_PMAX (36) /* 36*30.5 = ~1098us ~= 549*2, Pluse < IRRX_PMAX */ +#define IRRX_32K_DMID (36) /* 36*30.5 = ~1098us ~= 549*2, D1 > IRRX_DMID, D0 =< IRRX_DMID */ +#define IRRX_32K_DMAX (74) /* 74*30.5 = ~2257us ~= 564*4, D < IRRX_DMAX */ + +#define IRTX_32K_TS_US (61) /* Ts frome IRTX_SAMPLE */ + /* IRTX_9MS_NUM 0x94, 148*Ts=9028uS */ + /* IRTX_9MS_NUM1 127*Ts=7747uS */ + /* IRTX_9MS_NUM2 21*Ts=1281uS */ + /* IRTX_4P5MS_NUM 0x4A, 74*Ts=4514uS */ + /* IRTX_560US_NUM 0x09, 9*Ts=549uS */ + /* IRTX_1680US_NUM 0x1C, 28*Ts=1708uS */ +#define IRTX_32K_9MS_NUM (9000/IRTX_32K_TS_US) +#define IRTX_32K_9MS_NUM1 (0x7f) +#define IRTX_32K_9MS_NUM2 (IRTX_32K_9MS_NUM-IRTX_32K_9MS_NUM1) +#define IRTX_32K_4P5MS_NUM (4500/IRTX_32K_TS_US) +#define IRTX_32K_4P5MS_NUM1 (IRTX_32K_4P5MS_NUM) +#define IRTX_32K_2P25MS_NUM (IRTX_32K_4P5MS_NUM/2) +#define IRTX_32K_560US_NUM (560/IRTX_32K_TS_US) +#define IRTX_32K_1680US_NUM (1680/IRTX_32K_TS_US) + +#define IRTX_32K_NEC_CYCLE_MS (110) +#define IRTX_32K_NEC_IDC_VALUE ((IRTX_32K_NEC_CYCLE_MS*1000)/128/IRTX_32K_TS_US + 1) +#else +#define IRRX_26M_ACTIVE_T (0) /* ActionTreshold, Active Threshold */ +#define IRRX_26M_ACTIVE_T_C (1) /* SampleClock, Active Threshold Control, same with IRRX_ATHC_CLOCKUNIT_128 */ +#define IRRX_26M_L1_MIN (80) /* 80*39.4 = ~3.2ms, Lead1(9.0ms) Lead1R(4.5ms) > IR_L1_MIN */ +#define IRRX_26M_L0_MIN (41) /* 41*39.4 = ~1.6ms, Lead0(4.5ms) Lead0R(2.25ms)> IR_L0_MIN */ +#define IRRX_26M_PMAX (27) /* 27*39.4 = ~1064us ~= 532*2, Pluse < IRRX_PMAX */ +#define IRRX_26M_DMID (27) /* 27*39.4 = ~1064us ~= 532*2, D1 > IRRX_DMID, D0 =< IRRX_DMID */ +#define IRRX_26M_DMAX (55) /* 55*39.4 = ~2167us ~= 542*4, D < IRRX_DMAX */ + +#define IRTX_26M_TS_US (39) /* Ts frome IRTX_SAMPLE */ + /* IRTX_9MS_NUM 0xE4, 228*Ts=8994.6uS */ + /* IRTX_9MS_NUM1 127*Ts=5003.8uS */ + /* IRTX_9MS_NUM2 101*Ts=3979.4uS */ + /* IRTX_4P5MS_NUM 0x72, 114*Ts=4491.6uS */ + /* IRTX_560US_NUM 0x0E, 14*Ts=551.6uS */ + /* IRTX_1680US_NUM 0x2B, 43*Ts=1694.2uS */ +#define IRTX_26M_9MS_NUM (9000/IRTX_26M_TS_US) +#define IRTX_26M_9MS_NUM1 (0x7f) +#define IRTX_26M_9MS_NUM2 (IRTX_26M_9MS_NUM-IRTX_26M_9MS_NUM1) +#define IRTX_26M_4P5MS_NUM (4500/IRTX_26M_TS_US) +#define IRTX_26M_4P5MS_NUM1 (IRTX_26M_4P5MS_NUM) +#define IRTX_26M_2P25MS_NUM (IRTX_26M_4P5MS_NUM/2) +#define IRTX_26M_560US_NUM (560/IRTX_26M_TS_US) +#define IRTX_26M_1680US_NUM (1680/IRTX_26M_TS_US) + +#define IRTX_26M_NEC_CYCLE_MS (110) +#define IRTX_26M_NEC_IDC_VALUE ((IRTX_26M_NEC_CYCLE_MS*1000)/128/IRTX_26M_TS_US + 1) + +#define IRRX_24M_ACTIVE_T (0) /* ActionTreshold, Active Threshold */ +#define IRRX_24M_ACTIVE_T_C (1) /* SampleClock, Active Threshold Control, same with IRRX_ATHC_CLOCKUNIT_128 */ +#define IRRX_24M_L1_MIN (70) /* 70*42.7 = ~3.0ms, Lead1(9.0ms) Lead1R(4.5ms) > IR_L1_MIN */ +#define IRRX_24M_L0_MIN (40) /* 40*42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms)> IR_L0_MIN */ +#define IRRX_24M_PMAX (26) /* 26*42.7 = ~1109us ~= 561*2, Pluse < IRRX_PMAX */ +#define IRRX_24M_DMID (26) /* 26*42.7 = ~1109us ~= 561*2, D1 > IRRX_DMID, D0 =< IRRX_DMID */ +#define IRRX_24M_DMAX (53) /* 53*42.7 = ~2263us ~= 561*4, D < IRRX_DMAX */ + +#define IRTX_24M_TS_US (43) /* Ts frome IRTX_SAMPLE */ + /* IRTX_9MS_NUM 0xD1, 209*Ts=8924.3uS */ + /* IRTX_9MS_NUM1 127*Ts=5422.9uS */ + /* IRTX_9MS_NUM2 81*Ts=3458.7uS */ + /* IRTX_4P5MS_NUM 0x69, 105*Ts=4483.5uS */ + /* IRTX_560US_NUM 0x0D, 13*Ts=555.1uS */ + /* IRTX_1680US_NUM 0x27, 39*Ts=1665.3uS */ + +#define IRTX_24M_9MS_NUM (9000/IRTX_24M_TS_US) +#define IRTX_24M_9MS_NUM1 (0x7f) +#define IRTX_24M_9MS_NUM2 (IRTX_24M_9MS_NUM-IRTX_24M_9MS_NUM1) +#define IRTX_24M_4P5MS_NUM (4500/IRTX_24M_TS_US) +#define IRTX_24M_4P5MS_NUM1 (IRTX_24M_4P5MS_NUM) +#define IRTX_24M_2P25MS_NUM (IRTX_24M_4P5MS_NUM/2) +#define IRTX_24M_560US_NUM (560/IRTX_24M_TS_US) +#define IRTX_24M_1680US_NUM (1680/IRTX_24M_TS_US) + +#define IRTX_24M_NEC_CYCLE_MS (110) +#define IRTX_24M_NEC_IDC_VALUE ((IRTX_24M_NEC_CYCLE_MS*1000)/128/IRTX_24M_TS_US + 1) +#endif + +/** + * @brief Format code by NEC protocal. + * @param add: + * @arg add->[in] The address. + * @param key: + * @arg key->[in] The key. + * @retval Formated code. + */ +static __inline uint32_t IR_NEC_CODE(uint8_t add, uint8_t key) +{ + uint32_t code = (add << 24) | (((~add) << 16) & 0x00ff0000); + + code |= (key << 8) | ((~key) & 0x00ff); + + return code; +} + +/** + * @brief Check code valied. + * @param code: + * @arg code->[in] The code wanted be checked. + * @retval 1 if valid or 0 if unvalid. + */ +extern int32_t IRRX_NECCode_Valid(uint32_t code); + +/** + * @brief DePacket code by NEC protocal. + * @param buf: + * @arg buf->[in]Raw code buffer. + * @param dcnt: + * @arg dcnt->[in] Num of Raw code. + * @retval DePacket code if success or 0xffffffff if depacket failed. + */ +extern uint32_t IRRX_NECPacket_DeCode(uint8_t *buf, uint32_t dcnt); + +/** + * @brief Packet code by NEC protocal. + * @param txBuff: + * @arg txBuff->[out] Raw code will put in. + * @param ir_tx_code: + * @arg ir_tx_code->[in] The code will be Packeted. + * @retval Raw code num. + */ +extern uint32_t IRTX_NECPacket_Code(uint8_t *txBuff, uint32_t ir_tx_code); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_IR_NEC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/sdmmc/card.h b/platform/mcu/xr871/include/driver/chip/sdmmc/card.h new file mode 100644 index 0000000000..fbc3c3e1ca --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/sdmmc/card.h @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_SDMMC_CARD_H_ +#define _DRIVER_CHIP_HAL_SDMMC_CARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONFIG_USE_SD + +struct mmc_ocr { + union { + uint32_t vol_window : 24, + to_1v8_acpt : 1, + : 5, + high_capacity : 1, + : 1; + uint32_t ocr; + }; +}; + +struct mmc_cid { + uint16_t oemid; + uint8_t manfid; + uint32_t serial; + uint16_t year; + uint8_t month; + uint8_t hwrev; + uint8_t fwrev; + uint8_t prod_name[6]; +}; + +struct mmc_csd { + uint8_t csd_ver; + uint8_t read_blk_len; + uint8_t c_size_mult; + uint32_t max_dtr; + uint16_t c_size; + uint16_t cmdclass; + uint32_t capacity; +}; + +struct sd_scr { + uint8_t sda_vsn; + uint8_t sda_spec3; + uint8_t sda_spec4; + uint8_t sda_spec5; + uint8_t bus_widths; + uint8_t security_sup; +#define SD_SCR_BUS_WIDTH_1 (1<<0) +#define SD_SCR_BUS_WIDTH_4 (1<<2) + uint8_t cmds; +#define SD_SCR_CMD20_SUPPORT (1<<0) +#define SD_SCR_CMD23_SUPPORT (1<<1) +}; + +struct sd_switch_caps { + uint32_t hs_max_dtr; + uint32_t uhs_max_dtr; +#define HIGH_SPEED_MAX_DTR 50000000 +#define UHS_SDR104_MAX_DTR 208000000 +#define UHS_SDR50_MAX_DTR 100000000 +#define UHS_DDR50_MAX_DTR 50000000 +#define UHS_SDR25_MAX_DTR UHS_DDR50_MAX_DTR +#define UHS_SDR12_MAX_DTR 25000000 + uint32_t sd3_bus_mode; +#define UHS_SDR12_BUS_SPEED 0 +#define HIGH_SPEED_BUS_SPEED 1 +#define UHS_SDR25_BUS_SPEED 1 +#define UHS_SDR50_BUS_SPEED 2 +#define UHS_SDR104_BUS_SPEED 3 +#define UHS_DDR50_BUS_SPEED 4 + +#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED) +#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED) +#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED) +#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED) +#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED) +#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED) + uint32_t sd3_drv_type; +#define SD_DRIVER_TYPE_B 0x01 +#define SD_DRIVER_TYPE_A 0x02 +#define SD_DRIVER_TYPE_C 0x04 +#define SD_DRIVER_TYPE_D 0x08 + uint32_t sd3_curr_limit; +#define SD_SET_CURRENT_LIMIT_200 0 +#define SD_SET_CURRENT_LIMIT_400 1 +#define SD_SET_CURRENT_LIMIT_600 2 +#define SD_SET_CURRENT_LIMIT_800 3 + +#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200) +#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400) +#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600) +#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800) +}; + +struct mmc_ext_csd { + uint8_t version; + uint8_t card_type; + uint8_t csd_struc; + uint8_t hs_timing; + uint8_t bus_width; + uint8_t part_config; + uint8_t boot_bus_cond; +}; + +struct mmc_host; + +#define SDIO_MAX_FUNCS 7 + +struct mmc_card { + /* register info. */ + struct mmc_cid cid; + struct mmc_csd csd; + struct sd_scr scr; + struct mmc_ext_csd extcsd; + struct sd_switch_caps sw_caps; /* switch (CMD6) caps */ + /* card information */ + uint32_t type; /* card type */ +#define MMC_TYPE_MMC 0 /* MMC card */ +#define MMC_TYPE_SD 1 /* SD card */ +#define MMC_TYPE_SDIO 2 /* SDIO card */ +#define MMC_TYPE_SD_COMBO 3 /* SD combo (IO+mem) card */ + + uint32_t sd_bus_speed; /* Bus Speed Mode set for the card */ + uint32_t state; /* (our) card state */ +#define MMC_STATE_PRESENT (1 << 0) /* present */ +#define MMC_STATE_READONLY (1 << 1) /* card is read-only */ +#define MMC_STATE_HIGHSPEED (1 << 2) /* card is in high speed mode */ +#define MMC_STATE_BLOCKADDR (1 << 3) /* card uses block-addressing */ +#define MMC_STATE_HIGHSPEED_DDR (1 << 4) /* card is in high speed mode */ + +#define MMC_STATE_ULTRAHIGHSPEED (1<<5) /* card is in ultra high speed mode */ +#define MMC_CARD_SDXC (1<<6) /* card is SDXC */ +#define MMC_CARD_REMOVED (1<<7) /* card has been removed */ +#define MMC_STATE_HIGHSPEED_200 (1<<8) /* card is in HS200 mode */ +#define MMC_STATE_SLEEP (1<<9) /* card is in sleep state */ + + uint8_t bus_width; + uint8_t speed_class; + uint32_t cidno[4]; + + uint32_t rca; /* relative card address of device */ + struct mmc_ocr ocr; + struct mmc_host *host; /* the host this device belongs to */ +}; + +#define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC) +#define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD) +#define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO) + +#define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) +#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) +#define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED) +#define mmc_card_hs200(c) ((c)->state & MMC_STATE_HIGHSPEED_200) +#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) +#define mmc_card_ddr_mode(c) ((c)->state & MMC_STATE_HIGHSPEED_DDR) +#define mmc_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED) +#define mmc_sd_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED) +#define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC) +#define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED)) +#define mmc_card_is_sleep(c) ((c)->state & MMC_STATE_SLEEP) + +#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) +#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) +#define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED) +#define mmc_card_set_hs200(c) ((c)->state |= MMC_STATE_HIGHSPEED_200) +#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) +#define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR) +#define mmc_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED) +#define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED) +#define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC) +#define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED) +#define mmc_card_set_sleep(c) ((c)->state |= MMC_STATE_SLEEP) + +#define mmc_card_clr_sleep(c) ((c)->state &= ~MMC_STATE_SLEEP) + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_SDMMC_CARD_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/sdmmc/hal_sdhost.h b/platform/mcu/xr871/include/driver/chip/sdmmc/hal_sdhost.h new file mode 100644 index 0000000000..48cda90700 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/sdmmc/hal_sdhost.h @@ -0,0 +1,114 @@ +/** + * @file hal_sdhost.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_SDMMC_SDHOST_H_ +#define _DRIVER_CHIP_HAL_SDMMC_SDHOST_H_ + +#include "driver/chip/hal_def.h" +#ifdef __CONFIG_ARCH_APP_CORE +#include "driver/chip/hal_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @bried Detect card by gpio irq or D3. */ +//#define CONFIG_DETECT_CARD 1 + +typedef enum +{ + SDCGPIO_BAS = 0, + SDCGPIO_DET = 1, +} HAL_SDCGPIOType; + +typedef struct { + uint8_t data_bits; + int8_t has_detect_gpio; + GPIO_Port detect_port; + GPIO_Pin detect_pin; +} HAL_SDCGPIOCfg; + +/** @bried Detect card callback if used CONFIG_DETECT_CARD. */ +typedef void (*card_detect_cb)(uint32_t present); + +/** @bried SDC Init Structure definition. */ +typedef struct { +#ifdef CONFIG_DETECT_CARD + uint32_t cd_mode; +/* NOTE: The specification advise that CARD_DETECT_BY_D3 is not a preferred + * mechanism for card detection. Moreover it won't work with MMC cards. + * And, this won't work with external pull-up resistors on the card interface. + * The preferred card detection mechanism is a mechanical switch on the card connector. +*/ +#define CARD_DETECT_BY_GPIO_IRQ (2) /* mmc detected by gpio irq */ +#define CARD_ALWAYS_PRESENT (3) /* mmc always present, without detect pin */ +#define CARD_DETECT_BY_FS (4) /* mmc insert/remove by fs */ +#define CARD_DETECT_BY_D3 (5) /* mmc detected by data3 */ + + card_detect_cb cd_cb; /* NOTE: should delay 500ms before rescan card to wait Voltage stable */ +#endif +} SDC_InitTypeDef; + +/** + * @brief Initializes the SDC peripheral. + * @param sdc_id: + * @arg sdc_id->SDC ID. + * @param param: + * @arg param->[in] The configuration information. + * @retval SDC handler. + */ +extern struct mmc_host *HAL_SDC_Init(uint32_t sdc_id, SDC_InitTypeDef *param); +#else +/** + * @brief Initializes the SDC peripheral. + * @param sdc_id: + * @arg sdc_id->SDC ID. + * @retval SDC handler. + */ +extern struct mmc_host *HAL_SDC_Init(uint32_t sdc_id); +#endif + +/** + * @brief DeInitializes the SDC peripheral. + * @param sdc_id: + * @arg sdc_id-> SDC ID. + * @retval None. + */ +extern int32_t HAL_SDC_Deinit(uint32_t sdc_id); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_SDMMC_SDHOST_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/sdmmc/sdmmc.h b/platform/mcu/xr871/include/driver/chip/sdmmc/sdmmc.h new file mode 100644 index 0000000000..7bd78d4ef2 --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/sdmmc/sdmmc.h @@ -0,0 +1,486 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_SDMMC_SDMMC_H_ +#define _DRIVER_CHIP_HAL_SDMMC_SDMMC_H_ + +#include "driver/chip/sdmmc/card.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SD_EXCLUSIVE_HOST + +/* SD commands type argument response */ + /* class 0 */ +/* This is basically the same command as for MMC with some quirks. */ +#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6, ask the card to publish a new relative address */ +#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7, sends Sd memory card interface condition, for sd 2.0 */ +#define SD_SWITCH_VOLTAGE 11 /* ac R1, switch to 1.8V bus signaling level */ + + /* class 10 */ +#define SD_SWITCH 6 /* adtc [31:0] See below R1, checks swithcable function(mode 0),And swtich card function(mode 1), for sd 1.x */ + + /* class 5 */ +#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */ +#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */ + + /* Application commands */ +#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ +#define SD_APP_SD_STATUS 13 /* adtc R1 */ +#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ +#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ +#define SD_APP_SEND_SCR 51 /* adtc R1 */ + +/* OCR bit definitions */ +#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */ +#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ +#define SD_OCR_XPC (1 << 28) /* SDXC power control */ +#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */ + +/* + * SD_SWITCH argument format: + * + * [31] Check (0) or switch (1) + * [30:24] Reserved (0) + * [23:20] Function group 6 + * [19:16] Function group 5 + * [15:12] Function group 4 + * [11:8] Function group 3 + * [7:4] Function group 2 + * [3:0] Function group 1 + */ + +/* + * SD_SEND_IF_COND argument format: + * + * [31:12] Reserved (0) + * [11:8] Host Voltage Supply Flags + * [7:0] Check Pattern (0xAA) + */ + +/* + * SCR field definitions + */ +#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ +#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ +#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */ + +/* + * SD bus widths + */ +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 + +/* + * SD_SWITCH mode + */ +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SET 1 + +/* + * SD_SWITCH function groups + */ +#define SD_SWITCH_GRP_ACCESS 0 + +/* + * SD_SWITCH access modes + */ +#define SD_SWITCH_ACCESS_DEF 0 +#define SD_SWITCH_ACCESS_HS 1 + +/*command index*/ +/*basic commands*/ +#define MMC_GO_IDLE_STATE 0 /* bc,rest all cards to idle state */ +#define MMC_ALL_SEND_CID 2 /* bcr R2, asks any card to send CID numbers */ +#define MMC_SET_RELATIVE_ADDR 3 /* bcr,ask the card to publish a new relative address,R6 */ +#define MMC_SET_DSR 4 /* bc,program the DSR of all cards,for sd 2.0 */ +#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1, select or deselect one card */ +#define MMC_SEND_EXT_CSD 8 /* adtc,the card sends it's ex_csd as a block of data,R1 */ +#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2, addressed card send CSD */ +#define MMC_SEND_CID 10 /* ac, addressed card send CID,R2 */ +#define MMC_READ_DATA_UNTIL_STOP 11 /* atdc,read data stream from catd until a STOP_TRANSMITISSION follows,R1 */ +#define MMC_STOP_TRANSMISSION 12 /* ac, termilate a multiple block read/write operation,R1b */ +#define MMC_SEND_STATUS 13 /* ac, addressed card send its status regesiter,R1 */ +#define MMC_GO_INACTIVE_STATE 15 /* ac, sets the card to inactive state */ +#define MMC_SEND_TUNING_PATTERN 19 /* adtc, send 64 bytes pattern for sdr50 and sdr104 mode */ + +/* erase commands*/ +#define MMC_ERASE_WR_BLK_START 32 /* ac,sets the address of the first write bloock to be erased,R1 */ +#define MMC_ERASE_WR_BLK_END 33 /* ac,sets the address of the last write bloock to be erased,R1 */ + +/*MMC private command*/ +#define MMC_SEND_OP_COND 1 /* bcr,Activates the card's initialization process,R3 */ +#define MMC_SWITCH 6 /* ac,switch the mode of operation of the selected card or modifies tge EXT_CSD,R1b */ +#define MMC_BUSTEST_R 14 /* adtc,a host reads the reversed testing data pattern from a card,R1 */ +#define MMC_BUSTEST_W 19 /* adtc,a host sends the bus teset data pattern to a card,R1 */ + +/*sd io command*/ +#define IO_SEND_OP_COND 5 /* for SD IO.similar to ACMD41 for sd mem */ +#define IO_RW_DIRECT 52 +#define IO_RW_EXTENDED 53 +#define SD_IO_CMD54 54 + + /* class 2 */ +#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1, select a block length for all read/write cmds */ +#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1, reads a block of the size seclected by SET_BLOCKLEN */ +#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1, continuously send blocks of data until interrupted by a stop transmission commmad */ +#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ +#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ + + /* class 3 */ +#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ + + /* class 4 */ +#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_SINGLE_BLOCK 24 /* adtc [31:0] data addr R1, writes a block of the size seclected by SET_BLOCKLEN */ +#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1, continuously writes blocks of data until interrupted by a stop transmission commmad */ +#define MMC_PROGRAM_CID 26 /* adtc R1 */ +#define MMC_PROGRAM_CSD 27 /* adtc R1, program the programmable bits of CSD */ + + /* class 6 */ +#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b, sets the write protect bit of the addressed group */ +#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b, clears the write protect bit of the addressed group */ +#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1, ask the card to send status of the write protection bits */ + + /* class 5 */ +#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ +#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ +#define MMC_ERASE 38 /* ac R1b, erase all selected write blocks */ + + /* class 9 */ +#define MMC_FAST_IO 39 /* ac R4, used to read or write 8 bit registers */ +#define MMC_GO_IRQ_STATE 40 /* bcr R5, sets the system info interrupt mode */ + + /* class 7 */ +#define MMC_LOCK_UNLOCK 42 /* adtc R1b, lock or unlock sd card */ + + /* class 8 */ +#define MMC_APP_CMD 55 /* ac [31:16] RCA R1, indicates the next cmd is an specific cmd */ +#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1, send or get a block of data */ + +static inline uint32_t mmc_op_multi(uint32_t opcode) +{ + return opcode == MMC_WRITE_MULTIPLE_BLOCK || + opcode == MMC_READ_MULTIPLE_BLOCK; +} + +/* + * MMC_SWITCH argument format: + * + * [31:26] Always 0 + * [25:24] Access Mode + * [23:16] Location of target Byte in EXT_CSD + * [15:08] Value Byte + * [07:03] Always 0 + * [02:00] Command Set + */ + +/* + MMC status in R1, for native mode (SPI bits are different) + Type + e : error bit + s : status bit + r : detected and set for the actual command response + x : detected and set during command execution. the host must poll + the card by sending status command in order to read these bits. + Clear condition + a : according to the card state + b : always related to the previous command. Reception of + a valid command will clear it (with a delay of one command) + c : clear by read + */ + +#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ +#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ +#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ +#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ +#define R1_ERASE_PARAM (1 << 27) /* ex, c */ +#define R1_WP_VIOLATION (1 << 26) /* erx, c */ +#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ +#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ +#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ +#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ +#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ +#define R1_CC_ERROR (1 << 20) /* erx, c */ +#define R1_ERROR (1 << 19) /* erx, c */ +#define R1_UNDERRUN (1 << 18) /* ex, c */ +#define R1_OVERRUN (1 << 17) /* ex, c */ +#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ +#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ +#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ +#define R1_ERASE_RESET (1 << 13) /* sr, c */ +#define R1_STATUS(x) (x & 0xFFFFE000) +#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ +#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ +#define R1_SWITCH_ERROR (1 << 7) /* sx, c */ +#define R1_APP_CMD (1 << 5) /* sr, c */ + +#define R1_STATE_IDLE 0 +#define R1_STATE_READY 1 +#define R1_STATE_IDENT 2 +#define R1_STATE_STBY 3 +#define R1_STATE_TRAN 4 +#define R1_STATE_DATA 5 +#define R1_STATE_RCV 6 +#define R1_STATE_PRG 7 +#define R1_STATE_DIS 8 + +/* + * OCR bits are mostly in host.h + */ +#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ + +/*ce-ata command*/ +#define CEATA_RW_MULTIPLE_REGISTER 60 +#define CEATA_RW_MULTIPLE_BLOCK 61 + +/*application specific commands used by sd mem*/ +#define SET_BUS_WIDTH 6 /* ac,define the bus width(00 = 1bit, 10 = 4bit),R1 */ +#define SD_STATUS 13 /* adtc,send the sd card status,R1 */ +#define SEND_NUM_WR_BLOCKS 22 /* adtc,send the number of written write blocks,R1 */ +#define SET_WR_BLK_ERASE_CNT 23 /* ac,set the number of write blocks to be pre-erased before writing,R1 */ +#define SD_APP_OP_COND 41 /* bcr,asks the accessed card to send its OCR(operating conditon register) content,R3 */ +#define SET_CLR_CARD_DETECT 42 /* ac,connect or disconnect the pull up resistor of the card for card detect,R1 */ +#define SEND_SCR 51 /* adtc,reads the SCR(sd configure register),R1 */ + +/* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS + * R1 is the low order byte; R2 is the next highest byte, when present. + */ +#define R1_SPI_IDLE (1 << 0) +#define R1_SPI_ERASE_RESET (1 << 1) +#define R1_SPI_ILLEGAL_COMMAND (1 << 2) +#define R1_SPI_COM_CRC (1 << 3) +#define R1_SPI_ERASE_SEQ (1 << 4) +#define R1_SPI_ADDRESS (1 << 5) +#define R1_SPI_PARAMETER (1 << 6) + +/* R1 bit 7 is always zero */ +#define R2_SPI_CARD_LOCKED (1 << 8) +#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ +#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP +#define R2_SPI_ERROR (1 << 10) +#define R2_SPI_CC_ERROR (1 << 11) +#define R2_SPI_CARD_ECC_ERROR (1 << 12) +#define R2_SPI_WP_VIOLATION (1 << 13) +#define R2_SPI_ERASE_PARAM (1 << 14) +#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ +#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE + +#define CEATA_INDENTIFY_DEVICE 0xec +#define CEATA_READ_DMA_EXT 0x25 +#define CEATA_WRITE_DMA_EXT 0x35 +#define CEATA_STANBY_IMMIDIATE 0xe0 +#define CEATA_FLUSH_CACHE_EXT 0Xea + +/* + * OCR bits are mostly in host.h + */ +#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ + +/* Card Command Classes (CCC) */ +#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ + /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ + /* (and for SPI, CMD58,59) */ +#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ + /* (CMD11) */ +#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ + /* (CMD16,17,18) */ +#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ + /* (CMD20) */ +#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ + /* (CMD16,24,25,26,27) */ +#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ + /* (CMD32,33,34,35,36,37,38,39) */ +#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ + /* (CMD28,29,30) */ +#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ + /* (CMD16,CMD42) */ +#define CCC_APP_SPEC (1<<8) /* (8) Application specific */ + /* (CMD55,56,57,ACMD*) */ +#define CCC_IO_MODE (1<<9) /* (9) I/O mode */ + /* (CMD5,39,40,52,53) */ +#define CCC_SWITCH (1<<10) /* (10) High speed switch */ + /* (CMD6,34,35,36,37,50) */ + /* (11) Reserved */ + /* (CMD?) */ + +/* CSD field definitions */ +#define MMC_CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ +#define MMC_CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ +#define MMC_CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ +#define MMC_CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ + +#define MMC_CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ +#define MMC_CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ +#define MMC_CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ +#define MMC_CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ +#define MMC_CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ + +/* EXT_CSD fields */ +#define MMC_EXT_CSD_BOOT_BUS_COND 177 /* R/W */ +#define MMC_EXT_CSD_PART_CONF 179 /* R/W */ +#define MMC_EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define MMC_EXT_CSD_HS_TIMING 185 /* R/W */ +#define MMC_EXT_CSD_CARD_TYPE 196 /* RO */ +#define MMC_EXT_CSD_REV 192 /* RO */ +#define MMC_EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ + +/* EXT_CSD field definitions */ +#define MMC_EXT_CSD_CMD_SET_NORMAL (1<<0) +#define MMC_EXT_CSD_CMD_SET_SECURE (1<<1) +#define MMC_EXT_CSD_CMD_SET_CPSECURE (1<<2) + +#define MMC_EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ +#define MMC_EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ + +#define MMC_EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define MMC_EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define MMC_EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define MMC_EXT_CSD_BUS_WIDTH_4_DDR 5 /* Card is in 4 bit mode in DDR mode */ +#define MMC_EXT_CSD_BUS_WIDTH_8_DDR 6 /* Card is in 8 bit mode in DDR mode */ + +/* MMC_SWITCH access modes */ +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ + +/* MMC_SWITCH boot modes */ +#define MMC_SWITCH_MMCPART_NOAVAILABLE (0xff) +#define MMC_SWITCH_PART_ACCESS_MASK (0x7) +#define MMC_SWITCH_PART_SUPPORT (0x1) +#define MMC_SWITCH_PART_BOOT_PART_MASK (0x7 << 3) +#define MMC_SWITCH_PART_BOOT_PART_NONE (0x0) +#define MMC_SWITCH_PART_BOOT_PART_1 (0x1) +#define MMC_SWITCH_PART_BOOT_PART_2 (0x2) +#define MMC_SWITCH_PART_BOOT_USER (0x7) +#define MMC_SWITCH_PART_BOOT_ACK_MASK (0x1 << 6) +#define MMC_SWITCH_PART_BOOT_ACK_ENB (0x1) + +/* MMC_SWITCH boot condition */ +#define MMC_SWITCH_MMCBOOT_BUS_NOAVAILABLE (0xff) +#define MMC_SWITCH_BOOT_MODE_MASK (0x3 << 3) +#define MMC_SWITCH_BOOT_SDR_NORMAL (0x0) +#define MMC_SWITCH_BOOT_SDR_HS (0x1) +#define MMC_SWITCH_BOOT_DDR (0x2) +#define MMC_SWITCH_BOOT_RST_BUS_COND_MASK (0x1 << 2) +#define MMC_SWITCH_BOOT_RST_BUS_COND (0x0) +#define MMC_SWITCH_BOOT_RETAIN_BUS_COND (0x1) +#define MMC_SWITCH_BOOT_BUS_WIDTH_MASK (0x3 << 0) +#define MMC_SWITCH_BOOT_BUS_SDRx1_DDRx4 (0x0) +#define MMC_SWITCH_BOOT_BUS_SDRx4_DDRx4 (0x1) +#define MMC_SWITCH_BOOT_BUS_SDRx8_DDRx8 (0x2) + +/* SD_SWITCH function groups */ +#define SD_SWITCH_GRP_ACCESS_MODE 0 +#define SD_SWITCH_GRP_CMD_SYSTEM 1 +#define SD_SWITCH_GRP_DRV_STRENGTH 2 +#define SD_SWITCH_GRP_CUR_LIMIT 3 + +/* SD_SWITCH access modes */ +#define SD_SWITCH_ACCESS_DEF_SDR12 0 +#define SD_SWITCH_ACCESS_HS_SDR25 1 +#define SD_SWITCH_ACCESS_SDR50 2 +#define SD_SWITCH_ACCESS_SDR104 3 +#define SD_SWITCH_ACCESS_DDR50 4 + +/* SD_SWITCH cmd system */ +#define SD_SWITCH_CMDSYS_DEF 0 +#define SD_SWITCH_CMDSYS_EC 1 +#define SD_SWITCH_CMDSYS_OTP 3 +#define SD_SWITCH_CMDSYS_ASSD 4 +#define SD_SWITCH_CMDSYS_ESD 0xc + +/* SD_SWITCH driver strength */ +#define SD_SWITCH_DRVSTR_DEF_TB 0 +#define SD_SWITCH_DRVSTR_DEF_TA 1 +#define SD_SWITCH_DRVSTR_DEF_TC 2 +#define SD_SWITCH_DRVSTR_DEF_TD 3 + +/* SD_SWITCH current limit */ +#define SD_SWITCH_CURLMT_DEF_200MA 0 +#define SD_SWITCH_CURLMT_DEF_400MA 1 +#define SD_SWITCH_CURLMT_DEF_600MA 2 +#define SD_SWITCH_CURLMT_DEF_800MA 3 + +/** + * @brief read SD card. + * @param card: + * @arg card->card handler. + * @param buf: + * @arg buf->for store readed data. + * @param sblk: + * @arg sblk->start block num. + * @param nblk: + * @arg nblk->number of blocks. + * @retval 0 if success or other if failed. + */ +extern int32_t mmc_block_read(struct mmc_card *card, uint8_t *buf, uint64_t sblk, uint32_t nblk); + +/** + * @brief write SD card. + * @param card: + * @arg card->card handler. + * @param buf: + * @arg buf->data will be write. + * @param sblk: + * @arg sblk->start block num. + * @param nblk: + * @arg nblk->number of blocks. + * @retval 0 if success or other if failed. + */ +extern int32_t mmc_block_write(struct mmc_card *card, const uint8_t *buf, uint64_t sblk, uint32_t nblk); + +/** + * @brief scan or rescan SD card. + * @param card: + * @arg card->card handler. + * @param sdc_id: + * @arg sdc_id->SDC ID which card on. + * @retval 0 if success or other if failed. + */ +extern int32_t mmc_rescan(struct mmc_card *card, uint32_t sdc_id); + +/** + * @brief deinit SD card. + * @param card: + * @arg card->card handler. + * @retval 0 if success or other if failed. + */ +extern int32_t mmc_card_deinit(struct mmc_card *card); + +extern int32_t mmc_test(uint32_t cd_mode); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_SDMMC_SDMMC_H_ */ diff --git a/platform/mcu/xr871/include/driver/chip/system_chip.h b/platform/mcu/xr871/include/driver/chip/system_chip.h new file mode 100644 index 0000000000..0fb5d697fc --- /dev/null +++ b/platform/mcu/xr871/include/driver/chip/system_chip.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_SYSTEM_CHIP_H_ +#define _DRIVER_CHIP_SYSTEM_CHIP_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SYSTEM_DEINIT_FLAG_RESET_CLK HAL_BIT(0) + +void SystemInit(void); +void SystemDeInit(uint32_t flag); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_SYSTEM_CHIP_H_ */ diff --git a/platform/mcu/xr871/include/driver/cmsis/core_cm3.h b/platform/mcu/xr871/include/driver/cmsis/core_cm3.h new file mode 100644 index 0000000000..e1357c6735 --- /dev/null +++ b/platform/mcu/xr871/include/driver/cmsis/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/mcu/xr871/include/driver/cmsis/core_cm4.h b/platform/mcu/xr871/include/driver/cmsis/core_cm4.h new file mode 100644 index 0000000000..bb6be1305d --- /dev/null +++ b/platform/mcu/xr871/include/driver/cmsis/core_cm4.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/mcu/xr871/include/driver/cmsis/core_cmFunc.h b/platform/mcu/xr871/include/driver/cmsis/core_cmFunc.h new file mode 100644 index 0000000000..01089f1333 --- /dev/null +++ b/platform/mcu/xr871/include/driver/cmsis/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/platform/mcu/xr871/include/driver/cmsis/core_cmInstr.h b/platform/mcu/xr871/include/driver/cmsis/core_cmInstr.h new file mode 100644 index 0000000000..d14110b2ab --- /dev/null +++ b/platform/mcu/xr871/include/driver/cmsis/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/platform/mcu/xr871/include/driver/cmsis/core_cmSimd.h b/platform/mcu/xr871/include/driver/cmsis/core_cmSimd.h new file mode 100644 index 0000000000..ee58eee56d --- /dev/null +++ b/platform/mcu/xr871/include/driver/cmsis/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/platform/mcu/xr871/include/driver/hal_board.h b/platform/mcu/xr871/include/driver/hal_board.h new file mode 100644 index 0000000000..e705262b0d --- /dev/null +++ b/platform/mcu/xr871/include/driver/hal_board.h @@ -0,0 +1,67 @@ +/** + * @file hal_board.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_HAL_BOARD_H_ +#define _DRIVER_HAL_BOARD_H_ + +#include "driver/chip/hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief HAL board I/O control request + * + * @note Every request MUST be related to board's configuration + */ +typedef enum { + HAL_BIR_PINMUX_INIT, /* init pinmux */ + HAL_BIR_PINMUX_DEINIT, /* deinit pinmux */ + HAL_BIR_CHIP_CLOCK_INIT, /* init chip clock */ + HAL_BIR_GET_CFG, /* get configuration */ +} HAL_BoardIoctlReq; + +/** @brief type define of HAL board I/O control callback function */ +typedef HAL_Status (*HAL_BoardIoctlCb)(HAL_BoardIoctlReq req, uint32_t param0, uint32_t param1); + +HAL_BoardIoctlCb HAL_BoardIoctlCbRegister(HAL_BoardIoctlCb cb); + +HAL_Status HAL_BoardIoctl(HAL_BoardIoctlReq req, uint32_t param0, uint32_t param1); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_HAL_BOARD_H_ */ diff --git a/platform/mcu/xr871/include/driver/hal_dev.h b/platform/mcu/xr871/include/driver/hal_dev.h new file mode 100644 index 0000000000..bef41be259 --- /dev/null +++ b/platform/mcu/xr871/include/driver/hal_dev.h @@ -0,0 +1,94 @@ +/** + * @file hal_dev.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_HAL_DEV_H_ +#define _DRIVER_HAL_DEV_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief HAL device number + * + * HAL device number is made up of major number and minor number. + * - Major number is defined as HAL_DEV_MAJOR_XXX + * - minor number is defined by the specific driver + */ +typedef uint32_t HAL_Dev_t; + +#define HAL_DEV_MINOR_BITS 16 +#define HAL_DEV_MINOR_MASK ((1U << HAL_DEV_MINOR_BITS) - 1) + +/** @brief Get major number from device number */ +#define HAL_DEV_MAJOR(dev) ((uint32_t)((dev) >> HAL_DEV_MINOR_BITS)) + +/** @brief Get minor number from device number */ +#define HAL_DEV_MINOR(dev) ((uint32_t)((dev) & HAL_DEV_MINOR_MASK)) + +/** @brief Make device number from major number and minor number */ +#define HAL_MKDEV(major, minor) \ + (((HAL_Dev_t)(major) << HAL_DEV_MINOR_BITS) | \ + ((HAL_Dev_t)(minor) & HAL_DEV_MINOR_MASK)) + +/** + * @brief Major number of device + */ +enum { + /* peripheral interface of chip */ + HAL_DEV_MAJOR_UART = 0U, + HAL_DEV_MAJOR_I2C, + HAL_DEV_MAJOR_SPI, + HAL_DEV_MAJOR_IRRX, + HAL_DEV_MAJOR_IRTX, + HAL_DEV_MAJOR_I2S, + HAL_DEV_MAJOR_DMIC, + HAL_DEV_MAJOR_ADC, + HAL_DEV_MAJOR_PWM, + HAL_DEV_MAJOR_FLASHC, /* FLASH controller interface */ + HAL_DEV_MAJOR_SDC, + HAL_DEV_MAJOR_CSI, + + /* external component */ + HAL_DEV_MAJOR_FLASH = 100U, + HAL_DEV_MAJOR_AUDIO_CODEC, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_HAL_DEV_H_ */ diff --git a/platform/mcu/xr871/include/efpg/efpg.h b/platform/mcu/xr871/include/efpg/efpg.h new file mode 100644 index 0000000000..ac2691d255 --- /dev/null +++ b/platform/mcu/xr871/include/efpg/efpg.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EFPG_EFPG_H_ +#define _EFPG_EFPG_H_ + +#include +#include "driver/chip/hal_uart.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief EFPG field definition + */ +typedef enum efpg_field { + EFPG_FIELD_HOSC = 0, /* data buffer size: 1 byte */ + EFPG_FIELD_BOOT = 1, /* data buffer size: 32 bytes */ + EFPG_FIELD_DCXO = 2, /* data buffer size: 1 byte */ + EFPG_FIELD_POUT = 3, /* data buffer size: 3 bytes */ + EFPG_FIELD_MAC = 4, /* data buffer size: 6 bytes */ + EFPG_FIELD_CHIPID = 5, /* data buffer size: 16 bytes */ + EFPG_FIELD_UA = 6, /* data buffer size: 601 bytes */ + EFPG_FIELD_NUM = 7, +} efpg_field_t; + +/** + * @brief EFPG HOSC value definition + */ +#define EFPG_HOSC_24M (0x06) +#define EFPG_HOSC_26M (0x03) +#define EFPG_HOSC_40M (0x0C) +#define EFPG_HOSC_52M (0x09) + +/** @brief Type define of EFPG callback function */ +typedef void (*efpg_cb_t)(void); + +int efpg_start(uint8_t *key, uint8_t key_len, UART_ID uart_id, efpg_cb_t start_cb, efpg_cb_t stop_cb); + +int efpg_read(efpg_field_t field, uint8_t *data); + +int efpg_read_ua(uint32_t start, uint32_t num, uint8_t *data); + +#ifdef __cplusplus +} +#endif + +#endif /* _EFPG_EFPG_H_ */ \ No newline at end of file diff --git a/platform/mcu/xr871/include/fs/fatfs/ff.h b/platform/mcu/xr871/include/fs/fatfs/ff.h new file mode 100644 index 0000000000..90659b7836 --- /dev/null +++ b/platform/mcu/xr871/include/fs/fatfs/ff.h @@ -0,0 +1,365 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem module R0.13 / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2017, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: + +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#ifndef FF_DEFINED +#define FF_DEFINED 87030 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* Standard errno definations */ +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if FF_DEFINED != FFCONF_DEF +#error Wrong configuration file (ffconf.h). +#endif + + + +/* Definitions of volume management */ + +#if FF_MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ +#endif + + + +/* Type of path name strings on FatFs API */ + +#if FF_LFN_UNICODE && FF_USE_LFN /* Unicode (UTF-16) string */ +#ifndef _INC_TCHAR +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#define _INC_TCHAR +#endif +#else /* ANSI/OEM string */ +#ifndef _INC_TCHAR +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#define _INC_TCHAR +#endif +#endif + + + +/* Type of file size variables */ + +#if FF_FS_EXFAT +#if !FF_USE_LFN +#error LFN must be enabled when enable exFAT +#endif +typedef QWORD FSIZE_t; +#else +typedef DWORD FSIZE_t; +#endif + + + +/* Filesystem object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* Filesystem type (0:N/A) */ + BYTE pdrv; /* Physical drive number */ + BYTE n_fats; /* Number of FATs (1 or 2) */ + BYTE wflag; /* win[] flag (b0:dirty) */ + BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ + WORD id; /* Volume mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ + WORD csize; /* Cluster size [sectors] */ +#if FF_MAX_SS != FF_MIN_SS + WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ +#endif +#if FF_USE_LFN + WCHAR* lfnbuf; /* LFN working buffer */ +#endif +#if FF_FS_EXFAT + BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */ +#endif +#if FF_FS_REENTRANT + FF_SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !FF_FS_READONLY + DWORD last_clst; /* Last allocated cluster */ + DWORD free_clst; /* Number of free clusters */ +#endif +#if FF_FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#if FF_FS_EXFAT + DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ + DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ + DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ +#endif +#endif + DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ + DWORD fsize; /* Size of an FAT [sectors] */ + DWORD volbase; /* Volume base sector */ + DWORD fatbase; /* FAT base sector */ + DWORD dirbase; /* Root directory base sector/cluster */ + DWORD database; /* Data base sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ +} FATFS; + + + +/* Object ID and allocation information (FFOBJID) */ + +typedef struct { + FATFS* fs; /* Pointer to the hosting volume of this object */ + WORD id; /* Hosting volume mount ID */ + BYTE attr; /* Object attribute */ + BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */ + DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */ + FSIZE_t objsize; /* Object size (valid when sclust != 0) */ +#if FF_FS_EXFAT + DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */ + DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */ + DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ + DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ + DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */ +#endif +#if FF_FS_LOCK + UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ +#endif +} FFOBJID; + + + +/* File object structure (FIL) */ + +typedef struct { + FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ + BYTE flag; /* File status flags */ + BYTE err; /* Abort flag (error code) */ + FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ + DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */ + DWORD sect; /* Sector number appearing in buf[] (0:invalid) */ +#if !FF_FS_READONLY + DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */ + BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */ +#endif +#if FF_USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ +#endif +#if !FF_FS_TINY + BYTE buf[FF_MAX_SS]; /* File private data read/write window */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FFOBJID obj; /* Object identifier */ + DWORD dptr; /* Current read/write offset */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector (0:Read operation has terminated) */ + BYTE* dir; /* Pointer to the directory item in the win[] */ + BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ +#if FF_USE_LFN + DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ +#endif +#if FF_USE_FIND + const TCHAR* pat; /* Pointer to the name matching pattern */ +#endif +} FF_DIR; + + + +/* File information structure (FILINFO) */ + +typedef struct { + FSIZE_t fsize; /* File size */ + WORD fdate; /* Modified date */ + WORD ftime; /* Modified time */ + BYTE fattrib; /* File attribute */ +#if FF_USE_LFN + TCHAR altname[13]; /* Altenative file name */ + TCHAR fname[FF_MAX_LFN + 1]; /* Primary file name */ +#else + TCHAR fname[13]; /* File name */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR = -EIO, /* (1) A hard error occurred in the low level disk I/O layer */ + FR_INT_ERR = -EIO, /* (2) Assertion failed */ + FR_NOT_READY = -ENODEV, /* (3) The physical drive cannot work */ + FR_NO_FILE = -ENOENT, /* (4) Could not find the file */ + FR_NO_PATH = -ENOENT, /* (5) Could not find the path */ + FR_INVALID_NAME = -EINVAL, /* (6) The path name format is invalid */ + FR_DENIED = -EACCES, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST = -EEXIST, /* (8) Access denied due to prohibited access */ + FR_INVALID_OBJECT = -EBADF, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED = -EACCES, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE = -ENXIO, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED = -ENODEV, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM = -ENODEV, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED = -EINTR, /* (14) The f_mkfs() aborted due to any problem */ + FR_TIMEOUT = -ETIMEDOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED = -EACCES, /* (16) The operation is rejected according to the file sharing policy */ + FR_NOT_ENOUGH_CORE = -ENOMEM, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES = -ENFILE, /* (18) Number of open files > FF_FS_LOCK */ + FR_INVALID_PARAMETER = -EINVAL /* (19) Given parameter is invalid */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ +FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ +FRESULT f_truncate (FIL* fp); /* Truncate the file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ +FRESULT f_opendir (FF_DIR* dp, const TCHAR* path); /* Open a directory */ +FRESULT f_closedir (FF_DIR* dp); /* Close an open directory */ +FRESULT f_readdir (FF_DIR* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_findfirst (FF_DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ +FRESULT f_findnext (FF_DIR* dp, FILINFO* fno); /* Find next file */ +FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ +FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ +FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ +FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ +FRESULT f_chdir (const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ +FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */ +FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */ +FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */ +FRESULT f_setcp (WORD cp); /* Set current code page */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ + +#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) +#define f_error(fp) ((fp)->err) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->obj.objsize) +#define f_rewind(fp) f_lseek((fp), 0) +#define f_rewinddir(dp) f_readdir((dp), 0) +#define f_rmdir(path) f_unlink(path) +#define f_unmount(path) f_mount(0, path, 0) + +#ifndef EOF +#define EOF (-1) +#endif + + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !FF_FS_READONLY && !FF_FS_NORTC +DWORD get_fattime (void); +#endif + +/* LFN support functions */ +#if FF_USE_LFN /* Code conversion (defined in unicode.c) */ +WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */ +WCHAR ff_uni2oem (WCHAR uni, WORD cp); /* Unicode to OEM code conversion */ +WCHAR ff_wtoupper (WCHAR uni); /* Unicode upper-case conversion */ +#endif +#if FF_USE_LFN == 3 /* Dynamic memory allocation */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ +#endif + +/* Sync functions */ +#if FF_FS_REENTRANT +int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */ +int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */ +void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */ +int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access mode and open method flags (3rd argument of f_open) */ +#define FA_READ 0x01 +#define FA_WRITE 0x02 +#define FA_OPEN_EXISTING 0x00 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA_OPEN_APPEND 0x30 + +/* Fast seek controls (2nd argument of f_lseek) */ +#define CREATE_LINKMAP ((FSIZE_t)0 - 1) + +/* Format options (2nd argument of f_mkfs) */ +#define FM_FAT 0x01 +#define FM_FAT32 0x02 +#define FM_EXFAT 0x04 +#define FM_ANY 0x07 +#define FM_SFD 0x08 + +/* Filesystem type (FATFS.fs_type) */ +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 +#define FS_EXFAT 4 + +/* File attribute bits for directory entry (FILINFO.fattrib) */ +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + +#ifdef __cplusplus +} +#endif + +#endif /* FF_DEFINED */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_common.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_common.h new file mode 100644 index 0000000000..605c8f1e18 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_common.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_COMMON_H_ +#define _KERNEL_OS_YUNOS_OS_COMMON_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OS_PRIORITY_IDLE = RHINO_IDLE_PRI, + OS_PRIORITY_LOW = 11, + OS_PRIORITY_BELOW_NORMAL = 10, + OS_PRIORITY_NORMAL = 9, + OS_PRIORITY_ABOVE_NORMAL = 8, + OS_PRIORITY_HIGH = (RHINO_CONFIG_TIMER_TASK_PRI + 1), + OS_PRIORITY_REAL_TIME = (RHINO_CONFIG_TIMER_TASK_PRI) +} OS_Priority; + +typedef enum { + OS_OK = 0, + OS_FAIL = -1, + OS_E_NOMEM = -2, + OS_E_PARAM = -3, + OS_E_TIMEOUT = -4, + OS_E_ISR = -5, +} OS_Status; + +typedef uint32_t OS_Time_t; + +#define OS_WAIT_FOREVER 0xffffffffU +#define OS_SEMAPHORE_MAX_COUNT 0xffffffffU +#define OS_INVALID_HANDLE NULL + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_COMMON_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_errno.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_errno.h new file mode 100644 index 0000000000..f3c0339e58 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_errno.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_ERRNO_H_ +#define _KERNEL_OS_YUNOS_OS_ERRNO_H_ + +#include "kernel/os/YunOS/os_common.h" + +/* nothing to define for BSP */ + +static __inline int OS_GetErrno(void) +{ + return 0; +} + +static __inline void OS_SetErrno(int err) +{ +} + +#endif /* _KERNEL_OS_YUNOS_OS_ERRNO_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_mutex.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_mutex.h new file mode 100644 index 0000000000..2987832d4f --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_mutex.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_MUTEX_H_ +#define _KERNEL_OS_YUNOS_OS_MUTEX_H_ + +#include "kernel/os/YunOS/os_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct OS_Mutex { + kmutex_t mutex; +} OS_Mutex_t; + +static __inline OS_Status OS_MutexCreate(OS_Mutex_t *mutex) +{ + if (RHINO_SUCCESS == krhino_mutex_create(&mutex->mutex, "UNDEF")) { + return OS_OK; + } else { + return OS_FAIL; + } +} + + +static __inline OS_Status OS_MutexDelete(OS_Mutex_t *mutex) +{ + if (RHINO_SUCCESS == krhino_mutex_del(&mutex->mutex)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_MutexLock(OS_Mutex_t *mutex, OS_Time_t waitMS) +{ + tick_t ticks = OS_MSecsToTicks(waitMS); + + if (RHINO_SUCCESS == krhino_mutex_lock(&mutex->mutex, ticks)) { + return OS_OK; + } else { + return OS_E_TIMEOUT; + } +} + +static __inline OS_Status OS_MutexUnlock(OS_Mutex_t *mutex) +{ + if (RHINO_SUCCESS == krhino_mutex_unlock(&mutex->mutex)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_RecursiveMutexCreate(OS_Mutex_t *mutex) +{ + return OS_MutexCreate(mutex); +} + +static __inline OS_Status OS_RecursiveMutexDelete(OS_Mutex_t *mutex) +{ + return OS_MutexDelete(mutex); +} + +static __inline OS_Status OS_RecursiveMutexLock(OS_Mutex_t *mutex, OS_Time_t waitMS) +{ + return OS_MutexLock(mutex, waitMS); +} + +static __inline OS_Status OS_RecursiveMutexUnlock(OS_Mutex_t *mutex) +{ + return OS_MutexUnlock(mutex); +} + +static __inline int OS_MutexIsValid(OS_Mutex_t *mutex) +{ + return (mutex->mutex.blk_obj.obj_type == RHINO_MUTEX_OBJ_TYPE); +} + +static __inline void OS_MutexSetInvalid(OS_Mutex_t *mutex) +{ + mutex->mutex.blk_obj.obj_type = RHINO_OBJ_TYPE_NONE; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_MUTEX_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_queue.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_queue.h new file mode 100644 index 0000000000..6a541354ed --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_queue.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_QUEUE_H_ +#define _KERNEL_OS_YUNOS_OS_QUEUE_H_ + +#include "kernel/os/YunOS/os_time.h" +#include "kernel/os/YunOS/os_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct OS_Queue { + kbuf_queue_t queue; + uint32_t item_size; + void* msg_start; +} OS_Queue_t; + +static __inline int OS_QueueIsValid(OS_Queue_t *queue) +{ + return (queue->queue.blk_obj.obj_type == RHINO_BUF_QUEUE_OBJ_TYPE); +} + +static __inline void OS_QueueSetInvalid(OS_Queue_t *queue) +{ + queue->queue.blk_obj.obj_type = RHINO_OBJ_TYPE_NONE; +} + + +static __inline OS_Status OS_QueueCreate(OS_Queue_t *queue, uint32_t queueLen, uint32_t itemSize) +{ + void *msg_start = NULL; + + msg_start = malloc(queueLen * itemSize); + if (msg_start == NULL) { + return OS_E_NOMEM; + } + + if (RHINO_SUCCESS == krhino_buf_queue_create(&queue->queue, "UNDEF", (void**)msg_start, queueLen * itemSize, itemSize)) { + queue->msg_start = msg_start; + queue->item_size = itemSize; + return OS_OK; + } else { + free(msg_start); + msg_start = NULL; + return OS_FAIL; + } +} + +static __inline OS_Status OS_QueueDelete(OS_Queue_t *queue) +{ + if ((queue != NULL)) { + if (RHINO_SUCCESS == krhino_buf_queue_del(&queue->queue)) { + if(queue->msg_start != NULL) + free(queue->msg_start); + return OS_OK; + } else { + return OS_FAIL; + } + } + return OS_OK; +} + +static __inline OS_Status OS_QueueSend(OS_Queue_t *queue, const void *item, OS_Time_t waitMS) +{ + if (RHINO_SUCCESS == krhino_buf_queue_send(&queue->queue, item, queue->item_size)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_QueueReceive(OS_Queue_t *queue, void *item, OS_Time_t waitMS) +{ + tick_t ticks = waitMS == OS_WAIT_FOREVER ? OS_WAIT_FOREVER : OS_MSecsToTicks(waitMS); + size_t msg_len; + + if (RHINO_SUCCESS == krhino_buf_queue_recv(&queue->queue, ticks, item, &msg_len)) { + return OS_OK; + } else { + return OS_E_TIMEOUT; + } +} + +static __inline OS_Status OS_MsgQueueCreate(OS_Queue_t *queue, uint32_t queueLen) +{ + return OS_QueueCreate(queue, queueLen, sizeof(void*)); +} + +static __inline OS_Status OS_MsgQueueDelete(OS_Queue_t *queue) +{ + return OS_QueueDelete(queue); +} + +static __inline OS_Status OS_MsgQueueSend(OS_Queue_t *queue, void *msg, OS_Time_t waitMS) +{ + return OS_QueueSend(queue, &msg, waitMS); +} + +static __inline OS_Status OS_MsgQueueReceive(OS_Queue_t *queue, void **msg, OS_Time_t waitMS) +{ + return OS_QueueReceive(queue, msg, waitMS); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_QUEUE_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_semaphore.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_semaphore.h new file mode 100644 index 0000000000..6904fea90e --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_semaphore.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_SEMAPHORE_H_ +#define _KERNEL_OS_YUNOS_OS_SEMAPHORE_H_ + +#include "kernel/os/YunOS/os_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct OS_Semaphore { + ksem_t sem; + uint32_t count; + uint32_t max_count; +} OS_Semaphore_t; + +static __inline OS_Status OS_SemaphoreCreate(OS_Semaphore_t *sem, uint32_t initCount, uint32_t maxCount) +{ + if (RHINO_SUCCESS == krhino_sem_create(&sem->sem, "UNDEF", (sem_count_t)initCount)) { + sem->count = initCount; + sem->max_count = maxCount; + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_SemaphoreCreateBinary(OS_Semaphore_t *sem) +{ + if (RHINO_SUCCESS == krhino_sem_create(&sem->sem, "UNDEF", 0)) { + sem->count = 0; + sem->max_count = 1; + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_SemaphoreDelete(OS_Semaphore_t *sem) +{ + if (RHINO_SUCCESS == krhino_sem_del(&sem->sem)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_SemaphoreWait(OS_Semaphore_t *sem, OS_Time_t waitMS) +{ + tick_t ticks = waitMS == OS_WAIT_FOREVER ? OS_WAIT_FOREVER : OS_MSecsToTicks(waitMS); + OS_Status ret; + kstat_t sta; + uint32_t time_tick = OS_GetTicks(); + + if (sem == NULL) { + return OS_FAIL; + } + + sta = krhino_sem_take(&sem->sem, ticks); + if(sta == RHINO_SUCCESS) { + if (sem->count) + sem->count--; + ret = OS_OK; + } else { + ret = OS_E_TIMEOUT; + } + + return ret; +} + +static __inline OS_Status OS_SemaphoreRelease(OS_Semaphore_t *sem) +{ + if (sem->max_count == 1 && sem->count == 1) { + return OS_FAIL; + } + if (RHINO_SUCCESS == krhino_sem_give(&sem->sem)) { + if (sem->count < sem->max_count) + sem->count++; + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline int OS_SemaphoreIsValid(OS_Semaphore_t *sem) +{ + return (sem->sem.blk_obj.obj_type == RHINO_SEM_OBJ_TYPE); +} + +static __inline void OS_SemaphoreSetInvalid(OS_Semaphore_t *sem) +{ + sem->sem.blk_obj.obj_type = RHINO_OBJ_TYPE_NONE; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_SEMAPHORE_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_thread.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_thread.h new file mode 100644 index 0000000000..2c13881352 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_thread.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_THREAD_H_ +#define _KERNEL_OS_YUNOS_OS_THREAD_H_ + +#include +#include "kernel/os/YunOS/os_common.h" +#include "kernel/os/YunOS/os_time.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* thread priority */ +#define OS_THREAD_PRIO_DRV_BH OS_PRIORITY_HIGH +#define OS_THREAD_PRIO_DRV_WORK OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_NET80211 OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_CTRL OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_WPAS OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_DRV_RX OS_PRIORITY_NORMAL +#define OS_THREAD_PRIO_LWIP OS_PRIORITY_NORMAL +#define OS_THREAD_PRIO_CONSOLE OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_SYS_CTRL OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_APP OS_PRIORITY_NORMAL + +#ifdef __CONFIG_ARCH_DUAL_CORE +#define OS_THREAD_PRIO_DUCC_APP_NORMAL OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_DUCC_APP_DATA OS_PRIORITY_NORMAL +#define OS_THREAD_PRIO_DUCC_NET_NORMAL OS_PRIORITY_ABOVE_NORMAL +#define OS_THREAD_PRIO_DUCC_NET_DATA OS_PRIORITY_NORMAL +#endif /* __CONFIG_ARCH_DUAL_CORE */ + + +typedef task_entry_t OS_ThreadEntry_t; +typedef void * OS_ThreadHandle_t; + +typedef struct OS_Thread { + OS_ThreadHandle_t handle; +} OS_Thread_t; + +static __inline OS_Status OS_ThreadCreate(OS_Thread_t *thread, const char *name, + OS_ThreadEntry_t entry, void *arg, + OS_Priority priority, uint32_t stackSize) +{ + if (RHINO_SUCCESS == krhino_task_dyn_create((ktask_t**)&thread->handle, name, arg, + priority, 0, stackSize/sizeof(cpu_stack_t), entry, 1u)) { + return OS_OK; + } else { + thread->handle = OS_INVALID_HANDLE; + return OS_FAIL; + } +} + +static __inline OS_Status OS_ThreadDelete(OS_Thread_t *thread) +{ + if (RHINO_SUCCESS == krhino_task_dyn_del(thread->handle)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline int OS_ThreadIsValid(OS_Thread_t *thread) +{ + return (thread->handle != OS_INVALID_HANDLE); +} + +static __inline void OS_ThreadSetInvalid(OS_Thread_t *thread) +{ + thread->handle = OS_INVALID_HANDLE; +} + +static __inline void OS_ThreadSuspendScheduler(void) +{ + krhino_sched_disable(); +} + +static __inline void OS_ThreadResumeScheduler(void) +{ + krhino_sched_enable(); +} + +static __inline void OS_ThreadSleep(OS_Time_t msec) +{ + krhino_task_sleep((tick_t)OS_MSecsToTicks(msec)); +} + +static __inline void OS_ThreadYield() +{ + krhino_task_yield(); +} + +static __inline OS_ThreadHandle_t OS_ThreadGetCurrentHandle(void) +{ + return (OS_ThreadHandle_t)krhino_cur_task_get(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_THREAD_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_time.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_time.h new file mode 100644 index 0000000000..6ba0ac5cfd --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_time.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_TIME_H_ +#define _KERNEL_OS_YUNOS_OS_TIME_H_ + +#include "kernel/os/YunOS/os_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Parameters of time */ +#define OS_MSEC_PER_SEC 1000UL +#define OS_USEC_PER_MSEC 1000UL +#define OS_USEC_PER_SEC 1000000UL + +/* system clock's frequency, ticks per second */ +#define OS_HZ RHINO_CONFIG_TICKS_PER_SECOND + +/* usec per tick (1000000 / OS_HZ) */ +#define OS_TICK (OS_USEC_PER_SEC / OS_HZ) + +/* The number of ticks since boot. */ +#define OS_GetTicks() ((uint32_t)(krhino_sys_tick_get() / OS_MSEC_PER_SEC)) + /* Due to portTICK_TYPE_IS_ATOMIC is 1, call xTaskGetTickCount() in ISR is safe also */ + +/* The number of seconds since boot. */ +#define OS_GetTime() (krhino_sys_time_get() / OS_HZ) + +/* Time conversion */ +#define OS_SecsToTicks(sec) ((uint32_t)(sec) * OS_HZ) +#define OS_MSecsToTicks(msec) ((uint32_t)(krhino_ms_to_ticks(msec))) +#define OS_TicksToMSecs(t) ((uint32_t)(krhino_ticks_to_ms(t))) +#define OS_TicksToSecs(t) ((uint32_t)((krhino_ticks_to_ms(t)) / OS_MSEC_PER_SEC)) + +#define OS_GetJiffies() OS_GetTicks() +#define OS_SecsToJiffies(sec) OS_SecsToTicks(sec) +#define OS_MSecsToJiffies(msec) OS_MSecsToTicks(msec) +#define OS_JiffiesToMSecs(j) OS_TicksToMSecs(j) +#define OS_JiffiesToSecs(j) OS_TicksToSecs(j) + +/* sleep */ +#define OS_MSleep(msec) krhino_task_sleep(krhino_ms_to_ticks(msec)) +#define OS_Sleep(sec) OS_MSleep((sec) * OS_MSEC_PER_SEC) +#define OS_SSleep(sec) OS_Sleep(sec) + +#define OS_TimeAfter(a, b) ((int32_t)(b) - (int32_t)(a) < 0) +#define OS_TimeBefore(a, b) OS_TimeAfter(b, a) +#define OS_TimeAfterEqual(a, b) ((int32_t)(a) - (int32_t)(b) >= 0) +#define OS_TimeBeforeEqual(a, b) OS_TimeAfterEqual(b, a) + +/* rand, read value from Cortex-M SYST_CVR register */ +#define OS_Rand32() \ + ((uint32_t)(((*((volatile uint32_t *)0xE000E018)) & 0xffffff) | \ + (OS_GetTicks() << 24))) + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_TIME_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/YunOS/os_timer.h b/platform/mcu/xr871/include/kernel/os/YunOS/os_timer.h new file mode 100644 index 0000000000..b1efe681b6 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/YunOS/os_timer.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _KERNEL_OS_YUNOS_OS_TIMER_H_ +#define _KERNEL_OS_YUNOS_OS_TIMER_H_ + +#include "kernel/os/YunOS/os_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OS_TIMER_ONCE = 0, + OS_TIMER_PERIODIC = 1 +} OS_TimerType; + +typedef void (*OS_TimerCallback_t)(void *arg); + +typedef struct OS_Timer { + void* handle; /* must be first */ + OS_TimerCallback_t cb; + OS_TimerType type; +} OS_Timer_t; + +static __inline void krhino_timer_cb(void *timer, void *arg) +{ + OS_Timer_t *tmr = timer; + tmr->cb(arg); +} + +kstat_t krhino_timer_dyn_create(ktimer_t **timer, const name_t *name, timer_cb_t cb, + tick_t first, tick_t round, void *arg, uint8_t auto_run); + +static __inline OS_Status OS_TimerCreate(OS_Timer_t *timer, OS_TimerType type, + OS_TimerCallback_t cb, void *ctx, OS_Time_t periodMS) +{ + tick_t first = krhino_ms_to_ticks((uint32_t)periodMS); + tick_t round = type == OS_TIMER_ONCE ? 0 : first; +#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0) + ktimer_t *timer_obj = NULL; + if (RHINO_SUCCESS == krhino_timer_dyn_create(&timer_obj, "UNDEF", krhino_timer_cb, + first, round, ctx, 1)) { + timer->handle = (void*)timer_obj; + timer->cb = cb; + timer->type = type; + return OS_OK; + } else { + timer->handle = NULL; + timer->cb = NULL; + return OS_FAIL; + } +#else + ktimer_t *timer_obj = = yoc_mm_alloc(sizeof(ktimer_t)); + if (timer_obj == NULL) { + return OS_FAIL; + } + + if (RHINO_SUCCESS == krhino_timer_create(timer_obj, "UNDEF", krhino_timer_cb, + first, round, ctx, 1)) { + timer->handle = (void*)timer_obj; + timer->cb = cb; + return OS_OK; + } else { + yoc_mm_free(timer_obj); + timer->handle = NULL; + timer->cb = NULL; + return OS_FAIL; + } + +#endif +} + +static __inline OS_Status OS_TimerDelete(OS_Timer_t *timer) +{ +#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0) + if (RHINO_SUCCESS == krhino_timer_dyn_del(timer->handle)) { + timer->handle = NULL; + timer->cb = NULL; + return OS_OK; + } else { + return OS_FAIL; + } +#else + if (RHINO_SUCCESS == krhino_timer_del(timer->handle)) { + yoc_mm_free(timer->handle); + timer->handle = NULL; + timer->cb = cb; + return OS_OK; + } else { + return OS_FAIL; + } +#endif +} + +static __inline OS_Status OS_TimerStart(OS_Timer_t *timer) +{ + if (RHINO_SUCCESS == krhino_timer_start(timer->handle)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_TimerChangePeriod(OS_Timer_t *timer, OS_Time_t periodMS) +{ + tick_t first = krhino_ms_to_ticks((uint32_t)periodMS); + tick_t round = timer->type == OS_TIMER_ONCE ? 0 : first; + if (RHINO_SUCCESS == krhino_timer_change(timer->handle, first, round)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline OS_Status OS_TimerStop(OS_Timer_t *timer) +{ + if (RHINO_SUCCESS == krhino_timer_stop(timer->handle)) { + return OS_OK; + } else { + return OS_FAIL; + } +} + +static __inline int OS_TimerIsValid(OS_Timer_t *timer) +{ + return (timer->handle != OS_INVALID_HANDLE); +} + +static __inline void OS_TimerSetInvalid(OS_Timer_t *timer) +{ + timer->handle = OS_INVALID_HANDLE; +} + +static __inline void *OS_TimerGetContext(void *arg) +{ + return arg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _KERNEL_OS_YUNOS_OS_TIMER_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os.h b/platform/mcu/xr871/include/kernel/os/os.h new file mode 100644 index 0000000000..fc2d719018 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_H_ +#define _KERNEL_OS_OS_H_ + +#include "kernel/os/os_time.h" +#include "kernel/os/os_thread.h" +#include "kernel/os/os_queue.h" +#include "kernel/os/os_semaphore.h" +#include "kernel/os/os_mutex.h" +#include "kernel/os/os_timer.h" +#include "kernel/os/os_time.h" +#include "kernel/os/os_errno.h" + + +#endif /* _KERNEL_OS_OS_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_common.h b/platform/mcu/xr871/include/kernel/os/os_common.h new file mode 100644 index 0000000000..df6465cf25 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_common.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_COMMON_H_ +#define _KERNEL_OS_OS_COMMON_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_common.h" +#else +#error "No OS defined!" +#endif + +#endif diff --git a/platform/mcu/xr871/include/kernel/os/os_errno.h b/platform/mcu/xr871/include/kernel/os/os_errno.h new file mode 100644 index 0000000000..e4bf47dc62 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_errno.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_ERRNO_H_ +#define _KERNEL_OS_OS_ERRNO_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_errno.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_ERRNO_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_mutex.h b/platform/mcu/xr871/include/kernel/os/os_mutex.h new file mode 100644 index 0000000000..391e65a917 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_mutex.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_MUTEX_H_ +#define _KERNEL_OS_OS_MUTEX_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_time.h" +#include "kernel/os/YunOS/os_mutex.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_MUTEX_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_queue.h b/platform/mcu/xr871/include/kernel/os/os_queue.h new file mode 100644 index 0000000000..860d6d7c40 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_queue.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_QUEUE_H_ +#define _KERNEL_OS_OS_QUEUE_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_queue.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_QUEUE_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_semaphore.h b/platform/mcu/xr871/include/kernel/os/os_semaphore.h new file mode 100644 index 0000000000..e9d7f5b463 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_semaphore.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_SEMAPHORE_H_ +#define _KERNEL_OS_OS_SEMAPHORE_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_semaphore.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_SEMAPHORE_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_thread.h b/platform/mcu/xr871/include/kernel/os/os_thread.h new file mode 100644 index 0000000000..e22dc75e5b --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_thread.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_THREAD_H_ +#define _KERNEL_OS_OS_THREAD_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_thread.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_THREAD_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_time.h b/platform/mcu/xr871/include/kernel/os/os_time.h new file mode 100644 index 0000000000..865ff568ef --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_time.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_TIME_H_ +#define _KERNEL_OS_OS_TIME_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_time.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_TIME_H_ */ diff --git a/platform/mcu/xr871/include/kernel/os/os_timer.h b/platform/mcu/xr871/include/kernel/os/os_timer.h new file mode 100644 index 0000000000..8998b623c0 --- /dev/null +++ b/platform/mcu/xr871/include/kernel/os/os_timer.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _KERNEL_OS_OS_TIMER_H_ +#define _KERNEL_OS_OS_TIMER_H_ + +#if defined (__CONFIG_OS_USE_YUNOS) +#include "kernel/os/YunOS/os_timer.h" +#else +#error "No OS defined!" +#endif + +#endif /* _KERNEL_OS_OS_TIMER_H_ */ diff --git a/platform/mcu/xr871/include/libc/errno.h b/platform/mcu/xr871/include/libc/errno.h new file mode 100644 index 0000000000..b848aacffa --- /dev/null +++ b/platform/mcu/xr871/include/libc/errno.h @@ -0,0 +1,180 @@ +#ifndef _LIBC_ERRNO_H_ +#define _LIBC_ERRNO_H_ + +#include "kernel/os/os_errno.h" + +#define errno OS_GetErrno() + + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#define ECANCELED 125 /* Operation Canceled */ +#define ENOKEY 126 /* Required key not available */ +#define EKEYEXPIRED 127 /* Key has expired */ +#define EKEYREVOKED 128 /* Key has been revoked */ +#define EKEYREJECTED 129 /* Key was rejected by service */ + +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + +#define ERFKILL 132 /* Operation not possible due to RF-kill */ + +#define EHWPOISON 133 /* Memory page has hardware error */ + + +/* + * These should never be seen by user programs. To return one of ERESTART* + * codes, signal_pending() MUST be set. Note that ptrace can observe these + * at syscall exit tracing, but they will never be left for the debugged user + * process to see. + */ +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ +#define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */ +#define EPROBE_DEFER 517 /* Driver requests probe retry */ +#define EOPENSTALE 518 /* open found a stale dentry */ + +/* Defined for the NFSv3 protocol */ +#define EBADHANDLE 521 /* Illegal NFS file handle */ +#define ENOTSYNC 522 /* Update synchronization mismatch */ +#define EBADCOOKIE 523 /* Cookie is stale */ +#define ENOTSUPP 524 /* Operation is not supported */ +#define ETOOSMALL 525 /* Buffer or request is too small */ +#define ESERVERFAULT 526 /* An untranslatable error occurred */ +#define EBADTYPE 527 /* Type not supported by server */ +#define EJUKEBOX 528 /* Request initiated, but will not complete before timeout */ +#define EIOCBQUEUED 529 /* iocb queued, will get completion event */ + +/* alias */ +#define ENOTSUP EOPNOTSUPP /* Operation not supported */ + +#endif /* _LIBC_ERRNO_H_ */ diff --git a/platform/mcu/xr871/include/libc/sys/features.h b/platform/mcu/xr871/include/libc/sys/features.h new file mode 100644 index 0000000000..5b314bc263 --- /dev/null +++ b/platform/mcu/xr871/include/libc/sys/features.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * In order to redefine int32_t to int when compiles using GCC, this file is + * added to override of GCC. + */ + +#ifndef _LIBC_SYS_FEATURES_H_ +#define _LIBC_SYS_FEATURES_H_ + +#ifdef __CONFIG_LIBC_REDEFINE_GCC_INT32_TYPE + +/* + * Redefine some macros defined by GCC + */ +#ifdef __INT32_MAX__ +#undef __INT32_MAX__ +#endif +#define __INT32_MAX__ 2147483647 + +#ifdef __UINT32_MAX__ +#undef __UINT32_MAX__ +#endif +#define __UINT32_MAX__ 4294967295U + +#ifdef __INT_LEAST32_MAX__ +#undef __INT_LEAST32_MAX__ +#endif +#define __INT_LEAST32_MAX__ 2147483647 + +#ifdef __UINT_LEAST32_MAX__ +#undef __UINT_LEAST32_MAX__ +#endif +#define __UINT_LEAST32_MAX__ 4294967295U + +#ifdef __INT_LEAST32_TYPE__ +#undef __INT_LEAST32_TYPE__ +#endif +#define __INT_LEAST32_TYPE__ int + +#ifdef __UINT_LEAST32_TYPE__ +#undef __UINT_LEAST32_TYPE__ +#endif +#define __UINT_LEAST32_TYPE__ unsigned int + +#ifdef __INT32_C +#undef __INT32_C +#endif +#define __INT32_C(c) c + +#ifdef __UINT32_C +#undef __UINT32_C +#endif +#define __UINT32_C(c) c ## U + +#ifdef __INT32_TYPE__ +#undef __INT32_TYPE__ +#endif +#define __INT32_TYPE__ int + +#ifdef __UINT32_TYPE__ +#undef __UINT32_TYPE__ +#endif +#define __UINT32_TYPE__ unsigned int + +#endif /* __CONFIG_LIBC_REDEFINE_GCC_INT32_TYPE */ + +/* + * Include of compiler + */ +#include_next + +#endif /* _LIBC_SYS_FEATURES_H_ */ diff --git a/platform/mcu/xr871/include/net/lwip/arch/cc.h b/platform/mcu/xr871/include/net/lwip/arch/cc.h new file mode 100644 index 0000000000..258c7c1842 --- /dev/null +++ b/platform/mcu/xr871/include/net/lwip/arch/cc.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_CC_H__ +#define __ARCH_CC_H__ + + +#include +#include +#include + +#include "types.h" +#include "sys/defs.h" + +/* Types based on stdint.h */ +typedef uint8_t u8_t; +typedef int8_t s8_t; +typedef uint16_t u16_t; +typedef int16_t s16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef uintptr_t mem_ptr_t; + +//#define LWIP_COMPAT_MUTEX 1 +#define LWIP_MAILBOX_QUEUE 1 + +#define LWIP_TIMEVAL_PRIVATE 0 + +#define LWIP_NO_INTTYPES_H 1 + +/* Define (sn)printf formatters for these lwIP types */ +#if LWIP_NO_INTTYPES_H +#define X8_F "02x" +#define U16_F "hu" +#define S16_F "hd" +#define X16_F "hx" +#define U32_F "u" +#define S32_F "d" +#define X32_F "x" +#define SZT_F "uz" +#endif + +/* Define platform endianness */ +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif /* BYTE_ORDER */ + + +#if (defined(__GNUC__)) + /* GNU Compiler */ + #define PACK_STRUCT_BEGIN + #define PACK_STRUCT_STRUCT __attribute__((__packed__)) + #define PACK_STRUCT_END + #define PACK_STRUCT_FIELD(fld) fld + #define ALIGNED(n) __attribute__((aligned (n))) +#elif defined(__CC_ARM) + /* ARM Compiler */ + #define PACK_STRUCT_BEGIN __packed + #define PACK_STRUCT_STRUCT + #define PACK_STRUCT_END + #define PACK_STRUCT_FIELD(fld) fld + #define ALIGNED(n) __align(n) +#else + #error "Compiler not supported." +#endif + +/* Provide Thumb-2 routines for GCC to improve performance */ +#if defined(__GNUC__) && defined(__thumb2__) + #define MEMCPY(dst,src,len) thumb2_memcpy(dst,src,len) + #define SMEMCPY(dst,src,len) thumb2_memcpy(dst,src,len) + #define LWIP_CHKSUM thumb2_checksum + /* Set algorithm to 0 so that unused lwip_standard_chksum function + doesn't generate compiler warning */ + #define LWIP_CHKSUM_ALGORITHM 0 + + void thumb2_memcpy(void* pDest, const void* pSource, size_t length); + u16_t thumb2_checksum(void* pData, int length); +#else + #include + #define MEMCPY(dst,src,len) memcpy(dst,src,len) + #define SMEMCPY(dst,src,len) memcpy(dst,src,len) + /* Used with IP headers only */ + #define LWIP_CHKSUM_ALGORITHM 1 +#endif + + +#include + +#ifdef NDEBUG +#define LWIP_NOASSERT +#else // Assertions enabled + +// If assertions are on, the default LWIP_ERROR handler behaviour is to +// abort w/ an assertion failure. Don't do this, instead just print the error (if LWIP_DEBUG is set) +// and run the handler (same as the LWIP_ERROR behaviour if LWIP_NOASSERT is set). +#ifdef LWIP_DEBUG +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + puts(message); handler;}} while(0) +#else +// If LWIP_DEBUG is not set, return the error silently (default LWIP behaviour, also.) +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + handler;}} while(0) +#endif // LWIP_DEBUG + +#endif /* NDEBUG */ + +/* Plaform specific diagnostic output */ +#define LWIP_PLATFORM_DIAG(x) do {printf x;} while(0) +#define LWIP_PLATFORM_ASSERT(x) \ + do { \ + printf("%s at line %d in %s\n", x, __LINE__, __FILE__); \ + } while(0) + +#include "kernel/os/os_time.h" +#define LWIP_RAND() OS_Rand32() + +#include "sys/endian.h" +#define LWIP_PLATFORM_BYTESWAP 1 +#define LWIP_PLATFORM_HTONS(x) htobe16(x) //__REV16(x) +#define LWIP_PLATFORM_HTONL(x) htobe32(x) //__REV(x) + +#include "compiler.h" +#define LWIP_INLINE __inline + +#endif /* __ARCH_CC_H__ */ diff --git a/platform/mcu/xr871/include/net/lwip/lwipopts.h b/platform/mcu/xr871/include/net/lwip/lwipopts.h new file mode 100644 index 0000000000..294f234fb3 --- /dev/null +++ b/platform/mcu/xr871/include/net/lwip/lwipopts.h @@ -0,0 +1,2341 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#if !defined LWIP_HDR_LWIPOPTS_H +#define LWIP_HDR_LWIPOPTS_H + +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you don't like! + */ + +/** + * @defgroup lwip_opts Options (lwipopts.h) + * @ingroup lwip + * + * @defgroup lwip_opts_debug Debugging + * @ingroup lwip_opts + * + * @defgroup lwip_opts_infrastructure Infrastructure + * @ingroup lwip_opts + * + * @defgroup lwip_opts_callback Callback-style APIs + * @ingroup lwip_opts + * + * @defgroup lwip_opts_threadsafe_apis Thread-safe APIs + * @ingroup lwip_opts + */ + +/* + -------------------------------------------------- + ---------- New options added for XRadio ---------- + -------------------------------------------------- +*/ + +#define LWIP_XR_IMPL 1 // XRadio's implementation +#define LWIP_XR_MEM 0 // XRadio's implementation of memory +#define LWIP_XR_DEINIT 0 // LwIP deinit +#define LWIP_SUPPRESS_WARNING 1 +#define LWIP_RESOURCE_TRACE 0 // trace resource usage for debugging +#define LWIP_MBOX_TRACE 0 // trace mbox usage for debugging + +/** + * LWIP_MBUF_SUPPORT==1: Reserve some head/tail space in pbuf for adding data, + * which used by mbuf. + */ +#define LWIP_MBUF_SUPPORT __CONFIG_MBUF_IMPL_MODE +#if LWIP_MBUF_SUPPORT +#define LWIP_PBUF_POOL_SMALL 1 // add small PBUF_POOL_SMALL to save memory +#endif /* LWIP_MBUF_SUPPORT */ + +/* + ------------------------------------ + ---------- Packet options ---------- + ------------------------------------ +*/ +/** + * LWIP_PACKET==1: Enable application layer to access datalink directly. + */ +#define LWIP_PACKET 0 + +/** + * DEFAULT_PKT_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_PKT. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_PKT_RECVMBOX_SIZE 4 + +/** + * MEMP_NUM_PKT_PCB: Number of packet connection PCBs + * (requires the LWIP_PACKET option) + */ +#define MEMP_NUM_PKT_PCB 2 + +/** + * PKT_DEBUG: Enable debugging in packet.c. + */ +#define PKT_DEBUG LWIP_DBG_OFF + +/* + ------------------------------------ + -------------- NO SYS -------------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_nosys NO_SYS + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * NO_SYS==1: Use lwIP without OS-awareness (no thread, semaphores, mutexes or + * mboxes). This means threaded APIs cannot be used (socket, netconn, + * i.e. everything in the 'api' folder), only the callback-style raw API is + * available (and you have to watch out for yourself that you don't access + * lwIP functions/structures from more than one context at a time!) + */ +#define NO_SYS 0 +/** + * @} + */ + +/** + * @defgroup lwip_opts_timers Timers + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_TIMERS==0: Drop support for sys_timeout and lwip-internal cyclic timers. + * (the array of lwip-internal cyclic timers is still provided) + * (check NO_SYS_NO_TIMERS for compatibility to old versions) + */ +#define LWIP_TIMERS 1 + +/** + * LWIP_TIMERS_CUSTOM==1: Provide your own timer implementation. + * Function prototypes in timeouts.h and the array of lwip-internal cyclic timers + * are still included, but the implementation is not. The following functions + * will be required: sys_timeouts_init(), sys_timeout(), sys_untimeout(), + * sys_timeouts_mbox_fetch() + */ +#define LWIP_TIMERS_CUSTOM 0 +/** + * @} + */ + +/** + * @defgroup lwip_opts_memcpy memcpy + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +// define in +//#define MEMCPY(dst,src,len) memcpy(dst,src,len) + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +// define in +//#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +/** + * @} + */ + +/* + ------------------------------------ + ----------- Core locking ----------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_lock Core locking and MPU + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_MPU_COMPATIBLE: enables special memory management mechanism + * which makes lwip able to work on MPU (Memory Protection Unit) system + * by not passing stack-pointers to other threads + * (this decreases performance as memory is allocated from pools instead + * of keeping it on the stack) + */ +#define LWIP_MPU_COMPATIBLE 0 + +/** + * LWIP_TCPIP_CORE_LOCKING + * Creates a global mutex that is held during TCPIP thread operations. + * Can be locked by client code to perform lwIP operations without changing + * into TCPIP thread using callbacks. See LOCK_TCPIP_CORE() and + * UNLOCK_TCPIP_CORE(). + * Your system should provide mutexes supporting priority inversion to use this. + */ +#define LWIP_TCPIP_CORE_LOCKING 0 // ??? + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: when LWIP_TCPIP_CORE_LOCKING is enabled, + * this lets tcpip_input() grab the mutex for input packets as well, + * instead of allocating a message and passing it to tcpip_thread. + * + * ATTENTION: this does not work when tcpip_input() is called from + * interrupt context! + */ +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 + +/** + * SYS_LIGHTWEIGHT_PROT==1: enable inter-task protection (and task-vs-interrupt + * protection) for certain critical regions during buffer allocation, deallocation + * and memory allocation and deallocation. + * ATTENTION: This is required when using lwIP from more than one context! If + * you disable this, you must be sure what you are doing! + */ +#define SYS_LIGHTWEIGHT_PROT 1 +/** + * @} + */ + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_mem Heap and memory pools + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#define MEM_LIBC_MALLOC LWIP_XR_MEM + +/** + * MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. + * Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution + * speed (heap alloc can be much slower than pool alloc) and usage from interrupts + * (especially if your netif driver allocates PBUF_POOL pbufs for received frames + * from interrupt)! + * ATTENTION: Currently, this uses the heap for ALL pools (also for private pools, + * not only for internal pools defined in memp_std.h)! + */ +#define MEMP_MEM_MALLOC LWIP_XR_MEM + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> \#define MEM_ALIGNMENT 4 + * 2 byte alignment -> \#define MEM_ALIGNMENT 2 + */ +#define MEM_ALIGNMENT 4 + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#define MEM_SIZE (24 * 1024) + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#define MEMP_OVERFLOW_CHECK 0 + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#define MEMP_SANITY_CHECK 0 + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#define MEM_USE_POOLS 0 + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * include path somewhere. + */ +#define MEMP_USE_CUSTOM_POOLS 0 + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1 +/** + * @} + */ + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * @defgroup lwip_opts_memp Internal memory pools + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#define MEMP_NUM_PBUF 6 + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#define MEMP_NUM_RAW_PCB 2 + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#define MEMP_NUM_UDP_PCB 10 + +/** + * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB 8 + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB_LISTEN 2 + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_SEG 24 + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#define MEMP_NUM_REASSDATA 2 + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 + * with DMA-enabled MACs where the packet is not yet sent when netif->output + * returns. + */ +#define MEMP_NUM_FRAG_PBUF 2 + +/** + * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#define MEMP_NUM_ARP_QUEUE 16 + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members at the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#define MEMP_NUM_IGMP_GROUP 3 + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts. + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#define MEMP_NUM_NETBUF 10 + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#define MEMP_NUM_NETCONN 20 + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#define MEMP_NUM_TCPIP_MSG_API 4 + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#define MEMP_NUM_TCPIP_MSG_INPKT 16 + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#define MEMP_NUM_NETDB 1 + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#define MEMP_NUM_LOCALHOSTLIST 1 + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#if (MEMP_MEM_MALLOC && LWIP_XR_MEM) +#define PBUF_POOL_SIZE 14 +#else +#define PBUF_POOL_SIZE 8 +#endif + +/** MEMP_NUM_API_MSG: the number of concurrently active calls to various + * socket, netconn, and tcpip functions + */ +#define MEMP_NUM_API_MSG MEMP_NUM_TCPIP_MSG_API // ??? + +/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname + */ +#define MEMP_NUM_DNS_API_MSG MEMP_NUM_TCPIP_MSG_API // ??? + +/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls + * to getsockopt/setsockopt + */ +#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API // ??? + +/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the + * netifapi functions + */ +#define MEMP_NUM_NETIFAPI_MSG MEMP_NUM_TCPIP_MSG_API // ??? +/** + * @} + */ + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_arp ARP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#define LWIP_ARP 1 + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#define ARP_TABLE_SIZE 8 + +/** the time an ARP entry stays valid after its last update, + * for ARP_TMR_INTERVAL = 1000, this is + * (60 * 5) seconds = 5 minutes. + */ +#define ARP_MAXAGE 300 // ??? + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#define ARP_QUEUEING 1 + +/** The maximum number of packets which may be queued for each + * unresolved address by other network layers. Defaults to 3, 0 means disabled. + * Old packets are dropped, new packets are queued. + */ +#define ARP_QUEUE_LEN 3 // ??? + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with + * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and + * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#define ETHARP_SUPPORT_VLAN 0 + +/** LWIP_ETHERNET==1: enable ethernet support even though ARP might be disabled + */ +#define LWIP_ETHERNET LWIP_ARP + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#define ETH_PAD_SIZE 0 + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 + +/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries. + * If disabled, duplicate IP address on multiple netifs are not supported + * (but this should only occur for AutoIP). + */ +#define ETHARP_TABLE_MATCH_NETIF 0 // ??? +/** + * @} + */ + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * @defgroup lwip_opts_ipv4 IPv4 + * @ingroup lwip_opts + * @{ + */ +/** + * LWIP_IPV4==1: Enable IPv4 + */ +#define LWIP_IPV4 1 + +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#define IP_FORWARD 0 + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#define IP_REASSEMBLY 1 + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#define IP_FRAG 1 + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#define IP_OPTIONS_ALLOWED 1 + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#define IP_REASS_MAXAGE 3 + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#define IP_REASS_MAX_PBUFS 4 + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#define IP_DEFAULT_TTL 255 + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#define IP_SOF_BROADCAST 1 + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#define IP_SOF_BROADCAST_RECV 1 + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +/** + * @} + */ + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_icmp ICMP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#define LWIP_ICMP 1 + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#define ICMP_TTL (IP_DEFAULT_TTL) + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#define LWIP_BROADCAST_PING 0 + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#define LWIP_MULTICAST_PING 0 +/** + * @} + */ + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_raw RAW + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#define LWIP_RAW 1 + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#define RAW_TTL (IP_DEFAULT_TTL) +/** + * @} + */ + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_dhcp DHCP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#define LWIP_DHCP 1 + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) + +/** + * LWIP_DHCP_CHECK_LINK_UP==1: dhcp_start() only really starts if the netif has + * NETIF_FLAG_LINK_UP set in its flags. As this is only an optimization and + * netif drivers might not set this flag, the default is off. If enabled, + * netif_set_link_up() must be called to continue dhcp starting. + */ +#define LWIP_DHCP_CHECK_LINK_UP 1 // ??? + +/** + * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name. + */ +#define LWIP_DHCP_BOOTP_FILE 0 // ??? + +/** + * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each + * response packet, an callback is called, which has to be provided by the port: + * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs); +*/ +#define LWIP_DHCP_GET_NTP_SRV 0 // ??? + +/** + * The maximum of NTP servers requested + */ +#define LWIP_DHCP_MAX_NTP_SERVERS 1 // ??? + +/** + * LWIP_DHCP_MAX_DNS_SERVERS > 0: Request DNS servers with discover/select. + * DHCP servers received in the response are passed to DNS via @ref dns_setserver() + * (up to the maximum limit defined here). + */ +#define LWIP_DHCP_MAX_DNS_SERVERS DNS_MAX_SERVERS // ??? +/** + * @} + */ + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_autoip AUTOIP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#define LWIP_AUTOIP 0 + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#define LWIP_DHCP_AUTOIP_COOP 0 + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP (the DHCP client keeps + * running in this case). This can be set as low as 1 to get an AutoIP address + * very quickly, but you should be prepared to handle a changing IP address + * when DHCP overrides AutoIP. + */ +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +/** + * @} + */ + +/* + ---------------------------------- + ----- SNMP MIB2 support ----- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_mib2 SNMP MIB2 callbacks + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks. + * Turn this on to get callbacks needed to implement MIB2. + * Usually MIB2_STATS should be enabled, too. + */ +#define LWIP_MIB2_CALLBACKS 0 +/** + * @} + */ + +/* + ---------------------------------- + ----- Multicast/IGMP options ----- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_igmp IGMP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#define LWIP_IGMP 1 + +/** + * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options + * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP + */ +#define LWIP_MULTICAST_TX_OPTIONS (LWIP_IGMP && LWIP_UDP) +/** + * @} + */ + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_dns DNS + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#define LWIP_DNS 1 + +/** DNS maximum number of entries to maintain locally. */ +#define DNS_TABLE_SIZE 3 + +/** DNS maximum host name length supported in the name table. */ +#define DNS_MAX_NAME_LENGTH 256 + +/** The maximum of DNS servers + * The first server can be initialized automatically by defining + * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*' + */ +#define DNS_MAX_SERVERS 2 + +/** DNS do a name checking between the query and the response. */ +#define DNS_DOES_NAME_CHECK 1 + +/** LWIP_DNS_SECURE: controls the security level of the DNS implementation + * Use all DNS security features by default. + * This is overridable but should only be needed by very small targets + * or when using against non standard DNS servers. */ +#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) // ??? + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, you have to define an initializer: + * \#define DNS_LOCAL_HOSTLIST_INIT {DNS_LOCAL_HOSTLIST_ELEM("host_ip4", IPADDR4_INIT_BYTES(1,2,3,4)), \ + * DNS_LOCAL_HOSTLIST_ELEM("host_ip6", IPADDR6_INIT_HOST(123, 234, 345, 456)} + * + * Instead, you can also use an external function: + * \#define DNS_LOOKUP_LOCAL_EXTERN(x) extern err_t my_lookup_function(const char *name, ip_addr_t *addr, u8_t dns_addrtype) + * that looks up the IP address and returns ERR_OK if found (LWIP_DNS_ADDRTYPE_xxx is passed in dns_addrtype). + */ +#define DNS_LOCAL_HOSTLIST 0 + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 + +/** Set this to 1 to enable querying ".local" names via mDNS + * using a One-Shot Multicast DNS Query */ +#define LWIP_DNS_SUPPORT_MDNS_QUERIES 0 // ??? +/** + * @} + */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_udp UDP + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#define LWIP_UDP 1 + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#define LWIP_UDPLITE 0 + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#define UDP_TTL (IP_DEFAULT_TTL) + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#define LWIP_NETBUF_RECVINFO 0 +/** + * @} + */ + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_tcp TCP + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#define LWIP_TCP 1 + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#define TCP_TTL (IP_DEFAULT_TTL) + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well. + * ATTENTION: when using TCP_RCV_SCALE, TCP_WND is the total size + * with scaling applied. Maximum window value in the TCP header + * will be TCP_WND >> TCP_RCV_SCALE + */ +#define TCP_WND (4 * TCP_MSS) + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#define TCP_MAXRTX 12 + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#define TCP_SYNMAXRTX 6 + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#define TCP_MSS 1460 + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#define TCP_CALCULATE_EFF_SEND_MSS 1 + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#define TCP_SND_BUF (2 * TCP_MSS) + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==1. + */ +#define TCP_OOSEQ_MAX_BYTES 0 + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==1. + */ +#define TCP_OOSEQ_MAX_PBUFS 0 + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#define TCP_LISTEN_BACKLOG 1 + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#define TCP_OVERSIZE TCP_MSS + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + * The timestamp option is currently only used to help remote hosts, it is not + * really used locally. Therefore, it is only enabled when a TS option is + * received in the initial SYN packet from a remote host. + */ +#define LWIP_TCP_TIMESTAMPS 0 + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#define TCP_WND_UPDATE_THRESHOLD LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4)) + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 + +/** + * LWIP_WND_SCALE and TCP_RCV_SCALE: + * Set LWIP_WND_SCALE to 1 to enable window scaling. + * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the + * range of [0..14]). + * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large + * send window while having a small receive window only. + */ +#define LWIP_WND_SCALE 0 // ??? +#define TCP_RCV_SCALE 0 // ??? +/** + * @} + */ + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_pbuf PBUF + * @ingroup lwip_opts + * @{ + */ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#if defined LWIP_HOOK_VLAN_SET +#define PBUF_LINK_HLEN (18 + ETH_PAD_SIZE) +#else /* LWIP_HOOK_VLAN_SET */ +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif /* LWIP_HOOK_VLAN_SET */ + +/** + * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated + * for an additional encapsulation header before ethernet headers (e.g. 802.11) + */ +#define PBUF_LINK_ENCAPSULATION_HLEN 0u + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accommodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN) +/** + * @} + */ + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * @defgroup lwip_opts_netif NETIF + * @ingroup lwip_opts + * @{ + */ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#define LWIP_NETIF_HOSTNAME 1 + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#define LWIP_NETIF_API 1 + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquisition) + */ +#define LWIP_NETIF_STATUS_CALLBACK 1 + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#define LWIP_NETIF_LINK_CALLBACK 1 + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#define LWIP_NETIF_REMOVE_CALLBACK 0 + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#define LWIP_NETIF_HWADDRHINT 0 + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#define LWIP_NETIF_TX_SINGLE_PBUF 0 + +/** + * LWIP_NUM_NETIF_CLIENT_DATA: Number of clients that may store + * data in client_data member array of struct netif. + */ +#define LWIP_NUM_NETIF_CLIENT_DATA 0 // ??? +/** + * @} + */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_loop Loopback interface + * @ingroup lwip_opts_netif + * @{ + */ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1). + * This is only needed when no real netifs are available. If at least one other + * netif is available, loopback traffic uses this netif. + */ +#define LWIP_HAVE_LOOPIF 1 + +/** + * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1). + */ +#define LWIP_LOOPIF_MULTICAST 0 + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#define LWIP_NETIF_LOOPBACK 1 + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#define LWIP_LOOPBACK_MAX_PBUFS 0 + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +/** + * @} + */ + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_thread Threading + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#define TCPIP_THREAD_NAME "tcpip" + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define TCPIP_THREAD_STACKSIZE (2 * 1024) + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define TCPIP_THREAD_PRIO (9) + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#define TCPIP_MBOX_SIZE 32 + +/** + * Define this to something that triggers a watchdog. This is called from + * tcpip_thread after processing a message. + */ +#define LWIP_TCPIP_THREAD_ALIVE() + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#define SLIPIF_THREAD_NAME "slipif_loop" + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define SLIPIF_THREAD_STACKSIZE (4 * 1024) + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define SLIPIF_THREAD_PRIO (TCPIP_THREAD_PRIO) + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#define DEFAULT_THREAD_NAME "lwIP" + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define DEFAULT_THREAD_STACKSIZE (4 * 1024) + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define DEFAULT_THREAD_PRIO (TCPIP_THREAD_PRIO) + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_RAW_RECVMBOX_SIZE 4 + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_UDP_RECVMBOX_SIZE 8 + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_TCP_RECVMBOX_SIZE 8 + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#define DEFAULT_ACCEPTMBOX_SIZE 4 +/** + * @} + */ + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * @defgroup lwip_opts_netconn Netconn + * @ingroup lwip_opts_threadsafe_apis + * @{ + */ +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 1 + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create + * timers running in tcpip_thread from another thread. + */ +#define LWIP_TCPIP_TIMEOUT 0 + +/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per + * thread calling socket/netconn functions instead of allocating one + * semaphore per netconn (and per select etc.) + * ATTENTION: a thread-local semaphore for API calls is needed: + * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t* + * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore + * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore + * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup(). + * Ports may call these for threads created with sys_thread_new(). + */ +#define LWIP_NETCONN_SEM_PER_THREAD 0 // ???, set to 1 + +/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread, + * writing from a 2nd thread and closing from a 3rd thread at the same time. + * ATTENTION: This is currently really alpha! Some requirements: + * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from + * multiple threads at once + * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox + * and prevent a task pending on this during/after deletion + */ +#define LWIP_NETCONN_FULLDUPLEX 0 +/** + * @} + */ + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_socket Sockets + * @ingroup lwip_opts_threadsafe_apis + * @{ + */ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 1 + +/* LWIP_SOCKET_SET_ERRNO==1: Set errno when socket functions cannot complete + * successfully, as required by POSIX. Default is POSIX-compliant. + */ +#define LWIP_SOCKET_SET_ERRNO 1 // ??? + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines. + * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created. + * While this helps code completion, it might conflict with existing libraries. + * (only used if you use sockets.c) + */ +#define LWIP_COMPAT_SOCKETS 1 + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 + +/** + * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n. + * This can be useful when there are multiple APIs which create file descriptors. + * When they all start with a different offset and you won't make them overlap you can + * re implement read/write/close/ioctl/fnctl to send the requested action to the right + * library (sharing select will need more work though). + */ +#define LWIP_SOCKET_OFFSET 0 // ??? + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#define LWIP_TCP_KEEPALIVE 1 + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#define LWIP_SO_SNDTIMEO 1 + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#define LWIP_SO_RCVTIMEO 1 + +/** + * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int + * (milliseconds, much like winsock does) instead of a struct timeval (default). + */ +#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0 + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#define LWIP_SO_RCVBUF 0 + +/** + * LWIP_SO_LINGER==1: Enable SO_LINGER processing. + */ +#define LWIP_SO_LINGER 0 // ??? + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#define RECV_BUFSIZE_DEFAULT INT_MAX // ??? + +/** + * By default, TCP socket/netconn close waits 20 seconds max to send the FIN + */ +#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000 + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#define SO_REUSE 1 + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#define SO_REUSE_RXTOALL 0 + +/** + * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of + * pending data in the network buffer. This is the way windows does it. It's + * the default for lwIP since it is smaller. + * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next + * pending datagram in bytes. This is the way linux does it. This code is only + * here for compatibility. + */ +#define LWIP_FIONREAD_LINUXMODE 0 // ??? +/** + * @} + */ + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * @defgroup lwip_opts_stats Statistics + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#define LWIP_STATS 1 // ??? + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#define LWIP_STATS_DISPLAY 0 + +/** + * LINK_STATS==1: Enable link stats. + */ +#define LINK_STATS 1 + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#define ETHARP_STATS (LWIP_ARP) + +/** + * IP_STATS==1: Enable IP stats. + */ +#define IP_STATS 1 + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#define ICMP_STATS 1 + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#define IGMP_STATS (LWIP_IGMP) + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#define UDP_STATS (LWIP_UDP) + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#define TCP_STATS (LWIP_TCP) + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#define SYS_STATS (NO_SYS == 0) + +/** + * IP6_STATS==1: Enable IPv6 stats. + */ +#define IP6_STATS (LWIP_IPV6) + +/** + * ICMP6_STATS==1: Enable ICMP for IPv6 stats. + */ +#define ICMP6_STATS (LWIP_IPV6 && LWIP_ICMP6) + +/** + * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats. + */ +#define IP6_FRAG_STATS (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS)) + +/** + * MLD6_STATS==1: Enable MLD for IPv6 stats. + */ +#define MLD6_STATS (LWIP_IPV6 && LWIP_IPV6_MLD) + +/** + * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats. + */ +#define ND6_STATS (LWIP_IPV6) + +/** + * MIB2_STATS==1: Stats for SNMP MIB2. + */ +#define MIB2_STATS 1 + +#else /* LWIP_STATS */ + +#define LINK_STATS 0 +#define ETHARP_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 +#define IP6_STATS 0 +#define ICMP6_STATS 0 +#define IP6_FRAG_STATS 0 +#define MLD6_STATS 0 +#define ND6_STATS 0 +#define MIB2_STATS 0 + +#endif /* LWIP_STATS */ +/** + * @} + */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * @defgroup lwip_opts_checksum Checksum + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled + * per netif. + * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled! + */ +#define LWIP_CHECKSUM_CTRL_PER_NETIF 0 // ??? + +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#define CHECKSUM_GEN_IP 1 + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#define CHECKSUM_GEN_UDP 1 + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#define CHECKSUM_GEN_TCP 1 + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#define CHECKSUM_GEN_ICMP 1 + +/** + * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets. + */ +#define CHECKSUM_GEN_ICMP6 1 + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#define CHECKSUM_CHECK_IP 1 + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#define CHECKSUM_CHECK_UDP 1 + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#define CHECKSUM_CHECK_TCP 1 + +/** + * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets. + */ +#define CHECKSUM_CHECK_ICMP 1 + +/** + * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets + */ +#define CHECKSUM_CHECK_ICMP6 1 + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#define LWIP_CHECKSUM_ON_COPY 0 +/** + * @} + */ + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +*/ +/** + * @defgroup lwip_opts_ipv6 IPv6 + * @ingroup lwip_opts + * @{ + */ +/** + * LWIP_IPV6==1: Enable IPv6 + */ +#define LWIP_IPV6 0 + +/** + * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif. + */ +#define LWIP_IPV6_NUM_ADDRESSES 3 + +/** + * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs + */ +#define LWIP_IPV6_FORWARD 0 + +/** + * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big. + */ +#define LWIP_IPV6_FRAG 0 + +/** + * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented + */ +#define LWIP_IPV6_REASS (LWIP_IPV6) + +/** + * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during + * network startup. + */ +#define LWIP_IPV6_SEND_ROUTER_SOLICIT 1 + +/** + * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862. + */ +#define LWIP_IPV6_AUTOCONFIG (LWIP_IPV6) + +/** + * LWIP_IPV6_DUP_DETECT_ATTEMPTS=[0..7]: Number of duplicate address detection attempts. + */ +#define LWIP_IPV6_DUP_DETECT_ATTEMPTS 1 +/** + * @} + */ + +/** + * @defgroup lwip_opts_icmp6 ICMP6 + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC) + */ +#define LWIP_ICMP6 (LWIP_IPV6) + +/** + * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in + * ICMPv6 error messages. + */ +#define LWIP_ICMP6_DATASIZE 8 + +/** + * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages + */ +#define LWIP_ICMP6_HL 255 +/** + * @} + */ + +/** + * @defgroup lwip_opts_mld6 Multicast listener discovery + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol. + * If LWIP_IPV6 is enabled but this setting is disabled, the MAC layer must + * indiscriminately pass all inbound IPv6 multicast traffic to lwIP. + */ +#define LWIP_IPV6_MLD (LWIP_IPV6) + +/** + * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast groups that can be joined. + * There must be enough groups so that each netif can join the solicited-node + * multicast group for each of its local addresses, plus one for MDNS if + * applicable, plus any number of groups to be joined on UDP sockets. + */ +#define MEMP_NUM_MLD6_GROUP 4 +/** + * @} + */ + +/** + * @defgroup lwip_opts_nd6 Neighbor discovery + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address + * is being resolved. + */ +#define LWIP_ND6_QUEUEING (LWIP_IPV6) + +/** + * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. + */ +#define MEMP_NUM_ND6_QUEUE 20 + +/** + * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache + */ +#define LWIP_ND6_NUM_NEIGHBORS 10 + +/** + * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache + */ +#define LWIP_ND6_NUM_DESTINATIONS 10 + +/** + * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache + */ +#define LWIP_ND6_NUM_PREFIXES 5 + +/** + * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache + */ +#define LWIP_ND6_NUM_ROUTERS 3 + +/** + * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send + * (neighbor solicit and router solicit) + */ +#define LWIP_ND6_MAX_MULTICAST_SOLICIT 3 + +/** + * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages + * to send during neighbor reachability detection. + */ +#define LWIP_ND6_MAX_UNICAST_SOLICIT 3 + +/** + * Unused: See ND RFC (time in milliseconds). + */ +#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000 + +/** + * Unused: See ND RFC + */ +#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT 3 + +/** + * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds). + * May be updated by router advertisement messages. + */ +#define LWIP_ND6_REACHABLE_TIME 30000 + +/** + * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages + */ +#define LWIP_ND6_RETRANS_TIMER 1000 + +/** + * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation + * message is sent, during neighbor reachability detection. + */ +#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000 + +/** + * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update + * Reachable time and retransmission timers, and netif MTU. + */ +#define LWIP_ND6_ALLOW_RA_UPDATES 1 + +/** + * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery + * with reachability hints for connected destinations. This helps avoid sending + * unicast neighbor solicitation messages. + */ +#define LWIP_ND6_TCP_REACHABILITY_HINTS 1 + +/** + * LWIP_ND6_RDNSS_MAX_DNS_SERVERS > 0: Use IPv6 Router Advertisement Recursive + * DNS Server Option (as per RFC 6106) to copy a defined maximum number of DNS + * servers to the DNS module. + */ +#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 +/** + * @} + */ + +/** + * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful address autoconfiguration. + */ +#define LWIP_IPV6_DHCP6 0 // ??? + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/** + * @defgroup lwip_opts_hooks Hooks + * @ingroup lwip_opts_infrastructure + * Hooks are undefined by default, define them to a function if you need them. + * @{ + */ + +/** + * LWIP_HOOK_FILENAME: Custom filename to #include in files that provide hooks. + * Declare your hook function prototypes in there, you may also #include all headers + * providing data types that are need in this file. + */ +//#define LWIP_HOOK_FILENAME "path/to/my/lwip_hooks.h" + +/** + * LWIP_HOOK_TCP_ISN: + * Hook for generation of the Initial Sequence Number (ISN) for a new TCP + * connection. The default lwIP ISN generation algorithm is very basic and may + * allow for TCP spoofing attacks. This hook provides the means to implement + * the standardized ISN generation algorithm from RFC 6528 (see contrib/adons/tcp_isn), + * or any other desired algorithm as a replacement. + * Called from tcp_connect() and tcp_listen_input() when an ISN is needed for + * a new TCP connection, if TCP support (@ref LWIP_TCP) is enabled.\n + * Signature: u32_t my_hook_tcp_isn(const ip_addr_t* local_ip, u16_t local_port, const ip_addr_t* remote_ip, u16_t remote_port); + * - it may be necessary to use "struct ip_addr" (ip4_addr, ip6_addr) instead of "ip_addr_t" in function declarations\n + * Arguments: + * - local_ip: pointer to the local IP address of the connection + * - local_port: local port number of the connection (host-byte order) + * - remote_ip: pointer to the remote IP address of the connection + * - remote_port: remote port number of the connection (host-byte order)\n + * Return value: + * - the 32-bit Initial Sequence Number to use for the new TCP connection. + */ +//#define LWIP_HOOK_TCP_ISN(local_ip, local_port, remote_ip, remote_port) + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ +//#define LWIP_HOOK_IP4_INPUT(pbuf, input_netif) + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ +//#define LWIP_HOOK_IP4_ROUTE() + +/** + * LWIP_HOOK_IP4_ROUTE_SRC(dest, src): + * - source-based routing for IPv4 (see LWIP_HOOK_IP4_ROUTE(), src may be NULL) + */ +//#define LWIP_HOOK_IP4_ROUTE_SRC(dest, src) + +/** + * LWIP_HOOK_ETHARP_GET_GW(netif, dest): + * - called from etharp_output() (IPv4) + * - netif: the netif used for sending + * - dest: the destination IPv4 address + * Returns the IPv4 address of the gateway to handle the specified destination + * IPv4 address. If NULL is returned, the netif's default gateway is used. + * The returned address MUST be directly reachable on the specified netif! + * This function is meant to implement advanced IPv4 routing together with + * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is + * not part of lwIP but can e.g. be hidden in the netif's state argument. +*/ +//#define LWIP_HOOK_ETHARP_GET_GW(netif, dest) + +/** + * LWIP_HOOK_IP6_INPUT(pbuf, input_netif): + * - called from ip6_input() (IPv6) + * - pbuf: received struct pbuf passed to ip6_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ +//#define LWIP_HOOK_IP6_INPUT(pbuf, input_netif) + +/** + * LWIP_HOOK_IP6_ROUTE(src, dest): + * - called from ip6_route() (IPv6) + * - src: sourc IPv6 address + * - dest: destination IPv6 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip6_route() continues as normal. + */ +//#define LWIP_HOOK_IP6_ROUTE(src, dest) + +/** + * LWIP_HOOK_ND6_GET_GW(netif, dest): + * - called from nd6_get_next_hop_entry() (IPv6) + * - netif: the netif used for sending + * - dest: the destination IPv6 address + * Returns the IPv6 address of the next hop to handle the specified destination + * IPv6 address. If NULL is returned, a NDP-discovered router is used instead. + * The returned address MUST be directly reachable on the specified netif! + * This function is meant to implement advanced IPv6 routing together with + * LWIP_HOOK_IP6_ROUTE(). The actual routing/gateway table implementation is + * not part of lwIP but can e.g. be hidden in the netif's state argument. +*/ +//#define LWIP_HOOK_ND6_GET_GW(netif, dest) + +/** + * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr): + * - called from ethernet_input() if VLAN support is enabled + * - netif: struct netif on which the packet has been received + * - eth_hdr: struct eth_hdr of the packet + * - vlan_hdr: struct eth_vlan_hdr of the packet + * Return values: + * - 0: Packet must be dropped. + * - != 0: Packet must be accepted. + */ +//#define LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr) + +/** + * LWIP_HOOK_VLAN_SET: + * Hook can be used to set prio_vid field of vlan_hdr. If you need to store data + * on per-netif basis to implement this callback, see @ref netif_cd. + * Called from ethernet_output() if VLAN support (@ref ETHARP_SUPPORT_VLAN) is enabled.\n + * Signature: s32_t my_hook_vlan_set(struct netif* netif, struct pbuf* pbuf, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);\n + * Arguments: + * - netif: struct netif that the packet will be sent through + * - p: struct pbuf packet to be sent + * - src: source eth address + * - dst: destination eth address + * - eth_type: ethernet type to packet to be sent\n + * + * + * Return values: + * - <0: Packet shall not contain VLAN header. + * - 0 <= return value <= 0xFFFF: Packet shall contain VLAN header. Return value is prio_vid in host byte order. + */ +//#define LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type) + +/** + * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type): + * - called from memp_free() when a memp pool was empty and an item is now available + */ +//#define LWIP_HOOK_MEMP_AVAILABLE(memp_t_type) + +/** + * LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif): + * Called from ethernet_input() when an unknown eth type is encountered. + * Return ERR_OK if packet is accepted, any error code otherwise. + * Payload points to ethernet header! + */ +//#define LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif) +/** + * @} + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +//#define LWIP_DEBUG +/** + * @defgroup lwip_opts_debugmsg Debug messages + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + * @see debugging_levels + */ +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + * @see debugging_levels + */ +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#define ETHARP_DEBUG LWIP_DBG_OFF + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#define NETIF_DEBUG LWIP_DBG_OFF + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#define PBUF_DEBUG LWIP_DBG_OFF + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#define API_LIB_DEBUG LWIP_DBG_OFF + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#define API_MSG_DEBUG LWIP_DBG_OFF + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#define SOCKETS_DEBUG LWIP_DBG_OFF + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#define ICMP_DEBUG LWIP_DBG_OFF + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#define IGMP_DEBUG LWIP_DBG_OFF + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#define INET_DEBUG LWIP_DBG_OFF + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#define IP_DEBUG LWIP_DBG_OFF + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#define IP_REASS_DEBUG LWIP_DBG_OFF + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#define RAW_DEBUG LWIP_DBG_OFF + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#define MEM_DEBUG LWIP_DBG_OFF + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#define MEMP_DEBUG LWIP_DBG_OFF + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#define SYS_DEBUG LWIP_DBG_OFF + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#define TIMERS_DEBUG LWIP_DBG_OFF + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#define TCP_DEBUG LWIP_DBG_OFF + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#define TCP_INPUT_DEBUG LWIP_DBG_OFF + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#define TCP_FR_DEBUG LWIP_DBG_OFF + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#define TCP_RTO_DEBUG LWIP_DBG_OFF + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#define TCP_CWND_DEBUG LWIP_DBG_OFF + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#define TCP_WND_DEBUG LWIP_DBG_OFF + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#define TCP_RST_DEBUG LWIP_DBG_OFF + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#define TCP_QLEN_DEBUG LWIP_DBG_OFF + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#define UDP_DEBUG LWIP_DBG_OFF + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#define TCPIP_DEBUG LWIP_DBG_OFF + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#define SLIP_DEBUG LWIP_DBG_OFF + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#define DHCP_DEBUG LWIP_DBG_OFF + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#define AUTOIP_DEBUG LWIP_DBG_OFF + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#define DNS_DEBUG LWIP_DBG_OFF + +/** + * IP6_DEBUG: Enable debugging for IPv6. + */ +#define IP6_DEBUG LWIP_DBG_OFF + +#if LWIP_XR_IMPL +/** + * LWIP_XR_DEBUG: Enable debugging for XRadio. + */ +#define LWIP_XR_DEBUG LWIP_DBG_OFF +#endif /* LWIP_XR_IMPL */ +/** + * @} + */ + +/* + -------------------------------------------------- + ---------- Performance tracking options ---------- + -------------------------------------------------- +*/ +/** + * @defgroup lwip_opts_perf Performance + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_PERF: Enable performance testing for lwIP + * (if enabled, arch/perf.h is included) + */ +#define LWIP_PERF 0 +/** + * @} + */ + +#endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/platform/mcu/xr871/include/net/lwip/lwippools.h b/platform/mcu/xr871/include/net/lwip/lwippools.h new file mode 100644 index 0000000000..8c30970e32 --- /dev/null +++ b/platform/mcu/xr871/include/net/lwip/lwippools.h @@ -0,0 +1,12 @@ +/** + * Define pools used by mbuf. + * + * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + */ + +#define SIZEOF_MBUF 48 /* MUST be equal to MSIZE defined in mbuf.h */ +#define MEMP_NUM_MBUF 64 + +//LWIP_MEMPOOL(MBUF, MEMP_NUM_MBUF, sizeof(struct mbuf), "MBUF") +LWIP_MEMPOOL(MBUF, MEMP_NUM_MBUF, SIZEOF_MBUF, "MBUF") diff --git a/platform/mcu/xr871/include/net/udhcp/usr_dhcpd.h b/platform/mcu/xr871/include/net/udhcp/usr_dhcpd.h new file mode 100644 index 0000000000..c5e9542415 --- /dev/null +++ b/platform/mcu/xr871/include/net/udhcp/usr_dhcpd.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USR_DHCPD_H_H +#define __USR_DHCPD_H_H + +#ifdef __cplusplus +extern "C" { +#endif + +struct dhcp_server_info { + unsigned int addr_start; + unsigned int addr_end; + unsigned int lease_time; + unsigned int max_leases; +}; + +void dhcp_server_start(const struct dhcp_server_info *arg); +void dhcp_server_stop(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __USR_DHCPD_H_H */ diff --git a/platform/mcu/xr871/include/net/wlan/ethernetif.h b/platform/mcu/xr871/include/net/wlan/ethernetif.h new file mode 100644 index 0000000000..aaf6b4dbc4 --- /dev/null +++ b/platform/mcu/xr871/include/net/wlan/ethernetif.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_ETHERNETIF_H_ +#define _NET_WLAN_ETHERNETIF_H_ + +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum wlan_mode { + WLAN_MODE_STA = 0, /* Infrastructure station */ + WLAN_MODE_HOSTAP, /* Software Access Point */ + WLAN_MODE_MONITOR, /* Monitor mode */ + WLAN_MODE_NUM, + WLAN_MODE_INVALID = WLAN_MODE_NUM +}; + +struct netif *ethernetif_create(enum wlan_mode mode); +void ethernetif_delete(struct netif *nif); +err_t ethernetif_input(struct netif *nif, struct pbuf *p); +#if (LWIP_MBUF_SUPPORT == 0) +err_t ethernetif_raw_input(struct netif *nif, uint8_t *data, u16_t len); +#endif +enum wlan_mode ethernetif_get_mode(struct netif *nif); + +#ifdef __cplusplus +} +#endif + +#endif /* _NET_WLAN_ETHERNETIF_H_ */ diff --git a/platform/mcu/xr871/include/net/wlan/wlan.h b/platform/mcu/xr871/include/net/wlan/wlan.h new file mode 100644 index 0000000000..10edcccc7f --- /dev/null +++ b/platform/mcu/xr871/include/net/wlan/wlan.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_WLAN_H_ +#define _NET_WLAN_WLAN_H_ + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +#include +#include "lwip/netif.h" +#include "sys/ducc/ducc_net.h" +#include "sys/ducc/ducc_app.h" +#include "net/wlan/wlan_defs.h" +#include "net/wlan/ethernetif.h" +#include "net/wlan/wlan_smart_config.h" +#include "net/wlan/wlan_airkiss.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* wlan sys */ +int wlan_sys_init(enum wlan_mode mode, ducc_cb_func cb); +int wlan_sys_deinit(void); + +int wlan_start(struct netif *nif); +int wlan_stop(void); /* Note: make sure wlan is disconnect before calling wlan_stop() */ + +static __inline int wlan_attach(void) +{ + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_ATTACH, NULL); +} + +static __inline int wlan_detach(void) +{ + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_DETACH, NULL); +} + +static __inline struct netif *wlan_if_create(enum wlan_mode mode) +{ + return ethernetif_create(mode); +} + +static __inline int wlan_if_delete(struct netif *nif) +{ + ethernetif_delete(nif); + return 0; +} + +static __inline enum wlan_mode wlan_if_get_mode(struct netif *nif) +{ + return ethernetif_get_mode(nif); +} + +int wlan_set_mac_addr(uint8_t *mac_addr, int mac_len); +int wlan_set_ip_addr(struct netif *nif, uint8_t *ip_addr, int ip_len); +int wlan_set_appie(struct netif *nif, uint8_t type, uint8_t *ie, uint16_t ie_len); + +/* STA */ +int wlan_sta_set(uint8_t *ssid, uint8_t ssid_len, uint8_t *psk); +int wlan_sta_set_config(wlan_sta_config_t *config); +int wlan_sta_get_config(wlan_sta_config_t *config); + +int wlan_sta_enable(void); +int wlan_sta_disable(void); + +int wlan_sta_scan_once(void); +int wlan_sta_scan_result(wlan_sta_scan_results_t *results); +int wlan_sta_scan_interval(int sec); +int wlan_sta_bss_flush(int age); + +int wlan_sta_connect(void); +int wlan_sta_disconnect(void); + +int wlan_sta_state(wlan_sta_states_t *state); +int wlan_sta_ap_info(wlan_sta_ap_t *ap); + +int wlan_sta_wps_pbc(void); +int wlan_sta_wps_pin_get(wlan_sta_wps_pin_t *wps); +int wlan_sta_wps_pin_set(wlan_sta_wps_pin_t *wps); + +/* softAP */ +int wlan_ap_set(uint8_t *ssid, uint8_t ssid_len, uint8_t *psk); +int wlan_ap_set_config(wlan_ap_config_t *config); +int wlan_ap_get_config(wlan_ap_config_t *config); + +int wlan_ap_enable(void); +int wlan_ap_reload(void); +int wlan_ap_disable(void); + +int wlan_ap_sta_num(int *num); +int wlan_ap_sta_info(wlan_ap_stas_t *stas); + +/* monitor */ +typedef void (*wlan_monitor_rx_cb)(uint8_t *data, uint32_t len, void *info); +int wlan_monitor_set_rx_cb(struct netif *nif, wlan_monitor_rx_cb cb); +int wlan_monitor_set_channel(struct netif *nif, int16_t channel); +void wlan_monitor_input(struct netif *nif, uint8_t *data, uint32_t len, void *info); + +#ifdef __cplusplus +} +#endif + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ + +#endif /* _NET_WLAN_WLAN_H_ */ diff --git a/platform/mcu/xr871/include/net/wlan/wlan_airkiss.h b/platform/mcu/xr871/include/net/wlan/wlan_airkiss.h new file mode 100644 index 0000000000..f0565c97df --- /dev/null +++ b/platform/mcu/xr871/include/net/wlan/wlan_airkiss.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_WLAN_AIRKISS_H_ +#define _NET_WLAN_WLAN_AIRKISS_H_ + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +#include +#include "net/wlan/wlan_defs.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + WLAN_AIRKISS_SUCCESS = 0, /* success */ + WLAN_AIRKISS_FAIL = -1, /* general error */ + WLAN_AIRKISS_TIMEOUT = -2, /* wait timeout */ + WLAN_AIRKISS_INVALID = -3, /* invalid argument */ +} wlan_airkiss_status_t; + +typedef struct wlan_airkiss_result { + uint8_t ssid[WLAN_SSID_MAX_LEN]; + uint8_t ssid_len; + uint8_t passphrase[WLAN_PASSPHRASE_MAX_LEN + 1]; /* ASCII string ending with '\0' */ + uint8_t random_num; +} wlan_airkiss_result_t; + +#define WLAN_AIRKISS_KEY_LEN 16 + +int wlan_airkiss_set_key(const char *key, uint32_t len); + +wlan_airkiss_status_t wlan_airkiss_start(struct netif *nif, uint32_t timeout_ms, + wlan_airkiss_result_t *result); +int wlan_airkiss_stop(void); + +int wlan_airkiss_ack_start(struct netif *nif, uint32_t random_num, uint32_t timeout_ms); +int wlan_airkiss_ack_stop(void); + +/* + * The wechat_public_id and devic_id should be global variables. + * In this mode, the driver will be send online data by cycle + */ +int wlan_airkiss_online_cycle_ack_start(char *app_id, char *drv_id, uint32_t period_ms); +int wlan_airkiss_online_cycle_ack_stop(void); + +/* + * The wechat_public_id and devic_id should be global variables. + * In this mode, the drivers will be listen to server's request and send ack for server, then the driver will + * be send online data by cycle + */ +int wlan_airkiss_online_dialog_mode_start(char *app_id, char *drv_id, uint32_t period_ms); +int wlan_airkiss_online_dialog_mode_stop(void); + +#ifdef __cplusplus +} +#endif + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ + +#endif /* _NET_WLAN_WLAN_AIRKISS_H_ */ diff --git a/platform/mcu/xr871/include/net/wlan/wlan_defs.h b/platform/mcu/xr871/include/net/wlan/wlan_defs.h new file mode 100644 index 0000000000..406efffe82 --- /dev/null +++ b/platform/mcu/xr871/include/net/wlan/wlan_defs.h @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_WLAN_DEFS_H_ +#define _NET_WLAN_WLAN_DEFS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef WPA_BIT +#define WPA_BIT(x) (1 << (x)) +#endif + +/** + * @brief WPA cipher definition + */ +#define WPA_CIPHER_NONE WPA_BIT(0) +#define WPA_CIPHER_WEP40 WPA_BIT(1) +#define WPA_CIPHER_WEP104 WPA_BIT(2) +#define WPA_CIPHER_TKIP WPA_BIT(3) +#define WPA_CIPHER_CCMP WPA_BIT(4) +#define WPA_CIPHER_AES_128_CMAC WPA_BIT(5) +#define WPA_CIPHER_GCMP WPA_BIT(6) +#define WPA_CIPHER_SMS4 WPA_BIT(7) +#define WPA_CIPHER_GCMP_256 WPA_BIT(8) +#define WPA_CIPHER_CCMP_256 WPA_BIT(9) +#define WPA_CIPHER_BIP_GMAC_128 WPA_BIT(11) +#define WPA_CIPHER_BIP_GMAC_256 WPA_BIT(12) +#define WPA_CIPHER_BIP_CMAC_256 WPA_BIT(13) +#define WPA_CIPHER_GTK_NOT_USED WPA_BIT(14) +#define WPA_CIPHER_MASK 0x7fffUL + +/** + * @brief WPA key management definition + */ +#define WPA_KEY_MGMT_IEEE8021X WPA_BIT(0) +#define WPA_KEY_MGMT_PSK WPA_BIT(1) +#define WPA_KEY_MGMT_NONE WPA_BIT(2) +#define WPA_KEY_MGMT_IEEE8021X_NO_WPA WPA_BIT(3) +#define WPA_KEY_MGMT_WPA_NONE WPA_BIT(4) +#define WPA_KEY_MGMT_FT_IEEE8021X WPA_BIT(5) +#define WPA_KEY_MGMT_FT_PSK WPA_BIT(6) +#define WPA_KEY_MGMT_IEEE8021X_SHA256 WPA_BIT(7) +#define WPA_KEY_MGMT_PSK_SHA256 WPA_BIT(8) +#define WPA_KEY_MGMT_WPS WPA_BIT(9) +#define WPA_KEY_MGMT_SAE WPA_BIT(10) +#define WPA_KEY_MGMT_FT_SAE WPA_BIT(11) +#define WPA_KEY_MGMT_WAPI_PSK WPA_BIT(12) +#define WPA_KEY_MGMT_WAPI_CERT WPA_BIT(13) +#define WPA_KEY_MGMT_CCKM WPA_BIT(14) +#define WPA_KEY_MGMT_OSEN WPA_BIT(15) +#define WPA_KEY_MGMT_IEEE8021X_SUITE_B WPA_BIT(16) +#define WPA_KEY_MGMT_IEEE8021X_SUITE_B_192 WPA_BIT(17) +#define WPA_KEY_MGMT_MASK 0x3ffffUL + +/** + * @brief WPA protocol definition + */ +#define WPA_PROTO_WPA WPA_BIT(0) +#define WPA_PROTO_RSN WPA_BIT(1) +#define WPA_PROTO_WAPI WPA_BIT(2) +#define WPA_PROTO_OSEN WPA_BIT(3) +#define WPA_PROTO_MASK 0xfUL + +/** + * @brief WPA authentication algorithm definition + */ +#define WPA_AUTH_ALG_OPEN WPA_BIT(0) +#define WPA_AUTH_ALG_SHARED WPA_BIT(1) +#define WPA_AUTH_ALG_LEAP WPA_BIT(2) +#define WPA_AUTH_ALG_FT WPA_BIT(3) +#define WPA_AUTH_ALG_SAE WPA_BIT(4) +#define WPA_AUTH_ALG_MASK 0x1fUL + +/** + * @brief WPA scan result flags definition + */ +#define WPA_FLAGS_WPA WPA_BIT(0) +#define WPA_FLAGS_WPA2 WPA_BIT(1) +#define WPA_FLAGS_WEP WPA_BIT(2) +#define WPA_FLAGS_WPS_PBC WPA_BIT(3) +#define WPA_FLAGS_WPS_AUTH WPA_BIT(4) +#define WPA_FLAGS_WPS_PIN WPA_BIT(5) +#define WPA_FLAGS_WPS WPA_BIT(6) +#define WPA_FLAGS_IBSS WPA_BIT(7) +#define WPA_FLAGS_ESS WPA_BIT(8) + +/** + * @brief WLAN SSID and passphrase definition + */ +#define WLAN_SSID_MAX_LEN 32 +#define WLAN_PASSPHRASE_MIN_LEN 8 +#define WLAN_PASSPHRASE_MAX_LEN 63 + +/** + * @brief IEEE 802.11 frame type definition + */ +#define IEEE80211_FC_TYPE_SHIFT 2 +#define IEEE80211_FC_TYPE_MASK (0x3 << IEEE80211_FC_TYPE_SHIFT) +#define IEEE80211_FC_TYPE_MGMT (0x0 << IEEE80211_FC_TYPE_SHIFT) +#define IEEE80211_FC_TYPE_CTRL (0x1 << IEEE80211_FC_TYPE_SHIFT) +#define IEEE80211_FC_TYPE_DATA (0x2 << IEEE80211_FC_TYPE_SHIFT) + +/** + * @brief IEEE 802.11 management frame subtype definition + */ +#define IEEE80211_FC_STYPE_SHIFT 4 +#define IEEE80211_FC_STYPE_MASK (0xf << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_ASSOC_REQ (0x0 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_ASSOC_RESP (0x1 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_REASSOC_REQ (0x2 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_REASSOC_RESP (0x3 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_PROBE_REQ (0x4 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_PROBE_RESP (0x5 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_BEACON (0x8 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_ATIM (0x9 << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_DISASSOC (0xa << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_AUTH (0xb << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_DEAUTH (0xc << IEEE80211_FC_STYPE_SHIFT) +#define IEEE80211_FC_STYPE_ACTION (0xd << IEEE80211_FC_STYPE_SHIFT) + +/** + * @brief Wlan event definition + */ +typedef enum wlan_event { + WLAN_EVENT_CONNECTED, + WLAN_EVENT_DISCONNECTED, + WLAN_EVENT_SCAN_SUCCESS, + WLAN_EVENT_SCAN_FAILED, + WLAN_EVENT_4WAY_HANDSHAKE_FAILED, + WLAN_EVENT_CONNECT_FAILED, + + WLAN_EVENT_DEV_HANG, +} wlan_event_t; + +/** + * @brief Wlan ssid definition + */ +typedef struct wlan_ssid { + uint8_t ssid[WLAN_SSID_MAX_LEN]; + uint8_t ssid_len; +} wlan_ssid_t; + +/** + * @brief Wlan station configuration field definition + */ +typedef enum wlan_sta_field { + WLAN_STA_FIELD_SSID = 0, + WLAN_STA_FIELD_PSK, + WLAN_STA_FIELD_WEP_KEY0, + WLAN_STA_FIELD_WEP_KEY1, + WLAN_STA_FIELD_WEP_KEY2, + WLAN_STA_FIELD_WEP_KEY3, + WLAN_STA_FIELD_WEP_KEY_INDEX, + WLAN_STA_FIELD_KEY_MGMT, + WLAN_STA_FIELD_PAIRWISE_CIPHER, + WLAN_STA_FIELD_GROUP_CIPHER, + WLAN_STA_FIELD_PROTO, + WLAN_STA_FIELD_AUTH_ALG, + WLAN_STA_FIELD_WPA_PTK_REKEY, + WLAN_STA_FIELD_SCAN_SSID, + + WLAN_STA_FIELD_NUM, +} wlan_sta_field_t; + +/** + * @brief Wlan station configuration definition + */ +typedef struct wlan_sta_config { + wlan_sta_field_t field; + + union { + /** + * Network name + */ + wlan_ssid_t ssid; + + /** + * WPA preshared key in one of the optional formats: + * - an ASCII string of passphrase, length is [8, 63] + * - a hex string of PSK (two characters per octet of PSK), length is 64 + */ + uint8_t psk[65]; + + /** + * WEP key in one of the optional formats: + * - an ASCII string with double quotation, length is [5, 13] + 2 + * - a hex string (two characters per octet of PSK), length is [10, 26] + */ + uint8_t wep_key[27]; + + /** + * Default key index for TX frames using WEP + */ + int wep_tx_keyidx; + + /** + * Bitfield of allowed key management protocols + * + * WPA_KEY_MGMT_* + */ + int key_mgmt; + + /** + * Bitfield of allowed pairwise ciphers + * + * WPA_CIPHER_* + */ + int pairwise_cipher; + + /** + * Bitfield of allowed group ciphers + * + * WPA_CIPHER_* + */ + int group_cipher; + + /** + * Bitfield of allowed protocols + * + * WPA_PROTO_* + */ + int proto; + + /** + * Bitfield of allowed authentication algorithms + * + * WPA_AUTH_ALG_* + */ + int auth_alg; + + /** + * Maximum lifetime for PTK in seconds + * + * This value can be used to enforce rekeying of PTK to + * mitigate some attacks against TKIP deficiencies. + */ + int wpa_ptk_rekey; + + /** + * Scan this SSID with Probe Requests + * + * scan_ssid can be used to scan for APs using hidden SSIDs. + */ + int scan_ssid; + } u; +} wlan_sta_config_t; + +/** + * @brief Wlan station connection state definition + */ +typedef enum wlan_sta_states { + WLAN_STA_STATE_DISCONNECTED = 0, + WLAN_STA_STATE_CONNECTED = 1, +} wlan_sta_states_t; + +/** + * @brief Wlan AP information definition + */ +typedef struct wlan_sta_ap { + wlan_ssid_t ssid; + uint8_t bssid[6]; + uint8_t channel; + uint16_t beacon_int; + int freq; + int rssi; + int level; + int wpa_flags; + int wpa_cipher; + int wpa_key_mgmt; + int wpa2_cipher; + int wpa2_key_mgmt; +}wlan_sta_ap_t; + +/** + * @brief Wlan station scan results definition + */ +typedef struct wlan_sta_scan_results { + wlan_sta_ap_t *ap; + int size; + int num; +} wlan_sta_scan_results_t; + +/** + * @brief Wlan WPS pin definition + */ +typedef struct wlan_sta_wps_pin { + uint8_t pin[9]; +} wlan_sta_wps_pin_t; + +/** + * @brief Wlan AP configuration field definition + */ +typedef enum wlan_ap_field { + WLAN_AP_FIELD_SSID = 0, + WLAN_AP_FIELD_PSK, + WLAN_AP_FIELD_KEY_MGMT, + WLAN_AP_FIELD_WPA_CIPHER, + WLAN_AP_FIELD_RSN_CIPHER, + WLAN_AP_FIELD_PROTO, + WLAN_AP_FIELD_AUTH_ALG, + WLAN_AP_FIELD_GROUP_REKEY, + WLAN_AP_FIELD_STRICT_REKEY, + WLAN_AP_FIELD_GMK_REKEY, + WLAN_AP_FIELD_PTK_REKEY, + WLAN_AP_FIELD_HW_MODE, + WLAN_AP_FIELD_IEEE80211N, + WLAN_AP_FIELD_CHANNEL, + WLAN_AP_FIELD_BEACON_INT, + WLAN_AP_FIELD_DTIM, + WLAN_AP_FIELD_MAX_NUM_STA, + + WLAN_AP_FIELD_NUM, +} wlan_ap_field_t; + +/** + * @brief Wlan AP hardware mode definition + */ +typedef enum wlan_ap_hw_mode { + WLAN_AP_HW_MODE_IEEE80211B = 0, + WLAN_AP_HW_MODE_IEEE80211G, + WLAN_AP_HW_MODE_IEEE80211A, + WLAN_AP_HW_MODE_IEEE80211AD, + + WLAN_AP_HW_MODE_NUM, +} wlan_ap_hw_mode_t; + +/** + * @brief Wlan AP configuration definition + */ +typedef struct wlan_ap_config { + wlan_ap_field_t field; + + union { + /** + * Network name + */ + wlan_ssid_t ssid; + + /** + * WPA preshared key in one of the optional formats: + * - an ASCII string of passphrase, length is [8, 63] + * - a hex string of PSK (two characters per octet of PSK), length is 64 + */ + uint8_t psk[65]; + + /** + * Bitfield of allowed key management protocols + * + * WPA_KEY_MGMT_* + */ + int key_mgmt; + + /** + * Bitfield of allowed WPA pairwise ciphers + * + * WPA_CIPHER_* + */ + int wpa_cipher; + + /** + * Bitfield of allowed RSN pairwise ciphers + * + * WPA_CIPHER_* + */ + int rsn_cipher; + + /** + * Bitfield of allowed protocols + * + * WPA_PROTO_* + */ + int proto; + + /** + * Bitfield of allowed authentication algorithms + * + * WPA_AUTH_ALG_* + */ + int auth_alg; + + /** + * Maximum lifetime for GTK in seconds + */ + int group_rekey; + + /** + * Rekey GTK when any STA that possesses the current GTK is + * leaving the BSS + */ + int strict_rekey; + + /** + * Maximum lifetime for GMK in seconds + */ + int gmk_rekey; + + /** + * Maximum lifetime for PTK in seconds + */ + int ptk_rekey; + + /** + * Hardware mode + */ + wlan_ap_hw_mode_t hw_mode; + + /** + * IEEE802.11n mode + */ + int ieee80211n; + + /** + * RF channel + */ + uint8_t channel; + + /** + * MIB defines range as 1..65535, but very small values + * cause problems with the current implementation. + * Since it is unlikely that this small numbers are + * useful in real life scenarios, do not allow beacon + * period to be set below 15 TU. + */ + uint16_t beacon_int; + + /** + * Delivery traffic indication message + */ + int dtim; + + /** + * Maximum number of STAs in station table + */ + int max_num_sta; + } u; +} wlan_ap_config_t; + +/** + * @brief Wlan station information definition + */ +typedef struct wlan_ap_sta { + uint8_t addr[6]; +} wlan_ap_sta_t; + +/** + * @brief Wlan connected stations information definition + */ +typedef struct wlan_ap_stas { + wlan_ap_sta_t *sta; + int size; + int num; +} wlan_ap_stas_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _NET_WLAN_WLAN_DEFS_H_ */ diff --git a/platform/mcu/xr871/include/net/wlan/wlan_smart_config.h b/platform/mcu/xr871/include/net/wlan/wlan_smart_config.h new file mode 100644 index 0000000000..e1f1332df9 --- /dev/null +++ b/platform/mcu/xr871/include/net/wlan/wlan_smart_config.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_WLAN_SMART_CONFIG_H_ +#define _NET_WLAN_WLAN_SMART_CONFIG_H_ + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +#include +#include "net/wlan/wlan_defs.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + WLAN_SMART_CONFIG_SUCCESS = 0, /* success */ + WLAN_SMART_CONFIG_FAIL = -1, /* general error */ + WLAN_SMART_CONFIG_TIMEOUT = -2, /* wait timeout */ + WLAN_SMART_CONFIG_INVALID = -3, /* invalid argument */ +} wlan_smart_config_status_t; + +typedef struct wlan_smart_config_result { + uint8_t ssid[WLAN_SSID_MAX_LEN]; + uint8_t ssid_len; + uint8_t passphrase[WLAN_PASSPHRASE_MAX_LEN + 1]; /* ASCII string ending with '\0' */ + uint8_t random_num; +} wlan_smart_config_result_t; + +#define WLAN_SMART_CONFIG_KEY_LEN 16 + +int wlan_smart_config_set_key(const char *key, uint32_t len); + +wlan_smart_config_status_t wlan_smart_config_start(struct netif *nif, + uint32_t timeout_ms, + wlan_smart_config_result_t *result); +int wlan_smart_config_stop(void); + +int wlan_smart_config_ack_start(struct netif *nif, uint32_t random_num, uint32_t timeout_ms); +int wlan_smart_config_ack_stop(void); + +#ifdef __cplusplus +} +#endif + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ + +#endif /* _NET_WLAN_WLAN_SMART_CONFIG_H_ */ diff --git a/platform/mcu/xr871/include/pm/pm.h b/platform/mcu/xr871/include/pm/pm.h new file mode 100644 index 0000000000..841d4df6b6 --- /dev/null +++ b/platform/mcu/xr871/include/pm/pm.h @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XRADIO_PM_H +#define __XRADIO_PM_H + +#include +#include +#include "sys/list.h" + +#ifdef __CONFIG_BOOTLOADER +#else +#define CONFIG_PM +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Defined all supported low power state. + * @note PM_MODE_HIBERNATION is not used. + */ +enum suspend_state_t { + PM_MODE_ON = 0, + PM_MODE_SLEEP = 1, + PM_MODE_STANDBY = 2, + PM_MODE_HIBERNATION = 3, + PM_MODE_POWEROFF = 4, + PM_MODE_MAX = 5, +}; + +/** @brief Platform pm mode support. */ +#define PM_SUPPORT_SLEEP (1<Device will be registered. + * @retval 0 if success or other if failed. + */ +extern int pm_register_ops(struct soc_device *dev); + +/** + * @brief Unregister a set of system core operations. + * @param dev: + * @arg dev->Device will be unregistered. + * @retval 0 if success or other if failed. + */ +extern int pm_unregister_ops(struct soc_device *dev); + +/** + * @brief Set a magin to synchronize with net. + */ +extern void pm_set_sync_magic(void); + +/** + * @brief Set system to a lowpower mode. + * @param state: + * @arg state->The lowpower mode will enter. + * @retval 0 if success or other if failed. + */ +extern int pm_enter_mode(enum suspend_state_t state); + +/** + * @brief Initialize the PM-related part of a device object. + * @note not use printf for this fun is called very earlier. + * @retval 0 if success or other if failed. + */ +extern int pm_init(void); + +/** + * @brief Set suspend test level. + * @param level: + * @arg level->Suspend will exit when run up to setted level. + */ +extern void pm_set_test_level(enum suspend_test_level_t level); + +/** + * @brief Set delay ms in debug mode. + * @note To prevent mutual interference between devices. + * @param ms: + * @arg ms->The delayed ms between two devices. + */ +extern void pm_set_debug_delay_ms(unsigned int ms); + +/** @brief Show suspend statistic info. */ +extern void pm_stats_show(void); + +/** + * @brief Select pm modes used on this platform. + * @note Select modes at init for some modes are not used on some platforms. + * This will prevent enter unselected modes. + * @param select: + * @arg select->The selected modes set. + */ +extern void pm_mode_platform_select(unsigned int select); + +/** + * @brief register wlan power on/off callback. + * @note Wlan power on/off calback will be called when pm enter select modes. + * @param wlan_power_cb: + * @arg wlan_power_cb->Wlan power on/off calback. + * @param select: + * @arg select->The selected modes set. + * retval 0 if success or other if failed. + */ +extern int pm_register_wlan_power_onoff(pm_wlan_power_onoff wlan_power_cb, + unsigned int select); + +/** @brief unregister wlan power on/off callback. */ +extern void pm_unregister_wlan_power_onoff(void); + +extern int pm_test(void); +#else /* CONFIG_PM */ +static inline int pm_register_ops(struct soc_device *dev) { return 0; } +static inline int pm_unregister_ops(struct soc_device *dev) { return 0; } +static inline void pm_set_sync_magic(void) { ; } +static inline int pm_enter_mode(enum suspend_state_t state) { return 0; } +static inline int pm_init(void) { return 0;} +static inline void pm_set_test_level(enum suspend_test_level_t level) {;} +static inline void pm_set_debug_delay_ms(unsigned int ms) { ; } +static inline void pm_stats_show(void) {;} +static inline void pm_mode_platform_select(unsigned int select) {;} +static inline int pm_register_wlan_power_onoff(pm_wlan_power_onoff wlan_power_cb, + unsigned int select) { return 0; } +static inline int pm_test(void) { return 0; } +#endif /* CONFIG_PM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/include/sys/defs.h b/platform/mcu/xr871/include/sys/defs.h new file mode 100644 index 0000000000..4e72cab74f --- /dev/null +++ b/platform/mcu/xr871/include/sys/defs.h @@ -0,0 +1,82 @@ +/* libc/sys/linux/sys/cdefs.h - Helper macros for K&R vs. ANSI C compat. */ + +/* Written 2000 by Werner Almesberger */ + +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_DEFS_H_ +#define _SYS_DEFS_H_ + +#include "types.h" +#include "compiler.h" + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(uintptr_t)(const volatile void *)(var)) +#endif + +#ifndef offsetof +#define offsetof(type, field) \ + ((size_t)(uintptr_t)((const volatile void *)&((type *)0)->field)) +#endif + +#ifndef __offsetof +#define __offsetof(type, field) offsetof(type, field) +#endif + +#ifndef __containerof +#define __containerof(ptr, type, field) \ + __DEQUALIFY(type *, (const volatile char *)(ptr) - offsetof(type, field)) +#endif + +#ifndef container_of +#define container_of(ptr, type, field) __containerof(ptr, type, field) +#endif + + +/* + * Definitions for byte order, according to byte significance from low + * address to high. + */ +#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ +#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ + +#define LITTLE_ENDIAN _LITTLE_ENDIAN +#define BIG_ENDIAN _BIG_ENDIAN + +#define _BYTE_ORDER _LITTLE_ENDIAN +#define BYTE_ORDER _BYTE_ORDER + +#endif /* _SYS_DEFS_H_ */ diff --git a/platform/mcu/xr871/include/sys/ducc/ducc_addr.h b/platform/mcu/xr871/include/sys/ducc/ducc_addr.h new file mode 100644 index 0000000000..a7496d075b --- /dev/null +++ b/platform/mcu/xr871/include/sys/ducc/ducc_addr.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_ADDR_H_ +#define _SYS_DUCC_DUCC_ADDR_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* There are 4 types of memory address value for app core and net core. + * - APP_MEM_APP_ADDR: memory allocated from app, used by app + * - APP_MEM_NET_ADDR: memory allocated from app, used by net + * - NET_MEM_APP_ADDR: memory allocated from net, used by app + * - NET_MEM_NET_ADDR: memory allocated from net, used by net + */ + +/* convert from APP_MEM_APP_ADDR to APP_MEM_NET_ADDR */ +#define DUCC_APPMEM_APP2NET(addr) ((uint32_t)(addr) | 0x20000000) + +/* convert from APP_MEM_NET_ADDR to APP_MEM_APP_ADDR */ +#define DUCC_APPMEM_NET2APP(addr) ((uint32_t)(addr) & ~0xf0000000) + +/* convert from NET_MEM_NET_ADDR to NET_MEM_APP_ADDR */ +#define DUCC_NETMEM_NET2APP(addr) ((uint32_t)(addr) | 0x60000000) + +/* convert from NET_MEM_APP_ADDR to NET_MEM_NET_ADDR */ +#define DUCC_NETMEM_APP2NET(addr) ((uint32_t)(addr) & ~0xf0000000) + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_ADDR_H_ */ diff --git a/platform/mcu/xr871/include/sys/ducc/ducc_app.h b/platform/mcu/xr871/include/sys/ducc/ducc_app.h new file mode 100644 index 0000000000..5518d43a9b --- /dev/null +++ b/platform/mcu/xr871/include/sys/ducc/ducc_app.h @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_APP_H_ +#define _SYS_DUCC_DUCC_APP_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum ducc_app_cmd { + /* data command */ + DUCC_APP_CMD_WLAN_LINKOUTPUT, + + /* normal command */ +#if (__CONFIG_MBUF_IMPL_MODE == 0) + DUCC_APP_CMD_MBUF_GET, + DUCC_APP_CMD_MBUF_FREE, +#endif + DUCC_APP_CMD_CONSOLE_EXEC, + DUCC_APP_CMD_UART_CONFIG, + DUCC_APP_CMD_POWER_NOTIFY, + + DUCC_APP_CMD_WLAN_ATTACH, + DUCC_APP_CMD_WLAN_DETACH, + DUCC_APP_CMD_WLAN_IF_CREATE, + DUCC_APP_CMD_WLAN_IF_DELETE, + DUCC_APP_CMD_WLAN_START, + DUCC_APP_CMD_WLAN_STOP, + DUCC_APP_CMD_WLAN_GET_MAC_ADDR, + DUCC_APP_CMD_WLAN_SET_MAC_ADDR, + DUCC_APP_CMD_WLAN_SET_IP_ADDR, + DUCC_APP_CMD_WLAN_SET_APPIE, + + DUCC_APP_CMD_WLAN_MONITOR_ENABLE_RX, + DUCC_APP_CMD_WLAN_MONITOR_SET_CHAN, + + DUCC_APP_CMD_WLAN_WPA_CTRL_OPEN, + DUCC_APP_CMD_WLAN_WPA_CTRL_CLOSE, + DUCC_APP_CMD_WLAN_WPA_CTRL_REQUEST, +}; + +#define DUCC_APP_IS_DATA_CMD(c) \ + ((c) == DUCC_APP_CMD_WLAN_LINKOUTPUT) + +#if (__CONFIG_MBUF_IMPL_MODE == 0) +struct ducc_param_mbuf_get { + int len; + int tx; + void *mbuf; +}; +#endif + +struct ducc_param_wlan_create { + uint32_t mode; + void *nif; + const char *name; + void *ifp; /* @out */ +}; + +struct ducc_param_wlan_get_mac_addr { + void *ifp; + uint8_t *buf; + int buf_len; +}; + +struct ducc_param_wlan_set_mac_addr { + uint8_t *mac_addr; + int mac_len; +}; + +struct ducc_param_wlan_linkoutput { + void *ifp; + void *mbuf; +}; + +struct ducc_param_wlan_set_ip_addr { + void *ifp; + uint8_t *ip_addr; + int ip_len; +}; + +struct ducc_param_wlan_appie { + void *ifp; + uint8_t type; + uint16_t ie_len; + uint8_t *ie; +}; + +struct ducc_param_wlan_mon_set_chan { + void *ifp; + int16_t channel; +}; + +struct ducc_param_wlan_wpa_ctrl_req { + uint32_t cmd; + void *data; +}; + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +typedef int (*ducc_cb_func)(uint32_t param0, uint32_t param1); + +struct ducc_app_param { + ducc_cb_func cb; +}; + +int ducc_app_start(struct ducc_app_param *param); +int ducc_app_ioctl(enum ducc_app_cmd cmd, void *param); +int ducc_app_stop(void); + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_APP_H_ */ diff --git a/platform/mcu/xr871/include/sys/ducc/ducc_net.h b/platform/mcu/xr871/include/sys/ducc/ducc_net.h new file mode 100644 index 0000000000..2e7e343d13 --- /dev/null +++ b/platform/mcu/xr871/include/sys/ducc/ducc_net.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_NET_H_ +#define _SYS_DUCC_DUCC_NET_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum ducc_net_cmd { + /* data command */ + DUCC_NET_CMD_WLAN_INPUT, + DUCC_NET_CMD_WLAN_MONITOR_INPUT, /* data input for monitor mode */ + + /* normal command */ +#if (__CONFIG_MBUF_IMPL_MODE == 1) + DUCC_NET_CMD_MBUF_GET, + DUCC_NET_CMD_MBUF_FREE, +#endif + DUCC_NET_CMD_POWER_NOTIFY, + DUCC_NET_CMD_BIN_READ, + DUCC_NET_CMD_EFUSE_READ, + + DUCC_NET_CMD_SYS_EVENT, /* refer to enum ducc_net_sys_event */ + DUCC_NET_CMD_WLAN_EVENT, /* refer to enum wlan_event */ +}; + +#define DUCC_NET_IS_DATA_CMD(c) \ + ((c) <= DUCC_NET_CMD_WLAN_MONITOR_INPUT) + +enum ducc_net_sys_event { + DUCC_NET_SYS_READY, +}; + +struct ducc_param_wlan_input { + void *nif; +#if (__CONFIG_MBUF_IMPL_MODE == 0) + uint8_t *data; + int len; +#elif (__CONFIG_MBUF_IMPL_MODE == 1) + void *mbuf; +#endif +}; + +struct ducc_param_wlan_mon_input { + void *nif; + uint8_t *data; + uint32_t len; + void *info; +}; + +#if (__CONFIG_MBUF_IMPL_MODE == 1) +struct ducc_param_mbuf_get { + int len; + int tx; + void *mbuf; +}; +#endif + +#define DUCC_WLAN_BIN_TYPE_BL (0) +#define DUCC_WLAN_BIN_TYPE_FW (1) +#define DUCC_WLAN_BIN_TYPE_SDD (2) + +struct ducc_param_wlan_bin { + int type; + int index; + int len; + void *buf; +}; + +struct ducc_param_efuse { + uint8_t *data; + uint32_t start_bit; + uint32_t bit_num; +}; + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_NET_CORE)) + +typedef int (*ducc_cb_func)(uint32_t param0, uint32_t param1); + +struct ducc_net_param { + ducc_cb_func cb; +}; + +int ducc_net_start(struct ducc_net_param *param); +int ducc_net_ioctl(enum ducc_net_cmd cmd, void *param); + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_NET_CORE)) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_NET_H_ */ diff --git a/platform/mcu/xr871/include/sys/endian.h b/platform/mcu/xr871/include/sys/endian.h new file mode 100644 index 0000000000..505d496c2c --- /dev/null +++ b/platform/mcu/xr871/include/sys/endian.h @@ -0,0 +1,234 @@ +/*- + * Copyright (c) 2002 Thomas Moestl + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: releng/10.1/sys/sys/endian.h 208331 2010-05-20 06:16:13Z phk $ + */ + +#ifndef _SYS_ENDIAN_H_ +#define _SYS_ENDIAN_H_ + +#include "types.h" +#include "sys/defs.h" + +/* TODO: Optimize it */ +#define __bswap16(x) ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define __bswap32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define __bswap64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +/* + * General byte order swapping functions. + */ +#define bswap16(x) __bswap16(x) +#define bswap32(x) __bswap32(x) +#define bswap64(x) __bswap64(x) + +/* + * Host to big endian, host to little endian, big endian to host, and little + * endian to host byte order functions as detailed in byteorder(9). + */ +#if _BYTE_ORDER == _LITTLE_ENDIAN +#define htobe16(x) bswap16((x)) +#define htobe32(x) bswap32((x)) +#define htobe64(x) bswap64((x)) +#define htole16(x) ((uint16_t)(x)) +#define htole32(x) ((uint32_t)(x)) +#define htole64(x) ((uint64_t)(x)) + +#define be16toh(x) bswap16((x)) +#define be32toh(x) bswap32((x)) +#define be64toh(x) bswap64((x)) +#define le16toh(x) ((uint16_t)(x)) +#define le32toh(x) ((uint32_t)(x)) +#define le64toh(x) ((uint64_t)(x)) +#elif (_BYTE_ORDER == _BIG_ENDIAN) +#define htobe16(x) ((uint16_t)(x)) +#define htobe32(x) ((uint32_t)(x)) +#define htobe64(x) ((uint64_t)(x)) +#define htole16(x) bswap16((x)) +#define htole32(x) bswap32((x)) +#define htole64(x) bswap64((x)) + +#define be16toh(x) ((uint16_t)(x)) +#define be32toh(x) ((uint32_t)(x)) +#define be64toh(x) ((uint64_t)(x)) +#define le16toh(x) bswap16((x)) +#define le32toh(x) bswap32((x)) +#define le64toh(x) bswap64((x)) +#else +#error "Endian not defined!" +#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */ + +#define __cpu_to_le64(x) htole64(x) +#define __le64_to_cpu(x) le64toh(x) +#define __cpu_to_le32(x) htole32(x) +#define __le32_to_cpu(x) le32toh(x) +#define __cpu_to_le16(x) htole16(x) +#define __le16_to_cpu(x) le16toh(x) +#define __cpu_to_be64(x) htobe64(x) +#define __be64_to_cpu(x) be64toh(x) +#define __cpu_to_be32(x) htobe32(x) +#define __be32_to_cpu(x) be32toh(x) +#define __cpu_to_be16(x) htobe16(x) +#define __be16_to_cpu(x) be16toh(x) + +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu + + +/* Alignment-agnostic encode/decode bytestream to/from little/big endian. */ + +static __inline uint16_t +be16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[0] << 8) | p[1]); +} + +static __inline uint32_t +be32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]); +} + +static __inline uint64_t +be64dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((uint64_t)be32dec(p) << 32) | be32dec(p + 4)); +} + +static __inline uint16_t +le16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static __inline uint32_t +le32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((unsigned)p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static __inline uint64_t +le64dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((uint64_t)le32dec(p + 4) << 32) | le32dec(p)); +} + +static __inline void +be16enc(void *pp, uint16_t u) +{ + uint8_t *p = (uint8_t *)pp; + + p[0] = (u >> 8) & 0xff; + p[1] = u & 0xff; +} + +static __inline void +be32enc(void *pp, uint32_t u) +{ + uint8_t *p = (uint8_t *)pp; + + p[0] = (u >> 24) & 0xff; + p[1] = (u >> 16) & 0xff; + p[2] = (u >> 8) & 0xff; + p[3] = u & 0xff; +} + +static __inline void +be64enc(void *pp, uint64_t u) +{ + uint8_t *p = (uint8_t *)pp; + + be32enc(p, (uint32_t)(u >> 32)); + be32enc(p + 4, (uint32_t)(u & 0xffffffffU)); +} + +static __inline void +le16enc(void *pp, uint16_t u) +{ + uint8_t *p = (uint8_t *)pp; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; +} + +static __inline void +le32enc(void *pp, uint32_t u) +{ + uint8_t *p = (uint8_t *)pp; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; + p[2] = (u >> 16) & 0xff; + p[3] = (u >> 24) & 0xff; +} + +static __inline void +le64enc(void *pp, uint64_t u) +{ + uint8_t *p = (uint8_t *)pp; + + le32enc(p, (uint32_t)(u & 0xffffffffU)); + le32enc(p + 4, (uint32_t)(u >> 32)); +} + +#endif /* _SYS_ENDIAN_H_ */ diff --git a/platform/mcu/xr871/include/sys/fdcm.h b/platform/mcu/xr871/include/sys/fdcm.h new file mode 100644 index 0000000000..859a039cc2 --- /dev/null +++ b/platform/mcu/xr871/include/sys/fdcm.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_FDCM_H_ +#define _SYS_FDCM_H_ + +#include "types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief FDCM handle definition + */ +typedef struct fdcm_handle { + uint32_t flash; + uint32_t addr; + uint32_t size; +} fdcm_handle_t; + +fdcm_handle_t *fdcm_open(uint32_t flash, uint32_t addr, uint32_t size); +uint32_t fdcm_read(fdcm_handle_t *hdl, void *data, uint16_t data_size); +uint32_t fdcm_write(fdcm_handle_t *hdl, void *data, uint16_t data_size); +void fdcm_close(fdcm_handle_t *hdl); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_FDCM_H_ */ diff --git a/platform/mcu/xr871/include/sys/image.h b/platform/mcu/xr871/include/sys/image.h new file mode 100644 index 0000000000..87811dba58 --- /dev/null +++ b/platform/mcu/xr871/include/sys/image.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_IMAGE_H_ +#define _SYS_IMAGE_H_ + +#include "types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IMAGE_INVALID_FLASH (0xFFFFFFFF) +#define IMAGE_INVALID_ADDR (0xFFFFFFFF) + +/** + * @brief Image sequence definition + */ +typedef enum image_sequence { + IMAGE_SEQ_1ST = 0, + IMAGE_SEQ_2ND = 1, + IMAGE_SEQ_NUM = 2, +} image_seq_t; + +/** + * @brief Image segment definition + */ +typedef enum image_segment { + IMAGE_SEG_HEADER = 0, + IMAGE_SEG_BODY = 1, + IMAGE_SEG_TAILER = 2, +} image_seg_t; + +/** + * @brief Image validity definition + */ +typedef enum image_validity { + IMAGE_INVALID = 0, + IMAGE_VALID = 1, +} image_val_t; + +/** + * @brief Section header magic number definition (AWIH) + */ +#define IMAGE_MAGIC_NUMBER (0x48495741) + +/** + * @brief Section ID definition + */ +#define IMAGE_BOOT_ID (0xA5FF5A00) +#define IMAGE_APP_ID (0xA5FE5A01) +#define IMAGE_APP_XIP_ID (0xA5FD5A02) +#define IMAGE_NET_ID (0xA5FC5A03) +#define IMAGE_NET_AP_ID (0xA5FB5A04) +#define IMAGE_WLAN_BL_ID (0xA5FA5A05) +#define IMAGE_WLAN_FW_ID (0xA5F95A06) +#define IMAGE_WLAN_SDD_ID (0xA5F85A07) + +/** + * @brief Section header definition (64 Bytes) + */ +typedef struct section_header { + uint32_t magic_number; /* magic number */ + uint32_t version; /* version */ + uint16_t header_chksum; /* header checksum */ + uint16_t data_chksum; /* data checksum */ + uint32_t data_size; /* data size */ + uint32_t load_addr; /* load address */ + uint32_t entry; /* entry point */ + uint32_t body_len; /* body length */ + uint32_t attribute; /* attribute */ + uint32_t next_addr; /* next section address */ + uint32_t id; /* section ID */ + uint32_t priv[6]; /* private data */ +} section_header_t; + +#define IMAGE_HEADER_SIZE sizeof(section_header_t) + +/** + * @brief OTA parameter definition + */ +typedef struct image_ota_param { + uint32_t flash[IMAGE_SEQ_NUM]; + uint32_t addr[IMAGE_SEQ_NUM]; + uint32_t image_size; + uint32_t boot_size; +} image_ota_param_t; + +void image_init(uint32_t flash, uint32_t addr, uint32_t size); +void image_deinit(void); + +void image_get_ota_param(image_ota_param_t *param); + +void image_set_running_seq(image_seq_t seq); +void image_get_running_seq(image_seq_t *seq); + +uint32_t image_get_section_addr(uint32_t id); + +uint32_t image_read(uint32_t id, image_seg_t seg, uint32_t offset, void *buf, uint32_t size); +uint32_t image_write(uint32_t id, image_seg_t seg, uint32_t offset, void *buf, uint32_t size); + +uint16_t image_get_checksum(void *buf, uint32_t len); + +image_val_t image_check_header(section_header_t *sh); +image_val_t image_check_data(section_header_t *sh, void *body, uint32_t body_len, + void *tailer, uint32_t tailer_len); + +image_val_t image_check_section(image_seq_t seq, uint32_t id); +image_val_t image_check_sections(image_seq_t seq); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_IMAGE_H_ */ diff --git a/platform/mcu/xr871/include/sys/interrupt.h b/platform/mcu/xr871/include/sys/interrupt.h new file mode 100644 index 0000000000..6d64e1c60d --- /dev/null +++ b/platform/mcu/xr871/include/sys/interrupt.h @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_INTERRUPT_H_ +#define _SYS_INTERRUPT_H_ + +#include "compiler.h" + +#if defined(__CC_ARM) +/* ARM Compiler */ + +/* + * CPU interrupt mask handling. + */ +#define IRQMASK_REG_NAME_R primask +#define IRQMASK_REG_NAME_W primask + +/* + * Save the current interrupt enable state & disable IRQs + */ +static __always_inline unsigned long arch_irq_save(void) +{ + unsigned long flags; + + __asm { + mrs flags, IRQMASK_REG_NAME_R + cpsid i + } + return flags; +} + +/* + * restore saved IRQ state + */ +static __always_inline void arch_irq_restore(unsigned long flags) +{ + __asm { msr IRQMASK_REG_NAME_W, flags } +} + +/* + * Enable IRQs + */ +#define arch_irq_enable() __enable_irq() + +/* + * Disable IRQs + */ +#define arch_irq_disable() __disable_irq() + +/* + * Enable FIQs + */ +#define arch_fiq_enable() __enable_fiq() + +/* + * Disable FIQs + */ +#define arch_fiq_disable() __disable_fiq() + +#elif defined(__GNUC__) +/* GNU Compiler */ + +/* + * CPU interrupt mask handling. + */ +#define IRQMASK_REG_NAME_R "primask" +#define IRQMASK_REG_NAME_W "primask" + +/* + * Save the current interrupt enable state & disable IRQs + */ +static __always_inline unsigned long arch_irq_save(void) +{ + unsigned long flags; + + __asm volatile( + "mrs %0, " IRQMASK_REG_NAME_R "\n" + "cpsid i" + : "=r" (flags) : : "memory", "cc"); + return flags; +} + +/* + * restore saved IRQ state + */ +static __always_inline void arch_irq_restore(unsigned long flags) +{ + __asm volatile( + "msr " IRQMASK_REG_NAME_W ", %0" + : + : "r" (flags) + : "memory", "cc"); +} + +/* + * Save the current interrupt enable state. + */ +static __always_inline unsigned long arch_irq_get_flags(void) +{ + unsigned long flags; + + __asm volatile( + "mrs %0, " IRQMASK_REG_NAME_R "\n" + : "=r" (flags) : : "memory", "cc"); + return flags; + +} + +/* + * Enable IRQs + */ +#define arch_irq_enable() __asm volatile("cpsie i" : : : "memory", "cc") + +/* + * Disable IRQs + */ +#define arch_irq_disable() __asm volatile("cpsid i" : : : "memory", "cc") + +/* + * Enable FIQs + */ +#define arch_fiq_enable() __asm volatile("cpsie f" : : : "memory", "cc") + +/* + * Disable FIQs + */ +#define arch_fiq_disable() __asm volatile("cpsid f" : : : "memory", "cc") + +#else +#error "Compiler not supported." +#endif + +#endif /* _SYS_INTERRUPT_H_ */ diff --git a/platform/mcu/xr871/include/sys/io.h b/platform/mcu/xr871/include/sys/io.h new file mode 100644 index 0000000000..84aa5e01e6 --- /dev/null +++ b/platform/mcu/xr871/include/sys/io.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IO_H +#define _IO_H + +#include +#include + +#define BIT(nr) (1UL << (nr)) + +#define get_bvalue(addr) (*((volatile unsigned char *)(addr))) +#define put_bvalue(addr, v) (*((volatile unsigned char *)(addr)) = (unsigned char)(v)) +#define get_hvalue(addr) (*((volatile unsigned short *)(addr))) +#define put_hvalue(addr, v) (*((volatile unsigned short *)(addr)) = (unsigned short)(v)) +#define get_wvalue(addr) (*((volatile unsigned long *)(addr))) +#define put_wvalue(addr, v) (*((volatile unsigned long *)(addr)) = (unsigned long)(v)) + +#define set_bit(addr, v) (*((volatile unsigned char *)(addr)) |= (unsigned char)(v)) +#define clr_bit(addr, v) (*((volatile unsigned char *)(addr)) &= ~(unsigned char)(v)) +#define set_bbit(addr, v) (*((volatile unsigned char *)(addr)) |= (unsigned char)(v)) +#define clr_bbit(addr, v) (*((volatile unsigned char *)(addr)) &= ~(unsigned char)(v)) +#define set_hbit(addr, v) (*((volatile unsigned short *)(addr)) |= (unsigned short)(v)) +#define clr_hbit(addr, v) (*((volatile unsigned short *)(addr)) &= ~(unsigned short)(v)) +#define set_wbit(addr, v) (*((volatile unsigned long *)(addr)) |= (unsigned long)(v)) +#define clr_wbit(addr, v) (*((volatile unsigned long *)(addr)) &= ~(unsigned long)(v)) + +#define readb(addr) (*((volatile unsigned char *)(addr))) +#define readw(addr) (*((volatile unsigned short *)(addr))) +#define readl(addr) (*((volatile unsigned long *)(addr))) +#define writeb(v, addr) (*((volatile unsigned char *)(addr)) = (unsigned char)(v)) +#define writew(v, addr) (*((volatile unsigned short *)(addr)) = (unsigned short)(v)) +#define writel(v, addr) (*((volatile unsigned long *)(addr)) = (unsigned long)(v)) + +#define ARRAY_SIZE(n) (sizeof(n)/sizeof(n[0])) + +/** + * sr32 - clear & set a value in a bit range for a 32 bit address + */ +static __inline void sr32(unsigned int addr, unsigned int start_bit, unsigned int num_bits, unsigned int value) +{ + unsigned int tmp, msk = (1 << num_bits) - 1; + tmp = readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + writel(tmp, addr); +} + +#endif /* _IO_H */ diff --git a/platform/mcu/xr871/include/sys/list.h b/platform/mcu/xr871/include/sys/list.h new file mode 100644 index 0000000000..daa43e9781 --- /dev/null +++ b/platform/mcu/xr871/include/sys/list.h @@ -0,0 +1,584 @@ +#ifndef _SYS_LIST_H +#define _SYS_LIST_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "compiler.h" + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD_DEF(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *newl, + struct list_head *prev, + struct list_head *next) +{ + next->prev = newl; + newl->next = next; + newl->prev = prev; + prev->next = newl; +} + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *newl, struct list_head *head) +{ + __list_add(newl, head, head->next); +} + + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *newl, struct list_head *head) +{ + __list_add(newl, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +static inline void __list_del_entry(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); +} + +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = entry; + entry->prev = entry; +} + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static inline void list_replace(struct list_head *old, struct list_head *newl) +{ + newl->next = old->next; + newl->next->prev = newl; + newl->prev = old->prev; + newl->prev->next = newl; +} + +static inline void list_replace_init(struct list_head *old, + struct list_head *newl) +{ + list_replace(old, newl); + INIT_LIST_HEAD(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del_entry(entry); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del_entry(list); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del_entry(list); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static inline int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_rotate_left - rotate the list to the left + * @head: the head of the list + */ +static inline void list_rotate_left(struct list_head *head) +{ + struct list_head *first; + + if (!list_empty(head)) { + first = head->next; + list_move_tail(first, head); + } +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static inline int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static inline void __list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + * + */ +static inline void list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && + (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static inline void __list_splice(const struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static inline void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_head within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_head within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_last_entry - get the last element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_head within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_last_entry(ptr, type, member) \ + list_entry((ptr)->prev, type, member) + +/** + * list_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_head within the struct. + * + * Note that if the list is empty, it returns NULL. + */ +#define list_first_entry_or_null(ptr, type, member) \ + (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL) + +/** + * list_next_entry - get the next element in list + * @pos: the type * to cursor + * @member: the name of the list_head within the struct. + */ +#define list_next_entry(pos, member) \ + list_entry((pos)->member.next, typeof(*(pos)), member) + +/** + * list_prev_entry - get the prev element in list + * @pos: the type * to cursor + * @member: the name of the list_head within the struct. + */ +#define list_prev_entry(pos, member) \ + list_entry((pos)->member.prev, typeof(*(pos)), member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_first_entry(head, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_next_entry(pos, member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_last_entry(head, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_prev_entry(pos, member)) + +/** + * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_head within the struct. + * + * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_next_entry(pos, member); \ + &pos->member != (head); \ + pos = list_next_entry(pos, member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = list_prev_entry(pos, member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; &pos->member != (head); \ + pos = list_next_entry(pos, member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_head within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_first_entry(head, typeof(*pos), member), \ + n = list_next_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_next_entry(n, member)) + +/** + * list_for_each_entry_safe_continue - continue list iteration safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_next_entry(pos, member), \ + n = list_next_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_next_entry(n, member)) + +/** + * list_for_each_entry_safe_from - iterate over list from current point safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_next_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_next_entry(n, member)) + +/** + * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_last_entry(head, typeof(*pos), member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) + +/** + * list_safe_reset_next - reset a stale list_for_each_entry_safe loop + * @pos: the loop cursor used in the list_for_each_entry_safe loop + * @n: temporary storage used in list_for_each_entry_safe + * @member: the name of the list_head within the struct. + * + * list_safe_reset_next is not safe to use in general if the list may be + * modified concurrently (eg. the lock is dropped in the loop body). An + * exception to this is if the cursor element (pos) is pinned in the list, + * and list_safe_reset_next is called after re-taking the lock and before + * completing the current iteration of the loop body. + */ +#define list_safe_reset_next(pos, n, member) \ + n = list_next_entry(pos, member) + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_LIST_H */ diff --git a/platform/mcu/xr871/include/sys/mbuf.h b/platform/mcu/xr871/include/sys/mbuf.h new file mode 100644 index 0000000000..1c292a4eb9 --- /dev/null +++ b/platform/mcu/xr871/include/sys/mbuf.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_MBUF_H_ +#define _SYS_MBUF_H_ + +#if (__CONFIG_MBUF_IMPL_MODE == 0) +#include "sys/mbuf_0.h" +#elif (__CONFIG_MBUF_IMPL_MODE == 1) +#include "sys/mbuf_1.h" +#else +#error "Invalid __CONFIG_MBUF_IMPL_MODE!" +#endif + +#endif /* !_SYS_MBUF_H_ */ diff --git a/platform/mcu/xr871/include/sys/mbuf_0.h b/platform/mcu/xr871/include/sys/mbuf_0.h new file mode 100644 index 0000000000..d239987574 --- /dev/null +++ b/platform/mcu/xr871/include/sys/mbuf_0.h @@ -0,0 +1,157 @@ +/*- + * Copyright (c) 1982, 1986, 1988, 1993 + * The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)mbuf.h 8.5 (Berkeley) 2/19/95 + * $FreeBSD: releng/10.1/sys/sys/mbuf.h 269047 2014-07-24 06:03:45Z kevlo $ + */ + +#ifndef _SYS_MBUF_0_H_ +#define _SYS_MBUF_0_H_ + +#if (__CONFIG_MBUF_IMPL_MODE == 0) + +#include +#ifdef __CONFIG_ARCH_DUAL_CORE +#include "sys/ducc/ducc_addr.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Callback structure + */ +struct m_cb { + void *func; + void *arg; +}; + +/* + * Record/packet header in first mbuf of chain; always valid and M_PKTHDR is set. + * Size : 24 + */ +struct pkthdr { + void *rcvif; /* rcv interface */ + int32_t len; /* total packet length */ + + union { + uint8_t eigth[8]; + uint16_t sixteen[4]; + uint32_t thirtytwo[2]; + uint64_t sixtyfour[1]; + uintptr_t unintptr[1]; + void *ptr; + } PH_per; + + struct m_cb cb; +}; +#define ether_vtag PH_per.sixteen[0] +#define PH_vt PH_per +#define vt_nrecs sixteen[0] +#define tso_segsz PH_per.sixteen[1] +#define csum_phsum PH_per.sixteen[2] +#define csum_data PH_per.thirtytwo[1] + +/* + * The core of the mbuf object along with some shortcut defines for practical + * purposes. + */ +struct mbuf { // Size : 48 + /* + * Header present at the beginning of every mbuf. + * Size : 24 + */ + uint8_t *m_buf; /* a continuous buffer */ // useless now + struct mbuf *m_nextpkt; /* next chain in queue/record */ + uint8_t *m_data; /* location of data */ + int32_t m_len; /* amount of data in this mbuf */ + uint16_t m_headspace; /* empty space available at the head */ + uint16_t m_tailspace; /* empty space available at the tail */ + uint32_t m_type :8, /* type of data in this mbuf */ // useless now + m_flags :24; /* flags; see below */ + /*** End of the mbuf header ***/ + + struct pkthdr m_pkthdr; /* M_PKTHDR always set */ +}; + +#ifdef __CONFIG_ARCH_DUAL_CORE +/* + * NB: mbuf is allocated from net core, pointer conversion MUST be done when + * transfer mbuf from app core to net core, or vice versa. + */ + +#ifdef __CONFIG_ARCH_NET_CORE +/* convert mbuf's pointers in net core, the new mbuf is used by net core */ +#define MBUF_APP2NET(m) \ + do { \ + (m) = (struct mbuf *)DUCC_NETMEM_APP2NET(m); \ + (m)->m_data = (uint8_t *)DUCC_NETMEM_APP2NET((m)->m_data); \ + } while (0) + +/* convert mbuf's pointers in net core, the new mbuf is used by app core */ +#define MBUF_NET2APP(m) \ + do { \ + (m)->m_data = (uint8_t *)DUCC_NETMEM_NET2APP((m)->m_data); \ + (m) = (struct mbuf *)DUCC_NETMEM_NET2APP(m); \ + } while (0) +#endif /* __CONFIG_ARCH_NET_CORE */ + +#ifdef __CONFIG_ARCH_APP_CORE +/* convert mbuf's pointers in app core, the new mbuf is used by net core */ +#define MBUF_APP2NET(m) \ + do { \ + (m)->m_data = (uint8_t *)DUCC_NETMEM_APP2NET((m)->m_data); \ + (m) = (struct mbuf *)DUCC_NETMEM_APP2NET(m); \ + } while (0) + +/* convert mbuf's pointers in app core, the new mbuf is used by app core */ +#define MBUF_NET2APP(m) \ + do { \ + (m) = (struct mbuf *)DUCC_NETMEM_NET2APP(m); \ + (m)->m_data = (uint8_t *)DUCC_NETMEM_NET2APP((m)->m_data); \ + } while (0) +#endif /* __CONFIG_ARCH_APP_CORE */ + +#endif /* __CONFIG_ARCH_DUAL_CORE */ + +/* + * Macro for type conversion: convert mbuf pointer to data pointer of correct + * type: + * + * mtod(m, t) -- Convert mbuf pointer to data pointer of correct type. + */ +#define mtod(m, t) ((t)((m)->m_data)) + +#ifdef __cplusplus +} +#endif + +#endif /* (__CONFIG_MBUF_IMPL_MODE == 0) */ +#endif /* !_SYS_MBUF_0_H_ */ diff --git a/platform/mcu/xr871/include/sys/mbuf_1.h b/platform/mcu/xr871/include/sys/mbuf_1.h new file mode 100644 index 0000000000..8c1fcba81b --- /dev/null +++ b/platform/mcu/xr871/include/sys/mbuf_1.h @@ -0,0 +1,244 @@ +/*- + * Copyright (c) 1982, 1986, 1988, 1993 + * The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)mbuf.h 8.5 (Berkeley) 2/19/95 + * $FreeBSD: releng/10.1/sys/sys/mbuf.h 269047 2014-07-24 06:03:45Z kevlo $ + */ + +#ifndef _SYS_MBUF_1_H_ +#define _SYS_MBUF_1_H_ + +#if (__CONFIG_MBUF_IMPL_MODE == 1) + +#include +#ifdef __CONFIG_ARCH_DUAL_CORE +#include "sys/ducc/ducc_addr.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Callback structure + */ +struct m_cb { + void *func; + void *arg; +}; + +/* + * Record/packet header in first mbuf of chain; always valid and M_PKTHDR is set. + * Size : 24 + */ +struct pkthdr { + void *rcvif; /* rcv interface */ + int32_t len; /* total packet length */ + + union { + uint8_t eigth[8]; + uint16_t sixteen[4]; + uint32_t thirtytwo[2]; + uint64_t sixtyfour[1]; + uintptr_t unintptr[1]; + void *ptr; + } PH_per; + + struct m_cb cb; +}; +#define ether_vtag PH_per.sixteen[0] +#define PH_vt PH_per +#define vt_nrecs sixteen[0] +#define tso_segsz PH_per.sixteen[1] +#define csum_phsum PH_per.sixteen[2] +#define csum_data PH_per.thirtytwo[1] + +/* + * The core of the mbuf object along with some shortcut defines for practical + * purposes. + */ +struct mbuf { // Size : 48 + /* + * Header present at the beginning of every mbuf. + * Size : 24 + */ + void *m_pbuf; /* only a single pbuf, not in chain */ + /* NB: All mbuf operations do not change the struct of pbuf. */ + struct mbuf *m_nextpkt; /* next chain in queue/record */ + uint8_t *m_data; /* location of data */ + int32_t m_len; /* amount of data in this mbuf */ + uint16_t m_headspace; /* empty space available at the head */ + uint16_t m_tailspace; /* empty space available at the tail */ + uint32_t m_type :8, /* type of data in this mbuf */ // useless now + m_flags :24; /* flags; see below */ + /*** End of the mbuf header ***/ + + struct pkthdr m_pkthdr; /* M_PKTHDR always set */ +}; + +#define MBUF_HEAD_SPACE 68 /* reserved head space in mbuf::m_buf, align to 4 */ +#define MBUF_TAIL_SPACE 16 /* reserved tail space in mbuf::m_buf, align to 4 */ + +/* + * mbuf flags of global significance and layer crossing. + * Those of only protocol/layer specific significance are to be mapped + * to M_PROTO[1-12] and cleared at layer handoff boundaries. + * NB: Limited to the lower 24 bits. + */ +#define M_EXT 0x00000001 /* has associated external storage */ +#define M_PKTHDR 0x00000002 /* start of record */ // always set +#define M_EOR 0x00000004 /* end of record */ +#define M_RDONLY 0x00000008 /* associated data is marked read-only */ +#define M_BCAST 0x00000010 /* send/received as link-level broadcast */ +#define M_MCAST 0x00000020 /* send/received as link-level multicast */ +#define M_PROMISC 0x00000040 /* packet was not for us */ +#define M_VLANTAG 0x00000080 /* ether_vtag is valid */ +#define M_FLOWID 0x00000100 /* deprecated: flowid is valid */ +#define M_NOFREE 0x00000200 /* do not free mbuf, embedded in cluster */ + +#define M_PROTO1 0x00001000 /* protocol-specific */ +#define M_PROTO2 0x00002000 /* protocol-specific */ +#define M_PROTO3 0x00004000 /* protocol-specific */ +#define M_PROTO4 0x00008000 /* protocol-specific */ +#define M_PROTO5 0x00010000 /* protocol-specific */ +#define M_PROTO6 0x00020000 /* protocol-specific */ +#define M_PROTO7 0x00040000 /* protocol-specific */ +#define M_PROTO8 0x00080000 /* protocol-specific */ +#define M_PROTO9 0x00100000 /* protocol-specific */ +#define M_PROTO10 0x00200000 /* protocol-specific */ +#define M_PROTO11 0x00400000 /* protocol-specific */ +#define M_PROTO12 0x00800000 /* protocol-specific */ + +/* + * Flags to purge when crossing layers. + */ +#define M_PROTOFLAGS \ + (M_PROTO1|M_PROTO2|M_PROTO3|M_PROTO4|M_PROTO5|M_PROTO6|M_PROTO7|M_PROTO8|\ + M_PROTO9|M_PROTO10|M_PROTO11|M_PROTO12) + +/* + * Flags preserved when copying m_pkthdr. + */ +#define M_COPYFLAGS \ + (M_PKTHDR|M_EOR|M_RDONLY|M_BCAST|M_MCAST|M_VLANTAG|M_PROMISC| \ + M_PROTOFLAGS) + +/* + * Mbuf flag description for use with printf(9) %b identifier. + */ +#define M_FLAG_BITS \ + "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY\5M_BCAST\6M_MCAST" \ + "\7M_PROMISC\10M_VLANTAG\11M_FLOWID" +#define M_FLAG_PROTOBITS \ + "\15M_PROTO1\16M_PROTO2\17M_PROTO3\20M_PROTO4\21M_PROTO5" \ + "\22M_PROTO6\23M_PROTO7\24M_PROTO8\25M_PROTO9\26M_PROTO10" \ + "\27M_PROTO11\30M_PROTO12" +#define M_FLAG_PRINTF (M_FLAG_BITS M_FLAG_PROTOBITS) + + +/* + * mbuf types describing the content of the mbuf (including external storage). + */ +#define MT_NOTMBUF 0 /* USED INTERNALLY ONLY! Object is not mbuf */ +#define MT_DATA 1 /* dynamic (data) allocation */ +#define MT_HEADER MT_DATA /* packet header, use M_PKTHDR instead */ + +#define MT_VENDOR1 4 /* for vendor-internal use */ +#define MT_VENDOR2 5 /* for vendor-internal use */ +#define MT_VENDOR3 6 /* for vendor-internal use */ +#define MT_VENDOR4 7 /* for vendor-internal use */ + +#define MT_SONAME 8 /* socket name */ + +#define MT_EXP1 9 /* for experimental use */ +#define MT_EXP2 10 /* for experimental use */ +#define MT_EXP3 11 /* for experimental use */ +#define MT_EXP4 12 /* for experimental use */ + +#define MT_CONTROL 14 /* extra-data protocol message */ +#define MT_OOBDATA 15 /* expedited data */ +#define MT_NTYPES 16 /* number of mbuf types for mbtypes[] */ + +#define MT_NOINIT 255 /* Not a type but a flag to allocate + a non-initialized mbuf */ + +#ifdef __CONFIG_ARCH_DUAL_CORE +/* + * NB: mbuf is allocated from app core, pointer conversion MUST be done when + * transfer mbuf from app core to net core, or vice versa. + */ + +#ifdef __CONFIG_ARCH_NET_CORE +/* convert mbuf's pointers in net core, the new mbuf is used by net core */ +#define MBUF_APP2NET(m) \ + do { \ + (m) = (struct mbuf *)DUCC_APPMEM_APP2NET(m); \ + (m)->m_data = (uint8_t *)DUCC_APPMEM_APP2NET((m)->m_data); \ + } while (0) + +/* convert mbuf's pointers in net core, the new mbuf is used by app core */ +#define MBUF_NET2APP(m) \ + do { \ + (m)->m_data = (uint8_t *)DUCC_APPMEM_NET2APP((m)->m_data); \ + (m) = (struct mbuf *)DUCC_APPMEM_NET2APP(m); \ + } while (0) +#endif /* __CONFIG_ARCH_NET_CORE */ + +#ifdef __CONFIG_ARCH_APP_CORE +/* convert mbuf's pointers in app core, the new mbuf is used by net core */ +#define MBUF_APP2NET(m) \ + do { \ + (m)->m_data = (uint8_t *)DUCC_APPMEM_APP2NET((m)->m_data); \ + (m) = (struct mbuf *)DUCC_APPMEM_APP2NET(m); \ + } while (0) + +/* convert mbuf's pointers in app core, the new mbuf is used by app core */ +#define MBUF_NET2APP(m) \ + do { \ + (m) = (struct mbuf *)DUCC_APPMEM_NET2APP(m); \ + (m)->m_data = (uint8_t *)DUCC_APPMEM_NET2APP((m)->m_data); \ + } while (0) +#endif /* __CONFIG_ARCH_APP_CORE */ + +#endif /* __CONFIG_ARCH_DUAL_CORE */ + +struct mbuf *mb_get(int len, int tx); +void mb_free(struct mbuf *m); + +#if (defined(__CONFIG_ARCH_APP_CORE) || !defined(__CONFIG_ARCH_DUAL_CORE)) +struct mbuf *mb_pbuf2mbuf(void *p); +void *mb_mbuf2pbuf(struct mbuf *m); +#endif /* (defined(__CONFIG_ARCH_APP_CORE) || !defined(__CONFIG_ARCH_DUAL_CORE)) */ + +#ifdef __cplusplus +} +#endif + +#endif /* (__CONFIG_MBUF_IMPL_MODE == 1) */ +#endif /* !_SYS_MBUF_1_H_ */ diff --git a/platform/mcu/xr871/include/sys/ota.h b/platform/mcu/xr871/include/sys/ota.h new file mode 100644 index 0000000000..f7421137ae --- /dev/null +++ b/platform/mcu/xr871/include/sys/ota.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_OTA_H_ +#define _SYS_OTA_H_ + +#include "types.h" +#include "sys/image.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief OTA status definition + */ +typedef enum ota_status { + OTA_STATUS_OK = 0, + OTA_STATUS_ERROR = -1, +} ota_status_t; + +/** + * @brief OTA image sequence definition + */ +typedef enum ota_image { + OTA_IMAGE_1ST = 1, + OTA_IMAGE_2ND = 2, +} ota_image_t; + +/** + * @brief OTA image verification state definition + */ +typedef enum ota_state { + OTA_STATE_UNVERIFIED = 0, + OTA_STATE_VERIFIED = 1, +} ota_state_t; + +/** + * @brief OTA configuration definition + */ +typedef struct ota_cfg { + ota_image_t image; + ota_state_t state; +} ota_cfg_t; + +/** + * @brief OTA protocol definition + */ +typedef enum ota_protocol { + OTA_PROTOCOL_FILE = 0, + OTA_PROTOCOL_HTTP = 1, +} ota_protocol_t; + +/** + * @brief OTA image verification algorithm definition + */ +typedef enum ota_verify { + OTA_VERIFY_NONE = 0, + OTA_VERIFY_CRC32 = 1, + OTA_VERIFY_MD5 = 2, + OTA_VERIFY_SHA1 = 3, + OTA_VERIFY_SHA256 = 4, +} ota_verify_t; + +ota_status_t ota_init(image_ota_param_t *param); +void ota_deinit(void); + +ota_status_t ota_read_cfg(ota_cfg_t *cfg); +ota_status_t ota_write_cfg(ota_cfg_t *cfg); + +ota_status_t ota_get_image(ota_protocol_t protocol, void *url); +ota_status_t ota_verify_image(ota_verify_t verify, uint32_t *value); +void ota_reboot(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_OTA_H_ */ diff --git a/platform/mcu/xr871/include/sys/param.h b/platform/mcu/xr871/include/sys/param.h new file mode 100644 index 0000000000..1ce5f943a1 --- /dev/null +++ b/platform/mcu/xr871/include/sys/param.h @@ -0,0 +1,68 @@ +/*- + * Copyright (c) 1982, 1986, 1989, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)param.h 8.3 (Berkeley) 4/4/95 + * $FreeBSD: releng/10.1/sys/sys/param.h 272463 2014-10-03 00:58:34Z gjb $ + */ + +#ifndef _SYS_PARAM_H_ +#define _SYS_PARAM_H_ + +#define NBBY 8 /* number of bits in a byte */ +#define NBPW sizeof(int) /* number of bytes per word (integer) */ + +/* Bit map related macros. */ +#define setbit(a,i) (((unsigned char *)(a))[(i)/NBBY] |= 1<<((i)%NBBY)) +#define clrbit(a,i) (((unsigned char *)(a))[(i)/NBBY] &= ~(1<<((i)%NBBY))) +#define isset(a,i) \ + (((const unsigned char *)(a))[(i)/NBBY] & (1<<((i)%NBBY))) +#define isclr(a,i) \ + ((((const unsigned char *)(a))[(i)/NBBY] & (1<<((i)%NBBY))) == 0) + +/* Macros for counting and rounding. */ +#ifndef howmany +#define howmany(x, y) (((x)+((y)-1))/(y)) +#endif +#define nitems(x) (sizeof((x)) / sizeof((x)[0])) +#define rounddown(x, y) (((x)/(y))*(y)) +#define rounddown2(x, y) ((x)&(~((y)-1))) /* if y is power of two */ +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ +#define roundup2(x, y) (((x)+((y)-1))&(~((y)-1))) /* if y is powers of two */ +#define powerof2(x) ((((x)-1)&(x))==0) + +/* Macros for min/max. */ +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#endif /* _SYS_PARAM_H_ */ diff --git a/platform/mcu/xr871/include/sys/queue.h b/platform/mcu/xr871/include/sys/queue.h new file mode 100644 index 0000000000..1f6ab00fd1 --- /dev/null +++ b/platform/mcu/xr871/include/sys/queue.h @@ -0,0 +1,694 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: releng/10.1/sys/sys/queue.h 251887 2013-06-18 02:57:56Z lstewart $ + */ + +#ifndef _SYS_QUEUE_H_ +#define _SYS_QUEUE_H_ + +#include "sys/defs.h" + +/* + * This file defines four types of data structures: singly-linked lists, + * singly-linked tail queues, lists and tail queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may be traversed in either direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ + * _HEAD + + + + + * _HEAD_INITIALIZER + + + + + * _ENTRY + + + + + * _INIT + + + + + * _EMPTY + + + + + * _FIRST + + + + + * _NEXT + + + + + * _PREV - + - + + * _LAST - - + + + * _FOREACH + + + + + * _FOREACH_FROM + + + + + * _FOREACH_SAFE + + + + + * _FOREACH_FROM_SAFE + + + + + * _FOREACH_REVERSE - - - + + * _FOREACH_REVERSE_FROM - - - + + * _FOREACH_REVERSE_SAFE - - - + + * _FOREACH_REVERSE_FROM_SAFE - - - + + * _INSERT_HEAD + + + + + * _INSERT_BEFORE - + - + + * _INSERT_AFTER + + + + + * _INSERT_TAIL - - + + + * _CONCAT - - + + + * _REMOVE_AFTER + - + - + * _REMOVE_HEAD + - + - + * _REMOVE + + + + + * _SWAP + + + + + * + */ +#ifdef QUEUE_MACRO_DEBUG +/* Store the last 2 places the queue element or head was altered */ +struct qm_trace { + unsigned long lastline; + unsigned long prevline; + const char *lastfile; + const char *prevfile; +}; + +#define TRACEBUF struct qm_trace trace; +#define TRACEBUF_INITIALIZER { __FILE__, __LINE__, NULL, 0 } , +#define TRASHIT(x) do {(x) = (void *)-1;} while (0) +#define QMD_SAVELINK(name, link) void **name = (void *)&(link) + +#define QMD_TRACE_HEAD(head) do { \ + (head)->trace.prevline = (head)->trace.lastline; \ + (head)->trace.prevfile = (head)->trace.lastfile; \ + (head)->trace.lastline = __LINE__; \ + (head)->trace.lastfile = __FILE__; \ +} while (0) + +#define QMD_TRACE_ELEM(elem) do { \ + (elem)->trace.prevline = (elem)->trace.lastline; \ + (elem)->trace.prevfile = (elem)->trace.lastfile; \ + (elem)->trace.lastline = __LINE__; \ + (elem)->trace.lastfile = __FILE__; \ +} while (0) + +#else +#define QMD_TRACE_ELEM(elem) +#define QMD_TRACE_HEAD(head) +#define QMD_SAVELINK(name, link) +#define TRACEBUF +#define TRACEBUF_INITIALIZER +#define TRASHIT(x) +#endif /* QUEUE_MACRO_DEBUG */ + +/* + * Singly-linked List declarations. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for ((var) = SLIST_FIRST((head)); \ + (var); \ + (var) = SLIST_NEXT((var), field)) + +#define SLIST_FOREACH_FROM(var, head, field) \ + for ((var) = ((var) ? (var) : SLIST_FIRST((head))); \ + (var); \ + (var) = SLIST_NEXT((var), field)) + +#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = SLIST_FIRST((head)); \ + (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define SLIST_FOREACH_FROM_SAFE(var, head, field, tvar) \ + for ((var) = ((var) ? (var) : SLIST_FIRST((head))); \ + (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ + for ((varp) = &SLIST_FIRST((head)); \ + ((var) = *(varp)) != NULL; \ + (varp) = &SLIST_NEXT((var), field)) + +#define SLIST_INIT(head) do { \ + SLIST_FIRST((head)) = NULL; \ +} while (0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ + SLIST_NEXT((slistelm), field) = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ + SLIST_FIRST((head)) = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.sle_next); \ + if (SLIST_FIRST((head)) == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = SLIST_FIRST((head)); \ + while (SLIST_NEXT(curelm, field) != (elm)) \ + curelm = SLIST_NEXT(curelm, field); \ + SLIST_REMOVE_AFTER(curelm, field); \ + } \ + TRASHIT(*oldnext); \ +} while (0) + +#define SLIST_REMOVE_AFTER(elm, field) do { \ + SLIST_NEXT(elm, field) = \ + SLIST_NEXT(SLIST_NEXT(elm, field), field); \ +} while (0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ +} while (0) + +#define SLIST_SWAP(head1, head2, type) do { \ + struct type *swap_first = SLIST_FIRST(head1); \ + SLIST_FIRST(head1) = SLIST_FIRST(head2); \ + SLIST_FIRST(head2) = swap_first; \ +} while (0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_CONCAT(head1, head2) do { \ + if (!STAILQ_EMPTY((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_INIT((head2)); \ + } \ +} while (0) + +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = STAILQ_FIRST((head)); \ + (var); \ + (var) = STAILQ_NEXT((var), field)) + +#define STAILQ_FOREACH_FROM(var, head, field) \ + for ((var) = ((var) ? (var) : STAILQ_FIRST((head))); \ + (var); \ + (var) = STAILQ_NEXT((var), field)) + +#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = STAILQ_FIRST((head)); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_FOREACH_FROM_SAFE(var, head, field, tvar) \ + for ((var) = ((var) ? (var) : STAILQ_FIRST((head))); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_INIT(head) do { \ + STAILQ_FIRST((head)) = NULL; \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_NEXT((tqelm), field) = (elm); \ +} while (0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_FIRST((head)) = (elm); \ +} while (0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + STAILQ_NEXT((elm), field) = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY((head)) ? NULL : \ + __containerof((head)->stqh_last, struct type, field.stqe_next)) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \ + if (STAILQ_FIRST((head)) == (elm)) { \ + STAILQ_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = STAILQ_FIRST((head)); \ + while (STAILQ_NEXT(curelm, field) != (elm)) \ + curelm = STAILQ_NEXT(curelm, field); \ + STAILQ_REMOVE_AFTER(head, curelm, field); \ + } \ + TRASHIT(*oldnext); \ +} while (0) + +#define STAILQ_REMOVE_AFTER(head, elm, field) do { \ + if ((STAILQ_NEXT(elm, field) = \ + STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if ((STAILQ_FIRST((head)) = \ + STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_SWAP(head1, head2, type) do { \ + struct type *swap_first = STAILQ_FIRST(head1); \ + struct type **swap_last = (head1)->stqh_last; \ + STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_FIRST(head2) = swap_first; \ + (head2)->stqh_last = swap_last; \ + if (STAILQ_EMPTY(head1)) \ + (head1)->stqh_last = &STAILQ_FIRST(head1); \ + if (STAILQ_EMPTY(head2)) \ + (head2)->stqh_last = &STAILQ_FIRST(head2); \ +} while (0) + + +/* + * List declarations. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#if (defined(_KERNEL) && defined(INVARIANTS)) +#define QMD_LIST_CHECK_HEAD(head, field) do { \ + if (LIST_FIRST((head)) != NULL && \ + LIST_FIRST((head))->field.le_prev != \ + &LIST_FIRST((head))) \ + panic("Bad list head %p first->prev != head", (head)); \ +} while (0) + +#define QMD_LIST_CHECK_NEXT(elm, field) do { \ + if (LIST_NEXT((elm), field) != NULL && \ + LIST_NEXT((elm), field)->field.le_prev != \ + &((elm)->field.le_next)) \ + panic("Bad link elm %p next->prev != elm", (elm)); \ +} while (0) + +#define QMD_LIST_CHECK_PREV(elm, field) do { \ + if (*(elm)->field.le_prev != (elm)) \ + panic("Bad link elm %p prev->next != elm", (elm)); \ +} while (0) +#else +#define QMD_LIST_CHECK_HEAD(head, field) +#define QMD_LIST_CHECK_NEXT(elm, field) +#define QMD_LIST_CHECK_PREV(elm, field) +#endif /* (_KERNEL && INVARIANTS) */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = LIST_FIRST((head)); \ + (var); \ + (var) = LIST_NEXT((var), field)) + +#define LIST_FOREACH_FROM(var, head, field) \ + for ((var) = ((var) ? (var) : LIST_FIRST((head))); \ + (var); \ + (var) = LIST_NEXT((var), field)) + +#define LIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = LIST_FIRST((head)); \ + (var) && ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_FOREACH_FROM_SAFE(var, head, field, tvar) \ + for ((var) = ((var) ? (var) : LIST_FIRST((head))); \ + (var) && ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_INIT(head) do { \ + LIST_FIRST((head)) = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + QMD_LIST_CHECK_NEXT(listelm, field); \ + if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ + LIST_NEXT((listelm), field)->field.le_prev = \ + &LIST_NEXT((elm), field); \ + LIST_NEXT((listelm), field) = (elm); \ + (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + QMD_LIST_CHECK_PREV(listelm, field); \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + LIST_NEXT((elm), field) = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + QMD_LIST_CHECK_HEAD((head), field); \ + if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ + LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ + LIST_FIRST((head)) = (elm); \ + (elm)->field.le_prev = &LIST_FIRST((head)); \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_PREV(elm, head, type, field) \ + ((elm)->field.le_prev == &LIST_FIRST((head)) ? NULL : \ + __containerof((elm)->field.le_prev, struct type, field.le_next)) + +#define LIST_REMOVE(elm, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.le_next); \ + QMD_SAVELINK(oldprev, (elm)->field.le_prev); \ + QMD_LIST_CHECK_NEXT(elm, field); \ + QMD_LIST_CHECK_PREV(elm, field); \ + if (LIST_NEXT((elm), field) != NULL) \ + LIST_NEXT((elm), field)->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = LIST_NEXT((elm), field); \ + TRASHIT(*oldnext); \ + TRASHIT(*oldprev); \ +} while (0) + +#define LIST_SWAP(head1, head2, type, field) do { \ + struct type *swap_tmp = LIST_FIRST((head1)); \ + LIST_FIRST((head1)) = LIST_FIRST((head2)); \ + LIST_FIRST((head2)) = swap_tmp; \ + if ((swap_tmp = LIST_FIRST((head1))) != NULL) \ + swap_tmp->field.le_prev = &LIST_FIRST((head1)); \ + if ((swap_tmp = LIST_FIRST((head2))) != NULL) \ + swap_tmp->field.le_prev = &LIST_FIRST((head2)); \ +} while (0) + +/* + * Tail queue declarations. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + TRACEBUF \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first, TRACEBUF_INITIALIZER } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ + TRACEBUF \ +} + +/* + * Tail queue functions. + */ +#if (defined(_KERNEL) && defined(INVARIANTS)) +#define QMD_TAILQ_CHECK_HEAD(head, field) do { \ + if (!TAILQ_EMPTY(head) && \ + TAILQ_FIRST((head))->field.tqe_prev != \ + &TAILQ_FIRST((head))) \ + panic("Bad tailq head %p first->prev != head", (head)); \ +} while (0) + +#define QMD_TAILQ_CHECK_TAIL(head, field) do { \ + if (*(head)->tqh_last != NULL) \ + panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \ +} while (0) + +#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \ + if (TAILQ_NEXT((elm), field) != NULL && \ + TAILQ_NEXT((elm), field)->field.tqe_prev != \ + &((elm)->field.tqe_next)) \ + panic("Bad link elm %p next->prev != elm", (elm)); \ +} while (0) + +#define QMD_TAILQ_CHECK_PREV(elm, field) do { \ + if (*(elm)->field.tqe_prev != (elm)) \ + panic("Bad link elm %p prev->next != elm", (elm)); \ +} while (0) +#else +#define QMD_TAILQ_CHECK_HEAD(head, field) +#define QMD_TAILQ_CHECK_TAIL(head, headname) +#define QMD_TAILQ_CHECK_NEXT(elm, field) +#define QMD_TAILQ_CHECK_PREV(elm, field) +#endif /* (_KERNEL && INVARIANTS) */ + +#define TAILQ_CONCAT(head1, head2, field) do { \ + if (!TAILQ_EMPTY(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + TAILQ_INIT((head2)); \ + QMD_TRACE_HEAD(head1); \ + QMD_TRACE_HEAD(head2); \ + } \ +} while (0) + +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = TAILQ_FIRST((head)); \ + (var); \ + (var) = TAILQ_NEXT((var), field)) + +#define TAILQ_FOREACH_FROM(var, head, field) \ + for ((var) = ((var) ? (var) : TAILQ_FIRST((head))); \ + (var); \ + (var) = TAILQ_NEXT((var), field)) + +#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = TAILQ_FIRST((head)); \ + (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define TAILQ_FOREACH_FROM_SAFE(var, head, field, tvar) \ + for ((var) = ((var) ? (var) : TAILQ_FIRST((head))); \ + (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_FROM(var, head, headname, field) \ + for ((var) = ((var) ? (var) : TAILQ_LAST((head), headname)); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ + (var) = (tvar)) + +#define TAILQ_FOREACH_REVERSE_FROM_SAFE(var, head, headname, field, tvar) \ + for ((var) = ((var) ? (var) : TAILQ_LAST((head), headname)); \ + (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ + (var) = (tvar)) + +#define TAILQ_INIT(head) do { \ + TAILQ_FIRST((head)) = NULL; \ + (head)->tqh_last = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + QMD_TAILQ_CHECK_NEXT(listelm, field); \ + if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else { \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + } \ + TAILQ_NEXT((listelm), field) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + QMD_TAILQ_CHECK_PREV(listelm, field); \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + TAILQ_NEXT((elm), field) = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + QMD_TAILQ_CHECK_HEAD(head, field); \ + if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ + TAILQ_FIRST((head))->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + TAILQ_FIRST((head)) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + QMD_TAILQ_CHECK_TAIL(head, field); \ + TAILQ_NEXT((elm), field) = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_REMOVE(head, elm, field) do { \ + QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \ + QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \ + QMD_TAILQ_CHECK_NEXT(elm, field); \ + QMD_TAILQ_CHECK_PREV(elm, field); \ + if ((TAILQ_NEXT((elm), field)) != NULL) \ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else { \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + QMD_TRACE_HEAD(head); \ + } \ + *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ + TRASHIT(*oldnext); \ + TRASHIT(*oldprev); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_SWAP(head1, head2, type, field) do { \ + struct type *swap_first = (head1)->tqh_first; \ + struct type **swap_last = (head1)->tqh_last; \ + (head1)->tqh_first = (head2)->tqh_first; \ + (head1)->tqh_last = (head2)->tqh_last; \ + (head2)->tqh_first = swap_first; \ + (head2)->tqh_last = swap_last; \ + if ((swap_first = (head1)->tqh_first) != NULL) \ + swap_first->field.tqe_prev = &(head1)->tqh_first; \ + else \ + (head1)->tqh_last = &(head1)->tqh_first; \ + if ((swap_first = (head2)->tqh_first) != NULL) \ + swap_first->field.tqe_prev = &(head2)->tqh_first; \ + else \ + (head2)->tqh_last = &(head2)->tqh_first; \ +} while (0) + +#endif /* !_SYS_QUEUE_H_ */ diff --git a/platform/mcu/xr871/include/sys/xr_debug.h b/platform/mcu/xr871/include/sys/xr_debug.h new file mode 100644 index 0000000000..fb9d17c10c --- /dev/null +++ b/platform/mcu/xr871/include/sys/xr_debug.h @@ -0,0 +1,355 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XR_DEBUG_H__ +#define __XR_DEBUG_H__ + +#include "sys/xr_util.h" +#include +#include +#include +#include + +#define XR_DEBUG_ON + + +/* + * @brief Debug level + */ +#define DBG_LEVEL_MASK (0x0F) + + +#define XR_LEVEL_EMERG 0 + +#define XR_LEVEL_ALERT 1 + +#define XR_LEVEL_CRIT 2 + +#define XR_LEVEL_ERROR 3 + +#define XR_LEVEL_WARNING 4 + +#define XR_LEVEL_NOTICE 5 + +#define XR_LEVEL_INFO 6 + +#define XR_LEVEL_DEBUG 7 + +#define XR_LEVEL_ALL 0x0F + + +/* + * No expanded condition + */ +#define NOEXPAND 1 + + +/* + * module ON/OFF + */ +#define DBG_ON (1 << 4) + +#define DBG_OFF (0) + + +/* + * Always show message + */ +#define MOD_DBG_ALW_ON (DBG_ON | XR_LEVEL_ALL) + + +/************************************************************ + * XR_DEBUG INTERFACE + ************************************************************/ +#ifdef XR_DEBUG_ON + +#define XR_DEBUG_PRINT(msg, arg...) printf(msg, ##arg) + +#define XR_DEBUG_ABORT() do { \ + printf("system aborted!"); \ + sys_abort(); \ + } while (0) + + +/* + * @brief The realization of showing debug messages. + * @param module: Contained a module On/Off and a module debug level. + * @param dlevel: Debug message showed level for seal like MDEBUG. + * @param expand: Expanded condition if level param and module ON/OFF are not + * enough for developer. + * @param msg: The debug message. + * @param arg: Arguement shown in debug message which like printf arguement. + * @retval None + */ +#define _XR_DEBUG(module, dlevel, expand, msg, arg...) \ + do { \ + if ( \ + ((module) & DBG_ON) && \ + (((module) & DBG_LEVEL_MASK) >= dlevel) && \ + (expand)) { \ + XR_DEBUG_PRINT(msg, ##arg); \ + } \ + } while(0) + +/* + * @brief The realization of showing debug messages and it can't be turn off by + * module ON/OFF. + * @param module: Contained a module On/Off and a module debug level. + * @param dlevel: Debug message showed level for seal. + * @param expand: Expanded condition if level param is not enough for developer. + * @param msg: The debug message. + * @param arg: Arguement shown in debug message which like printf arguement. + * @retval None + */ +#define _XR_INFO(module, dlevel, expand, msg, arg...) \ + do { \ + if ( \ + (((int16_t)(module) & DBG_LEVEL_MASK) >= dlevel) && \ + (expand)) { \ + XR_DEBUG_PRINT(msg, ##arg); \ + } \ + } while(0) + +/* + * @brief The realization of assert debug messages shown the assert position, + * for example: "[Assert] At module_debug.h line 112 fun _MASSERT: **" + * @param module: Contained a module On/Off and a module debug level. + * @param dlevel: Debug message showed level for seal. + * @param msg: The debug message. + * @param arg: Arguement shown in debug message which like printf arguement. + * @retval None + */ +#define _XR_ASSERT(assert, module, dlevel, msg, arg...) \ + _XR_DEBUG(module, dlevel, !(assert), \ + "[Assert] At %s line %d fun %s: " msg, \ + __FILE__, __LINE__, __func__, ##arg) + +/* + * @brief The realization of assert debug messages shown the assert position, + * and abort. for example: "[Assert] At module_debug.h line 112 fun + * _MASSERT: ***" + * @param module: Contained a module On/Off and a module debug level. + * @param dlevel: Debug message showed level for seal. + * @param msg: The debug message. + * @param arg: Arguement shown in debug message which like printf arguement. + * @retval None + */ +#define _XR_ASSERT_ABORT(assert, module, dlevel, msg, arg...) \ + do { \ + if ((((int16_t)(module) & DBG_LEVEL_MASK) >= dlevel) && !(assert)) { \ + XR_DEBUG_PRINT("[Assert] At %s line %d fun %s: " msg, \ + __FILE__, __LINE__, __func__, ##arg); \ + XR_DEBUG_ABORT(); \ + } \ + } while(0) + + +/* + * @brief A level debug message + * @param module: Contained a module On/Off and a module debug level. + * @param expand: Expanded condition if level param and module ON/OFF are not + * enough for developer. + * @param msg: The debug message. + * @param arg: Arguement shown in debug message which like printf arguement. + * @retval None + */ +#define XR_ERROR(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_ERROR, expand, msg, ##arg) + +#define XR_ALERT(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_ALERT, expand, msg, ##arg) + +#define XR_CRIT(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_CRIT, expand, msg, ##arg) + +#define XR_EMERG(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_EMERG, XR_xpand, msg, ##arg) + +#define XR_WARN(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_WARNING, expand, msg, ##arg) + +#define XR_NOTICE(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_NOTICE, expand, msg, ##arg) + +#define XR_INFO(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_INFO, expand, msg, ##arg) + +#define XR_DEBUG(module, expand, msg, arg...) \ + _XR_DEBUG(module, XR_LEVEL_DEBUG, expand, msg, ##arg) + + +/* + * @brief Assert a full debug message with position(file, line, etc.) without level. + * for example: "[Assert] At module_debug.h line 112 fun _MASSERT: ***" + * @param assert: Debug condition + * @param module: Contained a module On/Off at least. + * @param msg: The debug message. + * @param arg: Arguement shown in debug message which like printf arguement. + * @retval None + */ +#define XR_ASSERT(assert, module, msg, arg...) \ + _XR_ASSERT(assert, module, XR_LEVEL_ALL, msg, ##arg) + +#define XR_ASSERT_ABORT(assert, module, msg, arg...) \ + _XR_ASSERT_ABORT(assert, module, XR_LEVEL_ALL, msg, ##arg) + +/* + * @brief Assert a full debug message with position(file, line, etc.) and + * error number without level. for example: + * "[Assert] At module_debug.h line 112 fun _MASSERT: condition p != NULL is fault. errno is 115." + * @param condition: It will assert a message if condition is fault. + * @retval Nuon + */ +#ifndef assert +#define assert(condition) XR_ASSERT(condition, MOD_DBG_ALW_ON, "condition %s is fault. errno is %d.\n", #condition, xr_thread_errno) +#endif + +/* +// THIS REALIZATION DO NOT SEAL +#define XR_ASSERT(assert, module, msg, arg...) \ + _XR_ASSERT(assert, module, XR_LEVEL_ALL, "[%s]" msg, #module, ##arg) + +#define XR_ASSERT_ABORT(assert, module, msg, arg...) \ + _XR_ASSERT_ABORT(assert, module, XR_LEVEL_ALL, "[%s]" msg, #module, ##arg) +*/ + + +/* + * @brief notify the function entry and exit/return in the debug level + * @param module: Contained a module On/Off at least. + * @param mname: module name in string + * @param ret: return value + * @retval None + */ +#define XR_ENTRY(module, mname) \ + XR_DEBUG(module, NOEXPAND, mname "entry %s().\n", __func__) + +#define XR_RET(module, mname, ret) \ + XR_DEBUG(module, NOEXPAND, mname "exit %s() with return %d.\n", __func__, ret) + +#define XR_RET_NOVAL(module, mname) \ + XR_DEBUG(module, NOEXPAND, mname "exit %s().\n", __func__) + + +#else /* MDEBUG_ON */ + +#define XR_DEBUG_PRINT(msg, arg...) + +#define XR_DEBUG_ABORT() + + +#define _XR_DEBUG(module, dlevel, expand, msg, arg...) + +#define _XR_INFO(module, dlevel, expand, msg, arg...) + +#define _XR_ASSERT(assert, module, dlevel, msg, arg...) + +#define _XR_ASSERT_ABORT(assert, module, dlevel, msg, arg...) + + +#define XR_ERROR(module, expand, msg, arg...) + +#define XR_ALERT(module, expand, msg, arg...) + +#define XR_CRIT(module, expand, msg, arg...) + +#define XR_EMERG(module, expand, msg, arg...) + +#define XR_WARN(module, expand, msg, arg...) + +#define XR_NOTICE(module, expand, msg, arg...) + +#define XR_INFO(module, expand, msg, arg...) + +#define XR_DEBUG(module, expand, msg, arg...) + + +#define XR_ASSERT(assert, module, msg, arg...) + +#define XR_ASSERT_ABORT(assert, module, msg, arg...) + +#ifndef assert +#define assert(condition) +#endif + + +#define XR_ENTRY(module, mname) + +#define XR_RET(module, mname, ret) + +#define XR_RET_NOVAL(module, mname) + +#endif /* XR_DEBUG_ON */ + +/* +//$ Example of xr_debug from mqtt $ + +#define MQTT_MODULE (DBG_ON | XR_LEVEL_DEBUG) + +#ifdef MOTT_ASSERT_ON +#define MQTT_ASSERT(assert, msg, arg...) XR_ALERT(MOD_DBG_ALW_ON, (assert), "[MQTT assert] "msg, ##arg) +#else +#define MQTT_ASSERT(assert, msg, arg...) +#endif + +#ifdef MQTT_DBG_ON + +#define MQTT_INFO(msg, arg...) XR_INFO(MQTT_MODULE, NOEXPAND, "[MQTT info] " msg, ##arg) + +#define MQTT_WARN(msg, arg...) XR_WARN(MQTT_MODULE, NOEXPAND, "[MQTT warning] " msg, ##arg) + +#define MQTT_DEBUG(msg, arg...) XR_DEBUG(MQTT_MODULE, NOEXPAND, "[MQTT debug] " msg, ##arg) + + + +#define MQTT_ENTRY() XR_ENTRY(MQTT_MODULE, "[MQTT entry] ") + +#define MQTT_EXIT(ret) XR_RET(MQTT_MODULE, "[MQTT return] ", ret) + +#else + +#define MQTT_INFO(msg, arg...) + +#define MQTT_WARN(msg, arg...) + +#define MQTT_DEBUG(msg, arg...) + + +#define MQTT_ENTRY() + +#define MQTT_EXIT(ret) + +#endif + +*/ + +extern void print_hex_dump_bytes(const void *addr, unsigned int len); +extern void hex_dump_bytes(const void *addr, unsigned int len); + +#endif /* __XR_DEBUG_H__ */ diff --git a/platform/mcu/xr871/include/sys/xr_util.h b/platform/mcu/xr871/include/sys/xr_util.h new file mode 100644 index 0000000000..bb3a3fd68e --- /dev/null +++ b/platform/mcu/xr871/include/sys/xr_util.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_XR_UTIL_H_ +#define _SYS_XR_UTIL_H_ + +#include "compiler.h" +#include "sys/interrupt.h" + +#if defined(__CC_ARM) + #define arch_breakpoint(value) __breakpoint(value) +#elif defined(__GNUC__) + #define arch_breakpoint(value) __asm volatile ("bkpt "#value) +#endif + +#define sys_abort() \ + do { \ + arch_fiq_disable(); \ + arch_breakpoint(0); \ + } while (0) + +#endif /* _SYS_XR_UTIL_H_ */ diff --git a/platform/mcu/xr871/include/types.h b/platform/mcu/xr871/include/types.h new file mode 100644 index 0000000000..2c09480add --- /dev/null +++ b/platform/mcu/xr871/include/types.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _TYPES_H_ +#define _TYPES_H_ + +#include +#include + +#endif /* _TYPES_H_ */ diff --git a/platform/mcu/xr871/include/version.h b/platform/mcu/xr871/include/version.h new file mode 100644 index 0000000000..ef2f91361c --- /dev/null +++ b/platform/mcu/xr871/include/version.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _VERSION_H_ +#define _VERSION_H_ + +#define SDK_VERSION_STR "1.0.1" + +#define SDK_VERSION_MAJOR 1 +#define SDK_VERSION_MINOR 0 +#define SDK_VERSION_PATCH 1 + +#define SDK_VERSION_NUM ((SDK_VERSION_MAJOR << 16) | \ + (SDK_VERSION_MINOR << 8) | \ + (SDK_VERSION_PATCH)) + +#endif /* _VERSION_H_ */ diff --git a/platform/mcu/xr871/include/xz/decompress.h b/platform/mcu/xr871/include/xz/decompress.h new file mode 100644 index 0000000000..90453518b0 --- /dev/null +++ b/platform/mcu/xr871/include/xz/decompress.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef __DECOMPRESS_H__ +#define __DECOMPRESS_H__ + +#include "xz.h" + +int xz_uncompress_init(struct xz_buf *stream); +int xz_uncompress_stream(struct xz_buf *stream, uint8_t *sbuf, uint32_t slen, + uint8_t *dbuf, uint32_t dlen, uint32_t *decomp_len); +void xz_uncompress_end(); + +uint32_t xz_index_len(uint8_t *stream_footer); +uint32_t xz_file_uncompress_size(uint8_t *index, uint32_t len); + + +#endif /* __DECOMPRESS_H__ */ diff --git a/platform/mcu/xr871/include/xz/xz.h b/platform/mcu/xr871/include/xz/xz.h new file mode 100644 index 0000000000..d94d68bc42 --- /dev/null +++ b/platform/mcu/xr871/include/xz/xz.h @@ -0,0 +1,286 @@ +/* + * XZ decompressor + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_H +#define XZ_H + +#ifdef __KERNEL__ +# include +# include +# include +#else +# include +# include +# include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* In Linux, this is used to make extern functions static when needed. */ +#ifndef XZ_EXTERN +# define XZ_EXTERN extern +#endif + +/** + * enum xz_mode - Operation mode + * + * @XZ_SINGLE: Single-call mode. This uses less RAM than + * than multi-call modes, because the LZMA2 + * dictionary doesn't need to be allocated as + * part of the decoder state. All required data + * structures are allocated at initialization, + * so xz_dec_run() cannot return XZ_MEM_ERROR. + * @XZ_PREALLOC: Multi-call mode with preallocated LZMA2 + * dictionary buffer. All data structures are + * allocated at initialization, so xz_dec_run() + * cannot return XZ_MEM_ERROR. + * @XZ_DYNALLOC: Multi-call mode. The LZMA2 dictionary is + * allocated once the required size has been + * parsed from the stream headers. If the + * allocation fails, xz_dec_run() will return + * XZ_MEM_ERROR. + * + * It is possible to enable support only for a subset of the above + * modes at compile time by defining XZ_DEC_SINGLE, XZ_DEC_PREALLOC, + * or XZ_DEC_DYNALLOC. The xz_dec kernel module is always compiled + * with support for all operation modes, but the preboot code may + * be built with fewer features to minimize code size. + */ +enum xz_mode { + XZ_SINGLE, + XZ_PREALLOC, + XZ_DYNALLOC +}; + +/** + * enum xz_ret - Return codes + * @XZ_OK: Everything is OK so far. More input or more + * output space is required to continue. This + * return code is possible only in multi-call mode + * (XZ_PREALLOC or XZ_DYNALLOC). + * @XZ_STREAM_END: Operation finished successfully. + * @XZ_UNSUPPORTED_CHECK: Integrity check type is not supported. Decoding + * is still possible in multi-call mode by simply + * calling xz_dec_run() again. + * Note that this return value is used only if + * XZ_DEC_ANY_CHECK was defined at build time, + * which is not used in the kernel. Unsupported + * check types return XZ_OPTIONS_ERROR if + * XZ_DEC_ANY_CHECK was not defined at build time. + * @XZ_MEM_ERROR: Allocating memory failed. This return code is + * possible only if the decoder was initialized + * with XZ_DYNALLOC. The amount of memory that was + * tried to be allocated was no more than the + * dict_max argument given to xz_dec_init(). + * @XZ_MEMLIMIT_ERROR: A bigger LZMA2 dictionary would be needed than + * allowed by the dict_max argument given to + * xz_dec_init(). This return value is possible + * only in multi-call mode (XZ_PREALLOC or + * XZ_DYNALLOC); the single-call mode (XZ_SINGLE) + * ignores the dict_max argument. + * @XZ_FORMAT_ERROR: File format was not recognized (wrong magic + * bytes). + * @XZ_OPTIONS_ERROR: This implementation doesn't support the requested + * compression options. In the decoder this means + * that the header CRC32 matches, but the header + * itself specifies something that we don't support. + * @XZ_DATA_ERROR: Compressed data is corrupt. + * @XZ_BUF_ERROR: Cannot make any progress. Details are slightly + * different between multi-call and single-call + * mode; more information below. + * + * In multi-call mode, XZ_BUF_ERROR is returned when two consecutive calls + * to XZ code cannot consume any input and cannot produce any new output. + * This happens when there is no new input available, or the output buffer + * is full while at least one output byte is still pending. Assuming your + * code is not buggy, you can get this error only when decoding a compressed + * stream that is truncated or otherwise corrupt. + * + * In single-call mode, XZ_BUF_ERROR is returned only when the output buffer + * is too small or the compressed input is corrupt in a way that makes the + * decoder produce more output than the caller expected. When it is + * (relatively) clear that the compressed input is truncated, XZ_DATA_ERROR + * is used instead of XZ_BUF_ERROR. + */ +enum xz_ret { + XZ_OK, + XZ_STREAM_END, + XZ_UNSUPPORTED_CHECK, + XZ_MEM_ERROR, + XZ_MEMLIMIT_ERROR, + XZ_FORMAT_ERROR, + XZ_OPTIONS_ERROR, + XZ_DATA_ERROR, + XZ_BUF_ERROR +}; + +/** + * struct xz_buf - Passing input and output buffers to XZ code + * @in: Beginning of the input buffer. This may be NULL if and only + * if in_pos is equal to in_size. + * @in_pos: Current position in the input buffer. This must not exceed + * in_size. + * @in_size: Size of the input buffer + * @out: Beginning of the output buffer. This may be NULL if and only + * if out_pos is equal to out_size. + * @out_pos: Current position in the output buffer. This must not exceed + * out_size. + * @out_size: Size of the output buffer + * + * Only the contents of the output buffer from out[out_pos] onward, and + * the variables in_pos and out_pos are modified by the XZ code. + */ +struct xz_buf { + const uint8_t *in; + size_t in_pos; + size_t in_size; + + uint8_t *out; + size_t out_pos; + size_t out_size; +}; + +/** + * struct xz_dec - Opaque type to hold the XZ decoder state + */ +struct xz_dec; + +/** + * xz_dec_init() - Allocate and initialize a XZ decoder state + * @mode: Operation mode + * @dict_max: Maximum size of the LZMA2 dictionary (history buffer) for + * multi-call decoding. This is ignored in single-call mode + * (mode == XZ_SINGLE). LZMA2 dictionary is always 2^n bytes + * or 2^n + 2^(n-1) bytes (the latter sizes are less common + * in practice), so other values for dict_max don't make sense. + * In the kernel, dictionary sizes of 64 KiB, 128 KiB, 256 KiB, + * 512 KiB, and 1 MiB are probably the only reasonable values, + * except for kernel and initramfs images where a bigger + * dictionary can be fine and useful. + * + * Single-call mode (XZ_SINGLE): xz_dec_run() decodes the whole stream at + * once. The caller must provide enough output space or the decoding will + * fail. The output space is used as the dictionary buffer, which is why + * there is no need to allocate the dictionary as part of the decoder's + * internal state. + * + * Because the output buffer is used as the workspace, streams encoded using + * a big dictionary are not a problem in single-call mode. It is enough that + * the output buffer is big enough to hold the actual uncompressed data; it + * can be smaller than the dictionary size stored in the stream headers. + * + * Multi-call mode with preallocated dictionary (XZ_PREALLOC): dict_max bytes + * of memory is preallocated for the LZMA2 dictionary. This way there is no + * risk that xz_dec_run() could run out of memory, since xz_dec_run() will + * never allocate any memory. Instead, if the preallocated dictionary is too + * small for decoding the given input stream, xz_dec_run() will return + * XZ_MEMLIMIT_ERROR. Thus, it is important to know what kind of data will be + * decoded to avoid allocating excessive amount of memory for the dictionary. + * + * Multi-call mode with dynamically allocated dictionary (XZ_DYNALLOC): + * dict_max specifies the maximum allowed dictionary size that xz_dec_run() + * may allocate once it has parsed the dictionary size from the stream + * headers. This way excessive allocations can be avoided while still + * limiting the maximum memory usage to a sane value to prevent running the + * system out of memory when decompressing streams from untrusted sources. + * + * On success, xz_dec_init() returns a pointer to struct xz_dec, which is + * ready to be used with xz_dec_run(). If memory allocation fails, + * xz_dec_init() returns NULL. + */ +XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max); + +/** + * xz_dec_run() - Run the XZ decoder + * @s: Decoder state allocated using xz_dec_init() + * @b: Input and output buffers + * + * The possible return values depend on build options and operation mode. + * See enum xz_ret for details. + * + * Note that if an error occurs in single-call mode (return value is not + * XZ_STREAM_END), b->in_pos and b->out_pos are not modified and the + * contents of the output buffer from b->out[b->out_pos] onward are + * undefined. This is true even after XZ_BUF_ERROR, because with some filter + * chains, there may be a second pass over the output buffer, and this pass + * cannot be properly done if the output buffer is truncated. Thus, you + * cannot give the single-call decoder a too small buffer and then expect to + * get that amount valid data from the beginning of the stream. You must use + * the multi-call decoder if you don't want to uncompress the whole stream. + */ +XZ_EXTERN enum xz_ret xz_dec_run(struct xz_dec *s, struct xz_buf *b); + +/** + * xz_dec_reset() - Reset an already allocated decoder state + * @s: Decoder state allocated using xz_dec_init() + * + * This function can be used to reset the multi-call decoder state without + * freeing and reallocating memory with xz_dec_end() and xz_dec_init(). + * + * In single-call mode, xz_dec_reset() is always called in the beginning of + * xz_dec_run(). Thus, explicit call to xz_dec_reset() is useful only in + * multi-call mode. + */ +XZ_EXTERN void xz_dec_reset(struct xz_dec *s); + +/** + * xz_dec_end() - Free the memory allocated for the decoder state + * @s: Decoder state allocated using xz_dec_init(). If s is NULL, + * this function does nothing. + */ +XZ_EXTERN void xz_dec_end(struct xz_dec *s); + +/* + * Standalone build (userspace build or in-kernel build for boot time use) + * needs a CRC32 implementation. For normal in-kernel use, kernel's own + * CRC32 module is used instead, and users of this module don't need to + * care about the functions below. + */ +#ifndef XZ_INTERNAL_CRC32 +# ifdef __KERNEL__ +# define XZ_INTERNAL_CRC32 0 +# else +# define XZ_INTERNAL_CRC32 1 +# endif +#endif + +#if XZ_INTERNAL_CRC32 +/* + * This must be called before any other xz_* function to initialize + * the CRC32 lookup table. + */ +XZ_EXTERN void xz_crc32_init(void); + +/* + * Update CRC32 value using the polynomial from IEEE-802.3. To start a new + * calculation, the third argument must be zero. To continue the calculation, + * the previously returned value is passed as the third argument. + */ +XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc); +#endif + +#ifdef __cplusplus +} +#endif + +/* This function verifies if the input buffer matches the xz header. + * If so, it returns 0 else -1 */ +static inline int verify_xz_header(uint8_t *buffer) +{ + const uint8_t xz_header[6] = { 0xFD, '7', 'z', 'X', 'Z', 0x00 }; + if (buffer) { + if (!memcmp(buffer, xz_header, 6)) + return 0; + } + return -1; +} +#endif diff --git a/platform/mcu/xr871/lib/libamr/libamr.a b/platform/mcu/xr871/lib/libamr/libamr.a new file mode 100644 index 0000000000000000000000000000000000000000..edc7195093ffd476eae1f593b652f3ec4b6218c3 GIT binary patch literal 252734 zcmeFa3w&Hvxi-G{Tr!i)G)bGLO-tHNGHD64NhX)xZ@JS;+NMccDio%ZWYVO~jhUnu zPJsgDqH-%BA_r_mR1}UPa#gShc;r)1DyWF4RZ$ca0TIhZ`JQL3ckkJg2Ep@r{Qu7X z`&PT>S?^l!de^(Id+oj7wNkVsmgwwRmQ@i-ca=2@=g(VM8JS-d3Pn_u^EVW#oI9^Z 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z3+3v%e&=UAM4g_;?o=cO%M-7~m30a_Or|VYp3H}|+&KzVIVx9=adb(-FV4w3i##n< zEtot#?^67_m~joOLhZ#^P@aBz4wll5tX_U^`6h_yf=T1o_tCTmW$7T$qb zaEE1rTU0Qqj$743T}jXaTw_evE4@{lsOv2Z&>v430yKF^Qi!JM|HNLf`o0ws1tU>s z`LyQ;gEb@9-f(-q%^pn>o$b?}&tf_WrM8iz^15^MspcsEoLoLik_4Rv)Lxz*8MHzv zm%H?AAZcVPltQnk_?i|%Z0X)KpGk-m8mm?6!?G^~%`H{hV|~O2176AI2#tX%?QvJk zmyT3v|E&?1LR7i_@rY|~snTALMO<@cRoa!D^Er| bJp1lt?HKWw1R3P-Mf?*%*7l(tE_CiszHB2k literal 0 HcmV?d00001 diff --git a/platform/mcu/xr871/lib/libmp3/libmp3.mk b/platform/mcu/xr871/lib/libmp3/libmp3.mk new file mode 100644 index 0000000000..5d6272bcef --- /dev/null +++ b/platform/mcu/xr871/lib/libmp3/libmp3.mk @@ -0,0 +1,8 @@ + + +NAME := libmp3 + +$(NAME)_TYPE := kernel +$(NAME)_PREBUILT_LIBRARY := libmp3.a + + diff --git a/platform/mcu/xr871/mkimage.mk b/platform/mcu/xr871/mkimage.mk new file mode 100644 index 0000000000..7f12868b01 --- /dev/null +++ b/platform/mcu/xr871/mkimage.mk @@ -0,0 +1,57 @@ + +no_with_xip := 0 + +ifeq ($(HOST_OS),Win32) +MKIMAGE_TOOL := "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/tools/mkimage.exe" +else # Win32 +ifeq ($(HOST_OS),Linux32) +MKIMAGE_TOOL := "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/tools/mkimage" +XZ_TOOL := "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/tools/xz" +else # Linux32 +ifeq ($(HOST_OS),Linux64) +MKIMAGE_TOOL := "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/tools/mkimage" +XZ_TOOL := "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/tools/xz64" +else # Linux64 +$(error not surport for $(HOST_OS)) +endif # Linux64 +endif # Linux32 +endif # Win32 + +EXTRA_POST_BUILD_TARGETS += mkimage + +ifneq ($(no_with_xip),1) +IMAGE_XIP := -xip +else +IMAGE_XIP := +endif + +ifneq ($(no_with_image_compress),1) +IMAGE_XZ := -xz +else +IMAGE_XZ := +endif + +ifneq ($(no_with_ota),1) +IMAGE_OTA := -O +else +IMAGE_OTA := +endif + +IMAGE_CFG_FILE ?= "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/image-${APP}${IMAGE_XZ}.cfg" +IMAGE_PACK_DIR ?= "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/pack" +BINARY_DIR ?= $(SOURCE_ROOT)out/$(CLEANED_BUILD_STRING)/binary + +mkimage: + $(OBJCOPY) -O binary -R .xip -R .eh_frame -R .init -R .fini -R .comment -R .ARM.attributes $(BINARY_DIR)/$(CLEANED_BUILD_STRING).elf $(BINARY_DIR)/$(CLEANED_BUILD_STRING).bin + $(OBJCOPY) -O binary -j .xip $(BINARY_DIR)/$(CLEANED_BUILD_STRING).elf $(BINARY_DIR)/$(CLEANED_BUILD_STRING).xip.bin + $(CP) -vf $(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/bin/xr871/*.bin $(IMAGE_PACK_DIR)/ + $(CP) -vf $(SOURCE_ROOT)out/$(CLEANED_BUILD_STRING)/binary/$(CLEANED_BUILD_STRING).bin $(IMAGE_PACK_DIR)/app.bin + $(CP) -vf $(SOURCE_ROOT)out/$(CLEANED_BUILD_STRING)/binary/$(CLEANED_BUILD_STRING).xip.bin $(IMAGE_PACK_DIR)/app-xip.bin +ifneq ($(no_with_image_compress),1) + $(RM) -vf $(IMAGE_PACK_DIR)/*.bin.xz + $(XZ_TOOL) -vk --check=crc32 --lzma2=preset=6e,dict=32KiB $(IMAGE_PACK_DIR)/net.bin + $(XZ_TOOL) -vk --check=crc32 --lzma2=preset=6e,dict=32KiB $(IMAGE_PACK_DIR)/net_ap.bin +endif + $(CP) -vf $(MKIMAGE_TOOL) $(IMAGE_PACK_DIR)/ + $(CP) -vf $(IMAGE_CFG_FILE) $(IMAGE_PACK_DIR)/ + cd $(IMAGE_PACK_DIR) && mkimage ${IMAGE_OTA} -c image-${APP}${IMAGE_XZ}.cfg diff --git a/platform/mcu/xr871/pack/.keep b/platform/mcu/xr871/pack/.keep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/platform/mcu/xr871/project/common/board/board.c b/platform/mcu/xr871/project/common/board/board.c new file mode 100644 index 0000000000..2f891491bd --- /dev/null +++ b/platform/mcu/xr871/project/common/board/board.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "board_debug.h" +#include "board.h" +#include "driver/chip/hal_codec.h" +#include + +/* uart */ +#if PRJCONF_UART_EN +__weak HAL_Status board_uart_init(UART_ID uart_id) +{ + static const UART_InitParam board_uart_param = { + .baudRate = BOARD_UART_BAUD_RATE, + .parity = BOARD_UART_PARITY, + .stopBits = BOARD_UART_STOP_BITS, + .dataBits = BOARD_UART_DATA_BITS, + .isAutoHwFlowCtrl = BOARD_UART_HW_FLOW_CTRL + }; + + return HAL_UART_Init(uart_id, &board_uart_param); +} + +__weak HAL_Status board_uart_deinit(UART_ID uart_id) +{ + return HAL_UART_DeInit(uart_id); +} + +__weak int32_t board_uart_write(UART_ID uart_id, char *buf, int count) +{ + return HAL_UART_Transmit_Poll(uart_id, (uint8_t *)buf, count); +} +#endif /* PRJCONF_UART_EN */ + +/* spi */ +#if PRJCONF_SPI_EN +__weak HAL_Status board_spi_init(SPI_Port spi) +{ + static const SPI_Global_Config board_spi_param = { + .mclk = BOARD_SPI_MCLK, + .cs_level = BOARD_SPI_CS_LEVEL + }; + + return HAL_SPI_Init(spi, &board_spi_param); +} + +__weak HAL_Status board_spi_deinit(SPI_Port spi) +{ + return HAL_SPI_Deinit(spi); +} +#endif /* PRJCONF_SPI_EN */ + +/* sound card0 */ +#if PRJCONF_SOUNDCARD0_EN +__weak HAL_Status board_soundcard0_init(void) +{ + static const I2C_InitParam i2c_param = { + .addrMode = BOARD_SOUNDCARD0_I2C_ADDR_MODE, + .clockFreq = BOARD_SOUNDCARD0_I2C_CLK + }; + + static const CODEC_Param acodec_param = { + .name = (uint8_t *)BOARD_SOUNDCARD0_CODEC_NAME, + .write = BOARD_SOUNDCARD0_CODEC_WRITE, + .read = BOARD_SOUNDCARD0_CODEC_READ, + .i2cId = BOARD_SOUNDCARD0_I2C_ID, + .param = NULL + }; + + I2S_Param i2s_param; + HAL_Status ret; + + ret = HAL_I2C_Init(BOARD_SOUNDCARD0_I2C_ID, &i2c_param); + if (ret != HAL_OK) { + BOARD_ERR("I2C %d init failed\n", BOARD_SOUNDCARD0_I2C_ID); + return ret; + } + + memset(&i2s_param, 0, sizeof(i2s_param)); + ret = HAL_I2S_Init(&i2s_param); + if (ret != HAL_OK) { + BOARD_ERR("I2S init failed\n"); + HAL_I2C_DeInit(BOARD_SOUNDCARD0_I2C_ID); + return ret; + } + + ret = HAL_CODEC_Init(&acodec_param); + if (ret != HAL_OK) { + BOARD_ERR("acodec init failed\n"); + HAL_I2S_DeInit(); + HAL_I2C_DeInit(BOARD_SOUNDCARD0_I2C_ID); + return ret; + } + + return ret; +} + +__weak HAL_Status board_soundcard0_deinit(void) +{ + HAL_CODEC_DeInit(); + HAL_I2S_DeInit(); + return HAL_I2C_DeInit(BOARD_SOUNDCARD0_I2C_ID); +} +#endif /* PRJCONF_SOUNDCARD0_EN */ + +/* sound card1 */ +#if PRJCONF_SOUNDCARD1_EN +__weak HAL_Status board_soundcard1_init(void) +{ + DMIC_Param dmic_param; + memset(&dmic_param, 0, sizeof(dmic_param)); + + return HAL_DMIC_Init(&dmic_param); +} + +__weak HAL_Status board_soundcard1_deinit(void) +{ + HAL_DMIC_DeInit(); + return HAL_OK; +} +#endif /* PRJCONF_SOUNDCARD1_EN */ diff --git a/platform/mcu/xr871/project/common/board/board.h b/platform/mcu/xr871/project/common/board/board.h new file mode 100644 index 0000000000..58a638e2dc --- /dev/null +++ b/platform/mcu/xr871/project/common/board/board.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "board_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +HAL_Status board_ioctl(HAL_BoardIoctlReq req, uint32_t param0, uint32_t param1); + +/* uart */ +HAL_Status board_uart_init(UART_ID uart_id); +HAL_Status board_uart_deinit(UART_ID uart_id); +int32_t board_uart_write(UART_ID uart_id, char *buf, int count); + +/* spi */ +HAL_Status board_spi_init(SPI_Port spi); +HAL_Status board_spi_deinit(SPI_Port spi); + +/* sound card0 */ +#if PRJCONF_SOUNDCARD0_EN +HAL_Status board_soundcard0_init(void); +HAL_Status board_soundcard0_deinit(void); +#endif + +/* sound card1 */ +#if PRJCONF_SOUNDCARD1_EN +HAL_Status board_soundcard1_init(void); +HAL_Status board_soundcard1_deinit(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARD_H_ */ diff --git a/platform/mcu/xr871/project/common/board/board_common.c b/platform/mcu/xr871/project/common/board/board_common.c new file mode 100644 index 0000000000..c5ce3a3215 --- /dev/null +++ b/platform/mcu/xr871/project/common/board/board_common.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "board_common.h" +#include "board.h" + +HAL_Status board_pinmux_cfg(HAL_BoardIoctlReq req, + const GPIO_PinMuxParam *pinmux, uint32_t count) +{ + switch (req) { + case HAL_BIR_PINMUX_INIT: + HAL_GPIO_PinMuxConfig(pinmux, count); + break; + case HAL_BIR_PINMUX_DEINIT: + HAL_GPIO_PinMuxDeConfig(pinmux, count); + break; + default: + return HAL_INVALID; + } + + return HAL_OK; +} + +void board_chip_clock_init(void) +{ +#if (BOARD_HOSC_CLOCK == HOSC_CLOCK_24M) + HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_24M); + HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC24M); +#elif (BOARD_HOSC_CLOCK == HOSC_CLOCK_26M) + HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_26M); + HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC26M); +#elif (BOARD_HOSC_CLOCK == HOSC_CLOCK_40M) + HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_40M); + HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC40M); +#elif (BOARD_HOSC_CLOCK == HOSC_CLOCK_52M) + HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_52M); + HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC52M); +#else + #error "Invalid HOSC value!" +#endif + +#if (defined(BOARD_LOSC_EXTERNAL) && BOARD_LOSC_EXTERNAL) + HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_SRC_EXT32K); + HAL_PRCM_DisableInter32KCalib(); +#else + HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_SRC_INTER32K); + HAL_PRCM_EnableInter32KCalib(); +#endif + + HAL_PRCM_SetCPUAClk(BOARD_CPU_CLK_SRC, BOARD_CPU_CLK_FACTOR); + HAL_PRCM_SetDevClock(BOARD_DEV_CLK_FACTOR); + HAL_CCM_BusSetClock(BOARD_AHB2_CLK_DIV, BOARD_APB_CLK_SRC, BOARD_APB_CLK_DIV); +} diff --git a/platform/mcu/xr871/project/common/board/board_common.h b/platform/mcu/xr871/project/common/board/board_common.h new file mode 100644 index 0000000000..a76b432142 --- /dev/null +++ b/platform/mcu/xr871/project/common/board/board_common.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BOARD_COMMON_H_ +#define _BOARD_COMMON_H_ + +#include "driver/hal_board.h" +#include "driver/chip/hal_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +HAL_Status board_pinmux_cfg(HAL_BoardIoctlReq req, + const GPIO_PinMuxParam *pinmux, uint32_t count); +void board_chip_clock_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARD_COMMON_H_ */ diff --git a/platform/mcu/xr871/project/common/board/board_debug.h b/platform/mcu/xr871/project/common/board/board_debug.h new file mode 100644 index 0000000000..d800324ed3 --- /dev/null +++ b/platform/mcu/xr871/project/common/board/board_debug.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BOARD_DEBUG_H_ +#define _BOARD_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define BOARD_DBG_ON 1 +#define BOARD_WRN_ON 1 +#define BOARD_ERR_ON 1 +#define BOARD_ABORT_ON 0 + +#define BOARD_SYSLOG printf +#define BOARD_ABORT() sys_abort() + +#define BOARD_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + BOARD_SYSLOG(fmt, ##arg); \ + } while (0) + +#define BOARD_DBG(fmt, arg...) BOARD_LOG(BOARD_DBG_ON, "[board] "fmt, ##arg) +#define BOARD_WRN(fmt, arg...) BOARD_LOG(BOARD_WRN_ON, "[board WRN] "fmt, ##arg) + +#define BOARD_ERR(fmt, arg...) \ + do { \ + BOARD_LOG(BOARD_ERR_ON, "[board ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (BOARD_ABORT_ON) \ + BOARD_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARD_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/board/xr871_evb_main/board_config.c b/platform/mcu/xr871/project/common/board/xr871_evb_main/board_config.c new file mode 100644 index 0000000000..3f06e7c763 --- /dev/null +++ b/platform/mcu/xr871/project/common/board/xr871_evb_main/board_config.c @@ -0,0 +1,399 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "../board_debug.h" +#include "board_config.h" +#include "driver/chip/hal_codec.h" + +#define BOARD_SWD_EN 1 + +static const GPIO_PinMuxParam g_pinmux_uart0[] = { + { GPIO_PORT_B, GPIO_PIN_0, { GPIOB_P0_F2_UART0_TX, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, /* TX */ + { GPIO_PORT_B, GPIO_PIN_1, { GPIOB_P1_F2_UART0_RX, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, /* RX */ +}; + +static const GPIO_PinMuxParam g_pinmux_uart1[] = { + { GPIO_PORT_A, GPIO_PIN_17, { GPIOA_P17_F5_UART1_TX, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, /* TX */ + { GPIO_PORT_A, GPIO_PIN_18, { GPIOA_P18_F5_UART1_RX, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, /* RX */ +}; + +static const GPIO_PinMuxParam g_pinmux_dmic[] = { + { GPIO_PORT_A, GPIO_PIN_21, { GPIOA_P21_F3_DMIC_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_22, { GPIOA_P22_F3_DMIC_DATA, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +static const GPIO_PinMuxParam g_pinmux_i2s[] = { + { GPIO_PORT_A, GPIO_PIN_12, { GPIOA_P12_F4_I2S_MCLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_13, { GPIOA_P13_F4_I2S_BCLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_14, { GPIOA_P14_F4_I2S_DI, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_15, { GPIOA_P15_F4_I2S_DO, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_16, { GPIOA_P16_F4_I2S_LRCLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +static const GPIO_PinMuxParam g_pinmux_irrx[] = { + { GPIO_PORT_A, GPIO_PIN_17, { GPIOA_P17_F3_IR_RX, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_irtx[] = { + { GPIO_PORT_A, GPIO_PIN_18, { GPIOA_P18_F3_IR_TX, GPIO_DRIVING_LEVEL_1, GPIO_PULL_DOWN } }, +}; + +static const GPIO_PinMuxParam g_pinmux_i2c0[] = { + { GPIO_PORT_A, GPIO_PIN_4, { GPIOA_P4_F4_I2C0_SCL, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, + { GPIO_PORT_A, GPIO_PIN_5, { GPIOA_P5_F4_I2C0_SDA, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_i2c1[] = { + { GPIO_PORT_A, GPIO_PIN_17, { GPIOA_P17_F4_I2C1_SCL, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, + { GPIO_PORT_A, GPIO_PIN_18, { GPIOA_P18_F4_I2C1_SDA, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_adc[] = { + { GPIO_PORT_A, GPIO_PIN_8, { GPIOA_P8_F2_ADC_CH0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_9, { GPIOA_P9_F2_ADC_CH1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_10, { GPIOA_P10_F2_ADC_CH2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_11, { GPIOA_P11_F2_ADC_CH3, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_12, { GPIOA_P12_F2_ADC_CH4, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_13, { GPIOA_P13_F2_ADC_CH5, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_14, { GPIOA_P14_F2_ADC_CH6, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_15, { GPIOA_P15_F2_ADC_CH7, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +static const GPIO_PinMuxParam g_pinmux_spi0[] = { + { GPIO_PORT_B, GPIO_PIN_4, { GPIOB_P4_F2_SPI0_MOSI, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_B, GPIO_PIN_5, { GPIOB_P5_F2_SPI0_MISO, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_B, GPIO_PIN_7, { GPIOB_P7_F2_SPI0_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +static const GPIO_PinMuxParam g_pinmux_spi0_cs0[] = { + { GPIO_PORT_B, GPIO_PIN_6, { GPIOB_P6_F2_SPI0_CS0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_spi1[] = { + { GPIO_PORT_A, GPIO_PIN_0, { GPIOA_P0_F2_SPI1_MOSI, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_1, { GPIOA_P1_F2_SPI1_MISO, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_2, { GPIOA_P2_F2_SPI1_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +static const GPIO_PinMuxParam g_pinmux_spi1_cs0[] = { + { GPIO_PORT_A, GPIO_PIN_3, { GPIOA_P3_F2_SPI1_CS0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_spi1_cs1[] = { + { GPIO_PORT_A, GPIO_PIN_6, { GPIOA_P6_F3_SPI1_CS1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_spi1_cs2[] = { + { GPIO_PORT_A, GPIO_PIN_7, { GPIOA_P7_F3_SPI1_CS2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const GPIO_PinMuxParam g_pinmux_flashc[] = { + { GPIO_PORT_B, GPIO_PIN_4, { GPIOB_P4_F5_FLASH_MOSI, GPIO_DRIVING_LEVEL_3, GPIO_PULL_NONE } }, + { GPIO_PORT_B, GPIO_PIN_5, { GPIOB_P5_F5_FLASH_MISO, GPIO_DRIVING_LEVEL_3, GPIO_PULL_NONE } }, + { GPIO_PORT_B, GPIO_PIN_7, { GPIOB_P7_F5_FLASH_CLK, GPIO_DRIVING_LEVEL_3, GPIO_PULL_NONE } }, + { GPIO_PORT_B, GPIO_PIN_6, { GPIOB_P6_F5_FLASH_CS, GPIO_DRIVING_LEVEL_3, GPIO_PULL_UP } }, +#if (!BOARD_SWD_EN) + { GPIO_PORT_B, GPIO_PIN_2, { GPIOB_P2_F5_FLASH_WP, GPIO_DRIVING_LEVEL_3, GPIO_PULL_UP } }, + { GPIO_PORT_B, GPIO_PIN_3, { GPIOB_P3_F5_FLASH_HOLD, GPIO_DRIVING_LEVEL_3, GPIO_PULL_UP } }, +#endif +}; + +/* flash */ +static const FlashBoardCfg g_flash_cfg[] = { + { + .type = FLASH_DRV_FLASHC, + .mode = FLASH_READ_DUAL_O_MODE, + .flashc.clk = (48 * 1000 * 1000), + }, +}; + +static const GPIO_PinMuxParam g_pinmux_pwm[] = { + { GPIO_PORT_A, GPIO_PIN_8, { GPIOA_P8_F3_PWM0_ECT0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_9, { GPIOA_P9_F3_PWM1_ECT1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_10, { GPIOA_P10_F3_PWM2_ECT2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_11, { GPIOA_P11_F3_PWM3_ECT3, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_12, { GPIOA_P12_F3_PWM4_ECT4, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_13, { GPIOA_P13_F3_PWM5_ECT5, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_14, { GPIOA_P14_F3_PWM6_ECT6, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_15, { GPIOA_P15_F3_PWM7_ECT7, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +#define BOARD_SD0_DATA_BITS 1 +#define BOARD_SD0_DET_VALID 0 +#define BOARD_SD0_DET_PORT GPIO_PORT_A +#define BOARD_SD0_DET_PIN GPIO_PIN_3 +#define BOARD_SD0_DET_PIN_MODE GPIOA_P3_F6_EINTA3 + +static const GPIO_PinMuxParam g_pinmux_sd0[BOARD_SD0_DATA_BITS + 2] = { + { GPIO_PORT_A, GPIO_PIN_0, { GPIOA_P0_F3_SD_CMD, GPIO_DRIVING_LEVEL_2, GPIO_PULL_UP } }, /* CMD */ + { GPIO_PORT_A, GPIO_PIN_2, { GPIOA_P2_F3_SD_CLK, GPIO_DRIVING_LEVEL_2, GPIO_PULL_UP } }, /* CLK */ + { GPIO_PORT_A, GPIO_PIN_1, { GPIOA_P1_F3_SD_DATA0, GPIO_DRIVING_LEVEL_2, GPIO_PULL_UP } }, /* D0 */ +// { GPIO_PORT_A, GPIO_PIN_3, { GPIOA_P3_F3_SD_DATA1, GPIO_DRIVING_LEVEL_2, GPIO_PULL_UP } }, /* D1 */ +// { GPIO_PORT_A, GPIO_PIN_4, { GPIOA_P4_F3_SD_DATA2, GPIO_DRIVING_LEVEL_2, GPIO_PULL_UP } }, /* D2 */ +// { GPIO_PORT_A, GPIO_PIN_5, { GPIOA_P5_F3_SD_DATA3, GPIO_DRIVING_LEVEL_2, GPIO_PULL_NONE } }, /* D3 */ +}; + +static const GPIO_PinMuxParam g_pinmux_sd0_det[] = { + { BOARD_SD0_DET_PORT, BOARD_SD0_DET_PIN, { BOARD_SD0_DET_PIN_MODE, GPIO_DRIVING_LEVEL_2, GPIO_PULL_NONE } }, /* DET */ +}; + +static const HAL_SDCGPIOCfg g_sd0_cfg = { + .data_bits = BOARD_SD0_DATA_BITS, + .has_detect_gpio = BOARD_SD0_DET_VALID, + .detect_port = BOARD_SD0_DET_PORT, + .detect_pin = BOARD_SD0_DET_PIN +}; + +#define BOARD_SPK_PORT GPIO_PORT_A +#define BOARD_SPK_PIN GPIO_PIN_3 + +static const GPIO_PinMuxParam g_pinmux_spk[] = { + { BOARD_SPK_PORT, BOARD_SPK_PIN, { GPIOx_Pn_F1_OUTPUT, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } }, +}; + +static const SPK_Param g_spk_cfg = { + .ctrl_port = BOARD_SPK_PORT, + .ctrl_pin = BOARD_SPK_PIN, + .ctrl_on_state = GPIO_PIN_HIGH, + .ctrl_off_state = GPIO_PIN_LOW +}; + +GPIO_PinMuxParam g_pinmux_csi[] = { + { GPIO_PORT_A, GPIO_PIN_0, { GPIOA_P0_F5_CSI_D0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_1, { GPIOA_P1_F5_CSI_D1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_2, { GPIOA_P2_F5_CSI_D2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_3, { GPIOA_P3_F5_CSI_D3, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_4, { GPIOA_P4_F4_CSI_D4, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_5, { GPIOA_P5_F5_CSI_D5, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_6, { GPIOA_P6_F5_CSI_D6, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_7, { GPIOA_P7_F5_CSI_D7, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_8, { GPIOA_P8_F5_CSI_PCLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_9, { GPIOA_P9_F5_CSI_MCLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_10, { GPIOA_P10_F5_CSI_HSYNC, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, + { GPIO_PORT_A, GPIO_PIN_11, { GPIOA_P11_F5_CSI_VSYNC, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } }, +}; + +struct board_pinmux_info { + const GPIO_PinMuxParam *pinmux; + uint32_t count; +}; + +#define BOARD_PINMUX_INFO_MAX 2 + +static HAL_Status board_get_pinmux_info(uint32_t major, uint32_t minor, uint32_t param, + struct board_pinmux_info info[]) +{ + HAL_Status ret = HAL_OK; + + switch (major) { + case HAL_DEV_MAJOR_UART: + if (minor == UART0_ID) { + info[0].pinmux = g_pinmux_uart0; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_uart0); + } else if (minor == UART1_ID) { + info[0].pinmux = g_pinmux_uart1; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_uart1); + } else { + ret = HAL_INVALID; + } + break; + case HAL_DEV_MAJOR_I2C: + if (minor == I2C0_ID) { + info[0].pinmux = g_pinmux_i2c0; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_i2c0); + } else if (minor == I2C1_ID) { + info[0].pinmux = g_pinmux_i2c1; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_i2c1); + } else { + ret = HAL_INVALID; + } + break; + case HAL_DEV_MAJOR_SPI: + if (minor == SPI0) { + info[0].pinmux = g_pinmux_spi0; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_spi0); + info[1].pinmux = g_pinmux_spi0_cs0; + info[1].count = HAL_ARRAY_SIZE(g_pinmux_spi0_cs0); + } else if (minor == SPI1) { + info[0].pinmux = g_pinmux_spi1; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_spi1); + switch (param) { + case SPI_TCTRL_SS_SEL_SS0: + info[1].pinmux = g_pinmux_spi1_cs0; + info[1].count = HAL_ARRAY_SIZE(g_pinmux_spi1_cs0); + break; + case SPI_TCTRL_SS_SEL_SS1: + info[1].pinmux = g_pinmux_spi1_cs1; + info[1].count = HAL_ARRAY_SIZE(g_pinmux_spi1_cs1); + break; + case SPI_TCTRL_SS_SEL_SS2: + info[1].pinmux = g_pinmux_spi1_cs2; + info[1].count = HAL_ARRAY_SIZE(g_pinmux_spi1_cs2); + break; + default: + ret = HAL_INVALID; + break; + } + } else { + ret = HAL_INVALID; + } + break; + case HAL_DEV_MAJOR_IRRX: + info[0].pinmux = g_pinmux_irrx; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_irrx); + break; + case HAL_DEV_MAJOR_IRTX: + info[0].pinmux = g_pinmux_irtx; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_irtx); + break; + case HAL_DEV_MAJOR_I2S: + info[0].pinmux = g_pinmux_i2s; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_i2s); + break; + case HAL_DEV_MAJOR_DMIC: + info[0].pinmux = g_pinmux_dmic; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_dmic); + break; + case HAL_DEV_MAJOR_ADC: + if (minor < HAL_ARRAY_SIZE(g_pinmux_adc)) { + info[0].pinmux = &g_pinmux_adc[minor]; + info[0].count = 1; + } else { + ret = HAL_INVALID; + } + break; + case HAL_DEV_MAJOR_PWM: + if (minor < HAL_ARRAY_SIZE(g_pinmux_pwm)) { + info[0].pinmux = &g_pinmux_pwm[minor]; + info[0].count = 1; + } else if (minor != ADC_CHANNEL_8) { + ret = HAL_INVALID; + } + break; + case HAL_DEV_MAJOR_FLASHC: + info[0].pinmux = g_pinmux_flashc; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_flashc); + break; + case HAL_DEV_MAJOR_SDC: + info[0].pinmux = g_pinmux_sd0; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_sd0); + info[1].pinmux = g_pinmux_sd0_det; + info[1].count = 1; + break; + case HAL_DEV_MAJOR_CSI: + info[0].pinmux = g_pinmux_csi; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_csi); + break; + case HAL_DEV_MAJOR_AUDIO_CODEC: + info[0].pinmux = g_pinmux_spk; + info[0].count = HAL_ARRAY_SIZE(g_pinmux_spk); + break; + default: + BOARD_ERR("unknow major %u\n", major); + ret = HAL_INVALID; + } + + return ret; +} + +static HAL_Status board_get_cfg(uint32_t major, uint32_t minor, uint32_t param) +{ + HAL_Status ret = HAL_OK; + + switch (major) { + case HAL_DEV_MAJOR_SDC: + *((HAL_SDCGPIOCfg **)param) = (HAL_SDCGPIOCfg *)&g_sd0_cfg; + break; + case HAL_DEV_MAJOR_FLASH: + if (minor <= (sizeof(g_flash_cfg) / sizeof(FlashBoardCfg))) + *((FlashBoardCfg **)param) = (FlashBoardCfg *)&g_flash_cfg[minor]; + else + *((FlashBoardCfg **)param) = NULL; + break; + case HAL_DEV_MAJOR_AUDIO_CODEC: + *((SPK_Param **)param) = (SPK_Param *)&g_spk_cfg; + break; + default: + BOARD_ERR("unknow major %u\n", major); + ret = HAL_INVALID; + } + + return ret; +} + +HAL_Status board_ioctl(HAL_BoardIoctlReq req, uint32_t param0, uint32_t param1) +{ + HAL_Status ret = HAL_OK; + uint32_t major, minor, i; + struct board_pinmux_info info[BOARD_PINMUX_INFO_MAX]; + + switch (req) { + case HAL_BIR_PINMUX_INIT: + case HAL_BIR_PINMUX_DEINIT: + memset(info, 0, sizeof(info)); + major = HAL_DEV_MAJOR((HAL_Dev_t)param0); + minor = HAL_DEV_MINOR((HAL_Dev_t)param0); + ret = board_get_pinmux_info(major, minor, param1, info); + if (major == HAL_DEV_MAJOR_SDC) { + if (param1 == SDCGPIO_BAS) { + board_pinmux_cfg(req, info[0].pinmux, info[0].count); + } else if (param1 == SDCGPIO_DET) { + board_pinmux_cfg(req, info[1].pinmux, info[1].count); + } + } else { + for (i = 0; i < BOARD_PINMUX_INFO_MAX; ++i) { + if (info[i].pinmux != NULL && info[i].count != 0) { + board_pinmux_cfg(req, info[i].pinmux, info[i].count); + } else { + break; + } + } + } + break; + case HAL_BIR_CHIP_CLOCK_INIT: + board_chip_clock_init(); + break; + case HAL_BIR_GET_CFG: + major = HAL_DEV_MAJOR((HAL_Dev_t)param0); + minor = HAL_DEV_MINOR((HAL_Dev_t)param0); + ret = board_get_cfg(major, minor, param1); + break; + default: + BOARD_ERR("req %d not suppport\n", req); + ret = HAL_INVALID; + break; + } + + if (ret != HAL_OK) { + BOARD_ERR("req %d, param0 %#x, param1 %#x, ret %d\n", req, param0, param1, ret); + } + + return ret; +} diff --git a/platform/mcu/xr871/project/common/board/xr871_evb_main/board_config.h b/platform/mcu/xr871/project/common/board/xr871_evb_main/board_config.h new file mode 100644 index 0000000000..b96c3e6a85 --- /dev/null +++ b/platform/mcu/xr871/project/common/board/xr871_evb_main/board_config.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BOARD_CONFIG_H_ +#define _BOARD_CONFIG_H_ + +#include "driver/chip/hal_chip.h" +#include "driver/hal_board.h" +#include "driver/hal_dev.h" +#include "../board_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * board configuration + */ + +/* chip clock */ +#define BOARD_HOSC_CLOCK HOSC_CLOCK_24M +#define BOARD_LOSC_EXTERNAL 1 /* 0: inter 32k, 1: external 32k */ +#define BOARD_CPU_CLK_SRC PRCM_CPU_CLK_SRC_SYSCLK +#define BOARD_CPU_CLK_FACTOR PRCM_SYS_CLK_FACTOR_160M +#define BOARD_DEV_CLK_FACTOR PRCM_DEV_CLK_FACTOR_192M +#define BOARD_AHB2_CLK_DIV CCM_AHB2_CLK_DIV_2 +#define BOARD_APB_CLK_SRC CCM_APB_CLK_SRC_HFCLK +#define BOARD_APB_CLK_DIV CCM_APB_CLK_DIV_1 + +/* uart */ +#define BOARD_MAIN_UART_ID UART0_ID /* debug and console */ +#define BOARD_SUB_UART_ID UART0_ID /* debug for netos */ + +#define BOARD_UART_BAUD_RATE 115200 +#define BOARD_UART_PARITY UART_PARITY_NONE +#define BOARD_UART_STOP_BITS UART_STOP_BITS_1 +#define BOARD_UART_DATA_BITS UART_DATA_BITS_8 +#define BOARD_UART_HW_FLOW_CTRL 0 + +/* spi */ +#define BOARD_SPI_MCLK (48 * 1000 * 1000) +#define BOARD_SPI_CS_LEVEL 0 +#define BOARD_SPI_PORT SPI0 + +/* sound card0 */ +#define BOARD_SOUNDCARD0_I2C_ID I2C0_ID +#define BOARD_SOUNDCARD0_I2C_ADDR_MODE I2C_ADDR_MODE_7BIT +#define BOARD_SOUNDCARD0_I2C_CLK 400000 +#define BOARD_SOUNDCARD0_CODEC_NAME "AC101" +#define BOARD_SOUNDCARD0_CODEC_WRITE HAL_I2C_Master_Transmit_Mem_IT +#define BOARD_SOUNDCARD0_CODEC_READ HAL_I2C_Master_Receive_Mem_IT + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARD_CONFIG_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd.h b/platform/mcu/xr871/project/common/cmd/cmd.h new file mode 100644 index 0000000000..f212897796 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_H_ +#define _CMD_H_ + +#include "common/cmd/cmd_util.h" + +#include "common/cmd/cmd_echo.h" +#include "common/cmd/cmd_mem.h" +#include "common/cmd/cmd_heap.h" +#include "common/cmd/cmd_upgrade.h" +#include "common/cmd/cmd_sysinfo.h" + +#include "common/cmd/cmd_clock.h" +#include "common/cmd/cmd_uart.h" +#include "common/cmd/cmd_timer.h" +#include "common/cmd/cmd_wdg.h" +#include "common/cmd/cmd_rtc.h" +#include "common/cmd/cmd_irrx.h" +#include "common/cmd/cmd_irtx.h" +#include "common/cmd/cmd_ce.h" +#include "common/cmd/cmd_i2c.h" +#include "common/cmd/cmd_adc.h" +#include "common/cmd/cmd_flash.h" +#include "common/cmd/cmd_pwm.h" +#include "common/cmd/cmd_sd.h" +#include "common/cmd/cmd_efpg.h" +#include "common/cmd/cmd_audio.h" + +#include "common/cmd/cmd_pm.h" +#include "common/cmd/cmd_fs.h" +#include "common/cmd/cmd_cedarx.h" + +#include "common/cmd/cmd_wlan.h" +#include "common/cmd/cmd_ifconfig.h" +#include "common/cmd/cmd_smart_config.h" +#include "common/cmd/cmd_airkiss.h" +#include "common/cmd/cmd_ping.h" +#include "common/cmd/cmd_iperf.h" +#include "common/cmd/cmd_sntp.h" +#include "common/cmd/cmd_httpc.h" +#include "common/cmd/cmd_httpd.h" +#include "common/cmd/tls/cmd_tls.h" +#include "common/cmd/cmd_mqtt.h" +#include "common/cmd/cmd_ota.h" +#include "common/cmd/cmd_dhcpd.h" +#include "common/cmd/cmd_nopoll.h" + +#include "common/cmd/cmd_netcmd.h" +#include "common/cmd/cmd_etf.h" +#include "common/cmd/cmd_broadcast.h" +#include "common/cmd/cmd_arp.h" + +#endif /* _CMD_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_adc.c b/platform/mcu/xr871/project/common/cmd/cmd_adc.c new file mode 100644 index 0000000000..e7e1716645 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_adc.c @@ -0,0 +1,407 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_adc.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_adc.h" + +#define CMD_ADC_TEST_DBG 0 + +static uint8_t cmd_adc_pass; + +static struct cmd_adc_test_priv{ + uint8_t enable; + uint8_t irq_mode; + uint32_t low_value; + uint32_t high_value; + uint32_t voltage; + uint32_t deviation; +} priv[ADC_CHANNEL_NUM]; + +static enum cmd_status cmd_adc_output_check(uint32_t data, uint32_t voltage, + uint32_t deviation) +{ + uint32_t voltage_low, voltage_high; + + voltage_low = (voltage < deviation) ? 0 : (voltage - deviation); + voltage_high = ((voltage + deviation) > 2500) ? 2500 : (voltage + deviation); + + voltage_low = voltage_low * 4096 / 2500; + voltage_high = voltage_high * 4096 / 2500; + + if ((data >= voltage_low) && (data <= voltage_high)) { +#if CMD_ADC_TEST_DBG + CMD_DBG("ADC: data = %u, voltage_low = %u, voltage_high = %u\n", + data, voltage_low, voltage_high); +#endif /* CMD_ADC_TEST_DBG */ + return CMD_STATUS_OK; + } else { + CMD_ERR("ADC: data = %u, voltage_low = %u, voltage_high = %u\n", + data, voltage_low, voltage_high); + return CMD_STATUS_FAIL; + } +} + +static void cmd_adc_irq_cb(void *arg) +{ + uint32_t channel, data; + ADC_IRQState irq_state; + + for (channel = ADC_CHANNEL_0; channel < ADC_CHANNEL_NUM; channel++) { + if (priv[channel].enable == 0) + continue; + + data = HAL_ADC_GetValue((ADC_Channel)channel); + irq_state = HAL_ADC_GetIRQState((ADC_Channel)channel); + +#if CMD_ADC_TEST_DBG + CMD_DBG("channel = %u, irq_mode = %u, irq_state = %d, low_value = %u, high_value = %u, data = %u\n", + channel, priv[channel].irq_mode, irq_state, priv[channel].low_value, + priv[channel].high_value, data); +#endif /* CMD_ADC_TEST_DBG */ + + if (CMD_STATUS_OK != cmd_adc_output_check(data, priv[channel].voltage, priv[channel].deviation)) + cmd_adc_pass = 0; + + switch (priv[channel].irq_mode) { + case ADC_IRQ_NONE: + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_NONE, irq_state = %d\n", irq_state); + break; + case ADC_IRQ_DATA: + if (irq_state != ADC_DATA_IRQ) { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_DATA, irq_state = %d\n", irq_state); + } + break; + case ADC_IRQ_LOW: + if ((irq_state != ADC_LOW_IRQ) || (data > priv[channel].low_value)) { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_LOW, irq_state = %d, low_value = %u, data = %u\n", + irq_state, priv[channel].low_value, data); + } + break; + case ADC_IRQ_HIGH: + if ((irq_state != ADC_HIGH_IRQ) || (data < priv[channel].high_value)) { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_HIGH, irq_state = %d, high_value = %u, data = %u\n", + irq_state, priv[channel].high_value, data); + } + break; + case ADC_IRQ_LOW_DATA: + if (irq_state == ADC_LOW_DATA_IRQ) { + if (data > priv[channel].low_value) { + cmd_adc_pass = 0; + CMD_ERR("irq_state = %d, low_value = %u, data = %u\n", + irq_state, priv[channel].low_value, data); + } + } else if (irq_state != ADC_DATA_IRQ) { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_LOW_DATA, irq_state = %d\n", irq_state); + } + break; + case ADC_IRQ_HIGH_DATA: + if (irq_state == ADC_HIGH_DATA_IRQ) { + if (data < priv[channel].high_value) { + cmd_adc_pass = 0; + CMD_ERR("irq_state = %d, high_value = %u, data = %u\n", + irq_state, priv[channel].high_value, data); + } + } else if (irq_state != ADC_DATA_IRQ) { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_HIGH_DATA, irq_state = %d\n", irq_state); + } + break; + case ADC_IRQ_LOW_HIGH: + if (irq_state == ADC_LOW_IRQ) { + if (data > priv[channel].low_value) { + cmd_adc_pass = 0; + CMD_ERR("irq_state = %d, low_value = %u, data = %u\n", + irq_state, priv[channel].low_value, data); + } + } else if (irq_state == ADC_HIGH_IRQ) { + if (data < priv[channel].high_value) { + cmd_adc_pass = 0; + CMD_ERR("irq_state = %d, high_value = %u, data = %u\n", + irq_state, priv[channel].high_value, data); + } + } else { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_LOW_HIGH, irq_state = %d\n", irq_state); + } + break; + case ADC_IRQ_LOW_HIGH_DATA: + if (irq_state == ADC_LOW_DATA_IRQ) { + if (data > priv[channel].low_value) { + cmd_adc_pass = 0; + CMD_ERR("irq_state = %d, low_value = %u, data = %u\n", + irq_state, priv[channel].low_value, data); + } + } else if (irq_state == ADC_HIGH_DATA_IRQ) { + if (data < priv[channel].high_value) { + cmd_adc_pass = 0; + CMD_ERR("irq_state = %d, high_value = %u, data = %u\n", + irq_state, priv[channel].high_value, data); + } + } else if (irq_state != ADC_DATA_IRQ) { + cmd_adc_pass = 0; + CMD_ERR("irq_mode: ADC_IRQ_LOW_HIGH_DATA, irq_state = %d\n", irq_state); + } + break; + default: + cmd_adc_pass = 0; + CMD_ERR("channel = %u, irq_mode = %u\n", channel, priv[channel].irq_mode); + } + } + + return; +} + +static enum cmd_status cmd_adc_init_exec(char *cmd) +{ + int cnt; + uint32_t freq; + uint32_t delay; + ADC_InitParam adc_param; + HAL_Status hal_status; + + cnt = cmd_sscanf(cmd, "f=%u d=%u", &freq, &delay); + if (cnt != 2) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if ((freq < 1000) || (freq > 1000000)) { + CMD_ERR("invalid freq %u\n", freq); + return CMD_STATUS_INVALID_ARG; + } + + if ((delay >> 8) != 0) { + CMD_ERR("invalid delay %u\n", delay); + return CMD_STATUS_INVALID_ARG; + } + + cmd_memset(priv, 0, ADC_CHANNEL_NUM * sizeof(struct cmd_adc_test_priv)); + + adc_param.freq = freq; + adc_param.delay = delay; + + hal_status = HAL_ADC_Init(&adc_param); + if (hal_status == HAL_OK) { + return CMD_STATUS_OK; + } else { + CMD_ERR("HAL_ADC_Init return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } +} + +static enum cmd_status cmd_adc_deinit_exec(char *cmd) +{ + HAL_Status hal_status; + + hal_status = HAL_ADC_DeInit(); + if (hal_status == HAL_OK) { + return CMD_STATUS_OK; + } else { + CMD_ERR("HAL_ADC_DeInit return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } +} + +static enum cmd_status cmd_adc_conv_polling_exec(char *cmd) +{ + int cnt; + uint32_t channel, voltage, deviation; + uint32_t data; + HAL_Status hal_status; + + cnt = cmd_sscanf(cmd, "c=%u v=%u d=%u", &channel, &voltage, &deviation); + if (cnt != 3) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (channel >= ADC_CHANNEL_NUM) { + CMD_ERR("invalid channel %u\n", channel); + return CMD_STATUS_INVALID_ARG; + } + + if (voltage > 2500) { + CMD_ERR("invalid voltage %u\n", voltage); + return CMD_STATUS_INVALID_ARG; + } + + if (deviation > 2500) { + CMD_ERR("invalid deviation %u\n", deviation); + return CMD_STATUS_INVALID_ARG; + } + + hal_status = HAL_ADC_Conv_Polling((ADC_Channel)channel, &data, 10000); + if (hal_status != HAL_OK) { + CMD_ERR("HAL_ADC_Conv_Polling return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } + + return cmd_adc_output_check(data, voltage, deviation); +} + +static enum cmd_status cmd_adc_config_exec(char *cmd) +{ + int cnt; + uint32_t channel, enable, irq_mode, low_value, high_value, voltage, deviation; + HAL_Status hal_status; + + cnt = cmd_sscanf(cmd, "c=%u e=%u i=%u l=%u h=%u v=%u d=%u", + &channel, &enable, &irq_mode, &low_value, + &high_value, &voltage, &deviation); + if (cnt != 7) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (channel >= ADC_CHANNEL_NUM) { + CMD_ERR("invalid channel %u\n", channel); + return CMD_STATUS_INVALID_ARG; + } + + if (enable > 1) { + CMD_ERR("invalid enable %u\n", enable); + return CMD_STATUS_INVALID_ARG; + } + + if (irq_mode > 7) { + CMD_ERR("invalid irq_mode %u\n", irq_mode); + return CMD_STATUS_INVALID_ARG; + } + + if ((low_value >> 12) != 0) { + CMD_ERR("invalid low_value %u\n", low_value); + return CMD_STATUS_INVALID_ARG; + } + + if ((high_value >> 12) != 0) { + CMD_ERR("invalid high_value %u\n", high_value); + return CMD_STATUS_INVALID_ARG; + } + + if (voltage > 2500) { + CMD_ERR("invalid voltage %u\n", voltage); + return CMD_STATUS_INVALID_ARG; + } + + if (deviation > 2500) { + CMD_ERR("invalid deviation %u\n", deviation); + return CMD_STATUS_INVALID_ARG; + } + + hal_status = HAL_ADC_ConfigChannel((ADC_Channel)channel, (ADC_Select)enable, + (ADC_IRQMode)irq_mode, low_value, high_value); + if (hal_status != HAL_OK) { + CMD_ERR("HAL_ADC_ConfigChannel return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } + + priv[channel].enable = (uint8_t)enable; + priv[channel].irq_mode = (uint8_t)irq_mode; + priv[channel].low_value = low_value; + priv[channel].high_value = high_value; + priv[channel].voltage = voltage; + priv[channel].deviation = deviation; + +#if CMD_ADC_TEST_DBG + CMD_DBG("ADC config: channel = %u, enable = %u, irq_mode = %u, low_value = %u, high_value = %u, voltage = %u, deviation = %u\n", + channel, enable, irq_mode, low_value, high_value, voltage, deviation); +#endif /* CMD_ADC_TEST_DBG */ + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_adc_conv_it_start_exec(char *cmd) +{ + ADC_Channel chan; + HAL_Status hal_status; + + cmd_adc_pass = 1; + + for (chan = ADC_CHANNEL_0; chan < ADC_CHANNEL_NUM; chan++) { + hal_status = HAL_ADC_EnableIRQCallback(chan, cmd_adc_irq_cb, NULL); + if (hal_status != HAL_OK) { + CMD_ERR("HAL_ADC_EnableIRQCallback return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } + } + + hal_status = HAL_ADC_Start_Conv_IT(); + if (hal_status != HAL_OK) { + CMD_ERR("HAL_ADC_Start_Conv_IT return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_adc_conv_it_stop_exec(char *cmd) +{ + ADC_Channel chan; + HAL_Status hal_status; + + hal_status = HAL_ADC_Stop_Conv_IT(); + if (hal_status != HAL_OK) { + CMD_ERR("HAL_ADC_Stop_Conv_IT return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } + + for (chan = ADC_CHANNEL_0; chan < ADC_CHANNEL_NUM; chan++) { + hal_status = HAL_ADC_DisableIRQCallback(chan); + if (hal_status != HAL_OK) { + CMD_ERR("HAL_ADC_DisableIRQCallback return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } + } + + if (cmd_adc_pass == 1) + return CMD_STATUS_OK; + else + return CMD_STATUS_FAIL; +} + +static struct cmd2_data g_adc_cmds[] = { + { "init ", 5, cmd_adc_init_exec }, + { "deinit", 6, cmd_adc_deinit_exec }, + { "conv-polling ", 13, cmd_adc_conv_polling_exec }, + { "config ", 7, cmd_adc_config_exec }, + { "conv-it-start", 13, cmd_adc_conv_it_start_exec }, + { "conv-it-stop", 12, cmd_adc_conv_it_stop_exec }, +}; + +enum cmd_status cmd_adc_exec(char *cmd) +{ + return cmd2_exec(cmd, g_adc_cmds, cmd_nitems(g_adc_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_adc.h b/platform/mcu/xr871/project/common/cmd/cmd_adc.h new file mode 100644 index 0000000000..a07c81cc8f --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_adc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_ADC_H_ +#define _CMD_ADC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_adc_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_ADC_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_airkiss.c b/platform/mcu/xr871/project/common/cmd/cmd_airkiss.c new file mode 100644 index 0000000000..ba38aa7df5 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_airkiss.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "common/framework/net_ctrl.h" +#include "net/wlan/wlan.h" +#include "net/wlan/wlan_defs.h" +#include + +#define AK_TIME_OUT_MS 120000 +#define AK_ACK_TIME_OUT_MS 30000 +static char *key = "1234567812345678"; + +static OS_Thread_t g_ak_ctrl_thread; +#define AK_CTRL_THREAD_STACK_SIZE (1 * 1024) + +static void ak_task(void *arg) +{ + int ret; + wlan_airkiss_status_t status; + wlan_airkiss_result_t result; + + memset(&result, 0, sizeof(result)); + + net_switch_mode(WLAN_MODE_MONITOR); + + status = wlan_airkiss_start(g_wlan_netif, AK_TIME_OUT_MS, &result); + + net_switch_mode(WLAN_MODE_STA); + + if (status == WLAN_AIRKISS_SUCCESS) { + CMD_DBG("ssid: %.32s\n", (char *)result.ssid); + CMD_DBG("psk: %s\n", (char *)result.passphrase); + CMD_DBG("random: %d\n", result.random_num); + } else { + CMD_DBG ("airkiss failed %d\n", status); + OS_ThreadDelete(&g_ak_ctrl_thread); + return; + } + + if (result.passphrase[0] != '\0') { + wlan_sta_set(result.ssid, result.ssid_len, result.passphrase); + } else { + wlan_sta_set(result.ssid, result.ssid_len, NULL); + } + + wlan_sta_enable(); + + ret = wlan_airkiss_ack_start(g_wlan_netif, result.random_num, AK_ACK_TIME_OUT_MS); + if (ret < 0) + CMD_DBG("airkiss ack error, ap connect time out\n"); + + OS_ThreadDelete(&g_ak_ctrl_thread); +} + +static int ak_create() +{ + if (OS_ThreadCreate(&g_ak_ctrl_thread, + "ak_thread", + ak_task, + NULL, + OS_THREAD_PRIO_APP, + AK_CTRL_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("create ak thread failed\n"); + return -1; + } + return 0; +} + +enum cmd_status cmd_airkiss_exec(char *cmd) +{ + int ret = 0; + + if (g_wlan_netif == NULL) { + return CMD_STATUS_FAIL; + } + + if (cmd_strcmp(cmd, "start") == 0) { + if (OS_ThreadIsValid(&g_ak_ctrl_thread)) { + CMD_ERR("Airkiss is already start\n"); + ret = -1; + } else { + ret = ak_create(); + } + } else if (cmd_strcmp(cmd, "set_key") == 0) { + ret = wlan_airkiss_set_key(key, WLAN_AIRKISS_KEY_LEN); + CMD_DBG("Airkiss set key : %s\n", key); + } else if (cmd_strcmp(cmd, "stop") == 0) { + ret = wlan_airkiss_stop(); + } else { + CMD_ERR("invalid argument '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + return (ret == 0 ? CMD_STATUS_OK : CMD_STATUS_FAIL); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_airkiss.h b/platform/mcu/xr871/project/common/cmd/cmd_airkiss.h new file mode 100644 index 0000000000..a05d49daec --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_airkiss.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_AIRKISS_H_ +#define _CMD_AIRKISS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_airkiss_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_AIRKISS_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_arp.c b/platform/mcu/xr871/project/common/cmd/cmd_arp.c new file mode 100644 index 0000000000..f4e2afe844 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_arp.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "common/framework/net_ctrl.h" +#include "lwip/tcpip.h" +#include "netif/etharp.h" + +int arp_clean_table(struct netif *netif) +{ + tcpip_callback((tcpip_callback_fn)etharp_cleanup_netif, netif); + return 0; +} + +int arp_state(struct netif *netif) +{ +/* void etharp_printtable_netif(struct netif *netif); + tcpip_callback((tcpip_callback_fn)etharp_printtable_netif, netif); +*/ + return 0; +} + +int arp_del(struct netif *netif) +{ + return 0; +} + +int arp_set(struct netif *netif) +{ + return 0; +} + +enum cmd_status cmd_arp_exec(char *cmd) +{ + int ret = 0; + int argc; + char *argv[3]; + + if (g_wlan_netif == NULL) { + return CMD_STATUS_FAIL; + } + + argc = cmd_parse_argv(cmd, argv, cmd_nitems(argv)); + if (argc < 1) { + CMD_ERR("invalid arp cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(argv[0], "clean") == 0) { + ret = arp_clean_table(g_wlan_netif); + } else if (cmd_strcmp(argv[0], "state") == 0) { + ret = arp_state(g_wlan_netif); + } else if (cmd_strcmp(argv[0], "del") == 0) { + ret = arp_del(g_wlan_netif); + } else if (cmd_strcmp(argv[0], "set") == 0) { + ret = arp_set(g_wlan_netif); + } else { + CMD_ERR("invalid arp cmd <%s>\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + return (ret == 0 ? CMD_STATUS_OK : CMD_STATUS_FAIL); +} + + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_arp.h b/platform/mcu/xr871/project/common/cmd/cmd_arp.h new file mode 100644 index 0000000000..bcf7b8e5a5 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_arp.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_ARP_H_ +#define _CMD_ARP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_arp_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_ARP_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_audio.c b/platform/mcu/xr871/project/common/cmd/cmd_audio.c new file mode 100644 index 0000000000..4dde306cc6 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_audio.c @@ -0,0 +1,369 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_audio.h" +#include "audio/pcm/audio_pcm.h" +#include "audio/manager/audio_manager.h" +#include "driver/chip/hal_codec.h" +#include "fs/fatfs/ff.h" + +typedef struct { + int samplerate; + int channels; + struct pcm_config *pcm_config; +} audio_format_param; + +struct pcm_config stereo_44100_config = { + .channels = 2, + .rate = 44100, + .period_size = 2048, + .period_count = 2, + .format = PCM_FORMAT_S16_LE, +}; + +struct pcm_config mono_44100_config = { + .channels = 1, + .rate = 44100, + .period_size = 2048, + .period_count = 2, + .format = PCM_FORMAT_S16_LE, +}; + +struct pcm_config mono_8000_config = { + .channels = 1, + .rate = 8000, + .period_size = 2048, + .period_count = 2, + .format = PCM_FORMAT_S16_LE, +}; + +struct pcm_config stereo_8000_config = { + .channels = 2, + .rate = 8000, + .period_size = 2048, + .period_count = 2, + .format = PCM_FORMAT_S16_LE, +}; + +static audio_format_param audio_param[4] = { + {8000, 1, &mono_8000_config}, + {8000, 2, &stereo_8000_config}, + {44100, 1, &mono_44100_config}, + {44100, 2, &stereo_44100_config}, +}; + +static char file_path[50] = {0}; +#define TEST_DELAY_TIME 0X1FF + +#define SOUND_PLAYCARD AUDIO_CARD0 +#define SOUND_CAPCARD AUDIO_CARD0 + +#define SEARCH_FOREACH_CONFIG(a, b, c, i) for (i = 0; i < 4; i++) { \ + if (audio_param[i].samplerate == a && audio_param[i].channels == b) { \ + c = audio_param[i].pcm_config; \ + break; \ + } \ + } + + +#define CREATE_CAP_FILE(FILE_PATH, RES, FS, FILE) FRESULT RES; \ + FATFS fs; \ + FIL file; \ + memset(&fs, 0, sizeof(fs)); \ + fs.drv = 1; \ + if ((RES = f_mount(&fs, "0:/", 1)) != FR_OK) \ + CMD_ERR("failed to mount\n"); \ + else if ((RES = f_open(&file, FILE_PATH, FA_OPEN_ALWAYS|FA_READ|FA_WRITE)) != FR_OK) \ + CMD_ERR("[music file]failed to open,%s\n",file_path) + + +#define AUDIO_THREAD_STACK_SIZE (2 * 1024) +static OS_Thread_t g_audio_stream_thread; +static OS_Thread_t g_audio_control_thread; + +#define AUDIO_DELETE_THREAD(THREAD) OS_ThreadDelete(&THREAD) + +#define AUDIO_CREAT_THREAD(THREAD, TASK, ARG) \ + if (OS_ThreadIsValid(&THREAD)) { \ + CMD_ERR("audio task is running\n"); \ + return CMD_STATUS_FAIL; \ + } \ + if (OS_ThreadCreate(&THREAD, \ + "", \ + TASK, \ + (void *)ARG, \ + OS_THREAD_PRIO_APP, \ + AUDIO_THREAD_STACK_SIZE) != OS_OK) { \ + CMD_ERR("audio task create failed\n"); \ + return CMD_STATUS_FAIL; \ + } + +void cap_exec(void *cmd) +{ + int argc, i = 0, ret = 0; + unsigned int writenum = 0; + char *argv[5]; + struct pcm_config *config = NULL; + + argc = cmd_parse_argv(cmd, argv, 5); + if (argc < 3) { + CMD_ERR("invalid audio capture cmd, argc %d\n", argc); + goto exit_thread; + } + int samplerate = cmd_atoi(argv[0]); + int channels = cmd_atoi(argv[1]); + cmd_memset(file_path, 0, 50); + cmd_strlcpy(file_path, argv[2], 50); + + CMD_DBG("CMD:drv audio cap (samplerate)%d (channel)%d (file)%s\n", samplerate, channels,file_path); + + CREATE_CAP_FILE(file_path, result, fs, file); + if (result != FR_OK) { + CMD_ERR("creat file failed.\n"); + goto exit_thread; + } + + SEARCH_FOREACH_CONFIG(samplerate, channels, config, i); + if (config == NULL) { + CMD_ERR("invalid audio cap param.\n"); + f_close(&file); + goto exit_thread; + } + + unsigned int pcm_buf_size = (config->channels)*2*(config->period_size); + char *pcm_data = malloc(pcm_buf_size); + if (pcm_data == NULL) { + CMD_ERR("malloc buf failed\n"); + f_close(&file); + goto exit_thread; + } + memset(pcm_data, 0, pcm_buf_size); + + if (snd_pcm_open(config, SOUND_CAPCARD, PCM_IN) != 0) + { + CMD_ERR("sound card open err\n"); + goto exit; + } + unsigned int delay_time = TEST_DELAY_TIME; + + CMD_DBG("Capture run.\n"); + while (--delay_time != 0) { + + ret = snd_pcm_read(config, SOUND_CAPCARD, pcm_data, pcm_buf_size); + if (ret != pcm_buf_size) { + CMD_ERR("read data failed(%d),line:%d\n", ret, __LINE__); + break; + } + if ((result = f_write(&file, pcm_data, pcm_buf_size, &writenum)) != FR_OK) { + CMD_ERR("write failed(%d).\n",result); + break; + } else { + if (writenum != pcm_buf_size) { + CMD_ERR("write failed %d,%d\n", writenum, __LINE__); + break; + } + } + } + snd_pcm_close(SOUND_CAPCARD, PCM_IN); + +exit: + free(pcm_data); + f_close(&file); + //f_mount(NULL, "", 1); + CMD_DBG("Capture end.\n"); +exit_thread: + AUDIO_DELETE_THREAD(g_audio_stream_thread); +} + +void play_exec(void *cmd) +{ + int argc, i = 0; + unsigned int readnum = 0; + char *argv[5]; + struct pcm_config *config = NULL; + + argc = cmd_parse_argv(cmd, argv, 5); + if (argc < 3) { + CMD_ERR("invalid audio capture cmd, argc %d\n", argc); + goto exit_thread; + } + int samplerate = cmd_atoi(argv[0]); + int channels = cmd_atoi(argv[1]); + cmd_memset(file_path, 0, 50); + cmd_strlcpy(file_path, argv[2], 50); + + CMD_DBG("CMD:drv audio play (samplerate)%d (channel)%d (file)%s\n", samplerate, channels,file_path); + + CREATE_CAP_FILE(file_path, result, fs, file); + if (result != FR_OK) { + CMD_ERR("creat file failed.\n"); + goto exit_thread; + } + + SEARCH_FOREACH_CONFIG(samplerate, channels, config, i); + if (config == NULL) { + CMD_ERR("invalid audio cap param.\n"); + f_close(&file); + goto exit_thread; + } + + unsigned int pcm_buf_size = (config->channels)*2*(config->period_size); + char *pcm_data = malloc(pcm_buf_size); + if (pcm_data == NULL) { + CMD_ERR("malloc buf failed\n"); + f_close(&file); + goto exit_thread;; + } + if (snd_pcm_open(config, SOUND_PLAYCARD, PCM_OUT) != 0) + { + CMD_ERR("sound card open err\n"); + goto exit; + } + CMD_DBG("Play on.\n"); + while (1) { + if ((result = f_read(&file, pcm_data, pcm_buf_size, &readnum)) != FR_OK) { + CMD_ERR("read failed(%d).\n",result); + break; + } else { + if (readnum != pcm_buf_size) { + CMD_DBG("file end: file size = %d\n", readnum); + break; + } + } + snd_pcm_write(config, SOUND_PLAYCARD, pcm_data, pcm_buf_size); + } + snd_pcm_close(SOUND_PLAYCARD, PCM_OUT); + +exit: + f_close(&file); + //f_mount(NULL, "", 1); + free(pcm_data); + CMD_DBG("Play end.\n"); +exit_thread: + AUDIO_DELETE_THREAD(g_audio_stream_thread); + +} + +void vol_exec(void *cmd) +{ + int argc; + char *argv[2]; + + argc = cmd_parse_argv(cmd, argv, 2); + if (argc < 1) { + CMD_ERR("invalid audio set vol cmd, argc %d\n", argc); + goto exit; + } + int vol = cmd_atoi(argv[0]); + CMD_DBG("CMD:drv audio vol (level)%d\n", vol); + + if ( vol > aud_mgr_maxvol()) { + CMD_ERR("invalid audio vol.Range(0-31)\n"); + goto exit; + } + + aud_mgr_handler(AUDIO_DEVICE_MANAGER_VOLUME, vol); +exit: + AUDIO_DELETE_THREAD(g_audio_control_thread); +} + +void path_exec(void *cmd) +{ + int argc; + char *argv[2]; + + argc = cmd_parse_argv(cmd, argv, 2); + if (argc < 1) { + CMD_ERR("invalid audio set path cmd, argc %d\n", argc); + goto exit; + } + int path = cmd_atoi(argv[0]); + CMD_DBG("CMD:drv audio out-path %d\n", path); + + if (path > AUDIO_DEVICE_SPEAKER) { + CMD_ERR("invalid audio out-path.Range(1-2)\n"); + goto exit; + } + + aud_mgr_handler(AUDIO_DEVICE_MANAGER_PATH, path); +exit: + AUDIO_DELETE_THREAD(g_audio_control_thread); +} + +static enum cmd_status audio_play_task(char *arg) +{ + char *cmd = (char *)arg; + + AUDIO_CREAT_THREAD(g_audio_stream_thread, play_exec, cmd); + return CMD_STATUS_OK; +} + +static enum cmd_status audio_cap_task(char *arg) +{ + char *cmd = (char *)arg; + + AUDIO_CREAT_THREAD(g_audio_stream_thread, cap_exec, cmd); + return CMD_STATUS_OK; +} + +static enum cmd_status audio_vol_task(char *arg) +{ + char *cmd = (char *)arg; + + AUDIO_CREAT_THREAD(g_audio_control_thread, vol_exec, cmd); + return CMD_STATUS_OK; +} + +static enum cmd_status audio_path_task(char *arg) +{ + char *cmd = (char *)arg; + + AUDIO_CREAT_THREAD(g_audio_control_thread, path_exec, cmd); + return CMD_STATUS_OK; +} + +static struct cmd_data g_audio_cmds[] = { + { "cap", audio_cap_task }, + { "play", audio_play_task }, + { "vol", audio_vol_task }, + { "path", audio_path_task }, +}; + +void audio_task_run(void *arg) +{ + char *cmd = (char *)arg; + cmd_exec(cmd, g_audio_cmds, cmd_nitems(g_audio_cmds)); +} + +enum cmd_status cmd_audio_exec(char *cmd) +{ + audio_task_run(cmd); + return CMD_STATUS_OK; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_audio.h b/platform/mcu/xr871/project/common/cmd/cmd_audio.h new file mode 100644 index 0000000000..a4d7a0d93d --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_audio.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_AUDIO_H_ +#define _CMD_AUDIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * drv audio + * stream-cmd : play cap + * samplerate: 8000 44100 + * channel: 1 2 + * file: + * example: + * drv audio play 44100 2 0:/8.pcm + * drv audio cap 44100 2 0:/8.pcm + * + * drv audio + * + * example: + * control-cmd: vol out-path + * arg:vol (1- 30) + * path 0 1 + * drv audio vol 25 + * drv audio out-path 0 + */ + +enum cmd_status cmd_audio_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_AUDIO_H_ */ + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_broadcast.c b/platform/mcu/xr871/project/common/cmd/cmd_broadcast.c new file mode 100644 index 0000000000..80f60dac13 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_broadcast.c @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "net/lwip/lwip/sockets.h" + +#define BROADCAST_THREAD_STACK_SIZE (2 * 1024) +#define RECEIVE_BUF_LEN 1500 +OS_Thread_t g_broadcast_thread; + +typedef enum { + THREAD_STOP, + THREAD_RUN, +} run_flag; + +typedef enum { + BROADCAST_RECV, + BROADCAST_SEND, +} broadcast_mode; + +typedef struct { + int port; + ip_addr_t ip_addr; + broadcast_mode mode; + u16_t data_range_min; + u16_t data_range_max; + int time; + int count; + char* data_p; + run_flag run_flag; + int num; +} broadcast_format_param; + +static broadcast_format_param broadcast_param; + +static int get_range(char *buf, u16_t *min, u16_t *max) +{ + char *start, *end; + start = end = buf; + u16_t min_t = 0, max_t = 0; + + if (buf == NULL || min == NULL || max == NULL) + return -1; + if (*start == ',') { + min_t = 0; + max_t = (u16_t)atoi(++start); + if (max_t < min_t) + return -1; + *min = min_t; + *max = max_t; + return 0; + } else { + while (*end != ',' && *end != '\0') + end++; + if (*end == '\0') + return -1; + *end = '\0'; + min_t = (u16_t)atoi(start); + start = ++end; + if (*start == '\0') + max_t = 65535; + else + max_t = (u16_t)atoi(start); + if (max_t < min_t) + return -1; + *min = min_t; + *max = max_t; + return 0; + } +} + +int recv_broadcast_packet(broadcast_format_param *param) +{ + int fd; + int optval = 1; + int sock_timeout_val = 1000;//1s + int data_len=0; + char *message_buf; + struct sockaddr_in addr; + socklen_t addr_len = sizeof(addr); + + message_buf = malloc(RECEIVE_BUF_LEN); + if (message_buf == NULL) { + CMD_ERR("message_buf malloc faild\n"); + return -1; + } +/* + CMD_DBG("port=%d ip=%s mode=%d data_range_min=%d data_range_max=%d\n", + param->port, ipaddr_ntoa((ip_addr_t*)(&(param->ip_addr))), + param->mode, param->data_range_min, param->data_range_max); +*/ + memset(&addr, 0, sizeof(addr)); + addr.sin_family = AF_INET; + addr.sin_addr.s_addr = htonl(INADDR_ANY); + addr.sin_port = htons(param->port); + + fd = socket(AF_INET, SOCK_DGRAM, 0); + if (fd == -1) { + CMD_ERR("socket create failed\n"); + return -1; + } + + setsockopt(fd, SOL_SOCKET, SO_BROADCAST, (void*)&optval, sizeof(optval)); + setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, + (void*)&sock_timeout_val, sizeof(sock_timeout_val)); + if (bind(fd, (struct sockaddr *)&addr, sizeof(addr)) == -1) { + CMD_ERR("socket bind failed\n"); + closesocket(fd); + return -1; + } + param->run_flag = THREAD_RUN; + while (param->run_flag) { + data_len = recvfrom(fd, message_buf, RECEIVE_BUF_LEN, 0, + (struct sockaddr *)&addr, &addr_len); + if ((data_len > 0) && (data_len >= param->data_range_min) && + (data_len <= param->data_range_max)) { + if (param->ip_addr.addr == INADDR_BROADCAST) { + param->num++; + //CMD_DBG("Receive message:%.*s\n", data_len, message_buf); + } else if (param->ip_addr.addr == addr.sin_addr.s_addr) { + param->num++; + //CMD_DBG("Receive message:%.*s\n", data_len, message_buf); + } + } + } + CMD_DBG("broadcast packets num received: %d\n", param->num); + closesocket(fd); + free(message_buf); + return 0; +} + +void broadcast_run(void *param) +{ + ((broadcast_format_param*)param)->num = 0; + if (((broadcast_format_param*)param)->mode == BROADCAST_RECV) + recv_broadcast_packet((broadcast_format_param*)param); + + OS_ThreadDelete(&g_broadcast_thread); +} + +int broadcast_start(broadcast_format_param *param) +{ + if (OS_ThreadIsValid(&g_broadcast_thread)) { + CMD_ERR("broadcast task is running\n"); + return -1; + } + if (OS_ThreadCreate(&g_broadcast_thread, + "", + broadcast_run, + (void *)param, + OS_THREAD_PRIO_APP, + BROADCAST_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("broadcast task create failed\n"); + return -1; + } + return 0; +} + +enum cmd_status broadcast_state_exec(char *cmd) +{ + CMD_DBG("broadcast packets num received: %d\n", broadcast_param.num); + return CMD_STATUS_OK; +} + +enum cmd_status broadcast_reset_exec(char *cmd) +{ + broadcast_param.num = 0; + return CMD_STATUS_OK; +} + +enum cmd_status broadcast_stop_exec(char *cmd) +{ + broadcast_param.run_flag = THREAD_STOP; + return CMD_STATUS_OK; +} + +enum cmd_status broadcast_recv_exec(char *cmd) +{ + int argc; + int port; + char ip_buf[16]; + char range_buf[12]; + int ret = 0; + + argc = cmd_sscanf(cmd, "p=%d i=%16s r=%12s", &port, ip_buf, range_buf); + if (argc != 3) { + CMD_ERR("invalid broadcast cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + + broadcast_param.mode = BROADCAST_RECV; + if (port > 65535 || port < 0) { + ret = -1; + goto exit; + } + broadcast_param.port = port; + if (inet_aton(ip_buf, &(broadcast_param.ip_addr)) == 0) { + ret = -1; + goto exit; + } + if (get_range(range_buf, &(broadcast_param.data_range_min), + &(broadcast_param.data_range_max)) != 0) { + ret = -1; + goto exit; + } + if (broadcast_start(&broadcast_param) != 0) { + ret = -1; + goto exit; + } + +exit: + if (ret != 0) { + CMD_ERR("invalid broadcast cmd '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + return CMD_STATUS_OK; +} + +enum cmd_status broadcast_send_exec(char *cmd) +{ + return CMD_STATUS_OK; +} + +/* + * dhcp commands + */ +static struct cmd_data g_broadcast_cmds[] = { + { "recv", broadcast_recv_exec }, + { "send", broadcast_send_exec }, + { "state", broadcast_state_exec }, + { "reset", broadcast_reset_exec }, + { "stop", broadcast_stop_exec }, +}; + +enum cmd_status cmd_broadcast_exec(char *cmd) +{ + return cmd_exec(cmd, g_broadcast_cmds, cmd_nitems(g_broadcast_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_broadcast.h b/platform/mcu/xr871/project/common/cmd/cmd_broadcast.h new file mode 100644 index 0000000000..4d5285567e --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_broadcast.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_BROADCAST_H_ +#define _CMD_BROADCAST_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_broadcast_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_BROADCAST_H_ */ + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ce.c b/platform/mcu/xr871/project/common/cmd/cmd_ce.c new file mode 100644 index 0000000000..5878320659 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ce.c @@ -0,0 +1,808 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_ce.h" +#include "driver/chip/hal_crypto.h" + +#define CE_TEST_KEYNUM 5 + +#define CE_TEST_KEYMAXSIZE sizeof(CE_AES_Config) + +typedef enum { + NONE, + AES, + DES, + TDES +} crypto_key_type; + +typedef struct { + crypto_key_type type; + void *key_cfg; +} crypto_key; + +static crypto_key key[CE_TEST_KEYNUM]; +static uint32_t srv_cnt; + +/*static CE_CRC_Handler crc; +static CE_MD5_Handler md5; +static CE_SHA1_Handler sha1; +static CE_SHA256_Handler sha256; + +uint32_t crc_cont; +uint32_t md5_cont; +uint32_t sha1_cont; +uint32_t sha256_cont;*/ + +static uint32_t md5_iv[4]; +static uint32_t sha1_iv[5]; +static uint32_t sha256_iv[8]; + +static enum cmd_status cmd_crypto_addkey_exec(char *cmd) +{ + int32_t cnt; + char type_str[8]; + char mode_str[8]; + uint32_t i = 0; + uint32_t keysize; + CE_Crypto_Mode mode; + void *p; + uint8_t buf[32]; + uint32_t keysrc; + + /* get param */ + cnt = cmd_sscanf(cmd, "t=%7s m=%7s k=%u", type_str, mode_str, &keysrc); + + /* check param */ + if (cnt != 3) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (keysrc > 10) { + CMD_ERR("invalid keysrc %d\n", keysrc); + return CMD_STATUS_INVALID_ARG; + } + + /* create key */ + while (key[i].type != NONE) { + i++; + if (i > CE_TEST_KEYNUM) { + CMD_ERR("key full\n"); + return CMD_STATUS_FAIL; + } + } + + key[i].key_cfg = cmd_malloc(CE_TEST_KEYMAXSIZE); // staic may be good. + p = key[i].key_cfg; + if (p == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + /* check param */ + if (cmd_strcmp(mode_str, "ecb") == 0) { + mode = CE_CRYPT_MODE_ECB; + } else if (cmd_strcmp(mode_str, "cbc") == 0) { + mode = CE_CRYPT_MODE_CBC; + } else { + cmd_free(key[i].key_cfg); + CMD_ERR("invalid mode %s\n", mode_str); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(type_str, "aes128") == 0) { + keysize = 16; + key[i].type = AES; + ((CE_AES_Config *)p)->mode = mode; + ((CE_AES_Config *)p)->src = (CE_Crypto_KeySrc)keysrc; + ((CE_AES_Config *)p)->keysize = CE_CTL_AES_KEYSIZE_128BITS; + } else if (cmd_strcmp(type_str, "aes192") == 0) { + keysize = 24; + key[i].type = AES; + ((CE_AES_Config *)p)->mode = mode; + ((CE_AES_Config *)p)->src = (CE_Crypto_KeySrc)keysrc; + ((CE_AES_Config *)p)->keysize = CE_CTL_AES_KEYSIZE_192BITS; + } else if (cmd_strcmp(type_str, "aes256") == 0) { + keysize = 32; + key[i].type = AES; + ((CE_AES_Config *)p)->mode = mode; + ((CE_AES_Config *)p)->src = (CE_Crypto_KeySrc)keysrc; + ((CE_AES_Config *)p)->keysize = CE_CTL_AES_KEYSIZE_256BITS; + } else if (cmd_strcmp(type_str, "des") == 0) { + keysize = 8; + key[i].type = DES; + ((CE_DES_Config *)p)->mode = mode; + ((CE_DES_Config *)p)->src = (CE_Crypto_KeySrc)keysrc; + } else if (cmd_strcmp(type_str, "3des") == 0) { + keysize = 24; + key[i].type = TDES; + ((CE_3DES_Config *)p)->mode = mode; + ((CE_3DES_Config *)p)->src = (CE_Crypto_KeySrc)keysrc; + } else { + cmd_free(key[i].key_cfg); + CMD_ERR("invalid type %s\n", type_str); + return CMD_STATUS_INVALID_ARG; + } + + cmd_write_respond(CMD_STATUS_OK, "%d", i); + + if (keysrc == 0) { + + cmd_raw_mode_enable(); + cnt = cmd_raw_mode_read(buf, keysize, 30000); + cmd_raw_mode_disable(); + + buf[cnt] = 0; + + switch (key[i].type) { + case AES: + cmd_memcpy(((CE_AES_Config *)p)->key, buf, keysize); + break; + case DES: + cmd_memcpy(((CE_DES_Config *)p)->key, buf, keysize); + break; + case TDES: + cmd_memcpy(((CE_3DES_Config *)p)->key, buf, keysize); + break; + default: + break; + } + } + + if (srv_cnt++ == 0) + HAL_CE_Init(); + + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_crypto_delkey_exec(char *cmd) +{ + int32_t cnt; + uint32_t i; + + /* get param */ + cnt = cmd_sscanf(cmd, "k=%u", &i); + + /* check param */ + if (cnt != 1) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if ((i >= CE_TEST_KEYNUM) || (key[i].type == NONE)) { + CMD_ERR("invalid key %d\n", i); + return CMD_STATUS_INVALID_ARG; + } + + cmd_free(key[i].key_cfg); + key[i].type = NONE; + + if (--srv_cnt == 0) + HAL_CE_Deinit(); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_crypto_keyiv_exec(char *cmd) +{ + int32_t cnt; + uint32_t i; + uint32_t size; + void *p; + uint8_t buf[16]; + uint32_t iv_size; + + + /* get param */ + cnt = cmd_sscanf(cmd, "k=%u s=%u", &i, &size); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if ((i >= CE_TEST_KEYNUM) || (key[i].type == NONE)) { + CMD_ERR("invalid key %d\n", i); + return CMD_STATUS_INVALID_ARG; + } + + if (key[i].type == AES) { + iv_size = 16; + if (size > 16) { + CMD_ERR("invalid size %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + } else { + iv_size = 8; + if (size > 8) { + CMD_ERR("invalid size %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + } + + p = key[i].key_cfg; + + cmd_write_respond(CMD_STATUS_OK, "%d", iv_size); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, iv_size, 30000); + cmd_raw_mode_disable(); + + switch (key[i].type) { + case AES: + cmd_memset(((CE_AES_Config *)p)->iv, 0, iv_size); + cmd_memcpy(((CE_AES_Config *)p)->iv, buf, size); + break; + case DES: + cmd_memset(((CE_DES_Config *)p)->iv, 0, iv_size); + cmd_memcpy(((CE_DES_Config *)p)->iv, buf, size); + break; + case TDES: + cmd_memset(((CE_3DES_Config *)p)->iv, 0, iv_size); + cmd_memcpy(((CE_3DES_Config *)p)->iv, buf, size); + break; + default: + break; + } + + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_crypto_enc_exec(char *cmd) +{ + int32_t cnt; + uint32_t keyi; + uint32_t size; + uint32_t enc_size; + uint8_t *plain; + uint8_t *cipher; + + /* get param */ + cnt = cmd_sscanf(cmd, "k=%u s=%u", &keyi, &size); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if ((keyi >= CE_TEST_KEYNUM) || (key[keyi].type == NONE)) { + CMD_ERR("invalid key %d\n", keyi); + return CMD_STATUS_INVALID_ARG; + } + + plain = cmd_malloc(size); + if (plain == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cipher = cmd_malloc(size + 16); + if (cipher == NULL) { + CMD_ERR("no memory\n"); + cmd_free(plain); + return CMD_STATUS_FAIL; + } + + if (key[keyi].type == AES) + enc_size = (size + 15) & (~0xF); + else + enc_size = (size + 7) & (~0x7); + + cmd_write_respond(CMD_STATUS_OK, "%d", enc_size); + cmd_raw_mode_enable(); + cmd_raw_mode_read(plain, size, 30000); + + switch (key[keyi].type) { + case AES: + HAL_AES_Encrypt((CE_AES_Config *)(key[keyi].key_cfg), plain, cipher, size); + break; + case DES: + HAL_DES_Encrypt((CE_DES_Config *)(key[keyi].key_cfg), plain, cipher, size); + break; + case TDES: + HAL_3DES_Encrypt((CE_3DES_Config *)(key[keyi].key_cfg), plain, cipher, size); + break; + default: + break; + } + + cmd_raw_mode_write(cipher, enc_size); + cmd_raw_mode_disable(); + + cmd_free(plain); + cmd_free(cipher); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_crypto_dec_exec(char *cmd) +{ + int32_t cnt; + uint32_t keyi; + uint32_t size; + uint8_t *plain; + uint8_t *cipher; + + /* get param */ + cnt = cmd_sscanf(cmd, "k=%u s=%u", &keyi, &size); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if ((keyi >= CE_TEST_KEYNUM) || (key[keyi].type == NONE)) { + CMD_ERR("invalid key %d\n", keyi); + return CMD_STATUS_INVALID_ARG; + } + + if (key[keyi].type == AES) { + if (size & 0xF) { + CMD_ERR("invalid size %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + } else { + if (size & 0x7) { + CMD_ERR("invalid size %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + } + + plain = cmd_malloc(size); + if (plain == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cipher = cmd_malloc(size + 16); + if (cipher == NULL) { + CMD_ERR("no memory\n"); + cmd_free(plain); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "%d", size); + cmd_raw_mode_enable(); + cmd_raw_mode_read(cipher, size, 30000); + + switch (key[keyi].type) { + case AES: + HAL_AES_Decrypt((CE_AES_Config *)(key[keyi].key_cfg), cipher, plain, size); + break; + case DES: + HAL_DES_Decrypt((CE_DES_Config *)(key[keyi].key_cfg), cipher, plain, size); + break; + case TDES: + HAL_3DES_Decrypt((CE_3DES_Config *)(key[keyi].key_cfg), cipher, plain, size); + break; + default: + break; + } + + cmd_raw_mode_write(plain, size); + cmd_raw_mode_disable(); + + cmd_free(plain); + cmd_free(cipher); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_crypto_crc_exec(char *cmd) +{ + char type_str[16]; + CE_CRC_Types type; + uint32_t size; + + uint8_t *buf; + CE_CRC_Handler crc; + uint32_t half; + uint32_t res; + + /* get param */ + cmd_sscanf(cmd, "t=%16s s=%u", type_str, &size); + + /* check param */ + if (cmd_strcmp(type_str, "ibm") == 0) { + type = CE_CRC16_IBM; + } else if (cmd_strcmp(type_str, "maxim") == 0) { + type = CE_CRC16_MAXIM; + } else if (cmd_strcmp(type_str, "usb") == 0) { + type = CE_CRC16_USB; + } else if (cmd_strcmp(type_str, "modbus") == 0) { + type = CE_CRC16_MODBUS; + } else if (cmd_strcmp(type_str, "ccitt_1") == 0) { + type = CE_CRC16_CCITT_1; + } else if (cmd_strcmp(type_str, "ccitt") == 0) { + type = CE_CRC16_CCITT; + } else if (cmd_strcmp(type_str, "x25") == 0) { + type = CE_CRC16_X25; + } else if (cmd_strcmp(type_str, "xmodem") == 0) { + type = CE_CRC16_XMODEM; + } else if (cmd_strcmp(type_str, "dnp") == 0) { + type = CE_CRC16_DNP; + } else if (cmd_strcmp(type_str, "crc32") == 0) { + type = CE_CRC32; + } else if (cmd_strcmp(type_str, "mpeg2") == 0) { + type = CE_CRC32_MPEG2; + } else { + CMD_ERR("invalid type %s\n", type_str); + return CMD_STATUS_INVALID_ARG; + } + + half = size / 2; + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "%d", sizeof(res)); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, size, 30000); + + if (srv_cnt++ == 0) + HAL_CE_Init(); + + if (HAL_CRC_Init(&crc, type, size) != HAL_OK) { + CMD_ERR("crc init failed\n"); + return CMD_STATUS_FAIL; + } + if ((half) && (HAL_CRC_Append(&crc, buf, half) != HAL_OK)) { + CMD_ERR("crc append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_CRC_Append(&crc, buf + half, size - half) != HAL_OK) { + CMD_ERR("crc append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_CRC_Finish(&crc, &res) != HAL_OK) { + CMD_ERR("crc deinit failed\n"); + return CMD_STATUS_FAIL; + } + + if (--srv_cnt == 0) + HAL_CE_Deinit(); + + cmd_raw_mode_write((uint8_t *)&res, sizeof(res)); + cmd_raw_mode_disable(); + + cmd_free(buf); + return CMD_STATUS_ACKED; +} + + +static enum cmd_status cmd_crypto_md5_exec(char *cmd) +{ + char ivsrc_str[8]; + CE_Hash_IVsrc ivsrc; + uint32_t size; + + uint8_t *buf; + CE_MD5_Handler md5; + uint32_t half; + uint32_t res[4]; + + /* get param */ + cmd_sscanf(cmd, "i=%7s s=%u", ivsrc_str, &size); + + /* check param */ + if (cmd_strcmp(ivsrc_str, "fips180") == 0) { + ivsrc = CE_CTL_IVMODE_SHA_MD5_FIPS180; + } else if (cmd_strcmp(ivsrc_str, "input") == 0) { + ivsrc = CE_CTL_IVMODE_SHA_MD5_INPUT; + } else { + CMD_ERR("invalid ivsrc %s\n", ivsrc_str); + return CMD_STATUS_INVALID_ARG; + } + + half = size / 2; + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "%d", sizeof(res)); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, size, 30000); + + if (srv_cnt++ == 0) + HAL_CE_Init(); + + if (HAL_MD5_Init(&md5, ivsrc, md5_iv) != HAL_OK) { + CMD_ERR("md5 init failed\n"); + return CMD_STATUS_FAIL; + } + if ((half) && (HAL_MD5_Append(&md5, buf, half) != HAL_OK)) { + CMD_ERR("md5 append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_MD5_Append(&md5, buf + half, size - half) != HAL_OK) { + CMD_ERR("md5 append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_MD5_Finish(&md5, res) != HAL_OK) { + CMD_ERR("md5 deinit failed\n"); + return CMD_STATUS_FAIL; + } + + if (--srv_cnt == 0) + HAL_CE_Deinit(); + + cmd_raw_mode_write((uint8_t *)&res, sizeof(res)); + cmd_raw_mode_disable(); + + cmd_free(buf); + return CMD_STATUS_ACKED; + +} + + +static enum cmd_status cmd_crypto_sha1_exec(char *cmd) +{ + char ivsrc_str[8]; + CE_Hash_IVsrc ivsrc; + uint32_t size; + + uint8_t *buf; + CE_SHA1_Handler sha1; + uint32_t half; + uint32_t res[5]; + + /* get param */ + cmd_sscanf(cmd, "i=%7s s=%u", ivsrc_str, &size); + + /* check param */ + if (cmd_strcmp(ivsrc_str, "fips180") == 0) { + ivsrc = CE_CTL_IVMODE_SHA_MD5_FIPS180; + } else if (cmd_strcmp(ivsrc_str, "input") == 0) { + ivsrc = CE_CTL_IVMODE_SHA_MD5_INPUT; + } else { + CMD_ERR("invalid ivsrc %s\n", ivsrc_str); + return CMD_STATUS_INVALID_ARG; + } + + half = size / 2; + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "%d", sizeof(res)); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, size, 30000); + + if (srv_cnt++ == 0) + HAL_CE_Init(); + + if (HAL_SHA1_Init(&sha1, ivsrc, sha1_iv) != HAL_OK) { + CMD_ERR("sha1 init failed\n"); + return CMD_STATUS_FAIL; + } + if ((half) && (HAL_SHA1_Append(&sha1, buf, half) != HAL_OK)) { + CMD_ERR("sha1 append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_SHA1_Append(&sha1, buf + half, size - half) != HAL_OK) { + CMD_ERR("sha1 append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_SHA1_Finish(&sha1, res) != HAL_OK) { + CMD_ERR("sha1 deinit failed\n"); + return CMD_STATUS_FAIL; + } + + if (--srv_cnt == 0) + HAL_CE_Deinit(); + + cmd_raw_mode_write((uint8_t *)&res, sizeof(res)); + cmd_raw_mode_disable(); + + cmd_free(buf); + return CMD_STATUS_ACKED; + +} + +static enum cmd_status cmd_crypto_sha256_exec(char *cmd) +{ + char ivsrc_str[8]; + CE_Hash_IVsrc ivsrc; + uint32_t size; + + uint8_t *buf; + CE_SHA256_Handler sha256; + uint32_t half; + uint32_t res[8]; + + /* get param */ + cmd_sscanf(cmd, "i=%7s s=%u", ivsrc_str, &size); + + /* check param */ + if (cmd_strcmp(ivsrc_str, "fips180") == 0) { + ivsrc = CE_CTL_IVMODE_SHA_MD5_FIPS180; + } else if (cmd_strcmp(ivsrc_str, "input") == 0) { + ivsrc = CE_CTL_IVMODE_SHA_MD5_INPUT; + } else { + CMD_ERR("invalid ivsrc %s\n", ivsrc_str); + return CMD_STATUS_INVALID_ARG; + } + + half = size / 2; + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "%d", sizeof(res)); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, size, 30000); + + if (srv_cnt++ == 0) + HAL_CE_Init(); + + if (HAL_SHA256_Init(&sha256, ivsrc, sha256_iv) != HAL_OK) { + CMD_ERR("sha256 init failed\n"); + return CMD_STATUS_FAIL; + } + if ((half) && (HAL_SHA256_Append(&sha256, buf, half) != HAL_OK)) { + CMD_ERR("sha256 append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_SHA256_Append(&sha256, buf + half, size - half) != HAL_OK) { + CMD_ERR("sha256 append failed\n"); + return CMD_STATUS_FAIL; + } + if (HAL_SHA256_Finish(&sha256, res) != HAL_OK) { + CMD_ERR("sha256 deinit failed\n"); + return CMD_STATUS_FAIL; + } + + cmd_raw_mode_write((uint8_t *)&res, sizeof(res)); + cmd_raw_mode_disable(); + + if (--srv_cnt == 0) + HAL_CE_Deinit(); + + cmd_free(buf); + return CMD_STATUS_ACKED; + +} + + +static enum cmd_status cmd_crypto_prng_exec(char *cmd) +{ + uint8_t *res; + uint32_t size; + + /* get param */ + cmd_sscanf(cmd, "s=%u", &size); + + (void)size; //----------------------------the interface of prng should set size + + res = cmd_malloc(size); + if (res == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + if (srv_cnt++ == 0) + HAL_CE_Init(); + + if (HAL_PRNG_Generate(res, size) != HAL_OK) { + CMD_ERR("prng generate failed\n"); + return CMD_STATUS_FAIL; + } + + if (--srv_cnt == 0) + HAL_CE_Deinit(); + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + cmd_msleep(1000); + cmd_raw_mode_write((uint8_t *)res, size); + cmd_raw_mode_disable(); + + cmd_free(res); + + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_crypto_digiv_exec(char *cmd) +{ + char type[8]; + uint32_t size; + uint8_t *p; + + /* get param */ + cmd_sscanf(cmd, "t=%7s s=%u", type, &size); + + /* check param */ + if (cmd_strcmp(type, "md5") == 0) { + if (size > 4 * 4) { + CMD_ERR("invalid ivsize %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + p = (uint8_t *)&md5_iv; + cmd_memset(p, 0, 16); + } else if (cmd_strcmp(type, "sha1") == 0) { + if (size > 5 * 4) { + CMD_ERR("invalid ivsize %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + p = (uint8_t *)&sha1_iv; + cmd_memset(p, 0, 20); + } else if (cmd_strcmp(type, "sha256") == 0) { + if (size > 8 * 4) { + CMD_ERR("invalid ivsize %d\n", size); + return CMD_STATUS_INVALID_ARG; + } + p = (uint8_t *)&sha256_iv; + cmd_memset(p, 0, 32); + } else { + CMD_ERR("invalid type %s\n", type); + return CMD_STATUS_INVALID_ARG; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(p, size, 30000); + cmd_raw_mode_disable(); + + return CMD_STATUS_ACKED; +} + +static struct cmd_data g_crypto_cmds[] = { + { "addkey", cmd_crypto_addkey_exec }, + { "delkey", cmd_crypto_delkey_exec }, + { "keyiv", cmd_crypto_keyiv_exec }, + { "enc", cmd_crypto_enc_exec }, + { "dec", cmd_crypto_dec_exec }, + { "crc", cmd_crypto_crc_exec }, + { "md5", cmd_crypto_md5_exec }, + { "sha1", cmd_crypto_sha1_exec }, + { "sha256", cmd_crypto_sha256_exec }, + { "prng", cmd_crypto_prng_exec }, + { "digiv", cmd_crypto_digiv_exec }, +}; + +enum cmd_status cmd_crypto_exec(char *cmd) +{ + return cmd_exec(cmd, g_crypto_cmds, cmd_nitems(g_crypto_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ce.h b/platform/mcu/xr871/project/common/cmd/cmd_ce.h new file mode 100644 index 0000000000..2dfe7162ec --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ce.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_CE_H_ +#define _CMD_CE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_crypto_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_CE_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_cedarx.c b/platform/mcu/xr871/project/common/cmd/cmd_cedarx.c new file mode 100644 index 0000000000..4767211243 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_cedarx.c @@ -0,0 +1,532 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef __PRJ_CONFIG_XPLAYER + +#include "cmd_util.h" + +//#include +#include +#include +#include +#include "pthread.h" +//#include +//#include "errno.h" +//#include + +#include "iniparserapi.h" + +//#include "cdx_config.h" +#include +#include "xplayer.h" +#include "CdxTypes.h" +#include "fs/fatfs/ff.h" +//#include "memoryAdapter.h" +//#include "deinterlace.h" +//typedef unsigned long uintptr_t ; +extern SoundCtrl* SoundDeviceCreate(); + +static const int STATUS_STOPPED = 0; +static const int STATUS_PREPARING = 1; +static const int STATUS_PREPARED = 2; +static const int STATUS_PLAYING = 3; +static const int STATUS_PAUSED = 4; +static const int STATUS_SEEKING = 5; + +typedef struct DemoPlayerContext +{ + XPlayer* mAwPlayer; + int mPreStatus; + int mStatus; + int mSeekable; + int mError; + pthread_mutex_t mMutex; + sem_t mStoped; + sem_t mPrepared; +// int mVideoFrameNum; +}DemoPlayerContext; + + +//* define commands for user control. +typedef struct Command +{ + const char* strCommand; + int nCommandId; + const char* strHelpMsg; +}Command; + +#define COMMAND_HELP 0x1 //* show help message. +#define COMMAND_QUIT 0x2 //* quit this program. + +#define COMMAND_SET_SOURCE 0x101 //* set url of media file. +#define COMMAND_PLAY 0x102 //* start playback. +#define COMMAND_PAUSE 0x103 //* pause the playback. +#define COMMAND_STOP 0x104 //* stop the playback. +#define COMMAND_SEEKTO 0x105 //* seek to posion, in unit of second. +#define COMMAND_SHOW_MEDIAINFO 0x106 //* show media information. +#define COMMAND_SHOW_DURATION 0x107 //* show media duration, in unit of second. +#define COMMAND_SHOW_POSITION 0x108 //* show current play position, in unit of second. +#define COMMAND_SWITCH_AUDIO 0x109 //* switch autio track. +#define COMMAND_SETSPEED 0x10a + + +static void set_source(DemoPlayerContext *demoPlayer, char* pUrl) +{ + demoPlayer->mSeekable = 1; + + //* set url to the AwPlayer. + if(XPlayerSetDataSourceUrl(demoPlayer->mAwPlayer, + (const char*)pUrl, NULL, NULL) != 0) + { + printf("error:\n"); + printf(" AwPlayer::setDataSource() return fail.\n"); + return; + } + printf("setDataSource end\n"); + + if (!strncmp(pUrl, "http://", 7)) { + if(XPlayerPrepareAsync(demoPlayer->mAwPlayer) != 0) + { + printf("error:\n"); + printf(" AwPlayer::prepareAsync() return fail.\n"); + pthread_mutex_unlock(&demoPlayer->mMutex); + return; + } + sem_wait(&demoPlayer->mPrepared); + } + + //* start preparing. + pthread_mutex_lock(&demoPlayer->mMutex); + demoPlayer->mPreStatus = STATUS_STOPPED; + demoPlayer->mStatus = STATUS_PREPARING; + pthread_mutex_unlock(&demoPlayer->mMutex); + printf("preparing...\n"); +} + +static void play(DemoPlayerContext *demoPlayer) +{ + if(XPlayerStart(demoPlayer->mAwPlayer) != 0) + { + printf("error:\n"); + printf(" AwPlayer::start() return fail.\n"); + return; + } + demoPlayer->mPreStatus = demoPlayer->mStatus; + demoPlayer->mStatus = STATUS_PLAYING; + printf("playing.\n"); +} + +static void pause(DemoPlayerContext *demoPlayer) +{ + if(XPlayerPause(demoPlayer->mAwPlayer) != 0) + { + printf("error:\n"); + printf(" AwPlayer::pause() return fail.\n"); + return; + } + demoPlayer->mPreStatus = demoPlayer->mStatus; + demoPlayer->mStatus = STATUS_PAUSED; + printf("paused.\n"); +} + +static void stop(DemoPlayerContext *demoPlayer) +{ + if(XPlayerReset(demoPlayer->mAwPlayer) != 0) + { + printf("error:\n"); + printf(" AwPlayer::reset() return fail.\n"); + return; + } + demoPlayer->mPreStatus = demoPlayer->mStatus; + demoPlayer->mStatus = STATUS_STOPPED; + printf("stopped.\n"); +} + + +//* a callback for awplayer. +static int CallbackForAwPlayer(void* pUserData, int msg, int ext1, void* param) +{ + DemoPlayerContext* pDemoPlayer = (DemoPlayerContext*)pUserData; + + switch(msg) + { + case AWPLAYER_MEDIA_INFO: + { + switch(ext1) + { + case AW_MEDIA_INFO_NOT_SEEKABLE: + { + pDemoPlayer->mSeekable = 0; + printf("info: media source is unseekable.\n"); + break; + } + case AW_MEDIA_INFO_RENDERING_START: + { + printf("info: start to show pictures.\n"); + break; + } + } + break; + } + + case AWPLAYER_MEDIA_ERROR: + { + pthread_mutex_lock(&pDemoPlayer->mMutex); + pDemoPlayer->mStatus = STATUS_STOPPED; + pDemoPlayer->mPreStatus = STATUS_STOPPED; + pthread_mutex_unlock(&pDemoPlayer->mMutex); + printf("error: open media source fail.\n"); + sem_post(&pDemoPlayer->mPrepared); + sem_post(&pDemoPlayer->mStoped); + pDemoPlayer->mError = 1; + + loge(" error : how to deal with it"); + break; + } + + case AWPLAYER_MEDIA_PREPARED: + { + logd("info : preared"); + pDemoPlayer->mPreStatus = pDemoPlayer->mStatus; + pDemoPlayer->mStatus = STATUS_PREPARED; + sem_post(&pDemoPlayer->mPrepared); + printf("info: prepare ok.\n"); + break; + } + + case AWPLAYER_MEDIA_PLAYBACK_COMPLETE: + { + sem_post(&pDemoPlayer->mStoped);//* stop the player. + //* TODO + break; + } + + case AWPLAYER_MEDIA_SEEK_COMPLETE: + { + pthread_mutex_lock(&pDemoPlayer->mMutex); + pDemoPlayer->mStatus = pDemoPlayer->mPreStatus; + printf("info: seek ok.\n"); + pthread_mutex_unlock(&pDemoPlayer->mMutex); + break; + } + + default: + { + //printf("warning: unknown callback from AwPlayer.\n"); + break; + } + } + + return 0; +} + +static uint8_t cedarx_inited = 0; +static uint8_t xplayer_inited = 0; +void AwParserInit(void); +void AwStreamInit(void); + +static DemoPlayerContext *demoPlayer; +static FATFS fs; + +static enum cmd_status cmd_cedarx_create_exec(char *cmd) +{ + FRESULT res; + demoPlayer = malloc(sizeof(*demoPlayer)); + + if (cedarx_inited++ == 0) { + printf_lock_init(); + if ((res = f_mount(&fs, "0:/", 1)) != FR_OK) { + printf("can not mount\n"); + return -1; + } else { + printf("mount success\n"); + } + } + + if (!xplayer_inited) { + xplayer_inited = 1; + AwParserInit(); + AwStreamInit(); + } + + //* create a player. + memset(demoPlayer, 0, sizeof(DemoPlayerContext)); + pthread_mutex_init(&demoPlayer->mMutex, NULL); + sem_init(&demoPlayer->mStoped, 0, 0); + sem_init(&demoPlayer->mPrepared, 0, 0); + + demoPlayer->mAwPlayer = XPlayerCreate(); + if(demoPlayer->mAwPlayer == NULL) + { + printf("can not create AwPlayer, quit.\n"); + return -1; + } else { + printf("create AwPlayer success.\n"); + } + + //* set callback to player. + XPlayerSetNotifyCallback(demoPlayer->mAwPlayer, CallbackForAwPlayer, (void*)demoPlayer); + + //* check if the player work. + if(XPlayerInitCheck(demoPlayer->mAwPlayer) != 0) + { + printf("initCheck of the player fail, quit.\n"); + XPlayerDestroy(demoPlayer->mAwPlayer); + demoPlayer->mAwPlayer = NULL; + return -1; + } else + printf("AwPlayer check success.\n"); + + SoundCtrl* sound = SoundDeviceCreate(); + + XPlayerSetAudioSink(demoPlayer->mAwPlayer, (void*)sound); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_destroy_exec(char *cmd) +{ + FRESULT res; + + printf("destroy AwPlayer.\n"); + + if(demoPlayer->mAwPlayer != NULL) + { + XPlayerDestroy(demoPlayer->mAwPlayer); + demoPlayer->mAwPlayer = NULL; + } + + printf("destroy AwPlayer 1.\n"); + pthread_mutex_destroy(&demoPlayer->mMutex); + + sem_destroy(&demoPlayer->mPrepared); + sem_destroy(&demoPlayer->mStoped); + + if (--cedarx_inited == 0) { + if ((res = f_mount(NULL, "", 1)) != FR_OK) + printf("failed to unmount\n"); + printf_lock_deinit(); + } + + free(demoPlayer); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_play_exec(char *cmd) +{ + play(demoPlayer); + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_stop_exec(char *cmd) +{ + stop(demoPlayer); + msleep(5); + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_pause_exec(char *cmd) +{ + pause(demoPlayer); + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_seturl_exec(char *cmd) +{ + set_source(demoPlayer, cmd); + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_getpos_exec(char *cmd) +{ + int msec; + XPlayerGetCurrentPosition(demoPlayer->mAwPlayer, &msec); + cmd_write_respond(CMD_STATUS_OK, "played time: %d ms", msec); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_cedarx_seek_exec(char *cmd) +{ + int nSeekTimeMs = atoi(cmd); + + XPlayerSeekTo(demoPlayer->mAwPlayer, nSeekTimeMs); + return CMD_STATUS_OK; +} + +#include "driver/chip/hal_codec.h" +#include "audio/manager/audio_manager.h" + +static enum cmd_status cmd_cedarx_setvol_exec(char *cmd) +{ + int vol = atoi(cmd); + if (vol > 31) + vol = 31; + + aud_mgr_handler(AUDIO_DEVICE_MANAGER_VOLUME, vol); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_playdic_exec(char *cmd) +{ + return CMD_STATUS_OK; +} + + +#include +#include +#include +#include "awencoder.h" +#include "RecoderWriter.h" +#include "xrecord.h" +#include "CaptureControl.h" + + +static uint8_t xrecord_inited = 0; +static XRecord *xrecord; + +static enum cmd_status cmd_cedarx_rec_exec(char *cmd) +{ + FRESULT res; + + XRECODER_AUDIO_ENCODE_TYPE type; + if (strstr(cmd, ".amr")) + type = XRECODER_AUDIO_ENCODE_AMR_TYPE; + else if (strstr(cmd, ".pcm")) + type = XRECODER_AUDIO_ENCODE_PCM_TYPE; + else { + printf("do not support this encode type\n"); + return CMD_STATUS_INVALID_ARG; + } + + if (cedarx_inited++ == 0) { + printf_lock_init(); + + if ((res = f_mount(&fs, "0:/", 1)) != FR_OK) { + printf("can not mount\n"); + return -1; + } + } + + + void AwMuxerInit(); + if (xrecord_inited == 0) { + AwMuxerInit(); + xrecord_inited = 1; + } + + xrecord = XRecordCreate(); + if (xrecord == NULL) + printf("create success\n"); + + CaptureCtrl* cap = CaptureDeviceCreate(); + if (!cap) + printf("cap device create failed\n"); + XRecordSetAudioCap(xrecord, cap); + AudioEncodeConfig audioConfig; + + audioConfig.nType = AUDIO_ENCODE_AMR_TYPE; + audioConfig.nInChan = 1; + audioConfig.nInSamplerate = 8000; + audioConfig.nOutChan = 1; + audioConfig.nOutSamplerate = 8000; + audioConfig.nSamplerBits = 16; + audioConfig.nBitrate = 12200; + audioConfig.nFrameStyle = 0; + + + XRecordSetDataDstUrl(xrecord, cmd, NULL, NULL); + XRecordSetAudioEncodeType(xrecord, type, &audioConfig); + + XRecordPrepare(xrecord); + XRecordStart(xrecord); + printf("record start\n"); + + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_cedarx_end_exec(char *cmd) +{ + FRESULT res; + + XRecordStop(xrecord); + printf("record stop\n"); + XRecordDestroy(xrecord); + printf("record destroy\n"); + + if (--cedarx_inited == 0) { + printf_lock_deinit(); + + if ((res = f_mount(NULL, "", 1)) != FR_OK) + printf("failed to unmount\n"); + } + + return CMD_STATUS_OK; +} + + +/* + * brief cedarx Test Command + * command cedarx create + * cedarx destroy + * cedarx play + * cedarx stop + * cedarx pause + * cedarx seturl file://music/01.mp3 + * cedarx getpos + * cedarx seek 6000 + * cedarx setvol 8 + * cedarx playdic file://music + * cedarx rec file://record/wechat.amr + * cedarx end + */ +static struct cmd_data g_cedarx_cmds[] = { + { "create", cmd_cedarx_create_exec }, + { "destroy", cmd_cedarx_destroy_exec }, + { "play", cmd_cedarx_play_exec }, + { "stop", cmd_cedarx_stop_exec }, + { "pause", cmd_cedarx_pause_exec }, + { "seturl", cmd_cedarx_seturl_exec }, + { "getpos", cmd_cedarx_getpos_exec }, + { "seek", cmd_cedarx_seek_exec }, + { "setvol", cmd_cedarx_setvol_exec }, + { "playdic", cmd_cedarx_playdic_exec }, + + { "rec", cmd_cedarx_rec_exec }, + { "end", cmd_cedarx_end_exec }, +}; + +enum cmd_status cmd_cedarx_exec(char *cmd) +{ + return cmd_exec(cmd, g_cedarx_cmds, cmd_nitems(g_cedarx_cmds)); +} + +#endif /* __PRJ_CONFIG_XPLAYER */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_cedarx.h b/platform/mcu/xr871/project/common/cmd/cmd_cedarx.h new file mode 100644 index 0000000000..85b997ee85 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_cedarx.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_CEDARX_H_ +#define _CMD_CEDARX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __PRJ_CONFIG_XPLAYER +enum cmd_status cmd_cedarx_exec(char *cmd); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_CEDARX_H_ */ + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_clock.c b/platform/mcu/xr871/project/common/cmd/cmd_clock.c new file mode 100644 index 0000000000..b84c21f7d2 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_clock.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "driver/chip/hal_clock.h" + +enum CMD_CLOCK_TYPE { + CMD_CLOCK_TYPE_HF = 0, + CMD_CLOCK_TYPE_LF, + CMD_CLOCK_TYPE_CPU, + CMD_CLOCK_TYPE_DEV, + CMD_CLOCK_TYPE_AHB1, + CMD_CLOCK_TYPE_AHB2, + CMD_CLOCK_TYPE_APB, + CMD_CLOCK_TYPE_NUM +}; + +/* index by enum CMD_CLOCK_TYPE */ +static const char *cmd_clock_type_str[CMD_CLOCK_TYPE_NUM] = { + "LF", "HF", "CPU", "DEV", "AHB1", "AHB2", "APB" +}; + +static uint32_t cmd_clock_get(enum CMD_CLOCK_TYPE type) +{ + uint32_t clock; + + switch (type) { + case CMD_CLOCK_TYPE_HF: + clock = HAL_GetLFClock(); + break; + case CMD_CLOCK_TYPE_LF: + clock = HAL_GetHFClock(); + break; + case CMD_CLOCK_TYPE_CPU: + clock = HAL_GetCPUClock(); + break; + case CMD_CLOCK_TYPE_DEV: + clock = HAL_GetDevClock(); + break; + case CMD_CLOCK_TYPE_AHB1: + clock = HAL_GetAHB1Clock(); + break; + case CMD_CLOCK_TYPE_AHB2: + clock = HAL_GetAHB2Clock(); + break; + case CMD_CLOCK_TYPE_APB: + clock = HAL_CCM_BusGetAPBClock(); + break; + default: + clock = 0; + break; + } + return clock; +} + +/* + * drv clock + */ +enum cmd_status cmd_clock_exec(char *cmd) +{ + int type; + uint32_t clock = 0; + + for (type = 0; type < CMD_CLOCK_TYPE_NUM; ++type) { + if (cmd_strcmp(cmd, cmd_clock_type_str[type]) == 0) { + clock = cmd_clock_get((enum CMD_CLOCK_TYPE)type); + break; + } + } + + if (clock != 0) { + cmd_write_respond(CMD_STATUS_OK, "%d Hz (%s clock)", clock, cmd); + return CMD_STATUS_ACKED; + } + + return CMD_STATUS_INVALID_ARG; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_clock.h b/platform/mcu/xr871/project/common/cmd/cmd_clock.h new file mode 100644 index 0000000000..31c56bf045 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_clock.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_CLOCK_H_ +#define _CMD_CLOCK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_clock_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_CLOCK_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_debug.h b/platform/mcu/xr871/project/common/cmd/cmd_debug.h new file mode 100644 index 0000000000..0df08daffb --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_debug.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_DEBUG_H_ +#define _CMD_DEBUG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CMD_DBG_ON 1 +#define CMD_WRN_ON 1 +#define CMD_ERR_ON 1 + +#define CMD_SYSLOG printf + +#define CMD_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + CMD_SYSLOG(fmt, ##arg); \ + } while (0) + +#define CMD_DBG(fmt, arg...) \ + CMD_LOG(CMD_DBG_ON, "[cmd] "fmt, ##arg) + +#define CMD_WRN(fmt, arg...) \ + CMD_LOG(CMD_WRN_ON, "[cmd WRN] "fmt, ##arg) + +#define CMD_ERR(fmt, arg...) \ + CMD_LOG(CMD_ERR_ON, "[cmd ERR] %s():%d, "fmt, __func__, __LINE__, ##arg) + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_defs.h b/platform/mcu/xr871/project/common/cmd/cmd_defs.h new file mode 100644 index 0000000000..e99ce7c5c4 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_defs.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_DEFS_H_ +#define _CMD_DEFS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_code_type { + CMD_CODE_TYEP_STATUS = 0, + CMD_CODE_TYEP_EVENT, +}; + +enum cmd_status { + CMD_STATUS_ACKED = 100, /* already acked, no need to send respond */ + + /* success status */ + CMD_STATUS_SUCCESS_MIN = 200, + CMD_STATUS_OK = 200, /* command exec success */ + CMD_STATUS_SUCCESS_MAX = 200, + + /* error status */ + CMD_STATUS_ERROR_MIN = 400, + CMD_STATUS_UNKNOWN_CMD = 400, /* unknown command */ + CMD_STATUS_INVALID_ARG = 401, /* invalid argument */ + CMD_STATUS_FAIL = 402, /* command exec failed */ + CMD_STATUS_ERROR_MAX = 402, +}; + +enum cmd_event { + CMD_EVENT_MIN = 600, + CMD_EVENT_TEST_FINISH = 600, + CMD_EVENT_TIMER_NOTIFY = 601, + CMD_EVENT_RTC_NOTIFY = 602, + CMD_EVENT_MQTT_MSG_RECV = 603, + CMD_EVENT_WDG_TIMEOUT = 604, + CMD_EVENT_MAX = 604, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_DEFS_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_dhcpd.c b/platform/mcu/xr871/project/common/cmd/cmd_dhcpd.c new file mode 100644 index 0000000000..78e894e443 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_dhcpd.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_dhcpd.h" +#include "net/udhcp/usr_dhcpd.h" +#include "net/lwip/ipv4/lwip/inet.h" + +#define CMD_DHCPD_ADDR_START "192.168.51.150" +#define CMD_DHCPD_ADDR_END "192.168.51.155" + +static struct dhcp_server_info dhcpd_info; + +enum cmd_status dhcpd_start_exec(char *cmd) +{ + if (dhcpd_info.addr_start == 0) + dhcpd_info.addr_start = inet_addr(CMD_DHCPD_ADDR_START); + if (dhcpd_info.addr_end == 0) + dhcpd_info.addr_end = inet_addr(CMD_DHCPD_ADDR_END); + if (dhcpd_info.lease_time == 0) + dhcpd_info.lease_time = 60*60*12; + + dhcp_server_start(&dhcpd_info); + return CMD_STATUS_OK; +} + +enum cmd_status dhcpd_stop_exec(char *cmd) +{ + dhcp_server_stop(); + return CMD_STATUS_OK; +} + +enum cmd_status dhcpd_set_ippool_exec(char *cmd) +{ + int argc; + char *argv[2]; + ip_addr_t ip_addr_start; + ip_addr_t ip_addr_end; + + argc = cmd_parse_argv(cmd, argv, cmd_nitems(argv)); + if (argc < 2) { + CMD_ERR("invalid dhcp cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + if (inet_aton(argv[0], &ip_addr_start) ==0 || + inet_aton(argv[1], &ip_addr_end) == 0) { + CMD_ERR("invalid dhcp cmd <%s %s>\n", argv[0], argv[1]); + return CMD_STATUS_INVALID_ARG; + } + + dhcpd_info.addr_start = ip_addr_start.addr; + dhcpd_info.addr_end = ip_addr_end.addr; + + return CMD_STATUS_OK; +} + +enum cmd_status dhcpd_set_max_leases_exec(char *cmd) +{ + int argc; + char *argv[1]; + int leases; + + argc = cmd_parse_argv(cmd, argv, cmd_nitems(argv)); + if (argc < 1) { + CMD_ERR("invalid dhcp cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + + leases = cmd_atoi(argv[0]); + if (leases > 254) { + CMD_ERR("invalid dhcp cmd, leases=%s", argv[0]); + return CMD_STATUS_INVALID_ARG; + } + + dhcpd_info.max_leases = leases; + return CMD_STATUS_OK; +} + +enum cmd_status dhcpd_set_lease_time_exec(char *cmd) +{ + int argc; + char *argv[1]; + int lease_time; + + argc = cmd_parse_argv(cmd, argv, cmd_nitems(argv)); + if (argc < 1) { + CMD_ERR("invalid dhcp cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + if ((lease_time = cmd_atoi(argv[0])) < 0) { + CMD_ERR("invalid dhcp cmd, leasetime=%d", lease_time); + return CMD_STATUS_INVALID_ARG; + } + + dhcpd_info.lease_time = lease_time; + return CMD_STATUS_OK; +} + +/* + * dhcp commands + */ +static struct cmd_data g_dhcpd_cmds[] = { + { "start", dhcpd_start_exec }, + { "stop", dhcpd_stop_exec }, + { "ippool", dhcpd_set_ippool_exec }, + { "leases", dhcpd_set_max_leases_exec }, + { "leasetime", dhcpd_set_lease_time_exec }, +}; + +enum cmd_status cmd_dhcpd_exec(char *cmd) +{ + return cmd_exec(cmd, g_dhcpd_cmds, cmd_nitems(g_dhcpd_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_dhcpd.h b/platform/mcu/xr871/project/common/cmd/cmd_dhcpd.h new file mode 100644 index 0000000000..b6c1c2208c --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_dhcpd.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_DHCPD_H_ +#define _CMD_DHCPD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_dhcpd_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_DHCPD_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_echo.c b/platform/mcu/xr871/project/common/cmd/cmd_echo.c new file mode 100644 index 0000000000..cd1f8f074f --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_echo.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +enum cmd_status cmd_echo_exec(char *cmd) +{ + cmd_write_respond(CMD_STATUS_OK, "%s", cmd); + return CMD_STATUS_ACKED; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_echo.h b/platform/mcu/xr871/project/common/cmd/cmd_echo.h new file mode 100644 index 0000000000..eaa28688d0 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_echo.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_ECHO_H_ +#define _CMD_ECHO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_echo_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_ECHO_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_efpg.c b/platform/mcu/xr871/project/common/cmd/cmd_efpg.c new file mode 100644 index 0000000000..c571bfd271 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_efpg.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "sys/xr_debug.h" +#include "cmd_debug.h" +#include "cmd_util.h" +#include "efpg/efpg.h" +#include "console/console.h" + +/* + * efpg + * + * efpg get hosc + * efpg get boot + * efpg get dcxo + * efpg get pout + * efpg get mac + * efpg get chipid + */ + +static enum cmd_status cmd_efpg_start(void) +{ + const char *efpg_key = "efpgtest"; + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + UART_ID uart_id = console_get_uart_id(); + if (uart_id == UART_NUM) { + CMD_ERR("get uart id failed\n"); + return CMD_STATUS_ACKED; + } + + if (efpg_start((uint8_t *)efpg_key, strlen(efpg_key), uart_id, console_disable, console_enable) < 0) { + CMD_ERR("efpg program failed\n"); + return CMD_STATUS_ACKED; + } + + return CMD_STATUS_ACKED; +} + +static void cmd_efpg_log(uint8_t *buf, uint8_t size) +{ + int i; + + CMD_SYSLOG("\n"); + for (i = 0; i < size; i++) + CMD_SYSLOG("[%02d] 0x%02x\n", i, buf[i]); + CMD_SYSLOG("\n"); +} + +static enum cmd_status cmd_efpg_get_exec(char *cmd) +{ + uint8_t buf[32] = {0}; + efpg_field_t field; + + if (cmd_strcmp(cmd, "hosc") == 0) { + field = EFPG_FIELD_HOSC; + } else if (cmd_strcmp(cmd, "boot") == 0) { + field = EFPG_FIELD_BOOT; + } else if (cmd_strcmp(cmd, "dcxo") == 0) { + field = EFPG_FIELD_DCXO; + } else if (cmd_strcmp(cmd, "pout") == 0) { + field = EFPG_FIELD_POUT; + } else if (cmd_strcmp(cmd, "mac") == 0) { + field = EFPG_FIELD_MAC; + } else if (cmd_strcmp(cmd, "chipid") == 0) { + field = EFPG_FIELD_CHIPID; + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + if (efpg_read(field, buf) != 0) { + CMD_ERR("efpg read failed, field %d\n", field); + return CMD_STATUS_FAIL; + } + + if (field == EFPG_FIELD_HOSC) { + cmd_efpg_log(buf, 1); + } else if (field == EFPG_FIELD_BOOT) { + cmd_efpg_log(buf, 32); + } else if (field == EFPG_FIELD_DCXO) { + cmd_efpg_log(buf, 1); + } else if (field == EFPG_FIELD_POUT) { + cmd_efpg_log(buf, 3); + } else if (field == EFPG_FIELD_MAC) { + cmd_efpg_log(buf, 6); + } else if (field == EFPG_FIELD_CHIPID) { + cmd_efpg_log(buf, 16); + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_efpg_read_ua_exec(char *cmd) +{ + uint8_t* buf; + int32_t cnt; + uint32_t start_addr, len_bit, len_byte; + + cnt = cmd_sscanf(cmd, "a=%u l=%u", &start_addr, &len_bit); + if (cnt != 2) { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + len_byte = len_bit / 8; + if (len_bit % 8) + len_byte ++; + buf = cmd_malloc(len_byte); + if (efpg_read_ua(start_addr, len_bit, buf)) { + CMD_ERR("efpg read user area failed\n"); + return CMD_STATUS_FAIL; + } + CMD_DBG("data:\n"); + print_hex_dump_bytes(buf, len_byte); + cmd_free(buf); + + return CMD_STATUS_OK; +} + + +static struct cmd_data g_efpg_cmds[] = { + { "get", cmd_efpg_get_exec}, + { "read_user_area", cmd_efpg_read_ua_exec}, +}; + +enum cmd_status cmd_efpg_exec(char *cmd) +{ + if (cmd[0] == '\0') + return cmd_efpg_start(); + + return cmd_exec(cmd, g_efpg_cmds, cmd_nitems(g_efpg_cmds)); +} + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_efpg.h b/platform/mcu/xr871/project/common/cmd/cmd_efpg.h new file mode 100644 index 0000000000..8031b36200 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_efpg.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_EFPG_H_ +#define _CMD_EFPG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_efpg_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_EFPG_H_ */ \ No newline at end of file diff --git a/platform/mcu/xr871/project/common/cmd/cmd_etf.c b/platform/mcu/xr871/project/common/cmd/cmd_etf.c new file mode 100644 index 0000000000..12c2c27781 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_etf.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +#include "sys/ota.h" + +enum cmd_status cmd_etf_exec(char *cmd) +{ + ota_cfg_t ota_cfg; + + cmd_write_respond(CMD_STATUS_OK, "%s", cmd); + + ota_cfg.image = OTA_IMAGE_2ND; + ota_cfg.state = OTA_STATE_VERIFIED; + ota_write_cfg(&ota_cfg); + ota_reboot(); + + return CMD_STATUS_ACKED; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_etf.h b/platform/mcu/xr871/project/common/cmd/cmd_etf.h new file mode 100644 index 0000000000..afd85fffd8 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_etf.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_ETF_H_ +#define _CMD_ETF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_etf_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_ETF_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_flash.c b/platform/mcu/xr871/project/common/cmd/cmd_flash.c new file mode 100644 index 0000000000..03945841d5 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_flash.c @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_debug.h" +#include "cmd_util.h" +#include "cmd_flash.h" +#include "driver/chip/hal_flash.h" + +#define MFLASH 0 + +static enum cmd_status cmd_flash_start_exec(char *cmd) +{ + if (HAL_Flash_Open(MFLASH, 5000) != HAL_OK) + { + CMD_ERR("flash driver open failed\n"); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_flash_stop_exec(char *cmd) +{ + /* deinie driver */ + if (HAL_Flash_Close(0) != HAL_OK) { + CMD_ERR("flash driver close failed\n"); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +#define FLASH_TEST_BUF_SIZE (0x100) + +static enum cmd_status cmd_flash_erase_exec(char *cmd) +{ + int32_t cnt; + char size_str[8]; + uint32_t addr; + FlashEraseMode size_type; + int32_t size; + uint8_t buf[FLASH_TEST_BUF_SIZE]; + + /* get param */ + cnt = cmd_sscanf(cmd, "s=%7s a=0x%x", size_str, &addr); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(size_str, "chip") == 0) { + size_type = FLASH_ERASE_CHIP; + size = 0; + } else if (cmd_strcmp(size_str, "64kb") == 0) { + size = 0x10000; + size_type = FLASH_ERASE_64KB; + } else if (cmd_strcmp(size_str, "32kb") == 0) { + size_type = FLASH_ERASE_32KB; + size = 0x8000; + } else if (cmd_strcmp(size_str, "4kb") == 0) { + size = 0x1000; + size_type = FLASH_ERASE_4KB; + } else { + CMD_ERR("invalid size %s\n", size_str); + return CMD_STATUS_INVALID_ARG; + } + + /* erase */ + HAL_Flash_MemoryOf(MFLASH, size_type, addr, &addr); + if (HAL_Flash_Erase(MFLASH, size_type, addr, 1) != HAL_OK) { + CMD_ERR("flash erase failed\n"); + return CMD_STATUS_FAIL; + } + + while (size > 0) { + int32_t tmp_size = (size < FLASH_TEST_BUF_SIZE) ? size : FLASH_TEST_BUF_SIZE; + +// CMD_DBG("tmp_size: %d\n", tmp_size); + + if (HAL_Flash_Read(MFLASH, addr, buf, tmp_size) != HAL_OK) { + CMD_ERR("flash read failed\n"); + return CMD_STATUS_FAIL; + } + + size -= tmp_size; + addr += tmp_size; + + while (--tmp_size >= 0) { + if ((uint8_t)(~(buf[tmp_size])) != 0) { + CMD_ERR("flash write failed: read data from flash != 0xFF, ~data = 0x%x, tmp_size = %d\n", (uint8_t)(~(buf[tmp_size])), tmp_size); + return CMD_STATUS_FAIL; + } + } + + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_flash_write_exec(char *cmd) +{ + uint32_t cnt; + uint32_t addr; + int32_t size; + uint8_t *wbuf; + uint8_t *rbuf; + + /* get param */ + cnt = cmd_sscanf(cmd, "a=0x%x s=%d", &addr, &size); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + wbuf = cmd_malloc(size); + if (wbuf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + rbuf = cmd_malloc(size); + if (rbuf == NULL) { + CMD_ERR("no memory\n"); + cmd_free(wbuf); + return CMD_STATUS_FAIL; + } + + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(wbuf, size, 30000); + + + /* write */ + if (HAL_Flash_Write(MFLASH, addr, wbuf, size) != HAL_OK) { + CMD_ERR("flash write failed\n"); + } + + if (HAL_Flash_Read(MFLASH, addr, rbuf, size) != HAL_OK) { + CMD_ERR("flash read failed\n"); + } + + cmd_raw_mode_write(rbuf, size); + cmd_raw_mode_disable(); + + cmd_free(wbuf); + cmd_free(rbuf); + + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_flash_read_exec(char *cmd) +{ + int32_t cnt; + uint8_t *buf; + uint32_t addr; + uint32_t size; + + /* get param */ + cnt = cmd_sscanf(cmd, "a=0x%x s=%u", &addr, &size); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + + /* read */ + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + cmd_free(buf); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + if (HAL_Flash_Read(MFLASH, addr, buf, size) != HAL_OK) { + CMD_ERR("spi driver read failed\n"); + } + + cmd_raw_mode_enable(); + cmd_msleep(1000); + cmd_raw_mode_write(buf, size); + cmd_raw_mode_disable(); + + cmd_free(buf); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_flash_overwrite_exec(char *cmd) +{ + uint32_t cnt; + uint32_t addr; + int32_t size; + uint8_t *wbuf; + int ret; + + /* get param */ + cnt = cmd_sscanf(cmd, "a=0x%x s=%d", &addr, &size); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + wbuf = cmd_malloc(size); + if (wbuf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + cmd_raw_mode_read(wbuf, size, 30000); + + /* write */ + if ((ret = HAL_Flash_Overwrite(MFLASH, addr, wbuf, size)) != HAL_OK) { + CMD_ERR("flash write failed: %d\n", ret); + } + + if ((ret = HAL_Flash_Check(MFLASH, addr, wbuf, size)) != 0) { + CMD_ERR("flash write not success %d\n", ret); + } + + cmd_raw_mode_write(wbuf, size); + cmd_raw_mode_disable(); + + cmd_free(wbuf); + + return CMD_STATUS_ACKED; +} + +/* + * brief Flash Auto Test Command + * command start {spiNum} {csNum} {freq} {mode} + * stop + * config {ioMode}// -----need to be supported by Flash chip + * erase {size} {addr} + * write {addr} "{str}" + * read {str/hex} {addr} {size} // recommanded that size should not too large + */ +static struct cmd_data g_flash_cmds[] = { + { "start", cmd_flash_start_exec }, + { "stop", cmd_flash_stop_exec }, + { "erase", cmd_flash_erase_exec }, + { "write", cmd_flash_write_exec }, + { "read", cmd_flash_read_exec }, + { "overwrite", cmd_flash_overwrite_exec }, +}; + +enum cmd_status cmd_flash_exec(char *cmd) +{ + return cmd_exec(cmd, g_flash_cmds, cmd_nitems(g_flash_cmds)); +} + + + + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_flash.h b/platform/mcu/xr871/project/common/cmd/cmd_flash.h new file mode 100644 index 0000000000..c0b79e939d --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_flash.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_FLASH_H_ +#define _CMD_FLASH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_flash_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_FLASH_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_fs.c b/platform/mcu/xr871/project/common/cmd/cmd_fs.c new file mode 100644 index 0000000000..13e3fd81b2 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_fs.c @@ -0,0 +1,461 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +#include "fs/fatfs/ff.h" + +#define FS_TEST_LFN 1 + +#if FS_TEST_LFN +#define FS_TEST_LFN_STR "longlongLongLongName" +#else +#define FS_TEST_LFN_STR "" +#endif + +#define FS_TEST_DATA_BUF_SIZE 1024 +#define FS_TEST_PATH_MAX_SIZE 256 + +#define CMD_FS_VOL_NAME "" + +static FATFS cmd_fs; + +int fs_test_create_file(const char *file_path, int file_size, uint8_t *buf, int buf_size) +{ + int len; + uint32_t byte_w, left = file_size; + FRESULT res; + uint32_t start_tm; + + FIL *fp = cmd_malloc(sizeof(FIL)); + cmd_memset(fp, 0, sizeof(FIL)); + + start_tm = OS_GetTicks(); + res = f_open(fp, file_path, FA_WRITE | FA_CREATE_ALWAYS); + if (res != FR_OK) { + CMD_ERR("create file %s failed, return %d\n", file_path, res); + cmd_free(fp); + return -1; + } + + while (left > 0) { + len = left > buf_size ? buf_size : left; + res = f_write(fp, buf, len, &byte_w); + if (res != FR_OK || len != byte_w) { + CMD_ERR("write file failed, len %d, left %d, return %d, written %u\n", + len, left, res, byte_w); + break; + } + left -= byte_w; + } + + f_close(fp); + cmd_free(fp); + + CMD_DBG("create file %s %s, size %d B (%d KB, %d MB), cost %u ms\n", + file_path, (left > 0) ? "failed" : "success", + file_size, file_size / 1024, file_size / 1024 / 1024, + OS_GetTicks() - start_tm); + return (left > 0 ? -1 : 0); +} + +int fs_test_create_dir(const char *dir_path, int file_num, int file_size_unit) +{ + int i; + char *path; + uint8_t *buf; + FRESULT res; + + res = f_mkdir(dir_path); + if (res != FR_OK) { + CMD_ERR("create dir %s failed, return %d\n", dir_path, res); + return -1; + } else { + CMD_DBG("create dir %s success\n", dir_path); + } + + path = cmd_malloc(FS_TEST_PATH_MAX_SIZE); + buf = cmd_malloc(FS_TEST_DATA_BUF_SIZE); + for (i = 0; i < FS_TEST_DATA_BUF_SIZE; ++i) { + buf[i] = '0' + (i % 10); + } + + for (i = 0; i < file_num; ++i) { + cmd_snprintf(path, FS_TEST_PATH_MAX_SIZE, "%s/file-%s-%02d.dat", dir_path, FS_TEST_LFN_STR, i); + if (fs_test_create_file(path, i * file_size_unit, buf, FS_TEST_DATA_BUF_SIZE) < 0) { + break; + } + } + + cmd_free(buf); + cmd_free(path); + return (i < file_num ? -1 : 0); +} + +int fs_test_rm_dir(const char *dir_path, int do_rm_dir) +{ + int ret = -1; + FRESULT res; + DIR *dp = NULL; + FILINFO *entry = NULL; + char *path = NULL; + + path = cmd_malloc(FS_TEST_PATH_MAX_SIZE); + + dp = cmd_malloc(sizeof(DIR)); + cmd_memset(dp, 0, sizeof(DIR)); + + entry = cmd_malloc(sizeof(FILINFO)); + cmd_memset(entry, 0, sizeof(FILINFO)); + + res = f_opendir(dp, dir_path); + if (res != FR_OK) { + CMD_ERR("open dir %s failed, return %d\n", dir_path, res); + goto out; + } + + while (1) { + res = f_readdir(dp, entry); + if (res != FR_OK) { + CMD_ERR("read dir %s failed, return %d\n", dir_path, res); + break; + } + + if (entry->fname[0] == 0) { + CMD_DBG("delete dir %s files finish\n", dir_path); + ret = 0; + break; + } + + cmd_snprintf(path, FS_TEST_PATH_MAX_SIZE, "%s/%s", dir_path, entry->fname); + if (entry->fattrib & AM_DIR) { + if (fs_test_rm_dir(path, 1) < 0) { + break; + } + } else { + res = f_unlink(path); + CMD_DBG("delete file %s %s\n", path, + (res != FR_OK) ? "failed" : "success"); + if (res != FR_OK) { + break; + } + } + } + + f_closedir(dp); + if (ret == 0 && do_rm_dir) { + res = f_unlink(dir_path); + if (res != FR_OK) { + CMD_ERR("delete dir %s failed, return %d\n", dir_path, res); + ret = -1; + } else { + CMD_DBG("delete dir %s success\n", dir_path); + } + } + +out: + if (entry) + cmd_free(entry); + + if (dp) + cmd_free(dp); + + if (path) + cmd_free(path); + + return ret; +} + +int fs_test_cp_file(const char *file_dst, const char *file_src, uint8_t *buf, int len) +{ + int ret = -1; + uint32_t byte_r, byte_w; + FRESULT res; + uint32_t start_tm; + + start_tm = OS_GetTicks(); + + FIL *fp_r = cmd_malloc(sizeof(FIL)); + cmd_memset(fp_r, 0, sizeof(FIL)); + + FIL *fp_w = cmd_malloc(sizeof(FIL)); + cmd_memset(fp_w, 0, sizeof(FIL)); + + res = f_open(fp_r, file_src, FA_READ | FA_OPEN_EXISTING ); + if (res != FR_OK) { + CMD_ERR("open read file %s failed, return %d\n", file_src, res); + goto out; + } + + res = f_open(fp_w, file_dst, FA_WRITE | FA_CREATE_ALWAYS); + if (res != FR_OK) { + CMD_ERR("open write file %s failed, return %d\n", file_dst, res); + f_close(fp_r); + goto out; + } + + while (1) { + res = f_read(fp_r, buf, len, &byte_r); + if (res != FR_OK) { + CMD_ERR("read file %s failed\n", file_src); + break; + } + + if (byte_r == 0) { + ret = 0; + break; + } + + res = f_write(fp_w, buf, byte_r, &byte_w); + if (res != FR_OK || byte_r != byte_w) { + CMD_ERR("write file %s failed, len %d, return %d, written %u\n", + file_dst, byte_r, res, byte_w); + break; + } + + if (byte_r < len) { + ret = 0; + break; + } + } + + CMD_DBG("copy %s to %s %s, cost %u ms\n", file_src, file_dst, + (ret == 0) ? "success" : "failed", OS_GetTicks() - start_tm); + f_close(fp_w); + f_close(fp_r); + +out: + if (fp_w) + cmd_free(fp_w); + + if (fp_r) + cmd_free(fp_r); + + return ret; +} + +int fs_test_cp_dir( const char *dir_dst, const char *dir_src) +{ + int ret = -1; + FRESULT res; + DIR *dp = NULL; + FILINFO *entry = NULL; + char *path_src = NULL; + char *path_dst = NULL; + uint8_t *buf = NULL; + + res = f_mkdir(dir_dst); + if (res != FR_OK) { + CMD_ERR("create dir %s failed, return %d\n", dir_dst, res); + return -1; + } else { + CMD_DBG("create dir %s success\n", dir_dst); + } + + dp = cmd_malloc(sizeof(DIR)); + cmd_memset(dp, 0, sizeof(DIR)); + + entry = cmd_malloc(sizeof(FILINFO)); + cmd_memset(entry, 0, sizeof(FILINFO)); + + res = f_opendir(dp, dir_src); + if (res != FR_OK) { + CMD_ERR("open dir %s failed, return %d\n", dir_src, res); + goto out; + } + + path_src = cmd_malloc(FS_TEST_PATH_MAX_SIZE); + path_dst = cmd_malloc(FS_TEST_PATH_MAX_SIZE); + buf = cmd_malloc(FS_TEST_DATA_BUF_SIZE); + + while (1) { + res = f_readdir(dp, entry); + if (res != FR_OK) { + CMD_ERR("read dir %s failed, return %d\n", dir_src, res); + goto out; + } + + if (entry->fname[0] == 0) { + break; + } + + cmd_snprintf(path_src, FS_TEST_PATH_MAX_SIZE, "%s/%s", dir_src, entry->fname); + cmd_snprintf(path_dst, FS_TEST_PATH_MAX_SIZE, "%s/%s", dir_dst, entry->fname); + if (entry->fattrib & AM_DIR) { + if (fs_test_cp_dir(path_dst, path_src) < 0) { + goto out; + } + } + + if (fs_test_cp_file(path_dst, path_src, buf, FS_TEST_DATA_BUF_SIZE) < 0) { + goto out; + } + } + + f_closedir(dp); + ret = 0; + +out: + if (buf) + cmd_free(buf); + + if (path_dst) + cmd_free(path_dst); + + if (path_src) + cmd_free(path_src); + + if (entry) + cmd_free(entry); + + if (dp) + cmd_free(dp); + + CMD_DBG("copy dir from %s to %s %s\n", + dir_src, dir_dst, ret == 0 ? "success" : "failed"); + return ret; +} + +struct fs_test_param { + uint8_t task_idx; + uint8_t file_num; + int file_size_unit; +}; + +static void fs_test_task(void *arg) +{ + char dir_path[2][64]; + struct fs_test_param *param = arg; + + CMD_DBG("fatfs test task %d start ...\n", param->task_idx); + + CMD_DBG("*** create dir and file test ***\n"); + cmd_sprintf(dir_path[0], "%s/dir%d_0-%s", CMD_FS_VOL_NAME, param->task_idx, FS_TEST_LFN_STR); + fs_test_create_dir(dir_path[0], param->file_num, param->file_size_unit); + + CMD_DBG("*** copy dir test ***\n"); + cmd_sprintf(dir_path[1], "%s/dir%d_1-%s", CMD_FS_VOL_NAME, param->task_idx, FS_TEST_LFN_STR); + fs_test_cp_dir(dir_path[1], dir_path[0]); + + CMD_DBG("*** copy dir test ***\n"); + cmd_sprintf(dir_path[1], "%s/dir%d_2-%s", CMD_FS_VOL_NAME, param->task_idx, FS_TEST_LFN_STR); + fs_test_cp_dir(dir_path[1], dir_path[0]); + + CMD_DBG("*** remove dir test ***\n"); + cmd_sprintf(dir_path[0], "%s/dir%d_0-%s", CMD_FS_VOL_NAME, param->task_idx, FS_TEST_LFN_STR); + fs_test_rm_dir(dir_path[0], 1); + + CMD_DBG("fatfs test task %d finish\n", param->task_idx); + cmd_free(arg); + OS_ThreadDelete(NULL); +} + +static enum cmd_status cmd_fs_mount_exec(char *cmd) +{ + FRESULT res; + + res = f_mount(&cmd_fs, "", 1); + if (res != FR_OK) { + CMD_ERR("mount fatfs failed, return %d\n", res); + return CMD_STATUS_FAIL; + } + + CMD_DBG("mount fatfs success\n"); + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_fs_unmount_exec(char *cmd) +{ + FRESULT res; + + res = f_mount(NULL, "", 1); + if (res != FR_OK) { + CMD_ERR("unmount fatfs failed, return %d\n", res); + return CMD_STATUS_FAIL; + } + + cmd_memset(&cmd_fs, 0, sizeof(cmd_fs)); + CMD_DBG("unmount fatfs success\n"); + return CMD_STATUS_OK; +} + +// fs test t=1, n=2, u=2097152 // 2MB +static enum cmd_status cmd_fs_test_exec(char *cmd) +{ + OS_Thread_t thread; + int i, thread_cnt, file_num, file_size_unit, cnt; + struct fs_test_param *param; + + cnt = cmd_sscanf(cmd, "t=%d, n=%d, u=%d", &thread_cnt, &file_num, &file_size_unit); + if (cnt != 3 || thread_cnt < 1) { + CMD_ERR("invalid argument %s\n", cmd); + return CMD_STATUS_FAIL; + } + + for (i = 0; i < thread_cnt; ++i) { + param = cmd_malloc(sizeof(struct fs_test_param)); + param->task_idx = i; + param->file_num = file_num; + param->file_size_unit = file_size_unit; + + OS_ThreadSetInvalid(&thread); + if (OS_ThreadCreate(&thread, + "", + fs_test_task, + (void *)param, + OS_THREAD_PRIO_APP, + 2 * 1024) != OS_OK) { + CMD_ERR("create fs test task %d failed\n", i); + return CMD_STATUS_FAIL; + } + OS_Sleep(1); + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_fs_emptydir_exec(char *cmd) +{ + if (fs_test_rm_dir(cmd, 0) < 0) + return CMD_STATUS_FAIL; + else + return CMD_STATUS_OK; +} + +static struct cmd_data g_fs_cmds[] = { + { "mount", cmd_fs_mount_exec }, + { "unmount", cmd_fs_unmount_exec }, + { "test", cmd_fs_test_exec }, + { "rmdir", cmd_fs_emptydir_exec }, +}; + +enum cmd_status cmd_fs_exec(char *cmd) +{ + return cmd_exec(cmd, g_fs_cmds, cmd_nitems(g_fs_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_fs.h b/platform/mcu/xr871/project/common/cmd/cmd_fs.h new file mode 100644 index 0000000000..6773e9f249 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_fs.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_FS_H_ +#define _CMD_FS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_fs_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_FS_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_heap.c b/platform/mcu/xr871/project/common/cmd/cmd_heap.c new file mode 100644 index 0000000000..daa4f32c2a --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_heap.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +extern void heap_get_space(uint8_t **start, uint8_t **end, uint8_t **current); + +enum cmd_status cmd_heap_space_exec(char *cmd) +{ + uint8_t *start, *end, *current; + + heap_get_space(&start, &end, ¤t); + cmd_write_respond(CMD_STATUS_OK, "heap total %u, use %u, free %u, [%p, %p, %p)", + end - start, current - start, end - current, start, current, end); + return CMD_STATUS_ACKED; +} + +static struct cmd_data g_heap_cmds[] = { + { "space", cmd_heap_space_exec }, +}; + +enum cmd_status cmd_heap_exec(char *cmd) +{ + return cmd_exec(cmd, g_heap_cmds, cmd_nitems(g_heap_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_heap.h b/platform/mcu/xr871/project/common/cmd/cmd_heap.h new file mode 100644 index 0000000000..37dec35bff --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_heap.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_HEAP_H_ +#define _CMD_HEAP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_heap_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_HEAP_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_httpc.c b/platform/mcu/xr871/project/common/cmd/cmd_httpc.c new file mode 100644 index 0000000000..97928a9ed7 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_httpc.c @@ -0,0 +1,509 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "net/HTTPClient/HTTPCUsr_api.h" +#include "net/mbedtls/mbedtls.h" + +static int HTTPC_checksum_check(void *url) +{ + if (strstr(url, "checksum") != NULL) + return 0; + return -1; +} +static char HTTPC_cal_checksum(void *buffer, int length) +{ + unsigned char *cal = (unsigned char *)buffer; + unsigned char result = 0; + while (length != 0) { + result += cal[--length]; + } + return result; +} + +static unsigned char checksum = 0; +static int checksum_flag = 0; +static int HTTPC_get_test(HTTPParameters *clientParams) +{ + int nRetCode = 0; + int recvSize = 0; + char *buf = NULL; + if ((buf = malloc(HTTP_CLIENT_BUFFER_SIZE)) == NULL) { + return -1; + } + do { + nRetCode = HTTPC_get(clientParams,buf, 4096,(INT32 *)&recvSize); + if (checksum_flag == 1) + checksum += HTTPC_cal_checksum(buf,recvSize); + + if (nRetCode != HTTP_CLIENT_SUCCESS) + break; + } while(1); + if (buf) { + free(buf); + buf = NULL; + } + if (nRetCode == HTTP_CLIENT_EOS) { + CMD_DBG("HTTP GET SUCCESS\n"); + nRetCode = HTTP_CLIENT_SUCCESS; + } + + return nRetCode; +} + +#ifdef HTTPC_CMD_REGISTER_USER_CALLBACK +security_client user_param; +extern const char mbedtls_test_cas_pem[]; +extern const size_t mbedtls_test_cas_pem_len; + +void* get_certs() +{ + memset(&user_param, 0, sizeof(user_param)); + user_param.pCa = (char *)mbedtls_test_cas_pem; + user_param.nCa = mbedtls_test_cas_pem_len; + return &user_param; +} +#endif + +static int HTTPC_get_test_fresh(HTTPParameters *clientParams) +{ + int ret = 0; + unsigned int toReadLength = 4096; + unsigned int Received = 0; + HTTP_CLIENT httpClient; + memset((void *)&httpClient, 0, sizeof(httpClient)); + char *buf = malloc(toReadLength); + if (buf == NULL) { + CMD_ERR("malloc pbuffer failed..\n"); + return -1; + } + + clientParams->HttpVerb = VerbGet; + +#ifdef HTTPC_CMD_REGISTER_USER_CALLBACK + HTTPC_Register_user_certs(get_certs); +#endif + + if (HTTPC_open(clientParams) != 0) { + CMD_ERR("http open err..\n"); + } else if (HTTPC_request(clientParams, NULL) != 0) { + CMD_ERR("http request err..\n"); + } else if (HTTPC_get_request_info(clientParams, &httpClient) != 0){ + CMD_ERR("http get request info err..\n"); + }else if (httpClient.TotalResponseBodyLength != 0) { + do { + if ((ret = HTTPC_read(clientParams, buf, toReadLength, (void *)&Received)) != 0) { + if (ret == 1000) { + CMD_DBG("The end..\n"); + } else + CMD_ERR("Transfer err...ret:%d\n",ret); + } else { + //CMD_DBG("get data :%d\n", Received); + } + + if (checksum_flag == 1) + checksum += HTTPC_cal_checksum(buf,Received); + + if (ret != 0) + break; + + } while (1); + + } + free(buf); + HTTPC_close(clientParams); + return ret; +} + +static int HTTPC_muti_get_test(HTTPParameters *clientParams,char *url0, char *url1) +{ + int ret = 0; + unsigned int toReadLength = 4096; + unsigned int Received = 0; + char *pUrl0 = NULL; + char *pUrl1 = NULL; + char *buf = malloc(toReadLength); + if (buf == NULL) { + CMD_ERR("malloc pbuffer failed..\n"); + return -1; + } + HTTP_CLIENT httpClient; + memset((void *)&httpClient, 0, sizeof(httpClient)); + clientParams->HttpVerb = VerbGet; + if ((pUrl0 = url0) == NULL) { + CMD_ERR("http request NULL url0..\n"); + ret = -1; + goto request_release; + } + if ((pUrl1 = url1) == NULL) { + CMD_ERR("http request NULL url..\n"); + ret = -1; + goto request_release; + } + strlcpy(clientParams->Uri, pUrl0,sizeof(clientParams->Uri)); + CMD_DBG("http test get url0..\n"); + if (HTTPC_open(clientParams) != 0) { + CMD_ERR("http open err..\n"); + ret = -1; + goto request_release; + } + pUrl0 = NULL; + goto direct_request; +set_url1: + HTTPC_reset_session(clientParams); + strlcpy(clientParams->Uri, pUrl1,sizeof(clientParams->Uri)); + CMD_DBG("http test get url1..\n"); + pUrl1 = NULL; +direct_request: + if (HTTPC_request(clientParams, NULL) != 0) { + CMD_ERR("http request err..\n"); + goto request_release; + } + if (HTTPC_get_request_info(clientParams, &httpClient) != 0){ + CMD_ERR("http get request info err..\n"); + }else if (httpClient.TotalResponseBodyLength != 0) { + do { + if ((ret = HTTPC_read(clientParams, buf, toReadLength, (void *)&Received)) != 0) { + if (ret == 1000) { + CMD_DBG("The end..\n"); + } else + CMD_ERR("Transfer err...ret:%d\n",ret); + } else { + //CMD_DBG("get data :%d\n", Received); + } + if (checksum_flag == 1) + checksum += HTTPC_cal_checksum(buf,Received); + if (ret != 0) + break; + } while (1); + + } + if (pUrl1 != NULL && checksum == 0xFF) { + checksum = 0; + goto set_url1; + } +request_release: + free(buf); + HTTPC_close(clientParams); + return ret; +} + +#if 0 +char *headers = "testkey0:testvalue0&testkey1:testvalue1"; +void* get_heads() +{ + return headers; +} +#endif +static int HTTPC_post_test(HTTPParameters *clientParams, char *credentials) +{ + int ret = 0; + unsigned int toReadLength = 4096; + unsigned int Received = 0; + char *buf = malloc(toReadLength); + if (buf == NULL) + CMD_ERR("malloc pbuffer failed..\n"); + HTTP_CLIENT httpClient; + memset((void *)&httpClient, 0, sizeof(httpClient)); + + memset(buf, 0, toReadLength); + clientParams->HttpVerb = VerbPost; + clientParams->pData = buf; + memcpy(buf, credentials, strlen(credentials)); + clientParams->pLength = strlen(credentials); +request: + if ((ret = HTTPC_open(clientParams)) != 0) { + CMD_ERR("http open err..\n"); + goto relese; + } + + if ((ret = HTTPC_request(clientParams, NULL)) != 0) { + CMD_ERR("http request err..\n"); + goto relese; + } + if ((ret = HTTPC_get_request_info(clientParams, &httpClient)) != 0) { + CMD_ERR("http get request info err..\n"); + goto relese; + } + if (httpClient.HTTPStatusCode != HTTP_STATUS_OK) { + if((httpClient.HTTPStatusCode == HTTP_STATUS_OBJECT_MOVED) || + (httpClient.HTTPStatusCode == HTTP_STATUS_OBJECT_MOVED_PERMANENTLY)) { + CMD_DBG("Redirect url..\n"); + HTTPC_close(clientParams); + memset(clientParams, 0, sizeof(*clientParams)); + clientParams->HttpVerb = VerbGet; + if (httpClient.RedirectUrl->nLength < sizeof(clientParams->Uri)) + strncpy(clientParams->Uri, httpClient.RedirectUrl->pParam, + httpClient.RedirectUrl->nLength); + else + goto relese; + CMD_DBG("go to request.\n"); + goto request; + + } else { + ret = -1; + CMD_DBG("get result not correct.\n"); + goto relese; + } + } + if (httpClient.TotalResponseBodyLength != 0 || (httpClient.HttpFlags & HTTP_CLIENT_FLAG_CHUNKED )) { + + do { + memset(buf, 0, 4096); + if ((ret = HTTPC_read(clientParams, buf, toReadLength, (void *)&Received)) != 0) { + //CMD_DBG("get data,Received:%d\n",Received); + if (ret == 1000) { + ret = 0; + CMD_DBG("The end..\n"); + } else + CMD_ERR("Transfer err...ret:%d\n",ret); + + if (checksum_flag == 1) + checksum += HTTPC_cal_checksum(buf,Received); + + break; + } else { + //CMD_DBG("get data,Received:%d\n",Received); + + } + if (checksum_flag == 1) + checksum += HTTPC_cal_checksum(buf,Received); + } while (1); + } +relese: + free(buf); + HTTPC_close(clientParams); + return ret; +} + +static int HTTPC_head_test(HTTPParameters *clientParams) +{ + return 0; +} +static int httpc_exec(char *cmd) +{ + //CMD_DBG("HTTPC TEST %s\n",cmd); + int ret = -1; + int argc = 0; + char *argv[6]; + + HTTPParameters *clientParams; + clientParams = malloc(sizeof(*clientParams)); + if (!clientParams) { + return -1; + } else{ + memset(clientParams,0,sizeof(HTTPParameters)); + } + + argc = cmd_parse_argv(cmd, argv, 6); + if (argc < 2) { + CMD_ERR("invalid httpc cmd, argc %d\n", argc); + ret = -1; + goto releaseParams; + } + + if (HTTPC_checksum_check(argv[1]) == 0) + checksum_flag = 1; + else + checksum_flag = 0; + checksum = 0; + + strcpy(clientParams->Uri,argv[1]); + if (cmd_strncmp(argv[0],"get",3) == 0) { + if ((ret = HTTPC_get_test(clientParams)) != 0) + goto releaseParams; + } else if (cmd_strncmp(argv[0], "post", 4) == 0) { + if (argc < 3) { + CMD_ERR("invalid httpc cmd(post), argc %d\n", argc); + ret = -1; + goto releaseParams; + } + if ((ret = HTTPC_post_test(clientParams, argv[2])) != 0) + goto releaseParams; + + } else if (cmd_strncmp(argv[0], "-get", 4) == 0) { + + if ((ret = HTTPC_get_test_fresh(clientParams)) != 0) + goto releaseParams; + + } else if (cmd_strncmp(argv[0], "head", 4) == 0) { + if ((ret = HTTPC_head_test(clientParams)) != 0) + goto releaseParams; + }else if (cmd_strncmp(argv[0], "auth-get", 8) == 0) { + // net httpc auth-get(0) url(1) test(id)(2) 12345678(key)(3) + if (argc < 4) { + CMD_ERR("invalid httpc cmd(auth-get), argc %d\n", argc); + ret = -1; + goto releaseParams; + } + cmd_memcpy(clientParams->UserName, argv[2], cmd_strlen(argv[2])); + cmd_memcpy(clientParams->Password, argv[3], cmd_strlen(argv[3])); + clientParams->AuthType = AuthSchemaDigest; + if ((ret = HTTPC_get_test_fresh(clientParams)) != 0) + goto releaseParams; + }else if (cmd_strncmp(argv[0], "ssl-get", 7) == 0) { + //net httpc ssl-get(0) url(1) + if ((ret = HTTPC_get_test_fresh(clientParams)) != 0) + goto releaseParams; + + }else if (cmd_strncmp(argv[0], "ssl-post", 8) == 0) { + //net httpc ssl-post(0) url(1) data(2) + if (argc < 3) { + CMD_ERR("invalid httpc cmd(ssl-post), argc %d\n", argc); + ret = -1; + goto releaseParams; + } + if ((ret = HTTPC_post_test(clientParams, argv[2])) != 0) + goto releaseParams; + }else if (cmd_strncmp(argv[0], "muti-get", 8) == 0) { + if (argc < 3) { + CMD_ERR("invalid httpc cmd(muti-get), argc %d\n", argc); + ret = -1; + goto releaseParams; + } + clientParams->Flags |= HTTP_CLIENT_FLAG_KEEP_ALIVE; + if ((ret = HTTPC_muti_get_test(clientParams,argv[1], argv[2])) != 0) + goto releaseParams; + }else if (cmd_strncmp(argv[0], "muti-post", 8) == 0) { + } + +releaseParams: + if (clientParams != NULL) { + free(clientParams); + clientParams = NULL; + } + if (checksum_flag == 1) { + printf("[httpc test]:checksum = %#x\n",checksum); + if (checksum != 0xff) + ret = -1; + else + ret = 0; + } + checksum_flag = 0; + checksum = 0; + return ret; +} + +#define HTTPC_THREAD_STACK_SIZE (4 * 1024) +static OS_Thread_t g_httpc_thread; + +void httpc_cmd_task(void *arg) +{ + char *cmd = (char *)arg; + CMD_LOG(1, " \n",cmd); + int ret = httpc_exec(cmd); + if (ret != 0 && ret != 1000) + CMD_LOG(1, " <%s>\n",cmd); + else { + CMD_LOG(1, " <%s>\n",cmd); + } + OS_ThreadDelete(&g_httpc_thread); +} + +enum cmd_status cmd_httpc_exec(char *cmd) +{ + if (OS_ThreadIsValid(&g_httpc_thread)) { + CMD_ERR("httpc task is running\n"); + return CMD_STATUS_FAIL; + } + if (OS_ThreadCreate(&g_httpc_thread, + "", + httpc_cmd_task, + (void *)cmd, + OS_THREAD_PRIO_APP, + HTTPC_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("httpc task create failed\n"); + return CMD_STATUS_FAIL; + } + return CMD_STATUS_OK; +} + +#if 0 + if (cmd_strncmp(argv[0],"__post_m",8) == 0) { + + strcpy(ClientParams->Uri,argv[1]); + int conLength = 0; + unsigned int toReadLength = 4096; + unsigned int Received = 0; + char *pBuffer = malloc(toReadLength); + if (pBuffer == NULL) + printf("malloc pbuffer failed..\n"); + + memset(pBuffer, 0, toReadLength); + ClientParams->HttpVerb = VerbPost; + ClientParams->pData = pBuffer; + ClientParams->sData = client_credentials; + ClientParams->sLength = strlen(client_credentials); + + if (HTTPC_open(ClientParams) != 0) { + + printf("http open err..\n"); + + } + unsigned int times = 0x2; + while(times--) { + if (HTTPC_request(ClientParams,(void *)&conLength) != 0) { + printf("http request err..\n"); + + } else if (conLength != 0 || (((P_HTTP_SESSION)(ClientParams->pHTTP))->HttpFlags & HTTP_CLIENT_FLAG_CHUNKED )) { + + do { + int retValue = 0; + if ((retValue = HTTPC_read(ClientParams, pBuffer, toReadLength, (void *)&Received)) != 0) { + if (retValue == 1000) { + printf("The end..\n"); + } else + printf("Transfer err...retValue:%d\n",retValue); + break; + + + } else { + printf("get data :%d\n", Received); + } + + } while (1); + } + if (retValue != 1000 && retValue != 0) { + printf("httpc post err...\n"); + break; + + } else { + printf("*******httpc post success********\n"); + while(1){ + OS_Sleep(20); + } + ret = retValue; + } + OS_Sleep(2); + } + + free(pBuffer); + HTTPC_close(ClientParams); + } +#endif diff --git a/platform/mcu/xr871/project/common/cmd/cmd_httpc.h b/platform/mcu/xr871/project/common/cmd/cmd_httpc.h new file mode 100644 index 0000000000..8de0b728bb --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_httpc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_HTTPC_H_ +#define _CMD_HTTPC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_httpc_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_HTTPC_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_httpd.c b/platform/mcu/xr871/project/common/cmd/cmd_httpd.c new file mode 100644 index 0000000000..1a21c28241 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_httpd.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_httpd.h" + +static OS_Thread_t g_httpd_thread; +#define HTTPD_THREAD_STACK_SIZE (4 * 1024) +#define HTTPD_THREAD_EXIT OS_ThreadDelete + +extern int webserver_start(int argc, char *argv[]); +extern void webserver_stop(); + +void httpd_run(void *arg) +{ + webserver_start(0, NULL); + HTTPD_THREAD_EXIT(&g_httpd_thread); + +} + +int httpd_start() +{ + if (OS_ThreadIsValid(&g_httpd_thread)) { + CMD_ERR("HTTPD task is running\n"); + return -1; + } + + if (OS_ThreadCreate(&g_httpd_thread, + "", + httpd_run, + NULL, + OS_THREAD_PRIO_APP, + HTTPD_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("httpd task create failed\n"); + return -1; + } + + return 0; +} +enum cmd_status cmd_httpd_exec(char *cmd) +{ + int argc; + char *argv[3]; + + argc = cmd_parse_argv(cmd, argv, 3); + if (argc < 1) { + CMD_ERR("invalid httpd cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + int enable = atoi(argv[0]); + if (enable == 1) + httpd_start(); + else + webserver_stop(); + + return CMD_STATUS_OK; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_httpd.h b/platform/mcu/xr871/project/common/cmd/cmd_httpd.h new file mode 100644 index 0000000000..4177f59d08 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_httpd.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_HTTPD_H_ +#define _CMD_HTTPD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_httpd_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_HTTPD_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_i2c.c b/platform/mcu/xr871/project/common/cmd/cmd_i2c.c new file mode 100644 index 0000000000..6c7c3ec2c5 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_i2c.c @@ -0,0 +1,508 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_i2c.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_i2c.h" + + +#define DRV_TEST_I2C_NORM 0 +#define DRV_TEST_I2C_MEM 1 +#define DRV_TEST_I2C_SCCB 0 + +#define DRV_TEST_I2C_ADDR_10BIT 0 + +static enum cmd_status cmd_i2c_init_exec(char *cmd) +{ + int cnt; + uint32_t id, addr_mode, clock_freq; + I2C_InitParam i2c_param; + HAL_Status hal_status; + + cnt = cmd_sscanf(cmd, "i=%u a=%u c=%u", &id, &addr_mode, &clock_freq); + if (cnt != 3) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + +#if DRV_TEST_I2C_ADDR_10BIT + if ((addr_mode != 7) && (addr_mode != 10)) { +#else /* DRV_TEST_I2C_ADDR_10BIT */ + if (addr_mode != 7) { +#endif /* DRV_TEST_I2C_ADDR_10BIT */ + CMD_ERR("invalid addr mode %u\n", addr_mode); + return CMD_STATUS_INVALID_ARG; + } + + if ((clock_freq < 100000) || (clock_freq > 400000)) { + CMD_ERR("invalid clock freq %u\n", clock_freq); + return CMD_STATUS_INVALID_ARG; + } + +#if DRV_TEST_I2C_ADDR_10BIT + if (addr_mode == 10) + i2c_param.addrMode = I2C_ADDR_MODE_10BIT; + else +#endif /* DRV_TEST_I2C_ADDR_10BIT */ + i2c_param.addrMode = I2C_ADDR_MODE_7BIT; + i2c_param.clockFreq = clock_freq; + + hal_status = HAL_I2C_Init((I2C_ID)id, &i2c_param); + if (hal_status == HAL_OK) { + return CMD_STATUS_OK; + } else { + CMD_ERR("HAL_I2C_Init return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } +} + +static enum cmd_status cmd_i2c_deinit_exec(char *cmd) +{ + int cnt; + uint32_t id; + HAL_Status hal_status; + + cnt = cmd_sscanf(cmd, "i=%u", &id); + if (cnt != 1) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + hal_status = HAL_I2C_DeInit((I2C_ID)id); + if (hal_status == HAL_OK) { + return CMD_STATUS_OK; + } else { + CMD_ERR("HAL_I2C_DeInit return: hal_status = %d\n", hal_status); + return CMD_STATUS_FAIL; + } +} + +#if DRV_TEST_I2C_NORM +static enum cmd_status cmd_i2c_transmit_norm_exec(char *cmd) +{ + int cnt; + uint32_t id, dev_addr, len; + uint8_t *buf; + int32_t size; + + cnt = cmd_sscanf(cmd, "i=%u d=%u l=%u", &id, &dev_addr, &len); + if (cnt != 3) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + +#if DRV_TEST_I2C_ADDR_10BIT + if ((dev_addr >> 10) != 0) { +#else /* DRV_TEST_I2C_ADDR_10BIT */ + if ((dev_addr >> 7) != 0) { +#endif /* DRV_TEST_I2C_ADDR_10BIT */ + CMD_ERR("invalid dev_addr %u\n", dev_addr); + return CMD_STATUS_INVALID_ARG; + } + + if ((len >> 31) != 0) { + CMD_ERR("invalid len %u\n", len); + return CMD_STATUS_INVALID_ARG; + } + + buf = (uint8_t *)cmd_malloc(len * sizeof(uint8_t)); + if (buf == NULL) { + CMD_ERR("cmd_malloc return NULL.\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + size = cmd_raw_mode_read(buf, (int32_t)len, 10000); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but raw mode read size = %d\n", len, size); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL", 4); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + + size = HAL_I2C_Master_Transmit_IT((I2C_ID)id, (uint16_t)dev_addr, buf, (int32_t)len); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but I2C transmit size = %d\n", len, size); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL", 4); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"OK", 2); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_i2c_receive_norm_exec(char *cmd) +{ + int cnt; + uint32_t id, dev_addr, len; + uint8_t *buf; + int32_t size; + + cnt = cmd_sscanf(cmd, "i=%u d=%u l=%u", &id, &dev_addr, &len); + if (cnt != 3) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + +#if DRV_TEST_I2C_ADDR_10BIT + if ((dev_addr >> 10) != 0) { +#else /* DRV_TEST_I2C_ADDR_10BIT */ + if ((dev_addr >> 7) != 0) { +#endif /* DRV_TEST_I2C_ADDR_10BIT */ + CMD_ERR("invalid dev_addr %u\n", dev_addr); + return CMD_STATUS_INVALID_ARG; + } + + if ((len >> 31) != 0) { + CMD_ERR("invalid len %u\n", len); + return CMD_STATUS_INVALID_ARG; + } + + buf = (uint8_t *)cmd_malloc(len * sizeof(uint8_t)); + if (buf == NULL) { + CMD_ERR("cmd_malloc return NULL.\n"); + return CMD_STATUS_FAIL; + } + cmd_memset(buf, 0, len); + + size = HAL_I2C_Master_Receive_IT((I2C_ID)id, (uint16_t)dev_addr, buf, (int32_t)len); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but I2C receive size = %d\n", len, size); + cmd_free(buf); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_msleep(1000); + + cmd_raw_mode_enable(); + size = cmd_raw_mode_write(buf, (int32_t)len); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but raw mode write size = %d\n", len, size); + } + + cmd_free(buf); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; +} +#endif /* DRV_TEST_I2C_NORM */ + +#if DRV_TEST_I2C_MEM +static enum cmd_status cmd_i2c_transmit_mem_exec(char *cmd) +{ + int cnt; + uint32_t id, dev_addr, mem_addr, len; + uint8_t *buf; + int32_t size; + + cnt = cmd_sscanf(cmd, "i=%u d=%u m=%u l=%u", &id, &dev_addr, &mem_addr, &len); + if (cnt != 4) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if ((mem_addr >> 8) != 0) { + CMD_ERR("invalid mem_addr %u\n", mem_addr); + return CMD_STATUS_INVALID_ARG; + } + + if (len > 16) { + CMD_ERR("invalid len %u\n", len); + return CMD_STATUS_INVALID_ARG; + } + + buf = (uint8_t *)cmd_malloc(len * sizeof(uint8_t)); + if (buf == NULL) { + CMD_ERR("cmd_malloc return NULL.\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + size = cmd_raw_mode_read(buf, (int32_t)len, 10000); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but raw mode read size = %d\n", len, size); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL", 4); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + + size = HAL_I2C_Master_Transmit_Mem_IT((I2C_ID)id, (uint16_t)dev_addr, (uint8_t)mem_addr, buf, (int32_t)len); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but I2C transmit size = %d\n", len, size); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL", 4); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"OK", 2); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_i2c_receive_mem_exec(char *cmd) +{ + int cnt; + uint32_t id, dev_addr, mem_addr, len; + uint8_t *buf; + int32_t size; + + cnt = cmd_sscanf(cmd, "i=%u d=%u m=%u l=%u", &id, &dev_addr, &mem_addr, &len); + if (cnt != 4) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if ((mem_addr >> 8) != 0) { + CMD_ERR("invalid mem_addr %u\n", mem_addr); + return CMD_STATUS_INVALID_ARG; + } + + if (len > 2048) { + CMD_ERR("invalid len %u\n", len); + return CMD_STATUS_INVALID_ARG; + } + + buf = (uint8_t *)cmd_malloc(len * sizeof(uint8_t)); + if (buf == NULL) { + CMD_ERR("cmd_malloc return NULL.\n"); + return CMD_STATUS_FAIL; + } + cmd_memset(buf, 0, len); + + size = HAL_I2C_Master_Receive_Mem_IT((I2C_ID)id, (uint16_t)dev_addr, (uint8_t)mem_addr, buf, (int32_t)len); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but I2C receive size = %d\n", len, size); + cmd_free(buf); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_msleep(1000); + + cmd_raw_mode_enable(); + size = cmd_raw_mode_write(buf, (int32_t)len); + if (size != (int32_t)len) { + CMD_ERR("len = %u, but raw mode write size = %d\n", len, size); + } + + cmd_free(buf); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; +} +#endif /* DRV_TEST_I2C_MEM */ + +#if DRV_TEST_I2C_SCCB +static enum cmd_status cmd_i2c_transmit_sccb_exec(char *cmd) +{ + int cnt; + uint32_t id, dev_addr, sub_addr; + uint8_t *buf; + int32_t size; + + cnt = cmd_sscanf(cmd, "i=%u d=%u s=%u", &id, &dev_addr, &sub_addr); + if (cnt != 3) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if ((dev_addr >> 8) != 0) { + CMD_ERR("invalid dev_addr %u\n", dev_addr); + return CMD_STATUS_INVALID_ARG; + } + + if ((sub_addr >> 8) != 0) { + CMD_ERR("invalid sub_addr %u\n", sub_addr); + return CMD_STATUS_INVALID_ARG; + } + + buf = (uint8_t *)cmd_malloc(sizeof(uint8_t)); + if (buf == NULL) { + CMD_ERR("cmd_malloc return NULL.\n"); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + size = cmd_raw_mode_read(buf, 1, 10000); + if (size != 1) { + CMD_ERR("len = 1, but raw mode read size = %d\n", size); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL", 4); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + + size = HAL_I2C_SCCB_Master_Transmit_IT((I2C_ID)id, (uint8_t)dev_addr, (uint8_t)sub_addr, buf); + if (size != 1) { + CMD_ERR("len = 1, but I2C transmit size = %d\n", size); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL", 4); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"OK", 2); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_i2c_receive_sccb_exec(char *cmd) +{ + int cnt; + uint32_t id, dev_addr, sub_addr; + uint8_t *buf; + int32_t size; + + cnt = cmd_sscanf(cmd, "i=%u d=%u s=%u", &id, &dev_addr, &sub_addr); + if (cnt != 3) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (id >= I2C_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if ((dev_addr >> 8) != 0) { + CMD_ERR("invalid dev_addr %u\n", dev_addr); + return CMD_STATUS_INVALID_ARG; + } + + if ((sub_addr >> 8) != 0) { + CMD_ERR("invalid sub_addr %u\n", sub_addr); + return CMD_STATUS_INVALID_ARG; + } + + buf = (uint8_t *)cmd_malloc(sizeof(uint8_t)); + if (buf == NULL) { + CMD_ERR("cmd_malloc return NULL.\n"); + return CMD_STATUS_FAIL; + } + cmd_memset(buf, 0, 1); + + size = HAL_I2C_SCCB_Master_Receive_IT((I2C_ID)id, (uint8_t)dev_addr, (uint8_t)sub_addr, buf); + if (size != 1) { + CMD_ERR("len = 1, but I2C receive size = %d\n", size); + cmd_free(buf); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_msleep(1000); + + cmd_raw_mode_enable(); + size = cmd_raw_mode_write(buf, 1); + if (size != 1) { + CMD_ERR("len = 1, but raw mode write size = %d\n", size); + } + + cmd_free(buf); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; +} +#endif /* DRV_TEST_I2C_SCCB */ + +static struct cmd_data g_i2c_cmds[] = { + { "init", cmd_i2c_init_exec }, + { "deinit", cmd_i2c_deinit_exec }, + +#if DRV_TEST_I2C_NORM + { "transmit-norm", cmd_i2c_transmit_norm_exec }, + { "receive-norm", cmd_i2c_receive_norm_exec }, +#endif /* DRV_TEST_I2C_NORM */ + +#if DRV_TEST_I2C_MEM + { "transmit-mem", cmd_i2c_transmit_mem_exec }, + { "receive-mem", cmd_i2c_receive_mem_exec }, +#endif /* DRV_TEST_I2C_MEM */ + +#if DRV_TEST_I2C_SCCB + { "transmit-sccb", cmd_i2c_transmit_sccb_exec }, + { "receive-sccb", cmd_i2c_receive_sccb_exec }, +#endif /* DRV_TEST_I2C_SCCB */ +}; + +enum cmd_status cmd_i2c_exec(char *cmd) +{ + return cmd_exec(cmd, g_i2c_cmds, cmd_nitems(g_i2c_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_i2c.h b/platform/mcu/xr871/project/common/cmd/cmd_i2c.h new file mode 100644 index 0000000000..6342a5473d --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_I2C_H_ +#define _CMD_I2C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_i2c_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_I2C_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ifconfig.c b/platform/mcu/xr871/project/common/cmd/cmd_ifconfig.c new file mode 100644 index 0000000000..71da0165f1 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ifconfig.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "lwip/inet.h" + +#include "cmd_util.h" + +#include "common/framework/net_ctrl.h" + +enum cmd_status cmd_ifconfig_exec(char *cmd) +{ + struct netif *nif = g_wlan_netif; + + if (nif == NULL) { + return CMD_STATUS_FAIL; + } + + if (cmd_strcmp(cmd, "status") == 0) { + if (netif_is_up(nif) && netif_is_link_up(nif)) { + char address[16]; + char gateway[16]; + char netmask[16]; + inet_ntoa_r(nif->ip_addr, address, sizeof(address)); + inet_ntoa_r(nif->gw, gateway, sizeof(gateway)); + inet_ntoa_r(nif->netmask, netmask, sizeof(netmask)); + cmd_write_respond(CMD_STATUS_OK, "%c%c%d up, " + "address:%s gateway:%s netmask:%s", + nif->name[0], nif->name[1], nif->num, + address, gateway, netmask); + } else { + cmd_write_respond(CMD_STATUS_OK, "%c%c%d down", + nif->name[0], nif->name[1], nif->num); + } + return CMD_STATUS_ACKED; + } else if (cmd_strcmp(cmd, "up") == 0) { + net_config(nif, 1); + } else if (cmd_strcmp(cmd, "down") == 0) { + net_config(nif, 0); + } else { + CMD_ERR("invalid argument '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + return CMD_STATUS_OK; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ifconfig.h b/platform/mcu/xr871/project/common/cmd/cmd_ifconfig.h new file mode 100644 index 0000000000..2dd1ca95ae --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ifconfig.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_IFCONFIG_H_ +#define _CMD_IFCONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_ifconfig_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_IFCONFIG_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_iperf.c b/platform/mcu/xr871/project/common/cmd/cmd_iperf.c new file mode 100644 index 0000000000..c6b7d7201a --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_iperf.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +#include "common/iperf/iperf.h" +#include "common/framework/net_ctrl.h" + +static const char *iperf_mode_str[IPERF_MODE_NUM] = { + "udp-send", + "udp-recv", + "tcp-send", + "tcp-recv", +}; /* index by enum IPERF_MODE */ +#define IPERF_STOP_SIGNAL "stop" +enum cmd_status cmd_iperf_exec(char *cmd) +{ + int argc, i; + char *argv[5]; + struct iperf_data idata; + cmd_memset(&idata, 0, sizeof(idata)); + argc = cmd_parse_argv(cmd, argv, 5); + if (cmd_strcmp(argv[0], IPERF_STOP_SIGNAL) == 0) { + if (iperf_stop(NULL) == 0) + return CMD_STATUS_OK; + else + return CMD_STATUS_FAIL; + } + if (argc < 3) { + CMD_ERR("invalid iperf cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + + for (i = 0; i < IPERF_MODE_NUM; ++i) { + if (cmd_strcmp(argv[0], iperf_mode_str[i]) == 0) { + idata.mode = (enum IPERF_MODE)i; + break; + } + } + + if (i >= IPERF_MODE_NUM) { + CMD_ERR("invalid iperf mode '%s'\n", argv[0]); + return CMD_STATUS_INVALID_ARG; + } + + cmd_strlcpy(idata.remote_ip, argv[1], 16); + idata.run_time = cmd_atoi(argv[2]); + if (argc == 4) + idata.port = cmd_atoi(argv[3]); + + if (iperf_start(g_wlan_netif, &idata) == 0) + return CMD_STATUS_OK; + else + return CMD_STATUS_FAIL; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_iperf.h b/platform/mcu/xr871/project/common/cmd/cmd_iperf.h new file mode 100644 index 0000000000..23809bc6ec --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_iperf.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_IPERF_H_ +#define _CMD_IPERF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_iperf_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_IPERF_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_irrx.c b/platform/mcu/xr871/project/common/cmd/cmd_irrx.c new file mode 100644 index 0000000000..9ae2018dc2 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_irrx.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_irrx.h" +#include "driver/chip/hal_irrx.h" + +enum cmd_irrx_action { + CMD_IRRX_ACTION_DECONFIG, + CMD_IRRX_ACTION_VALUE, +}; + +static uint32_t irrx_addr, irrx_key; +static IRRX_HandleTypeDef *irrx; + +static void irrx_rxcplt_callback(uint32_t addr, uint32_t key) +{ + irrx_addr = addr; + irrx_key = key; + + printf("received ir code addr:0x%02x key:0x%02x\n", addr, key); +} + +/* + * drv irrx config p= + */ +static enum cmd_status cmd_irrx_config_exec(char *cmd) +{ + IRRX_InitTypeDef irrx_param; + int32_t cnt; + char PulsePolarity[8]; + + cnt = cmd_sscanf(cmd, "p=%6s", PulsePolarity); + if (cnt != 1) { + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(PulsePolarity, "none") == 0) { + irrx_param.PulsePolariyInvert = IRRX_RPPI_NONE; + } else if (cmd_strcmp(PulsePolarity, "invert") == 0) { + irrx_param.PulsePolariyInvert = IRRX_RPPI_INVERT; + } else { + CMD_ERR("invalid PulsePolarity:%s\n", PulsePolarity); + return CMD_STATUS_INVALID_ARG; + } + + irrx_param.rxCpltCallback = &irrx_rxcplt_callback; + + irrx = HAL_IRRX_Init(&irrx_param); + + return CMD_STATUS_OK; +} + +/* + * drv irrx + */ +static enum cmd_status cmd_irrx_action_exec(char *cmd, enum cmd_irrx_action action) +{ + enum cmd_status status; + + status = CMD_STATUS_OK; + switch (action) { + case CMD_IRRX_ACTION_DECONFIG: + HAL_IRRX_DeInit(irrx); + break; + case CMD_IRRX_ACTION_VALUE: + cmd_write_respond(CMD_STATUS_OK, "addr=0x%02x key=0x%02x", irrx_addr, irrx_key); + status = CMD_STATUS_ACKED; + break; + default: + status = CMD_STATUS_INVALID_ARG; + break; + } + return status; +} + +/* + * drv irrx deconfig + */ +static enum cmd_status cmd_irrx_deconfig_exec(char *cmd) +{ + return cmd_irrx_action_exec(cmd, CMD_IRRX_ACTION_DECONFIG); +} + +/* + * drv irrx value + */ +static enum cmd_status cmd_irrx_value_exec(char *cmd) +{ + return cmd_irrx_action_exec(cmd, CMD_IRRX_ACTION_VALUE); +} + +static struct cmd_data g_irrx_cmds[] = { + { "config", cmd_irrx_config_exec }, + { "deconfig", cmd_irrx_deconfig_exec }, + { "value", cmd_irrx_value_exec }, +}; + +enum cmd_status cmd_irrx_exec(char *cmd) +{ + return cmd_exec(cmd, g_irrx_cmds, cmd_nitems(g_irrx_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_irrx.h b/platform/mcu/xr871/project/common/cmd/cmd_irrx.h new file mode 100644 index 0000000000..9c711f64bf --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_irrx.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_IRRX_H_ +#define _CMD_IRRX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* example: + * 1. init irrx use: drv irrx config p=invert + * use "p=none" when tx rx gpio direct connect in test mode. + * 2. get received addr and key use: drv irrx value 0 + * 3. deinit irrx use: drv irrx deconfig 0 + */ + +enum cmd_status cmd_irrx_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_IRRX_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_irtx.c b/platform/mcu/xr871/project/common/cmd/cmd_irtx.c new file mode 100644 index 0000000000..3380b0957b --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_irtx.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_irtx.h" +#include "driver/chip/hal_clock.h" +#include "driver/chip/hal_irtx.h" +#include "driver/chip/ir_nec.h" + +enum cmd_irtx_action { + CMD_IRTX_ACTION_DECONFIG, + CMD_IRTX_ACTION_SEND, +}; + +static IRTX_HandleTypeDef *irtx; + +/* + * drv irtx config p= d= t= + * c= m= r= + */ +static enum cmd_status cmd_irtx_config_exec(char *cmd) +{ + char PulsePolarity[8], ModulateDutyLevel[4], SendModeType[8], Modulation[4], Protocol[8]; + int32_t cnt; + int32_t CyclicalCnt; + IRTX_InitTypeDef irtx_param; + + cnt = cmd_sscanf(cmd, "p=%6s d=%2s t=%5s c=%u m=%3s r=%3s", + PulsePolarity, ModulateDutyLevel, SendModeType, &CyclicalCnt, Modulation, Protocol); + if (cnt != 6) { + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(PulsePolarity, "none") == 0) { + irtx_param.PulsePolarity = IRTX_TPPI_NONE; + } else if (cmd_strcmp(PulsePolarity, "invert") == 0) { + irtx_param.PulsePolarity = IRTX_TPPI_INVERT; + } else { + CMD_ERR("invalid PulsePolarity:%s\n", PulsePolarity); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(ModulateDutyLevel, "t1") == 0) { + irtx_param.ModulateDutyLevel = IRTX_DRMC_TIME_1; + } else if (cmd_strcmp(ModulateDutyLevel, "t2") == 0) { + irtx_param.ModulateDutyLevel = IRTX_DRMC_TIME_2; + } else if (cmd_strcmp(ModulateDutyLevel, "t3") == 0) { + irtx_param.ModulateDutyLevel = IRTX_DRMC_TIME_3; + } else { + CMD_ERR("invalid ModulateDutyLevel:%s\n", ModulateDutyLevel); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(SendModeType, "none") == 0) { /* IRTX_TTS_NONE for signal mode */ + irtx_param.SendModeType = IRTX_TTS_NONE; + } else if (cmd_strcmp(SendModeType, "cycle") == 0) { /* IRTX_TTS_CYCLICAL for cycle mode */ + irtx_param.SendModeType = IRTX_TTS_CYCLICAL; + } else { + CMD_ERR("invalid SendModeType:%s\n", SendModeType); + return CMD_STATUS_INVALID_ARG; + } + + + if (cmd_strcmp(Modulation, "dis") == 0) { /* IRTX_TTS_NONE for signal mode */ + irtx_param.InternalModulation = IRTX_IMS_DISABLE; + } else if (cmd_strcmp(Modulation, "en") == 0) { /* IRTX_TTS_CYCLICAL for cycle mode */ + irtx_param.InternalModulation = IRTX_IMS_ENABLE; + } else { + CMD_ERR("invalid InternalModulation:%s\n", Modulation); + return CMD_STATUS_INVALID_ARG; + } + + irtx_param.CyclicalCnt = CyclicalCnt; /* send CyclicalCnt times if cycle mode */ + + if (CyclicalCnt > 20) { + CMD_ERR("invalid CyclicalCnt:%d\n", CyclicalCnt); + return CMD_STATUS_INVALID_ARG; + } + if (cmd_strcmp(Protocol, "nec") == 0) { +#if defined (IR_CLK_32K_USED) + irtx_param.IdleDurationCnt = IRTX_32K_NEC_IDC_VALUE; +#else + uint32_t clk = HAL_GetHFClock(); + + if (clk == HOSC_CLOCK_26M) { + irtx_param.IdleDurationCnt = IRTX_26M_NEC_IDC_VALUE; + } else if (clk == HOSC_CLOCK_24M) { + irtx_param.IdleDurationCnt = IRTX_24M_NEC_IDC_VALUE; + } else { + CMD_ERR("%s unknow clk type(%d)!\n", __func__, clk); + } +#endif + } else { + CMD_ERR("invalid protocol:%s\n", Protocol); + return CMD_STATUS_INVALID_ARG; + } + + irtx = HAL_IRTX_Init(&irtx_param); + + return CMD_STATUS_OK; +} + +/* + * drv irtx + */ +static enum cmd_status cmd_irtx_action_exec(char *cmd, enum cmd_irtx_action action) +{ + enum cmd_status status; + + status = CMD_STATUS_OK; + switch (action) { + case CMD_IRTX_ACTION_DECONFIG: + HAL_IRTX_DeInit(irtx); + break; + case CMD_IRTX_ACTION_SEND: { + int32_t addr, key; + int32_t cnt; + + cnt = cmd_sscanf(cmd, "a=0x%x k=0x%x", &addr, &key); + if (cnt != 2) { + return CMD_STATUS_INVALID_ARG; + } + HAL_IRTX_Transmit(irtx, IRTX_NEC_PROTO, IR_NEC_CODE(addr, key)); + break; + } + default: + status = CMD_STATUS_INVALID_ARG; + break; + } + return status; +} + +/* + * drv irtx deconfig + */ +static enum cmd_status cmd_irtx_deconfig_exec(char *cmd) +{ + return cmd_irtx_action_exec(cmd, CMD_IRTX_ACTION_DECONFIG); +} + +/* + * drv irtx send + */ +static enum cmd_status cmd_irtx_send_exec(char *cmd) +{ + return cmd_irtx_action_exec(cmd, CMD_IRTX_ACTION_SEND); +} + +static struct cmd_data g_irtx_cmds[] = { + { "config", cmd_irtx_config_exec }, + { "deconfig", cmd_irtx_deconfig_exec }, + { "send", cmd_irtx_send_exec }, +}; + +enum cmd_status cmd_irtx_exec(char *cmd) +{ + return cmd_exec(cmd, g_irtx_cmds, cmd_nitems(g_irtx_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_irtx.h b/platform/mcu/xr871/project/common/cmd/cmd_irtx.h new file mode 100644 index 0000000000..c77725beb3 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_irtx.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_IRTX_H_ +#define _CMD_IRTX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* example: + * 1. init irtx mode use + * single: drv irtx config p=none d=t1 t=none c=0 m=en r=nec + * cycle : drv irtx config p=none d=t1 t=cycle c=3 m=en r=nec + * use "m=dis" when tx rx gpio direct connect in test mode. + * 2. send addr and key use: drv irtx send a=0x0 k=0x18 + * 3. deinit irtx use: drv irtx deconfig 0 + */ + +enum cmd_status cmd_irtx_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_IRTX_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_mem.c b/platform/mcu/xr871/project/common/cmd/cmd_mem.c new file mode 100644 index 0000000000..be4b18124c --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_mem.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +/* + * $ mem r8 + * $ mem r16 + * $ mem r32 + * $ mem w8 + * $ mem w16 + * $ mem w32 + */ + +#define MEM_LOG(fmt, arg...) printf(fmt, ##arg) + +enum mem_rw_mode { + MEM_RW_MODE_8BIT = 0, + MEM_RW_MODE_16BIT, + MEM_RW_MODE_32BIT, + MEM_RW_MODE_NUM +}; + +struct mem_dump_param { + const char *hint_fmt; + const char *data_fmt; + uint8_t byte_align; +}; + +#define MEM_DUMP_BYTES_PER_LINE 16 + +static const struct mem_dump_param g_mem_dump_param[MEM_RW_MODE_NUM] = { +// "12345678: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F" + { "address 0 1 2 3 4 5 6 7 8 9 A B C D E F", " %02x", 1 }, + +// "12345678: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E" + { "address 0 2 4 6 8 A C E", " %04x", 2 }, + +// "12345678: 03020100 07060504 0B0A0908 0F0E0D0C" + { "address 0 4 8 C", " %08x", 4 } +}; + +static int mem_dump(uint32_t addr, uint32_t len, enum mem_rw_mode mode) +{ + uint32_t i, byte_align, item_cnt, item_per_line; + const char *data_fmt; + const struct mem_dump_param *param; + + if (mode >= MEM_RW_MODE_NUM) { + MEM_LOG("invalid mem rw mode %d\n", mode); + return -1; + } + + param = &g_mem_dump_param[mode]; + byte_align = param->byte_align; + if ((addr & (byte_align - 1)) != 0) { + MEM_LOG("addr 0x%08x not align with %u\n", addr, byte_align); + return -1; + } + + item_cnt = len / byte_align; + item_per_line = MEM_DUMP_BYTES_PER_LINE / byte_align; + data_fmt = param->data_fmt; + + MEM_LOG(param->hint_fmt); + switch (mode) { + case MEM_RW_MODE_8BIT: + for (i = 0; i < item_cnt; ++i) { + if (i % item_per_line == 0) { + MEM_LOG("\n%08x:", addr); + } + MEM_LOG(data_fmt, *((uint8_t *)addr)); + addr += byte_align; + } + break; + case MEM_RW_MODE_16BIT: + for (i = 0; i < item_cnt; ++i) { + if (i % item_per_line == 0) { + MEM_LOG("\n%08x:", addr); + } + MEM_LOG(data_fmt, *((uint16_t *)addr)); + addr += byte_align; + } + break; + case MEM_RW_MODE_32BIT: + for (i = 0; i < item_cnt; ++i) { + if (i % item_per_line == 0) { + MEM_LOG("\n%08x:", addr); + } + MEM_LOG(data_fmt, *((uint32_t *)addr)); + addr += byte_align; + } + break; + default: + break; + } + MEM_LOG("\n"); + + return 0; +} + +static enum mem_rw_mode cmd_mem_parse_arg(char *cmd, uint32_t *addr, uint32_t *val) +{ + int argc; + char *argv[3]; + uint32_t bits; + enum mem_rw_mode mode; + + argc = cmd_parse_argv(cmd, argv, cmd_nitems(argv)); + if (argc != 3) { + return MEM_RW_MODE_NUM; + } + + if (cmd_sscanf(argv[0], "%u", &bits) != 1) { + return MEM_RW_MODE_NUM; + } + + switch (bits) { + case 8: + mode = MEM_RW_MODE_8BIT; + break; + case 16: + mode = MEM_RW_MODE_16BIT; + break; + case 32: + mode = MEM_RW_MODE_32BIT; + break; + default: + return MEM_RW_MODE_NUM; + } + + if (cmd_sscanf(argv[1], "%x", addr) != 1) { + return MEM_RW_MODE_NUM; + } + + if (cmd_strncasecmp(argv[2], "0x", 2) == 0) { + if (cmd_sscanf(argv[2], "%x", val) != 1) { + return MEM_RW_MODE_NUM; + } + } else { + if (cmd_sscanf(argv[2], "%u", val) != 1) { + return MEM_RW_MODE_NUM; + } + } + return mode; +} + +static enum cmd_status cmd_mem_read_exec(char *cmd) +{ + uint32_t addr, len; + enum mem_rw_mode mode; + + mode = cmd_mem_parse_arg(cmd, &addr, &len); + if (mode >= MEM_RW_MODE_NUM) { + return CMD_STATUS_INVALID_ARG; + } + + mem_dump(addr, len, mode); + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_mem_write_exec(char *cmd) +{ + uint32_t addr, value; + enum mem_rw_mode mode; + + mode = cmd_mem_parse_arg(cmd, &addr, &value); + if (mode >= MEM_RW_MODE_NUM) { + return CMD_STATUS_INVALID_ARG; + } + + switch (mode) { + case MEM_RW_MODE_8BIT: + *((volatile uint8_t *)addr) = (uint8_t)value; + MEM_LOG("write 0x%02x -> 0x%08x\n", (uint8_t)value, addr); + break; + case MEM_RW_MODE_16BIT: + *((volatile uint16_t *)addr) = (uint16_t)value; + MEM_LOG("write 0x%04x -> 0x%08x\n", (uint16_t)value, addr); + break; + case MEM_RW_MODE_32BIT: + *((volatile uint32_t *)addr) = (uint32_t)value; + MEM_LOG("write 0x%08x -> 0x%08x\n", (uint32_t)value, addr); + break; + default: + break; + } + + return CMD_STATUS_ACKED; +} + +static struct cmd2_data g_mem_cmds[] = { + { "r", 1, cmd_mem_read_exec }, + { "w", 1, cmd_mem_write_exec }, +}; + +enum cmd_status cmd_mem_exec(char *cmd) +{ + return cmd2_exec(cmd, g_mem_cmds, cmd_nitems(g_mem_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_mem.h b/platform/mcu/xr871/project/common/cmd/cmd_mem.h new file mode 100644 index 0000000000..e89a5b4634 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_mem.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_MEM_H_ +#define _CMD_MEM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_mem_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_MEM_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_mqtt.c b/platform/mcu/xr871/project/common/cmd/cmd_mqtt.c new file mode 100644 index 0000000000..9ee64e3a51 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_mqtt.c @@ -0,0 +1,559 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_mqtt.h" +#include "net/mqtt/MQTTClient-C/MQTTClient.h" + + +static MQTTPacket_connectData connectData = MQTTPacket_connectData_initializer; +static char *client_name; +static uint8_t *send_buf; +static uint8_t *recv_buf; +static Client client; +static Network network; + +#define MAX_SUB_TOPICS 5 +static char *sub_topic[MAX_SUB_TOPICS]; + +#define CMD_MQTT_BG_THREAD_STACK_SIZE (1024) +static OS_Thread_t mqtt_bg_thread; + +static OS_Mutex_t lock; + + +static enum cmd_status cmd_mqtt_init_exec(char *cmd) +{ + int32_t cnt; + uint32_t buf_size; + uint32_t alive_interval; + uint32_t clean; + char *tmp; + + /* get param */ + cnt = cmd_sscanf(cmd, "bufsize=%u alive=%u clean=%u", + &buf_size, &alive_interval, &clean); + + /* check param */ + if (cnt != 3) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (clean > 1) { + CMD_ERR("invalid clean %d\n", clean); + return CMD_STATUS_INVALID_ARG; + } + + if (OS_MutexCreate(&lock) != OS_OK) + return CMD_STATUS_FAIL;; + + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + client_name = cmd_malloc(cmd_strlen(tmp) + 1); + + cmd_memcpy(client_name, tmp, cmd_strlen(tmp) + 1); + CMD_DBG("client name = %s\n", client_name); + + connectData.clientID.cstring = client_name; + connectData.keepAliveInterval = alive_interval; + connectData.cleansession = clean; + + send_buf = cmd_malloc(buf_size); + if (send_buf == NULL) { + CMD_ERR("no memory\n"); + OS_MutexDelete(&lock); + return CMD_STATUS_FAIL; + } + recv_buf = cmd_malloc(buf_size); + if (recv_buf == NULL) { + cmd_free(send_buf); + CMD_ERR("no memory\n"); + OS_MutexDelete(&lock); + return CMD_STATUS_FAIL; + } + + NewNetwork(&network); + MQTTClient(&client, &network, 6000, send_buf, buf_size, recv_buf, buf_size); + + + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_mqtt_will_exec(char *cmd) +{ + int32_t cnt; + char *topic; + uint8_t *buf; + char *tmp; + uint32_t qos; + uint32_t retain; + uint32_t size; + + /* get param */ + cnt = cmd_sscanf(cmd, "qos=%u retain=%u", + &qos, &retain); + + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + cnt += cmd_sscanf(tmp + 2, "size=%u", &size); + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + /* check param */ + if (cnt != 3) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (qos > 2) { + CMD_ERR("invalid qos %d\n", qos); + return CMD_STATUS_INVALID_ARG; + } + + if (retain > 1) { + CMD_ERR("invalid retain %d\n", retain); + return CMD_STATUS_INVALID_ARG; + } + + topic = tmp; + CMD_DBG("topic name = %s\n", topic); + + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + + cmd_write_respond(CMD_STATUS_OK, "OK"); + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, size, 30000); + cmd_raw_mode_disable(); + + //will function + connectData.willFlag = 1; + connectData.will.message.lenstring.data = (char *)buf; + connectData.will.message.lenstring.len = size; + connectData.will.qos = qos; + connectData.will.retained = retain; + connectData.will.topicName.cstring = topic; + + cmd_free(buf); + + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_mqtt_user_exec(char *cmd) +{ + char *tmp; + uint32_t size; + + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + if ((size = cmd_strlen(tmp)) == 0) + return CMD_STATUS_INVALID_ARG; + size++; + + connectData.username.lenstring.data = cmd_malloc(size); + connectData.username.lenstring.len = size; + memcpy(connectData.username.lenstring.data, tmp, size); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_mqtt_password_exec(char *cmd) +{ + char *tmp; + uint32_t size; + + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + if ((size = cmd_strlen(tmp)) == 0) + return CMD_STATUS_INVALID_ARG; + size++; + + connectData.password.lenstring.data = cmd_malloc(size); + connectData.password.lenstring.len = size; + memcpy(connectData.password.lenstring.data, tmp, size); + + return CMD_STATUS_OK; +} + + +static void cmd_mqtt_bg(void *arg) +{ + int rc; + + while (1) { + OS_MutexLock(&lock, 0xffffffffU); + if ((rc = MQTTYield(&client, 3000)) != 0) + CMD_WRN("Return code from yield is %d\n", rc); + OS_MutexUnlock(&lock); + } + +} + +static enum cmd_status cmd_mqtt_connect_exec(char *cmd) +{ + int32_t cnt; + char addr_str[15]; + uint32_t port; + int32_t rc; + uint32_t i; + + /* get param */ + cnt = cmd_sscanf(cmd, "server=%15s port=%u", + addr_str, &port); + + /* check param */ + if (cnt != 2) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + i = 10; + char* address = addr_str; + while ((rc = ConnectNetwork(&network, address, port)) != 0) + { + CMD_WRN("Return code from network connect is %d\n", rc); + cmd_msleep(2000); + if (!(i--)) + return CMD_STATUS_FAIL; + } + + if ((rc = MQTTConnect(&client, &connectData)) != 0) { + CMD_ERR("Return code from MQTT connect is %d\n", rc); + return CMD_STATUS_FAIL; + } + else + CMD_DBG("MQTT Connected\n"); + + + + if (OS_ThreadCreate(&mqtt_bg_thread, + "", + cmd_mqtt_bg, + NULL, + OS_PRIORITY_NORMAL, + CMD_MQTT_BG_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("create mqtt background failed\n"); + return CMD_STATUS_FAIL; + } + + + return CMD_STATUS_OK; +} + +void mqtt_msg_cb(MessageData* data) +{ + cmd_write_event(CMD_EVENT_MQTT_MSG_RECV, "[topic: %.*s] %.*s", data->topicName->lenstring.len, + data->topicName->lenstring.data, data->message->payloadlen, + (char *)data->message->payload); +} + +static enum cmd_status cmd_mqtt_subscribe_exec(char *cmd) +{ + int32_t cnt; + uint32_t i; + char *tmp; + uint32_t qos; + int rc; + + /* get param */ + cnt = cmd_sscanf(cmd, "qos=%u", + &qos); + + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + + /* check param */ + if (cnt != 1) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (qos > 2) { + CMD_ERR("invalid qos %d\n", qos); + return CMD_STATUS_INVALID_ARG; + } + + i = 0; + while (sub_topic[i] != NULL) { + i++; + if (i >= MAX_SUB_TOPICS) { + CMD_WRN("Subscribe topics is max\n"); + return CMD_STATUS_FAIL; + } + } + + sub_topic[i] = cmd_malloc(cmd_strlen(tmp) + 1); + cmd_memcpy(sub_topic[i], tmp, cmd_strlen(tmp) + 1); + + if (OS_MutexLock(&lock, 60000) == OS_E_TIMEOUT) + return CMD_STATUS_FAIL; + + if ((rc = MQTTSubscribe(&client, sub_topic[i], qos, mqtt_msg_cb)) != 0) { + CMD_ERR("Return code from MQTT subscribe is %d\n", rc); + return CMD_STATUS_FAIL; + } + + OS_MutexUnlock(&lock); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_mqtt_unsubscribe_exec(char *cmd) +{ + uint32_t i; + char *tmp; + int rc; + + /* get param */ + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + i = 0; + while (i < MAX_SUB_TOPICS) { + if ((sub_topic[i] != NULL) && (!cmd_memcmp(sub_topic[i], tmp, cmd_strlen(tmp) + 1))) + break; + i++; + } + + if (OS_MutexLock(&lock, 60000) == OS_E_TIMEOUT) + return CMD_STATUS_FAIL; + + if ((rc = MQTTUnsubscribe(&client, tmp/*sub_topic[i]*/)) != 0) { + CMD_ERR("Return code from MQTT unsubscribe is %d\n", rc); + return CMD_STATUS_FAIL; + } + + if (i == MAX_SUB_TOPICS) + CMD_WRN("Unsubscribe topics is inexist\n"); + else { + cmd_free(sub_topic[i]); + sub_topic[i] = NULL; + } + + OS_MutexUnlock(&lock); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_mqtt_publish_exec(char *cmd) +{ + int32_t cnt; + MQTTMessage message; + char *topic; + uint8_t *buf; + char *tmp; + uint32_t qos; + uint32_t retain; + uint32_t size; + int rc; + + /* get param */ + cnt = cmd_sscanf(cmd, "qos=%u retain=%u", + &qos, &retain); + + if ((tmp = cmd_strrchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + *tmp = '\0'; + cnt += cmd_sscanf(tmp + 2, "size=%u", &size); + if ((tmp = cmd_strchr(cmd, '\"')) == NULL) + return CMD_STATUS_INVALID_ARG; + tmp++; + + + /* check param */ + if (cnt != 3) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (qos > 2) { + CMD_ERR("invalid qos %d\n", qos); + return CMD_STATUS_INVALID_ARG; + } + + if (retain > 1) { + CMD_ERR("invalid retain %d\n", retain); + return CMD_STATUS_INVALID_ARG; + } + + topic = tmp; + CMD_DBG("topic name = %s\n", topic); + + buf = cmd_malloc(size); + if (buf == NULL) { + CMD_ERR("no memory\n"); + return CMD_STATUS_FAIL; + } + + + cmd_write_respond(CMD_STATUS_OK, "OK"); + cmd_raw_mode_enable(); + cmd_raw_mode_read(buf, size, 30000); + + message.qos = qos; + message.retained = retain; + message.payload = buf; + message.payloadlen = size; + + if (OS_MutexLock(&lock, 60000) == OS_E_TIMEOUT) + return CMD_STATUS_FAIL; + + if ((rc = MQTTPublish(&client, topic, &message)) != 0) + CMD_ERR("Return code from MQTT publish is %d\n", rc); + else + CMD_DBG("MQTT publish is success\n"); + + OS_MutexUnlock(&lock); + + cmd_raw_mode_write((uint8_t *)&rc, sizeof(rc)); + cmd_raw_mode_disable(); + + cmd_free(buf); + + return CMD_STATUS_ACKED; + +} + +static enum cmd_status cmd_mqtt_disconnect_exec(char *cmd) +{ + int32_t cnt; + uint32_t tcponly; + int rc; + uint32_t i; + + /* get param */ + cnt = cmd_sscanf(cmd, "tcponly=%u", + &tcponly); + + /* check param */ + if (cnt != 1) { + CMD_ERR("invalid param number %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (tcponly > 1) { + CMD_ERR("invalid tcponly %d\n", tcponly); + return CMD_STATUS_INVALID_ARG; + } + + + OS_ThreadDelete(&mqtt_bg_thread); + + i = 0; + while (i < MAX_SUB_TOPICS) { + if (sub_topic[i] != NULL) { + cmd_free(sub_topic[i]); + sub_topic[i] = NULL; + } + i++; + } + + if (tcponly == 0) { + if ((rc = MQTTDisconnect(&client)) != 0){ + CMD_ERR("Return code from MQTT disconnect is %d\n", rc); + network.disconnect(&network); + return CMD_STATUS_FAIL; + } + } else { + network.disconnect(&network); + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_mqtt_deinit_exec(char *cmd) +{ + + + + if (connectData.username.lenstring.len != 0) + cmd_free(connectData.username.lenstring.data); + if (connectData.password.lenstring.len != 0) + cmd_free(connectData.password.lenstring.data); + + cmd_free(send_buf); + cmd_free(recv_buf); + cmd_free(client_name); + + OS_MutexDelete(&lock); + + connectData = (MQTTPacket_connectData)MQTTPacket_connectData_initializer; + + return CMD_STATUS_OK; +} + +static struct cmd_data g_mqtt_cmds[] = { + { "init", cmd_mqtt_init_exec }, + { "will", cmd_mqtt_will_exec }, + { "user", cmd_mqtt_user_exec }, + { "password", cmd_mqtt_password_exec }, + { "connect", cmd_mqtt_connect_exec }, + { "subscribe", cmd_mqtt_subscribe_exec }, + { "unsubscribe", cmd_mqtt_unsubscribe_exec }, + { "publish", cmd_mqtt_publish_exec }, + { "disconnect", cmd_mqtt_disconnect_exec }, + { "deinit", cmd_mqtt_deinit_exec }, +}; + +enum cmd_status cmd_mqtt_exec(char *cmd) +{ + return cmd_exec(cmd, g_mqtt_cmds, cmd_nitems(g_mqtt_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_mqtt.h b/platform/mcu/xr871/project/common/cmd/cmd_mqtt.h new file mode 100644 index 0000000000..051f0f92bc --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_mqtt.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_MQTT_H_ +#define _CMD_MQTT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_mqtt_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_MQTT_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_netcmd.c b/platform/mcu/xr871/project/common/cmd/cmd_netcmd.c new file mode 100644 index 0000000000..c8e9949a7f --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_netcmd.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "sys/ducc/ducc_app.h" + +enum cmd_status cmd_netcmd_exec(char *cmd) +{ + cmd_write_respond(CMD_STATUS_OK, cmd_get_status_desc(CMD_STATUS_OK)); + ducc_app_ioctl(DUCC_APP_CMD_CONSOLE_EXEC, cmd); + return CMD_STATUS_ACKED; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_netcmd.h b/platform/mcu/xr871/project/common/cmd/cmd_netcmd.h new file mode 100644 index 0000000000..2fba08e957 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_netcmd.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_NETCMD_H_ +#define _CMD_NETCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_netcmd_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_NETCMD_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_nopoll.c b/platform/mcu/xr871/project/common/cmd/cmd_nopoll.c new file mode 100644 index 0000000000..e28ec180a3 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_nopoll.c @@ -0,0 +1,892 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "net/nopoll/nopoll.h" + +static const char g_root_pem[] = +"-----BEGIN CERTIFICATE-----\r\n" +"MIID2TCCAsGgAwIBAgIJAM55lRNEqQ/FMA0GCSqGSIb3DQEBCwUAMIGCMQswCQYD\r\n" +"VQQGEwJFUzEPMA0GA1UECAwGTWFkcmlkMQ8wDQYDVQQHDAZNYWRyaWQxDTALBgNV\r\n" +"BAoMBEFTUEwxEzARBgNVBAsMClRJIFN1cHBvcnQxDTALBgNVBAMMBFJvb3QxHjAc\r\n" +"BgkqhkiG9w0BCQEWD3NvcG9ydGVAYXNwbC5lczAeFw0xNzA4MTMwNDMzNTdaFw0y\r\n" +"MDA2MDIwNDMzNTdaMIGCMQswCQYDVQQGEwJFUzEPMA0GA1UECAwGTWFkcmlkMQ8w\r\n" +"DQYDVQQHDAZNYWRyaWQxDTALBgNVBAoMBEFTUEwxEzARBgNVBAsMClRJIFN1cHBv\r\n" +"cnQxDTALBgNVBAMMBFJvb3QxHjAcBgkqhkiG9w0BCQEWD3NvcG9ydGVAYXNwbC5l\r\n" +"czCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAPKbeM0iCe0u/IaZcDAA\r\n" +"8uWRGgKQZaXLOZmC4i6DaARX93UWyqY/BL5iTgDhW2hEVd+IKHg6gfqT8M4MhZAN\r\n" +"HplrZC+5kB8zBebhsTOy0xlTc7TZUGGN32IlJL7yX6uG0dAezEHiLLwbnszd6LxK\r\n" +"qv9+bI2dXcbpUyPpgSoPwEM+DYmmzaHvJYOjh23P9Qqsb9BxIvQMgQnevo7mKV7+\r\n" +"jem4J6zZURFgoSjqGAKX9DKmU73WUpf+aGByqCYA/c7Mq+Zc0zcMv42Z/GF34iST\r\n" +"8PA98LnhvzsA/XvDJ9Ilw5xuSx/AwX3luyrq/3h9r3XGH4IfPh74i/R253nR5gz1\r\n" +"fRcCAwEAAaNQME4wHQYDVR0OBBYEFO/TotXSWOl7YvpaGlS2fz5SvrJ4MB8GA1Ud\r\n" +"IwQYMBaAFO/TotXSWOl7YvpaGlS2fz5SvrJ4MAwGA1UdEwQFMAMBAf8wDQYJKoZI\r\n" +"hvcNAQELBQADggEBAM1F0Rs8y40qAHxE0NGAbhueoD7FydD12tn1Iwctox958/9k\r\n" +"UKZpHKZLpK7r4o9ysEJm5achMSNjOuVP7E5GeCONvrlIMB0ofW+5ilN23X4cQQpb\r\n" +"6CciICtYN00PR0RhpljvVqssv5m7OZA2ak2+mmTcxki0ZfBpkiID8EFEygPXkOgS\r\n" +"noTZmeh73OhQxHRQmmoqcZMmelcE0Mkygw/MVmdFhwM9kjkQ6agXXeWLJ83ORVCm\r\n" +"5bOt2dFsDvGwb+qo0EedNsBswthPlx66NRHD3+ULwQdNFIlE9MFVezwIWRyI+F+D\r\n" +"+5hCmkR6W8fWKxXLJqR501AsSqJCloKa3EOUCxQ=\r\n" +"-----END CERTIFICATE-----\r\n" +"-----BEGIN RSA PRIVATE KEY-----\r\n" +"MIIEpAIBAAKCAQEA8pt4zSIJ7S78hplwMADy5ZEaApBlpcs5mYLiLoNoBFf3dRbK\r\n" +"pj8EvmJOAOFbaERV34goeDqB+pPwzgyFkA0emWtkL7mQHzMF5uGxM7LTGVNztNlQ\r\n" +"YY3fYiUkvvJfq4bR0B7MQeIsvBuezN3ovEqq/35sjZ1dxulTI+mBKg/AQz4NiabN\r\n" +"oe8lg6OHbc/1Cqxv0HEi9AyBCd6+juYpXv6N6bgnrNlREWChKOoYApf0MqZTvdZS\r\n" +"l/5oYHKoJgD9zsyr5lzTNwy/jZn8YXfiJJPw8D3wueG/OwD9e8Mn0iXDnG5LH8DB\r\n" +"feW7Kur/eH2vdcYfgh8+HviL9HbnedHmDPV9FwIDAQABAoIBAQDO6vtlOhrtSJ3o\r\n" +"zwV4a9a/JbrhZPbNKT+/RnpS4ZDd44kTPJUqpaUOHBobdhnYHDCBrkeWA5DIf1Vq\r\n" +"6BMigY4PnCCe882QTpxCB0xzo5mYiCyvmomMKszTkIp+sYoXaa2ZrCraJmWxKn2O\r\n" +"jdXqgmTF9LXxMr7A4FAg2Q9pKHX64lDcYQKinB6ehuCa5TB/I4KZUdhck7zGYy4o\r\n" +"vaFM57tWo36Cl9VWC/kpwBnzecSIASm/EI+Tro0shybLzdBzbgC4AmMHl/s0sVmy\r\n" +"nh6LbDrLW/HLDyIqreGpkg5WL7sforz62v05BLN3yRNhf4wXJr+yvy9+pl39SA34\r\n" +"TcqW79ABAoGBAPoWc8fF+/qyxnv75WqmjaPqfIyFAzEGin0ftyAGjFPuiBV7qLWf\r\n" +"F5UaKuCPwJKXziAoOpC9eCLnKNa9b4x3lMUoUAQaswePUSKZetjygg165NZcKbaU\r\n" +"VRe7ZomHfoZCMmCuPxDcPGvzkqWILggSUwT706dxP8FKzUT9GMHG/nUBAoGBAPhX\r\n" +"v24Llj5xSFQ9T96tv05ZbDUzJhF/D5KJQPGgze8Y+yPcc0qXwvNDWv2deP956ozD\r\n" +"izPR0BiTif7BLYtGl1QCqVsHH1bXNL41zDoQyd0MYbnvgMtO63JzEnXgjeEPf9MB\r\n" +"URGrzTtybH0QbjjjyOHDYN2ov6ibo4BDqIff1voXAoGAQ5S5qOyZkT+qX2rMritf\r\n" +"70G4coinOiJYXkOpyt+6IBw/bf7CsoHRb5toptJx6atYKlx0pxRsWJI6+PysHjta\r\n" +"WoTwSoukgZB7DmyHRAUUm+vv1vWE2C/xZr5fkR6qVEGjN3ke1cGOGmXx5QWN2uSI\r\n" +"xrn+kisKXYOHQPNcM1FBBgECgYBYTaMktvwCUfd89Jwcur0GV+eQ9xH3MK3R1foA\r\n" +"sMPo24IZGz7nbBUGuJF3EnI+rRQIX1N05orO4k80BW5zUnNmjNe5JUwwba80Xx6y\r\n" +"GtwcPFXXbmDmabZwaJhMz77DIua5mYNA/EyqcaI/ygLXOa9pDza3OlSD2GuHpQcc\r\n" +"4SuomwKBgQCb9TSOwLBvhUQuJeLnKOFJ2BNseYUVMWGq1+Kkg/47UfA/fPH8dk8q\r\n" +"8OuTKucLMi8AiBb9LKlnF87/019E1HReOuUIsrBfgBWwfsZUIypc8lGQHvoBjj1D\r\n" +"G98fdnnfXT6Xs5YwKCGi+DF7ZKq402GsjTa+XByAN95PdxEKqCUQnw==\r\n" +"-----END RSA PRIVATE KEY-----\r\n"; + +static const char g_server_pem[] = +"-----BEGIN CERTIFICATE-----\r\n" +"MIIDkzCCAnsCCQDpTEc56X02UDANBgkqhkiG9w0BAQsFADCBgjELMAkGA1UEBhMC\r\n" +"RVMxDzANBgNVBAgMBk1hZHJpZDEPMA0GA1UEBwwGTWFkcmlkMQ0wCwYDVQQKDARB\r\n" +"U1BMMRMwEQYDVQQLDApUSSBTdXBwb3J0MQ0wCwYDVQQDDARSb290MR4wHAYJKoZI\r\n" +"hvcNAQkBFg9zb3BvcnRlQGFzcGwuZXMwHhcNMTcwODEzMDQzMzU3WhcNMjAwNjAy\r\n" +"MDQzMzU3WjCBkzELMAkGA1UEBhMCRVMxDzANBgNVBAgMBk1hZHJpZDEPMA0GA1UE\r\n" +"BwwGTWFkcmlkMQ0wCwYDVQQKDARBU1BMMRMwEQYDVQQLDApUSSBTdXBwb3J0MR4w\r\n" +"HAYDVQQDDBVzZXJ2ZXIubm9wb2xsLmFzcGwuZXMxHjAcBgkqhkiG9w0BCQEWD3Nv\r\n" +"cG9ydGVAYXNwbC5lczCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALgr\r\n" +"2XCOc1Ee/O8QnMV2aWwqarsQDlEjwtn6uvwz7MWM42iKgPfbA+eJzhdqCmbnwNsJ\r\n" +"K6aC8Xt0P/OjVlC8UNgGk6IcGhceoteyQXVEYF3ccVMDOX37xwAAcVbRIXXA0sAc\r\n" +"H+kXOPnjuJiQyaZa4K/Wv6WFQKVZ5tefg1dcn1TiS/1gbLNhqgGBPEueNH5+S0/2\r\n" +"2LiG9+IN8hA+Xag604d7ryscmhim1JpwHx57jd96a4WiZ744vz/V8rQB3Gx0iwJV\r\n" +"wj+6NEkxvDmDp0N5IFwQNgEqVTZg900w1I1aNVn1tP4kiNtT3mzyrMYjvKTbunOt\r\n" +"UfRvdND3U6y+7VnZG4MCAwEAATANBgkqhkiG9w0BAQsFAAOCAQEAKoxmoX+DNLyA\r\n" +"2Wj/WO/HGY38tQboQYhFUftWLyNxFIXL+BibIPGuPcdKHJI56V+pXRDopdZ4s8Wm\r\n" +"zv+UW2/EjKS1QsGl7C780OzRFFUgOJfRM2WpdvY2DhBpyiKOG3+n9N1Yawk1bWe9\r\n" +"sjL34kcNdSwU48BQsSLhhdqhnXrJOwM6khIHoWcWrDexBD6cYkqzB1vJIuRx/mEy\r\n" +"LzV6vLARttavNljLr9m3jCI4jl/xrVVn1enhoBoR+EaX/NRC25RTnu4NpVNIZsjH\r\n" +"QG7o4N84J5qiLhzSVwsMFaOgZFboEtsIopdn54GuxLPuW8Lj96pQwI7Zn7BcGqqj\r\n" +"epOMHKhd3w==\r\n" +"-----END CERTIFICATE-----\r\n" +"-----BEGIN RSA PRIVATE KEY-----\r\n" +"MIIEpAIBAAKCAQEAuCvZcI5zUR787xCcxXZpbCpquxAOUSPC2fq6/DPsxYzjaIqA\r\n" +"99sD54nOF2oKZufA2wkrpoLxe3Q/86NWULxQ2AaTohwaFx6i17JBdURgXdxxUwM5\r\n" +"ffvHAABxVtEhdcDSwBwf6Rc4+eO4mJDJplrgr9a/pYVApVnm15+DV1yfVOJL/WBs\r\n" +"s2GqAYE8S540fn5LT/bYuIb34g3yED5dqDrTh3uvKxyaGKbUmnAfHnuN33prhaJn\r\n" +"vji/P9XytAHcbHSLAlXCP7o0STG8OYOnQ3kgXBA2ASpVNmD3TTDUjVo1WfW0/iSI\r\n" +"21PebPKsxiO8pNu6c61R9G900PdTrL7tWdkbgwIDAQABAoIBAHl0GWH73xppGB5D\r\n" +"0075Js65LkeMcBScQ7xid/sn9wXUQofHhwNtAKcpnqqcOJ3iSbFo28tkYQGsCRyP\r\n" +"47U8awf7VlK6u43xmywplrdRz0c2v9khsEFfz701jYjWQ32XGqSsJ3Mc6GsK/MpH\r\n" +"+WNmXPQ454utU5N3tR8PR5tOLpjXwItT0QvtbojP58vvvdRAmEbG0m3jSV8vhxuu\r\n" +"7/SRtWZhDk/aHYv47bdwyb8xQYneAjXjF5CINQWKEs6qnZRlvGWiiGgZR+zyoFQ6\r\n" +"H8jN8zYsEnLbII+ODDRkCXkVeEmJ9bZl7fARpYXQoCraYra1Tyk4RkkVYC8hjUji\r\n" +"ruf4LnECgYEA58lvPw/dTs6AXAnQz8A9s4743REvSy2ivR5zFzsPkfcpplMNmhBH\r\n" +"JsolBrRBsFzd1O+Wh8uENFmez7l2mnGlpn/n8dDBzN7Iy9sJ+o9dQhRRQX3mtKr7\r\n" +"80MBmTMxiGCgNk2Zc1/K4Ze8B/1gQlyIWcwj1A/bQEpDBYA/mU9jVkkCgYEAy2kN\r\n" +"7AQKZfRcmFM+SZi8xyr4ulI4Wb7wbrIVIROv9l3ea0jAz1etozt/HOShpj0s3jYm\r\n" +"5nXEGAwu7MOaSKMwRG323KA3+pRHUoyISA4OWeY0dVJbmi3HYT8eqkWFupXwbgBi\r\n" +"x5dFQ0a0EfK9J3THs1Q6mhwF8XWX6ZTWPIoHs2sCgYEAihhjZUkIa5lwtGVMuVop\r\n" +"6L732o4QhVPtL4viuiaAAlElyWiWJAIqwhuRr8rZkD/kEqekIcfJPn9etRgkZ6Pq\r\n" +"M6blBBeCP5NEQuB/s36S63m7Z6+hMmbksWxsmV/81Onsyi21jR23fGywpHn7Tc5f\r\n" +"llCf0AqacFVOVQqx2Z+I6bECgYEAwbueEeNLUA2sPzxRf+EkM4G/Ah6bIwcTkiq0\r\n" +"qxtIJZsD4ySY1yJH88cP6yHqwB1V5ZKn/CnACbNY4hHumS4sI5CkZT+H8XZWc837\r\n" +"Yr1Yd9Ekt3UoX7EoS3vFpiCvHKYAJ5Tgf/6Ybloh2VJbTAASz77yTaNRGceJV2R1\r\n" +"o5VHfl8CgYB3ZZMaMTP7f27CtKFqk5x/nreBPaT0KWe3nI06AO7o0odY5BnkjBxB\r\n" +"tRj/fbqi8CLMcD4shbUr6RSAbf8lsmmiUgsDUYZA7e6wspn4S1f2z9uREGzfUopm\r\n" +"3i20zlGmTOFFr96ny6qx/meiZBvVy7Kl5kWKRM1B6Pu6X4mtxi0hvA==\r\n" +"-----END RSA PRIVATE KEY-----\r\n"; + +static const char g_client_pem[] = +"-----BEGIN CERTIFICATE-----\r\n" +"MIIDkzCCAnsCCQDpTEc56X02UTANBgkqhkiG9w0BAQsFADCBgjELMAkGA1UEBhMC\r\n" +"RVMxDzANBgNVBAgMBk1hZHJpZDEPMA0GA1UEBwwGTWFkcmlkMQ0wCwYDVQQKDARB\r\n" +"U1BMMRMwEQYDVQQLDApUSSBTdXBwb3J0MQ0wCwYDVQQDDARSb290MR4wHAYJKoZI\r\n" +"hvcNAQkBFg9zb3BvcnRlQGFzcGwuZXMwHhcNMTcwODEzMDQzMzU4WhcNMjAwNjAy\r\n" +"MDQzMzU4WjCBkzELMAkGA1UEBhMCRVMxDzANBgNVBAgMBk1hZHJpZDEPMA0GA1UE\r\n" +"BwwGTWFkcmlkMQ0wCwYDVQQKDARBU1BMMRMwEQYDVQQLDApUSSBTdXBwb3J0MR4w\r\n" +"HAYDVQQDDBVjbGllbnQubm9wb2xsLmFzcGwuZXMxHjAcBgkqhkiG9w0BCQEWD3Nv\r\n" +"cG9ydGVAYXNwbC5lczCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALqc\r\n" +"fTM7ADZT3TNLX5dojfpmwh8nxcQjM9/JeC5aPa027hds9js80JlQVeoAcgWNuJjD\r\n" +"V9ISOnAEED6taOrz4cNMRweHbniYUJAC0ADaGJNVjhl7Y1TsQ2v+Ja/Pypj8tSJp\r\n" +"14sKH8qFJz5wm0e8F0x2ZpoMxkhp7G1lFW/3CpjZEcpIwzh0BL6AhngIPgohAmQt\r\n" +"v+SkKhooZhy3aDh87ex1Al4BjQ7z2pckK/mYLKOnZFZS9KRxLC1nB2H+SdwzRd3b\r\n" +"woP5V+OkjdoLFPvPLH+AFlvrYMRj/Rhc5cHSTyqM1DO6sMpCuKOuXClmkjURAXiA\r\n" +"Q7CJTPZs/FurvHbgiSkCAwEAATANBgkqhkiG9w0BAQsFAAOCAQEArXstlNlqZgYx\r\n" +"2qImPdZeKBMGS9ymWcb7Vh3JgqMcERZzwjq5cYiY6+CTL+oAyZ0iWGRqTAUQkuZN\r\n" +"iQ18j5norcGJTTC3hmJqJTDE0P60f/0L84vd/T+nJ9wmwIPcfkK+KcdKlfEdSXNg\r\n" +"dDzLb1nBTyDnb6+uPZIxA3ujO+szSBqD1c7fUh//+DhjAZoUD6EMFixTRmjnD90c\r\n" +"gEemQl++Z/6f1T3XzSiszo/+K1rJISyG/nQ08jo3uH0qBIPhjziNqoZ6LvZ8BAwr\r\n" +"Bvvz7zkPtCWoxEiHq+nhzS4lS6fSiHJ5Zeu9tUeljhbE7Zg0y6T2jqqE22npcYRZ\r\n" +"E2Z//IOQnA==\r\n" +"-----END CERTIFICATE-----\r\n" +"-----BEGIN RSA PRIVATE KEY-----\r\n" +"MIIEpAIBAAKCAQEAupx9MzsANlPdM0tfl2iN+mbCHyfFxCMz38l4Llo9rTbuF2z2\r\n" +"OzzQmVBV6gByBY24mMNX0hI6cAQQPq1o6vPhw0xHB4dueJhQkALQANoYk1WOGXtj\r\n" +"VOxDa/4lr8/KmPy1ImnXiwofyoUnPnCbR7wXTHZmmgzGSGnsbWUVb/cKmNkRykjD\r\n" +"OHQEvoCGeAg+CiECZC2/5KQqGihmHLdoOHzt7HUCXgGNDvPalyQr+Zgso6dkVlL0\r\n" +"pHEsLWcHYf5J3DNF3dvCg/lX46SN2gsU+88sf4AWW+tgxGP9GFzlwdJPKozUM7qw\r\n" +"ykK4o65cKWaSNREBeIBDsIlM9mz8W6u8duCJKQIDAQABAoIBADj34wTLw0HSklnB\r\n" +"bdpEEevaiPKH6sj40jJESAsmg2OovECsg/MLmsbjDodUQXrOjAcew2WfKPXfV7I6\r\n" +"sCfh8g7z708uGhx4q0d7hFJuQkhgOvQuheF8Cw0h1hF5BulzZDywQRvyKEhkI9nc\r\n" +"+JqKojY2gxYORk3/AC1ZSZUXvsVwIWrDzx14y2fiHixwgrudBVD3V+cNXtivGV3N\r\n" +"dEt3Q/taTLUGLm9z0iRu0fY5O4Q7NGt7tBWmeKqd+tSQQf+IZIuv4JSETnnKMBFz\r\n" +"fdG1V379eBt9G60k31DyLwdnNXZ1UXwF8Yiuh3FWoTdF47EIjUvhY3W79eamcxQ0\r\n" +"ZG0OEk0CgYEA5lizFcihcYx2ABSnQaUBfntpEiRJ9aXMugJIxctJtvg/0LPvrMBI\r\n" +"wz/ISjRTNXQfzgvFK2ho9Z9ZCn5gACgg9TajoJXhiEW3YJmv+bQCkwHqvmlfrYhQ\r\n" +"CHskWAcC2wG4Eai4mhrquBZWC0P407FkrIPqXR5VuP0Lnt968YP7xa8CgYEAz2Tg\r\n" +"NoL6hi/BvkjiJEbtx6ysDIxfmxy/c3v8zeTbSnjUa7NfpDlmHZ7foeHJwsTvB9Es\r\n" +"iGhpolfewPyBJTNRaKTO7KG0h9h4ZNOzswUepE+y9sQYXzqWLrVIa59Fd/OD1DjX\r\n" +"tyvRWnE+vlMi2jr90oMoQ6gtxgW8f5OqEs1/rKcCgYEAmt0VgdbCW9HgX4uDK4oh\r\n" +"KAUWjgDhzIpsyr3QaVKUO7RJSyo+P/mCsepG4USukKiC3YdiRx3KOyCnv3tZVaGl\r\n" +"DtduSP+bgn/EmuiYvBt/A5DtXpj/n26eyCTqOVh1XgKY2x6BBfKEzcEOlkJbnw+L\r\n" +"rMR/o51KarWNw4Fiac+fTLcCgYBcBk7W4Vd4o0g8vupZXn+z0hKlnsPtd9wbyjBq\r\n" +"y9niOatH/te5bx64lf51PlLgcbH+rfosrOfyeTsGNwS3FQZSgI6wwS/x90O0uZtL\r\n" +"HEJ0dkja5jhKSRzKrPXti0av6wXb7T0Ksg67KvTETu9wFiz6c+gx3TYyX+k8UrFs\r\n" +"lnLIkQKBgQCLTxcJcf48uBQOBJ3yBZJWI9R/1ZQnaA4BcLj9VuC0iMK0URyV/uc4\r\n" +"hZ7F+/4URAuobYENLFJ6dagHW4JDFlUTdTT+CLqQLzEhglGMXiUIqz31o6QQft1j\r\n" +"lQrSLp9Di/IQhMs2r78NCbHbkopvqCjO186ufJHvE+e3eDefBQZ/BQ==\r\n" +"-----END RSA PRIVATE KEY-----\r\n"; + +#define CMD_NOPOLL_MSG_EXIT (0) +#define CMD_NOPOLL_MSG_OPEN (1) +#define CMD_NOPOLL_MSG_SEND (2) +#define CMD_NOPOLL_MSG_RECV (3) +#define CMD_NOPOLL_MSG_CLOSE (4) + +struct cmd_nopoll_open_data { + uint32_t tls; + uint32_t verify; + uint32_t cer; +}; + +struct cmd_nopoll_send_data { + uint8_t *buf; + uint32_t size; +}; + +struct cmd_nopoll_msg { + uint32_t type; + void *data; +}; + +#define CMD_NOPOLL_QUEUE_WAIT_TIME (5000) +#define CMD_NOPOLL_THREAD_STACK_SIZE (4 * 1024) +static OS_Thread_t g_nopoll_server_thread; +static OS_Thread_t g_nopoll_client_thread; + +static char g_server_host[32] = {0}; +static char g_server_port[8] = {0}; +static noPollCtx *g_server_ctx = NULL; +static noPollConn *g_listener = NULL; +static noPollConnOpts *g_listener_opts = NULL; + +static OS_Queue_t g_client_queue; +static char g_client_host[32] = {0}; +static char g_client_port[8] = {0}; +static noPollCtx *g_client_ctx = NULL; +static noPollConn *g_conn = NULL; +static noPollConnOpts *g_conn_opts = NULL; + +static void cmd_nopoll_server_task(void *arg) +{ + nopoll_loop_wait(g_server_ctx, 0); + + CMD_DBG("%s() end\n", __func__); + OS_ThreadDelete(&g_nopoll_server_thread); +} + +static void cmd_nopoll_server_on_close(noPollCtx *ctx, noPollConn *conn, noPollPtr user_data) +{ + CMD_LOG(1, "called connection close\n"); +} + +static nopoll_bool cmd_nopoll_server_on_open(noPollCtx *ctx, noPollConn *conn, noPollPtr user_data) +{ + CMD_LOG(1, "called connection open\n"); + + nopoll_conn_set_on_close(conn, cmd_nopoll_server_on_close, NULL); + + if (!nopoll_conn_set_sock_block(nopoll_conn_socket(conn), nopoll_false)) { + CMD_ERR("ERROR: failed to configure non-blocking state to connection..\n"); + return nopoll_false; + } + + return nopoll_true; +} + +static void cmd_nopoll_server_on_message(noPollCtx *ctx, noPollConn *conn, noPollMsg *msg, noPollPtr user_data) +{ + int size = nopoll_msg_get_payload_size(msg); + const char *content = (const char *)nopoll_msg_get_payload(msg); + + CMD_LOG(1, "server receive message:\n"); + CMD_LOG(1, "%s\n", content); + + nopoll_conn_send_text(conn, content, size); + + if (nopoll_cmp(content, "nopoll test stop running")) { + nopoll_loop_stop(g_server_ctx); + } +} + +static enum cmd_status cmd_nopoll_server_init_exec(char *cmd) +{ + int cnt; + uint32_t dbg; + + cnt = cmd_sscanf(cmd, "d=%u", &dbg); + if (cnt != 1) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (g_server_ctx != NULL) { + CMD_ERR("already init\n"); + return CMD_STATUS_FAIL; + } + + g_server_ctx = nopoll_ctx_new(); + if (g_server_ctx == NULL) { + CMD_ERR("nopoll_ctx_new failed\n"); + return CMD_STATUS_FAIL; + } + + if (dbg == 0) + nopoll_log_enable(g_server_ctx, nopoll_false); + else + nopoll_log_enable(g_server_ctx, nopoll_true); + + /* set on open */ + nopoll_ctx_set_on_open(g_server_ctx, cmd_nopoll_server_on_open, NULL); + + /* set on message received */ + nopoll_ctx_set_on_msg(g_server_ctx, cmd_nopoll_server_on_message, NULL); + + OS_ThreadSetInvalid(&g_nopoll_server_thread); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_server_open_exec(char *cmd) +{ + int cnt; + uint32_t tls; + uint32_t verify; + + cnt = cmd_sscanf(cmd, "h=%s p=%s t=%u v=%u", g_server_host, g_server_port, &tls, &verify); + if (cnt != 4) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (g_server_ctx == NULL) { + CMD_ERR("without init\n"); + return CMD_STATUS_FAIL; + } + + if ((g_listener != NULL) || (g_listener_opts != NULL)) { + CMD_ERR("already open\n"); + return CMD_STATUS_FAIL; + } + + g_listener_opts = nopoll_conn_opts_new(); + if (g_listener_opts == NULL) { + CMD_ERR("nopoll_conn_opts_new failed\n"); + return CMD_STATUS_FAIL; + } + + if (tls == 0) + g_listener = nopoll_listener_new_opts(g_server_ctx, g_listener_opts, g_server_host, g_server_port); + else { + if (!nopoll_conn_opts_set_ssl_certs(g_listener_opts, + g_server_pem, sizeof(g_server_pem), + g_server_pem, sizeof(g_server_pem), + NULL, 0, + g_root_pem, sizeof(g_root_pem))) { + CMD_ERR("nopoll_conn_opts_set_ssl_certs failed\n"); + nopoll_conn_opts_free(g_listener_opts); + g_listener_opts = NULL; + return CMD_STATUS_FAIL; + } + + if (verify == 0) + nopoll_conn_opts_ssl_peer_verify (g_listener_opts, nopoll_false); + else + nopoll_conn_opts_ssl_peer_verify (g_listener_opts, nopoll_true); + + g_listener = nopoll_listener_tls_new_opts(g_server_ctx, g_listener_opts, g_server_host, g_server_port); + } + + if (g_listener == NULL) { + CMD_ERR("nopoll_listener(_tls)_new_opts failed\n"); + nopoll_conn_opts_free(g_listener_opts); + g_listener_opts = NULL; + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_server_start_exec(char *cmd) +{ + if ((g_listener == NULL) || (g_listener_opts == NULL)) { + CMD_ERR("without open\n"); + return CMD_STATUS_FAIL; + } + + if (OS_ThreadIsValid(&g_nopoll_server_thread)) { + CMD_ERR("already start\n"); + return CMD_STATUS_FAIL; + } + + if (OS_ThreadCreate(&g_nopoll_server_thread, + "nopoll test server", + cmd_nopoll_server_task, + NULL, + OS_THREAD_PRIO_CONSOLE, + CMD_NOPOLL_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("thread create failed\n"); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_server_stop_exec(char *cmd) +{ + if (!OS_ThreadIsValid(&g_nopoll_server_thread)) { + CMD_ERR("without start\n"); + return CMD_STATUS_FAIL; + } + + nopoll_loop_stop(g_server_ctx); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_server_close_exec(char *cmd) +{ + if ((g_listener == NULL) || (g_listener_opts == NULL)) { + CMD_ERR("without open\n"); + return CMD_STATUS_FAIL; + } + + if (OS_ThreadIsValid(&g_nopoll_server_thread)) { + CMD_ERR("without stop\n"); + return CMD_STATUS_FAIL; + } + + nopoll_conn_close(g_listener); + g_listener = NULL; + g_listener_opts = NULL; + + cmd_memset(g_server_host, 0, sizeof(g_server_host)); + cmd_memset(g_server_port, 0, sizeof(g_server_port)); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_server_deinit_exec(char *cmd) +{ + if (g_server_ctx == NULL) { + CMD_ERR("without init\n"); + return CMD_STATUS_FAIL; + } + + nopoll_ctx_unref(g_server_ctx); + nopoll_cleanup_library(); + g_server_ctx = NULL; + + return CMD_STATUS_OK; +} + +static void cmd_nopoll_client_open_task(struct cmd_nopoll_open_data *data) +{ + g_conn_opts = nopoll_conn_opts_new(); + if (g_conn_opts == NULL) { + CMD_ERR("nopoll_conn_opts_new failed\n"); + goto open_task_exit; + } + + if (data->tls == 0) + g_conn = nopoll_conn_new_opts(g_client_ctx, g_conn_opts, g_client_host, g_client_port, NULL, NULL, NULL, NULL); + else { + if (data->cer != 0) { + if (!nopoll_conn_opts_set_ssl_certs(g_conn_opts, + g_client_pem, sizeof(g_client_pem), + g_client_pem, sizeof(g_client_pem), + NULL, 0, + g_root_pem, sizeof(g_root_pem))) { + CMD_ERR("nopoll_conn_opts_set_ssl_certs failed\n"); + nopoll_conn_opts_free(g_conn_opts); + g_conn_opts = NULL; + goto open_task_exit; + } + } + + if (data->verify == 0) + nopoll_conn_opts_ssl_peer_verify (g_conn_opts, nopoll_false); + else + nopoll_conn_opts_ssl_peer_verify (g_conn_opts, nopoll_true); + + g_conn = nopoll_conn_tls_new(g_client_ctx, g_conn_opts, g_client_host, g_client_port, NULL, NULL, NULL, NULL); + } + + if (g_conn == NULL) { + CMD_ERR("nopoll_conn(_tls)_new(_opts) failed\n"); + goto open_task_exit; + } + + if (nopoll_conn_wait_until_connection_ready(g_conn, 10)) + CMD_LOG(1, "the connection is ready\n"); + else + CMD_ERR("connection timeout\n"); + +open_task_exit: + cmd_free(data); + data = NULL; + return; +} + +static void cmd_nopoll_client_send_task(struct cmd_nopoll_send_data *data) +{ + int ret = nopoll_conn_send_text(g_conn, (char *)data->buf, data->size); + if (ret != (int)data->size) + CMD_ERR("size = %u, but nopoll_conn_send_text ret = %d\n", data->size, ret); + + cmd_free(data->buf); + data->buf = NULL; + cmd_free(data); + data = NULL; + return; +} + +static void cmd_nopoll_client_recv_task(void *data) +{ + uint32_t msec = 10 * 1000; + noPollMsg *msg; + const char *content; + + while ((msg = nopoll_conn_get_msg(g_conn)) == NULL) { + if (!nopoll_conn_is_ok(g_conn)) { + CMD_ERR("received websocket connection close\n"); + return; + } + + if (msec == 0) { + CMD_ERR("get message timeout\n"); + return; + } + + nopoll_sleep(100000); + msec -= 100; + } + + content = (const char *)nopoll_msg_get_payload(msg); + CMD_LOG(1, "receive message:\n"); + CMD_LOG(1, "%s\n", content); + + nopoll_msg_unref (msg); + return; +} + +static void cmd_nopoll_client_close_task(void *data) +{ + nopoll_conn_close(g_conn); + g_conn = NULL; + g_conn_opts = NULL; + + cmd_memset(g_client_host, 0, sizeof(g_client_host)); + cmd_memset(g_client_port, 0, sizeof(g_client_port)); + + return; +} + +static void cmd_nopoll_client_task(void *arg) +{ + uint8_t task_exit = 0; + struct cmd_nopoll_msg *msg; + + while (task_exit == 0) { + + if (OS_MsgQueueReceive(&g_client_queue, (void **)&msg, OS_WAIT_FOREVER) != OS_OK) { + CMD_ERR("msg queue receive failed\n"); + break; + } + + CMD_DBG("recv msg type %u\n", msg->type); + + switch (msg->type) { + case CMD_NOPOLL_MSG_EXIT: + task_exit = 1; + break; + case CMD_NOPOLL_MSG_OPEN: + cmd_nopoll_client_open_task(msg->data); + break; + case CMD_NOPOLL_MSG_SEND: + cmd_nopoll_client_send_task(msg->data); + break; + case CMD_NOPOLL_MSG_RECV: + cmd_nopoll_client_recv_task(msg->data); + break; + case CMD_NOPOLL_MSG_CLOSE: + cmd_nopoll_client_close_task(msg->data); + break; + default: + CMD_WRN("unknown msg\n"); + break; + } + + cmd_free(msg); + msg = NULL; + } + + CMD_DBG("%s() end\n", __func__); + OS_ThreadDelete(&g_nopoll_client_thread); +} + +static enum cmd_status cmd_nopoll_client_init_exec(char *cmd) +{ + int cnt; + uint32_t dbg; + + cnt = cmd_sscanf(cmd, "d=%u", &dbg); + if (cnt != 1) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (g_client_ctx != NULL) { + CMD_ERR("already init\n"); + return CMD_STATUS_FAIL; + } + + g_client_ctx = nopoll_ctx_new(); + if (g_client_ctx == NULL) { + CMD_ERR("nopoll_ctx_new failed\n"); + return CMD_STATUS_FAIL; + } + + if (dbg == 0) + nopoll_log_enable(g_client_ctx, nopoll_false); + else + nopoll_log_enable(g_client_ctx, nopoll_true); + + OS_ThreadSetInvalid(&g_nopoll_client_thread); + + if (OS_MsgQueueCreate(&g_client_queue, 1) != OS_OK) { + CMD_ERR("msg queue create failed\n"); + return CMD_STATUS_FAIL; + } + + if (OS_ThreadCreate(&g_nopoll_client_thread, + "nopoll test client", + cmd_nopoll_client_task, + NULL, + OS_THREAD_PRIO_CONSOLE, + CMD_NOPOLL_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("thread create failed\n"); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_client_open_exec(char *cmd) +{ + int cnt; + uint32_t tls; + uint32_t verify; + uint32_t cer; + struct cmd_nopoll_open_data *data; + struct cmd_nopoll_msg *msg; + + cnt = cmd_sscanf(cmd, "h=%s p=%s t=%u v=%u c=%u", g_client_host, g_client_port, &tls, &verify, &cer); + if (cnt != 5) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (g_client_ctx == NULL) { + CMD_ERR("without init\n"); + return CMD_STATUS_FAIL; + } + + if ((g_conn != NULL) || (g_conn_opts != NULL)) { + CMD_ERR("already open\n"); + return CMD_STATUS_FAIL; + } + + msg = cmd_malloc(sizeof(struct cmd_nopoll_msg)); + data = cmd_malloc(sizeof(struct cmd_nopoll_open_data)); + if ((msg == NULL) || (data == NULL)) { + CMD_ERR("malloc failed\n"); + if (msg) + cmd_free(msg); + if (data) + cmd_free(data); + return CMD_STATUS_FAIL; + } + + data->tls = tls; + data->verify = verify; + data->cer = cer; + + msg->type = CMD_NOPOLL_MSG_OPEN; + msg->data = data; + + if (OS_MsgQueueSend(&g_client_queue, msg, CMD_NOPOLL_QUEUE_WAIT_TIME) != OS_OK) { + CMD_ERR("msg queue send failed\n"); + if (msg) + cmd_free(msg); + if (data) + cmd_free(data); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_client_send_exec(char *cmd) +{ + int cnt; + int ret; + uint32_t size; + uint8_t *buf; + struct cmd_nopoll_send_data *data; + struct cmd_nopoll_msg *msg; + + cnt = cmd_sscanf(cmd, "s=%u", &size); + if (cnt != 1) { + CMD_ERR("cmd_sscanf return: cnt = %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (size == 0) { + CMD_ERR("size = 0\n"); + return CMD_STATUS_INVALID_ARG; + } + + if ((g_conn == NULL) || (g_conn_opts == NULL)) { + CMD_ERR("without open\n"); + return CMD_STATUS_FAIL; + } + + msg = cmd_malloc(sizeof(struct cmd_nopoll_msg)); + data = cmd_malloc(sizeof(struct cmd_nopoll_send_data)); + buf = cmd_malloc(size); + if ((msg == NULL) || (data == NULL) || (buf == NULL)) { + CMD_ERR("malloc failed\n"); + if (msg) + cmd_free(msg); + if (data) + cmd_free(data); + if (buf) + cmd_free(buf); + return CMD_STATUS_FAIL; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + cmd_raw_mode_enable(); + ret = cmd_raw_mode_read(buf, size, 10000); + if (ret != (int)size) { + CMD_ERR("size = %u, but cmd_raw_mode_read ret = %d\n", size, ret); + cmd_free(msg); + cmd_free(data); + cmd_free(buf); + cmd_raw_mode_write((uint8_t *)"FAIL\n", 5); + cmd_raw_mode_disable(); + return CMD_STATUS_ACKED; + } + cmd_raw_mode_disable(); + + data->buf = buf; + data->size = size; + + msg->type = CMD_NOPOLL_MSG_SEND; + msg->data = data; + + if (OS_MsgQueueSend(&g_client_queue, msg, CMD_NOPOLL_QUEUE_WAIT_TIME) != OS_OK) { + CMD_ERR("msg queue send failed\n"); + if (msg) + cmd_free(msg); + if (data) + cmd_free(data); + if (buf) + cmd_free(buf); + return CMD_STATUS_ACKED; + } + + return CMD_STATUS_ACKED; +} + +static enum cmd_status cmd_nopoll_client_recv_exec(char *cmd) +{ + struct cmd_nopoll_msg *msg; + + if ((g_conn == NULL) || (g_conn_opts == NULL)) { + CMD_ERR("without open\n"); + return CMD_STATUS_FAIL; + } + + msg = cmd_malloc(sizeof(struct cmd_nopoll_msg)); + if (msg == NULL) { + CMD_ERR("msg queue send failed\n"); + return CMD_STATUS_FAIL; + } + + msg->type = CMD_NOPOLL_MSG_RECV; + msg->data = NULL; + + if (OS_MsgQueueSend(&g_client_queue, msg, CMD_NOPOLL_QUEUE_WAIT_TIME) != OS_OK) { + CMD_ERR("msg queue send failed\n"); + if (msg) + cmd_free(msg); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_client_close_exec(char *cmd) +{ + struct cmd_nopoll_msg *msg; + + if ((g_conn == NULL) || (g_conn_opts == NULL)) { + CMD_ERR("without open\n"); + return CMD_STATUS_FAIL; + } + + msg = cmd_malloc(sizeof(struct cmd_nopoll_msg)); + if (msg == NULL) { + CMD_ERR("msg queue send failed\n"); + return CMD_STATUS_FAIL; + } + + msg->type = CMD_NOPOLL_MSG_CLOSE; + msg->data = NULL; + + if (OS_MsgQueueSend(&g_client_queue, msg, CMD_NOPOLL_QUEUE_WAIT_TIME) != OS_OK) { + CMD_ERR("msg queue send failed\n"); + if (msg) + cmd_free(msg); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_nopoll_client_deinit_exec(char *cmd) +{ + struct cmd_nopoll_msg *msg; + + if (g_client_ctx == NULL) { + CMD_ERR("without init\n"); + return CMD_STATUS_FAIL; + } + + nopoll_ctx_unref(g_client_ctx); + g_client_ctx = NULL; + + msg = cmd_malloc(sizeof(struct cmd_nopoll_msg)); + if (msg == NULL) { + CMD_ERR("msg queue send failed\n"); + return CMD_STATUS_FAIL; + } + + msg->type = CMD_NOPOLL_MSG_EXIT; + msg->data = NULL; + + if (OS_MsgQueueSend(&g_client_queue, msg, CMD_NOPOLL_QUEUE_WAIT_TIME) != OS_OK) { + CMD_ERR("msg queue send failed\n"); + if (msg) + cmd_free(msg); + return CMD_STATUS_FAIL; + } + + OS_MSleep(100); + + if (OS_MsgQueueDelete(&g_client_queue) != OS_OK) { + CMD_ERR("msg queue delete failed\n"); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +static struct cmd_data g_nopoll_server_cmds[] = { + { "init", cmd_nopoll_server_init_exec }, + { "open", cmd_nopoll_server_open_exec }, + { "start", cmd_nopoll_server_start_exec }, + { "stop", cmd_nopoll_server_stop_exec }, + { "close", cmd_nopoll_server_close_exec }, + { "deinit", cmd_nopoll_server_deinit_exec }, +}; + +static struct cmd_data g_nopoll_client_cmds[] = { + { "init", cmd_nopoll_client_init_exec }, + { "open", cmd_nopoll_client_open_exec }, + { "send", cmd_nopoll_client_send_exec }, + { "recv", cmd_nopoll_client_recv_exec }, + { "close", cmd_nopoll_client_close_exec }, + { "deinit", cmd_nopoll_client_deinit_exec }, +}; + +static enum cmd_status cmd_nopoll_server_exec(char *cmd) +{ + return cmd_exec(cmd, g_nopoll_server_cmds, cmd_nitems(g_nopoll_server_cmds)); +} + +static enum cmd_status cmd_nopoll_client_exec(char *cmd) +{ + return cmd_exec(cmd, g_nopoll_client_cmds, cmd_nitems(g_nopoll_client_cmds)); +} + +static struct cmd_data g_nopoll_cmds[] = { + { "srv", cmd_nopoll_server_exec }, + { "cli", cmd_nopoll_client_exec }, +}; + +enum cmd_status cmd_nopoll_exec(char *cmd) +{ + return cmd_exec(cmd, g_nopoll_cmds, cmd_nitems(g_nopoll_cmds)); +} + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_nopoll.h b/platform/mcu/xr871/project/common/cmd/cmd_nopoll.h new file mode 100644 index 0000000000..b32f2dba3a --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_nopoll.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_NOPOLL_H_ +#define _CMD_NOPOLL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_nopoll_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_NOPOLL_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ota.c b/platform/mcu/xr871/project/common/cmd/cmd_ota.c new file mode 100644 index 0000000000..5db6cb72d6 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ota.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "sys/ota.h" + +/* + * ota file + * ota http + */ + +enum cmd_status cmd_ota_file_exec(char *cmd) +{ + if (cmd[0] == '\0') { + CMD_ERR("OTA empty file url\n"); + return CMD_STATUS_INVALID_ARG; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + if (ota_get_image(OTA_PROTOCOL_FILE, cmd) != OTA_STATUS_OK) { + CMD_ERR("OTA file get image failed\n"); + return CMD_STATUS_ACKED; + } + + if (ota_verify_image(OTA_VERIFY_NONE, NULL) != OTA_STATUS_OK) { + CMD_ERR("OTA file verify image failed\n"); + return CMD_STATUS_ACKED; + } + + ota_reboot(); + + return CMD_STATUS_ACKED; +} + +enum cmd_status cmd_ota_http_exec(char *cmd) +{ + if (cmd[0] == '\0') { + CMD_ERR("OTA empty http url\n"); + return CMD_STATUS_INVALID_ARG; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + if (ota_get_image(OTA_PROTOCOL_HTTP, cmd) != OTA_STATUS_OK) { + CMD_ERR("OTA http get image failed\n"); + return CMD_STATUS_ACKED; + } + + if (ota_verify_image(OTA_VERIFY_NONE, NULL) != OTA_STATUS_OK) { + CMD_ERR("OTA http verify image failed\n"); + return CMD_STATUS_ACKED; + } + + ota_reboot(); + + return CMD_STATUS_ACKED; +} + +static struct cmd_data g_ota_cmds[] = { + { "file", cmd_ota_file_exec}, + { "http", cmd_ota_http_exec}, +}; + +enum cmd_status cmd_ota_exec(char *cmd) +{ + return cmd_exec(cmd, g_ota_cmds, cmd_nitems(g_ota_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ota.h b/platform/mcu/xr871/project/common/cmd/cmd_ota.h new file mode 100644 index 0000000000..cefed2de55 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ota.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_OTA_H_ +#define _CMD_OTA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_ota_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_OTA_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ping.c b/platform/mcu/xr871/project/common/cmd/cmd_ping.c new file mode 100644 index 0000000000..0c166e53d0 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ping.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_ping.h" +#include "lwip/netdb.h" +#include "net/ping/ping.h" + +struct ping_data pdata; +static OS_Thread_t g_ping_thread; +#define PING_THREAD_STACK_SIZE (1 * 1024) +#define PING_THREAD_EXIT OS_ThreadDelete + +void ping_run(void *arg) +{ + struct ping_data *data = (struct ping_data *)arg; + ping(data); + PING_THREAD_EXIT(&g_ping_thread); + +} + +int ping_start(struct ping_data *data) +{ + if (OS_ThreadIsValid(&g_ping_thread)) { + CMD_ERR("PING task is running\n"); + return -1; + } + + if (OS_ThreadCreate(&g_ping_thread, + "", + ping_run, + (void *)data, + OS_THREAD_PRIO_APP, + PING_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("PING task create failed\n"); + return -1; + } + + return 0; +} + +int ping_get_host_by_name(char *name, unsigned int *address) +{ + struct hostent *host_entry; + + host_entry = gethostbyname(name); + if(host_entry) { + *(address) = *((u_long*)host_entry->h_addr_list[0]); + return 0; // OK + } else { + return 1; // Error + } +} + +enum cmd_status cmd_ping_exec(char *cmd) +{ + int argc; + char *argv[3]; + //struct ping_data pdata; + memset((void*) &pdata, 0, sizeof(pdata)); + + argc = cmd_parse_argv(cmd, argv, 3); + if (argc < 1 || argc > 2) { + CMD_ERR("invalid ping cmd, argc %d\n", argc); + return CMD_STATUS_INVALID_ARG; + } + unsigned int address = 0; + + if (ping_get_host_by_name(argv[0], &address) != 0) { + CMD_ERR("invalid ping host.\n"); + return CMD_STATUS_INVALID_ARG; + } + + pdata.sin_addr.addr = address; + if (argc > 1) + pdata.count = atoi(argv[1]); + else + pdata.count = 3; + + if (ping_start(&pdata) == 0) + return CMD_STATUS_OK; + else + return CMD_STATUS_FAIL; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_ping.h b/platform/mcu/xr871/project/common/cmd/cmd_ping.h new file mode 100644 index 0000000000..4f091c0632 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_ping.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_PING_H_ +#define _CMD_PING_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_ping_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_PING_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_pm.c b/platform/mcu/xr871/project/common/cmd/cmd_pm.c new file mode 100644 index 0000000000..082423e8b3 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_pm.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_pm.h" +#include "pm/pm.h" +#include "driver/chip/hal_wakeup.h" + +#ifdef CONFIG_PM +/* pm config l= d= + * : TEST_NONE ~ TEST_DEVICES. + * : based on ms. + */ +static enum cmd_status cmd_pm_config_exec(char *cmd) +{ + int32_t cnt; + uint32_t level, delayms; + + cnt = cmd_sscanf(cmd, "l=%d d=%d", &level, &delayms); + if (cnt != 2 || level > __TEST_AFTER_LAST || delayms > 100) { + CMD_ERR("err cmd:%s, expect: l= d=\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + pm_set_test_level(level); + pm_set_debug_delay_ms(delayms); + + return CMD_STATUS_OK; +} + +/* pm wk_timer + * : seconds. + */ +static enum cmd_status cmd_pm_wakeuptimer_exec(char *cmd) +{ + int32_t cnt; + uint32_t wakeup_time; + + cnt = cmd_sscanf(cmd, "%d", &wakeup_time); + if (cnt != 1 || wakeup_time < 1) { + CMD_ERR("err cmd:%s, expect: \n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + HAL_Wakeup_SetTimer_mS(wakeup_time * 1000); + + return CMD_STATUS_OK; +} + +/* pm wk_io p= m= + * : 0 ~ 9 + * : 0: negative edge, 1: positive edge, 2: disable this port as wakeup io. + */ +static enum cmd_status cmd_pm_wakeupio_exec(char *cmd) +{ + int32_t cnt; + uint32_t io_num, mode; + + cnt = cmd_sscanf(cmd, "p=%d m=%d", &io_num, &mode); + if (cnt != 2 || io_num > 9 || mode > 2) { + CMD_ERR("err cmd:%s, expect: p= m=\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + if (mode < 2) { + HAL_Wakeup_SetIO(io_num, mode); + } else { + HAL_Wakeup_ClrIO(io_num); + } + + return CMD_STATUS_OK; +} + +/* pm wk_event + */ +static enum cmd_status cmd_pm_wakeupevent_exec(char *cmd) +{ + uint32_t event; + + event = HAL_Wakeup_GetEvent(); + CMD_LOG(1, "wakeup event:%x\n", event); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_pm_sleep_exec(char *cmd) +{ + pm_enter_mode(PM_MODE_SLEEP); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_pm_standby_exec(char *cmd) +{ + pm_enter_mode(PM_MODE_STANDBY); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_pm_hibernation_exec(char *cmd) +{ + pm_enter_mode(PM_MODE_HIBERNATION); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_pm_poweroff_exec(char *cmd) +{ + pm_enter_mode(PM_MODE_POWEROFF); + + return CMD_STATUS_OK; +} + +static struct cmd_data g_pm_cmds[] = { + { "config", cmd_pm_config_exec }, + { "wk_timer", cmd_pm_wakeuptimer_exec }, + { "wk_io", cmd_pm_wakeupio_exec }, + { "wk_event", cmd_pm_wakeupevent_exec }, + { "sleep", cmd_pm_sleep_exec }, + { "standby", cmd_pm_standby_exec }, + { "hibernation", cmd_pm_hibernation_exec }, + { "poweroff", cmd_pm_poweroff_exec }, + { "shutdown", cmd_pm_poweroff_exec }, +}; + +enum cmd_status cmd_pm_exec(char *cmd) +{ + return cmd_exec(cmd, g_pm_cmds, cmd_nitems(g_pm_cmds)); +} +#else /* CONFIG_PM */ +enum cmd_status cmd_pm_exec(char *cmd) +{ + return CMD_STATUS_FAIL; +} +#endif /* CONFIG_PM */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_pm.h b/platform/mcu/xr871/project/common/cmd/cmd_pm.h new file mode 100644 index 0000000000..4e9ccf9b61 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_pm.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_PM_H_ +#define _CMD_PM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_pm_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_PM_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_pwm.c b/platform/mcu/xr871/project/common/cmd/cmd_pwm.c new file mode 100644 index 0000000000..116b841fc4 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_pwm.c @@ -0,0 +1,704 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_pwm.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_pwm.h" + +typedef enum { + PWM_COMPLE, + PWM_PLUSE, + PWM_CYCLE, + PWM_CAPTURE, + PWM_DEADZONE, + PWM_MODENUM, +}Cmd_PwmMode; + +typedef struct { + uint32_t high_time; + uint32_t low_time; + uint16_t num; + uint16_t count; + uint8_t d_value; + uint8_t d_hz; + uint8_t input_ch; +} Cmd_Capinfo; + +static Cmd_Capinfo private_cap[8]; + +static Cmd_PwmMode cmd_pwm_mode_analytic(char *data) +{ + if (cmd_strcmp(data, "comple") == 0) { + return PWM_COMPLE; + } else if (cmd_strcmp(data, "pluse") == 0) { + return PWM_PLUSE; + } else if (cmd_strcmp(data, "cycle") == 0) { + return PWM_CYCLE; + } else if (cmd_strcmp(data, "capture") == 0) { + return PWM_CAPTURE; + } else if (cmd_strcmp(data, "deadzone") == 0) { + return PWM_DEADZONE; + } + return PWM_MODENUM; +} + +typedef struct { + PWM_GROUP_ID group; + PWM_CH_ID ch; +}PWM_IoInfo; + +static int cmd_pwm_init(Cmd_PwmMode mode, PWM_IoInfo info, uint32_t hz) +{ + HAL_Status ret = HAL_ERROR; + PWM_ClkParam clk_cfg; + PWM_CompInitParam comp_cfg; + PWM_ChInitParam ch_cfg; + int cycle = 0; + + clk_cfg.clk = PWM_CLK_HOSC; + clk_cfg.div = PWM_SRC_CLK_DIV_1; + + ret = HAL_PWM_GroupClkCfg(info.group, &clk_cfg); + if (ret != HAL_OK) + return -1; + + switch(mode) { + case PWM_COMPLE: + comp_cfg.hz = hz; + comp_cfg.polarity = PWM_HIGHLEVE; + + cycle = HAL_PWM_ComplementaryInit(info.group, &comp_cfg); + if (cycle == -1) + return -1; + + ret = HAL_PWM_ComplementarySetDutyRatio(info.group, cycle / 4); + if (ret != HAL_OK) + return -1; + + break; + case PWM_CYCLE: + ch_cfg.hz = hz; + ch_cfg.mode = PWM_CYCLE_MODE; + ch_cfg.polarity = PWM_HIGHLEVE; + + cycle = HAL_PWM_ChInit(info.ch, &ch_cfg); + if (cycle == -1) + return -1; + + ret = HAL_PWM_ChSetDutyRatio(info.ch, cycle / 2); + if (ret != HAL_OK) + return -1; + + break; + case PWM_PLUSE: + ch_cfg.hz = hz; + ch_cfg.mode = PWM_PLUSE_MODE; + ch_cfg.polarity = PWM_HIGHLEVE; + + cycle = HAL_PWM_ChInit(info.ch, &ch_cfg); + if (cycle == -1) + return -1; + break; + case PWM_CAPTURE: + ch_cfg.hz = hz; + ch_cfg.mode = PWM_CAPTURE_MODE; + ch_cfg.polarity = PWM_HIGHLEVE; + + cycle = HAL_PWM_ChInit(info.ch, &ch_cfg); + if (cycle == -1) + return -1; + + break; + default : + CMD_DBG("invalid PWM mode\n"); + return -1; + } + return 0; +} + +static PWM_IoInfo cmd_pwm_channel_analytic(Cmd_PwmMode mode, uint32_t channel) +{ + PWM_IoInfo info; + if (mode == PWM_COMPLE || mode == PWM_DEADZONE) { + if (channel > 3) { + info.ch = PWM_CH_NULL; + info.group = PWM_GROUP_NULL; + return info; + } + info.group = channel; + info.ch = PWM_CH_NULL; + return info; + } else if (channel > 7) { + info.ch = PWM_CH_NULL; + info.group = PWM_GROUP_NULL; + return info; + } + + info.ch = channel; + info.group = channel / 2; + + return info; +} + +static enum cmd_status cmd_pwm_config_exec(char *cmd) +{ + uint32_t hz; + uint32_t channel; + char mode_char[8]; + int cnt; + + cnt = cmd_sscanf(cmd, "c=%u m=%s h=%u", &channel, mode_char, &hz); + + if (cnt != 3) { + return CMD_STATUS_INVALID_ARG; + } + + Cmd_PwmMode mode = cmd_pwm_mode_analytic(mode_char); + if (mode >= PWM_MODENUM) { + CMD_ERR("invalid pwm mode %u\n", mode); + return CMD_STATUS_INVALID_ARG; + } + if (hz < 2 || hz > 240000) { + CMD_ERR("pwm hz out of range %u\n", hz); + return CMD_STATUS_FAIL; + } + + PWM_IoInfo info = cmd_pwm_channel_analytic(mode, channel); + + if (info.group >= PWM_GROUP_NULL) + return CMD_STATUS_INVALID_ARG; + + if (cmd_pwm_init(mode, info, hz) == -1) + return CMD_STATUS_FAIL; + + return CMD_STATUS_OK; +} + +enum cmd_status cmd_pwm_deinit_exec(char *cmd) +{ + int cnt = 0; + uint32_t channel; + char mode_char[8]; + HAL_Status ret = HAL_ERROR; + + cnt = cmd_sscanf(cmd, "c=%u m=%s", &channel, mode_char); + if (cnt != 2) + return CMD_STATUS_INVALID_ARG; + + Cmd_PwmMode mode = cmd_pwm_mode_analytic(mode_char); + if (mode >= PWM_MODENUM) { + CMD_ERR("invalid pwm mode %u\n", mode); + return CMD_STATUS_INVALID_ARG; + } + + PWM_IoInfo info = cmd_pwm_channel_analytic(mode, channel); + if (info.group == PWM_GROUP_NULL) { + CMD_ERR("invalid pwm channel\n"); + return CMD_STATUS_INVALID_ARG; + } + + if (mode == PWM_COMPLE) { + ret = HAL_PWM_ComplementaryDeInit(info.group); + if (ret != HAL_OK) + return CMD_STATUS_FAIL; + } else { + ret = HAL_PWM_ChDeinit(info.ch); + if (ret != HAL_OK) + return CMD_STATUS_FAIL; + } + return CMD_STATUS_OK; +} + +enum cmd_status cmd_pwm_start_exec(char *cmd) +{ + HAL_Status ret; + char mode_char[8]; + uint32_t channel; + int cnt; + PWM_IrqParam irq_cfg; + + cnt = cmd_sscanf(cmd, "c=%u m=%s", &channel, mode_char); + if (cnt != 2) + return CMD_STATUS_INVALID_ARG; + + Cmd_PwmMode mode = cmd_pwm_mode_analytic(mode_char); + if (mode >= PWM_MODENUM) { + CMD_ERR("invalid pwm mode %u\n", mode); + return CMD_STATUS_INVALID_ARG; + } + + PWM_IoInfo info = cmd_pwm_channel_analytic(mode, channel); + if (info.group == PWM_GROUP_NULL) { + CMD_DBG("invalid pwm channel\n"); + return CMD_STATUS_INVALID_ARG; + } + + switch (mode) { + case PWM_COMPLE: + ret = HAL_PWM_EnableComplementary(info.group, 1); + if (ret != HAL_OK) { + CMD_ERR("Enable comple error\n"); + return CMD_STATUS_FAIL; + } + break; + case PWM_PLUSE: + ret = HAL_PWM_EnableCh(info.ch, PWM_PLUSE_MODE, 1); + if (ret != HAL_OK) { + CMD_ERR("Enable channel error\n"); + return CMD_STATUS_FAIL; + } + + ret = HAL_PWM_OutputPluse(info.ch); + if (ret != HAL_OK) { + CMD_ERR("start pluse fail, it's busy\n"); + return CMD_STATUS_FAIL; + } + break; + case PWM_CYCLE: + ret = HAL_PWM_EnableCh(info.ch, PWM_CYCLE_MODE, 1); + if (ret != HAL_OK) { + CMD_ERR("Enable channel error\n"); + return CMD_STATUS_FAIL; + } + break; + case PWM_CAPTURE: + ret = HAL_PWM_EnableCh(info.ch, PWM_CAPTURE_MODE, 1); + if (ret != HAL_OK) { + CMD_ERR("Enable channel error\n"); + return CMD_STATUS_FAIL; + } + + irq_cfg.arg = NULL; + irq_cfg.callback = NULL; + irq_cfg.event = PWM_IRQ_BOTHEDGE; + + ret = HAL_PWM_EnableIRQ(info.ch, &irq_cfg); + if (ret != HAL_OK) { + CMD_ERR("Enable irq error\n"); + return CMD_STATUS_FAIL; + } + break; + case PWM_DEADZONE: + ret = HAL_PWM_EnableDeadZone(info.group, 1); + if (ret != HAL_OK) + CMD_ERR("Enable dead zone error\n"); + return CMD_STATUS_FAIL; + + break; + default: + CMD_DBG("invalid pwm mode %u\n", mode); + return CMD_STATUS_INVALID_ARG; + } + return CMD_STATUS_OK; +} + +enum cmd_status cmd_pwm_set_exec(char *cmd) +{ + uint32_t value; + uint32_t channel; + char function[10]; + int cnt; + PWM_IoInfo info; + cnt = cmd_sscanf(cmd, "c=%u m=%s v=%u", &channel, function, &value); + + if (cnt != 3) + return CMD_STATUS_INVALID_ARG; + + if (cmd_strcmp(function, "comple") == 0 || + cmd_strcmp(function, "deadzone") == 0 ) + info = cmd_pwm_channel_analytic(PWM_COMPLE, channel); + else + info = cmd_pwm_channel_analytic(PWM_CYCLE, channel); + + if (info.group == PWM_GROUP_NULL) { + CMD_ERR("invalid pwm channel\n"); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(function, "deadzone") == 0) { + if (value > 255) { + CMD_ERR("deadzone value out of range\n"); + return CMD_STATUS_INVALID_ARG; + } + HAL_PWM_SetDeadZoneTime(info.group, value); + } else if (cmd_strcmp(function, "comple") == 0) { + __IO uint32_t *reg; + + if (value > 0) { + info.ch = info.group * 2; + + reg = &PWM->CH_REG[info.ch].PPR; + value = value * ((*reg & PWM_PPR_ENTIER_CYCLE) >> 16) / 10000; + if (value <= 1) + value = 2; + } + + HAL_PWM_ComplementarySetDutyRatio(info.group, value); + } else if (cmd_strcmp(function, "cycle") == 0) { + __IO uint32_t *reg; + + if (value > 0) { + reg = &PWM->CH_REG[info.ch].PPR; + value = value * ((*reg & PWM_PPR_ENTIER_CYCLE) >> 16) / 10000; + if (value <= 1) + value = 2; + } + + HAL_PWM_ChSetDutyRatio(info.ch, value); + } else if (cmd_strcmp(function, "pluse") == 0) { + __IO uint32_t *reg; + + if (value > 0) { + reg = &PWM->CH_REG[info.ch].PPR; + value = value * ((*reg & PWM_PPR_ENTIER_CYCLE) >> 16) / 10000; + if (value <= 1) + value = 2; + } + + HAL_PWM_ChSetDutyRatio(info.ch, value); + } else + return CMD_STATUS_INVALID_ARG; + + return CMD_STATUS_OK; +} + + +static int PWM_DeadTime(uint8_t chGroup) +{ + + if (chGroup >= PWM_GROUP_NUM) + return -1; + + uint32_t p = PWM->PDZCR[chGroup]; + p &= PWM_CH_DZ_INV; + return (p >> 8); +} + +static int PWM_ReadActCycle(uint8_t ch) +{ + if (ch >= PWM_CH_NUM) + return -1; + int p = (int)PWM->CH_REG[ch].PPR; + return p; +} + +static PWM_Polarity _PWM_Polarity(uint8_t ch) +{ + if ((PWM->CH_REG[ch].PCR & PWM_PCR_ACT_STA) > 0) + return PWM_HIGHLEVE; + + return PWM_LOWLEVE; + +} + +static Cmd_PwmMode PWM_ChMode(uint8_t ch) +{ + __IO uint32_t *reg = NULL; + reg = &PWM->CH_REG[ch].PCR; + + if ((*reg & PWM_PCR_MODE) > 0) + return PWM_PLUSE_MODE; + + return PWM_CYCLE_MODE; +} + +int PWM_DeadZoneEnable(PWM_GROUP_ID chGroup) +{ + if (chGroup >= PWM_GROUP_NUM) + return -1; + + return PWM->PDZCR[chGroup]&PWM_CH_DZ_EN; +} + + +#define CAPTURE_TASK_THREAD_STACK_SIZE (2 * 1024) +static OS_Thread_t g_capture_thread_t; + +void cmd_capture_task(void *arg) +{ + int i = 0; + + if (PWM->CIER == 0) { + OS_ThreadDelete(&g_capture_thread_t); + return; + } + + PWM_CapResult result; + + while (PWM->CIER) { + Cmd_Capinfo *info = &private_cap[i]; + + if (info->count < info->num) { + while (info->count < info->num) { + if ( PWM_ChMode(info->input_ch) == PWM_PLUSE) + result = HAL_PWM_CaptureResult(PWM_CAP_PLUSE, i); + else + result = HAL_PWM_CaptureResult(PWM_CAP_CYCLE, i); + + if (result.highLevelTime) { + info->count += 1; + if (info->count == 1) + continue; + + info->high_time += result.highLevelTime; + info->low_time += result.lowLevelTime; + } + } + } else + OS_MSleep(10); + + i ++; + if (i >= 8) + i = 0; + } + OS_ThreadDelete(&g_capture_thread_t); +} + +enum cmd_status cmd_pwm_get_exec(char *cmd) +{ + uint32_t channel; + uint32_t src_signal; + char function[8]; + uint32_t num = 0; + uint32_t value_deviation = 0; + uint32_t hz_deviation = 0; + int cnt; + + cnt = cmd_sscanf(cmd, "c=%u m=%s n=%u input_ch=%u dv=%u dh=%u", &channel, function, &num, + &src_signal, &value_deviation, &hz_deviation); + if (cnt != 6) { + CMD_ERR("miss param, %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (num > 1000) { + CMD_ERR("The n value out of range\n"); + return CMD_STATUS_INVALID_ARG; + } + + if (value_deviation > 100 || hz_deviation > 100) { + CMD_ERR("The value out of range\n"); + return CMD_STATUS_FAIL; + } + + PWM_IoInfo info; + info = cmd_pwm_channel_analytic(PWM_CYCLE, src_signal); + if (info.group== PWM_GROUP_NULL) { + CMD_ERR("invalid src_signal\n"); + return CMD_STATUS_INVALID_ARG; + } + + info = cmd_pwm_channel_analytic(PWM_CAPTURE, channel); + if (info.group== PWM_GROUP_NULL) { + CMD_ERR("invalid ch \n"); + return CMD_STATUS_INVALID_ARG; + } + Cmd_Capinfo *cap_info = private_cap; + + cap_info[channel].num = num; + cap_info[channel].count = 0; + cap_info[channel].d_hz = hz_deviation; + cap_info[channel].d_value = value_deviation; + cap_info[channel].input_ch = src_signal; + cap_info[channel].high_time = 0; + cap_info[channel].low_time = 0; + + if (!OS_ThreadIsValid(&g_capture_thread_t)) { + if (OS_ThreadCreate(&g_capture_thread_t, + "", + cmd_capture_task, + NULL, + OS_PRIORITY_ABOVE_NORMAL, + CAPTURE_TASK_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("create sys ctrl task failed\n"); + } + } + + return CMD_STATUS_OK; +} + + +typedef enum { + CAP_ERROR, + CAP_BUSY, + CAP_OK, +}CAP_RESULT; + +CAP_RESULT cmd_CapResult(uint8_t ch) { + CAP_RESULT ret; + + uint16_t input_right_period = 0, input_right_h_time = 0; + uint8_t deadzone_time = 0; + Cmd_Capinfo *info = &private_cap[ch]; + + if (PWM_DeadZoneEnable(info->input_ch/ 2)) + deadzone_time = PWM_DeadTime(info->input_ch / 2); + + if (info->count == info->num) { + uint32_t cap_period = 0; + uint32_t cap_h_time = 0; + + __IO uint32_t *reg = &PWM->CH_REG[info->input_ch].PPR; + + input_right_period = (*reg & PWM_PPR_ENTIER_CYCLE) >> 16; + input_right_h_time = PWM_ReadActCycle(info->input_ch); + + if (_PWM_Polarity(info->input_ch)== PWM_LOWLEVE) + input_right_h_time = input_right_period- input_right_h_time; + + if (deadzone_time > 0) { + input_right_h_time -= deadzone_time; + } + + cap_h_time = info->high_time / (info->num - 1); + cap_period = cap_h_time + info->low_time / (info->num - 1); + + if ( PWM_ChMode(info->input_ch) == PWM_CYCLE) { + if (abs(cap_h_time - input_right_h_time) <= info->d_value && + abs(cap_period - input_right_period) <= info->d_hz) + ret = CAP_OK; + else + ret = CAP_ERROR; + } else { + if (abs(cap_h_time - input_right_h_time) <= info->d_value) + ret = CAP_OK; + else + ret = CAP_ERROR; + } + + memset(info, 0, sizeof(Cmd_Capinfo)); + + return ret; + } + + return CAP_BUSY; +} + + +enum cmd_status cmd_pwm_get_result_exec(char *cmd) +{ + uint32_t channel; + int cnt; + + cnt = cmd_sscanf(cmd, "c=%u ", &channel); + if (cnt != 1) + return CMD_STATUS_INVALID_ARG; + + PWM_IoInfo info = cmd_pwm_channel_analytic(PWM_CAPTURE, channel); + + if (info.group== PWM_GROUP_NULL) { + CMD_ERR("invalid pwm channel\n"); + return CMD_STATUS_INVALID_ARG; + } + + CAP_RESULT ret = cmd_CapResult(channel); + + if (ret == CAP_BUSY) { + CMD_ERR("PWM%d Capture BUSY\n", info.ch); + return CMD_STATUS_ERROR_MIN; + } else if (ret == CAP_ERROR) { + CMD_ERR("PWM%d Capture ERROR\n",info.ch); + return CMD_STATUS_FAIL; + } else if (ret == CAP_OK) { + return CMD_STATUS_OK; + } + + return CMD_STATUS_OK; +} + +enum cmd_status cmd_pwm_stop_exec(char *cmd) +{ + char mode_char[8]; + uint32_t channel; + int cnt; + + cnt = cmd_sscanf(cmd, "c=%u m=%s", &channel, mode_char); + if (cnt != 2) + return CMD_STATUS_INVALID_ARG; + + Cmd_PwmMode mode = cmd_pwm_mode_analytic(mode_char); + if (mode >= PWM_MODENUM) { + CMD_ERR("invalid pwm mode %u\n", mode); + return CMD_STATUS_INVALID_ARG; + } + + PWM_IoInfo info = cmd_pwm_channel_analytic(mode, channel); + if (info.group== PWM_GROUP_NULL) { + CMD_ERR("invalid pwm channel\n"); + return CMD_STATUS_INVALID_ARG; + } + + + + switch(mode) { + case PWM_COMPLE: + HAL_PWM_EnableComplementary(info.group, 0); + HAL_PWM_SetDeadZoneTime(info.group, 0); + HAL_PWM_EnableDeadZone(info.group, 0); + break; + case PWM_PLUSE: + HAL_PWM_EnableCh(info.ch, PWM_PLUSE_MODE, 0); + break; + case PWM_CYCLE: + HAL_PWM_EnableCh(info.ch, PWM_CYCLE_MODE, 0); + break; + case PWM_CAPTURE: + HAL_PWM_EnableCh(info.ch, PWM_CAPTURE_MODE, 0); + HAL_PWM_DisableIRQ(info.ch); + break; + case PWM_DEADZONE: + HAL_PWM_SetDeadZoneTime(info.group, 0); + HAL_PWM_EnableDeadZone(info.group, 0); + break; + default : + CMD_ERR("invalid pwm mode\n"); + return CMD_STATUS_INVALID_ARG; + } + return CMD_STATUS_OK; +} + +/* + * driver commands + */ +static struct cmd_data g_pwm_cmds[] = { + { "deinit", cmd_pwm_deinit_exec }, + { "config", cmd_pwm_config_exec }, + { "start", cmd_pwm_start_exec }, + { "set", cmd_pwm_set_exec }, + { "get", cmd_pwm_get_exec }, + { "get_result", cmd_pwm_get_result_exec }, + { "stop", cmd_pwm_stop_exec }, +}; + +enum cmd_status cmd_pwm_exec(char *cmd) +{ + return cmd_exec(cmd, g_pwm_cmds, cmd_nitems(g_pwm_cmds)); +} + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_pwm.h b/platform/mcu/xr871/project/common/cmd/cmd_pwm.h new file mode 100644 index 0000000000..e6f3d21909 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_pwm.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_PWM_H_ +#define _CMD_PWM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_pwm_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_PWM_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_rtc.c b/platform/mcu/xr871/project/common/cmd/cmd_rtc.c new file mode 100644 index 0000000000..e25a6081c2 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_rtc.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_rtc.h" +#include "driver/chip/hal_rtc.h" +#include + +#define CMD_YEAR0 1900 /* the first year for struct tm::tm_year */ +#define CMD_IS_LEAP_YEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400))) + +/* due to time_t is singed long, we will get problems on 2038-01-19 03:14:08 */ +#define CMD_YEAR_MIN 1970 +#define CMD_YEAR_MAX 2037 + +#define CMD_WDAY_TM2RTC(wday) (((wday) + 6) % 7) +#define CMD_WDAY_RTC2TM(wday) (((wday) + 1) % 7) + +enum cmd_rtc_alarm { + CMD_RTC_ALARM_SECOND = 0, + CMD_RTC_ALARM_WDAY +}; + +const int8_t g_cmd_mday[2][12] = { + { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }, /* normal year */ + { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } /* leap year */ +}; + +const char *g_cmd_wday_str[] = { + "Sunday", "Monday", "Tuesday", "Wednesday", "Thursday", "Friday", "Saturday" +}; + +/* + * drv rtc set + */ +static enum cmd_status cmd_rtc_set_exec(char *cmd) +{ + int year, month, mday, hour, minute, second; + int32_t cnt; + struct tm t; + time_t clock; + int leap; + + cnt = cmd_sscanf(cmd, "%d-%d-%d,%d:%d:%d", + &year, &month, &mday, &hour, &minute, &second); + if (cnt != 6) { + return CMD_STATUS_INVALID_ARG; + } + + if (year < CMD_YEAR_MIN || year > CMD_YEAR_MAX) { + CMD_ERR("invalid year %u\n", year); + return CMD_STATUS_INVALID_ARG; + } + leap = CMD_IS_LEAP_YEAR(year); + + if (month < 1 || month > 12) { + CMD_ERR("invalid month %u\n", month); + return CMD_STATUS_INVALID_ARG; + } + month -= 1; + + if (mday < 1 || mday > g_cmd_mday[leap][month]) { + CMD_ERR("invalid mday %u\n", mday); + return CMD_STATUS_INVALID_ARG; + } + + if (hour < 0 || hour > 23) { + CMD_ERR("invalid hour %u\n", hour); + return CMD_STATUS_INVALID_ARG; + } + + if (minute < 0 || minute > 59) { + CMD_ERR("invalid minute %u\n", minute); + return CMD_STATUS_INVALID_ARG; + } + + if (second < 0 || second > 59) { + CMD_ERR("invalid second %u\n", second); + return CMD_STATUS_INVALID_ARG; + } + + cmd_memset(&t, 0, sizeof(t)); + t.tm_year = year - CMD_YEAR0; + t.tm_mon = month; + t.tm_mday = mday; + t.tm_hour = hour; + t.tm_min = minute; + t.tm_sec = second; + clock = mktime(&t); + gmtime_r(&clock, &t); + + t.tm_mon += 1; + HAL_RTC_SetYYMMDD(leap, t.tm_year, t.tm_mon, t.tm_mday); + HAL_RTC_SetDDHHMMSS(CMD_WDAY_TM2RTC(t.tm_wday), t.tm_hour, t.tm_min, t.tm_sec); + + CMD_DBG("%d-%02d-%02d %s %02d:%02d:%02d, leap %d\n", + t.tm_year + CMD_YEAR0, t.tm_mon, t.tm_mday, + g_cmd_wday_str[t.tm_wday], t.tm_hour, t.tm_min, t.tm_sec, leap); + + return CMD_STATUS_OK; +} + +/* + * drv rtc get + */ +static enum cmd_status cmd_rtc_get_exec(char *cmd) +{ + uint8_t leap, year, month, mday, hour, minute, second; + RTC_WeekDay wday; + + HAL_RTC_GetYYMMDD(&leap, &year, &month, &mday); + HAL_RTC_GetDDHHMMSS(&wday, &hour, &minute, &second); + + cmd_write_respond(CMD_STATUS_OK, "%d-%02d-%02d %s %02d:%02d:%02d", + year + CMD_YEAR0, month, mday, + g_cmd_wday_str[CMD_WDAY_RTC2TM(wday)], + hour, minute, second); + + return CMD_STATUS_ACKED; +} + +static void cmd_rtc_alarm_callback(void *arg) +{ + uint8_t leap, year, month, mday, hour, minute, second; + RTC_WeekDay wday; + enum cmd_rtc_alarm alarm = (enum cmd_rtc_alarm)arg; + + HAL_RTC_GetYYMMDD(&leap, &year, &month, &mday); + HAL_RTC_GetDDHHMMSS(&wday, &hour, &minute, &second); + + cmd_write_event(CMD_EVENT_RTC_NOTIFY, "rtc %s-alarm notify at " + "%d-%02d-%02d %s %02d:%02d:%02d", + alarm == CMD_RTC_ALARM_SECOND ? "sec" : "wday", + year + CMD_YEAR0, month, mday, + g_cmd_wday_str[CMD_WDAY_RTC2TM(wday)], + hour, minute, second); +} + +/* + * drv rtc alarm sec start + */ +static enum cmd_status cmd_rtc_sec_alarm_start_exec(char *cmd) +{ + uint32_t second; + int32_t cnt; + RTC_SecAlarmStartParam param; + + cnt = cmd_sscanf(cmd, "%u", &second); + if (cnt != 1) { + return CMD_STATUS_INVALID_ARG; + } + + param.alarmSeconds = second; + param.callback = cmd_rtc_alarm_callback; + param.arg = (void *)CMD_RTC_ALARM_SECOND; + HAL_RTC_StartSecAlarm(¶m); + return CMD_STATUS_OK; +} + +/* + * drv rtc alarm sec stop + */ +static enum cmd_status cmd_rtc_sec_alarm_stop_exec(char *cmd) +{ + HAL_RTC_StopSecAlarm(); + return CMD_STATUS_OK; +} + +/* + * drv rtc alarm wday start ... + */ +static enum cmd_status cmd_rtc_wday_alarm_start_exec(char *cmd) +{ + int argc, i, j; + char *argv[9]; + uint32_t hour, minute, second; + uint8_t wday_mask; + int32_t cnt; + RTC_WDayAlarmStartParam param; + + argc = cmd_parse_argv(cmd, argv, 9); + if (argc < 2 || argc > 8) { + return CMD_STATUS_INVALID_ARG; + } + + cnt = cmd_sscanf(argv[0], "%d:%d:%d", &hour, &minute, &second); + if (cnt != 3) { + return CMD_STATUS_INVALID_ARG; + } + + if (hour < 0 || hour > 23) { + CMD_ERR("invalid hour %u\n", hour); + return CMD_STATUS_INVALID_ARG; + } + + if (minute < 0 || minute > 59) { + CMD_ERR("invalid minute %u\n", minute); + return CMD_STATUS_INVALID_ARG; + } + + if (second < 0 || second > 59) { + CMD_ERR("invalid second %u\n", second); + return CMD_STATUS_INVALID_ARG; + } + + wday_mask = 0; + for (i = 1; i < argc; ++i) { + for (j = 0; j < cmd_nitems(g_cmd_wday_str); ++j) { + if (cmd_strcmp(argv[i], g_cmd_wday_str[j]) == 0) { + wday_mask |= RTC_WDAY_ALARM_EN_BIT(CMD_WDAY_TM2RTC(j)); + break; + } + } + if (j >= cmd_nitems(g_cmd_wday_str)) { + wday_mask = 0; + break; /* Invalid week day */ + } + } + + if (wday_mask == 0) { + CMD_ERR("invalid week days\n"); + return CMD_STATUS_INVALID_ARG; + } + + param.alarmHour = hour; + param.alarmMinute = minute; + param.alarmSecond = second; + param.alarmWDayMask = wday_mask; + param.callback = cmd_rtc_alarm_callback; + param.arg = (void *)CMD_RTC_ALARM_WDAY; + HAL_RTC_StartWDayAlarm(¶m); + return CMD_STATUS_OK; +} + +/* + * drv rtc alarm wday stop + */ +static enum cmd_status cmd_rtc_wday_alarm_stop_exec(char *cmd) +{ + HAL_RTC_StopWDayAlarm(); + return CMD_STATUS_OK; +} + +static struct cmd_data g_rtc_cmds[] = { + { "set", cmd_rtc_set_exec }, + { "get", cmd_rtc_get_exec }, + { "sec-alarm-start", cmd_rtc_sec_alarm_start_exec }, + { "sec-alarm-stop", cmd_rtc_sec_alarm_stop_exec}, + { "wday-alarm-start", cmd_rtc_wday_alarm_start_exec }, + { "wday-alarm-stop", cmd_rtc_wday_alarm_stop_exec }, +}; + +enum cmd_status cmd_rtc_exec(char *cmd) +{ + return cmd_exec(cmd, g_rtc_cmds, cmd_nitems(g_rtc_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_rtc.h b/platform/mcu/xr871/project/common/cmd/cmd_rtc.h new file mode 100644 index 0000000000..72e4160842 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_RTC_H_ +#define _CMD_RTC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_rtc_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_RTC_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_sd.c b/platform/mcu/xr871/project/common/cmd/cmd_sd.c new file mode 100644 index 0000000000..1366383c82 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_sd.c @@ -0,0 +1,565 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "sys/xr_debug.h" + +#include "cmd_util.h" +#include "cmd_sd.h" + +#include "driver/chip/hal_def.h" +#include "driver/chip/sdmmc/hal_sdhost.h" +#include "driver/chip/sdmmc/sdmmc.h" + +static struct mmc_card *card; + +extern int32_t mmc_test(uint32_t cd_mode); +extern int32_t mmc_test_init(void); +extern int32_t mmc_test_exit(void); +struct mmc_card *mmc_scan_init(void); + +/* + * drv sd init + */ +static enum cmd_status cmd_sd_init_exec(char *cmd) +{ + mmc_test_init(); + + return CMD_STATUS_OK; +} + +/* + * drv sd scan + */ +static enum cmd_status cmd_sd_scan_exec(char *cmd) +{ + card = mmc_scan_init(); + if (!card) { + CMD_ERR("scan card failed!\n"); + return CMD_STATUS_OK;; + } + + return CMD_STATUS_OK; +} + +/* + * drv sd read s= n= + */ +static enum cmd_status cmd_sd_read_exec(char *cmd) +{ + int32_t err; + uint32_t cnt; + uint32_t start_sector, r_secnum; + char *buf; + + cnt = cmd_sscanf(cmd, "s=%d n=%d", &start_sector, &r_secnum); + if (cnt != 2) { + CMD_ERR("invalid argument %s\n", cmd); + return CMD_STATUS_FAIL; + } + + buf = cmd_malloc(r_secnum*512); + if (!buf) + return CMD_STATUS_OK;; + + err = mmc_block_read(card, (uint8_t *)buf, start_sector, r_secnum); + if (err) { + CMD_ERR("mmc mult blocks read err!\n"); + return CMD_STATUS_FAIL; + } + + CMD_DBG("read from %d sector, %d sectors\n", start_sector, r_secnum); + print_hex_dump_bytes(buf, r_secnum*512); + + return CMD_STATUS_OK; +} + +/* + * drv sd test + */ +static enum cmd_status cmd_sd_test_exec(char *cmd) +{ + mmc_test(0); + + return CMD_STATUS_OK; +} + +/* + * drv sd deinit + */ +static enum cmd_status cmd_sd_deinit_exec(char *cmd) +{ + mmc_test_exit(); + + return CMD_STATUS_OK; +} + +#define CMD_ARG_LEN 64 + +struct sd_test_param { + uint8_t task_idx; + uint8_t random; + uint8_t task_num; + uint16_t time_sec; + uint32_t start_sector; + uint32_t sector_num; +}; + +static void cmd_sd_bench_task(void *arg) +{ + int32_t err; + char *cmd = (char *)arg; + uint32_t start_sector; + uint32_t cnt; + uint32_t throuth_mb, throuth_kb; + OS_Time_t tick_use; + uint32_t bench_sector; + + cnt = cmd_sscanf(cmd, "s=%d", &start_sector); + if (cnt != 1) { + CMD_ERR("invalid argument %s\n", cmd); + goto out; + } + + mmc_test_init(); + card = mmc_scan_init(); + if (!card) { + CMD_ERR("scan card failed!\n"); + goto out; + } + + bench_sector = start_sector - 1; + + for (int i = 0; i < 1000; i++) { + uint32_t bench_size = 512 * (1 << i); + uint8_t *buf = cmd_malloc(bench_size); + if (!buf) { + CMD_DBG("%s test end for malloc buff failed!\n", __func__); + goto out; + } + + for (int j = 0; j < bench_size/4; j++) + ((unsigned int *)buf)[j] = j; + + bench_sector += bench_size/512; + + tick_use = OS_GetTicks(); + err = mmc_block_write(card, buf, bench_sector, bench_size/512); + tick_use = OS_GetTicks() - tick_use; + if (!tick_use) + tick_use = 1; + if (err) { + CMD_ERR("mmc mult blocks write err!\n"); + goto next; + } else { + throuth_kb = bench_size*1000/1024/(uint32_t)OS_TicksToMSecs(tick_use); + throuth_mb = throuth_kb/1000; + CMD_DBG("%s mult blocks write ok, ", __func__); + if (bench_size <= 512) + CMD_LOG(CMD_DBG_ON, "0.5"); + else + CMD_LOG(CMD_DBG_ON, "%3d", bench_size/1024); + CMD_LOG(CMD_DBG_ON, " KB use:%3d ms, throughput:%d.%d MB/S\n", + (uint32_t)OS_TicksToMSecs(tick_use), + throuth_mb, throuth_kb - throuth_mb); + } + + for (int j = 0; j < bench_size/4; j++) + ((unsigned int *)buf)[j] = 0; + + tick_use = OS_GetTicks(); + err = mmc_block_read(card, buf, bench_sector, bench_size/512); + tick_use = OS_GetTicks() - tick_use; + if (!tick_use) + tick_use = 1; + if (err) { + CMD_ERR("mmc mult blocks read err!\n"); + goto next; + } else { + throuth_kb = bench_size*1000/1024/(uint32_t)OS_TicksToMSecs(tick_use); + throuth_mb = throuth_kb/1000; + CMD_DBG("%s mult blocks read ok, ", __func__); + if (bench_size <= 512) + CMD_LOG(CMD_DBG_ON, "0.5"); + else + CMD_LOG(CMD_DBG_ON, "%3d", bench_size/1024); + CMD_LOG(CMD_DBG_ON, " KB use:%3d ms, throughput:%d.%d MB/S\n", + (uint32_t)OS_TicksToMSecs(tick_use), + throuth_mb, throuth_kb - throuth_mb); + } + + err = 0; + for (int j = 0; j < bench_size/4; j++) { + if (((unsigned int *)buf)[j] != j) { + err = -1; + break; + } + } + if (err) { + CMD_ERR("mmc %d blocks write data err!\n", bench_size/512); + goto next; + } +next: + cmd_free(buf); + if (err) + break; + } + +out: + CMD_DBG("%s test end\n", __func__); + mmc_test_exit(); + cmd_free(arg); + OS_ThreadDelete(NULL); +} + +#define PRESS_FILE_SIZE (20 * 1024 * 1024) /* 20M */ +#define PRESS_READ_SIZE 2048 +#define PRESS_WRITE_SIZE 8192 +static OS_Semaphore_t sem_wait; + +static void cmd_sd_press_read_task(void *arg) +{ + int32_t err; + struct sd_test_param *param = (struct sd_test_param *)arg; + OS_Time_t tick_now = 0, tick_print = 0; + OS_Time_t tick_end = OS_GetTicks() + OS_MSecsToTicks(param->time_sec * 1000); + uint32_t random_sleep = param->random; + char *buf; + uint32_t start_sector = param->start_sector; + + if (param->task_idx == 0) { + buf = cmd_malloc(4096); + for (int i = 0; i < 512/4; i++) { + ((unsigned int *)buf)[i] = i; + } + memcpy(buf+512, buf, 512); + memcpy(buf+1024, buf, 1024); + memcpy(buf+2048, buf, 2048); + CMD_DBG("%s do nothing until sd card prepare ok!\n", __func__); + for (int i = 0; i < (PRESS_FILE_SIZE+4095)/4096; i++) { /* 10M */ + int32_t err; + err = mmc_block_write(card, (uint8_t *)buf, start_sector + (i*(4096/512)), 4096/512); + if (err) + goto out; + } + CMD_DBG("%s sd card prepared ok!\n", __func__); + + for (int j = 0; j < param->task_num - 1; j++) + OS_SemaphoreRelease(&sem_wait); + cmd_free(buf); + } else { + OS_SemaphoreWait(&sem_wait, OS_WAIT_FOREVER); + } + + buf = cmd_malloc(param->sector_num*512); + if (!buf) + goto exit; + + if (!random_sleep) + random_sleep = 2; + OS_MSleep(random_sleep); + CMD_DBG("%s id:%d random:%d start_sector:%d\n", __func__, param->task_idx, + random_sleep, start_sector); + + while (tick_now < tick_end) { + int j; + err = mmc_block_read(card, (uint8_t *)buf, start_sector, param->sector_num); + if (err) { + CMD_ERR("mmc mult blocks read err!\n"); + goto out; + } + err = 0; + for (j = 0; j < param->sector_num*(512/4); j++) { + if (((unsigned int *)buf)[j] != (j & 0x07f)) { + err = -1; + CMD_ERR("%x %x\n", j, ((unsigned int *)buf)[j]); + break; + } + } + if (err) { + CMD_ERR("mmc %d blocks read data err! at sector:%d count:%d\n", + param->sector_num, start_sector, j); + goto out; + } else + ;//CMD_DBG("%s mmc blocks read data ok! at sector:%d\n", + // __func__, start_sector); + start_sector += param->sector_num; + if (start_sector >= param->start_sector + PRESS_FILE_SIZE/512) { + start_sector = param->start_sector; + } + OS_MSleep(random_sleep); + tick_now = OS_GetTicks(); + if (tick_now >= tick_print + 5000) { + CMD_DBG("%s id:%d testing... at sector:%d\n", __func__, + param->task_idx, start_sector); + tick_print = tick_now; + } + } + +out: + CMD_DBG("%s id:%d test end\n", __func__, param->task_idx); + cmd_free(buf); +exit: + cmd_free(param); + if (param->task_idx == 0) + OS_SemaphoreDelete(&sem_wait); + OS_ThreadDelete(NULL); +} + +static void cmd_sd_press_write_task(void *arg) +{ + int32_t err; + struct sd_test_param *param = (struct sd_test_param *)arg; + OS_Time_t tick_now = 0, tick_print = 0; + OS_Time_t tick_end = OS_GetTicks() + OS_MSecsToTicks(param->time_sec * 1000); + uint32_t random_sleep = param->random; + char *buf; + uint32_t start_sector = param->start_sector; + uint32_t round = 0; + uint32_t total_num; + + buf = cmd_malloc(param->sector_num*512); + if (!buf) + goto out; + + for (int i = 0; i < 512/4; i++) + ((unsigned int *)buf)[i] = i; + + for (int i = 1; i < param->sector_num; i++) + memcpy(buf + i * 512, buf, 512); + + if (!random_sleep) + random_sleep = 2; + OS_MSleep(random_sleep); + CMD_DBG("%s id:%d random:%d\n", __func__, param->task_idx, random_sleep); + + while (tick_now < tick_end) { + err = mmc_block_write(card, (uint8_t *)buf, start_sector, param->sector_num); + if (err) { + CMD_ERR("mmc mult blocks write err!\n"); + goto out; + } + start_sector += param->sector_num; + if (start_sector >= param->start_sector + PRESS_FILE_SIZE/512) { + start_sector = param->start_sector; + round = 1; + } + OS_MSleep(random_sleep); + tick_now = OS_GetTicks(); + if (tick_now >= tick_print + 5000) { + CMD_DBG("%s id:%d testing... at sector:%d\n", __func__, + param->task_idx, start_sector); + tick_print = tick_now; + } + } + CMD_DBG("%s test end. round:%d start_sector:%d end_sector:%d\n", __func__, + round, param->start_sector, start_sector); + + if (round) { + total_num = PRESS_FILE_SIZE/512; + } else { + // BUG_ON(start_sector <= param->start_sector); + total_num = start_sector - param->start_sector; + } + total_num /= param->sector_num; + + start_sector = param->start_sector; + CMD_DBG("%s test checking... start_sector:%d total_num:%d\n", __func__, + start_sector, total_num); + for (int i = 0; i < total_num; i++) { + int j; + + memset(buf, 0, param->sector_num*512); + err = mmc_block_read(card, (uint8_t *)buf, start_sector, param->sector_num); + if (err) { + CMD_ERR("mmc mult blocks read err!\n"); + goto out; + } + err = 0; + for (j = 0; j < param->sector_num*(512/4); j++) { + if (((unsigned int *)buf)[j] != (j & 0x07f)) { + err = -1; + break; + } + } + if (err) { + CMD_ERR("%x %x\n", ((unsigned int *)buf)[j], (j & 0x07f)); + CMD_ERR("mmc %d blocks write data err! at sector:%d count:%d\n", + param->sector_num, start_sector, j); + goto out; + } else + ;//CMD_DBG("%s mmc blocks write data ok! at sector:%d\n", + // __func__, start_sector); + start_sector += param->sector_num; + } + +out: + CMD_DBG("%s id:%d test end\n", __func__, param->task_idx); + cmd_free(buf); + cmd_free(param); + OS_ThreadDelete(NULL); +} + +/* + * drv sd bench s= + */ +static enum cmd_status cmd_sd_bench_exec(char *cmd) +{ + OS_Thread_t thread; + char *param; + uint32_t len; + + len = strlen(cmd); + if (len >= CMD_ARG_LEN) { + CMD_ERR("should adjust CMD_ARG_LEN to %d\n", len); + return CMD_STATUS_FAIL; + } + + param = cmd_malloc(CMD_ARG_LEN); + if (!param) + return CMD_STATUS_FAIL; + memcpy(param, cmd, len); + param[len+1] = 0; + + OS_ThreadSetInvalid(&thread); + if (OS_ThreadCreate(&thread, + "", + cmd_sd_bench_task, + param, + OS_THREAD_PRIO_APP, + 2 * 1024) != OS_OK) { + CMD_ERR("create sd bench test task failed\n"); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +/* + * drv sd press r= s= n= w= + * s= n= t= + */ +static enum cmd_status cmd_sd_press_exec(char *cmd) +{ + OS_Thread_t thread; + struct sd_test_param *param; + uint32_t r_threads, w_threads; + uint32_t r_secnum, w_secnum; + uint32_t cnt; + uint32_t time_sec; + uint32_t start_rsector, start_wsector; + + cnt = cmd_sscanf(cmd, "r=%d s=%d n=%d w=%d s=%d n=%d t=%d", + &r_threads, &start_rsector, &r_secnum, + &w_threads, &start_wsector, &w_secnum, &time_sec); + if (cnt != 7) { + CMD_ERR("invalid argument %s\n", cmd); + return CMD_STATUS_FAIL; + } + + OS_SemaphoreCreate(&sem_wait, 0, OS_SEMAPHORE_MAX_COUNT); + + OS_MSleep(5); + + for (uint32_t i = 0; i < r_threads; i++) { + param = cmd_malloc(sizeof(struct sd_test_param)); + if (!param) + return CMD_STATUS_FAIL; + param->task_idx = i; + param->task_num = r_threads; + param->start_sector = start_rsector; + param->sector_num = r_secnum; + param->time_sec = time_sec; + param->random = rand() % 8 + i; + if (!r_secnum || time_sec < 2) { + CMD_ERR("%s read n= should not 0 !\n", __func__); + cmd_free(param); + goto out; + } + OS_ThreadSetInvalid(&thread); + if (OS_ThreadCreate(&thread, + "", + cmd_sd_press_read_task, + param, + OS_THREAD_PRIO_APP, + 2 * 1024) != OS_OK) { + CMD_ERR("create sd bench test task failed\n"); + return CMD_STATUS_FAIL; + } + (void)cmd_sd_press_read_task; + OS_MSleep(2); + } + + for (uint32_t i = 0; i < w_threads; i++) { + param = cmd_malloc(sizeof(struct sd_test_param)); + if (!param) + return CMD_STATUS_FAIL; + param->task_idx = i; + param->task_num = w_threads; + param->start_sector = start_wsector; + param->sector_num = w_secnum; + param->time_sec = time_sec; + param->random = rand() % 20 + i; + if (!w_secnum || time_sec < 2) { + CMD_ERR("%s write n= should not 0 !\n", __func__); + cmd_free(param); + goto out; + } + OS_ThreadSetInvalid(&thread); + if (OS_ThreadCreate(&thread, + "", + cmd_sd_press_write_task, + param, + OS_THREAD_PRIO_APP, + 2 * 1024) != OS_OK) { + CMD_ERR("create sd bench test task failed\n"); + return CMD_STATUS_FAIL; + } + OS_MSleep(2); + } + +out: + return CMD_STATUS_OK; +} + +static struct cmd_data g_sd_cmds[] = { + { "init", cmd_sd_init_exec }, + { "deinit", cmd_sd_deinit_exec }, + { "scan", cmd_sd_scan_exec }, + { "read", cmd_sd_read_exec }, + { "test", cmd_sd_test_exec }, + { "bench", cmd_sd_bench_exec }, + { "press", cmd_sd_press_exec }, +}; + +enum cmd_status cmd_sd_exec(char *cmd) +{ + return cmd_exec(cmd, g_sd_cmds, cmd_nitems(g_sd_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_sd.h b/platform/mcu/xr871/project/common/cmd/cmd_sd.h new file mode 100644 index 0000000000..11a96bf089 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_sd.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_SD_H_ +#define _CMD_SD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* example: + * 1. init sd use: drv sd config p=invert + * use "p=none" when tx rx gpio direct connect in test mode. + * 2. get received addr and key use: drv sd value 0 + * 3. deinit sd use: drv sd deconfig 0 + */ + +enum cmd_status cmd_sd_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_SD_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_smart_config.c b/platform/mcu/xr871/project/common/cmd/cmd_smart_config.c new file mode 100644 index 0000000000..cda779a185 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_smart_config.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" + +#include "common/framework/net_ctrl.h" +#include "net/wlan/wlan.h" +#include "net/wlan/wlan_defs.h" +#include + +#define SC_TIME_OUT 120000 +#define SC_ACK_TIME_OUT 30000 +static char *key = "1234567812345678"; + +static OS_Thread_t g_sc_ctrl_thread; +#define SC_CTRL_THREAD_STACK_SIZE (1 * 1024) + +static void sc_task(void *arg) +{ + int ret; + wlan_smart_config_status_t status; + wlan_smart_config_result_t result; + + memset(&result, 0, sizeof(result)); + + net_switch_mode(WLAN_MODE_MONITOR); + + status = wlan_smart_config_start(g_wlan_netif, SC_TIME_OUT, &result); + + net_switch_mode(WLAN_MODE_STA); + + if (status == WLAN_SMART_CONFIG_SUCCESS) { + CMD_DBG("ssid: %.32s\n", (char *)result.ssid); + CMD_DBG("psk: %s\n", (char *)result.passphrase); + CMD_DBG("random: %d\n", result.random_num); + } else { + CMD_DBG ("smartconfig failed %d\n", status); + OS_ThreadDelete(&g_sc_ctrl_thread); + return; + } + + if (result.passphrase[0] != '\0') { + wlan_sta_set(result.ssid, result.ssid_len, result.passphrase); + } else { + wlan_sta_set(result.ssid, result.ssid_len, NULL); + } + + wlan_sta_enable(); + + ret = wlan_smart_config_ack_start(g_wlan_netif, result.random_num, SC_ACK_TIME_OUT); + if (ret < 0) + CMD_ERR("smartconfig ack error, timeout\n"); + + OS_ThreadDelete(&g_sc_ctrl_thread); +} + +static int sc_create() +{ + if (OS_ThreadCreate(&g_sc_ctrl_thread, + "sc_thread", + sc_task, + NULL, + OS_THREAD_PRIO_APP, + SC_CTRL_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("create sc thread failed\n"); + return -1; + } + return 0; +} + +enum cmd_status cmd_smart_config_exec(char *cmd) +{ + int ret; + + if (g_wlan_netif == NULL) { + return CMD_STATUS_FAIL; + } + + if (cmd_strcmp(cmd, "start") == 0) { + if (OS_ThreadIsValid(&g_sc_ctrl_thread)) { + CMD_ERR("smartconfig already start\n"); + ret = -1; + } else { + ret = sc_create(); + } + } else if (cmd_strcmp(cmd, "stop") == 0) { + ret = wlan_smart_config_stop(); + } else if (cmd_strcmp(cmd, "set_key") == 0) { + ret = wlan_smart_config_set_key(key, WLAN_SMART_CONFIG_KEY_LEN); + CMD_DBG("Smartconfig set key : %s\n", key); + } else { + CMD_ERR("invalid argument '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + return (ret == 0 ? CMD_STATUS_OK : CMD_STATUS_FAIL); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_smart_config.h b/platform/mcu/xr871/project/common/cmd/cmd_smart_config.h new file mode 100644 index 0000000000..1a9750ccd3 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_smart_config.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_SMART_CONFIG_H_ +#define _CMD_SMART_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_smart_config_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_SMART_CONFIG_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_sntp.c b/platform/mcu/xr871/project/common/cmd/cmd_sntp.c new file mode 100644 index 0000000000..2c7e32d638 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_sntp.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_sntp.h" +#include "net/sntp/sntp.h" + +static OS_Thread_t g_sntp_thread; +#define SNTP_THREAD_STACK_SIZE (1 * 1024) +#define SNTP_THREAD_EXIT OS_ThreadDelete + +void sntp_run(void *arg) +{ + CMD_LOG(1, " \n"); + if (sntp_request(NULL) != 0) { + CMD_LOG(1, " \n"); + goto exit; + } + + sntp_time *time = (sntp_time *)sntp_obtain_time(); + CMD_LOG(1, " \n"); + CMD_LOG(1,"sntp(%u %u %u ",time->week, time->mon, time->day); + CMD_LOG(1,"%u:%u:%u %u)\n", time->hour, time->min, time->sec, time->year); +exit: + SNTP_THREAD_EXIT(&g_sntp_thread); + +} + +int sntp_start() +{ + if (OS_ThreadIsValid(&g_sntp_thread)) { + CMD_ERR("sntp task is running\n"); + return -1; + } + + if (OS_ThreadCreate(&g_sntp_thread, + "", + sntp_run, + NULL, + OS_THREAD_PRIO_APP, + SNTP_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("sntp task create failed\n"); + return -1; + } + + return 0; +} + +enum cmd_status cmd_sntp_exec(char *cmd) +{ + sntp_start(); + return CMD_STATUS_OK; +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_sntp.h b/platform/mcu/xr871/project/common/cmd/cmd_sntp.h new file mode 100644 index 0000000000..0e7642971d --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_sntp.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_SNTP_H_ +#define _CMD_SNTP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_sntp_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_SNTP_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_sysinfo.c b/platform/mcu/xr871/project/common/cmd/cmd_sysinfo.c new file mode 100644 index 0000000000..e31b4a7835 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_sysinfo.c @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "lwip/inet.h" +#include "common/framework/sysinfo.h" + +/* + * sysinfo default + * sysinfo save + * sysinfo load + * + * sysinfo get mac + * sysinfo set mac + * - sysinfo set mac 00:80:E1:29:E8:D1 + * + * sysinfo get sta ssid + * sysinfo set sta ssid + * - sysinfo set sta ssid ssid_example + * + * sysinfo get sta psk + * sysinfo set sta psk + * - sysinfo set sta psk psk_example + * + * sysinfo get ap ssid + * sysinfo set ap ssid + * - sysinfo set ap ssid ssid_example + * + * sysinfo get ap psk + * sysinfo set ap psk + * - sysinfo set ap psk psk_example + * + * sysinfo get sta dhcp + * sysinfo set sta dhcp + * - sysinfo set sta dhcp 1 + * + * sysinfo get sta ip + * sysinfo set sta ip + * - sysinfo set sta ip 192.168.51.100 + * + * sysinfo get sta mask + * sysinfo set sta mask + * - sysinfo set sta mask 255.255.255.0 + * + * sysinfo get sta gateway + * sysinfo set sta gateway + * - sysinfo set sta gateway 192.168.51.1 + * + * sysinfo get ap ip + * sysinfo set ap ip + * - sysinfo set ap ip 192.168.51.1 + * + * sysinfo get ap mask + * sysinfo set ap mask + * - sysinfo set ap mask 255.255.255.0 + * + * sysinfo get ap gateway + * sysinfo set ap gateway + * - sysinfo set ap gateway 192.168.51.1 + */ + +enum cmd_status cmd_sysinfo_default_exec(char *cmd) +{ + if (sysinfo_default() != 0) + return CMD_STATUS_FAIL; + else + return CMD_STATUS_OK; +} + +enum cmd_status cmd_sysinfo_save_exec(char *cmd) +{ + if (sysinfo_save() != 0) + return CMD_STATUS_FAIL; + else + return CMD_STATUS_OK; +} + +enum cmd_status cmd_sysinfo_load_exec(char *cmd) +{ + if (sysinfo_load() != 0) + return CMD_STATUS_FAIL; + else + return CMD_STATUS_OK; +} + +static int cmd_sysinfo_parse_int(const char *value, int min, int max, int *dst) +{ + int val; + char *end; + + val = cmd_strtol(value, &end, 0); + if (*end) { + CMD_ERR("Invalid number '%s'", value); + return -1; + } + + if (val < min || val > max) { + CMD_ERR("out of range value %d (%s), range is [%d, %d]\n", + val, value, min, max); + return -1; + } + + *dst = val; + return 0; +} + +static enum cmd_status cmd_sysinfo_set_mac(char *cmd, struct sysinfo *sysinfo) +{ + int i; + int cnt; + uint32_t mac[SYSINFO_MAC_ADDR_LEN]; + + cnt = cmd_sscanf(cmd, "%x:%x:%x:%x:%x:%x", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + if (cnt != 6) { + CMD_ERR("cnt %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + for (i = 0; i < SYSINFO_MAC_ADDR_LEN; i++) + sysinfo->mac_addr[i] = (uint8_t)mac[i]; + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_sysinfo_set_ssid(char *cmd, uint8_t *ssid, uint8_t *ssid_len) +{ + uint32_t len = cmd_strlen(cmd); + + if ((len == 0) || (len > SYSINFO_SSID_LEN_MAX)) { + CMD_ERR("len %d\n", len); + return CMD_STATUS_INVALID_ARG; + } + + cmd_memset(ssid, 0, SYSINFO_SSID_LEN_MAX); + cmd_memcpy(ssid, cmd, len); + *ssid_len = (uint8_t)len; + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_sysinfo_set_psk(char *cmd, uint8_t *psk) +{ + uint32_t len = cmd_strlen(cmd); + + if ((len < 8) || (len >= SYSINFO_PSK_LEN_MAX)) { + CMD_ERR("len %d\n", len); + return CMD_STATUS_INVALID_ARG; + } + + cmd_memset(psk, 0, SYSINFO_PSK_LEN_MAX); + cmd_memcpy(psk, cmd, len); + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_sysinfo_set_dhcp(char *cmd, struct sysinfo *sysinfo) +{ + int dhcp; + + if (cmd_sysinfo_parse_int(cmd, 0, 1, &dhcp) != 0) { + CMD_ERR("invalid dhcp '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + sysinfo->sta_use_dhcp = dhcp; + + return CMD_STATUS_OK; +} + +static enum cmd_status cmd_sysinfo_set_netif(char *cmd, ip_addr_t *addr) +{ + int cnt; + uint32_t val[4]; + + cnt = cmd_sscanf(cmd, "%u.%u.%u.%u", &val[0], &val[1], &val[2], &val[3]); + if (cnt != 4) { + CMD_ERR("cnt %d\n", cnt); + return CMD_STATUS_INVALID_ARG; + } + + if (((val[0] | val[1] | val[2] | val[3]) & 0xffffff00) != 0) { + CMD_ERR("val[0] %d, val[1] %d, val[2] %d, val[3] %d\n", + val[0], val[1], val[2], val[3]); + return CMD_STATUS_INVALID_ARG; + } + + IP4_ADDR(addr, val[0], val[1], val[2], val[3]); + + return CMD_STATUS_OK; +} + +enum cmd_status cmd_sysinfo_set_exec(char *cmd) +{ + struct sysinfo *sysinfo = sysinfo_get(); + if (sysinfo == NULL) { + CMD_ERR("sysinfo %p\n", sysinfo); + return CMD_STATUS_FAIL; + } + + if (cmd_strncmp(cmd, "mac ", 4) == 0) { + return cmd_sysinfo_set_mac(cmd + 4, sysinfo); + } else if (cmd_strncmp(cmd, "sta ", 4) == 0) { + if (cmd_strncmp(cmd + 4, "ssid ", 5) == 0) { + return cmd_sysinfo_set_ssid(cmd + 9, sysinfo->wlan_sta_param.ssid, + &(sysinfo->wlan_sta_param.ssid_len)); + } else if (cmd_strncmp(cmd + 4, "psk ", 4) == 0) { + return cmd_sysinfo_set_psk(cmd + 8, sysinfo->wlan_sta_param.psk); + } else if (cmd_strncmp(cmd + 4, "dhcp ", 5) == 0) { + return cmd_sysinfo_set_dhcp(cmd + 9, sysinfo); + } else if (cmd_strncmp(cmd + 4, "ip ", 3) == 0) { + return cmd_sysinfo_set_netif(cmd + 7, &sysinfo->netif_sta_param.ip_addr); + } else if (cmd_strncmp(cmd + 4, "mask ", 5) == 0) { + return cmd_sysinfo_set_netif(cmd + 9, &sysinfo->netif_sta_param.net_mask); + } else if (cmd_strncmp(cmd + 4, "gateway ", 8) == 0) { + return cmd_sysinfo_set_netif(cmd + 12, &sysinfo->netif_sta_param.gateway); + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + } else if (cmd_strncmp(cmd, "ap ", 3) == 0) { + if (cmd_strncmp(cmd + 3, "ssid ", 5) == 0) { + return cmd_sysinfo_set_ssid(cmd + 8, sysinfo->wlan_ap_param.ssid, + &(sysinfo->wlan_ap_param.ssid_len)); + } else if (cmd_strncmp(cmd + 3, "psk ", 4) == 0) { + return cmd_sysinfo_set_psk(cmd + 7, sysinfo->wlan_ap_param.psk); + } else if (cmd_strncmp(cmd + 3, "ip ", 3) == 0) { + return cmd_sysinfo_set_netif(cmd + 6, &sysinfo->netif_ap_param.ip_addr); + } else if (cmd_strncmp(cmd + 3, "mask ", 5) == 0) { + return cmd_sysinfo_set_netif(cmd + 8, &sysinfo->netif_ap_param.net_mask); + } else if (cmd_strncmp(cmd + 3, "gateway ", 8) == 0) { + return cmd_sysinfo_set_netif(cmd + 11, &sysinfo->netif_ap_param.gateway); + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + return CMD_STATUS_OK; +} + +enum cmd_status cmd_sysinfo_get_exec(char *cmd) +{ + struct sysinfo *sysinfo = sysinfo_get(); + if (sysinfo == NULL) { + CMD_ERR("sysinfo %p\n", sysinfo); + return CMD_STATUS_FAIL; + } + + if (cmd_strcmp(cmd, "mac") == 0) { + CMD_LOG(1, "MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + sysinfo->mac_addr[0], sysinfo->mac_addr[1], sysinfo->mac_addr[2], + sysinfo->mac_addr[3], sysinfo->mac_addr[4], sysinfo->mac_addr[5]); + } else if (cmd_strncmp(cmd, "sta ", 4) == 0) { + if (cmd_strcmp(cmd + 4, "ssid") == 0) { + CMD_LOG(1, "ssid: %.32s\n", sysinfo->wlan_sta_param.ssid); + } else if (cmd_strcmp(cmd + 4, "psk") == 0) { + CMD_LOG(1, "psk: %.64s\n", sysinfo->wlan_sta_param.psk); + } else if (cmd_strcmp(cmd + 4, "dhcp") == 0) { + CMD_LOG(1, "use dhcp: %d\n", sysinfo->sta_use_dhcp); + } else if (cmd_strcmp(cmd + 4, "ip") == 0) { + CMD_LOG(1, "ip: %s\n", inet_ntoa(sysinfo->netif_sta_param.ip_addr)); + } else if (cmd_strcmp(cmd + 4, "mask") == 0) { + CMD_LOG(1, "net mask: %s\n", inet_ntoa(sysinfo->netif_sta_param.net_mask)); + } else if (cmd_strcmp(cmd + 4, "gateway") == 0) { + CMD_LOG(1, "gateway: %s\n", inet_ntoa(sysinfo->netif_sta_param.gateway)); + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + } else if (cmd_strncmp(cmd, "ap ", 3) == 0) { + if (cmd_strcmp(cmd + 3, "ssid") == 0) { + CMD_LOG(1, "ssid: %.32s\n", sysinfo->wlan_ap_param.ssid); + } else if (cmd_strcmp(cmd + 3, "psk") == 0) { + CMD_LOG(1, "psk: %.64s\n", sysinfo->wlan_ap_param.psk); + } else if (cmd_strcmp(cmd + 3, "ip") == 0) { + CMD_LOG(1, "ip: %s\n", inet_ntoa(sysinfo->netif_ap_param.ip_addr)); + } else if (cmd_strcmp(cmd + 3, "mask") == 0) { + CMD_LOG(1, "net mask: %s\n", inet_ntoa(sysinfo->netif_ap_param.net_mask)); + } else if (cmd_strcmp(cmd + 3, "gateway") == 0) { + CMD_LOG(1, "gateway: %s\n", inet_ntoa(sysinfo->netif_ap_param.gateway)); + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + } else { + CMD_ERR("invalid arg '%s'\n", cmd); + return CMD_STATUS_INVALID_ARG; + } + + return CMD_STATUS_OK; +} + +static struct cmd_data g_sysinfo_cmds[] = { + { "default", cmd_sysinfo_default_exec}, + { "save", cmd_sysinfo_save_exec}, + { "load", cmd_sysinfo_load_exec}, + { "set", cmd_sysinfo_set_exec}, + { "get", cmd_sysinfo_get_exec}, +}; + +enum cmd_status cmd_sysinfo_exec(char *cmd) +{ + return cmd_exec(cmd, g_sysinfo_cmds, cmd_nitems(g_sysinfo_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_sysinfo.h b/platform/mcu/xr871/project/common/cmd/cmd_sysinfo.h new file mode 100644 index 0000000000..f723862f62 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_sysinfo.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_SYSINFO_H_ +#define _CMD_SYSINFO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_sysinfo_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_SYSINFO_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_timer.c b/platform/mcu/xr871/project/common/cmd/cmd_timer.c new file mode 100644 index 0000000000..77c5673760 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_timer.c @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_timer.h" +#include "driver/chip/hal_timer.h" + +enum cmd_timer_action { + CMD_TIMER_ACTION_DECONFIG, + CMD_TIMER_ACTION_START, + CMD_TIMER_ACTION_STOP, + CMD_TIMER_ACTION_PAUSE, + CMD_TIMER_ACTION_CONTINUE, + CMD_TIMER_ACTION_VALUE, +}; + +static void cmd_timer_callback(void *arg) +{ + cmd_write_event(CMD_EVENT_TIMER_NOTIFY, "timer %d notify @ %d ms", + (int)arg, OS_GetTicks()); +} + +/* + * drv timer config i= m= s= d= p= + */ +static enum cmd_status cmd_timer_config_exec(char *cmd) +{ + uint32_t id, clk_div, period; + char mode_str[8], clk_src_str[8]; + TIMER_Mode mode; + TIMER_ClkSrc clk_src; + TIMER_ClkPrescaler clk_prescaler; + TIMER_InitParam param; + int32_t cnt; + + cnt = cmd_sscanf(cmd, "i=%u m=%7s s=%7s d=%u p=%u", + &id, mode_str, clk_src_str, &clk_div, &period); + if (cnt != 5) { + return CMD_STATUS_INVALID_ARG; + } + + if (id >= TIMER_NUM) { + CMD_ERR("invalid id %d\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(mode_str, "repeat") == 0) { + mode = TIMER_MODE_REPEAT; + } else if (cmd_strcmp(mode_str, "once") == 0) { + mode = TIMER_MODE_ONCE; + } else { + CMD_ERR("invalid mode %s\n", mode_str); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(clk_src_str, "LF") == 0) { + clk_src = TIMER_CLK_SRC_LFCLK; + } else if (cmd_strcmp(clk_src_str, "HF") == 0) { + clk_src = TIMER_CLK_SRC_HFCLK; + } else { + CMD_ERR("invalid clk-src %s\n", clk_src_str); + return CMD_STATUS_INVALID_ARG; + } + + switch (clk_div) { + case 1: + clk_prescaler = TIMER_CLK_PRESCALER_1; + break; + case 2: + clk_prescaler = TIMER_CLK_PRESCALER_2; + break; + case 4: + clk_prescaler = TIMER_CLK_PRESCALER_4; + break; + case 8: + clk_prescaler = TIMER_CLK_PRESCALER_8; + break; + case 16: + clk_prescaler = TIMER_CLK_PRESCALER_16; + break; + case 32: + clk_prescaler = TIMER_CLK_PRESCALER_32; + break; + case 64: + clk_prescaler = TIMER_CLK_PRESCALER_64; + break; + case 128: + clk_prescaler = TIMER_CLK_PRESCALER_128; + break; + default: + CMD_ERR("invalid clk-div %u\n", clk_div); + return CMD_STATUS_INVALID_ARG; + } + + if (period == 0) { + CMD_ERR("invalid period %u\n", period); + return CMD_STATUS_INVALID_ARG; + } + + param.cfg = HAL_TIMER_MakeInitCfg(mode, clk_src, clk_prescaler); + param.period = period; + param.isEnableIRQ = 1; + param.callback = cmd_timer_callback; + param.arg = (void *)id; + if (HAL_TIMER_Init((TIMER_ID)id, ¶m) != HAL_OK) { + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +/* + * drv timer i= + */ +static enum cmd_status cmd_timer_action_exec(char *cmd, enum cmd_timer_action action) +{ + uint32_t id, tmp; + int32_t cnt; + enum cmd_status status; + + cnt = cmd_sscanf(cmd, "i=%u", &id); + if (cnt != 1) { + return CMD_STATUS_INVALID_ARG; + } + + if (id >= TIMER_NUM) { + CMD_ERR("invalid id %d\n", id); + return CMD_STATUS_INVALID_ARG; + } + + status = CMD_STATUS_OK; + switch (action) { + case CMD_TIMER_ACTION_DECONFIG: + HAL_TIMER_DeInit((TIMER_ID)id); + break; + case CMD_TIMER_ACTION_START: + HAL_TIMER_Start((TIMER_ID)id); + break; + case CMD_TIMER_ACTION_STOP: + HAL_TIMER_Stop((TIMER_ID)id); + break; + case CMD_TIMER_ACTION_PAUSE: + HAL_TIMER_Pause((TIMER_ID)id); + break; + case CMD_TIMER_ACTION_CONTINUE: + HAL_TIMER_Continue((TIMER_ID)id); + break; + case CMD_TIMER_ACTION_VALUE: + tmp = HAL_TIMER_GetCurrentValue((TIMER_ID)id); + cmd_write_respond(CMD_STATUS_OK, "value=%u", tmp); + status = CMD_STATUS_ACKED; + break; + default: + status = CMD_STATUS_INVALID_ARG; + break; + } + return status; +} + +/* + * drv timer deconfig i= + */ +static enum cmd_status cmd_timer_deconfig_exec(char *cmd) +{ + return cmd_timer_action_exec(cmd, CMD_TIMER_ACTION_DECONFIG); +} + +/* + * drv timer start i= + */ +static enum cmd_status cmd_timer_start_exec(char *cmd) +{ + return cmd_timer_action_exec(cmd, CMD_TIMER_ACTION_START); +} + +/* + * drv timer stop i= + */ +static enum cmd_status cmd_timer_stop_exec(char *cmd) +{ + return cmd_timer_action_exec(cmd, CMD_TIMER_ACTION_STOP); +} + +/* + * drv timer pause i= + */ +static enum cmd_status cmd_timer_pause_exec(char *cmd) +{ + return cmd_timer_action_exec(cmd, CMD_TIMER_ACTION_PAUSE); +} + +/* + * drv timer continue i= + */ +static enum cmd_status cmd_timer_continue_exec(char *cmd) +{ + return cmd_timer_action_exec(cmd, CMD_TIMER_ACTION_CONTINUE); +} + +/* + * drv timer value i= + */ +static enum cmd_status cmd_timer_value_exec(char *cmd) +{ + return cmd_timer_action_exec(cmd, CMD_TIMER_ACTION_VALUE); +} + + +static struct cmd_data g_timer_cmds[] = { + { "config", cmd_timer_config_exec }, + { "deconfig", cmd_timer_deconfig_exec }, + { "start", cmd_timer_start_exec }, + { "stop", cmd_timer_stop_exec }, + { "pause", cmd_timer_pause_exec }, + { "continue", cmd_timer_continue_exec }, + { "value", cmd_timer_value_exec }, +}; + +enum cmd_status cmd_timer_exec(char *cmd) +{ + return cmd_exec(cmd, g_timer_cmds, cmd_nitems(g_timer_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_timer.h b/platform/mcu/xr871/project/common/cmd/cmd_timer.h new file mode 100644 index 0000000000..3314c1cc4c --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_timer.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_TIMER_H_ +#define _CMD_TIMER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_timer_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_TIMER_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_uart.c b/platform/mcu/xr871/project/common/cmd/cmd_uart.c new file mode 100644 index 0000000000..6f3c8361fc --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_uart.c @@ -0,0 +1,385 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_uart.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_uart.h" + + +typedef int32_t (*uart_receive_func)(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec); +typedef int32_t (*uart_transmit_func)(UART_ID uartID, uint8_t *buf, int32_t size); + +#define CMD_UART_TRANSFER_BUF_SIZE 2048 +#define CMD_UART_QUEUE_LEN 1 +#define CMD_UART_TRANSFER_THREAD_STACK_SIZE (1 * 1024) + +struct cmd_uart_msg { + int32_t len; + uint32_t timeout; +}; + +enum cmd_uart_transfer_mode { + CMD_UART_TRANSFER_MODE_IT = 0, + CMD_UART_TRANSFER_MODE_DMA, + CMD_UART_TRANSFER_MODE_POLL, +}; + +struct cmd_uart_priv { + UART_ID id; + enum cmd_uart_transfer_mode mode; + OS_Queue_t queue; + OS_Thread_t thread; +}; + +struct cmd_uart_priv g_cmd_uart_priv; + +UART_DataBits uart_data_bits[4] = { + UART_DATA_BITS_5, UART_DATA_BITS_6, UART_DATA_BITS_7, UART_DATA_BITS_8 +}; + +UART_StopBits uart_stop_bits[2] = { UART_STOP_BITS_1, UART_STOP_BITS_2 }; + +/* + * drv uart config i= b= d= p= s= f= + */ +static enum cmd_status cmd_uart_config_exec(char *cmd) +{ + uint32_t id, baud_rate, data_bits, stop_bits; + char parity[8]; + char flow_ctrl[8]; + int cnt; + UART_Parity uart_parity; + UART_InitParam uart_param; + + cnt = cmd_sscanf(cmd, "i=%u b=%u d=%u p=%7s s=%u f=%7s", &id, &baud_rate, + &data_bits, parity, &stop_bits, flow_ctrl); + if (cnt != 6) { + return CMD_STATUS_INVALID_ARG; + } + + if (id >= UART_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if (baud_rate < 110 || baud_rate > 921600) { + CMD_ERR("invalid baud rate %u\n", baud_rate); + return CMD_STATUS_INVALID_ARG; + } + + if (data_bits < 5 || data_bits > 8) { + CMD_ERR("invalid data bits %u\n", data_bits); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(parity, "none") == 0) { + uart_parity = UART_PARITY_NONE; + } else if (cmd_strcmp(parity, "odd") == 0) { + uart_parity = UART_PARITY_ODD; + } else if (cmd_strcmp(parity, "even") == 0) { + uart_parity = UART_PARITY_EVEN; + } else { + CMD_ERR("invalid parity %s\n", parity); + return CMD_STATUS_INVALID_ARG; + } + + if (stop_bits < 1 || stop_bits > 2) { + CMD_ERR("invalid stop bits %u\n", stop_bits); + return CMD_STATUS_INVALID_ARG; + } + + if (cmd_strcmp(flow_ctrl, "none") != 0) { + CMD_ERR("invalid flow contorl %s\n", flow_ctrl); + return CMD_STATUS_INVALID_ARG; + } + + HAL_UART_DeInit((UART_ID)id); + uart_param.baudRate = baud_rate; + uart_param.parity = uart_parity; + uart_param.stopBits = uart_stop_bits[stop_bits - 1]; + uart_param.dataBits = uart_data_bits[data_bits - 5]; + uart_param.isAutoHwFlowCtrl = 0; + HAL_UART_Init((UART_ID)id, &uart_param); + + return CMD_STATUS_OK; +} + +static void cmd_uart_transfer_task(void *arg) +{ + struct cmd_uart_priv *priv = arg; + struct cmd_uart_msg msg; + uart_receive_func rx_func; + uart_transmit_func tx_func; + uint8_t *buf = NULL; + int32_t cnt; + + if (priv->mode == CMD_UART_TRANSFER_MODE_IT) { + rx_func = HAL_UART_Receive_IT; + tx_func = HAL_UART_Transmit_IT; + } else if (priv->mode == CMD_UART_TRANSFER_MODE_DMA) { + rx_func = HAL_UART_Receive_DMA; + tx_func = HAL_UART_Transmit_DMA; + } else if (priv->mode == CMD_UART_TRANSFER_MODE_POLL) { + rx_func = HAL_UART_Receive_Poll; + tx_func = HAL_UART_Transmit_Poll; + } else { + CMD_ERR("invalid mode %d\n", priv->mode); + goto out; + } + + buf = cmd_malloc(CMD_UART_TRANSFER_BUF_SIZE); + if (buf == NULL) { + CMD_ERR("no memory\n"); + goto out; + } + + if (priv->mode == CMD_UART_TRANSFER_MODE_DMA) { + if (HAL_UART_EnableRxDMA(priv->id) != HAL_OK) { + CMD_ERR("enable rx dma fail\n"); + goto out; + } + if (HAL_UART_EnableTxDMA(priv->id) != HAL_OK) { + CMD_ERR("enable tx dma fail\n"); + HAL_UART_DisableRxDMA(priv->id); + goto out; + } + } + + while (1) { + if (OS_QueueReceive(&priv->queue, &msg, OS_WAIT_FOREVER) != OS_OK) { + CMD_ERR("wait msg fail\n"); + continue; + } + + if (msg.len <= 0) { + CMD_DBG("uart transfer test end\n"); + break; + } + + cnt = rx_func(priv->id, buf, msg.len, msg.timeout); + if (cnt > 0) { + tx_func(priv->id, buf, cnt); + } + } + + if (priv->mode == CMD_UART_TRANSFER_MODE_DMA) { + HAL_UART_DisableTxDMA(priv->id); + HAL_UART_DisableRxDMA(priv->id); + } + +out: + if (buf) + cmd_free(buf); + + CMD_DBG("%s() exit\n", __func__); + OS_ThreadDelete(&priv->thread); +} + +/* + * drv uart transfer-start i= m= + */ +static enum cmd_status cmd_uart_transfer_start_exec(char *cmd) +{ + int32_t cnt; + uint32_t id; + char mode[8]; + struct cmd_uart_priv *priv = &g_cmd_uart_priv; + + if (OS_ThreadIsValid(&priv->thread)) { + CMD_ERR("uart transfer already start\n"); + return CMD_STATUS_FAIL; + } + + cnt = cmd_sscanf(cmd, "i=%u m=%7s", &id, mode); + if (cnt != 2) { + return CMD_STATUS_INVALID_ARG; + } + + if (id >= UART_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } else { + priv->id = (UART_ID)id; + } + + if (cmd_strcmp(mode, "it") == 0) { + priv->mode = CMD_UART_TRANSFER_MODE_IT; + } else if (cmd_strcmp(mode, "dma") == 0) { + priv->mode = CMD_UART_TRANSFER_MODE_DMA; + } else if (cmd_strcmp(mode, "poll") == 0) { + priv->mode = CMD_UART_TRANSFER_MODE_POLL; + } else { + CMD_ERR("invalid mode %s\n", mode); + return CMD_STATUS_INVALID_ARG; + } + + if (OS_QueueCreate(&priv->queue, + CMD_UART_QUEUE_LEN, + sizeof(struct cmd_uart_msg)) != OS_OK) { + CMD_ERR("create queue failed\n"); + return CMD_STATUS_FAIL; + } + + if (OS_ThreadCreate(&priv->thread, + "", + cmd_uart_transfer_task, + priv, + OS_PRIORITY_NORMAL, + CMD_UART_TRANSFER_THREAD_STACK_SIZE) != OS_OK) { + CMD_ERR("create transfer task failed\n"); + OS_QueueDelete(&priv->queue); + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +/* + * drv uart transfer-data i= l= t= + */ +static enum cmd_status cmd_uart_transfer_data_exec(char *cmd) +{ + int32_t cnt; + uint32_t id, len, timeout; + struct cmd_uart_msg msg; + struct cmd_uart_priv *priv = &g_cmd_uart_priv; + + if (!OS_ThreadIsValid(&priv->thread)) { + CMD_ERR("uart transfer not started\n"); + return CMD_STATUS_FAIL; + } + + cnt = cmd_sscanf(cmd, "i=%u l=%u t=%u", &id, &len, &timeout); + if (cnt != 3) { + return CMD_STATUS_INVALID_ARG; + } + + if (id != priv->id) { + CMD_ERR("invalid id %u, != %d\n", id, priv->id); + return CMD_STATUS_INVALID_ARG; + } + + if (len == 0 || len > CMD_UART_TRANSFER_BUF_SIZE) { + CMD_ERR("invalid data-length %u\n", len); + return CMD_STATUS_INVALID_ARG; + } + + if (timeout == 0) { + timeout = HAL_WAIT_FOREVER; + } + + msg.len = len; + msg.timeout = timeout; + if (OS_QueueSend(&priv->queue, &msg, 0) != OS_OK) + return CMD_STATUS_FAIL; + else + return CMD_STATUS_OK; +} + +/* + * drv uart transfer-stop i= + */ +static enum cmd_status cmd_uart_transfer_stop_exec(char *cmd) +{ + int32_t cnt; + uint32_t id; + struct cmd_uart_msg msg; + struct cmd_uart_priv *priv = &g_cmd_uart_priv; + + if (!OS_ThreadIsValid(&priv->thread)) { + CMD_ERR("uart transfer not started\n"); + return CMD_STATUS_FAIL; + } + + cnt = cmd_sscanf(cmd, "i=%u", &id); + if (cnt != 1) { + return CMD_STATUS_INVALID_ARG; + } + + if (id != priv->id) { + CMD_ERR("invalid id %u, != %d\n", id, priv->id); + return CMD_STATUS_INVALID_ARG; + } + + msg.len = 0; /* trigger transfer test end */ + msg.timeout = 0; + if (OS_QueueSend(&priv->queue, &msg, OS_WAIT_FOREVER) != OS_OK) + return CMD_STATUS_FAIL; + + while (OS_ThreadIsValid(&priv->thread)) { + OS_MSleep(1); /* wait for thread termination */ + } + + OS_QueueDelete(&priv->queue); + return CMD_STATUS_OK; +} + +/* + * drv uart sendbreak i= t= + */ +static enum cmd_status cmd_uart_sendbreak_exec(char *cmd) +{ + uint32_t id, break_len; + int32_t cnt; + + cnt = cmd_sscanf(cmd, "i=%u t=%u", &id, &break_len); + if (cnt != 2) { + return CMD_STATUS_INVALID_ARG; + } + + if (id >= UART_NUM) { + CMD_ERR("invalid id %u\n", id); + return CMD_STATUS_INVALID_ARG; + } + + if (break_len < 1 || break_len > 5000) { + CMD_ERR("invalid break length %u\n", break_len); + return CMD_STATUS_INVALID_ARG; + } + + HAL_UART_SetBreakCmd((UART_ID)id, 1); + OS_MSleep(break_len); + HAL_UART_SetBreakCmd((UART_ID)id, 0); + + return CMD_STATUS_OK; +} + +static struct cmd_data g_uart_cmds[] = { + { "config", cmd_uart_config_exec }, + { "transfer-start", cmd_uart_transfer_start_exec }, + { "transfer-data", cmd_uart_transfer_data_exec }, + { "transfer-stop", cmd_uart_transfer_stop_exec }, + { "sendbreak", cmd_uart_sendbreak_exec }, +}; + +enum cmd_status cmd_uart_exec(char *cmd) +{ + return cmd_exec(cmd, g_uart_cmds, cmd_nitems(g_uart_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_uart.h b/platform/mcu/xr871/project/common/cmd/cmd_uart.h new file mode 100644 index 0000000000..24fae5ec93 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_uart.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_UART_H_ +#define _CMD_UART_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_uart_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_UART_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_upgrade.c b/platform/mcu/xr871/project/common/cmd/cmd_upgrade.c new file mode 100644 index 0000000000..8cd67566ff --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_upgrade.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "driver/chip/hal_prcm.h" + +#define CMD_REBOOT_BY_WDG 1 + +#if CMD_REBOOT_BY_WDG + +#include "driver/chip/hal_wdg.h" + +enum cmd_status cmd_reboot(PRCM_CPUABootFlag flag) +{ + cmd_write_respond(CMD_STATUS_OK, cmd_get_status_desc(CMD_STATUS_OK)); + + HAL_PRCM_SetCPUABootFlag(flag); + HAL_WDG_Reboot(); + return CMD_STATUS_ACKED; +} + +#else /* CMD_REBOOT_BY_WDG */ + +#include "driver/chip/hal_nvic.h" +#include "driver/chip/hal_global.h" +#include "driver/chip/system_chip.h" +#include "sys/interrupt.h" + +#define CMD_BROM_RESET_HANDLER (*((volatile uint32_t *)0x4)) + +enum cmd_status cmd_reboot(PRCM_CPUABootFlag flag) +{ + uint32_t handler; + + cmd_write_respond(CMD_STATUS_OK, cmd_get_status_desc(CMD_STATUS_OK)); + cmd_msleep(10); + + HAL_PRCM_SetCPUABootFlag(flag); + handler = CMD_BROM_RESET_HANDLER; +#ifdef __CONFIG_CHIP_XR871 + handler |= 0x1; /* set thumb bit */ +#endif + + arch_irq_disable(); + HAL_PRCM_DisableSys2(); + HAL_PRCM_DisableSys2Power(); + HAL_GlobalInit(); + SystemDeInit(0); + + SCB->VTOR = 0x0; + __set_CONTROL(0); /* reset to Privileged Thread mode and use MSP */ + __DSB(); + __ISB(); + ((NVIC_IRQHandler)handler)(); + return CMD_STATUS_ACKED; +} + +#endif /* CMD_REBOOT_BY_WDG */ + +enum cmd_status cmd_reboot_exec(char *cmd) +{ + return cmd_reboot(PRCM_CPUA_BOOT_FROM_COLD_RESET); +} + +enum cmd_status cmd_upgrade_exec(char *cmd) +{ + return cmd_reboot(PRCM_CPUA_BOOT_FROM_SYS_UPDATE); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_upgrade.h b/platform/mcu/xr871/project/common/cmd/cmd_upgrade.h new file mode 100644 index 0000000000..4df30b8f39 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_upgrade.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_UPGRADE_H_ +#define _CMD_UPGRADE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_upgrade_exec(char *cmd); +enum cmd_status cmd_reboot_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_UPGRADE_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_util.c b/platform/mcu/xr871/project/common/cmd/cmd_util.c new file mode 100644 index 0000000000..02fc12b535 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_util.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include + + +/* cmd format: ... */ +enum cmd_status cmd_exec(char *cmd, struct cmd_data *cdata, int count) +{ + int i; + char *args; + + args = cmd_strchr(cmd, ' '); + if (args) { + *args++ = '\0'; /* has arguments */ + } + + for (i = 0; i < count; ++i, ++cdata) { + if (cmd_strcmp(cmd, cdata->name) == 0) { + return cdata->exec(args ? args : ""); + } + } + + CMD_ERR("unknown cmd '%s'\n", cmd); + return CMD_STATUS_UNKNOWN_CMD; +} + +/* cmd2 format: [ ...] */ +enum cmd_status cmd2_exec(char *cmd, struct cmd2_data *cdata, int count) +{ + int i; + + for (i = 0; i < count; ++i, ++cdata) { + if (cmd_strncmp(cmd, cdata->name, cdata->name_len) == 0) { + return cdata->exec(cmd + cdata->name_len); + } + } + + CMD_ERR("unknown cmd '%s'\n", cmd); + return CMD_STATUS_UNKNOWN_CMD; +} + +/* parse all argument vectors from a command string, return argument count */ +int cmd_parse_argv(char *cmd, char *argv[], int size) +{ + int last, argc; + char *start, *end; + + argc = 0; + start = cmd; + + while (argc < size && *start != '\0') { + while (*start == ' ' || *start == '\t') + start++; + if (*start == '\0') + break; + end = start; + while (*end != ' ' && *end != '\t' && *end != '\0') + end++; + last = *end == '\0'; + *end = '\0'; + argv[argc++] = start; + if (last) + break; + start = end + 1; + } + + if (argc > 0 && argc < size) { + argv[argc] = NULL; /* ANSI-C requirement */ + } + + return argc; +} + +static const char *cmd_status_success_desc[CMD_STATUS_SUCCESS_MAX + 1 - + CMD_STATUS_SUCCESS_MIN] = { + "OK", +}; + +static const char *cmd_status_error_desc[CMD_STATUS_ERROR_MAX + 1 - + CMD_STATUS_ERROR_MIN] = { + "Unknown command", + "Invalid argument", + "Fail", +}; + +static const char *cmd_empty_desc = ""; + +const char *cmd_get_status_desc(enum cmd_status status) +{ + if (status >= CMD_STATUS_SUCCESS_MIN && + status <= CMD_STATUS_SUCCESS_MAX) { + return cmd_status_success_desc[status - CMD_STATUS_SUCCESS_MIN]; + } else if (status >= CMD_STATUS_ERROR_MIN && + status <= CMD_STATUS_ERROR_MAX) { + return cmd_status_error_desc[status - CMD_STATUS_ERROR_MIN]; + } + + return cmd_empty_desc; +} + +#if 0 +static const char *cmd_event_desc[CMD_EVENT_MAX + 1 - CMD_EVENT_MIN] = { + "Test finish", + "timer notify" +}; + +const char *cmd_get_event_desc(enum cmd_event event) +{ + if (event >= CMD_EVENT_MIN && event <= CMD_EVENT_MAX) { + return cmd_event_desc[event - CMD_EVENT_MIN]; + } + + return cmd_empty_desc; +} +#endif + +int cmd_write(enum cmd_code_type type, int code, const char *fmt, ...) +{ + static char str_buf[400]; + + va_list ap; + int len, left; + char *ptr; + + ptr = str_buf; + left = sizeof(str_buf) - 1; /* reserve 1 byte for '\n' */ + len = cmd_snprintf(ptr, left, "<%s> %d ", + type == CMD_CODE_TYEP_STATUS ? "ACK" : "EVT", code); + + ptr += len; + left -= len; + va_start(ap, fmt); + len = vsnprintf(ptr, left, fmt, ap); + va_end(ap); + + ptr += len; + left -= len; + left += 1; + len = cmd_snprintf(ptr, left, "\n"); + + left -= len; + len = sizeof(str_buf) - left; + + return console_write((uint8_t *)str_buf, len); +} + +int32_t cmd_raw_mode_read(uint8_t *buf, int32_t size, uint32_t msec) +{ + UART_ID uart_id = console_get_uart_id(); + + if (uart_id < UART_NUM) { + return HAL_UART_Receive_Poll(uart_id, buf, size, msec); + } else { + return -1; + } +} + +int32_t cmd_raw_mode_write(uint8_t *buf, int32_t size) +{ + UART_ID uart_id = console_get_uart_id(); + + if (uart_id < UART_NUM) { + return HAL_UART_Transmit_Poll(uart_id, buf, size); + } else { + return -1; + } +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_util.h b/platform/mcu/xr871/project/common/cmd/cmd_util.h new file mode 100644 index 0000000000..95856f31ab --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_util.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_UTIL_H_ +#define _CMD_UTIL_H_ + +#include +#include +#include "sys/param.h" +#include "cmd_defs.h" +#include "cmd_debug.h" +#include "console/console.h" +#include "kernel/os/os.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* command format: ... */ +struct cmd_data { + char *name; + enum cmd_status (*exec)(char *); +}; + +/* command2 format: [ ...] */ +struct cmd2_data { + char *name; + int name_len; + enum cmd_status (*exec)(char *); +}; + +enum cmd_status cmd_exec(char *cmd, struct cmd_data *cdata, int count); +enum cmd_status cmd2_exec(char *cmd, struct cmd2_data *cdata, int count); + +int cmd_parse_argv(char *cmd, char *argv[], int size); + +const char *cmd_get_status_desc(enum cmd_status status); +//const char *cmd_get_event_desc(enum cmd_event event); + +int cmd_write(enum cmd_code_type type, int code, const char *fmt, ...); + +#define cmd_write_respond(status, fmt, arg...) \ + cmd_write(CMD_CODE_TYEP_STATUS, (int)status, fmt, ##arg) + +#define cmd_write_event(event, fmt, arg...) \ + cmd_write(CMD_CODE_TYEP_EVENT, (int)event, fmt, ##arg) + +int32_t cmd_raw_mode_read(uint8_t *buf, int32_t size, uint32_t msec); +int32_t cmd_raw_mode_write(uint8_t *buf, int32_t size); + +#define cmd_raw_mode_enable() console_disable(); +#define cmd_raw_mode_disable() console_enable(); + + +#define cmd_malloc(l) malloc(l) +#define cmd_free(p) free(p) + +#define cmd_memcpy(d, s, n) memcpy(d, s, n) +#define cmd_memset(s, c, n) memset(s, c, n) +#define cmd_memcmp(s1, s2, n) memcmp(s1, s2, n) + +#define cmd_strlen(s) strlen(s) +#define cmd_strcmp(s1, s2) strcmp(s1, s2) +#define cmd_strncmp(s1, s2, n) strncmp(s1, s2, n) +#define cmd_strcasecmp(s1, s2) strcasecmp(s1, s2) +#define cmd_strncasecmp(s1, s2, n) strncasecmp(s1, s2, n) +#define cmd_strchr(s, c) strchr(s, c) +#define cmd_strrchr(s, c) strrchr(s, c) +#define cmd_strstr(s1, s2) strstr(s1, s2) +#define cmd_strtol(s, p, b) strtol(s, p, b) +#define cmd_strdup(s) strdup(s) +#define cmd_strlcpy(d, s, n) strlcpy(d, s, n) + +#define cmd_atoi(s) atoi(s) +#define cmd_atol(s) atol(s) + +#define cmd_sscanf(s, f, a...) sscanf(s, f, ##a) +#define cmd_sprintf(s, f, a...) sprintf(s, f, ##a) +#define cmd_snprintf(s, n, f, a...) snprintf(s, n, f, ##a) + +#define cmd_nitems(a) nitems(a) + +#define cmd_msleep(msec) OS_MSleep(msec) + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_UTIL_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_wdg.c b/platform/mcu/xr871/project/common/cmd/cmd_wdg.c new file mode 100644 index 0000000000..8698c121cb --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_wdg.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cmd_util.h" +#include "cmd_wdg.h" +#include "driver/chip/hal_wdg.h" + +static void cmd_wdg_callback(void *arg) +{ + cmd_write_event(CMD_EVENT_WDG_TIMEOUT, "wdg timeout @ %d ms", OS_GetTicks()); +} + +/* + * drv wdg config m= t= + */ +static enum cmd_status cmd_wdg_config_exec(char *cmd) +{ + char mode_str[8]; + uint32_t timeout; + WDG_InitParam param; + int32_t cnt; + + cnt = cmd_sscanf(cmd, "m=%7s t=%u", mode_str, &timeout); + if (cnt != 2) { + return CMD_STATUS_INVALID_ARG; + } + + cmd_memset(¶m, 0, sizeof(param)); + + if (cmd_strcmp(mode_str, "reset") == 0) { + param.event = WDG_EVT_RESET; + param.resetCycle = WDG_DEFAULT_RESET_CYCLE; + } else if (cmd_strcmp(mode_str, "it") == 0) { + param.event = WDG_EVT_INTERRUPT; + param.callback = cmd_wdg_callback; + param.arg = NULL; + } else { + CMD_ERR("invalid mode %s\n", mode_str); + return CMD_STATUS_INVALID_ARG; + } + + if (timeout > 11) { + CMD_ERR("invalid timeout %u\n", timeout); + return CMD_STATUS_INVALID_ARG; + } else { + param.timeout = (timeout << WDG_TIMEOUT_SHIFT) & WDG_TIMEOUT_MASK; + } + + if (HAL_WDG_Init(¶m) != HAL_OK) { + return CMD_STATUS_FAIL; + } + + return CMD_STATUS_OK; +} + +/* + * drv wdg deconfig + */ +static enum cmd_status cmd_wdg_deconfig_exec(char *cmd) +{ + HAL_WDG_DeInit(); + return CMD_STATUS_OK; +} + +/* + * drv wdg start + */ +static enum cmd_status cmd_wdg_start_exec(char *cmd) +{ + HAL_WDG_Start(); + return CMD_STATUS_OK; +} + +/* + * drv wdg stop + */ +static enum cmd_status cmd_wdg_stop_exec(char *cmd) +{ + HAL_WDG_Stop(); + return CMD_STATUS_OK; +} + +/* + * drv wdg feed + */ +static enum cmd_status cmd_wdg_feed_exec(char *cmd) +{ + HAL_WDG_Feed(); + return CMD_STATUS_OK; +} + +/* + * drv wdg reboot + */ +static enum cmd_status cmd_wdg_reboot_exec(char *cmd) +{ + HAL_WDG_Reboot(); + return CMD_STATUS_OK; +} + +static struct cmd_data g_wdg_cmds[] = { + { "config", cmd_wdg_config_exec }, + { "deconfig", cmd_wdg_deconfig_exec }, + { "start", cmd_wdg_start_exec }, + { "stop", cmd_wdg_stop_exec }, + { "feed", cmd_wdg_feed_exec }, + { "reboot", cmd_wdg_reboot_exec }, +}; + +enum cmd_status cmd_wdg_exec(char *cmd) +{ + return cmd_exec(cmd, g_wdg_cmds, cmd_nitems(g_wdg_cmds)); +} diff --git a/platform/mcu/xr871/project/common/cmd/cmd_wdg.h b/platform/mcu/xr871/project/common/cmd/cmd_wdg.h new file mode 100644 index 0000000000..a10c704a5a --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_wdg.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_WDG_H_ +#define _CMD_WDG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_wdg_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_WDG_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/cmd_wlan.c b/platform/mcu/xr871/project/common/cmd/cmd_wlan.c new file mode 100644 index 0000000000..be9f2607b0 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_wlan.c @@ -0,0 +1,1041 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * net mode + * - net mode sta + * - net mode ap + * - net mode mon + */ + +/* + * net sta config [psk] + * - net sta config ssid_example + * - net sta config ssid_example psk_example + * + * net sta set + * - net sta set ssid ssid_example + * - net sta set psk psk_example + * - net sta set wep_key0 wep_key_example + * - net sta set wep_key1 wep_key_example + * - net sta set wep_key2 wep_key_example + * - net sta set wep_key3 wep_key_example + * - net sta set wep_key_index <0, 1, 2, 3> + * - net sta set key_mgmt {WPA-PSK, NONE} + * - net sta set pairwise {CCMP, TKIP, WEP40, WEP104, NONE} + * - net sta set group {CCMP, TKIP, WEP40, WEP104, NONE} + * - net sta set proto {WPA, RSN} + * - net sta set auth_alg {OPEN, SHARED} + * - net sta set ptk_rekey + * - net sta set scan_ssid (0, 1) + * + * net sta get + * - net sta get ssid + * - net sta get psk + * - net sta get wep_key0 + * - net sta get wep_key1 + * - net sta get wep_key2 + * - net sta get wep_key3 + * - net sta get wep_key_index + * - net sta get key_mgmt + * - net sta get pairwise + * - net sta get group + * - net sta get proto + * - net sta get auth_alg + * - net sta get ptk_rekey + * - net sta get scan_ssid + * + * net sta enable + * net sta disable + * + * net sta scan once + * net sta scan result + * net sta scan interval + * net sta bss flush + * + * net sta connect + * net sta disconnect + * net sta state + * net sta ap + * + * net sta wps pbc + * net sta wps pin get + * net sta wps pin set + */ + +/* + * net ap config [psk] + * - net ap config ssid_example + * - net ap config ssid_example psk_example + * + * net ap set + * - net ap set ssid ssid_example + * - net ap set psk psk_example + * - net ap set key_mgmt {WPA-PSK, NONE} + * - net ap set wpa {CCMP, TKIP, NONE} + * - net ap set rsn {CCMP, TKIP, NONE} + * - net ap set proto + * - net ap set auth_alg {OPEN} + * - net ap set group_rekey + * - net ap set strict_rekey <0, 1> + * - net ap set gmk_rekey + * - net ap set ptk_rekey + * - net ap set hw_mode + * - net ap set 80211n <0, 1> + * - net ap set channel <1 ~ 13> + * - net ap set beacon_int <15 ~ 65535> + * - net ap set dtim <1 ~ 255> + * - net ap set max_num_sta + * + * net ap get + * - net ap get ssid + * - net ap get psk + * - net ap get key_mgmt + * - net ap get wpa + * - net ap get rsn + * - net ap get proto + * - net ap get auth_alg + * - net ap get group_rekey + * - net ap get strict_rekey + * - net ap get gmk_rekey + * - net ap get ptk_rekey + * - net ap get hw_mode + * - net ap get 80211n + * - net ap get channel + * - net ap get beacon_int + * - net ap get dtim + * - net ap get max_num_sta + * + * net ap enable + * net ap reload + * net ap disable + * + * net ap sta num + * net ap sta info + */ + +#include "cmd_util.h" +#include "net/wlan/wlan.h" +#include "net/wlan/wlan_defs.h" +#include "common/framework/net_ctrl.h" + +#ifdef __PRJ_CONFIG_WLAN_STA_AP +static const char *g_wlan_mode_str[WLAN_MODE_NUM] = { + [WLAN_MODE_STA] = "station", + [WLAN_MODE_HOSTAP] = "hostap", + [WLAN_MODE_MONITOR] = "monitor", +}; + +enum cmd_status cmd_wlan_mode_exec(char *cmd) +{ + enum wlan_mode cur_mode, new_mode; + const char *mode_str; + + if (cmd_strcmp(cmd, "") == 0) { + cur_mode = wlan_if_get_mode(g_wlan_netif); + if (cur_mode < WLAN_MODE_NUM) { + mode_str = g_wlan_mode_str[cur_mode]; + } else { + mode_str = "invalid"; + } + cmd_write_respond(CMD_STATUS_OK, "%s", mode_str); + return CMD_STATUS_ACKED; + } + + if (cmd_strcmp(cmd, "sta") == 0) { + new_mode = WLAN_MODE_STA; + } else if (cmd_strcmp(cmd, "ap") == 0) { + new_mode = WLAN_MODE_HOSTAP; + } else if (cmd_strcmp(cmd, "mon") == 0) { + new_mode = WLAN_MODE_MONITOR; + } else { + return CMD_STATUS_INVALID_ARG; + } + + cmd_write_respond(CMD_STATUS_OK, "OK"); + net_switch_mode(new_mode); + + return CMD_STATUS_ACKED; +} +#endif /* __PRJ_CONFIG_WLAN_STA_AP */ + +/* wpas parse */ + +static int cmd_wpas_parse_int(const char *value, int min, int max, int *dst) +{ + int val; + char *end; + + val = cmd_strtol(value, &end, 0); + if (*end) { + CMD_ERR("Invalid number '%s'", value); + return -1; + } + + if (val < min || val > max) { + CMD_ERR("out of range value %d (%s), range is [%d, %d]\n", + val, value, min, max); + return -1; + } + + *dst = val; + return 0; +} + +static int cmd_wpas_parse_key_mgmt(const char *value) +{ + int val = 0, last, errors = 0; + char *start, *end, *buf; + + buf = cmd_strdup(value); + if (buf == NULL) + return -1; + start = buf; + + while (*start != '\0') { + while (*start == ' ' || *start == '\t') + start++; + if (*start == '\0') + break; + end = start; + while (*end != ' ' && *end != '\t' && *end != '\0') + end++; + last = *end == '\0'; + *end = '\0'; + if (cmd_strcmp(start, "WPA-PSK") == 0) + val |= WPA_KEY_MGMT_PSK; + else if (cmd_strcmp(start, "WPA-EAP") == 0) + val |= WPA_KEY_MGMT_IEEE8021X; + else if (cmd_strcmp(start, "IEEE8021X") == 0) + val |= WPA_KEY_MGMT_IEEE8021X_NO_WPA; + else if (cmd_strcmp(start, "NONE") == 0) + val |= WPA_KEY_MGMT_NONE; + else if (cmd_strcmp(start, "WPA-NONE") == 0) + val |= WPA_KEY_MGMT_WPA_NONE; + else { + CMD_DBG("Invalid key_mgmt '%s'", start); + errors++; + } + + if (last) + break; + start = end + 1; + } + cmd_free(buf); + + if (val == 0) { + CMD_DBG("No key_mgmt values configured\n"); + errors++; + } + + CMD_DBG("key_mgmt: 0x%x\n", val); + return errors ? -1 : val; +} + +static int cmd_wpas_parse_cipher(const char *value) +{ + int val = 0, last; + char *start, *end, *buf; + + buf = cmd_strdup(value); + if (buf == NULL) + return -1; + start = buf; + + while (*start != '\0') { + while (*start == ' ' || *start == '\t') + start++; + if (*start == '\0') + break; + end = start; + while (*end != ' ' && *end != '\t' && *end != '\0') + end++; + last = *end == '\0'; + *end = '\0'; + if (cmd_strcmp(start, "CCMP-256") == 0) + val |= WPA_CIPHER_CCMP_256; + else if (cmd_strcmp(start, "GCMP-256") == 0) + val |= WPA_CIPHER_GCMP_256; + else if (cmd_strcmp(start, "CCMP") == 0) + val |= WPA_CIPHER_CCMP; + else if (cmd_strcmp(start, "GCMP") == 0) + val |= WPA_CIPHER_GCMP; + else if (cmd_strcmp(start, "TKIP") == 0) + val |= WPA_CIPHER_TKIP; + else if (cmd_strcmp(start, "WEP104") == 0) + val |= WPA_CIPHER_WEP104; + else if (cmd_strcmp(start, "WEP40") == 0) + val |= WPA_CIPHER_WEP40; + else if (cmd_strcmp(start, "NONE") == 0) + val |= WPA_CIPHER_NONE; + else if (cmd_strcmp(start, "GTK_NOT_USED") == 0) + val |= WPA_CIPHER_GTK_NOT_USED; + else { + cmd_free(buf); + return -1; + } + + if (last) + break; + start = end + 1; + } + cmd_free(buf); + + return val; +} + +static int cmd_wpas_parse_proto(const char *value) +{ + int val = 0, last, errors = 0; + char *start, *end, *buf; + + buf = cmd_strdup(value); + if (buf == NULL) + return -1; + start = buf; + + while (*start != '\0') { + while (*start == ' ' || *start == '\t') + start++; + if (*start == '\0') + break; + end = start; + while (*end != ' ' && *end != '\t' && *end != '\0') + end++; + last = *end == '\0'; + *end = '\0'; + + /* softAP work on open mode. */ + if (cmd_strcmp(start, "NONE") == 0) { + val = 0; + break; + } + + if (cmd_strcmp(start, "WPA") == 0) + val |= WPA_PROTO_WPA; + else if (cmd_strcmp(start, "RSN") == 0 || + cmd_strcmp(start, "WPA2") == 0) + val |= WPA_PROTO_RSN; + else if (cmd_strcmp(start, "OSEN") == 0) + val |= WPA_PROTO_OSEN; + else { + CMD_DBG("Invalid proto '%s'\n", start); + errors++; + } + + if (last) + break; + start = end + 1; + } + cmd_free(buf); + +/* softAP work on open mode. */ +#if 0 + if (val == 0) { + CMD_DBG("No proto values configured\n"); + errors++; + } +#endif + + CMD_DBG("proto: 0x%x\n", val); + return errors ? -1 : val; +} + +static int cmd_wpas_parse_auth_alg(const char *value) +{ + int val = 0, last, errors = 0; + char *start, *end, *buf; + + buf = cmd_strdup(value); + if (buf == NULL) + return -1; + start = buf; + + while (*start != '\0') { + while (*start == ' ' || *start == '\t') + start++; + if (*start == '\0') + break; + end = start; + while (*end != ' ' && *end != '\t' && *end != '\0') + end++; + last = *end == '\0'; + *end = '\0'; + if (cmd_strcmp(start, "OPEN") == 0) + val |= WPA_AUTH_ALG_OPEN; + else if (cmd_strcmp(start, "SHARED") == 0) + val |= WPA_AUTH_ALG_SHARED; + else if (cmd_strcmp(start, "LEAP") == 0) + val |= WPA_AUTH_ALG_LEAP; + else { + CMD_DBG("Invalid auth_alg '%s'\n", start); + errors++; + } + + if (last) + break; + start = end + 1; + } + cmd_free(buf); + + if (val == 0) { + CMD_DBG("No auth_alg values configured\n"); + errors++; + } + + CMD_DBG("auth_alg: 0x%x\n", val); + return errors ? -1 : val; +} + +static __inline void cmd_wlan_sta_print_ap(wlan_sta_ap_t *ap) +{ + CMD_LOG(1, "%02x:%02x:%02x:%02x:%02x:%02x ssid=%-32.32s " + "beacon_int=%d freq=%d channel=%u rssi=%d level=%d " + "flags=%#010x wpa_key_mgmt=%#010x wpa_cipher=%#010x " + "wpa2_key_mgmt=%#010x wpa2_cipher=%#010x\n", + ap->bssid[0], ap->bssid[1], + ap->bssid[2], ap->bssid[3], + ap->bssid[4], ap->bssid[5], + ap->ssid.ssid, + ap->beacon_int, + ap->freq, + ap->channel, + ap->rssi, + ap->level, + ap->wpa_flags, + ap->wpa_key_mgmt, + ap->wpa_cipher, + ap->wpa2_key_mgmt, + ap->wpa2_cipher); +} + + +static void cmd_wlan_sta_print_scan_results(wlan_sta_scan_results_t *results) +{ + int i; + + for (i = 0; i < results->num; ++i) { + CMD_LOG(1, "\n%02d: ", i + 1); + cmd_wlan_sta_print_ap(&results->ap[i]); + } +} + +/* @return + * -2: CMD_STATUS_INVALID_ARG + * -1: CMD_STATUS_FAIL + * 0: CMD_STATUS_OK + */ +static int cmd_wlan_sta_set(char *cmd) +{ + char *value; + wlan_sta_config_t config; + + value = cmd_strchr(cmd, ' '); + if (value == NULL) + return -2; + *value++ = '\0'; + + config.field = WLAN_STA_FIELD_NUM; + + if (cmd_strcmp(cmd, "ssid") == 0) { + uint8_t ssid_len = cmd_strlen(value); + if ((ssid_len >= 1) && (ssid_len <= 32)) { + config.field = WLAN_STA_FIELD_SSID; + cmd_memcpy(config.u.ssid.ssid, value, ssid_len); + config.u.ssid.ssid_len = ssid_len; + } + } else if (cmd_strcmp(cmd, "psk") == 0) { + config.field = WLAN_STA_FIELD_PSK; + cmd_strlcpy((char *)config.u.psk, value, sizeof(config.u.psk)); + } else if (cmd_strcmp(cmd, "wep_key0") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY0; + cmd_strlcpy((char *)config.u.wep_key, value, sizeof(config.u.wep_key)); + } else if (cmd_strcmp(cmd, "wep_key1") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY1; + cmd_strlcpy((char *)config.u.wep_key, value, sizeof(config.u.wep_key)); + } else if (cmd_strcmp(cmd, "wep_key2") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY2; + cmd_strlcpy((char *)config.u.wep_key, value, sizeof(config.u.wep_key)); + } else if (cmd_strcmp(cmd, "wep_key3") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY3; + cmd_strlcpy((char *)config.u.wep_key, value, sizeof(config.u.wep_key)); + } else if (cmd_strcmp(cmd, "wep_key_index") == 0) { + int index; + if (cmd_wpas_parse_int(value, 0, 3, &index) == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY_INDEX; + config.u.wep_tx_keyidx = index; + } + } else if (cmd_strcmp(cmd, "key_mgmt") == 0) { + int key_mgmt = cmd_wpas_parse_key_mgmt(value); + if (key_mgmt > 0) { + config.field = WLAN_STA_FIELD_KEY_MGMT; + config.u.key_mgmt = key_mgmt; + } + } else if (cmd_strcmp(cmd, "pairwise") == 0) { + int pairwise_cipher = cmd_wpas_parse_cipher(value); + if (pairwise_cipher > 0) { + config.field = WLAN_STA_FIELD_PAIRWISE_CIPHER; + config.u.pairwise_cipher = pairwise_cipher; + } + } else if (cmd_strcmp(cmd, "group") == 0) { + int group_cipher = cmd_wpas_parse_cipher(value); + if (group_cipher > 0) { + config.field = WLAN_STA_FIELD_GROUP_CIPHER; + config.u.group_cipher = group_cipher; + } + } else if (cmd_strcmp(cmd, "proto") == 0) { + int proto = cmd_wpas_parse_proto(value); + if (proto >= 0) { + config.field = WLAN_STA_FIELD_PROTO; + config.u.proto = proto; + } + } else if (cmd_strcmp(cmd, "auth_alg") == 0) { + int auth_alg = cmd_wpas_parse_auth_alg(value); + if (auth_alg > 0) { + config.field = WLAN_STA_FIELD_AUTH_ALG; + config.u.auth_alg = auth_alg; + } + } else if (cmd_strcmp(cmd, "ptk_rekey") == 0) { + int sec; + if (cmd_wpas_parse_int(value, 0, INT32_MAX, &sec) == 0) { + config.field = WLAN_STA_FIELD_WPA_PTK_REKEY; + config.u.wpa_ptk_rekey = sec; + } + } else if (cmd_strcmp(cmd, "scan_ssid") == 0) { + int enable; + if (cmd_wpas_parse_int(value, 0, 1, &enable) == 0) { + config.field = WLAN_STA_FIELD_SCAN_SSID; + config.u.scan_ssid = enable; + } + } + + if (config.field < WLAN_STA_FIELD_NUM) + return wlan_sta_set_config(&config); + + CMD_ERR("%s: invalid arg '%s %s'\n", __func__, cmd, value); + return -2; +} + +/* @return + * -2: CMD_STATUS_INVALID_ARG + * -1: CMD_STATUS_FAIL + * 0: CMD_STATUS_OK + */ +static int cmd_wlan_sta_get(char *cmd) +{ + wlan_sta_config_t config; + cmd_memset(&config, 0, sizeof(config)); + + if (cmd_strcmp(cmd, "ssid") == 0) { + config.field = WLAN_STA_FIELD_SSID; + } else if (cmd_strcmp(cmd, "psk") == 0) { + config.field = WLAN_STA_FIELD_PSK; + } else if (cmd_strcmp(cmd, "wep_key0") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY0; + } else if (cmd_strcmp(cmd, "wep_key1") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY1; + } else if (cmd_strcmp(cmd, "wep_key2") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY2; + } else if (cmd_strcmp(cmd, "wep_key3") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY3; + } else if (cmd_strcmp(cmd, "wep_key_index") == 0) { + config.field = WLAN_STA_FIELD_WEP_KEY_INDEX; + } else if (cmd_strcmp(cmd, "key_mgmt") == 0) { + config.field = WLAN_STA_FIELD_KEY_MGMT; + } else if (cmd_strcmp(cmd, "pairwise") == 0) { + config.field = WLAN_STA_FIELD_PAIRWISE_CIPHER; + } else if (cmd_strcmp(cmd, "group") == 0) { + config.field = WLAN_STA_FIELD_GROUP_CIPHER; + } else if (cmd_strcmp(cmd, "proto") == 0) { + config.field = WLAN_STA_FIELD_PROTO; + } else if (cmd_strcmp(cmd, "auth_alg") == 0) { + config.field = WLAN_STA_FIELD_AUTH_ALG; + } else if (cmd_strcmp(cmd, "ptk_rekey") == 0) { + config.field = WLAN_STA_FIELD_WPA_PTK_REKEY; + } else if (cmd_strcmp(cmd, "scan_ssid") == 0) { + config.field = WLAN_STA_FIELD_SCAN_SSID; + } else { + CMD_ERR("%s: invalid arg '%s'\n", __func__, cmd); + return -2; + } + + if (wlan_sta_get_config(&config) != 0) { + CMD_ERR("%s: get config failed\n", __func__); + return -1; + } + + if (config.field == WLAN_STA_FIELD_SSID) { + CMD_LOG(1, "ssid: %.32s\n", config.u.ssid.ssid); + } else if (config.field == WLAN_STA_FIELD_PSK) { + CMD_LOG(1, "psk: %s\n", config.u.psk); + } else if (config.field == WLAN_STA_FIELD_WEP_KEY0) { + CMD_LOG(1, "wep_key0: %s\n", config.u.wep_key); + } else if (config.field == WLAN_STA_FIELD_WEP_KEY1) { + CMD_LOG(1, "wep_key1: %s\n", config.u.wep_key); + } else if (config.field == WLAN_STA_FIELD_WEP_KEY2) { + CMD_LOG(1, "wep_key2: %s\n", config.u.wep_key); + } else if (config.field == WLAN_STA_FIELD_WEP_KEY3) { + CMD_LOG(1, "wep_key3: %s\n", config.u.wep_key); + } else if (config.field == WLAN_STA_FIELD_WEP_KEY_INDEX) { + CMD_LOG(1, "wep_key_index: %d\n", config.u.wep_tx_keyidx); + } else if (config.field == WLAN_STA_FIELD_KEY_MGMT) { + CMD_LOG(1, "key_mgmt: %#06x\n", config.u.key_mgmt); + } else if (config.field == WLAN_STA_FIELD_PAIRWISE_CIPHER) { + CMD_LOG(1, "pairwise_cipher: %#06x\n", config.u.pairwise_cipher); + } else if (config.field == WLAN_STA_FIELD_GROUP_CIPHER) { + CMD_LOG(1, "group_cipher: %#06x\n", config.u.group_cipher); + } else if (config.field == WLAN_STA_FIELD_PROTO) { + CMD_LOG(1, "proto: %#06x\n", config.u.proto); + } else if (config.field == WLAN_STA_FIELD_AUTH_ALG) { + CMD_LOG(1, "auth_alg: %#06x\n", config.u.auth_alg); + } else if (config.field == WLAN_STA_FIELD_WPA_PTK_REKEY) { + CMD_LOG(1, "ptk_rekey: %d\n", config.u.wpa_ptk_rekey); + } else if (config.field == WLAN_STA_FIELD_SCAN_SSID) { + CMD_LOG(1, "scan_ssid: %d\n", config.u.scan_ssid); + } + + return 0; +} + +enum cmd_status cmd_wlan_sta_exec(char *cmd) +{ + int ret; + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + if (cmd_strncmp(cmd, "config ", 7) == 0) { + char *argv[2]; + if (cmd_parse_argv(cmd + 7, argv, cmd_nitems(argv)) == 0) { + ret = -2; + goto out; + } + ret = wlan_sta_set((uint8_t *)argv[0], cmd_strlen(argv[0]), (uint8_t *)argv[1]); + } else if (cmd_strncmp(cmd, "set ", 4) == 0) { + ret = cmd_wlan_sta_set(cmd + 4); + } else if (cmd_strncmp(cmd, "get ", 4) == 0) { + ret = cmd_wlan_sta_get(cmd + 4); + } else if (cmd_strcmp(cmd, "enable") == 0) { + ret = wlan_sta_enable(); + } else if (cmd_strcmp(cmd, "disable") == 0) { + ret = wlan_sta_disable(); + } else if (cmd_strcmp(cmd, "scan once") == 0) { + ret = wlan_sta_scan_once(); + } else if (cmd_strncmp(cmd, "scan result ", 12) == 0) { + int size; + if (cmd_wpas_parse_int(cmd + 12, 1, 30, &size) != 0) { + ret = -2; + goto out; + } + wlan_sta_scan_results_t results; + results.ap = cmd_malloc(size * sizeof(wlan_sta_ap_t)); + if (results.ap == NULL) { + CMD_ERR("%s: malloc failed\n", __func__); + ret = -1; + goto out; + } + results.size = size; + ret = wlan_sta_scan_result(&results); + if (ret == 0) + cmd_wlan_sta_print_scan_results(&results); + cmd_free(results.ap); + } else if (cmd_strncmp(cmd, "scan interval ", 14) == 0) { + int sec; + if (cmd_wpas_parse_int(cmd + 14, 0, INT32_MAX, &sec) != 0) { + ret = -2; + goto out; + } + ret = wlan_sta_scan_interval(sec); + } else if (cmd_strncmp(cmd, "bss flush ", 10) == 0) { + int age; + if (cmd_wpas_parse_int(cmd + 10, 0, INT32_MAX, &age) != 0) { + ret = -2; + goto out; + } + ret = wlan_sta_bss_flush(age); + } else if (cmd_strcmp(cmd, "connect") == 0) { + ret = wlan_sta_connect(); + } else if (cmd_strcmp(cmd, "disconnect") == 0) { + ret = wlan_sta_disconnect(); + } else if (cmd_strcmp(cmd, "state") == 0) { + wlan_sta_states_t state; + ret = wlan_sta_state(&state); + if (ret == 0) + CMD_LOG(1, "sta state: %d\n", state); + } else if (cmd_strcmp(cmd, "ap") == 0) { + wlan_sta_ap_t *ap = cmd_malloc(sizeof(wlan_sta_ap_t)); + if (ap == NULL) { + CMD_ERR("%s: malloc failed\n", __func__); + ret = -1; + goto out; + } + ret = wlan_sta_ap_info(ap); + if (ret == 0) + cmd_wlan_sta_print_ap(ap); + cmd_free(ap); + } else if (cmd_strcmp(cmd, "wps pbc") == 0) { + ret = wlan_sta_wps_pbc(); + } else if ((cmd_strlen(cmd) == 7) || (cmd_strcmp(cmd, "wps pin") == 0)) { + wlan_sta_wps_pin_t wps; + ret = wlan_sta_wps_pin_get(&wps); + if (ret == 0) + CMD_LOG(1, "WPS pin: %s\n", wps.pin); + } else if (cmd_strncmp(cmd, "wps pin ", 8) == 0) { + if (cmd_strlen(cmd + 8) != 8) { + ret = -2; + goto out; + } + wlan_sta_wps_pin_t wps; + cmd_memcpy(wps.pin, cmd + 8, 8); + wps.pin[8] = '\0'; + ret = wlan_sta_wps_pin_set(&wps); + } else { + CMD_ERR("%s: unknown command '%s'\n", __func__, cmd); + return CMD_STATUS_ACKED; + } + +out: + if (ret == -2) { + CMD_ERR("%s: command '%s' invalid arg\n", __func__, cmd); + return CMD_STATUS_ACKED; + } else if (ret == -1) { + CMD_ERR("%s: command '%s' exec failed\n", __func__, cmd); + return CMD_STATUS_ACKED; + } + + return CMD_STATUS_ACKED; +} + +static void cmd_wlan_ap_print_sta_info(wlan_ap_stas_t *stas) +{ + int i; + + CMD_LOG(1, "sta_num: %d\n", stas->num); + + for (i = 0; i < stas->num; i++) { + CMD_LOG(1, "[%02d]Mac addr: %02x:%02x:%02x:%02x:%02x:%02x\n", + i + 1, stas->sta[i].addr[0], stas->sta[i].addr[1], + stas->sta[i].addr[2], stas->sta[i].addr[3], + stas->sta[i].addr[4], stas->sta[i].addr[5]); + } +} + +/* @return + * -2: CMD_STATUS_INVALID_ARG + * -1: CMD_STATUS_FAIL + * 0: CMD_STATUS_OK + */ +static int cmd_wlan_ap_set(char *cmd) +{ + char *value; + wlan_ap_config_t config; + + value = cmd_strchr(cmd, ' '); + if (value == NULL) + return -2; + *value++ = '\0'; + + config.field = WLAN_AP_FIELD_NUM; + + if (cmd_strcmp(cmd, "ssid") == 0) { + uint8_t ssid_len = cmd_strlen(value); + if ((ssid_len >= 1) && (ssid_len <= 32)) { + config.field = WLAN_STA_FIELD_SSID; + cmd_memcpy(config.u.ssid.ssid, value, ssid_len); + config.u.ssid.ssid_len = ssid_len; + } + } else if (cmd_strcmp(cmd, "psk") == 0) { + config.field = WLAN_AP_FIELD_PSK; + cmd_strlcpy((char *)config.u.psk, value, sizeof(config.u.psk)); + } else if (cmd_strcmp(cmd, "key_mgmt") == 0) { + int key_mgmt = cmd_wpas_parse_key_mgmt(value); + if (key_mgmt > 0) { + config.field = WLAN_AP_FIELD_KEY_MGMT; + config.u.key_mgmt = key_mgmt; + } + } else if (cmd_strcmp(cmd, "wpa") == 0) { + int wpa_cipher = cmd_wpas_parse_cipher(value); + if (wpa_cipher > 0) { + config.field = WLAN_AP_FIELD_WPA_CIPHER; + config.u.wpa_cipher = wpa_cipher; + } + } else if (cmd_strcmp(cmd, "rsn") == 0) { + int rsn_cipher = cmd_wpas_parse_cipher(value); + if (rsn_cipher > 0) { + config.field = WLAN_AP_FIELD_RSN_CIPHER; + config.u.rsn_cipher = rsn_cipher; + } + } else if (cmd_strcmp(cmd, "proto") == 0) { + int proto = cmd_wpas_parse_proto(value); + if (proto >= 0) { + config.field = WLAN_AP_FIELD_PROTO; + config.u.proto = proto; + } + } else if (cmd_strcmp(cmd, "auth_alg") == 0) { + int auth_alg = cmd_wpas_parse_auth_alg(value); + if (auth_alg > 0) { + config.field = WLAN_AP_FIELD_AUTH_ALG; + config.u.auth_alg = auth_alg; + } + } else if (cmd_strcmp(cmd, "group_rekey") == 0) { + int group_rekey; + if (cmd_wpas_parse_int(value, 0, INT32_MAX, &group_rekey) == 0) { + config.field = WLAN_AP_FIELD_GROUP_REKEY; + config.u.group_rekey = group_rekey; + } + } else if (cmd_strcmp(cmd, "strict_rekey") == 0) { + int strict_rekey; + if (cmd_wpas_parse_int(value, 0, 1, &strict_rekey) == 0) { + config.field = WLAN_AP_FIELD_STRICT_REKEY; + config.u.strict_rekey = strict_rekey; + } + } else if (cmd_strcmp(cmd, "gmk_rekey") == 0) { + int gmk_rekey; + if (cmd_wpas_parse_int(value, 0, INT32_MAX, &gmk_rekey) == 0) { + config.field = WLAN_AP_FIELD_GMK_REKEY; + config.u.gmk_rekey = gmk_rekey; + } + } else if (cmd_strcmp(cmd, "ptk_rekey") == 0) { + int ptk_rekey; + if (cmd_wpas_parse_int(value, 0, INT32_MAX, &ptk_rekey) == 0) { + config.field = WLAN_AP_FIELD_PTK_REKEY; + config.u.ptk_rekey = ptk_rekey; + } + } else if (cmd_strcmp(cmd, "hw_mode") == 0) { + if ((value[0] == 'b') && (value[1] == '\0')) { + config.field = WLAN_AP_FIELD_HW_MODE; + config.u.hw_mode = WLAN_AP_HW_MODE_IEEE80211B; + } else if ((value[0] == 'g') && (value[1] == '\0')) { + config.field = WLAN_AP_FIELD_HW_MODE; + config.u.hw_mode = WLAN_AP_HW_MODE_IEEE80211G; + } + } else if (cmd_strcmp(cmd, "80211n") == 0) { + int ieee80211n; + if (cmd_wpas_parse_int(value, 0, 1, &ieee80211n) == 0) { + config.field = WLAN_AP_FIELD_IEEE80211N; + config.u.ieee80211n = ieee80211n; + } + } else if (cmd_strcmp(cmd, "channel") == 0) { + int channel; + if (cmd_wpas_parse_int(value, 1, 14, &channel) == 0) { + config.field = WLAN_AP_FIELD_CHANNEL; + config.u.channel = channel; + } + } else if (cmd_strcmp(cmd, "beacon_int") == 0) { + int beacon_int; + if (cmd_wpas_parse_int(value, 15, 65535, &beacon_int) == 0) { + config.field = WLAN_AP_FIELD_BEACON_INT; + config.u.beacon_int = beacon_int; + } + } else if (cmd_strcmp(cmd, "dtim") == 0) { + int dtim; + if (cmd_wpas_parse_int(value, 1, 255, &dtim) == 0) { + config.field = WLAN_AP_FIELD_DTIM; + config.u.dtim = dtim; + } + } else if (cmd_strcmp(cmd, "max_num_sta") == 0) { + int max_num_sta; + if (cmd_wpas_parse_int(value, 0, INT32_MAX, &max_num_sta) == 0) { + config.field = WLAN_AP_FIELD_MAX_NUM_STA; + config.u.max_num_sta = max_num_sta; + } + } + + if (config.field < WLAN_AP_FIELD_NUM) + return wlan_ap_set_config(&config); + + CMD_ERR("%s: invalid arg '%s %s'\n", __func__, cmd, value); + return -2; +} + +/* @return + * -2: CMD_STATUS_INVALID_ARG + * -1: CMD_STATUS_FAIL + * 0: CMD_STATUS_OK + */ +static int cmd_wlan_ap_get(char *cmd) +{ + wlan_ap_config_t config; + cmd_memset(&config, 0, sizeof(config)); + + if (cmd_strcmp(cmd, "ssid") == 0) { + config.field = WLAN_AP_FIELD_SSID; + } else if (cmd_strcmp(cmd, "psk") == 0) { + config.field = WLAN_AP_FIELD_PSK; + } else if (cmd_strcmp(cmd, "key_mgmt") == 0) { + config.field = WLAN_AP_FIELD_KEY_MGMT; + } else if (cmd_strcmp(cmd, "wpa") == 0) { + config.field = WLAN_AP_FIELD_WPA_CIPHER; + } else if (cmd_strcmp(cmd, "rsn") == 0) { + config.field = WLAN_AP_FIELD_RSN_CIPHER; + } else if (cmd_strcmp(cmd, "proto") == 0) { + config.field = WLAN_AP_FIELD_PROTO; + } else if (cmd_strcmp(cmd, "auth_alg") == 0) { + config.field = WLAN_AP_FIELD_AUTH_ALG; + } else if (cmd_strcmp(cmd, "group_rekey") == 0) { + config.field = WLAN_AP_FIELD_GROUP_REKEY; + } else if (cmd_strcmp(cmd, "strict_rekey") == 0) { + config.field = WLAN_AP_FIELD_STRICT_REKEY; + } else if (cmd_strcmp(cmd, "gmk_rekey") == 0) { + config.field = WLAN_AP_FIELD_GMK_REKEY; + } else if (cmd_strcmp(cmd, "ptk_rekey") == 0) { + config.field = WLAN_AP_FIELD_PTK_REKEY; + } else if (cmd_strcmp(cmd, "hw_mode") == 0) { + config.field = WLAN_AP_FIELD_HW_MODE; + } else if (cmd_strcmp(cmd, "80211n") == 0) { + config.field = WLAN_AP_FIELD_IEEE80211N; + } else if (cmd_strcmp(cmd, "channel") == 0) { + config.field = WLAN_AP_FIELD_CHANNEL; + } else if (cmd_strcmp(cmd, "beacon_int") == 0) { + config.field = WLAN_AP_FIELD_BEACON_INT; + } else if (cmd_strcmp(cmd, "dtim") == 0) { + config.field = WLAN_AP_FIELD_DTIM; + } else if (cmd_strcmp(cmd, "max_num_sta") == 0) { + config.field = WLAN_AP_FIELD_MAX_NUM_STA; + } else { + CMD_ERR("%s: invalid arg '%s'\n", __func__, cmd); + return -2; + } + + if (wlan_ap_get_config(&config) != 0) { + CMD_ERR("%s: get config failed\n", __func__); + return -1; + } + + if (config.field == WLAN_AP_FIELD_SSID) { + CMD_LOG(1, "ssid: %.32s\n", config.u.ssid.ssid); + } else if (config.field == WLAN_AP_FIELD_PSK) { + CMD_LOG(1, "psk: %s\n", config.u.psk); + } else if (config.field == WLAN_AP_FIELD_KEY_MGMT) { + CMD_LOG(1, "key_mgmt: %#06x\n", config.u.key_mgmt); + } else if (config.field == WLAN_AP_FIELD_WPA_CIPHER) { + CMD_LOG(1, "wpa_cipher: %#06x\n", config.u.wpa_cipher); + } else if (config.field == WLAN_AP_FIELD_RSN_CIPHER) { + CMD_LOG(1, "rsn_cipher: %#06x\n", config.u.rsn_cipher); + } else if (config.field == WLAN_AP_FIELD_PROTO) { + CMD_LOG(1, "proto: %#06x\n", config.u.proto); + } else if (config.field == WLAN_AP_FIELD_AUTH_ALG) { + CMD_LOG(1, "auth_alg: %#06x\n", config.u.auth_alg); + } else if (config.field == WLAN_AP_FIELD_GROUP_REKEY) { + CMD_LOG(1, "group_rekey: %d\n", config.u.group_rekey); + } else if (config.field == WLAN_AP_FIELD_STRICT_REKEY) { + CMD_LOG(1, "strict_rekey: %d\n", config.u.strict_rekey); + } else if (config.field == WLAN_AP_FIELD_GMK_REKEY) { + CMD_LOG(1, "gmk_rekey: %d\n", config.u.gmk_rekey); + } else if (config.field == WLAN_AP_FIELD_PTK_REKEY) { + CMD_LOG(1, "ptk_rekey: %d\n", config.u.ptk_rekey); + } else if (config.field == WLAN_AP_FIELD_HW_MODE) { + if (config.u.hw_mode == WLAN_AP_HW_MODE_IEEE80211B) { + CMD_LOG(1, "hw_mode: b\n"); + } else if (config.u.hw_mode == WLAN_AP_HW_MODE_IEEE80211G) { + CMD_LOG(1, "hw_mode: g\n"); + } else if (config.u.hw_mode == WLAN_AP_HW_MODE_IEEE80211A) { + CMD_LOG(1, "hw_mode: a\n"); + } else if (config.u.hw_mode == WLAN_AP_HW_MODE_IEEE80211AD) { + CMD_LOG(1, "hw_mode: ad\n"); + } else { + CMD_ERR("%s: invalid hw_mode\n", __func__); + } + } else if (config.field == WLAN_AP_FIELD_IEEE80211N) { + CMD_LOG(1, "ieee80211n: %d\n", config.u.ieee80211n); + } else if (config.field == WLAN_AP_FIELD_CHANNEL) { + CMD_LOG(1, "channel: %d\n", config.u.channel); + } else if (config.field == WLAN_AP_FIELD_BEACON_INT) { + CMD_LOG(1, "beacon_int: %d\n", config.u.beacon_int); + } else if (config.field == WLAN_AP_FIELD_DTIM) { + CMD_LOG(1, "dtim: %d\n", config.u.dtim); + } else if (config.field == WLAN_AP_FIELD_MAX_NUM_STA) { + CMD_LOG(1, "max_num_sta: %d\n", config.u.max_num_sta); + } + + return 0; +} + +enum cmd_status cmd_wlan_ap_exec(char *cmd) +{ + int ret; + + cmd_write_respond(CMD_STATUS_OK, "OK"); + + if (cmd_strncmp(cmd, "config ", 7) == 0) { + char *argv[2]; + if (cmd_parse_argv(cmd + 7, argv, cmd_nitems(argv)) == 0) { + ret = -2; + goto out; + } + ret = wlan_ap_set((uint8_t *)argv[0], cmd_strlen(argv[0]), (uint8_t *)argv[1]); + } else if (cmd_strncmp(cmd, "set ", 4) == 0) { + ret = cmd_wlan_ap_set(cmd + 4); + } else if (cmd_strncmp(cmd, "get ", 4) == 0) { + ret = cmd_wlan_ap_get(cmd + 4); + } else if (cmd_strcmp(cmd, "enable") == 0) { + ret = wlan_ap_enable(); + } else if (cmd_strcmp(cmd, "reload") == 0) { + ret = wlan_ap_reload(); + } else if (cmd_strcmp(cmd, "disable") == 0) { + ret = wlan_ap_disable(); + } else if (cmd_strcmp(cmd, "sta num") == 0) { + int num; + ret = wlan_ap_sta_num(&num); + if (ret == 0) + CMD_LOG(1, "sta num: %d\n", num); + } else if (cmd_strncmp(cmd, "sta info ", 9) == 0) { + int size; + if (cmd_wpas_parse_int(cmd + 9, 1, 30, &size) != 0) { + ret = -2; + goto out; + } + wlan_ap_stas_t stas; + stas.sta = (wlan_ap_sta_t *)cmd_malloc(size * sizeof(wlan_ap_sta_t)); + if (stas.sta == NULL) { + CMD_ERR("%s: malloc failed\n", __func__); + ret = -1; + goto out; + } + stas.size = size; + ret = wlan_ap_sta_info(&stas); + if (ret == 0) + cmd_wlan_ap_print_sta_info(&stas); + cmd_free(stas.sta); + } else { + CMD_ERR("%s: unknown command '%s'\n", __func__, cmd); + return CMD_STATUS_ACKED; + } + +out: + if (ret == -2) { + CMD_ERR("%s: command '%s' invalid arg\n", __func__, cmd); + return CMD_STATUS_ACKED; + } else if (ret == -1) { + CMD_ERR("%s: command '%s' exec failed\n", __func__, cmd); + return CMD_STATUS_ACKED; + } + + return CMD_STATUS_ACKED; +} + diff --git a/platform/mcu/xr871/project/common/cmd/cmd_wlan.h b/platform/mcu/xr871/project/common/cmd/cmd_wlan.h new file mode 100644 index 0000000000..237bf044ce --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/cmd_wlan.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CMD_WLAN_H_ +#define _CMD_WLAN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __PRJ_CONFIG_WLAN_STA_AP +enum cmd_status cmd_wlan_mode_exec(char *cmd); +#endif +enum cmd_status cmd_wlan_sta_exec(char *cmd); +enum cmd_status cmd_wlan_ap_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_WLAN_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/tls/client.c b/platform/mcu/xr871/project/common/cmd/tls/client.c new file mode 100644 index 0000000000..30ecfc504c --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/client.c @@ -0,0 +1,274 @@ +/* + * SSL client demonstration program + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ +#include "tls.h" + +#if !defined(MBEDTLS_BIGNUM_C) || !defined(MBEDTLS_ENTROPY_C) || \ + !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_CLI_C) || \ + !defined(MBEDTLS_NET_C) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_CERTS_C) || !defined(MBEDTLS_PEM_PARSE_C) || \ + !defined(MBEDTLS_CTR_DRBG_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) + +void mbedtls_client( void *arg) +{ + mbedtls_printf("MBEDTLS_BIGNUM_C and/or MBEDTLS_ENTROPY_C and/or " + "MBEDTLS_SSL_TLS_C and/or MBEDTLS_SSL_CLI_C and/or " + "MBEDTLS_NET_C and/or MBEDTLS_RSA_C and/or " + "MBEDTLS_CTR_DRBG_C and/or MBEDTLS_X509_CRT_PARSE_C " + "not defined.\n"); +} + +#else +#include +#include "net/mbedtls/net.h" +#include "net/mbedtls/debug.h" +#include "net/mbedtls/ssl.h" +#include "net/mbedtls/entropy.h" +#include "net/mbedtls/ctr_drbg.h" +#include "net/mbedtls/error.h" +#include "net/mbedtls/certs.h" + +extern volatile int mbedtls_string_mismatch; + +static void cli_debug( void *ctx, int level, + const char *file, int line, + const char *str ) +{ + ((void) level); + mbedtls_printf("%s:%04d: %s\n", file, line, str); +} + +void mbedtls_client(void *arg) +{ + mbedtls_test_param *param = (mbedtls_test_param *)arg; + unsigned int flags = param->flags; + unsigned int time_start = 0,time_now = 0, time_elapse = 0; + unsigned int milliseconds = 0; + int ret = 0, len = 0; + const char *pers = "ssl_client1"; + mbedtls_net_context server_fd; + mbedtls_entropy_context entropy; + mbedtls_ctr_drbg_context ctr_drbg; + mbedtls_ssl_context ssl; + mbedtls_ssl_config conf; + mbedtls_x509_crt cacert; + unsigned char *buf = mbedtls_calloc(1,TLS_TEST_BUF_SIZE); + if (!buf) { + mbedtls_printf( "\n[TLS CLI]Malloc failed.\n" ); + goto exit; + } + +#if defined(MBEDTLS_DEBUG_C) + mbedtls_debug_set_threshold(DEBUG_LEVEL); +#endif + /* Initialize the RNG and the session data */ + mbedtls_net_init(&server_fd); + mbedtls_ssl_init(&ssl); + mbedtls_ssl_config_init(&conf); + mbedtls_x509_crt_init(&cacert); + mbedtls_ctr_drbg_init(&ctr_drbg); + + mbedtls_printf("Seeding the random number generator.\n"); + mbedtls_entropy_init(&entropy); + if ((ret = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, + (const unsigned char *) pers, + strlen(pers))) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ctr_drbg_seed returned %d\n", ret); + goto exit; + } + mbedtls_printf("ok\n"); + /* Initialize certificates */ + mbedtls_printf("Loading the CA root certificate .\n"); +#if defined(MBEDTLS_CUSTOM_CA) + ret = mbedtls_x509_crt_parse(&cacert, (const unsigned char *) mbedtls_custom_cas_pem, + mbedtls_custom_cas_pem_len); +#else + ret = mbedtls_x509_crt_parse(&cacert, (const unsigned char *) mbedtls_test_cas_pem, + mbedtls_test_cas_pem_len); +#endif + if (ret < 0) { + mbedtls_printf(" failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret); + goto exit; + } + mbedtls_printf(" ok (%d skipped)\n", ret); + /* Start the connection */ + char *port = NULL; + if (flags & MBEDTLS_SSL_FLAG_SERVER_PORT) + port = param->server_port; + else + port = SERVER_PORT; + + char *server = NULL; + if (flags & MBEDTLS_SSL_FLAG_SERVER_NAME) + server = param->server_name; + else + goto exit; + mbedtls_printf("Connecting to %s (%s).\n", server, port); + if ((ret = mbedtls_net_connect(&server_fd, server, + port, MBEDTLS_NET_PROTO_TCP)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_net_connect returned %d\n\n", ret); + goto exit; + } + mbedtls_printf(" ok\n"); + /* Setup stuff */ + mbedtls_printf("Setting up the SSL/TLS structure...\n"); + if ((ret = mbedtls_ssl_config_defaults(&conf, + MBEDTLS_SSL_IS_CLIENT, + MBEDTLS_SSL_TRANSPORT_STREAM, + MBEDTLS_SSL_PRESET_DEFAULT)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ssl_config_defaults returned %d\n\n", ret); + goto exit; + } + mbedtls_printf(" ok\n"); + /* + * OPTIONAL is not optimal for security, + * but makes interop easier in this simplified example. + */ +#if defined(MBEDTLS_CUSTOM_CA) + mbedtls_ssl_conf_authmode(&conf, MBEDTLS_SSL_VERIFY_REQUIRED); +#else + mbedtls_ssl_conf_authmode(&conf, MBEDTLS_SSL_VERIFY_OPTIONAL); +#endif + mbedtls_ssl_conf_ca_chain(&conf, &cacert, NULL); + mbedtls_ssl_conf_rng(&conf, mbedtls_ctr_drbg_random, &ctr_drbg); + mbedtls_ssl_conf_dbg(&conf, cli_debug, stdout); + if ((ret = mbedtls_ssl_setup(&ssl, &conf)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ssl_setup returned %d\n\n", ret); + goto exit; + } + #if 0 + if ((ret = mbedtls_ssl_set_hostname(&ssl, server)) != 0) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_set_hostname returned %d\n\n", ret ); + goto exit; + } + #endif + mbedtls_ssl_set_bio( &ssl, &server_fd, mbedtls_net_send, mbedtls_net_recv, NULL ); + /* Handshake */ + mbedtls_printf( "Performing the SSL/TLS handshake...\n" ); + while ((ret = mbedtls_ssl_handshake( &ssl ) ) != 0) { + if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE) { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret); + goto exit; + } + } + mbedtls_printf(" ok(%s)\n", mbedtls_ssl_get_ciphersuite(&ssl)); + /* Verify the server certificate */ + mbedtls_printf("Verifying peer X.509 certificate...\n"); + + /* In real life, we probably want to bail out when ret != 0 */ + if ((ret = mbedtls_ssl_get_verify_result( &ssl ) ) != 0) { + char *vrfy_buf = malloc(512); + if (!vrfy_buf) + mbedtls_printf("[TLS-CLI]Malloc vrfy buf failed\n"); + else { + mbedtls_printf(" failed\n"); + mbedtls_x509_crt_verify_info(vrfy_buf, sizeof( vrfy_buf ), " ! ", ret); + mbedtls_printf("%s\n", vrfy_buf); + free(vrfy_buf); + } + } + else + mbedtls_printf(" ok\n"); + /* Write */ + mbedtls_printf("Write to server.\n"); + + if (flags & MBEDTLS_SSL_FLAG_CONTINUE) + milliseconds = param->continue_ms; + else + milliseconds = DEFALT_TEST_TIME; + time_start = TLS_GET_TIME(); + +client: + mbedtls_string_mismatch = -1; + + len = sprintf((char *) buf, CLIENT_DATA); + while (( ret = mbedtls_ssl_write(&ssl, buf, len)) <= 0) { + if(ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE) + { + mbedtls_printf(" failed\n ! mbedtls_ssl_write returned %d\n", ret); + goto exit; + } + } + mbedtls_printf(" %d bytes written\n", len); +// mbedtls_printf("%s\n", (char *) buf); + /* Read response */ + mbedtls_printf("Read from server:\n"); + unsigned int length = 0; + do { + len = TLS_TEST_BUF_SIZE; + memset(buf, 0, len); + unsigned char *read_buf = buf; + +read_data: + ret = mbedtls_ssl_read(&ssl, read_buf, len); + if (ret == MBEDTLS_ERR_SSL_WANT_READ || ret == MBEDTLS_ERR_SSL_WANT_WRITE) + continue; + if (ret == MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY) + break; + if (ret < 0) { + mbedtls_printf("failed\n ! mbedtls_ssl_read returned %d\n\n", ret); + break; + } + if (ret == 0) { + mbedtls_printf("\n\nEOF\n\n" ); + break; + } + mbedtls_printf(" %d bytes read\n", ret); + //mbedtls_printf("%s\n", (char *)buf); + length += ret; + if (ret >= mbedtls_strlen(CLIENT_DATA)) { + mbedtls_printf("Read data success\n"); + break; + } else { + read_buf += ret; + len -= ret; + goto read_data; + } + } while (1); + if ((ret = mbedtls_strncmp(CLIENT_DATA, (char *)buf, mbedtls_strlen(CLIENT_DATA))) != 0) { + mbedtls_string_mismatch = -1; + goto exit; + } else + mbedtls_string_mismatch = 0; + time_now = TLS_GET_TIME(); + if (time_now >= time_start) { + time_elapse = time_now - time_start; + } else { + time_elapse = 0xFFFFFFFFUL - time_start + time_now; + } + if (time_elapse < milliseconds) + goto client; + mbedtls_ssl_close_notify(&ssl); +exit: + if (ret != 0) + mbedtls_printf("Last error was: %d\n\n", ret); + mbedtls_net_free(&server_fd); + mbedtls_x509_crt_free(&cacert); + mbedtls_ssl_free(&ssl); + mbedtls_ssl_config_free(&conf); + mbedtls_ctr_drbg_free(&ctr_drbg); + mbedtls_entropy_free(&entropy); + FREE_BUF(buf); +} +#endif /* MBEDTLS_BIGNUM_C && MBEDTLS_ENTROPY_C && MBEDTLS_SSL_TLS_C && + MBEDTLS_SSL_CLI_C && MBEDTLS_NET_C && MBEDTLS_RSA_C && + MBEDTLS_CERTS_C && MBEDTLS_PEM_PARSE_C && MBEDTLS_CTR_DRBG_C && + MBEDTLS_X509_CRT_PARSE_C */ diff --git a/platform/mcu/xr871/project/common/cmd/tls/cmd_tls.c b/platform/mcu/xr871/project/common/cmd/tls/cmd_tls.c new file mode 100644 index 0000000000..a75ba45147 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/cmd_tls.c @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../cmd_util.h" +#include "cmd_tls.h" +#include "tls.h" + +struct config_exec_arg { + char cmd_str[5]; + int (*handler)(void *var); + int config; +}; + +mbedtls_test_param g_tls_data; + +int count_one(unsigned int P) +{ + int n = 0; + while (P != 0) { + if ((P & 0x1) != 0) { + n++; + } + P = P>>1; + } + return n; +} + +static int set_port(void *arg) +{ + char *dest = arg; + if (dest != NULL) { + if (cmd_strlen(dest) > (sizeof(g_tls_data.server_port) - 1)) { + CMD_ERR("invalid param : port.\n"); + return -1; + } + cmd_memcpy(g_tls_data.server_port, dest, cmd_strlen(dest)); + g_tls_data.flags |= MBEDTLS_SSL_FLAG_SERVER_PORT; + g_tls_data.server_port[cmd_strlen(dest)] = '\0'; + } + + return 0; +} + +static int set_servername(void *arg) +{ + char *dest = arg; + if (dest != NULL) { + if (cmd_strlen(dest) > (sizeof(g_tls_data.server_name) - 1)) { + CMD_ERR("invalid param : server_name.\n"); + return -1; + } + cmd_memcpy(g_tls_data.server_name, dest, cmd_strlen(dest)); + g_tls_data.flags |= MBEDTLS_SSL_FLAG_SERVER_NAME; + g_tls_data.server_name[cmd_strlen(dest)] = '\0'; + } + + return 0; +} + +static int set_timer(void *arg) +{ + char *dest = arg; + + if (*dest) { + g_tls_data.continue_ms = cmd_atoi(dest); + g_tls_data.flags |= MBEDTLS_SSL_FLAG_CONTINUE; + } + + return 0; +} + +static int set_client(void *arg) +{ + g_tls_data.flags |= MBEDTLS_SSL_FLAG_CLINET; + + return 0; +} + +static int set_server(void *arg) +{ + g_tls_data.flags |= MBEDTLS_SSL_FLAG_SERVER; + + return 0; +} +#if 0 +static int set_webserver(void *arg) +{ + g_tls_data.flags |= MBEDTLS_SSL_FLAG_WEBSERVER; + + return 0; +} + +static int set_webclient(void *arg) +{ + g_tls_data.flags |= MBEDTLS_SSL_FLAG_WEBCLIENT; + + return 0; +} +#endif +static struct config_exec_arg keywords[] = { + + {"-p", set_port, 1}, /* set port*/ + {"-n", set_servername, 1}, + {"-t", set_timer, 1}, + {"-c", set_client, 0}, + {"-s", set_server, 0}, + //{"-ws", set_webserver, 0}, + //-wc", set_webclient, 0}, + {"", NULL, 0}, +}; + +enum cmd_status cmd_tls_exec(char *cmd) +{ + int argc, i = 0, j = 0; + char *argv[12]; + unsigned int flags = 0; + mbedtls_test_param *param = (mbedtls_test_param *)&g_tls_data; + memset(param, 0, sizeof(mbedtls_test_param)); + argc = cmd_parse_argv(cmd, argv, 12); + + for (j = 0; j < argc; ++j) { + for (i = 0; strlen(keywords[i].cmd_str); i++) + if (cmd_strcmp(argv[j], keywords[i].cmd_str) == 0) { + if (keywords[i].config == 1) + j++; + keywords[i].handler(argv[j]); + } + } + + flags = MBEDTLS_SSL_FLAG_CLINET | MBEDTLS_SSL_FLAG_WEBCLIENT; + + if ((param->flags & flags) != 0) { + if ((param->flags & MBEDTLS_SSL_FLAG_SERVER_NAME) == 0) { + CMD_ERR("invalid tls cmd.\n"); + return CMD_STATUS_INVALID_ARG; + } + } + flags = MBEDTLS_SSL_FLAG_CLINET|MBEDTLS_SSL_FLAG_SERVER| \ + MBEDTLS_SSL_FLAG_WEBSERVER|MBEDTLS_SSL_FLAG_WEBCLIENT; + + flags = param->flags & flags; + if (count_one(flags) > 1 || count_one(flags) == 0) { + CMD_ERR("invalid tls cmd.\n"); + return CMD_STATUS_INVALID_ARG; + } + + if (tls_start(param) == 0) + return CMD_STATUS_OK; + else + return CMD_STATUS_FAIL; +} diff --git a/platform/mcu/xr871/project/common/cmd/tls/cmd_tls.h b/platform/mcu/xr871/project/common/cmd/tls/cmd_tls.h new file mode 100644 index 0000000000..c2ac1628c1 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/cmd_tls.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CMD_TLS_H_ +#define _CMD_TLS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum cmd_status cmd_tls_exec(char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMD_TLS_H_ */ diff --git a/platform/mcu/xr871/project/common/cmd/tls/custom_certs.c b/platform/mcu/xr871/project/common/cmd/tls/custom_certs.c new file mode 100644 index 0000000000..24f25bf4ec --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/custom_certs.c @@ -0,0 +1,29 @@ +#include "tls.h" + +//#define MBEDTLS_CUSTOM_CA + +#if defined(MBEDTLS_CUSTOM_CA) +#define CUSTOM_CA_CRT_RSA \ +"-----BEGIN CERTIFICATE-----\r\n" \ +"MIICtDCCAZwCAQAwDQYJKoZIhvcNAQELBQAwIDEeMBwGA1UEAxMVQ2VydGlmaWNh\r\n" \ +"dGUgQXV0aG9yaXR5MB4XDTE3MDcxOTExMzU1NVoXDTIyMDcxODExMzU1NVowIDEe\r\n" \ +"MBwGA1UEAxMVQ2VydGlmaWNhdGUgQXV0aG9yaXR5MIIBIjANBgkqhkiG9w0BAQEF\r\n" \ +"AAOCAQ8AMIIBCgKCAQEA3FPtvNnMiETM5qprK4625nf8z39HnM5pdkyjW3a4JWt4\r\n" \ +"RTuLv6x7b56OnJttZPL0hYyVwGsxt3LeuoXD3pBlLn61iwUK6Fb4NX5Xo04LaKl7\r\n" \ +"gQFQ+lENPPSu/JdzcERly0d1JYIQ4Z11732yCdblf5oZJ/0skUzhTVCusWnYvY3Z\r\n" \ +"xs/O3wjvbuCucxgZoyDv6AZ8ZQ0xKZ3JKjm8URD4yrRYEkQ+gBeTkNC3nVFJ/u8X\r\n" \ +"nrNT/qzhhI6HS8Lf88dkQu3W5gvIVVy5qv49hqpWGXwbEkrIsMgC9OJCZ5qoo17Y\r\n" \ +"iUj/SBH6xVA9ikaFOlVeH9rD1euzwgjIm+X2Wu7S5wIDAQABMA0GCSqGSIb3DQEB\r\n" \ +"CwUAA4IBAQCt9EYWA2vTVJmEajB87MzHHvjTV/cTWRGLKnLoBHL3OKf+Lembmu6Q\r\n" \ +"YxoN8OCqRjrcvh0sgQ1H6jpfmVSIoLKoT9BVy16t5PZ8x0XSSrMlXQKz+pAuOZBc\r\n" \ +"sinSoRPDMr0M92m2CAnJ8mIpr6o0lTtWJfY1xeuT2+LbFzvaI6dtWnQYmN1mxPqA\r\n" \ +"JLhAlQhCqmRiDhgFPfKSwKsmEPdUtrA2InOsgxDGa0utawK2BWgQc6hkhT9uZ4dF\r\n" \ +"DxLkNG8w4QFnHXcm8pdpg5zbO7GSrtPRs2CU2fMpE79CMPKSH3ErxV2F4aPtHFP5\r\n" \ +"sV1Ai+iyFoUKCzjW4iUDTJux2gUTzpmH\r\n" \ +"-----END CERTIFICATE-----\r\n" + + +/* Concatenation of all available CA certificates */ +const char mbedtls_custom_cas_pem[] = CUSTOM_CA_CRT_RSA; +const size_t mbedtls_custom_cas_pem_len = sizeof( mbedtls_custom_cas_pem ); +#endif diff --git a/platform/mcu/xr871/project/common/cmd/tls/server.c b/platform/mcu/xr871/project/common/cmd/tls/server.c new file mode 100644 index 0000000000..809501f87e --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/server.c @@ -0,0 +1,300 @@ +/* + * SSL server demonstration program + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ +#include "tls.h" + +#if !defined(MBEDTLS_BIGNUM_C) || !defined(MBEDTLS_CERTS_C) || \ + !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_SSL_TLS_C) || \ + !defined(MBEDTLS_SSL_SRV_C) || !defined(MBEDTLS_NET_C) || \ + !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_CTR_DRBG_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C)|| \ + !defined(MBEDTLS_PEM_PARSE_C) + +void mbedtls_server(void *arg) +{ + mbedtls_printf("MBEDTLS_BIGNUM_C and/or MBEDTLS_CERTS_C and/or MBEDTLS_ENTROPY_C " + "and/or MBEDTLS_SSL_TLS_C and/or MBEDTLS_SSL_SRV_C and/or " + "MBEDTLS_NET_C and/or MBEDTLS_RSA_C and/or " + "MBEDTLS_CTR_DRBG_C and/or MBEDTLS_X509_CRT_PARSE_C " + "and/or MBEDTLS_PEM_PARSE_C not defined.\n"); +} +#else + +#include +#include +#include "net/mbedtls/entropy.h" +#include "net/mbedtls/ctr_drbg.h" +#include "net/mbedtls/certs.h" +#include "net/mbedtls/x509.h" +#include "net/mbedtls/ssl.h" +#include "net/mbedtls/net.h" +#include "net/mbedtls/error.h" +#include "net/mbedtls/debug.h" + +#if defined(MBEDTLS_SSL_CACHE_C) +#include "mbedtls/ssl_cache.h" +#endif + +extern volatile int mbedtls_string_mismatch; + +static char tls_cal_checksum(void *buffer, int length) +{ + unsigned char *cal = (unsigned char *)buffer; + unsigned char result = 0; + while (length != 0) { + result += cal[--length]; + } + return result; +} + +static void server_debug( void *ctx, int level, + const char *file, int line, + const char *str ) +{ + ((void) level); + mbedtls_printf("%s:%04d: %s\n", file, line, str ); +} + +void mbedtls_server(void *arg) +{ + mbedtls_test_param *param = (mbedtls_test_param *)arg; + unsigned int flags = param->flags; + int ret = 0, len = 0; + + const char *pers = "ssl_server"; + mbedtls_net_context listen_fd, client_fd; + mbedtls_entropy_context entropy; + mbedtls_ctr_drbg_context ctr_drbg; + mbedtls_ssl_context ssl; + mbedtls_ssl_config conf; + mbedtls_x509_crt srvcert; + mbedtls_pk_context pkey; +#if defined(MBEDTLS_SSL_CACHE_C) + mbedtls_ssl_cache_context cache; +#endif + unsigned char *buf = mbedtls_calloc(1,TLS_TEST_BUF_SIZE); + if (!buf) { + mbedtls_printf("[TLS SRV]Malloc failed...\n"); + goto exit; + } + mbedtls_net_init(&listen_fd); + mbedtls_net_init(&client_fd); + mbedtls_ssl_init(&ssl); + mbedtls_ssl_config_init(&conf); +#if defined(MBEDTLS_SSL_CACHE_C) + mbedtls_ssl_cache_init(&cache); +#endif + mbedtls_x509_crt_init(&srvcert); + mbedtls_pk_init(&pkey); + mbedtls_entropy_init(&entropy); + mbedtls_ctr_drbg_init(&ctr_drbg); + +#if defined(MBEDTLS_DEBUG_C) + mbedtls_debug_set_threshold(DEBUG_LEVEL); +#endif + /* load the certificates and private RSA key */ + mbedtls_printf("Loading the server cert. and key...\n"); + /* + * This demonstration program uses embedded test certificates. + * Instead, you may want to use mbedtls_x509_crt_parse_file() to read the + * server and CA certificates, as well as mbedtls_pk_parse_keyfile(). + */ + ret = mbedtls_x509_crt_parse(&srvcert, (const unsigned char *) mbedtls_test_srv_crt, + mbedtls_test_srv_crt_len); + if (ret != 0) { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned %d\n\n", ret ); + goto exit; + } + + ret = mbedtls_x509_crt_parse(&srvcert, (const unsigned char *) mbedtls_test_cas_pem, + mbedtls_test_cas_pem_len); + if (ret != 0) { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned %d\n\n", ret ); + goto exit; + } + + ret = mbedtls_pk_parse_key(&pkey, (const unsigned char *) mbedtls_test_srv_key, + mbedtls_test_srv_key_len, NULL, 0); + if (ret != 0) { + mbedtls_printf(" failed\n ! mbedtls_pk_parse_key returned %d\n\n", ret); + goto exit; + } + mbedtls_printf(" ok\n"); + /* Setup the listening TCP socket */ + char *tcp_port = NULL; + if (flags & MBEDTLS_SSL_FLAG_SERVER_PORT) + tcp_port = param->server_port; + else + tcp_port = SERVER_PORT; + + if ((ret = mbedtls_net_bind(&listen_fd, NULL, tcp_port, MBEDTLS_NET_PROTO_TCP)) != 0) { + mbedtls_printf( " failed\n ! mbedtls_net_bind returned %d\n\n", ret ); + goto exit; + } + mbedtls_printf(" ok\n"); + /* Seed the RNG */ + mbedtls_printf( "Seeding the random number generator...\n" ); + if ((ret = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, + (const unsigned char *) pers, + strlen(pers))) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ctr_drbg_seed returned %d\n", ret); + goto exit; + } + mbedtls_printf(" ok\n"); + /* Setup stuff */ + mbedtls_printf("Setting up the SSL data....\n"); + if ((ret = mbedtls_ssl_config_defaults(&conf, + MBEDTLS_SSL_IS_SERVER, + MBEDTLS_SSL_TRANSPORT_STREAM, + MBEDTLS_SSL_PRESET_DEFAULT)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ssl_config_defaults returned %d\n\n", ret); + goto exit; + } + + mbedtls_ssl_conf_rng(&conf, mbedtls_ctr_drbg_random, &ctr_drbg); + mbedtls_ssl_conf_dbg(&conf, server_debug, stdout); + +#if defined(MBEDTLS_SSL_CACHE_C) + mbedtls_ssl_conf_session_cache(&conf, &cache, + mbedtls_ssl_cache_get, + mbedtls_ssl_cache_set); +#endif + + mbedtls_ssl_conf_ca_chain(&conf, srvcert.next, NULL); + if ((ret = mbedtls_ssl_conf_own_cert(&conf, &srvcert, &pkey)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ssl_conf_own_cert returned %d\n\n", ret); + goto exit; + } + + if ((ret = mbedtls_ssl_setup(&ssl, &conf)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_ssl_setup returned %d\n", ret); + goto exit; + } + mbedtls_printf(" ok\n"); +reset: + if (ret != 0) { + mbedtls_printf("Last error was: %d\n", ret); + } + mbedtls_net_free(&client_fd); + mbedtls_ssl_session_reset(&ssl); + /* Wait until a client connects */ + mbedtls_printf("Waiting for a remote connection.\n"); + if ((ret = mbedtls_net_accept(&listen_fd, &client_fd, + NULL, 0, NULL)) != 0) { + mbedtls_printf(" failed\n ! mbedtls_net_accept returned %d\n", ret); + goto exit; + } + mbedtls_ssl_set_bio(&ssl, &client_fd, mbedtls_net_send, mbedtls_net_recv, NULL); + mbedtls_printf(" ok\n"); + + /* Handshake */ + mbedtls_printf("Performing the SSL/TLS handshake.\n"); + while ((ret = mbedtls_ssl_handshake(&ssl)) != 0) { + if(ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE) { + mbedtls_printf(" failed\n ! mbedtls_ssl_handshake returned %d\n", ret); + goto reset; + } + } + mbedtls_printf(" ok(%s)\n",mbedtls_ssl_get_ciphersuite(&ssl)); + mbedtls_printf("Read from client.\n"); + + unsigned char checksum = 0; + mbedtls_string_mismatch = -1; + + do { + len = TLS_TEST_BUF_SIZE; + memset( buf, 0, TLS_TEST_BUF_SIZE ); + ret = mbedtls_ssl_read(&ssl, buf, len); + if(ret == MBEDTLS_ERR_SSL_WANT_READ || ret == MBEDTLS_ERR_SSL_WANT_WRITE) + continue; + if (ret <= 0) { + switch (ret) { + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + mbedtls_printf(" connection was closed gracefully\n"); + break; + case MBEDTLS_ERR_NET_CONN_RESET: + mbedtls_printf(" connection was reset by peer\n"); + break; + default: + mbedtls_printf(" mbedtls_ssl_read returned -0x%x\n", -ret); + break; + } + break; + } + + len = ret; + checksum += tls_cal_checksum(buf, len); + mbedtls_printf(" %d bytes read\n%s\n", len, (char *) buf); + } while (1); + + if (checksum == 0xFF) + mbedtls_string_mismatch = 0; + else { + mbedtls_string_mismatch = -1; + mbedtls_printf("checksum: 0x%x\n", checksum); + } +#if 0 + /* Write Response */ + mbedtls_printf("Write to client:\n"); + while ((ret = mbedtls_ssl_write(&ssl, buf, len)) <= 0) { + if (ret == MBEDTLS_ERR_NET_CONN_RESET) { + mbedtls_printf(" failed\n ! peer closed the connection\n"); + goto reset; + } + if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE) { + mbedtls_printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); + goto exit; + } + } +#endif + mbedtls_printf("Closing the connection...\n"); + while ((ret = mbedtls_ssl_close_notify(&ssl)) < 0) { + if (ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE) { + mbedtls_printf("Warn : mbedtls_ssl_close_notify returned %d\n\n", ret); + //goto reset; + break; + } + } + mbedtls_printf(" ok\n"); + ret = 0; + +exit: + if (ret != 0) + mbedtls_printf("Last error was: %d\n\n", ret); + + mbedtls_net_free(&client_fd); + mbedtls_net_free(&listen_fd); + + mbedtls_x509_crt_free(&srvcert); + mbedtls_pk_free(&pkey); + mbedtls_ssl_free(&ssl); + mbedtls_ssl_config_free(&conf); +#if defined(MBEDTLS_SSL_CACHE_C) + mbedtls_ssl_cache_free(&cache); +#endif + mbedtls_ctr_drbg_free(&ctr_drbg); + mbedtls_entropy_free(&entropy); + FREE_BUF(buf); +} +#endif /* MBEDTLS_BIGNUM_C && MBEDTLS_CERTS_C && MBEDTLS_ENTROPY_C && + MBEDTLS_SSL_TLS_C && MBEDTLS_SSL_SRV_C && MBEDTLS_NET_C && + MBEDTLS_RSA_C && MBEDTLS_CTR_DRBG_C && MBEDTLS_X509_CRT_PARSE_C + && MBEDTLS_FS_IO && MBEDTLS_PEM_PARSE_C */ diff --git a/platform/mcu/xr871/project/common/cmd/tls/tls.c b/platform/mcu/xr871/project/common/cmd/tls/tls.c new file mode 100644 index 0000000000..74570b226b --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/tls.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "tls.h" + +extern void mbedtls_client( void *arg); +extern void mbedtls_server( void *arg); + +static const OS_ThreadEntry_t tls_thread_entry[2] = { + mbedtls_server, + mbedtls_client, +}; + +OS_Thread_t g_tls_thread; +volatile int mbedtls_string_mismatch = 0; + +void tls_thread_start(void *param) +{ + printf(" \n"); + int client = (((mbedtls_test_param *)param)->flags & (MBEDTLS_SSL_FLAG_CLINET + |MBEDTLS_SSL_FLAG_WEBCLIENT)) == 0 ? 0 : 1; + mbedtls_string_mismatch = -1; + tls_thread_entry[client](param); + + char * str = mbedtls_string_mismatch == 0 ? "success" : "fail"; + printf(" \n",str); + tls_thread_stop(); +} + +int tls_thread_stop() +{ + if (OS_ThreadIsValid(&g_tls_thread)) { + TLS_THREAD_EXIT(&g_tls_thread); + return 0; + } else + return -1; +} + +int tls_start(mbedtls_test_param *param) +{ + if (OS_ThreadIsValid(&g_tls_thread)) { + mbedtls_printf("tls task is running\n"); + return -1; + } + + if (OS_ThreadCreate(&g_tls_thread, + "", + tls_thread_start, + (void *)param, + OS_THREAD_PRIO_APP, + TLS_THREAD_STACK_SIZE) != OS_OK) { + mbedtls_printf("tls task create failed\n"); + return -1; + } + return 0; +} diff --git a/platform/mcu/xr871/project/common/cmd/tls/tls.h b/platform/mcu/xr871/project/common/cmd/tls/tls.h new file mode 100644 index 0000000000..1f33d36855 --- /dev/null +++ b/platform/mcu/xr871/project/common/cmd/tls/tls.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __TLS_H_H +#define __TLS_H_H + +#define MBEDTLS_CLIENT_SERVER + +#if defined (MBEDTLS_CLIENT) +#include "net/mbedtls/configs/config-xr-mini-cli.h" +#endif +#if defined (MBEDTLS_CLIENT_SERVER) +#include "net/mbedtls/configs/config-xr-mini-cliserv.h" +#endif +#if defined (MBEDTLS_SERVER) +#include "net/mbedtls/configs/config-xr-mini-serv.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_fprintf fprintf +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_strlen strlen +#define mbedtls_strncmp strncmp +#endif + +#include "kernel/os/os_time.h" +#include "kernel/os/os_thread.h" +#include "kernel/os/FreeRTOS/os_common.h" + +#ifndef DEBUG_LEVEL +#define DEBUG_LEVEL 0 +#endif + +#ifndef DEFALT_TEST_TIME +#define DEFALT_TEST_TIME 0 //ms +#endif + +#ifndef TLS_TEST_BUF_SIZE +#define TLS_TEST_BUF_SIZE 4096 +#endif + +#ifndef TLS_GET_TIME +#define TLS_GET_TIME OS_GetTicks +#endif + +#ifndef TLS_THREAD_STACK_SIZE +#define TLS_THREAD_STACK_SIZE (6 * 1024) +#endif + +#define SERVER_PORT "10000" +#define CLINET_PORT "10001" +#define CLIENT_DATA "1234567890QWERTYUIOPASDFGHJKLZXCVBNMfjafjakfjlak"\ + "jlakfjlakjflkajflkajflkjflkajflakfjlak" +typedef struct +{ + char server_port[10]; + char server_name[30]; + unsigned int continue_ms; + unsigned int flags; +} mbedtls_test_param; + +typedef enum +{ + MBEDTLS_SSL_FLAG_SERVER_PORT = 0x00000001, + MBEDTLS_SSL_FLAG_SERVER_NAME = 0x00000002, + MBEDTLS_SSL_FLAG_CONTINUE = 0x00000004, + MBEDTLS_SSL_FLAG_CLINET = 0x00000008, + MBEDTLS_SSL_FLAG_SERVER = 0x00000010, + MBEDTLS_SSL_FLAG_WEBSERVER = 0x00000020, + MBEDTLS_SSL_FLAG_WEBCLIENT = 0x00000040, +} mbedtls_test_flags; + +#define TLS_THREAD_EXIT OS_ThreadDelete +#define FREE_BUF(P) \ + if (P != NULL) { \ + free(P);\ + P = NULL;} + +extern const char mbedtls_custom_cas_pem[]; +extern const size_t mbedtls_custom_cas_pem_len; +int tls_start(mbedtls_test_param *param); +int tls_thread_stop(); + +#endif /* __TLS_H_H */ + diff --git a/platform/mcu/xr871/project/common/framework/ctrl_msg_debug.h b/platform/mcu/xr871/project/common/framework/ctrl_msg_debug.h new file mode 100644 index 0000000000..41e7448328 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/ctrl_msg_debug.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CTRL_MSG_DEBUG_H_ +#define _CTRL_MSG_DEBUG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CTRL_MSG_DBG_ON 0 +#define CTRL_MSG_WRN_ON 1 +#define CTRL_MSG_ERR_ON 1 +#define CTRL_MSG_ABORT_ON 0 + +#define CTRL_MSG_VALIDITY_CHECK 0 + +#define CTRL_MSG_SYSLOG printf +#define CTRL_MSG_ABORT() do { } while (0) + +#define CTRL_MSG_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + CTRL_MSG_SYSLOG(fmt, ##arg); \ + } while (0) + +#define CTRL_MSG_DBG(fmt, arg...) \ + CTRL_MSG_LOG(CTRL_MSG_DBG_ON, "[ctrlmsg] "fmt, ##arg) + +#define CTRL_MSG_WRN(fmt, arg...) \ + CTRL_MSG_LOG(CTRL_MSG_WRN_ON, "[ctrlmsg WRN] "fmt, ##arg) + +#define CTRL_MSG_ERR(fmt, arg...) \ + do { \ + CTRL_MSG_LOG(CTRL_MSG_ERR_ON, "[ctrlmsg ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (CTRL_MSG_ABORT_ON) \ + CTRL_MSG_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _CTRL_MSG_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/fwk_debug.h b/platform/mcu/xr871/project/common/framework/fwk_debug.h new file mode 100644 index 0000000000..29f003ab0c --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/fwk_debug.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FWK_DEBUG_H_ +#define _FWK_DEBUG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define FWK_DBG_ON 0 +#define FWK_WRN_ON 0 +#define FWK_ERR_ON 1 +#define FWK_ABORT_ON 0 + +#define FWK_SYSLOG printf +#define FWK_ABORT() do { } while (0) + +#define FWK_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + FWK_SYSLOG(fmt, ##arg); \ + } while (0) + +#define FWK_DBG(fmt, arg...) \ + FWK_LOG(FWK_DBG_ON, "[fwk] "fmt, ##arg) + +#define FWK_WRN(fmt, arg...) \ + FWK_LOG(FWK_WRN_ON, "[fwk WRN] "fmt, ##arg) + +#define FWK_ERR(fmt, arg...) \ + do { \ + FWK_LOG(FWK_ERR_ON, "[fwk ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (FWK_ABORT_ON) \ + FWK_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _FWK_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/img_ctrl.c b/platform/mcu/xr871/project/common/framework/img_ctrl.c new file mode 100644 index 0000000000..f54eaf0312 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/img_ctrl.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "img_ctrl.h" +#include "img_ctrl_debug.h" + +#include "common/board/board.h" +#include "driver/chip/hal_wdg.h" +#include "sys/image.h" +#include "sys/ota.h" + +static void img_ctrl_ota_init(image_ota_param_t *param) +{ + + image_seq_t seq; + ota_cfg_t cfg; + + ota_init(param); + if (ota_read_cfg(&cfg) != OTA_STATUS_OK) + IMG_CTRL_ERR("ota read cfg failed\n"); + + if (((cfg.image == OTA_IMAGE_1ST) && (cfg.state == OTA_STATE_VERIFIED)) + || ((cfg.image == OTA_IMAGE_2ND) && (cfg.state == OTA_STATE_UNVERIFIED))) { + seq = IMAGE_SEQ_1ST; + } else if (((cfg.image == OTA_IMAGE_2ND) && (cfg.state == OTA_STATE_VERIFIED)) + || ((cfg.image == OTA_IMAGE_1ST) && (cfg.state == OTA_STATE_UNVERIFIED))) { + seq = IMAGE_SEQ_2ND; + } else { + IMG_CTRL_ERR("invalid image %d, state %d\n", cfg.image, cfg.state); + seq = IMAGE_SEQ_1ST; + } + + IMG_CTRL_DBG("image seq %d\n", seq); + image_set_running_seq(seq); + +} + +void img_ctrl_init(uint32_t flash, uint32_t addr, uint32_t size) +{ + image_ota_param_t param; + + image_init(flash, addr, size); + image_get_ota_param(¶m); + + if (param.addr[IMAGE_SEQ_2ND] == IMAGE_INVALID_ADDR) + image_set_running_seq(IMAGE_SEQ_1ST); + else + img_ctrl_ota_init(¶m); +} + diff --git a/platform/mcu/xr871/project/common/framework/img_ctrl.h b/platform/mcu/xr871/project/common/framework/img_ctrl.h new file mode 100644 index 0000000000..e24a2d88a8 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/img_ctrl.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IMG_CTRL_H_ +#define _IMG_CTRL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void img_ctrl_init(uint32_t flash, uint32_t addr, uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* _IMG_CTRL_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/img_ctrl_debug.h b/platform/mcu/xr871/project/common/framework/img_ctrl_debug.h new file mode 100644 index 0000000000..3755d50c0a --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/img_ctrl_debug.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IMG_CTRL_DEBUG_H_ +#define _IMG_CTRL_DEBUG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define IMG_CTRL_DBG_ON 0 +#define IMG_CTRL_WRN_ON 1 +#define IMG_CTRL_ERR_ON 1 +#define IMG_CTRL_ABORT_ON 0 + +#define IMG_CTRL_VALIDITY_CHECK 0 + +#define IMG_CTRL_SYSLOG printf +#define IMG_CTRL_ABORT() do { } while (0) + +#define IMG_CTRL_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + IMG_CTRL_SYSLOG(fmt, ##arg); \ + } while (0) + +#define IMG_CTRL_DBG(fmt, arg...) \ + IMG_CTRL_LOG(IMG_CTRL_DBG_ON, "[imgctrl] "fmt, ##arg) + +#define IMG_CTRL_WRN(fmt, arg...) \ + IMG_CTRL_LOG(IMG_CTRL_WRN_ON, "[imgctrl WRN] "fmt, ##arg) + +#define IMG_CTRL_ERR(fmt, arg...) \ + do { \ + IMG_CTRL_LOG(IMG_CTRL_ERR_ON, "[imgctrl ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (IMG_CTRL_ABORT_ON) \ + IMG_CTRL_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _IMG_CTRL_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/net_ctrl.c b/platform/mcu/xr871/project/common/framework/net_ctrl.c new file mode 100644 index 0000000000..882293a987 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/net_ctrl.c @@ -0,0 +1,432 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "lwip/tcpip.h" +#include "lwip/inet.h" +#include "lwip/dhcp.h" +#include "lwip/netifapi.h" +#include "net/wlan/wlan.h" +#include "net/udhcp/usr_dhcpd.h" + +#include "common/framework/sys_ctrl/sys_ctrl.h" +#include "common/framework/sysinfo.h" +#include "net_ctrl.h" +#include "net_ctrl_debug.h" + +struct netif_conf { + uint8_t bring_up; // bring up or down + uint8_t use_dhcp; // use DHCP or not +#ifdef __CONFIG_LWIP_V1 + ip_addr_t ipaddr; + ip_addr_t netmask; + ip_addr_t gw; +#elif LWIP_IPV4 /* now only for IPv4 */ + ip4_addr_t ipaddr; + ip4_addr_t netmask; + ip4_addr_t gw; +#else + #error "IPv4 not support!" +#endif +}; + +#if LWIP_NETIF_LINK_CALLBACK +static void netif_link_callback(struct netif *netif) +{ + if (netif_is_link_up(netif)) { + NET_INF("netif is link up\n"); + } else { + NET_INF("netif is link down\n"); + } +} +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if LWIP_NETIF_STATUS_CALLBACK +static void netif_status_callback(struct netif *netif) +{ + if (NET_IS_IP4_VALID(netif)) { + NET_INF("netif is up\n"); + NET_INF("address: %s\n", inet_ntoa(netif->ip_addr)); +#if LWIP_IPV6 + NET_INF("ipv6 address: %s\n", inet6_ntoa(netif->ip6_addr)); +#endif + NET_INF("gateway: %s\n", inet_ntoa(netif->gw)); + NET_INF("netmask: %s\n", inet_ntoa(netif->netmask)); + net_ctrl_msg_send(NET_CTRL_MSG_NETWORK_UP, 0); + } else { + NET_INF("netif is down\n"); + net_ctrl_msg_send(NET_CTRL_MSG_NETWORK_DOWN, 0); + } +} +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_REMOVE_CALLBACK +static void netif_remove_callback(struct netif *netif) +{ + NET_DBG("%s()\n", __func__); +} +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + +#ifdef __CONFIG_LWIP_V1 +#define NET_DHCP_DATA(nif) (nif->dhcp) +#define NET_DHCP_STATE(nif) (nif->dhcp->state) +#define NET_DHCP_STATE_OFF DHCP_OFF +#define NET_DHCP_STATE_BOUND DHCP_BOUND +//#define NET_IP4_ADDR_ANY IP_ADDR_ANY +#elif LWIP_IPV4 /* now only for IPv4 */ +#include "lwip/prot/dhcp.h" +#define NET_DHCP_DATA(nif) netif_dhcp_data(nif) +#define NET_DHCP_STATE(nif) (netif_dhcp_data(nif)->state) +#define NET_DHCP_STATE_OFF DHCP_STATE_OFF +#define NET_DHCP_STATE_BOUND DHCP_STATE_BOUND +//#define NET_IP4_ADDR_ANY IP4_ADDR_ANY4 +#else +#error "IPv4 not support!" +#endif + +static void netif_config(struct netif *nif, struct netif_conf *conf) +{ + if (conf->bring_up) { + if (NET_IS_IP4_VALID(nif)) { + NET_INF("netif is already up\n"); + return; + } + if (conf->use_dhcp) { + if (NET_DHCP_DATA(nif) && + NET_DHCP_STATE(nif) != NET_DHCP_STATE_OFF) { + NET_INF("DHCP is already started\n"); + return; + } + + NET_INF("start DHCP...\n"); + if (netifapi_dhcp_start(nif) != ERR_OK) { + NET_ERR("DHCP start failed!\n"); + return; + } + } else { + netifapi_netif_set_addr(nif, &conf->ipaddr, &conf->netmask, &conf->gw); +#ifdef __CONFIG_LWIP_V1 + netifapi_netif_set_up(nif); +#endif + } + } else { + if (conf->use_dhcp) { + if (NET_DHCP_DATA(nif) == NULL) { + NET_INF("DHCP is not started\n"); + return; + } + if (netif_is_link_up(nif)) { + NET_INF("release DHCP\n"); + netifapi_dhcp_release(nif); + } else { + NET_INF("bring down netif\n"); +#ifdef __CONFIG_LWIP_V1 + netifapi_netif_set_down(nif); +#endif + netifapi_netif_set_addr(nif, NULL, NULL, NULL); + } + + NET_INF("stop DHCP\n"); + netifapi_dhcp_stop(nif); + } else { + if (!NET_IS_IP4_VALID(nif)) { + NET_INF("netif is already down\n"); + return; + } + NET_INF("bring down netif\n"); +#ifdef __CONFIG_LWIP_V1 + netifapi_netif_set_down(nif); +#endif + netifapi_netif_set_addr(nif, NULL, NULL, NULL); + } + } +} + +/* bring up/down network */ +void net_config(struct netif *nif, uint8_t bring_up) +{ + struct sysinfo *sysinfo = sysinfo_get(); + if (sysinfo == NULL) { + NET_ERR("failed to get sysinfo %p\n", sysinfo); + return; + } + + struct netif_conf net_conf; + memset(&net_conf, 0, sizeof(struct netif_conf)); + net_conf.bring_up = bring_up; + + if (sysinfo->wlan_mode == WLAN_MODE_STA) { + if (sysinfo->sta_use_dhcp) { + net_conf.use_dhcp = 1; + } else { + net_conf.use_dhcp = 0; + memcpy(&net_conf.ipaddr, &sysinfo->netif_sta_param.ip_addr, sizeof(net_conf.ipaddr)); + memcpy(&net_conf.netmask, &sysinfo->netif_sta_param.net_mask, sizeof(net_conf.netmask)); + memcpy(&net_conf.gw, &sysinfo->netif_sta_param.gateway, sizeof(net_conf.gw)); + } + } else if (sysinfo->wlan_mode == WLAN_MODE_HOSTAP) { + net_conf.use_dhcp = 0; + memcpy(&net_conf.ipaddr, &sysinfo->netif_ap_param.ip_addr, sizeof(net_conf.ipaddr)); + memcpy(&net_conf.netmask, &sysinfo->netif_ap_param.net_mask, sizeof(net_conf.netmask)); + memcpy(&net_conf.gw, &sysinfo->netif_ap_param.gateway, sizeof(net_conf.gw)); + } else { + NET_ERR("invalid wlan mode %d\n", sysinfo->wlan_mode); + return; + } + + netif_config(nif, &net_conf); +} + +struct netif *net_open(enum wlan_mode mode) +{ + struct netif *nif; + + NET_DBG("%s(), mode %d\n", __func__, mode); + + wlan_attach(); + nif = wlan_if_create(mode); + if (nif == NULL) { + return NULL; + } + +#ifndef __CONFIG_LWIP_V1 +#if LWIP_IPV6 + netif_create_ip6_linklocal_address(nif, 1); + #if LWIP_IPV6_AUTOCONFIG + netif_set_ip6_autoconfig_enabled(nif, 1); + #endif +#endif /* LWIP_IPV6 */ + /* set netif up, but no valid ip address, required by lwip-2.x.x */ + //netifapi_netif_set_up(nif); +#endif /* __CONFIG_LWIP_V1 */ + +#if LWIP_NETIF_LINK_CALLBACK + netif_set_link_callback(nif, netif_link_callback); +#endif +#if LWIP_NETIF_STATUS_CALLBACK + netif_set_status_callback(nif, netif_status_callback); +#endif +#if LWIP_NETIF_REMOVE_CALLBACK + netif_set_remove_callback(nif, netif_remove_callback); +#endif + wlan_start(nif); + + struct sysinfo *sysinfo = sysinfo_get(); + if (sysinfo) { + sysinfo->wlan_mode = mode; + } + + return nif; +} + +void _net_close(struct netif *nif) +{ + NET_DBG("%s(), mode %d\n", __func__, wlan_if_get_mode(nif)); + + wlan_stop(); +#if 0 +#if LWIP_NETIF_REMOVE_CALLBACK + netif_set_remove_callback(nif, NULL); +#endif +#if LWIP_NETIF_STATUS_CALLBACK + netif_set_status_callback(nif, NULL); +#endif +#if LWIP_NETIF_LINK_CALLBACK + netif_set_link_callback(nif, NULL); +#endif +#endif + wlan_if_delete(nif); + wlan_detach(); +} + +int net_switch_mode(enum wlan_mode mode) +{ + int ret = -1; + enum wlan_mode cur_mode; + struct netif *nif = g_wlan_netif; + + NET_DBG("%s(), mode %d --> %d\n", __func__, wlan_if_get_mode(nif), mode); + + if (nif == NULL) { + return net_sys_start(mode); /* start net sys only */ + } + + if (mode >= WLAN_MODE_NUM) { + NET_WRN("invalid wlan mode %d\n", mode); + return ret; + } + + cur_mode = wlan_if_get_mode(nif); + if (mode == cur_mode) { + NET_INF("no need to switch wlan mode %d\n", cur_mode); + return 0; + } + + if (NET_IS_IP4_VALID(nif)) { + net_config(nif, 0); /* bring down netif */ + } + + if (cur_mode == WLAN_MODE_STA && netif_is_link_up(nif)) { + wlan_sta_disable(); /* disconnect wlan */ + } + + switch (mode) { + case WLAN_MODE_HOSTAP: + net_sys_stop(); + ret = net_sys_start(mode); + break; + case WLAN_MODE_STA: + case WLAN_MODE_MONITOR: + if (cur_mode == WLAN_MODE_HOSTAP) { + net_sys_stop(); + ret = net_sys_start(mode); + } else { + _net_close(nif); + nif = net_open(mode); + g_wlan_netif = nif; + if (nif) { + ret = 0; + } + } + break; + default: + break; + } + + return ret; +} + +int net_ctrl_msg_send(uint16_t type, uint32_t data) +{ + return sys_event_send(CTRL_MSG_TYPE_NETWORK, type, data, OS_WAIT_FOREVER); +} + +int net_ctrl_msg_send_with_free(uint16_t type, uint32_t data) +{ + return sys_event_send_with_free(CTRL_MSG_TYPE_NETWORK, type, data, OS_WAIT_FOREVER); +} + +#if NET_INF_ON +const char *net_ctrl_msg_str[] = { + "wlan connected", + "wlan disconnected", + "wlan scan success", + "wlan scan failed", + "wlan 4way handshake failed", + "wlan connect failed", + "network up", + "network down", +}; +#endif + +int net_ctrl_connect_ap(void) +{ + return 0; +} + +int net_ctrl_disconnect_ap(void) +{ + return 0; +} + +void net_ctrl_msg_process(uint32_t event, uint32_t data) +{ + uint16_t type = EVENT_SUBTYPE(event); + NET_INF("msg <%s>\n", net_ctrl_msg_str[type]); + + switch (type) { + case NET_CTRL_MSG_WLAN_CONNECTED: + if (g_wlan_netif && !netif_is_link_up(g_wlan_netif)) { + //netifapi_netif_set_link_up(g_wlan_netif); /* set link up */ + netifapi_netif_common(g_wlan_netif, netif_set_link_up, NULL); +#if (defined(__CONFIG_LWIP_V1) || LWIP_IPV4) + netifapi_netif_set_up(g_wlan_netif); + net_config(g_wlan_netif, 1); /* bring up network */ +#endif + } + break; + case NET_CTRL_MSG_WLAN_DISCONNECTED: + if (g_wlan_netif) { + //netifapi_netif_set_link_down(g_wlan_netif); /* set link down */ + netifapi_netif_common(g_wlan_netif, netif_set_link_down, NULL); + } +#if (defined(__CONFIG_LWIP_V1) || LWIP_IPV4) + /* if dhcp is started and not bound, stop it */ + if (g_wlan_netif && NET_DHCP_DATA(g_wlan_netif) && + NET_DHCP_STATE(g_wlan_netif) != NET_DHCP_STATE_OFF && + NET_DHCP_STATE(g_wlan_netif) != NET_DHCP_STATE_BOUND) { + net_config(g_wlan_netif, 0); + } +#endif + break; + case NET_CTRL_MSG_WLAN_SCAN_SUCCESS: + break; + case NET_CTRL_MSG_WLAN_SCAN_FAILED: + break; + case NET_CTRL_MSG_WLAN_4WAY_HANDSHAKE_FAILED: + break; + case NET_CTRL_MSG_WLAN_CONNECT_FAILED: + break; + case NET_CTRL_MSG_NETWORK_UP: +#if (defined(__CONFIG_LWIP_V1) || LWIP_IPV4) + if (g_wlan_netif) { + enum wlan_mode mode = wlan_if_get_mode(g_wlan_netif); + if (mode == WLAN_MODE_STA) { + uint32_t addr = NET_IP_ADDR_GET_IP4U32(&g_wlan_netif->ip_addr); + wlan_set_ip_addr(g_wlan_netif, (uint8_t *)&addr, sizeof(addr)); + } else if (mode == WLAN_MODE_HOSTAP) { + NET_INF("dhcp_server_start...\n"); + dhcp_server_start(NULL); + } else { + NET_ERR("Invalid wlan mode %d\n", mode); + } + } +#endif + break; + case NET_CTRL_MSG_NETWORK_DOWN: + break; + default: + NET_WRN("unknown msg (%u, %u)\n", type, data); + break; + } +} + +int net_ctrl_init(void) +{ + observer_base *ob = sys_callback_observer_create(CTRL_MSG_TYPE_NETWORK, + NET_CTRL_MSG_ALL, + net_ctrl_msg_process); + if (ob == NULL) + return -1; + if (sys_ctrl_attach(ob) != 0) + return -1; + + return 0; +} diff --git a/platform/mcu/xr871/project/common/framework/net_ctrl.h b/platform/mcu/xr871/project/common/framework/net_ctrl.h new file mode 100644 index 0000000000..e036a4738c --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/net_ctrl.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_CTRL_H_ +#define _NET_CTRL_H_ + +#include "lwip/netif.h" +#include "net/wlan/wlan.h" +#include "net/wlan/wlan_defs.h" +#include "sys_ctrl/sys_ctrl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//#define CONFIG_AUTO_RECONNECT_AP + +enum net_ctrl_msg_type { + NET_CTRL_MSG_WLAN_CONNECTED = WLAN_EVENT_CONNECTED, + NET_CTRL_MSG_WLAN_DISCONNECTED = WLAN_EVENT_DISCONNECTED, + NET_CTRL_MSG_WLAN_SCAN_SUCCESS = WLAN_EVENT_SCAN_SUCCESS, + NET_CTRL_MSG_WLAN_SCAN_FAILED = WLAN_EVENT_SCAN_FAILED, + NET_CTRL_MSG_WLAN_4WAY_HANDSHAKE_FAILED = WLAN_EVENT_4WAY_HANDSHAKE_FAILED, + NET_CTRL_MSG_WLAN_CONNECT_FAILED = WLAN_EVENT_CONNECT_FAILED, + + NET_CTRL_MSG_NETWORK_UP, + NET_CTRL_MSG_NETWORK_DOWN, + + NET_CTRL_MSG_ALL = ALL_SUBTYPE, +}; + +#ifdef __CONFIG_LWIP_V1 +#define NET_IP_ADDR_GET_IP4U32(addr) ip4_addr_get_u32(addr) +#define NET_IS_IP4_VALID(nif) (netif_is_up(nif) && \ + !ip_addr_isany(&((nif)->ip_addr))) +#elif LWIP_IPV4 /* now only for IPv4 */ +#define NET_IP_ADDR_GET_IP4U32(addr) ip_addr_get_ip4_u32(addr) +#define NET_IS_IP4_VALID(nif) (netif_is_up(nif) && \ + !ip_addr_isany(&((nif)->ip_addr))) +#else +#error "IPv4 not support!" +#endif + +extern struct netif *g_wlan_netif; + +void net_sys_init(void); +int net_sys_start(enum wlan_mode mode); +int net_sys_stop(void); +int net_sys_onoff(unsigned int enable); + +struct netif *net_open(enum wlan_mode mode); +void _net_close(struct netif *nif); +int net_switch_mode(enum wlan_mode mode); +void net_config(struct netif *nif, uint8_t bring_up); +int net_ctrl_connect_ap(void); +int net_ctrl_disconnect_ap(void); + +int net_ctrl_init(void); +int net_ctrl_msg_send(uint16_t type, uint32_t data); +int net_ctrl_msg_send_with_free(uint16_t type, uint32_t data); +void net_ctrl_msg_process(uint32_t event, uint32_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _NET_CTRL_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/net_ctrl_debug.h b/platform/mcu/xr871/project/common/framework/net_ctrl_debug.h new file mode 100644 index 0000000000..1216e9fd27 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/net_ctrl_debug.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_CTRL_DEBUG_H_ +#define _NET_CTRL_DEBUG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define NET_DBG_ON 0 +#define NET_INF_ON 1 +#define NET_WRN_ON 1 +#define NET_ERR_ON 1 +#define NET_ABORT_ON 0 + +#define NET_SYSLOG printf +#define NET_ABORT() do { } while (0) + +#define NET_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + NET_SYSLOG(fmt, ##arg); \ + } while (0) + +#define NET_DBG(fmt, arg...) \ + NET_LOG(NET_DBG_ON, "[net DBG] "fmt, ##arg) + +#define NET_INF(fmt, arg...) \ + NET_LOG(NET_INF_ON, "[net INF] "fmt, ##arg) + +#define NET_WRN(fmt, arg...) \ + NET_LOG(NET_WRN_ON, "[net WRN] "fmt, ##arg) + +#define NET_ERR(fmt, arg...) \ + do { \ + NET_LOG(NET_ERR_ON, "[net ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (NET_ABORT_ON) \ + NET_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _NET_CTRL_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/net_sys.c b/platform/mcu/xr871/project/common/framework/net_sys.c new file mode 100644 index 0000000000..f274039840 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/net_sys.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "kernel/os/os.h" +#include "sys/ducc/ducc_net.h" +#include "sys/ducc/ducc_app.h" +#include "net/wlan/wlan.h" +#include "net/wlan/wlan_defs.h" +#include "lwip/tcpip.h" +#include "net/udhcp/usr_dhcpd.h" + +#include "common/framework/sysinfo.h" +#include "common/board/board.h" +#include "net_ctrl.h" +#include "net_ctrl_debug.h" + +#include "driver/chip/hal_prcm.h" + +struct netif *g_wlan_netif = NULL; + +static void netif_tcpip_init_done(void *arg) +{ +// NET_DBG("%s()\n", __func__); +} + +void net_sys_init(void) +{ + tcpip_init(netif_tcpip_init_done, NULL); /* Init lwip module */ +} + + +static int net_sys_callback(uint32_t param0, uint32_t param1) +{ + switch (param0) { + case DUCC_NET_CMD_WLAN_EVENT: + switch (param1) { + case WLAN_EVENT_CONNECTED: + case WLAN_EVENT_DISCONNECTED: + case WLAN_EVENT_SCAN_SUCCESS: + case WLAN_EVENT_SCAN_FAILED: + case WLAN_EVENT_4WAY_HANDSHAKE_FAILED: + case WLAN_EVENT_CONNECT_FAILED: + net_ctrl_msg_send(param1, 0); + break; + default: + break; + } + break; + default: + break; + } + return 0; +} + +int net_sys_start(enum wlan_mode mode) +{ + struct sysinfo *sysinfo = sysinfo_get(); + if (sysinfo == NULL) { + NET_ERR("failed to get sysinfo %p\n", sysinfo); + return -1; + } + + if (wlan_sys_init(mode, net_sys_callback) != 0) { + NET_ERR("net system start failed\n"); + return -1; + } +#if PRJCONF_UART_EN + /* netos debug output is disable by default */ + UART_T *uart; + if (BOARD_SUB_UART_ID < UART_NUM) { + uart = HAL_UART_GetInstance(BOARD_SUB_UART_ID); + } else { + uart = NULL; /* disable netos debug output */ + } + ducc_app_ioctl(DUCC_APP_CMD_UART_CONFIG, uart); +#endif + +#ifndef __PRJ_CONFIG_ETF_CLI + wlan_set_mac_addr(sysinfo->mac_addr, SYSINFO_MAC_ADDR_LEN); + g_wlan_netif = net_open(mode); +#endif + return 0; +} + +int net_sys_stop(void) +{ + if (g_wlan_netif && wlan_if_get_mode(g_wlan_netif) == WLAN_MODE_HOSTAP) { + NET_INF("dhcp_server_stop...\n"); + dhcp_server_stop(); + } + + _net_close(g_wlan_netif); + g_wlan_netif = NULL; + + while (HAL_PRCM_IsSys3Alive()) { + OS_MSleep(10); /* wait net */ + } + + if (wlan_sys_deinit()) { + NET_ERR("net system stop failed\n"); + return -1; + } + + return 0; +} + +int net_sys_onoff(unsigned int enable) +{ + struct sysinfo *sysinfo = sysinfo_get(); + if (sysinfo == NULL) { + NET_ERR("failed to get sysinfo %p\n", sysinfo); + return -1; + } + + printf("%s set net to power%s\n", __func__, enable?"on":"off"); + + if (enable) { + net_sys_start(sysinfo->wlan_mode); +#ifdef CONFIG_AUTO_RECONNECT_AP + net_ctrl_connect_ap(NULL); +#endif + } else { +#ifdef CONFIG_AUTO_RECONNECT_AP + net_ctrl_disconnect_ap(NULL, 1); +#endif + net_sys_stop(); + } + + return 0; +} diff --git a/platform/mcu/xr871/project/common/framework/platform_init.c b/platform/mcu/xr871/project/common/framework/platform_init.c new file mode 100644 index 0000000000..94eb46ca44 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/platform_init.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "compiler.h" +#include "version.h" +#include "pm/pm.h" + +#include "common/board/board.h" +#include "sysinfo.h" +#include "img_ctrl.h" +#include "net_ctrl.h" +#include "sys_ctrl/sys_ctrl.h" +#include "fwk_debug.h" + +#if (PRJCONF_SOUNDCARD0_EN || PRJCONF_SOUNDCARD1_EN) +#include "audio/manager/audio_manager.h" +#include "audio/pcm/audio_pcm.h" +#endif +#if PRJCONF_CONSOLE_EN +#include "console/console.h" +#include "command.h" +#endif +#ifdef __PRJ_CONFIG_XIP +#include "driver/chip/hal_xip.h" +#include "sys/image.h" +#endif + +#define PLATFORM_SHOW_INFO 0 /* for internal debug only */ + +/* default app pm mode */ +#if (PRJCONF_PM_EN && !defined(PRJCONF_PM_MODE)) +#define PRJCONF_PM_MODE (PM_SUPPORT_SLEEP | \ + PM_SUPPORT_STANDBY | \ + PM_SUPPORT_POWEROFF) +#endif + +/* default net pm mode */ +#if (PRJCONF_NET_PM_EN && !defined(PRJCONF_NET_PM_MODE)) +#define PRJCONF_NET_PM_MODE (PM_SUPPORT_HIBERNATION | \ + PM_SUPPORT_POWEROFF) +#endif + + +#if PLATFORM_SHOW_INFO +static void platform_show_info(void) +{ + extern uint8_t __data_end__[]; + extern uint8_t _edata[]; + extern uint8_t __bss_start__[]; + extern uint8_t __bss_end__[]; + extern uint8_t __end__[]; + extern uint8_t end[]; + extern uint8_t __HeapLimit[]; + extern uint8_t __StackLimit[]; + extern uint8_t __StackTop[]; + extern uint8_t __stack[]; + extern uint8_t _estack[]; + + printf("__data_end__ %p\n", __data_end__); + printf("_edata %p\n", _edata); + printf("__bss_start__ %p\n", __bss_start__); + printf("__bss_end__ %p\n", __bss_end__); + printf("__end__ %p\n", __end__); + printf("end %p\n", end); + printf("__HeapLimit %p\n", __HeapLimit); + printf("__StackLimit %p\n", __StackLimit); + printf("__StackTop %p\n", __StackTop); + printf("__stack %p\n", __stack); + printf("_estack %p\n", _estack); + printf("\n"); + + printf("heap space [%p, %p), size %u\n\n", + __end__, _estack - PRJCONF_MSP_STACK_SIZE, + _estack - __end__ - PRJCONF_MSP_STACK_SIZE); + + printf("cpu clock %u Hz\n", HAL_GetCPUClock()); + printf("ahb1 clock %u Hz\n", HAL_GetAHB1Clock()); + printf("ahb2 clock %u Hz\n", HAL_GetAHB2Clock()); + printf("apb clock %u Hz\n", HAL_GetAPBClock()); + printf("HF clock %u Hz\n", HAL_GetHFClock()); + printf("LF clock %u Hz\n", HAL_GetLFClock()); + printf("\n"); +} +#endif /* PLATFORM_SHOW_INFO */ + +#ifdef __PRJ_CONFIG_XIP +static void platform_xip_init(void) +{ + uint32_t addr; + + addr = image_get_section_addr(IMAGE_APP_XIP_ID); + if (addr == IMAGE_INVALID_ADDR) { + FWK_ERR("no xip section\n"); + return; + } + + /* TODO: check section's validity */ + + HAL_Xip_Init(PRJCONF_IMG_FLASH, addr + IMAGE_HEADER_SIZE); +} +#endif /* __PRJ_CONFIG_XIP */ + +#if PRJCONF_WDG_EN +static void platform_wdg_feed(void *arg) +{ + FWK_DBG("feed wdg @ %u sec\n", OS_GetTime()); + HAL_WDG_Feed(); +} + +static void platform_wdg_start(void) +{ + WDG_InitParam param; + OS_Timer_t timer; + + /* init watchdog */ + param.event = WDG_EVT_RESET; + param.timeout = PRJCONF_WDG_TIMEOUT; + param.resetCycle = WDG_DEFAULT_RESET_CYCLE; + HAL_WDG_Init(¶m); + + /* create OS timer to feed watchdog */ + OS_TimerSetInvalid(&timer); + if (OS_TimerCreate(&timer, OS_TIMER_PERIODIC, platform_wdg_feed, NULL, + PRJCONF_WDG_FEED_PERIOD) != OS_OK) { + FWK_WRN("wdg timer create failed\n"); + HAL_WDG_DeInit(); + return; + } + + HAL_WDG_Start(); /* start watchdog */ + OS_TimerStart(&timer); /* start OS timer to feed watchdog */ +} +#endif /* PRJCONF_WDG_EN */ + +/* init basic platform hardware and services */ +__weak void platform_init_level0(void) +{ + HAL_Flash_Init(PRJCONF_IMG_FLASH); +#if PRJCONF_CE_EN + HAL_CE_Init(); +#endif + + img_ctrl_init(PRJCONF_IMG_FLASH, PRJCONF_IMG_ADDR, PRJCONF_IMG_SIZE); +#if (defined(__PRJ_CONFIG_XIP)) + platform_xip_init(); +#endif +} + +/* init standard platform hardware and services */ +__weak void platform_init_level1(void) +{ +#if PRJCONF_UART_EN + if ((BOARD_SUB_UART_ID < UART_NUM) && + (BOARD_SUB_UART_ID != BOARD_MAIN_UART_ID)) { + board_uart_init(BOARD_SUB_UART_ID); + } +#endif + +#if PRJCONF_SYS_CTRL_EN + sys_ctrl_create(); + #if PRJCONF_NET_EN + net_ctrl_init(); + #endif +#endif + + sysinfo_init(); + +#if PRJCONF_CONSOLE_EN + console_param_t cparam; + cparam.uart_id = BOARD_MAIN_UART_ID; + cparam.cmd_exec = main_cmd_exec; + console_start(&cparam); +#endif + +#if PRJCONF_PM_EN + pm_mode_platform_select(PRJCONF_PM_MODE); +#endif + +#if PRJCONF_NET_EN + net_sys_init(); + + struct sysinfo *sysinfo = sysinfo_get(); + net_sys_start(sysinfo->wlan_mode); + + #if PRJCONF_NET_PM_EN + pm_register_wlan_power_onoff(net_sys_onoff, PRJCONF_NET_PM_MODE); + #endif +#endif /* PRJCONF_NET_EN */ + +#if PRJCONF_WDG_EN + platform_wdg_start(); +#endif +} + +/* init extern platform hardware and services */ +__weak void platform_init_level2(void) +{ +#if PRJCONF_SPI_EN + board_spi_init(BOARD_SPI_PORT); +#endif + +#if PRJCONF_MMC_EN + SDC_InitTypeDef sdc_param; + #ifdef CONFIG_DETECT_CARD + sdc_param.cd_mode = PRJCONF_MMC_DETECT_MODE; + #endif + HAL_SDC_Init(0, &sdc_param); +#endif + +#if (PRJCONF_SOUNDCARD0_EN || PRJCONF_SOUNDCARD1_EN) + aud_mgr_init(); + snd_pcm_init(); + #if PRJCONF_SOUNDCARD0_EN + board_soundcard0_init(); + #endif + #if PRJCONF_SOUNDCARD1_EN + board_soundcard1_init(); + #endif +#endif +} + +void platform_init(void) +{ + printf("XRadio IoT WLAN SDK %s\n\n", SDK_VERSION_STR); +#if PLATFORM_SHOW_INFO + platform_show_info(); +#endif + + platform_init_level0(); + platform_init_level1(); + platform_init_level2(); +} diff --git a/platform/mcu/xr871/project/common/framework/platform_init.h b/platform/mcu/xr871/project/common/framework/platform_init.h new file mode 100644 index 0000000000..823748c8a6 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/platform_init.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PLATFORM_INIT_H_ +#define _PLATFORM_INIT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void platform_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _PLATFORM_INIT_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/container.c b/platform/mcu/xr871/project/common/framework/sys_ctrl/container.c new file mode 100644 index 0000000000..ea79e307ba --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/container.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include "kernel/os/os.h" +#include "sys/list.h" +#include "sys/param.h" +#include "sys/defs.h" +#include "container.h" + + +#define CONTAINER_DEBUG(fmt, arg...) //printf("[Container debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define CONTAINER_ALERT(fmt, arg...) printf("[Container alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define CONTAINER_ERROR(fmt, arg...) printf("[Container error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define CONTAINER_NOWAY() printf("[Container should not be here] <%s : %d> \n", __func__, __LINE__) +#define CONTAINER_NOTSUPPORT() CONTAINER_ALERT("not support command") + + +typedef struct list_node +{ + struct list_head node; + uint32_t arg; +} list_node; + +typedef struct sorted_list +{ + container_base base; + OS_Semaphore_t sem; + OS_Mutex_t lock; + struct list_head head; + struct list_head pool; + list_node *poolBuf; + int (*compare)(uint32_t newArg, uint32_t oldArg); +} sorted_list; + +typedef struct sorted_list_config +{ + uint32_t size; + int (*compare)(uint32_t oldArg, uint32_t newArg); +} sorted_list_config; + +static int sorted_list_init(struct container_base *base, uint32_t config) +{ + OS_Status ret1 = OS_FAIL; + OS_Status ret2 = OS_FAIL; + list_node *vec = NULL; + sorted_list_config *cfg = (sorted_list_config *)config; + sorted_list *impl = __containerof(base, sorted_list, base); + + INIT_LIST_HEAD(&impl->head); + INIT_LIST_HEAD(&impl->pool); + impl->base.size = cfg->size; + impl->compare = cfg->compare; + + ret1 = OS_SemaphoreCreateBinary(&impl->sem); + if (ret1 != OS_OK) + goto failed; + + ret2 = OS_MutexCreate(&impl->lock); + if (ret2 != OS_OK) + goto failed; + + vec = malloc(sizeof(list_node) * impl->base.size); + if (vec == NULL) + goto failed; + memset(vec, 0, sizeof(list_node) * impl->base.size); + impl->poolBuf = vec; + + for(int i = impl->base.size; i-- > 0; ) + { + INIT_LIST_HEAD(&vec[i].node); + list_add_tail(&vec[i].node, &impl->pool); + } + + return 0; + +failed: + if (vec != NULL) + free(vec); + if (ret1 == OS_OK) + OS_SemaphoreDelete(&impl->sem); + if (ret2 == OS_OK) + OS_MutexDelete(&impl->lock); + if (impl != NULL) + free(impl); + + return -1; +} + +static int sorted_list_deinit(struct container_base *base) +{ + sorted_list *impl = __containerof(base, sorted_list, base); + + /* TODO: flush the node left */ + + OS_SemaphoreDelete(&impl->sem); + OS_MutexDelete(&impl->lock); + if (impl->poolBuf != NULL) + free(impl->poolBuf); + if (impl != NULL) + free(impl); + + return 0; +} + +static int sorted_list_control(struct container_base *base, uint32_t cmd, uint32_t arg) +{ + sorted_list *impl = __containerof(base, sorted_list, base); + /* TODO: tbc... */ + (void)impl; + return -1; +} + +static int sorted_list_push(struct container_base *base, uint32_t arg, uint32_t timeout) +{ +#define BLOCK_WAIT_EACHTIME (3) + sorted_list *impl = __containerof(base, sorted_list, base); + list_node *node = NULL; + list_node *tmp = NULL; + + OS_MutexLock(&impl->lock, -1); /* TODO: OS should move to event_queue */ + + /* 1. get 1 node from pool */ + while ((node = list_first_entry_or_null(&impl->pool, list_node, node)) == NULL) + { + OS_MutexUnlock(&impl->lock); + OS_MSleep(BLOCK_WAIT_EACHTIME); + if (timeout <= BLOCK_WAIT_EACHTIME) { + CONTAINER_ALERT("list full and timeout"); + + return -1; + } + OS_MutexLock(&impl->lock, -1); + timeout -= BLOCK_WAIT_EACHTIME; + } + node->arg = arg; + + CONTAINER_DEBUG("get a node from pool"); + + /* 2. find a proper place and insert it */ + list_for_each_entry(tmp, &impl->head, node) + { + if (impl->compare(arg, tmp->arg) >= 0) { + tmp = list_prev_entry(tmp, node); + break; + } + } + list_add(&node->node, &tmp->node); + + CONTAINER_DEBUG("insert node to list"); + + /* 3. release sem to pop */ + OS_SemaphoreRelease(&impl->sem); + + OS_MutexUnlock(&impl->lock); + return 0; +} + +static int sorted_list_pop(struct container_base *base, uint32_t *arg, uint32_t timeout) +{ + sorted_list *impl = __containerof(base, sorted_list, base); + list_node *node = NULL; + OS_Status ret; + + ret = OS_SemaphoreWait(&impl->sem, timeout); + if (ret != OS_OK) + return -1; + + OS_MutexLock(&impl->lock, -1); + + /* 1. get node from list */ + node = list_first_entry_or_null(&impl->head, list_node, node); + if (node == NULL) + { + CONTAINER_ERROR("list empty but sem released!"); + OS_MutexUnlock(&impl->lock); + return -2; + } + *arg = node->arg; + + CONTAINER_DEBUG("get a node from list"); + + /* 2. remove the node from this and push it to pool */ + list_del(&node->node); + list_add_tail(&node->node, &impl->head); + + CONTAINER_DEBUG("remove a node from list and push it to pool"); + + OS_MutexUnlock(&impl->lock); + return 0; +} + +container_base *sorted_list_create(uint32_t size, int (*compare)(uint32_t newArg, uint32_t oldArg)) +{ + sorted_list *impl = malloc(sizeof(*impl)); + if (impl == NULL) + return NULL; + memset(impl, 0, sizeof(*impl)); + + sorted_list_config cfg; + cfg.compare = compare; + cfg.size = size; + + impl->base.control = sorted_list_control; + impl->base.deinit = sorted_list_deinit; + impl->base.pop = sorted_list_pop; + impl->base.push = sorted_list_push; + + if (sorted_list_init(&impl->base, (uint32_t)&cfg) != 0) + { + CONTAINER_ERROR("init failed"); + free(impl); + return NULL; + } + + return &impl->base; +} diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/container.h b/platform/mcu/xr871/project/common/framework/sys_ctrl/container.h new file mode 100644 index 0000000000..226025192f --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/container.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef CONTAINER_H_ +#define CONTAINER_H_ + +typedef struct container_base +{ + uint32_t size; + +// int (*init)(struct container_base *base, uint32_t config); + int (*deinit)(struct container_base *base); + int (*control)(struct container_base *base, uint32_t cmd, uint32_t arg); + int (*push)(struct container_base *base, uint32_t item, uint32_t timeout); + int (*pop)(struct container_base *base, uint32_t *item, uint32_t timeout); +} container_base; + +container_base *sorted_list_create(uint32_t size, int (*compare)(uint32_t newArg, uint32_t oldArg)); + +#endif /* CONTAINER_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/event_queue.c b/platform/mcu/xr871/project/common/framework/sys_ctrl/event_queue.c new file mode 100644 index 0000000000..433ee117bd --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/event_queue.c @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include "kernel/os/os.h" +#include "sys/list.h" +#include "sys/param.h" +#include "sys/defs.h" +#include "container.h" +#include "event_queue.h" + +#define EVTMSG_DEBUG(fmt, arg...) //printf("[event_msg debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define EVTMSG_ALERT(fmt, arg...) printf("[event_msg alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define EVTMSG_ERROR(fmt, arg...) printf("[event_msg error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define EVTMSG_NOWAY() printf("[event_msg should not be here] <%s : %d> \n", __func__, __LINE__) +#define EVTMSG_NOTSUPPORT() EVTMSG_ALERT("not support command") + + + +typedef struct prio_event_queue +{ + event_queue base; + container_base *container; +} prio_event_queue; + +static int complare_event_msg(uint32_t newArg, uint32_t oldArg) +{ + event_msg *newMsg = (event_msg *)newArg; + event_msg *oldMsg = (event_msg *)oldArg; + + return newMsg->event < oldMsg->event; +} + +static int prio_event_queue_deinit(struct event_queue *base) +{ + prio_event_queue *impl = __containerof(base, prio_event_queue, base); + + int ret = impl->container->deinit(impl->container); + if (ret == 0) + free(impl); + + return ret; +} + +static int prio_event_send(struct event_queue *base, struct event_msg *msg, uint32_t wait_ms) +{ + prio_event_queue *impl = __containerof(base, prio_event_queue, base); + + EVTMSG_DEBUG("send event: 0x%x", msg->event); + + /* TODO: cache some to faster create msg and less fragmented memory */ + struct event_msg *newMsg = malloc(sizeof(*newMsg)); + if (newMsg == NULL) + return -1; + memcpy(newMsg, msg, sizeof(*newMsg)); + + int ret = impl->container->push(impl->container, (uint32_t)newMsg, wait_ms); + if (ret != 0) + { + free(newMsg); + EVTMSG_ALERT("send event timeout"); + return -2; + } + + return 0; +} + +static int prio_event_recv(struct event_queue *base, struct event_msg *msg, uint32_t wait_ms) +{ + prio_event_queue *impl = __containerof(base, prio_event_queue, base); + event_msg *newMsg; + + int ret = impl->container->pop(impl->container, (uint32_t *)&newMsg, wait_ms); + if (ret != 0) + return -2; + + memcpy(msg, newMsg, sizeof(*newMsg)); + free(newMsg); + + EVTMSG_DEBUG("recv event: 0x%x", msg->event); + + return 0; +} + +struct event_queue *prio_event_queue_create(uint32_t queue_len) +{ + prio_event_queue *impl = malloc(sizeof(*impl)); + if (impl == NULL) + return NULL; + memset(impl, 0, sizeof(*impl)); + + impl->container = sorted_list_create(queue_len, complare_event_msg); + if (impl->container == NULL) + goto out; + impl->base.send = prio_event_send; + impl->base.recv = prio_event_recv; + impl->base.deinit = prio_event_queue_deinit; + + return &impl->base; + +out: + EVTMSG_ERROR("sorted_list_create failed"); + free(impl); + return NULL; +} + + +typedef struct normal_event_queue +{ + event_queue base; + OS_Queue_t queue; +} normal_event_queue; + +static int normal_event_queue_deinit(struct event_queue *base) +{ + normal_event_queue *impl = __containerof(base, normal_event_queue, base); + OS_Status ret; + +#if CTRL_MSG_VALIDITY_CHECK + if (!OS_QueueIsValid(&impl->queue)) { + EVTMSG_ALERT("%s(), invalid queue %p", __func__, g_ctrl_msg_queue.handle); + return 0; + } +#endif + + ret = OS_QueueDelete(&impl->queue); + if (ret != OS_OK) { + EVTMSG_ERROR("%s() failed, err 0x%x", __func__, ret); + return -1; + } + + free(impl); + + EVTMSG_DEBUG("%s()", __func__); + return 0; +} + +static int normal_event_send(struct event_queue *base, struct event_msg *msg, uint32_t wait_ms) +{ + normal_event_queue *impl = __containerof(base, normal_event_queue, base); + OS_Status ret; + + EVTMSG_DEBUG("send event: 0x%x", msg->event); + +#if CTRL_MSG_VALIDITY_CHECK + if (!OS_QueueIsValid(&impl->queue)) { + EVTMSG_ALERT("%s(), invalid queue %p", __func__, g_ctrl_msg_queue.handle); + return -1; + } +#endif + + ret = OS_QueueSend(&impl->queue, msg, wait_ms); + if (ret != OS_OK) { + EVTMSG_ERROR("%s() failed, err 0x%x", __func__, ret); + return -1; + } + return 0; +} + +static int normal_event_recv(struct event_queue *base, struct event_msg *msg, uint32_t wait_ms) +{ + normal_event_queue *impl = __containerof(base, normal_event_queue, base); + OS_Status ret; + +#if CTRL_MSG_VALIDITY_CHECK + if (!OS_QueueIsValid(&g_ctrl_msg_queue)) { + EVTMSG_ALERT("%s(), invalid queue %p", __func__, g_ctrl_msg_queue.handle); + return -1; + } +#endif + + ret = OS_QueueReceive(&impl->queue, msg, wait_ms); + if (ret != OS_OK) { + EVTMSG_ERROR("%s() failed, err 0x%x", __func__, ret); + return -1; + } + + EVTMSG_DEBUG("recv event: 0x%x", msg->event); + + return 0; +} + +struct event_queue *normal_event_queue_create(uint32_t queue_len) +{ + normal_event_queue *impl = malloc(sizeof(*impl)); + if (impl == NULL) + return NULL; + memset(impl, 0, sizeof(*impl)); + + impl->base.send = normal_event_send; + impl->base.recv = normal_event_recv; + impl->base.deinit = normal_event_queue_deinit; + + +#if CTRL_MSG_VALIDITY_CHECK + if (OS_QueueIsValid(&impl->queue)) { + EVTMSG_ALERT("control message queue already inited\n"); + return -1; + } +#endif + + if (OS_QueueCreate(&impl->queue, queue_len, sizeof(struct event_msg)) != OS_OK) { + EVTMSG_ERROR("%s() failed!", __func__); + goto out; + } + EVTMSG_DEBUG("%s()", __func__); + + return &impl->base; + +out: + if (impl != NULL) + free(impl); + return NULL; +} + + diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/event_queue.h b/platform/mcu/xr871/project/common/framework/sys_ctrl/event_queue.h new file mode 100644 index 0000000000..9c1ca97595 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/event_queue.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef EVENT_QUEUE_H_ +#define EVENT_QUEUE_H_ + +typedef struct event_msg { +// uint16_t type; +// uint16_t subtype; /* subtype = 0 means all subtype */ + uint32_t event; + uint32_t data; + void (*destruct)(uint32_t data); +} event_msg; + +typedef struct event_queue +{ +// int (*init)(struct event_queue *base, uint32_t queue_len); + int (*deinit)(struct event_queue *base); + int (*send)(struct event_queue *base, struct event_msg *msg, uint32_t wait_ms); + int (*recv)(struct event_queue *base, struct event_msg *msg, uint32_t wait_ms); +} event_queue; + + +struct event_queue *prio_event_queue_create(uint32_t queue_len); + +struct event_queue *normal_event_queue_create(uint32_t queue_len); + +#endif /* EVENT_QUEUE_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/observer.c b/platform/mcu/xr871/project/common/framework/sys_ctrl/observer.c new file mode 100644 index 0000000000..f28c442d45 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/observer.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include "sys/list.h" +#include "kernel/os/os.h" +#include "observer.h" + +#define OBSERVER_DEBUG(fmt, arg...) //printf("[Observer debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define OBSERVER_ALERT(fmt, arg...) printf("[Observer alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define OBSERVER_ERROR(fmt, arg...) printf("[Observer error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define OBSERVER_NOWAY() printf("[Observer should not be here] <%s : %d> \n", __func__, __LINE__) +#define OBSERVER_NOTSUPPORT() OBSERVER_ALERT("not support command") + + +typedef struct event_observer +{ + observer_base base; + OS_Semaphore_t sem; +} event_observer; + +static void event_trigger(struct observer_base *base, uint32_t event, uint32_t arg) +{ + event_observer *impl = __containerof(base, event_observer, base); + + OS_SemaphoreRelease(&impl->sem); +} + +observer_base *event_observer_create(uint32_t event) +{ + event_observer *obs = malloc(sizeof(*obs)); + if (obs == NULL) + return NULL; + memset(obs, 0, sizeof(*obs)); + + obs->base.event = event; +// obs->base.type = EVENT_OBSERVER; + obs->base.trigger = event_trigger; + INIT_LIST_HEAD(&obs->base.node); + OS_SemaphoreCreateBinary(&obs->sem); + + return &obs->base; +} + +OS_Status event_wait(observer_base *base, OS_Time_t timeout) +{ + event_observer *impl = __containerof(base, event_observer, base); + + return OS_SemaphoreWait(&impl->sem, timeout); +} + + +typedef struct callback_observer +{ + observer_base base; + void (*cb)(uint32_t event, uint32_t arg); +} callback_observer; + +static void trigger_callback(struct observer_base *base, uint32_t event, uint32_t arg) +{ + callback_observer *impl = __containerof(base, callback_observer, base); + + impl->cb(event, arg); +} + +observer_base *callback_observer_create(uint32_t event, void (*cb)(uint32_t event, uint32_t arg)) +{ + callback_observer *obs = malloc(sizeof(*obs)); + if (obs == NULL) + return NULL; + memset(obs, 0, sizeof(*obs)); + + obs->base.event = event; +// obs->base.type = CALLBACK_OBSERVER; + obs->base.trigger = trigger_callback; + INIT_LIST_HEAD(&obs->base.node); + obs->cb = cb; + + return &obs->base; +} + + +typedef struct thread_observer +{ + observer_base base; + OS_Thread_t thd; + void (*run)(uint32_t event, uint32_t arg); + void (*exception)(int ret); + uint32_t stack; + OS_Priority prio; + + uint32_t event; + uint32_t arg; +} thread_observer; + +static void wrap_thread(void *arg) +{ + thread_observer *impl = (thread_observer *)arg; + + impl->run(impl->event, impl->arg); + + OS_ThreadDelete(&impl->thd); +} + +static void trigger_thread(struct observer_base *base, uint32_t event, uint32_t arg) +{ + thread_observer *impl = __containerof(base, thread_observer, base); + OS_Status ret; + + impl->event = event; + impl->arg = arg; + + if (OS_ThreadIsValid(&impl->thd)) + { + OBSERVER_ALERT("thread still running or not init"); + return; + } + + if ((ret = OS_ThreadCreate(&impl->thd, "Trigger Thread", wrap_thread, impl, impl->prio, impl->stack)) != OS_OK) + { + OBSERVER_ERROR("thread create error, maybe no RAM to create"); + if (impl->exception != NULL) + impl->exception(ret); + } +} + +void thread_observer_throw(struct observer_base *base, void (*exception)(int ret)) +{ + thread_observer *impl = __containerof(base, thread_observer, base); + + impl->exception = exception; +} + +/* TODO: thread_observer_copy_data(struct observer_base *base, int (*copy)(uint32_t data)) */ + +observer_base *thread_observer_create(uint32_t event, void (*run)(uint32_t event, uint32_t arg), uint32_t stackSize, OS_Priority prio) +{ + thread_observer *obs = malloc(sizeof(*obs)); + if (obs == NULL) + return NULL; + memset(obs, 0, sizeof(*obs)); + + /* TODO: need mode in case of trigger serval times */ + obs->base.event = event; +// obs->base.type = THREAD_OBSERVER; + obs->base.trigger = trigger_thread; + INIT_LIST_HEAD(&obs->base.node); + obs->run = run; + obs->stack = stackSize; + obs->prio = prio; + + return &obs->base; +} + +int observer_destroy(observer_base *base) +{ + if (base == NULL) + return -1; + if (base->state != OBSERVER_ILDE) + return -1; + free(base); + return 0; +} + + diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/observer.h b/platform/mcu/xr871/project/common/framework/sys_ctrl/observer.h new file mode 100644 index 0000000000..703f099f13 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/observer.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef OBSERVER_H_ +#define OBSERVER_H_ + +#include +#include "sys/list.h" +#include "kernel/os/os.h" + + +typedef enum observer_types +{ + EVENT_OBSERVER, + CALLBACK_OBSERVER, + THREAD_OBSERVER, +} observer_types; + +typedef enum observer_modes +{ + SINGLE_OBSERVER, + CONTINUE_OBSERVER, +} observer_modes; + +typedef struct observer_base +{ + struct list_head node; + uint32_t event; + int state; +// uint32_t type; +// observer_modes mode; + + void (*trigger)(struct observer_base *base, uint32_t event, uint32_t arg); +} observer_base; + +typedef enum observer_state +{ + OBSERVER_ILDE, + OBSERVER_ATTACHED, + OBSERVER_DETACHED, + OBSERVER_WORKING, +} observer_state; + +observer_base *event_observer_create(uint32_t event); + +OS_Status event_wait(observer_base *base, OS_Time_t timeout); + +observer_base *callback_observer_create(uint32_t event, void (*cb)(uint32_t event, uint32_t arg)); + +observer_base *thread_observer_create(uint32_t event, void (*run)(uint32_t event, uint32_t arg), uint32_t stackSize, OS_Priority prio); + +void thread_observer_throw(struct observer_base *base, void (*exception)(int ret)); + +int observer_destroy(observer_base *base); + +#endif /* OBSERVER_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/publisher.c b/platform/mcu/xr871/project/common/framework/sys_ctrl/publisher.c new file mode 100644 index 0000000000..aa9eb8c320 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/publisher.c @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "sys/list.h" +#include "sys/param.h" +#include "sys/defs.h" +#include "sys/interrupt.h" +#include "kernel/os/os.h" +#include "observer.h" +#include "event_queue.h" +#include "publisher.h" + +#define PUBLISHER_DEBUG(fmt, arg...) //printf("[Publisher debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define PUBLISHER_ALERT(fmt, arg...) printf("[Publisher alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define PUBLISHER_ERROR(fmt, arg...) printf("[Publisher error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define PUBLISHER_NOWAY() printf("[Publisher should not be here] <%s : %d> \n", __func__, __LINE__) +#define PUBLISHER_NOTSUPPORT() PUBLISHER_ALERT("not support command") + + +#define PUBLISHER_THREAD_STACKSIZE (2 * 1024) + +static void atomic_set(int *var, uint32_t cnt) +{ + arch_irq_disable(); + *var = cnt; + arch_irq_enable(); +} + +static int attach(struct publisher_base *base, observer_base *obs) +{ + int ret = 0; + + PUBLISHER_DEBUG("new observe event: 0x%x", obs->event); + + /* TODO: entry critical section to sync list */ + OS_RecursiveMutexLock(&base->lock, -1); + if (obs->state == OBSERVER_DETACHED) + obs->state = OBSERVER_ATTACHED; + else if (list_empty(&obs->node)) + { + arch_irq_disable(); + list_add_tail(&obs->node, &base->head); + obs->state = OBSERVER_ATTACHED; + arch_irq_enable(); + } + else + { + PUBLISHER_ALERT("new observe event: %u failed", obs->event); + ret = -1; + } + OS_RecursiveMutexUnlock(&base->lock); + /* TODO: exit critical section */ + + return ret; +} + +static int detach(struct publisher_base *base, observer_base *obs) +{ + /* TODO: entry critical section to sync list or return failed */ + OS_RecursiveMutexLock(&base->lock, -1); /* it can't call in interrupt, should be fixed */ + if (base->state == PUBLISHER_IDLE) + { + list_del(&obs->node); + obs->state = OBSERVER_ILDE; + } + else + { + atomic_set(&obs->state, OBSERVER_DETACHED); + } + OS_RecursiveMutexUnlock(&base->lock); + /* TODO: exit critical section */ + + PUBLISHER_DEBUG("remove observe event: %d", obs->event); + + return 0; +} + +static int notify(struct publisher_base *base, uint32_t event, uint32_t arg) +{ + observer_base *obs = NULL; + observer_base *itor = NULL; + observer_base *safe = NULL; + int cnt = 0; + + /* TODO: define some event to debug, for example, event -1 can be detect how many observer now. */ + + OS_RecursiveMutexLock(&base->lock, -1); + atomic_set(&base->state, PUBLISHER_WORKING); + + /* trigger observers */ + list_for_each_entry(itor, &base->head, node) + { + /* TODO: detect the observer if is locked by detach or sth else */ + if (base->compare(event, itor->event) == 0 && itor->state == OBSERVER_ATTACHED) + { + obs = itor; + obs->trigger(obs, event, arg); + cnt++; + } + } + + /* remove observers detached in trigger function */ + list_for_each_entry_safe(itor, safe, &base->head, node) + { + if (itor->state == OBSERVER_DETACHED) + { + list_del(&itor->node); + atomic_set(&itor->state, OBSERVER_ILDE); + } + } + + atomic_set(&base->state, PUBLISHER_IDLE); + OS_RecursiveMutexUnlock(&base->lock); + + if (obs == NULL) + { + PUBLISHER_DEBUG("no observer eyes on this event"); + return 0; + } + + return cnt; +} + +static void main_publisher(void *arg) +{ + publisher_base *base = (publisher_base *)arg; + struct event_msg msg; + int ret; + + while (1) + { + ret = base->queue->recv(base->queue, &msg, -1); + if (ret != 0) { + PUBLISHER_ERROR("queue error"); + continue; + } + + ret = base->notify(base, msg.event, msg.data); + PUBLISHER_DEBUG("event 0x%x notified %d observers", msg.event, ret); + + if (msg.destruct != NULL) + msg.destruct(msg.data); + } + +} + +/* TODO: add stack size */ +publisher_base *publisher_create(struct event_queue *queue, int (*compare)(uint32_t newEvent, uint32_t obsEvent), OS_Priority prio, uint32_t stack) +{ + publisher_base *base = malloc(sizeof(*base)); + if (base == NULL) + return NULL; + memset(base, 0, sizeof(*base)); + + OS_Status ret = OS_RecursiveMutexCreate(&base->lock); + if (ret != OS_OK) + goto failed; + + INIT_LIST_HEAD(&base->head); + base->queue = queue; + base->attach = attach; + base->detach = detach; + base->notify = notify; + base->compare = compare; + + if (OS_ThreadCreate(&base->thd, "Publish Thread", main_publisher, + base, prio, stack) != OS_OK) + { + PUBLISHER_ERROR("thread create error, maybe no RAM to create"); + goto failed; + } + + return base; + +failed: + if (ret == OS_OK) + OS_RecursiveMutexDelete(&base->lock); + if (base != NULL) + free(base); + + return NULL; +} + diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/publisher.h b/platform/mcu/xr871/project/common/framework/sys_ctrl/publisher.h new file mode 100644 index 0000000000..55b9039fd5 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/publisher.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef PUBLISHER_H_ +#define PUBLISHER_H_ + +#include "sys/list.h" +#include "kernel/os/os.h" +#include "observer.h" + + +typedef struct publisher_base +{ + struct list_head head; + struct event_queue *queue; + OS_Thread_t thd; + OS_Mutex_t lock; // or uint32_t sync by atomic; + int state; + + int (*attach)(struct publisher_base *base, observer_base *obs); + int (*detach)(struct publisher_base *base, observer_base *obs); + int (*notify)(struct publisher_base *base, uint32_t event, uint32_t arg); + int (*compare)(uint32_t newEvent, uint32_t obsEvent); +} publisher_base; + +typedef enum publisher_state +{ + PUBLISHER_IDLE, + PUBLISHER_WORKING, +} publisher_state; + +publisher_base *publisher_create(struct event_queue *queue, int (*compare)(uint32_t newEvent, uint32_t obsEvent), + OS_Priority prio, uint32_t stack); + + +#endif /* PUBLISHER_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/sys_ctrl.c b/platform/mcu/xr871/project/common/framework/sys_ctrl/sys_ctrl.c new file mode 100644 index 0000000000..9104caf77f --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/sys_ctrl.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "sys/list.h" +#include "kernel/os/os.h" +#include "observer.h" +#include "publisher.h" +#include "event_queue.h" +#include "sys_ctrl.h" + + +#define SYS_CTRL_DEBUG(fmt, arg...) //printf("[SYS_CTRL debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define SYS_CTRL_ALERT(fmt, arg...) printf("[SYS_CTRL alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define SYS_CTRL_ERROR(fmt, arg...) printf("[SYS_CTRL error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define SYS_CTRL_NOWAY() printf("[SYS_CTRL should not be here] <%s : %d> \n", __func__, __LINE__) +#define SYS_CTRL_NOTSUPPORT() SYS_CTRL_ALERT("not support command") + + +static event_queue *g_sys_queue = NULL; +static publisher_base *g_sys_publisher = NULL; + +static int compare(uint32_t newEvent, uint32_t obsEvent) +{ + if (!CMP_EVENT_TYPE(newEvent, obsEvent) && (EVENT_SUBTYPE(obsEvent) == ALL_SUBTYPE || newEvent == obsEvent)) + return 0; + + SYS_CTRL_DEBUG("cmp -1, newEvent: 0x%x, obsEvent: 0x%x", newEvent, obsEvent); + + return -1; +} + +int sys_ctrl_create(void) +{ + uint32_t queue_len = PRJCONF_SYS_CTRL_QUEUE_LEN; + + if (g_sys_queue == NULL) +#if SYS_CTRL_PRIO_QUEUE + g_sys_queue = prio_event_queue_create(queue_len); +#else + g_sys_queue = normal_event_queue_create(queue_len); +#endif + if (g_sys_queue == NULL) + { + SYS_CTRL_ERROR("create queue failed"); + return -1; + } + + if (g_sys_publisher == NULL) + g_sys_publisher = publisher_create(g_sys_queue, compare, PRJCONF_SYS_CTRL_PRIO, PRJCONF_SYS_CTRL_STACK_SIZE); + if (g_sys_publisher == NULL) + { + SYS_CTRL_ERROR("create publisher failed"); + return -1; + } + + return 0; +} + +int sys_ctrl_attach(observer_base *obs) +{ + if (g_sys_publisher == NULL) + return -1; + + return g_sys_publisher->attach(g_sys_publisher, obs); +} + +int sys_ctrl_detach(observer_base *obs) +{ + if (g_sys_publisher == NULL) + return -1; + + return g_sys_publisher->detach(g_sys_publisher, obs); +} + +static __inline int event_send(event_queue *queue, uint16_t type, uint16_t subtype, uint32_t data, void (*destruct)(uint32_t data), uint32_t wait_ms) +{ + struct event_msg msg = {MK_EVENT(type, subtype), data, destruct}; + return queue->send(queue, &msg, wait_ms); +} + +/* +static void freeMsgData(uint32_t data) +{ + free((void *)data); +} +*/ + +int sys_event_send(uint16_t type, uint16_t subtype, uint32_t data, uint32_t wait_ms) +{ + if (g_sys_queue == NULL) + return -1; + + return event_send(g_sys_queue, type, subtype, data, NULL, wait_ms); +} + +/*int sys_event_send_with_free(uint16_t type, uint16_t subtype, uint32_t data, uint32_t wait_ms) +{ + if (g_sys_queue == NULL) + return -1; + + return event_send(g_sys_queue, type, subtype, data, freeMsgData, wait_ms); +}*/ + +int sys_event_send_with_destruct(uint16_t type, uint16_t subtype, uint32_t data, void (*destruct)(uint32_t data), uint32_t wait_ms) +{ + if (g_sys_queue == NULL) + return -1; + + return event_send(g_sys_queue, type, subtype, data, destruct, wait_ms); +} diff --git a/platform/mcu/xr871/project/common/framework/sys_ctrl/sys_ctrl.h b/platform/mcu/xr871/project/common/framework/sys_ctrl/sys_ctrl.h new file mode 100644 index 0000000000..b3deee9440 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sys_ctrl/sys_ctrl.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef SYS_CTRL_H_ +#define SYS_CTRL_H_ + +#include +#include "event_queue.h" +#include "publisher.h" +#include "observer.h" + +#define SYS_CTRL_PRIO_QUEUE (0) + +#define ALL_SUBTYPE (0xFFFF) + +typedef enum ctrl_msg_type{ + CTRL_MSG_TYPE_SYSTEM = 0, + CTRL_MSG_TYPE_NETWORK, + CTRL_MSG_TYPE_VKEY, + CTRL_MSG_VOLUME, + TEST_SYS_CTRL, +} ctrl_msg_type; + +typedef enum key_msg_subtype { + CTRL_MSG_SUB_TYPE_AD_BUTTON = 0, + CTRL_MSG_SUB_TYPE_GPIO_BUTTON, + CTRL_MSG_SUB_TYPE_ALL = ALL_SUBTYPE, +} key_msg_subtype; + +/** @brief Get type from event */ +#define EVENT_TYPE(event) ((uint16_t)((event) >> 16)) + +/** @brief Get subtype from event */ +#define EVENT_SUBTYPE(event) ((uint16_t)((event) & 0xFFFF)) + +/** @brief Make event from type and subtype */ +#define MK_EVENT(type, subtype) \ + (((uint32_t)(type) << 16) | ((uint32_t)(subtype) & 0xFFFF)) + +#define CMP_EVENT_TYPE(event1, event2) ((event1 ^ event2) & 0xFFFF0000) + + +static __inline observer_base *sys_callback_observer_create(uint16_t type, uint16_t subtype, void (*cb)(uint32_t event, uint32_t arg)) +{ + return callback_observer_create(MK_EVENT(type, subtype), cb); +} + +int sys_ctrl_create(void); + +int sys_ctrl_attach(observer_base *obs); + +int sys_ctrl_detach(observer_base *obs); + +int sys_event_send(uint16_t type, uint16_t subtype, uint32_t data, uint32_t wait_ms); + +int sys_event_send_with_destruct(uint16_t type, uint16_t subtype, uint32_t data, void (*destruct)(uint32_t data), uint32_t wait_ms); + +#define sys_event_send_with_free(type, subtype, data, wait_ms) \ + sys_event_send_with_destruct(type, subtype, data, (void (*)(uint32_t))free, wait_ms) + + +#endif /* SYS_CTRL_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sysinfo.c b/platform/mcu/xr871/project/common/framework/sysinfo.c new file mode 100644 index 0000000000..78657cb19a --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sysinfo.c @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "efpg/efpg.h" +#include "sys/fdcm.h" +#include "lwip/inet.h" +#include "lwip/ip_addr.h" +#include "sysinfo.h" +#include "sysinfo_debug.h" + +static struct sysinfo g_sysinfo; +static fdcm_handle_t *g_fdcm_hdl; + +static uint8_t m_sysinfo_mac_addr[] = { 0x00, 0x80, 0xE1, 0x29, 0xE8, 0xD1 }; + +static void sysinfo_init_mac_addr(void) +{ + struct sysinfo *info; + + switch (PRJCONF_MAC_ADDR_SOURCE) { + case SYSINFO_MAC_ADDR_CODE: + SYSINFO_DBG("mac addr source: code\n"); + memcpy(g_sysinfo.mac_addr, m_sysinfo_mac_addr, SYSINFO_MAC_ADDR_LEN); + return; + case SYSINFO_MAC_ADDR_EFUSE: + SYSINFO_DBG("mac addr source: eFuse\n"); + if (efpg_read(EFPG_FIELD_MAC, g_sysinfo.mac_addr) != 0) { + SYSINFO_WRN("failed to read MAC address from eFuse\n"); + goto random_mac_addr; + } + return; + case SYSINFO_MAC_ADDR_FLASH: + SYSINFO_DBG("mac addr source: flash\n"); + info = malloc(SYSINFO_SIZE); + if (info == NULL) { + SYSINFO_ERR("malloc failed\n"); + goto random_mac_addr; + } + if (fdcm_read(g_fdcm_hdl, info, SYSINFO_SIZE) != SYSINFO_SIZE) { + SYSINFO_WRN("failed to read MAC address from flash\n"); + free(info); + goto random_mac_addr; + } + memcpy(g_sysinfo.mac_addr, info->mac_addr, SYSINFO_MAC_ADDR_LEN); + free(info); + return; + default: + SYSINFO_ERR("invalid mac addr source\n"); + goto random_mac_addr; + } + +random_mac_addr: + SYSINFO_DBG("random mac address\n"); + + int i; + uint32_t chipid[4] = {0}; + + g_sysinfo.mac_addr[0] = 0x00; + g_sysinfo.mac_addr[1] = 0x54; + efpg_read(EFPG_FIELD_CHIPID, chipid); + + for (i = 2; i < SYSINFO_MAC_ADDR_LEN; i++) { + srand(chipid[i - 2]); + g_sysinfo.mac_addr[i] = rand() % 256; + } +} + +static void sysinfo_init_value(void) +{ + if (sysinfo_load() != 0) { + sysinfo_default(); + return; + } + + if (PRJCONF_MAC_ADDR_SOURCE != SYSINFO_MAC_ADDR_FLASH) { + sysinfo_init_mac_addr(); + } +} + +/** + * @brief Initialize the sysinfo module + * @return 0 on success, -1 on failure + */ +int sysinfo_init(void) +{ + g_fdcm_hdl = fdcm_open(PRJCONF_SYSINFO_FLASH, PRJCONF_SYSINFO_ADDR, PRJCONF_SYSINFO_SIZE); + if (g_fdcm_hdl == NULL) { + SYSINFO_ERR("fdcm open failed, hdl %p\n", g_fdcm_hdl); + return -1; + } + + sysinfo_init_value(); + + return 0; +} + +/** + * @brief DeInitialize the sysinfo module + * @return None + */ +void sysinfo_deinit(void) +{ + fdcm_close(g_fdcm_hdl); +} + +/** + * @brief Set default value to sysinfo + * @return 0 on success, -1 on failure + */ +int sysinfo_default(void) +{ + if (g_fdcm_hdl == NULL) { + SYSINFO_ERR("uninitialized, hdl %p\n", g_fdcm_hdl); + return -1; + } + + memset(&g_sysinfo, 0, SYSINFO_SIZE); + + /* MAC address */ + sysinfo_init_mac_addr(); + + /* wlan mode */ + g_sysinfo.wlan_mode = WLAN_MODE_STA; + + /* netif STA */ + g_sysinfo.sta_use_dhcp = 1; + + /* netif AP */ + IP4_ADDR(&g_sysinfo.netif_ap_param.ip_addr, 192, 168, 51, 1); + IP4_ADDR(&g_sysinfo.netif_ap_param.net_mask, 255, 255, 255, 0); + IP4_ADDR(&g_sysinfo.netif_ap_param.gateway, 192, 168, 51, 1); + + SYSINFO_DBG("set default value\n"); + + return 0; +} + +/** + * @brief Save sysinfo to flash + * @return 0 on success, -1 on failure + */ +int sysinfo_save(void) +{ + if (g_fdcm_hdl == NULL) { + SYSINFO_ERR("uninitialized, hdl %p\n", g_fdcm_hdl); + return -1; + } + + if (fdcm_write(g_fdcm_hdl, &g_sysinfo, SYSINFO_SIZE) != SYSINFO_SIZE) { + SYSINFO_ERR("fdcm write failed\n"); + return -1; + } + + SYSINFO_DBG("save sysinfo to flash\n"); + + return 0; +} + +/** + * @brief Load sysinfo from flash + * @return 0 on success, -1 on failure + */ +int sysinfo_load(void) +{ + if (g_fdcm_hdl == NULL) { + SYSINFO_ERR("uninitialized, hdl %p\n", g_fdcm_hdl); + return -1; + } + + if (fdcm_read(g_fdcm_hdl, &g_sysinfo, SYSINFO_SIZE) != SYSINFO_SIZE) { + SYSINFO_WRN("fdcm read failed\n"); + return -1; + } + + SYSINFO_DBG("load sysinfo from flash\n"); + + return 0; +} + +/** + * @brief Get the pointer of the sysinfo + * @return Pointer to the sysinfo, NULL on failure + */ +struct sysinfo *sysinfo_get(void) +{ + if (g_fdcm_hdl == NULL) { + SYSINFO_ERR("uninitialized, hdl %p\n", g_fdcm_hdl); + return NULL; + } + + return &g_sysinfo; +} + diff --git a/platform/mcu/xr871/project/common/framework/sysinfo.h b/platform/mcu/xr871/project/common/framework/sysinfo.h new file mode 100644 index 0000000000..3da9f509e1 --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sysinfo.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYSINFO_H_ +#define _SYSINFO_H_ + +#include +#include "lwip/netif.h" +#include "net/wlan/wlan.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Sysinfo MAC address source definition + */ +#define SYSINFO_MAC_ADDR_CODE (0x0U) +#define SYSINFO_MAC_ADDR_EFUSE (0x1U) +#define SYSINFO_MAC_ADDR_FLASH (0x2U) + +#define SYSINFO_MAC_ADDR_LEN (6) + +#define SYSINFO_SSID_LEN_MAX (32) +#define SYSINFO_PSK_LEN_MAX (65) + +/** + * @brief Sysinfo station wlan parameters definition + */ +struct sysinfo_wlan_sta_param { + uint8_t ssid[SYSINFO_SSID_LEN_MAX]; + uint8_t ssid_len; + + uint8_t psk[SYSINFO_PSK_LEN_MAX]; +}; + +/** + * @brief Sysinfo AP wlan parameters definition + */ +struct sysinfo_wlan_ap_param { + uint8_t ssid[SYSINFO_SSID_LEN_MAX]; + uint8_t ssid_len; + + uint8_t psk[SYSINFO_PSK_LEN_MAX]; + + uint8_t channel; +}; + +/** + * @brief Sysinfo net interface parameters definition + */ +struct sysinfo_netif_param { +#ifdef __CONFIG_LWIP_V1 + ip_addr_t ip_addr; + ip_addr_t net_mask; + ip_addr_t gateway; +#elif LWIP_IPV4 /* now only for IPv4 */ + ip4_addr_t ip_addr; + ip4_addr_t net_mask; + ip4_addr_t gateway; +#else + #error "IPv4 not support!" +#endif +}; + +/** + * @brief Sysinfo structure definition + */ +struct sysinfo { + uint32_t version; + + uint32_t sta_use_dhcp : 1; + + uint8_t mac_addr[SYSINFO_MAC_ADDR_LEN]; + + enum wlan_mode wlan_mode; + + struct sysinfo_wlan_sta_param wlan_sta_param; + struct sysinfo_wlan_ap_param wlan_ap_param; + + struct sysinfo_netif_param netif_sta_param; + struct sysinfo_netif_param netif_ap_param; +}; + +#define SYSINFO_SIZE sizeof(struct sysinfo) + +int sysinfo_init(void); +void sysinfo_deinit(void); + +int sysinfo_default(void); + +int sysinfo_save(void); +int sysinfo_load(void); + +struct sysinfo *sysinfo_get(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSINFO_H_ */ diff --git a/platform/mcu/xr871/project/common/framework/sysinfo_debug.h b/platform/mcu/xr871/project/common/framework/sysinfo_debug.h new file mode 100644 index 0000000000..81c09c935a --- /dev/null +++ b/platform/mcu/xr871/project/common/framework/sysinfo_debug.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYSINFO_DEBUG_H_ +#define _SYSINFO_DEBUG_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SYSINFO_DBG_ON 0 +#define SYSINFO_WRN_ON 0 +#define SYSINFO_ERR_ON 1 +#define SYSINFO_ABORT_ON 0 + +#define SYSINFO_SYSLOG printf +#define SYSINFO_ABORT() do { } while (0) + +#define SYSINFO_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + SYSINFO_SYSLOG(fmt, ##arg); \ + } while (0) + +#define SYSINFO_DBG(fmt, arg...) \ + SYSINFO_LOG(SYSINFO_DBG_ON, "[sysinfo] "fmt, ##arg) + +#define SYSINFO_WRN(fmt, arg...) \ + SYSINFO_LOG(SYSINFO_WRN_ON, "[sysinfo WRN] "fmt, ##arg) + +#define SYSINFO_ERR(fmt, arg...) \ + do { \ + SYSINFO_LOG(SYSINFO_ERR_ON, "[sysinfo ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (SYSINFO_ABORT_ON) \ + SYSINFO_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSINFO_DEBUG_H_ */ diff --git a/platform/mcu/xr871/project/common/startup/gcc/exception.c b/platform/mcu/xr871/project/common/startup/gcc/exception.c new file mode 100644 index 0000000000..3717981e44 --- /dev/null +++ b/platform/mcu/xr871/project/common/startup/gcc/exception.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "kernel/os/os.h" +#include "sys/param.h" +#include "driver/chip/chip.h" + +#ifndef __CONFIG_BOOTLOADER + +#define DUMP_BUF_LEN 64 + +#define readb(addr) (*((volatile unsigned char *)(addr))) +#define readw(addr) (*((volatile unsigned short *)(addr))) +#define readl(addr) (*((volatile unsigned int *)(addr))) + +#define CPU_REG_NVIC_ICSR (readl(0xE000ED04)) /* Int Ctrl State Reg. */ +#define CPU_REG_NVIC_SHCSR (readl(0xE000ED24)) /* Hard Fault Status Reg. */ +#define CPU_REG_NVIC_HFSR (readl(0xE000ED2C)) /* Hard Fault Status Reg. */ +#define CPU_REG_NVIC_DFSR (readl(0xE000ED30)) /* Debug Fault Status Reg. */ +#define CPU_REG_NVIC_MMFAR (readl(0xE000ED34)) /* Mem Manage Addr Reg. */ +#define CPU_REG_NVIC_BFAR (readl(0xE000ED38)) /* Bus Fault Addr Reg. */ +#define CPU_REG_FPU_FPSCR (readl(0xE000ED38)) /* FP status and control Reg. */ + +extern uint8_t __text_start__[]; +extern uint8_t __text_end__[]; +extern uint8_t _estack[]; + +#if configDEBUG_TRACE_TASK_MOREINFO +static char dbg_tasks_buf[1024]; +#endif + +/* defined for other modules to trace exception */ +volatile int exceptin_step; + +/* + * GET CURRENT EXCETOPM + * + * Description: get the source number of current exception, include all exceptions. + * Arguments : none. + * Returns : the source number of current exception. + * Note : + */ +static uint32_t intc_get_current_exception(void) +{ + return (CPU_REG_NVIC_ICSR & 0x3ff); +} + +static void exception_hex_dump(const uint32_t *addr, uint32_t num) +{ + uint32_t i; + + for (i = 0; i < num; i++) { + if ((i & 0x03) == 0x0) + printf("\n[%p]: ", addr); + printf("0x%08x ", *addr++); + } + printf("\n"); +} + +/* + * EXCEPTION ENTRY + * + * Description: the entry of CPU exception, mainly for CPU nmi, hard fault, + * memmanger fault, bus fault, usage fault, SVCall, debugmonitor exception. + * + * register list in stack: + * ---------LOW ADDR-------- + * R4 <-PSP(pstack) + * R5 + * R6 + * R7 + * R8 + * R9 + * R10 + * R11 <-PSP+4*7 + * R0 <-PSP+4*8 + * R1 + * R2 + * R3 + * R12 <-PSP+4*12 + * R14(LR) <-PSP+4*13 + * R15(PC) <-PSP+4*14 + * xPSR <-PSP+4*15 + * --------HIGH ADDR-------- + * Arguments : pstack:the pointer of stack, PSP before the exception happen. + * Returns : OK if process CPU exception succeeded, others if failed. + */ +int32_t exception_entry(uint32_t *pstack, uint32_t *msp, uint32_t *psp) +{ + uint32_t i; + uint32_t exceptionno = intc_get_current_exception(); + const uint32_t *add = pstack + 16; + uint32_t lr, pc; + uint32_t len; + + /* intno can't beyond then 16 */ + //ASSERT(exceptionno < 16); + + printf("\nexception:%d happen!!\n", exceptionno); + printf("appos pstack:0x%x msp:0x%x psp:0x%x\n", + (uint32_t)pstack, (uint32_t)msp, (uint32_t)psp); + + switch (exceptionno) { + case 2: + printf("NMI happen\n"); + break; + case 3: + printf("hard fault happen, HFSR:0x%x\n", CPU_REG_NVIC_HFSR); + printf("memm fault maybe happen, MFSR:0x%x, MMFAR:0x%x\n", + readb(0xE000ED28), CPU_REG_NVIC_MMFAR); + printf("bus fault maybe happen, BFSR:0x%x, BFAR:0x%x\n", + readb(0xE000ED29), CPU_REG_NVIC_BFAR); + printf("usage fault maybe happen, UFSR:0x%x\n", readw(0xE000ED2A)); + break; + case 4: + printf("memm fault happen, MFSR:0x%x, MMFAR:0x%x\n", + readb(0xE000ED28), CPU_REG_NVIC_MMFAR); + break; + case 5: + printf("bus fault happen, BFSR:0x%x, BFAR:0x%x\n", + readb(0xE000ED29), CPU_REG_NVIC_BFAR); + break; + case 6: + printf("usage fault happen, UFSR:0x%x\n", readw(0xE000ED2A)); + break; + case 11: + printf("SVCall fault happen\n"); + break; + case 12: + printf("SVCall fault happen, DFSR:0x%x\n", CPU_REG_NVIC_DFSR); + break; + default: + /* invalid exception nr */ + printf("invalid exception nr\n"); + } + + /* print R0-R3 */ + printf("CPU registers:\n"); + for (i = 0; i <= 3; i++) { + printf("R%02d:[%p]: 0x%08x\n", i, (pstack + (8 + i)), *(pstack + (8 + i))); + } + + /* print R4-R11 */ + for (i = 0; i <= 7; i++) { + printf("R%02d:[%p]: 0x%08x\n", i + 4, (pstack + i), *(pstack + i)); + } + + /* print R12, R14(LR), R15(PC), xPSR */ + printf("R12:[%p]: 0x%08x\n", (pstack + 12), *(pstack + 12)); + lr = *(pstack + 13); + printf("R14(LR):[%p]: 0x%08x\n", (pstack + 13), lr); + pc = *(pstack + 14); + printf("R15(PC):[%p]: 0x%08x\n", (pstack + 14), pc); + printf("xPSR:[%p]: 0x%08x\n", (pstack + 15), *(pstack + 15)); + printf("SHCSR:0x%08x step:%x\n", CPU_REG_NVIC_SHCSR, exceptin_step); +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + printf("FPSCR:0x%08x\n", CPU_REG_FPU_FPSCR); +#endif + + printf("\nstack info:"); + if ((((uint32_t)add) + DUMP_BUF_LEN*4) <= (uint32_t)_estack) + len = DUMP_BUF_LEN; + else + len = (((uint32_t)_estack) - ((uint32_t)add))/4; + len = MIN(len, DUMP_BUF_LEN*2); + exception_hex_dump(add, len); + + printf("\n[LR]:0x%x", lr); + lr &= ~0x07; + if (lr > (uint32_t)__text_start__ && lr < (uint32_t)__text_end__) { + lr -= DUMP_BUF_LEN * 2; + exception_hex_dump((const uint32_t *)lr, DUMP_BUF_LEN); + } + + printf("\n[PC]:0x%x", pc); + pc &= ~0x07; + if (pc < (uint32_t)__text_end__) { + pc -= DUMP_BUF_LEN * 2; + pc = (pc < (uint32_t)__text_end__) ? pc : 0; + exception_hex_dump((const uint32_t *)pc, DUMP_BUF_LEN); + } + +#if configDEBUG_TRACE_TASK_MOREINFO + printf("\ntasks state:\n"); + vTaskList(dbg_tasks_buf); + printf("%s\n", dbg_tasks_buf); +#endif + + /* if happen fault, print important information and drop-dead halt */ + while (1) + ; + + return 0; +} + +void exception_panic(const char *file, const char *func, const int line) +{ + printf("panic at %s func:%s line:%d!!\n", file, func, line); + + __asm volatile ("bkpt 0"); +} + +#endif /* __CONFIG_BOOTLOADER */ diff --git a/platform/mcu/xr871/project/common/startup/gcc/retarget.c b/platform/mcu/xr871/project/common/startup/gcc/retarget.c new file mode 100644 index 0000000000..e92a537d35 --- /dev/null +++ b/platform/mcu/xr871/project/common/startup/gcc/retarget.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "compiler.h" +#include "driver/chip/system_chip.h" +#include "driver/chip/hal_global.h" +#include "common/board/board.h" + +extern int stdout_init(void); + +void hardware_init_hook(void) +{ + HAL_BoardIoctlCbRegister(board_ioctl); + SystemInit(); +} + +int __wrap_main(void) +{ + SystemCoreClockUpdate(); + HAL_GlobalInit(); + __real_main(); + return -1; +} + +//#ifdef __CONFIG_MALLOC_USE_STDLIB +// +///* Linker defined symbol used by _sbrk to indicate where heap should start. */ +//extern uint8_t __end__[]; /* heap start address */ +//extern uint8_t _estack[]; /* heap end address */ +// +//static uint8_t *heap = __end__; +// +///* Dynamic memory allocation related syscall. */ +//void *_sbrk(int incr) +//{ +// uint8_t *prev_heap = heap; +// uint8_t *new_heap = heap + incr; +// +// /* avoid corrupting heap data by the increase of main stack (MSP) */ +// if (new_heap >= _estack - PRJCONF_MSP_STACK_SIZE) { +// printf("heap exhausted, incr %d, %p >= %p\n", +// incr, new_heap, _estack - PRJCONF_MSP_STACK_SIZE); +// return (void *)-1; +// } +// +// heap = new_heap; +// return (void *)prev_heap; +//} +// +//void heap_get_space(uint8_t **start, uint8_t **end, uint8_t **current) +//{ +// *start = __end__; +// *end = _estack - PRJCONF_MSP_STACK_SIZE; +// *current = heap; +//} +// +//#endif /* __CONFIG_MALLOC_USE_STDLIB */ +// +//void _exit(int return_code) +//{ +// printf("ERR: %s() not support\n", __func__); +// while (1); +//} diff --git a/platform/mcu/xr871/project/common/startup/gcc/retarget_main.c b/platform/mcu/xr871/project/common/startup/gcc/retarget_main.c new file mode 100644 index 0000000000..e09524024d --- /dev/null +++ b/platform/mcu/xr871/project/common/startup/gcc/retarget_main.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "kernel/os/os_thread.h" + +extern int __real_main(void); + +static OS_Thread_t g_main_thread; + +static void main_task(void *arg) +{ + __real_main(); + OS_ThreadDelete(&g_main_thread); +} + +void main_task_start(void) +{ + if (OS_ThreadCreate(&g_main_thread, + "", + main_task, + NULL, + PRJCONF_MAIN_THREAD_PRIO, + PRJCONF_MAIN_THREAD_STACK_SIZE) != OS_OK) { + printf("[ERR] create main task failed\n"); + } + + OS_ThreadStartScheduler(); + + while (1) { + printf("error\n"); + } +} diff --git a/platform/mcu/xr871/project/common/startup/gcc/retarget_stdout.c b/platform/mcu/xr871/project/common/startup/gcc/retarget_stdout.c new file mode 100644 index 0000000000..b9e54e9839 --- /dev/null +++ b/platform/mcu/xr871/project/common/startup/gcc/retarget_stdout.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include /* for STDOUT_FILENO and STDERR_FILENO */ + +#include "compiler.h" +#include "kernel/os/os_mutex.h" +#include "driver/chip/hal_cmsis.h" +#include "common/board/board.h" + + +/* + * retarget for standard output/error + */ + +static OS_Mutex_t g_stdout_mutex; +static uint8_t g_stdout_enable = 1; +static UART_ID g_stdout_uart_id = UART_NUM; + +/* case of critical context + * - IRQ enable + * - FIQ enable + * - Execute in ISR context + * - Scheduler is not running + */ +static __always_inline int stdout_is_critical_context(void) +{ + return (__get_PRIMASK() || + __get_FAULTMASK() || + __get_IPSR() || + !OS_ThreadIsSchedulerRunning()); +} + +static void stdout_mutex_lock(void) +{ + if (stdout_is_critical_context()) { + return; + } + + if (OS_MutexIsValid(&g_stdout_mutex)) { + OS_RecursiveMutexLock(&g_stdout_mutex, OS_WAIT_FOREVER); + } else { + OS_RecursiveMutexCreate(&g_stdout_mutex); + OS_RecursiveMutexLock(&g_stdout_mutex, OS_WAIT_FOREVER); + } +} + +static void stdout_mutex_unlock(void) +{ + if (stdout_is_critical_context()) { + return; + } + + if (OS_MutexIsValid(&g_stdout_mutex)) { + OS_RecursiveMutexUnlock(&g_stdout_mutex); + } +} + +void stdout_enable(uint8_t en) +{ + g_stdout_enable = en; +} + +int stdout_init(void) +{ + if (g_stdout_uart_id < UART_NUM) { + return 0; + } + + if (board_uart_init(BOARD_MAIN_UART_ID) == HAL_OK) { + g_stdout_uart_id = BOARD_MAIN_UART_ID; + return 0; + } + return -1; +} + +int stdout_deinit(void) +{ + if (g_stdout_uart_id >= UART_NUM) { + return 0; + } + + if (board_uart_deinit(g_stdout_uart_id) == HAL_OK) { + g_stdout_uart_id = UART_NUM; + return 0; + } + return -1; +} + +int _write(int fd, char *buf, int count) +{ + int ret; + + if (fd != STDOUT_FILENO && fd != STDERR_FILENO) { + return -1; + } + + if (!g_stdout_enable || g_stdout_uart_id >= UART_NUM) + return -1; + + stdout_mutex_lock(); + ret = board_uart_write(g_stdout_uart_id, buf, count); + stdout_mutex_unlock(); + + return ret; +} diff --git a/platform/mcu/xr871/project/common/startup/gcc/startup.S b/platform/mcu/xr871/project/common/startup/gcc/startup.S new file mode 100644 index 0000000000..07bf9d7b26 --- /dev/null +++ b/platform/mcu/xr871/project/common/startup/gcc/startup.S @@ -0,0 +1,581 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .syntax unified +#ifdef __CONFIG_CPU_CM4F + .cpu cortex-m4 + .fpu softvfp +#else + .cpu cortex-m3 +#endif + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .equ NVIC_SCR, (0xe000e000 + 0xd10) + .equ NVIC_SYSTICK_CTRL, (0xe000e000 + 0x010) + .equ NVIC_ICSR, (0xe000e000 + 0xd04) + .equ GPRCM_CPUA_BOOT_FLAG, (0x40040000 + 0x100) + .equ GPRCM_CPUA_BOOT_ADDR, (0x40040000 + 0x104) + .equ GPRCM_CPUA_BOOT_ARG, (0x40040000 + 0x108) + .equ GPRCM_CPUA_BOOT_FLAG_MASK, (3) + .equ GPRCM_CPUA_BOOT_FLAG_WAKEUP, (1) + .equ GPRCM_SYSCLK1_CTRLS, (0x40040000 + 0x024) + .equ GPRCM_SYSCLK1_EN_DIV_MASK, (0x8000000f) + .equ GPRCM_SYSCLK1_LFCLK, (0x00010000) + +/*.equ BootRAM, 0xF108F85F*/ +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + .size Reset_Handler, .-Reset_Handler +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + + cpsie i + cpsie f + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .extern exception_entry + + .section .cpu_text,"ax",%progbits +Default_Handler: +#ifndef __CONFIG_BOOTLOADER + CPSID F + TST LR, #0x04 + ITE EQ + MRSEQ R0, MSP + MRSNE R0, PSP + STMDB.W R0!, {R4-R11} + MRS R1, MSP + MRS R2, PSP + BL exception_entry +#endif +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word DMA_IRQHandler // 16 +#ifndef __CONFIG_BOOTLOADER + .word GPIOA_IRQHandler + .word SDC_IRQHandler + .word MBOX_A_IRQHandler + .word UART0_IRQHandler // 20 + .word UART1_IRQHandler + .word SPI0_IRQHandler + .word SPI1_IRQHandler + .word TWI0_IRQHandler + .word TWI1_IRQHandler + .word WDG_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word RTC_SecAlarm_IRQHandler + .word RTC_WDayAlarm_IRQHandler // 30 + .word CSI_IRQHandler + .word I2S_IRQHandler + .word PWM_ECT_IRQHandler + .word CE_IRQHandler + .word GPADC_IRQHandler + .word GPIOB_IRQHandler + .word DMIC_IRQHandler + .word IRRX_IRQHandler + .word IRTX_IRQHandler + .word MBOX_N_IRQHandler // 40 + .word 0 + .word 0 + .word N_UART_IRQHandler +#else + .word 0 //GPIOA_IRQHandler + .word 0 //SDC_IRQHandler + .word 0 //MBOX_A_IRQHandler + .word UART0_IRQHandler // 20 + .word UART1_IRQHandler + .word SPI0_IRQHandler + .word 0 //SPI1_IRQHandler + .word 0 //TWI0_IRQHandler + .word 0 //TWI1_IRQHandler + .word 0 //WDG_IRQHandler + .word 0 //TIMER0_IRQHandler + .word 0 //TIMER1_IRQHandler + .word 0 //RTC_SecAlarm_IRQHandler + .word 0 //RTC_WDayAlarm_IRQHandler // 30 + .word 0 //CSI_IRQHandler + .word 0 //I2S_IRQHandler + .word 0 //PWM_ECT_IRQHandler + .word 0 //CE_IRQHandler + .word 0 //GPADC_IRQHandler + .word 0 //GPIOB_IRQHandler + .word 0 //DMIC_IRQHandler + .word 0 //IRRX_IRQHandler + .word 0 //IRTX_IRQHandler + .word 0 //MBOX_N_IRQHandler // 40 + .word 0 + .word 0 + .word 0 +#endif + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 // 50 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 // 60 + .word 0 + .word 0 + .word 0 + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + +// .weak PendSV_Handler +// .thumb_set PendSV_Handler,Default_Handler + +// .weak SysTick_Handler +// .thumb_set SysTick_Handler,Default_Handler + + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak GPIOA_IRQHandler + .thumb_set GPIOA_IRQHandler,Default_Handler + + .weak SDC_IRQHandler + .thumb_set SDC_IRQHandler,Default_Handler + + .weak MBOX_A_IRQHandler + .thumb_set MBOX_A_IRQHandler,Default_Handler + + .weak MBOX_N_IRQHandler + .thumb_set MBOX_N_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak SPI0_IRQHandler + .thumb_set SPI0_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak TWI0_IRQHandler + .thumb_set TWI0_IRQHandler,Default_Handler + + .weak TWI1_IRQHandler + .thumb_set TWI1_IRQHandler,Default_Handler + + .weak WDG_IRQHandler + .thumb_set WDG_IRQHandler,Default_Handler + + .weak TIMER0_IRQHandler + .thumb_set TIMER0_IRQHandler,Default_Handler + + .weak TIMER1_IRQHandler + .thumb_set TIMER1_IRQHandler,Default_Handler + + .weak RTC_SecAlarm_IRQHandler + .thumb_set RTC_SecAlarm_IRQHandler,Default_Handler + + .weak RTC_WDayAlarm_IRQHandler + .thumb_set RTC_WDayAlarm_IRQHandler,Default_Handler + + .weak CSI_IRQHandler + .thumb_set CSI_IRQHandler,Default_Handler + + .weak I2S_IRQHandler + .thumb_set I2S_IRQHandler,Default_Handler + + .weak PWM_ECT_IRQHandler + .thumb_set PWM_ECT_IRQHandler,Default_Handler + + .weak CE_IRQHandler + .thumb_set CE_IRQHandler,Default_Handler + + .weak GPADC_IRQHandler + .thumb_set GPADC_IRQHandler,Default_Handler + + .weak GPIOC_IRQHandler + .thumb_set GPIOC_IRQHandler,Default_Handler + + .weak DMIC_IRQHandler + .thumb_set DMIC_IRQHandler,Default_Handler + + .weak IRRX_IRQHandler + .thumb_set IRRX_IRQHandler,Default_Handler + + .weak IRTX_IRQHandler + .thumb_set IRTX_IRQHandler,Default_Handler + + .weak N_UART_IRQHandler + .thumb_set N_UART_IRQHandler,Default_Handler + + .weak N_SPI_IRQHandler + .thumb_set N_SPI_IRQHandler,Default_Handler + + .weak N_WDT_IRQHandler + .thumb_set N_WDT_IRQHandler,Default_Handler + + .weak N_TIMER0_IRQHandler + .thumb_set N_TIMER0_IRQHandler,Default_Handler + + .weak N_TIMER1_IRQHandler + .thumb_set N_TIMER1_IRQHandler,Default_Handler + + .weak N_SDC_IRQHandler + .thumb_set N_SDC_IRQHandler,Default_Handler + + .weak N_WIFIC_IRQHandler + .thumb_set N_WIFIC_IRQHandler,Default_Handler + + .weak WKUP_TIMER0_IRQHandler + .thumb_set WKUP_TIMER0_IRQHandler,Default_Handler + + .weak WKUP_TIMER1_IRQHandler + .thumb_set WKUP_TIMER1_IRQHandler,Default_Handler + + /*------------------ void __cpu_sleep(int nouse) ------------------------*/ +#ifndef __CONFIG_BOOTLOADER + + .thumb_func + .section .cpu_text + .type __cpu_sleep, %function + .global __cpu_sleep + +__cpu_sleep: + .fnstart + .cantunwind + + PUSH {R0-R12, LR} + + /* clear pending and disable systick */ + LDR R2, =NVIC_SYSTICK_CTRL + LDR R5, [R2] + MOV R3, R5 + BIC R3, #0x03 + STR R3, [R2] + + LDR R2, =NVIC_ICSR + LDR R1, [R2] + AND R1, #0x4000000 + ASR R1, #1 + STR R1, [R2] + + /* switch to 32K/div */ + LDR R1, =GPRCM_SYSCLK1_CTRLS + LDR R0, [R1] + BIC R0, R0, #0x30000 + ORR R0, R0, #0x10000 + STR R0, [R1] + DSB + ISB + + WFI + WFI + WFI + + /* switch cpu clk to pll */ + LDR R1, =GPRCM_SYSCLK1_CTRLS + LDR R0, [R1] + BIC R0, R0, #0x30000 + ORR R0, R0, #0x20000 + STR R0, [R1] + DSB + ISB + + /* enable systick */ + LDR R2, =NVIC_SYSTICK_CTRL + STR R5, [R2] + + POP {R0-R12, PC} + + .fnend + .size __cpu_sleep, .-__cpu_sleep + + + /*------------------ void __cpu_suspend(int nouse) ------------------------*/ + .global check_wakeup_irqs + + .thumb_func + .section .cpu_text + .type __cpu_suspend, %function + .global __cpu_suspend + +__cpu_suspend: + .fnstart + .cantunwind + + PUSH {R0-R12, LR} + ISB + + LDR R0, =GPRCM_CPUA_BOOT_ARG + ISB + LDR R1, [R0] + MRS R0, MSP + ISB + STR R0, [R1] + + MRS R0, PSP + ISB + STR R0, [R1, #4] + + MRS R0, PRIMASK + STR R0, [R1, #12] + + MRS R0, FAULTMASK + STR R0, [R1, #16] + + MRS R0, BASEPRI + STR R0, [R1, #20] + + MRS R0, CONTROL + STR R0, [R1, #24] + + /* set deepsleep mode */ + LDR R0, =0x14 + LDR R1, =NVIC_SCR + ISB + STR R0, [R1] + + /* set bootflag */ + LDR R0, =0x429b0001 + LDR R1, =GPRCM_CPUA_BOOT_FLAG + ISB + STR R0, [R1] + + /* set resume address in thumb state */ + LDR R0, =resume + ORR.W R0, R0, #1 + LDR R1, =GPRCM_CPUA_BOOT_ADDR + ISB + STR R0, [R1] + + /* switch to 32K/div */ + LDR R1, =GPRCM_SYSCLK1_CTRLS + ISB + LDR R0, [R1] + BIC R0, R0, #0x30000 + ORR R0, R0, #0x10000 + STR R0, [R1] + DSB + ISB + NOP + NOP + NOP + + /* the WFE instruction will cause two kinds of CPU actions: + * 1. EVNET_REGISTER = 1, WFE will clear the EVENT_REGISTER and the + * CPU executes the next instruction. + * 2. EVENT_REGISTER = 0, WFE will make the CPU go to SLEEP state. + */ + /* first time executing WFE instruction, there are some different + * situations as follows: + * 1. if there are interrupts pending and be cleared already, + * the WFE will only clear the CPU EVENT_REGISTER. + * 2. if there are new interrupts pending after ar400_deepsleep_lock + * operation, the WFE will only clear the CPU EVENT_REGISTER. + * 3. if the SEV/NMI/DEBUG events coming before now, WFE will only + * clear the CPU EVENT_REGISTER. + * 4. if there are no SEV/NMI/DEBUG events before and no interrupts + * pending too, WFE wil make the CPU go to the SLEEP state. + */ + WFE + + /* read the NVIC SET_PENDING_REGISTER to check whether there are + * any new pending interrupts after ar400_deepsleep_lock operation + * which make the first WFE executing failed. + * 1. If ther are some new pending interrupts, jump to the RESUME_ENTRY + * and abandon the next WFE execution. + * 2. If there is no new pending interrupts, we execute WFE instruction + * twice to ensure the CPU goes to SLEEP state successfully. + */ + BL check_wakeup_irqs + CMP R0, #0 + BNE resume + ISB + NOP + NOP + NOP + + WFE + NOP + +resume: + /* switch cpu clk to pll */ + LDR R1, =GPRCM_SYSCLK1_CTRLS + ISB + LDR R0, [R1] + BIC R0, R0, #0x30000 + ORR R0, R0, #0x20000 + STR R0, [R1] + DSB + ISB + + /* restore cpu contex */ + LDR R0, =GPRCM_CPUA_BOOT_ARG + ISB + LDR R1, [R0] + + LDR R0, [R1] + MSR MSP, R0 + ISB + + LDR R0, [R1,#4] + MSR PSP, R0 + ISB + + LDR R0, [R1, #12] + MSR PRIMASK, R0 + + LDR R0, [R1, #16] + MSR FAULTMASK, R0 + + LDR R0, [R1, #20] + MSR BASEPRI, R0 + + LDR R0, [R1, #24] + MSR CONTROL, R0 + ISB + NOP + + POP {R0-R12, PC} + NOP + + .fnend + .size __cpu_suspend, .-__cpu_suspend + +#endif diff --git a/platform/mcu/xr871/project/main/main.c b/platform/mcu/xr871/project/main/main.c new file mode 100644 index 0000000000..f6228e1011 --- /dev/null +++ b/platform/mcu/xr871/project/main/main.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "common/framework/platform_init.h" + +int main(void) +{ + aos_startup(); +} diff --git a/platform/mcu/xr871/project/main/prj_config.h b/platform/mcu/xr871/project/main/prj_config.h new file mode 100644 index 0000000000..6205153544 --- /dev/null +++ b/platform/mcu/xr871/project/main/prj_config.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PRJ_CONFIG_H_ +#define _PRJ_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * project base config + */ +#define PRJCONF_MSP_STACK_SIZE (1 * 1024) /* stack size for IRQ service */ + +/* main thread */ +#define PRJCONF_MAIN_THREAD_PRIO OS_THREAD_PRIO_APP +#define PRJCONF_MAIN_THREAD_STACK_SIZE (1 * 1024) + +/* sys ctrl */ +#define PRJCONF_SYS_CTRL_EN 1 +#define PRJCONF_SYS_CTRL_PRIO OS_THREAD_PRIO_SYS_CTRL +#define PRJCONF_SYS_CTRL_STACK_SIZE (2 * 1024) +#define PRJCONF_SYS_CTRL_QUEUE_LEN (6) + +/* image */ +#define PRJCONF_IMG_FLASH (0) +#define PRJCONF_IMG_ADDR (0x00000000) +#define PRJCONF_IMG_SIZE ((1 << 20) - (4 << 10)) + +/* sysinfo */ +#define PRJCONF_SYSINFO_FLASH (0) +#define PRJCONF_SYSINFO_ADDR ((1 << 20) - (4 << 10)) +#define PRJCONF_SYSINFO_SIZE (4 << 10) + +/* MAC address source */ +#define PRJCONF_MAC_ADDR_SOURCE SYSINFO_MAC_ADDR_EFUSE + +/* watchdog hardware and service */ +#define PRJCONF_WDG_EN 0 +#define PRJCONF_WDG_TIMEOUT WDG_TIMEOUT_16SEC +#define PRJCONF_WDG_FEED_PERIOD (10 * 1000) /* in ms, MUST less than PRJCONF_WDG_TIMEOUT */ + +/* + * project hardware feature (enable/disable) + */ +#define PRJCONF_UART_EN 0 /* uart */ +#define PRJCONF_CE_EN 0 /* h/w crypto engine */ +#define PRJCONF_SPI_EN 1 /* spi */ +#define PRJCONF_MMC_EN 0 /* mmc */ +#define PRJCONF_MMC_DETECT_MODE CARD_ALWAYS_PRESENT /* mmc detect mode */ +#define PRJCONF_SOUNDCARD0_EN 1 /* sound card0, external audio codec */ +#define PRJCONF_SOUNDCARD1_EN 0 /* sound card1, internal dmic */ + +/* + * project service feature + */ +#define PRJCONF_CONSOLE_EN 0 /* console */ + +/* app pm mode + * - to override the default app pm mode, define PRJCONF_PM_MODE + */ +#define PRJCONF_PM_EN 1 /* app pm mode enable/disable */ +//#define PRJCONF_PM_MODE (PM_SUPPORT_SLEEP | PM_SUPPORT_STANDBY) + +/* network */ +#define PRJCONF_NET_EN 1 /* network and wlan */ + +/* net pm mode + * - to override the default net pm mode, define PRJCONF_NET_PM_MODE + */ +#define PRJCONF_NET_PM_EN 1 +//#define PRJCONF_NET_PM_MODE (PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF) + +#ifdef __cplusplus +} +#endif + +#endif /* _PRJ_CONFIG_H_ */ diff --git a/platform/mcu/xr871/project/project.mk b/platform/mcu/xr871/project/project.mk new file mode 100644 index 0000000000..f210760f70 --- /dev/null +++ b/platform/mcu/xr871/project/project.mk @@ -0,0 +1,24 @@ +NAME := project + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := common/board/board.c \ + common/board/board_common.c \ + common/board/xr871_evb_main/board_config.c \ + common/framework/sys_ctrl/container.c \ + common/framework/sys_ctrl/event_queue.c \ + common/framework/sys_ctrl/observer.c \ + common/framework/sys_ctrl/publisher.c \ + common/framework/sys_ctrl/sys_ctrl.c \ + common/framework/img_ctrl.c \ + common/framework/net_ctrl.c \ + common/framework/net_sys.c \ + common/framework/platform_init.c \ + common/framework/sysinfo.c \ + common/startup/gcc/exception.c \ + common/startup/gcc/retarget.c \ + common/startup/gcc/startup.S \ + common/cmd/cmd_wlan.c \ + common/cmd/cmd_util.c \ + main/main.c + +$(NAME)_ASMFLAGS += -c -x assembler-with-cpp diff --git a/platform/mcu/xr871/src/audio/audio_manager/audio_manager.c b/platform/mcu/xr871/src/audio/audio_manager/audio_manager.c new file mode 100644 index 0000000000..4d70843863 --- /dev/null +++ b/platform/mcu/xr871/src/audio/audio_manager/audio_manager.c @@ -0,0 +1,223 @@ +#include +#include +#include "kernel/os/os_mutex.h" +#include "audio/manager/audio_manager.h" + +#define MANAGER_NULL 0 + +#if !MANAGER_NULL + +#ifndef __LIKELY_ +#define likely(x) __builtin_expect(!!(x), 1) +#endif +#ifndef __UNLIKELY_ +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +#define BUG_ON(c) if (unlikely((c)!=0)) { \ + printf("Badness in %s at %s:%d/n", __func__, __FILE__, __LINE__);\ + return -1;\ + } +mgrctl_ctx g_mc; + +int aud_mgr_maxvol() +{ + return VOLUME_MAX_LEVEL; +} + +static int aud_set_mute(mgrctl_ctx* mc, int mute) +{ + BUG_ON(mute > 1 || mute < 0); + HAL_CODEC_MUTE_STATUS_Init(mute); + if (mc->playback == 0) + return 0; + + AUDIO_Device dev = mc->current_outdev; + if (HAL_CODEC_Mute(dev,mute) != 0) + return -1; + + return 0; +} + +static int aud_set_vol(mgrctl_ctx* mc, int level) +{ + BUG_ON(level > VOLUME_MAX_LEVEL || level < VOLUME_LEVEL0); + + int volume = level; + AUDIO_Device dev = mc->current_outdev; + + HAL_CODEC_INIT_VOLUME_Set(dev, volume); + if (mc->playback == 0) { + return 0; + } + + if (HAL_CODEC_VOLUME_LEVEL_Set(dev,volume) != 0) + return -1; + + return 0; +} + +static int aud_set_outdev(mgrctl_ctx* mc, int dev) +{ + BUG_ON(dev > AUDIO_DEVICE_SPEAKER || dev == 0); + + AUDIO_Device device = dev; + if (mc->current_outdev == device) + return 0; + else + mc->current_outdev = device; + + BUG_ON(mc->playback == 0); + + if (HAL_CODEC_ROUTE_Set(device) != 0) + return -1; + + return 0; +} + +static int aud_set_indev(mgrctl_ctx* mc, int dev) +{ + BUG_ON(dev != AUDIO_DEVICE_HEADPHONEMIC && dev != AUDIO_DEVICE_MAINMIC); + + AUDIO_Device device = dev; + if (mc->current_indev == device) + return 0; + else + mc->current_indev = device; + + BUG_ON(mc->record == 0); + + if (HAL_CODEC_ROUTE_Set(device) != 0) + return -1; + + return 0; +} + +static int __set_volume(mgrctl* m, int vol) +{ + mgrctl_ctx* mc; + mc = (mgrctl_ctx*)m; + if (aud_set_vol(mc, vol) != 0) + return -1; + return 0; +} + +static int __set_inpath(mgrctl* m, int dev) +{ + mgrctl_ctx* mc; + mc = (mgrctl_ctx*)m; + if (aud_set_indev(mc, dev) != 0) + return -1; + + return 0; +} + +static int __set_outpath(mgrctl* m, int dev) +{ + int ret = 0; + mgrctl_ctx* mc; + mc = (mgrctl_ctx*)m; + mc = (mgrctl_ctx*)m; + if (aud_set_outdev(mc, dev) != 0) + return -1; + return ret; +} + +static int __set_mute(mgrctl* m, int mute) +{ + mgrctl_ctx* mc; + mc = (mgrctl_ctx*)m; + if (aud_set_mute(mc, mute) != 0) + return -1; + return 0; +} + +static struct mgrctl_ops mgr_ops = +{ + .volume = __set_volume, + .in_path = __set_inpath, + .out_path = __set_outpath, + .mute = __set_mute, +}; + +static int set_mute(mgrctl* m, int mute) +{ + return m->ops->mute(m, mute); +} + +static int set_volume(mgrctl* m, int vol) +{ + return m->ops->volume(m, vol); +} + +static int set_inpath(mgrctl* m, int dev) +{ + return m->ops->in_path(m, dev); +} + +static int set_outpath(mgrctl* m, int dev) +{ + return m->ops->out_path(m, dev); +} + +/** + * event: + * 0: volume event + * 1: dev event + */ +int aud_mgr_handler(int event, int val) +{ + BUG_ON(event >= AUDIO_DEVICE_MANAGER_NONE); + + mgrctl_ctx* mc = &g_mc; + MANAGER_MUTEX_LOCK(&(mc->lock)); + + switch (event) { + case AUDIO_DEVICE_MANAGER_VOLUME : + set_volume(&(mc->base), val); + break; + case AUDIO_DEVICE_MANAGER_MUTE: + set_mute(&(mc->base), val); + break; + case AUDIO_DEVICE_MANAGER_PATH : + if (val <= AUDIO_DEVICE_SPEAKER) + set_outpath(&(mc->base), val); + else + set_inpath(&(mc->base), val); + break; + } + + MANAGER_MUTEX_UNLOCK(&(mc->lock)); + return 0; +} + +mgrctl_ctx * aud_mgr_ctx() +{ + mgrctl_ctx* mc = &g_mc; + return mc; +} + +int aud_mgr_init() +{ + mgrctl_ctx* mc = &g_mc; + memset(mc, 0, sizeof(*mc)); + + mc->current_outdev = AUDIO_DEVICE_SPEAKER; + mc->current_indev = AUDIO_DEVICE_MAINMIC; + mc->base.ops = &mgr_ops; + + if (MANAGER_MUTEX_INIT(&(mc->lock)) != 0) + return -1; + mc->is_initialize = 1; + return 0; +} + +int aud_mgr_deinit() +{ + mgrctl_ctx* mc = &g_mc; + mc->is_initialize = 0; + memset(mc, 0, sizeof(*mc)); + MANAGER_NUTEX_DESTROY(&(mc->lock)); + return 0; +} +#endif /* MANAGER_NULL */ diff --git a/platform/mcu/xr871/src/audio/audio_manager/audio_manager.mk b/platform/mcu/xr871/src/audio/audio_manager/audio_manager.mk new file mode 100644 index 0000000000..435f22b4b3 --- /dev/null +++ b/platform/mcu/xr871/src/audio/audio_manager/audio_manager.mk @@ -0,0 +1,8 @@ + + +NAME := audio_manager + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := \ + audio_manager.c + diff --git a/platform/mcu/xr871/src/audio/audio_pcm/audio_pcm.c b/platform/mcu/xr871/src/audio/audio_pcm/audio_pcm.c new file mode 100644 index 0000000000..8de0cad6f1 --- /dev/null +++ b/platform/mcu/xr871/src/audio/audio_pcm/audio_pcm.c @@ -0,0 +1,468 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include "driver/chip/hal_codec.h" +#include "driver/chip/hal_i2s.h" +#include "driver/chip/hal_dmic.h" +#include "driver/chip/hal_i2c.h" +#include "audio/pcm/audio_pcm.h" +#include "audio/manager/audio_manager.h" +#include "./../../driver/chip/hal_os.h" + +#define Oops(x) do {printf("[PCM]"); printf x; } while (0) +#define AUDIO_OUT_DEVICE_DEFAULT AUDIO_DEVICE_HEADPHONE +#define AUDIO_IN_DEVICE_DEFAULT AUDIO_DEVICE_MAINMIC + +#ifndef PCM_ASSERT +#define PCM_WARN_MESSAGE(x) do {printf(x);} while(0) + +#define PCM_ASSERT(message, assertion) do { if(!(assertion)) { \ + PCM_WARN_MESSAGE(message); \ + return -1; \ + } \ + } while(0) +#endif + +struct play_priv { + struct pcm_config *config; + unsigned char *cache; + unsigned int length; + unsigned int trigger; +}; + +struct cap_priv { + struct pcm_config *config; +}; + +struct audio_priv { + struct play_priv play_priv; + struct cap_priv cap_priv; + HAL_Mutex play_lock; + HAL_Mutex write_lock; + HAL_Mutex cap_lock; +}; + +static struct audio_priv snd_pcm_priv; + +#define pcm_lock(n) HAL_MutexLock(&((snd_pcm_priv).n##_lock), OS_WAIT_FOREVER) +#define pcm_unlock(n) HAL_MutexUnlock(&((snd_pcm_priv).n##_lock)) +#define pcm_lock_init(n) HAL_MutexInit(&((snd_pcm_priv).n##_lock)) +#define pcm_lock_deinit(n) HAL_MutexDeinit(&((snd_pcm_priv).n##_lock)) + +#define PA_STABILITY_TIME 150 //ms + +void* pcm_zalloc(unsigned int size) +{ + void *p; + if ((p = malloc(size)) != NULL){ + memset(p,0,size); + return p; + } + return NULL; +} + +void pcm_free(void *p) +{ + if (p) { + free(p); + p = NULL; + } + return; +} + +unsigned int pcm_get_buffer_size(struct pcm_config *config) +{ + return config->period_count * config->period_size; +} + +unsigned int pcm_format_to_bits(enum pcm_format format) +{ + switch (format) { + case PCM_FORMAT_S32_LE: + case PCM_FORMAT_S24_LE: + return 32; + case PCM_FORMAT_S16_LE: + return 16; + default: + Oops(("invalid pcm format...\n")); + return 0; + }; +} + +unsigned int pcm_frames_to_bytes(struct pcm_config *config, unsigned int frames) +{ + return frames * config->channels * + (pcm_format_to_bits(config->format) >> 3); +} + +int snd_pcm_write(struct pcm_config *config, unsigned int card, void *data, unsigned int count) +{ + PCM_ASSERT("Invalid card.\n", (card == SOUND_CARD_EXTERNAL_AUDIOCODEC)); + int len = 0, ret = 0, buf_size = 0, size = 0; + uint8_t *data_ptr = NULL; + + if (pcm_lock(write) != 0) { + Oops(("Obtain write lock err.\n")); + return -1; + } + + buf_size = pcm_frames_to_bytes(config,pcm_get_buffer_size(config))/2;; + data_ptr = data; + size = count; + + struct play_priv *ppriv = &(snd_pcm_priv.play_priv); + if (ppriv->length != 0) { + len = buf_size - ppriv->length; + if (ppriv->cache == NULL) { + pcm_unlock(write); + return -1; + } + if (len > size) { + memcpy(ppriv->cache + ppriv->length, data_ptr, size); + ppriv->length += size; + pcm_unlock(write); + return count; + } else + memcpy(ppriv->cache + ppriv->length, data_ptr, len); + + HAL_I2S_Write_DMA((void *)ppriv->cache, buf_size); + ppriv->length = 0; + } + + data_ptr = data_ptr +len; + size -= len; + + ret = HAL_I2S_Write_DMA(data_ptr, size); + + if (ret > 0 && ret != size) { + data_ptr += ret; + ppriv->length = size - ret; + memcpy(ppriv->cache, data_ptr, ppriv->length); + }else if (ret == size) { + ppriv->length = 0; + } else { + ppriv->length = size; + memcpy(ppriv->cache, data_ptr, ppriv->length); + } + +#if 0 + + #include "fs/fatfs/ff.h" + FRESULT result; + FATFS fs; + FIL file; + memset(&fs, 0, sizeof(fs)); + unsigned int writenum = 0; + fs.drv = 1; + if ((result = f_mount(&fs, "0:/", 1)) != FR_OK) // = "0:" = "0:/" = "" + printf("failed to mount\n"); + else if ((result = f_open(&file, "0:/5.pcm", FA_OPEN_ALWAYS|FA_READ|FA_WRITE)) != FR_OK) + printf("[music file]failed to open,%s\n","0:/5.pcm"); + if ((result = f_write(&file, data, count, &writenum)) != FR_OK) + printf("write failed(%d).\n",result); + + f_close(&file); + +#endif + pcm_unlock(write); + return count; +} + +int snd_pcm_flush(struct pcm_config *config, unsigned int card) +{ + PCM_ASSERT("Invalid card.\n", (card == SOUND_CARD_EXTERNAL_AUDIOCODEC)); + + struct play_priv *ppriv = &(snd_pcm_priv.play_priv); + PCM_ASSERT("Cache is NULL.\n", (ppriv->cache != NULL)); + int buf_size = pcm_frames_to_bytes(config,pcm_get_buffer_size(config)); + + pcm_lock(write); + + buf_size = buf_size / 2; + if (ppriv->length != 0){ + memset(ppriv->cache + ppriv->length, 0, buf_size - ppriv->length); + HAL_I2S_Write_DMA((void *)ppriv->cache, buf_size); + ppriv->length = 0; + } + + int delay = 0; + memset(ppriv->cache, 0, buf_size); + for(delay = 0; delay < 2; delay ++) { + HAL_I2S_Write_DMA((void *)ppriv->cache, buf_size); + } + pcm_unlock(write); + + return 0; +} + +int snd_pcm_read(struct pcm_config *config, unsigned int card, void *data, unsigned int count) +{ + PCM_ASSERT("Invalid card.\n", (card < SOUND_CARD_NULL)); + void *buf = data; + int size = 0; + int buf_size = pcm_frames_to_bytes(config,pcm_get_buffer_size(config))/2;; + if (buf_size > count) + return -1; + size = (count / buf_size) * buf_size; + if (card == SOUND_CARD_EXTERNAL_AUDIOCODEC) + return HAL_I2S_Read_DMA(buf, size); + else if (card == SOUND_CARD_INTERNAL_DMIC) + return HAL_DMIC_Read_DMA(buf, size); + return -1; +} + +int snd_pcm_open(struct pcm_config *config, unsigned int card, unsigned int flags) +{ + PCM_ASSERT("Wrong card and flags param.\n", ((card == 1) && (PCM_OUT == flags)) != 1); + mgrctl_ctx *mgr_ctx = aud_mgr_ctx(); + if (card == AUDIO_CARD0) { + DATA_Param codec_data; + memset(&codec_data, 0, sizeof(codec_data)); + + MANAGER_MUTEX_LOCK(&(mgr_ctx->lock)); + if (mgr_ctx->is_initialize) + codec_data.audioDev = (PCM_OUT == flags) ? mgr_ctx->current_outdev : mgr_ctx->current_indev; + else + codec_data.audioDev = (PCM_OUT == flags) ? AUDIO_OUT_DEVICE_DEFAULT : AUDIO_IN_DEVICE_DEFAULT; + MANAGER_MUTEX_UNLOCK(&(mgr_ctx->lock)); + + codec_data.sampleRate = config->rate; + + if (HAL_CODEC_Open(&codec_data) != HAL_OK) { + Oops(("Codec open failed..\n")); + return -1; + } + + I2S_DataParam i2s_data; + memset(&i2s_data, 0, sizeof(i2s_data)); + i2s_data.direction = (PCM_OUT == flags) ? PLAYBACK : RECORD; + i2s_data.bufSize = pcm_frames_to_bytes(config,pcm_get_buffer_size(config)); + i2s_data.channels = config->channels; + + if (i2s_data.direction == PLAYBACK) { + if (pcm_lock(play) != 0) { + Oops(("obtain play lock err...\n")); + return -1; + } + struct play_priv *ppriv = &(snd_pcm_priv.play_priv); + ppriv->cache = pcm_zalloc(i2s_data.bufSize/2); + if (ppriv->cache == NULL) { + pcm_unlock(play); + Oops(("obtain play cache failed...\n")); + return -1; + } + ppriv->length = 0; + ppriv->config = config; + + } else { + if (pcm_lock(cap) != 0) { + Oops(("obtain cap lock err...\n")); + return -1; + } + + struct cap_priv *cpriv = &(snd_pcm_priv.cap_priv); + cpriv->config = config; + } + i2s_data.resolution = (config->format == PCM_FORMAT_S16_LE) ? I2S_SR16BIT : I2S_SR32BIT; + + switch (config->rate) { + case 48000: + i2s_data.sampleRate = I2S_SR48K; + break; + case 44100: + i2s_data.sampleRate = I2S_SR44K; + break; + case 8000: + i2s_data.sampleRate = I2S_SR8K; + break; + case 12000: + i2s_data.sampleRate = I2S_SR12K; + break; + case 16000: + i2s_data.sampleRate = I2S_SR16K; + break; + case 24000: + i2s_data.sampleRate = I2S_SR24K; + break; + case 32000: + i2s_data.sampleRate = I2S_SR32K; + break; + case 11025: + i2s_data.sampleRate = I2S_SR11K; + break; + case 22050: + i2s_data.sampleRate = I2S_SR22K; + break; + + default: + break; + } + + if (HAL_I2S_Open(&i2s_data) != HAL_OK) { + Oops(("I2S open failed..\n")); + return -1; + } + OS_MSleep(5); + if (i2s_data.direction == PLAYBACK) { + if (HAL_CODEC_MUTE_STATUS_Get() == 0) { + if (codec_data.audioDev == AUDIO_DEVICE_SPEAKER) + OS_MSleep(PA_STABILITY_TIME); + HAL_CODEC_Trigger(codec_data.audioDev, 1); + } + } + MANAGER_MUTEX_LOCK(&(mgr_ctx->lock)); + if (i2s_data.direction == PLAYBACK) + mgr_ctx->playback = 1; + else + mgr_ctx->record = 1; + MANAGER_MUTEX_UNLOCK(&(mgr_ctx->lock)); + + } else { + + DMIC_DataParam dmic_data; + memset(&dmic_data, 0, sizeof(dmic_data)); + if (pcm_lock(cap) != 0) { + Oops(("obtain cap lock err...\n")); + return -1; + } + switch (config->rate) { + case 48000: + dmic_data.sampleRate = DMIC_SR48KHZ; + break; + case 44100: + dmic_data.sampleRate = DMIC_SR44KHZ; + break; + case 24000: + dmic_data.sampleRate = DMIC_SR24KHZ; + break; + case 22050: + dmic_data.sampleRate = DMIC_SR22KHZ; + break; + case 12000: + dmic_data.sampleRate = DMIC_SR12KHZ; + break; + case 11025: + dmic_data.sampleRate = DMIC_SR11KHZ; + break; + case 32000: + dmic_data.sampleRate = DMIC_SR32KHZ; + break; + case 16000: + dmic_data.sampleRate = DMIC_SR16KHZ; + break; + case 8000: + dmic_data.sampleRate = DMIC_SR8KHZ; + break; + + default: + break; + } + dmic_data.bufSize = pcm_frames_to_bytes(config,pcm_get_buffer_size(config)); + dmic_data.channels = config->channels; + dmic_data.resolution = (config->format == PCM_FORMAT_S16_LE) ? DMIC_RES16BIT : DMIC_RES24BIT; + + if (HAL_DMIC_Open(&dmic_data) != HAL_OK) { + Oops(("Dmic open failed..\n")); + pcm_unlock(cap); + return -1; + } + + MANAGER_MUTEX_LOCK(&(mgr_ctx->lock)); + mgr_ctx->record = 1; + MANAGER_MUTEX_UNLOCK(&(mgr_ctx->lock)); + } + return 0; +} + +int snd_pcm_close(unsigned int card, unsigned int flags) +{ + PCM_ASSERT("Wrong card and flags param..\n", ((card == 1) && (PCM_OUT == flags)) != 1); + int dir = (PCM_OUT == flags) ? PLAYBACK : RECORD; + mgrctl_ctx *mgr_ctx = aud_mgr_ctx(); + if (card == AUDIO_CARD0) { + AUDIO_Device dev; + + MANAGER_MUTEX_LOCK(&(mgr_ctx->lock)); + if (mgr_ctx->is_initialize) + dev = mgr_ctx->current_outdev; + else + dev = AUDIO_OUT_DEVICE_DEFAULT; + MANAGER_MUTEX_UNLOCK(&(mgr_ctx->lock)); + + HAL_CODEC_Trigger(dev, 0); + HAL_CODEC_Close(dir); + HAL_I2S_Close(dir); + + if (PCM_OUT == flags) { + pcm_free(snd_pcm_priv.play_priv.cache); + memset(&(snd_pcm_priv.play_priv), 0, sizeof(struct play_priv)); + pcm_unlock(play); + + } else { + memset(&(snd_pcm_priv.cap_priv), 0, sizeof(struct cap_priv)); + pcm_unlock(cap); + } + + MANAGER_MUTEX_LOCK(&(mgr_ctx->lock)); + if (PCM_OUT == flags) + mgr_ctx->playback = 0; + else + mgr_ctx->record = 0; + MANAGER_MUTEX_UNLOCK(&(mgr_ctx->lock)); + } else { + MANAGER_MUTEX_LOCK(&(mgr_ctx->lock)); + mgr_ctx->record = 0; + MANAGER_MUTEX_UNLOCK(&(mgr_ctx->lock)); + HAL_DMIC_Close(); + memset(&(snd_pcm_priv.cap_priv), 0, sizeof(struct cap_priv)); + pcm_unlock(cap); + } + return 0; +} + +int snd_pcm_init() +{ + struct audio_priv* audio_priv = &snd_pcm_priv; + + memset(audio_priv, 0, sizeof(*audio_priv)); + pcm_lock_init(play); + pcm_lock_init(write); + pcm_lock_init(cap); + return 0; +} + +int snd_pcm_deinit() +{ + pcm_lock_deinit(play); + pcm_lock_deinit(write); + pcm_lock_deinit(cap); + return 0; +} diff --git a/platform/mcu/xr871/src/audio/audio_pcm/audio_pcm.mk b/platform/mcu/xr871/src/audio/audio_pcm/audio_pcm.mk new file mode 100644 index 0000000000..f289a9b845 --- /dev/null +++ b/platform/mcu/xr871/src/audio/audio_pcm/audio_pcm.mk @@ -0,0 +1,8 @@ + + +NAME := audio_pcm + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := \ + audio_pcm.c + diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/AudioDec_Decode.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/AudioDec_Decode.h new file mode 100644 index 0000000000..7ca0d83554 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/AudioDec_Decode.h @@ -0,0 +1,123 @@ +#ifndef AUDIODEC_DECODE_H +#define AUDIODEC_DECODE_H +#include +#include "unistd.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#define cdx_mutex_lock(x) pthread_mutex_lock(x) +#define cdx_mutex_unlock(x) pthread_mutex_unlock(x) + +typedef void AudioDecoderLib; + +typedef struct CedarAudioCodec +{ + const char *name; + struct __AudioDEC_AC320 *(*init)(void); + int (*exit)(struct __AudioDEC_AC320 *p); + int flag; +} CedarAudioCodec; + + +typedef struct InitCodecInfo +{ + const char *handle; + const char *name; + const char *init; + const char *exit; + int flag; + struct __AudioDEC_AC320 *(*decInit)(void); + int (*decExit)(struct __AudioDEC_AC320 *p); +} InitCodecInfo; + +typedef struct RaFormatInofStruct +{ + unsigned int ulSampleRate; + unsigned int ulActualRate; + unsigned short usBitsPerSample; + unsigned short usNumChannels; + unsigned short usAudioQuality; + unsigned short usFlavorIndex; + unsigned int ulBitsPerFrame; + unsigned int ulGranularity; + unsigned int ulOpaqueDataSize; + unsigned char* pOpaqueData; +} RaFormatInfoT; +/*********************************************************************************/ + +typedef enum INPUTBSFILLMODE +{ + BSFILL_MODE_UNKONE = 0, + BSFILL_MODE_NORMAL, + BSFILL_MODE_HDRWRAP, + BSFILL_MODE_BSWRAP, +}INPUTBSFILLMODE; + +typedef struct CedarInputBsManage +{ + INPUTBSFILLMODE mode; + unsigned char *pHoloStartAddr0; + int nHoloLen0; + unsigned char *pHoloStartAddr1; + int nHoloLen1; +}CedarInputBsManage; + +typedef struct InputStreamBuf +{ + CedarInputBsManage InputBsManage; + int CedarAbsPackHdrLen; + unsigned char CedarAbsPackHdr[16]; +}InputStreamBufT; + +typedef struct AudioDecoderContextStructLib +{ + pthread_mutex_t mutex_audiodec_thread; + int nAudioInfoFlags; + InputStreamBufT Streambuffer; + Ac320FileRead DecFileInfo; + com_internal pInternal; + + CedarAudioCodec *pCedarCodec; + void *libhandle; + AudioDEC_AC320 *pCedarAudioDec; +#ifdef CEDARX_SUPPORT_SOUNDTOUCH + SoundTouchAPI *pSTouchAPI; + STPrivData* STpriv_data; +#endif + const char *handlename; +}AudioDecoderContextLib; + + +int ParseRequestAudioBitstreamBuffer(AudioDecoderLib* pDecoder, + int nRequireSize, + unsigned char** ppBuf, + int* pBufSize, + unsigned char** ppRingBuf, + int* pRingBufSize, + int* nOffset); +int ParseUpdateAudioBitstreamData(AudioDecoderLib* pDecoder, + int nFilledLen, + int64_t nTimeStamp, + int nOffset); +int ParseAudioStreamDataSize(AudioDecoderLib* pDecoder); +void BitstreamQueryQuality(AudioDecoderLib* pDecoder, int* pValidPercent, int* vbv); +void ParseBitstreamSeekSync(AudioDecoderLib* pDecoder, int64_t nSeekTime, int nGetAudioInfoFlag); + +int InitializeAudioDecodeLib(AudioDecoderLib* pDecoder, + AudioStreamInfo* pAudioStreamInfo, + BsInFor *pBsInFor); +int DecodeAudioFrame(AudioDecoderLib* pDecoder, + char* ppBuf, + int* pBufSize); +int DestroyAudioDecodeLib(AudioDecoderLib* pDecoder); + +void SetAudiolibRawParam(AudioDecoderLib* pDecoder, int commond); + +AudioDecoderLib* CreateAudioDecodeLib(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif//AUDIODEC_DECODE_H diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/CDX_Common.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/CDX_Common.h new file mode 100644 index 0000000000..c7921e9490 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/CDX_Common.h @@ -0,0 +1,45 @@ +/******************************************************************************* +-- -- +-- CedarX Multimedia Framework -- +-- -- +-- the Multimedia Framework for Linux/Android System -- +-- -- +-- This software is confidential and proprietary and may be used -- +-- only as expressly authorized by a licensing agreement from -- +-- Softwinner Products. -- +-- -- +-- (C) COPYRIGHT 2011 SOFTWINNER PRODUCTS -- +-- ALL RIGHTS RESERVED -- +-- -- +-- The entire notice above must be reproduced -- +-- on all copies and should not be removed. -- +-- -- +*******************************************************************************/ +#ifndef CDX_Common_H_ +#define CDX_Common_H_ + +typedef enum CEDARX_AUDIO_CHANNEL_TYPE +{ + CEDARX_AUDIO_CHANNEL_STEREO = 0, + CEDARX_AUDIO_CHANNEL_LEFT , + CEDARX_AUDIO_CHANNEL_RIGHT, +} CEDARX_AUDIO_CHANNEL_TYPE; + +typedef enum CDX_COMP_PRIV_FLAGS +{ + CDX_COMP_PRIV_FLAGS_REINIT = 1, + CDX_COMP_PRIV_FLAGS_STREAMEOF = 2, +}CDX_COMP_PRIV_FLAGS; + +enum CEDARXAUDIOFLAGSENUM +{ + ADEC_DISABLE_AAC_PACKING = (1<<0), +}; + + +typedef enum CDX_DECODE_MODE { + CDX_DECODER_MODE_NORMAL = 0, + CDX_DECODER_MODE_RAWMUSIC, +}CDX_DECODE_MODE; + +#endif \ No newline at end of file diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/CDX_Fileformat.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/CDX_Fileformat.h new file mode 100644 index 0000000000..6a1d5ef39c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/CDX_Fileformat.h @@ -0,0 +1,107 @@ +#ifndef CDX_FILEFORMAT_H_ +#define CDX_FILEFORMAT_H_ + +typedef enum CDX_MEDIA_FILE_FORMAT { + CDX_MEDIA_FILE_FMT_UNSUPPORT = -1, + CDX_MEDIA_FILE_FMT_UNKOWN = 0, + CDX_MEDIA_FILE_FMT_AVI, + CDX_MEDIA_FILE_FMT_RM, + CDX_MEDIA_FILE_FMT_RMVB, + CDX_MEDIA_FILE_FMT_MP4, + CDX_MEDIA_FILE_FMT_M4V, + CDX_MEDIA_FILE_FMT_3GP, + CDX_MEDIA_FILE_FMT_MOV, + CDX_MEDIA_FILE_FMT_FLV, + CDX_MEDIA_FILE_FMT_MPG, + CDX_MEDIA_FILE_FMT_VOB, + CDX_MEDIA_FILE_FMT_MOD, + CDX_MEDIA_FILE_FMT_PMP, + CDX_MEDIA_FILE_FMT_WMV, + CDX_MEDIA_FILE_FMT_ASF, + CDX_MEDIA_FILE_FMT_MKV, + CDX_MEDIA_FILE_FMT_PSR, + CDX_MEDIA_FILE_FMT_RAM, + CDX_MEDIA_FILE_FMT_SCM, + CDX_MEDIA_FILE_FMT_OGM, + CDX_MEDIA_FILE_FMT_M4P, + CDX_MEDIA_FILE_FMT_M4B, + CDX_MEDIA_FILE_FMT_TP, + CDX_MEDIA_FILE_FMT_TPR, + CDX_MEDIA_FILE_FMT_TS, + CDX_MEDIA_FILE_FMT_PVA, + CDX_MEDIA_FILE_FMT_PSS, + CDX_MEDIA_FILE_FMT_MPE, + CDX_MEDIA_FILE_FMT_WV, + CDX_MEDIA_FILE_FMT_M2TS, + CDX_MEDIA_FILE_FMT_EVO, + CDX_MEDIA_FILE_FMT_RPM, + CDX_MEDIA_FILE_FMT_3GPP, + CDX_MEDIA_FILE_FMT_3G2, + CDX_MEDIA_FILE_FMT_3GP2, + CDX_MEDIA_FILE_FMT_QT, + CDX_MEDIA_FILE_FMT_WMP, + CDX_MEDIA_FILE_FMT_WM, + CDX_MEDIA_FILE_FMT_AMV, + CDX_MEDIA_FILE_FMT_DSM, + CDX_MEDIA_FILE_FMT_M1V, + CDX_MEDIA_FILE_FMT_M2V, + CDX_MEDIA_FILE_FMT_SMK, + CDX_MEDIA_FILE_FMT_BIK, + CDX_MEDIA_FILE_FMT_RAT, + CDX_MEDIA_FILE_FMT_VG2, + CDX_MEDIA_FILE_FMT_IVF, + CDX_MEDIA_FILE_FMT_VP6, + CDX_MEDIA_FILE_FMT_VP7, + CDX_MEDIA_FILE_FMT_D2V, + CDX_MEDIA_FILE_FMT_M2P, + CDX_MEDIA_FILE_FMT_VID, + CDX_MEDIA_FILE_FMT_PMP2, + CDX_MEDIA_FILE_FMT_MTS, + CDX_MEDIA_FILE_FMT_MP3, + CDX_MEDIA_FILE_FMT_WAV, + CDX_MEDIA_FILE_FMT_WMA, + CDX_MEDIA_FILE_FMT_APE, + CDX_MEDIA_FILE_FMT_FLAC, + CDX_MEDIA_FILE_FMT_OGG, + CDX_MEDIA_FILE_FMT_RA, + CDX_MEDIA_FILE_FMT_MP1, + CDX_MEDIA_FILE_FMT_MP2, + CDX_MEDIA_FILE_FMT_AAC, + CDX_MEDIA_FILE_FMT_AC3, + CDX_MEDIA_FILE_FMT_DTS, + CDX_MEDIA_FILE_FMT_AIF, + CDX_MEDIA_FILE_FMT_AIFF, + CDX_MEDIA_FILE_FMT_AIFC, + CDX_MEDIA_FILE_FMT_AMR, + CDX_MEDIA_FILE_FMT_MAC, + CDX_MEDIA_FILE_FMT_TTA, + CDX_MEDIA_FILE_FMT_M4A, + CDX_MEDIA_FILE_FMT_CDA, + CDX_MEDIA_FILE_FMT_AU, + CDX_MEDIA_FILE_FMT_ACC, + CDX_MEDIA_FILE_FMT_MIDI, + CDX_MEDIA_FILE_FMT_MID, + CDX_MEDIA_FILE_FMT_RMI, + CDX_MEDIA_FILE_FMT_MP5, + CDX_MEDIA_FILE_FMT_MPA, + CDX_MEDIA_FILE_FMT_MPGA, + CDX_MEDIA_FILE_FMT_ACT, + CDX_MEDIA_FILE_FMT_ATRC, + CDX_MEDIA_FILE_FMT_WEBM, + CDX_MEDIA_FILE_FMT_M3U, + CDX_MEDIA_FILE_FMT_AWTS, + CDX_MEDIA_FILE_FMT_WVM,//87 + /*for test raw data */ + CDX_MEDIA_FILE_FMT_RAW, + + CDX_MEDIA_FILE_FMT_AUDIO = (1<<16), + CDX_MEDIA_FILE_FMT_NETWORK = (2<<16), + CDX_MEDIA_FILE_FMT_NETWORK_RTSP = (4<<16), + CDX_MEDIA_FILE_FMT_IDXSUB = (8<<16), + CDX_MEDIA_FILE_FMT_NETWORK_SFT = (16<<16), + CDX_MEDIA_FILE_FMT_WIFI_DISPLAY = (32<<16), + CDX_MEDIA_FILE_FMT_STREAMINGSRC = (64<<16), + CDX_MEDIA_FILE_FMT_NETWORK_OTHERS = (128<<16), +} CDX_MEDIA_FILE_FORMAT; + +#endif /* CDX_FILEFORMAT_H_ */ diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/GetAudio_format.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/GetAudio_format.h new file mode 100644 index 0000000000..448c89ffc1 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/GetAudio_format.h @@ -0,0 +1,184 @@ +/****************************************************************************** +* file:GetAudio_format.h 2008-12-24 10:47:12 +* +*author lszhang +* +* +* +*******************************************************************************/ +#ifndef _GETAUFIO_FORMAT_H_ +#define _GETAUFIO_FORMAT_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +typedef enum __AW_AUDIO_FORMAT +{ + SW_AUDIO_FORMAT_UNKNOWN = 0, /* �޷�ʶ�� */ + + SW_AUDIO_FORMAT_AAC, + SW_AUDIO_FORMAT_AC3, + SW_AUDIO_FORMAT_APE, + SW_AUDIO_FORMAT_DTS, + SW_AUDIO_FORMAT_FLAC, + SW_AUDIO_FORMAT_MP3, + SW_AUDIO_FORMAT_OGG, + SW_AUDIO_FORMAT_RA, + SW_AUDIO_FORMAT_WAV, + SW_AUDIO_FORMAT_WMA, + SW_AUDIO_FORMAT_AMR, + SW_AUDIO_FORMAT_ATRC, + SW_AUDIO_FORMAT_MID, + + SW_AUDIO_FORMAT_ = -1 + +} __sw_audio_format_e; + +typedef enum +{ + IMG_FORMAT_BMP =0, + IMG_FORMAT_JPG, + IMG_FORMAT_GIF, + IMG_FORMAT_PNG, + IMG_FORMAT_UNSUPPORT = -1 +}__w_img_format_t; + +typedef enum __A_AUDIO_FONTTYPE +{ + A_AUDIO_FONTTYPE_ISOIEC8859_1 = 0, //ISO/IEC 8859-1 + A_AUDIO_FONTTYPE_UTF_16LE,// + A_AUDIO_FONTTYPE_UTF_16BE, + A_AUDIO_FONTTYPE_UTF_8,// + A_AUDIO_FONTTYPE_ISOIEC8859_2,// + A_AUDIO_FONTTYPE_ISOIEC8859_3,// + A_AUDIO_FONTTYPE_ISOIEC8859_4,// + A_AUDIO_FONTTYPE_ISOIEC8859_5,// + A_AUDIO_FONTTYPE_ISOIEC8859_6, + A_AUDIO_FONTTYPE_ISOIEC8859_7, + A_AUDIO_FONTTYPE_ISOIEC8859_8, + A_AUDIO_FONTTYPE_ISOIEC8859_9, + A_AUDIO_FONTTYPE_ISOIEC8859_10, + A_AUDIO_FONTTYPE_ISOIEC8859_11, + A_AUDIO_FONTTYPE_ISOIEC8859_12, + A_AUDIO_FONTTYPE_ISOIEC8859_13, + A_AUDIO_FONTTYPE_ISOIEC8859_14, + A_AUDIO_FONTTYPE_ISOIEC8859_15, + A_AUDIO_FONTTYPE_ISOIEC8859_16, + A_AUDIO_FONTTYPE_WINDOWS_1250, + A_AUDIO_FONTTYPE_WINDOWS_1251,// + A_AUDIO_FONTTYPE_WINDOWS_1252, + A_AUDIO_FONTTYPE_WINDOWS_1253, + A_AUDIO_FONTTYPE_WINDOWS_1254, + A_AUDIO_FONTTYPE_WINDOWS_1255, + A_AUDIO_FONTTYPE_WINDOWS_1256, + A_AUDIO_FONTTYPE_WINDOWS_1257, + A_AUDIO_FONTTYPE_WINDOWS_1258, + A_AUDIO_FONTTYPE_KOI8_R, + A_AUDIO_FONTTYPE_KOI8_U, + A_AUDIO_FONTTYPE_GB2312, + A_AUDIO_FONTTYPE_GBK, + A_AUDIO_FONTTYPE_BIG5, + + + A_AUDIO_FONTTYPE_ = -1 +}__a_audio_fonttype_e; + +typedef struct __ID3_IMAGE_INFO +{ + int length; //��ݳ��� + int FileLocation; //�ļ�ƫ��λ�� + __w_img_format_t img_format; //ͼƬ��ʽ + int pic_type; //picture type; + int img_high; //Ԥ����ͼƬ�߶� + int img_width; //Ԥ����ͼƬ��� + int otherdata; //Ԥ�� + +}__id3_image_info_t; + + +typedef struct __AUDIO_FILE_INFO +{ + unsigned int ulSampleRate; // ������ sample rate + unsigned int ulBitRate; // ������ bit rate��λ��BPS + unsigned int ulChannels; // ����� channel + unsigned int ulDuration; // ����ʱ�� duration ��λ��ms + unsigned int ulBitsSample; // �����λ�� sample 8/16/24/32 + unsigned int ulCharEncode; // 0:GB2312.1:UNICODE + + int ulAudio_name_sz; // ��Ƶ��ʽ˵�� + signed char *ulAudio_name; // mp3 /RealAudio Cook.sipo. / aac-lc.... + __a_audio_fonttype_e ulAudio_nameCharEncode; // + + int ulGenre_sz; // ���� + signed char *ulGenre; // pop soft... + __a_audio_fonttype_e ulGenreCharEncode; + + int ultitle_sz; // ������ + signed char *ultitle; + __a_audio_fonttype_e ultitleCharEncode; + + int ulauthor_sz; // �ݳ��� + signed char *ulauthor; + __a_audio_fonttype_e ulauthorCharEncode; + + __sw_audio_format_e ulFormat; + int ulAlbum_sz; // ר�� + signed char *ulAlbum; + __a_audio_fonttype_e ulAlbumCharEncode; + + int ulYear_sz; // ��Ʒ��� + signed char *ulYear; + __a_audio_fonttype_e ulYearCharEncode; + + int ulAPic_sz; // attached picture + __id3_image_info_t *ulAPic; + __a_audio_fonttype_e ulAPicCharEncode; + + int ulUslt_sz; // ��ͬ���ĸ��/�ı� ���� + signed char* ulUslt; // int ulFileLocation�� + __a_audio_fonttype_e ulUsltCharEncode; + + int ulSylt_sz; // ͬ���ĸ��/�ı� + signed char* ulSylt; // int ulFileLocation�� + __a_audio_fonttype_e ulSyltCharEncode; + + int ulbufflag; //0:���ļ����з����������buf�������ݽ��з��� + int ulbuf_length; //buf length; + char* ulbuf; //����buf��������. + int data[3]; + int64_t offset; //audio data ļеƫid3Ҳaudio dataΪ˽һļijaudio + int64_t length; //audio data lenthЧaudioݵijȡԸֵ0˼Ч + int64_t readlen; //ǰȡٸЧaudio ݣ൱ļƫλüȥaudio dataļеƫ + + signed char *ulBSINFO; // temporary buffer of read data + int InforBufLeftLength; + signed char *InforBuf; // ���ڴ洢 ulAudio_name ultitle ulauthor����Ϣ��buffer + +}audio_file_info_t; + + +int GetAudioFormat(const char *pFilename,int *A_Audio_Format);//return 1 :succed 0 :fail +int GetAudioInfo(const char *pFilename, audio_file_info_t *AIF); //return 1 :succed 0 :fail +/* +function :GetAudioFormatData +˵ļǰֽڿжļ͡ +˵ptr ļ׵ַ + buflenݳȡ + A_Audio_Formatļļʽ +ֵ1 :succed 0 :fail +*/ +//simple format from first 16bytes +int GetAudioFormatData(unsigned char *ptr,int buflen,int *A_Audio_Format);//return 1 :succed 0 :fail + +int GetAudioDataInfo(const char *pFilename, audio_file_info_t *AIF,signed char* buf,int datalen); //return 1 :succed 0 :fail +int GetAudioFileInfo(FILE *Bitstream, audio_file_info_t *AIF); //return 1 :succed 0 :fail +int GetAudioFileInfoOffset(FILE *Bitstream,int64_t offset,int64_t length,audio_file_info_t *AIF); //return 1 :succed 0 :fail +#ifdef __cplusplus +} +#endif + +#endif //_GETAUFIO_FORMAT_H_ + diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/PostProcessCom.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/PostProcessCom.h new file mode 100644 index 0000000000..662ad24e9b --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/PostProcessCom.h @@ -0,0 +1,39 @@ + +#ifndef _POST_PROCESS_COM_H_ +#define _POST_PROCESS_COM_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define MaxSpecGroup (10) + +//Ϊ1024ٲţҪĵַͬ +typedef struct __PostProcessSt +{ + short fadeinoutflag; //0:normal 1:fade in 2:fade out + short VPS; //-40 - 100, ٶΪ: (1+vps%),ԱٷΧԭʼٶȵ0.6~2 + short spectrumflag; //0 : disable 1:enable + short spectrumOutNum;//Ƶ + short SpectrumOutval[MaxSpecGroup][32];//ΧΪ 0-20melis10θ߶ʾ32ƵΡ1024һƵף32ƵΣ + short UserEQ[11]; //0-10 + int channal; //1:mono 2:stereo + int samplerate; + + short *InputPcmBuf; + int InputPcmLen;//bufferlenth + + short *OutputPcmBuf; + int OutputPcmBufTotLen;//outputpcmbuf samplebufferlenth 2channels OutputPcmBufTotLen + int OutputPcmLen; + +}PostProcessSt; + +extern int AudioEQdo_auPostProc(PostProcessSt *PostProInfo); //0:fail 1:succed + +#ifdef __cplusplus +} +#endif + +#endif //_POST_PROCESS_COM_H_ diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/STTypes.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/STTypes.h new file mode 100644 index 0000000000..fce5eabeac --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/STTypes.h @@ -0,0 +1,152 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// Common type definitions for SoundTouch audio processing library. +/// +/// Author : Copyright (c) Olli Parviainen +/// Author e-mail : oparviai 'at' iki.fi +/// SoundTouch WWW: http://www.surina.net/soundtouch +/// +//////////////////////////////////////////////////////////////////////////////// +// +// Last changed : $Date: 2011-07-16 11:45:37 +0300 (Sat, 16 Jul 2011) $ +// File revision : $Revision: 3 $ +// +// $Id: STTypes.h 119 2011-07-16 08:45:37Z oparviai $ +// +//////////////////////////////////////////////////////////////////////////////// +// +// License : +// +// SoundTouch audio processing library +// Copyright (c) Olli Parviainen +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef STTypes_H +#define STTypes_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned int uint; +typedef unsigned long ulong; + +#ifdef __GNUC__ + // In GCC, include soundtouch_config.h made by config scritps + //#include "soundtouch_config.h" +#endif + +#ifndef _WINDEF_ + // if these aren't defined already by Windows headers, define now + + typedef int BOOL; + + #define FALSE 0 + #define TRUE 1 + +#endif // _WINDEF_ + + +//namespace soundtouch +//{ + /// Activate these undef's to overrule the possible sampletype + /// setting inherited from some other header file: + //#undef SOUNDTOUCH_INTEGER_SAMPLES + //#undef SOUNDTOUCH_FLOAT_SAMPLES + + #if !(SOUNDTOUCH_INTEGER_SAMPLES || SOUNDTOUCH_FLOAT_SAMPLES) + + /// Choose either 32bit floating point or 16bit integer sampletype + /// by choosing one of the following defines, unless this selection + /// has already been done in some other file. + //// + /// Notes: + /// - In Windows environment, choose the sample format with the + /// following defines. + /// - In GNU environment, the floating point samples are used by + /// default, but integer samples can be chosen by giving the + /// following switch to the configure script: + /// ./configure --enable-integer-samples + /// However, if you still prefer to select the sample format here + /// also in GNU environment, then please #undef the INTEGER_SAMPLE + /// and FLOAT_SAMPLE defines first as in comments above. + #define SOUNDTOUCH_INTEGER_SAMPLES 1 //< 16bit integer samples + //#define SOUNDTOUCH_FLOAT_SAMPLES 1 //< 32bit float samples + + #endif + + #if (WIN32 || __i386__ || __x86_64__) + /// Define this to allow X86-specific assembler/intrinsic optimizations. + /// Notice that library contains also usual C++ versions of each of these + /// these routines, so if you're having difficulties getting the optimized + /// routines compiled for whatever reason, you may disable these optimizations + /// to make the library compile. + + #define SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS 1 + + #endif + + // If defined, allows the SIMD-optimized routines to take minor shortcuts + // for improved performance. Undefine to require faithfully similar SIMD + // calculations as in normal C implementation. + #define SOUNDTOUCH_ALLOW_NONEXACT_SIMD_OPTIMIZATION 1 + + + #ifdef SOUNDTOUCH_INTEGER_SAMPLES + // 16bit integer sample type + typedef short SAMPLETYPE; + // data type for sample accumulation: Use 32bit integer to prevent overflows + typedef long LONG_SAMPLETYPE; + + #ifdef SOUNDTOUCH_FLOAT_SAMPLES + // check that only one sample type is defined + #error "conflicting sample types defined" + #endif // SOUNDTOUCH_FLOAT_SAMPLES + + #ifdef SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS + // Allow MMX optimizations + #define SOUNDTOUCH_ALLOW_MMX 1 + #endif + + #else + + // floating point samples + typedef float SAMPLETYPE; + // data type for sample accumulation: Use double to utilize full precision. + typedef double LONG_SAMPLETYPE; + + #ifdef SOUNDTOUCH_ALLOW_X86_OPTIMIZATIONS + // Allow SSE optimizations + #define SOUNDTOUCH_ALLOW_SSE 1 + #endif + + #endif // SOUNDTOUCH_INTEGER_SAMPLES +//}; + + +// When this #define is active, eliminates a clicking sound when the "rate" or "pitch" +// parameter setting crosses from value <1 to >=1 or vice versa during processing. +// Default is off as such crossover is untypical case and involves a slight sound +// quality compromise. +//#define SOUNDTOUCH_PREVENT_CLICK_AT_RATE_CROSSOVER 1 +#ifdef __cplusplus +} + +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/TouchToStretch.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/TouchToStretch.h new file mode 100644 index 0000000000..da350a3f34 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/TouchToStretch.h @@ -0,0 +1,45 @@ + +#ifndef TOUCH_TO_STRETCH_H +#define TOUCH_TO_STRETCH_H + #ifdef __cplusplus + extern "C" { + #endif +#include "STTypes.h" + +typedef void STPrivData; + +typedef struct RunParameter_s +{ + int VoiceChangeFlag; + int sample_rate; + int channel_number; + float tempoDelta;//'t=xx'[-60.0 60.0] + float pitchDelta;//'p=xx'[-95.0 5000.0] + float rateDelta;//'r=xx'[-95.0 5000.0] + int quick;//'q','-quick' + int noAntiAlias;//'n','-naa' + float goalBPM;//'b','bpm=xx' + int detectBPM;//'b,'bpm=xx' + int speech;//'s','-speech' +}RunParameters; + +typedef enum SetParam_{ + ALL, + TEMPO, + PITCH, + VPS, +}SetParam; +void RunParameters_RunParameters(RunParameters *params); +void RunParameters_checkLimits(RunParameters *params); +void setupSoundTouch(STPrivData* priv_data, const RunParameters *params, SetParam para); +//void processSoundTouch( FILE *inFile, FILE *outFile, const RunParameters *params); +int processSoundTouch( SAMPLETYPE *inbufer, SAMPLETYPE *outbuffer, int nSamples,STPrivData* priv_data); +void* SouchTouchInit(); +void SouchTouchDestroy(STPrivData* priv_data); + + + #ifdef __cplusplus + } + #endif +#endif//TOUCH_TO_STRETCH_H + diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/ad_cedarlib_com.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/ad_cedarlib_com.h new file mode 100644 index 0000000000..40c3a058b5 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/ad_cedarlib_com.h @@ -0,0 +1,142 @@ +#ifndef __BsInfoType__ +#define __BsInfoType__ +#include "adecoder.h" + +typedef struct __AFRAME_INFO +{ + unsigned char *startAddr; + unsigned int ptsValid;//0:锟斤拷前时锟斤拷锟斤拷锟叫э拷锟�锟斤拷锟斤拷前时锟斤拷锟斤拷锟叫� + int64_t pts; + unsigned int len; + unsigned int readlen; +}aframe_info_t; + +typedef struct __ASTREAM_FIFO +{ + aframe_info_t *inFrames; + unsigned int rdIdx;// + unsigned int wtIdx;// + int ValidchunkCnt;//锟斤拷效锟斤拷packet锟斤拷目//0:锟斤拷前帧没锟斤拷锟斤拷荩锟�:锟斤拷前帧锟斤拷锟斤拷锟� unsigned int maxchunkNum; + int64_t NowPTSTime; + int64_t dLastValidPTS; + unsigned int maxchunkNum; +}astream_fifo_t; + + +typedef struct __Ac320FileRead +{ + unsigned int FileLength; //锟侥硷拷锟杰筹拷锟斤拷 + unsigned int FileReadingOpsition; //锟侥硷拷锟铰达拷要锟斤拷锟斤拷位锟矫碉拷偏锟斤拷 + unsigned int FileWritingOpsition; //buffer锟铰达拷要写锟斤拷位锟矫碉拷偏锟斤拷 + unsigned int need_offset; + unsigned short updataoffsetflag; + unsigned short BigENDFlag; //1 big 0 little + unsigned char *bufStart; //buffer锟阶碉拷址 + int BufToTalLen; //锟杰筹拷锟斤拷 + + unsigned char *bufReadingPtr; //锟斤拷锟节讹拷锟斤拷指锟斤拷 + int BufLen; //锟斤拷效锟斤拷莩锟斤拷锟� + unsigned char *bufWritingPtr; //锟斤拷锟节讹拷锟斤拷指锟斤拷 + int BufValideLen; //锟斤拷锟洁长锟斤拷 + //unsigned int ReadingOffset; + astream_fifo_t frmFifo; + //add for android + void* tmpGlobalAudioDecData; + +}Ac320FileRead; + +#define AUD_TAG_INF_SIZE 512 +typedef struct com_internal_struct +{ + //0x88 + unsigned int *pdecInfoSet; + unsigned int *pBackupBufferPoint; + unsigned int ulBitstreamAddPtr; + unsigned int ulDspVersionNum; + unsigned int ulPlayStartTime; + unsigned int ulPlayEndTime; + unsigned int ulBreakSentenceEnergy; + unsigned int ulBreakSentenceTime; + unsigned int ulFileSumData; + unsigned int ulForwardBackSilenceTime; + unsigned int ulForwardBackPlayTime; + unsigned int *SptrumoutAdd; + unsigned int *UserEqinputAdd; + + unsigned short ulBackupLength; + + unsigned char ulNormalPlay; //=ulFadeInOutFinish + unsigned char ulDecComm; + unsigned char ulFadeinFlag; + //0x8b + unsigned char ulFadeInOutFinish; + //0x89 + unsigned int ulTotalTimeMS; + + unsigned int ulAverageBit; + int /*unsigned short*/ ulSampleRate; //?why not this data is fact data; + //0x8a + unsigned char ulExitMean; + unsigned int ulDebugInfo; + //0x60 + unsigned int ulNowTimeMS; + unsigned int ulNowTimeMSAPoint; + unsigned int ulBitrate; + unsigned char ulMode; + unsigned char ulFFREVDoing; + //0x70 + signed char ulVpsSet; + unsigned int/*char*/ ulFFREVStep; + unsigned char ulFFREVFlag; + unsigned char ulABSet; + unsigned char ulEQFlag; + unsigned short ulUserEq[10]; + unsigned char ulspectrum; + unsigned short Hmspetrum;//1-8 +// unsigned short ulspectrumval[8][32]; //reducted for saving memory + unsigned char ulChannelControl; + unsigned char ulVolumeSet; + //0x61 a sentence end + //0x62 dsp mips limit + //0x63 dsp alive minimum time + //0x40 decoder need new bitstream to decode + unsigned int ulReadBitstreamLen; + int ulSkipPageLength; + unsigned char urFadeOutFlag; + unsigned char urFileFlag; + unsigned int urTrueReadLen; + unsigned int ulFilecurrentpage; + //0x41 + unsigned char ulIndex; + unsigned int ulDestinationAdd; + //0x42 + unsigned char ulIndex1; + unsigned int ulDestinationAdd1; + //0x43 + unsigned int bWithVideo; + unsigned int ulDestinationAdd2; + //0x21 + unsigned int *ulBufferAddress; + unsigned int ulBufferLength; + + unsigned short NeedSetPlayTimeFlag; + unsigned int framecount; + + // unsigned char AudTagInfo[AUD_TAG_INF_SIZE]; //reducted for saving memory + +} com_internal; + +typedef struct __AudioDEC_AC320 +{ + Ac320FileRead *FileReadInfo; + BsInFor *BsInformation; + com_internal *DecoderCommand; + int Decinitedflag; + int (*DecInit)(struct __AudioDEC_AC320 *p); + int (*DecFrame)(struct __AudioDEC_AC320 *p,char *OutBuffer,int *OutBuffLen); + int (*DecExit)(struct __AudioDEC_AC320 *p); + +}AudioDEC_AC320; + + +#endif diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/adecoder.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/adecoder.h new file mode 100644 index 0000000000..214207b5d9 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/adecoder.h @@ -0,0 +1,438 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : adecoder.h +* Description : +* History : +* Author : gvc-al2 +* Date : long long ago +*/ + +#ifndef ADECODER_H +#define ADECODER_H + +#include "unistd.h" +#include + +#define OS_LINUX +//#include +//typedef signed long long int64_t; +//typedef int int32_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#define AUDIO_BITSTREAM_BUFFER_SIZE (1024 * 6)//(1024*4096) +#define AUDIO_BITSTREAM_BUFFER_MAX_FRAME_NUM (6)//(4096) +#define AUDIO_PCM_BUFFER_SIZE (16 * 1024)//(512*1024) + +typedef enum __AUDIO_DEC_RESULT +{ + ERR_AUDIO_DEC_EXIT = -4, // exit + ERR_AUDIO_DEC_ENDINGCHKFAIL = -3, //big ending or little ending check failed + ERR_AUDIO_DEC_ABSEND = -2, //audio bitstream decode end + ERR_AUDIO_DEC_ONEFRMFAIL = -1, //decode one frame failed, can try again + + ERR_AUDIO_DEC_NONE = 0, //decode successed, no error + ERR_AUDIO_DEC_FFREVRETURN = 1, //return from fast-forward or fast-reverse + ERR_AUDIO_DEC_RETAPOINT = 2, //return from A point under A/B play mode + ERR_AUDIO_DEC_RETTAG = 3, //return from the first frame of tag play + ERR_AUDIO_DEC_VIDEOJUMP = 4, //0X88 maybe return 4 or 0 + ERR_AUDIO_DEC_NO_BITSTREAM = 5, //No enough bitstream ,try again + ERR_AUDIO_DEC_ + +} __audio_dec_result_t; + +enum EAUDIOCODECFORMAT +{ + AUDIO_CODEC_FORMAT_UNKNOWN = 0, + AUDIO_CODEC_FORMAT_MP1, + AUDIO_CODEC_FORMAT_MP2, + AUDIO_CODEC_FORMAT_MP3, + AUDIO_CODEC_FORMAT_MPEG_AAC_LC, + AUDIO_CODEC_FORMAT_AC3, //* not supported. + AUDIO_CODEC_FORMAT_DTS, //* not supported. + AUDIO_CODEC_FORMAT_LPCM_V, + AUDIO_CODEC_FORMAT_LPCM_A, + AUDIO_CODEC_FORMAT_ADPCM, + AUDIO_CODEC_FORMAT_PCM, + AUDIO_CODEC_FORMAT_WMA_STANDARD, + AUDIO_CODEC_FORMAT_FLAC, + AUDIO_CODEC_FORMAT_APE, + AUDIO_CODEC_FORMAT_OGG, + AUDIO_CODEC_FORMAT_RAAC, + AUDIO_CODEC_FORMAT_COOK, + AUDIO_CODEC_FORMAT_SIPR, + AUDIO_CODEC_FORMAT_ATRC, + AUDIO_CODEC_FORMAT_AMR, + AUDIO_CODEC_FORMAT_RA, + AUDIO_CODEC_FORMAT_PPCM, //* not supported. + AUDIO_CODEC_FORMAT_WMA_LOSS, //* not supported. + AUDIO_CODEC_FORMAT_WMA_PRO, //* not supported. + AUDIO_CODEC_FORMAT_MP3_PRO, //* not supported. + AUDIO_CODEC_FORMAT_ALAC, + AUDIO_CODEC_FORMAT_G729, + AUDIO_CODEC_FORMAT_DSD, + AUDIO_CODEC_FORMAT_OPUS, + AUDIO_CODEC_FORMAT_MLP = AUDIO_CODEC_FORMAT_AC3, + AUDIO_CODEC_FORMAT_ = -1, +}; + +//**************************************************************************// +//* Below are definition for sub codec types. +//**************************************************************************// +#define ABS_EDIAN_FLAG_MASK ((unsigned int)(1<<16)) +#define ABS_EDIAN_FLAG_BIG ((unsigned int)(1<<16)) + +/* Windows WAVE File Encoding Tags */ +#define WAVE_FORMAT_UNKNOWN 0x0000 /* Unknown Format */ +#define WAVE_FORMAT_PCM 0x0001 /* PCM */ +#define WAVE_FORMAT_ADPCM 0x0002 /* Microsoft ADPCM Format */ +#define WAVE_FORMAT_IEEE_FLOAT 0x0003 /* IEEE Float */ +#define WAVE_FORMAT_VSELP 0x0004 /* Compaq Computer's VSELP */ +#define WAVE_FORMAT_IBM_CVSD 0x0005 /* IBM CVSD */ +#define WAVE_FORMAT_ALAW 0x0006 /* ALAW */ +#define WAVE_FORMAT_MULAW 0x0007 /* MULAW */ +#define WAVE_FORMAT_DTS 0x0008 /* Microsoft Corporation */ +#define WAVE_FORMAT_DRM 0x0009 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAVOICE9 0x000A /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAVOICE10 0x000B /* Microsoft Corporation */ +#define WAVE_FORMAT_OKI_ADPCM 0x0010 /* OKI ADPCM */ +#define WAVE_FORMAT_DVI_ADPCM 0x0011 /* Intel's DVI ADPCM */ +#define WAVE_FORMAT_IMA_ADPCM (WAVE_FORMAT_DVI_ADPCM) /* Intel Corporation */ +#define WAVE_FORMAT_MEDIASPACE_ADPCM 0x0012 /* Videologic's MediaSpace ADPCM*/ +#define WAVE_FORMAT_SIERRA_ADPCM 0x0013 /* Sierra ADPCM */ +#define WAVE_FORMAT_G723_ADPCM 0x0014 /* G.723 ADPCM */ +#define WAVE_FORMAT_DIGISTD 0x0015 /* DSP Solution's DIGISTD */ +#define WAVE_FORMAT_DIGIFIX 0x0016 /* DSP Solution's DIGIFIX */ +#define WAVE_FORMAT_DIALOGIC_OKI_ADPCM 0x0017 /* Dialogic OKI ADPCM */ +#define WAVE_FORMAT_MEDIAVISION_ADPCM 0x0018 /* MediaVision ADPCM */ +#define WAVE_FORMAT_CU_CODEC 0x0019 /* HP CU */ +#define WAVE_FORMAT_YAMAHA_ADPCM 0x0020 /* Yamaha ADPCM */ +#define WAVE_FORMAT_SONARC 0x0021 /* Speech Compression's Sonarc */ +#define WAVE_FORMAT_TRUESPEECH 0x0022 /* DSP Group's True Speech */ +#define WAVE_FORMAT_ECHOSC1 0x0023 /* Echo Speech's EchoSC1 */ +#define WAVE_FORMAT_AUDIOFILE_AF36 0x0024 /* Audiofile AF36 */ +#define WAVE_FORMAT_APTX 0x0025 /* APTX */ +#define WAVE_FORMAT_AUDIOFILE_AF10 0x0026 /* AudioFile AF10 */ +#define WAVE_FORMAT_PROSODY_1612 0x0027 /* Prosody 1612 */ +#define WAVE_FORMAT_LRC 0x0028 /* LRC */ +#define WAVE_FORMAT_AC2 0x0030 /* Dolby AC2 */ +#define WAVE_FORMAT_GSM610 0x0031 /* GSM610 */ +#define WAVE_FORMAT_MSNAUDIO 0x0032 /* MSNAudio */ +#define WAVE_FORMAT_ANTEX_ADPCME 0x0033 /* Antex ADPCME */ +#define WAVE_FORMAT_CONTROL_RES_VQLPC 0x0034 /* Control Res VQLPC */ +#define WAVE_FORMAT_DIGIREAL 0x0035 /* Digireal */ +#define WAVE_FORMAT_DIGIADPCM 0x0036 /* DigiADPCM */ +#define WAVE_FORMAT_CONTROL_RES_CR10 0x0037 /* Control Res CR10 */ +#define WAVE_FORMAT_VBXADPCM 0x0038 /* NMS VBXADPCM */ +#define WAVE_FORMAT_ROLAND_RDAC 0x0039 /* Roland RDAC */ +#define WAVE_FORMAT_ECHOSC3 0x003A /* EchoSC3 */ +#define WAVE_FORMAT_ROCKWELL_ADPCM 0x003B /* Rockwell ADPCM */ +#define WAVE_FORMAT_ROCKWELL_DIGITALK 0x003C /* Rockwell Digit LK */ +#define WAVE_FORMAT_XEBEC 0x003D /* Xebec */ +#define WAVE_FORMAT_G721_ADPCM 0x0040 /* Antex Electronics G.721 */ +#define WAVE_FORMAT_G728_CELP 0x0041 /* G.728 CELP */ +#define WAVE_FORMAT_MSG723 0x0042 /* MSG723 */ +#define WAVE_FORMAT_MPEG 0x0050 /* MPEG Layer 1,2 */ +#define WAVE_FORMAT_RT24 0x0051 /* RT24 */ +#define WAVE_FORMAT_PAC 0x0051 /* PAC */ +#define WAVE_FORMAT_MPEGLAYER3 0x0055 /* MPEG Layer 3 */ +//#define WAVE_FORMAT_CIRRUS 0x0059 /* Cirrus */ +#define WAVE_FORMAT_LUCENT_G723 0x0059 /* Lucent Technologies */ +#define WAVE_FORMAT_CIRRUS 0x0060 /* Cirrus Logic */ +#define WAVE_FORMAT_ESPCM 0x0061 /* ESPCM */ +#define WAVE_FORMAT_VOXWARE 0x0062 /* Voxware (obsolete) */ +#define WAVE_FORMAT_CANOPUS_ATRAC 0x0063 /* Canopus Atrac */ +#define WAVE_FORMAT_G726_ADPCM 0x0064 /* G.726 ADPCM */ +#define WAVE_FORMAT_G722_ADPCM 0x0065 /* G.722 ADPCM */ +#define WAVE_FORMAT_DSAT 0x0066 /* DSAT */ +#define WAVE_FORMAT_DSAT_DISPLAY 0x0067 /* DSAT Display */ +#define WAVE_FORMAT_VOXWARE_BYTE_ALIGNED 0x0069 /* Voxware Byte Aligned (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC8 0x0070 /* Voxware AC8 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC10 0x0071 /* Voxware AC10 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC16 0x0072 /* Voxware AC16 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC20 0x0073 /* Voxware AC20 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_RT24 0x0074 /* Voxware MetaVoice (obsolete) */ +#define WAVE_FORMAT_VOXWARE_RT29 0x0075 /* Voxware MetaSound (obsolete) */ +#define WAVE_FORMAT_VOXWARE_RT29HW 0x0076 /* Voxware RT29HW (obsolete) */ +#define WAVE_FORMAT_VOXWARE_VR12 0x0077 /* Voxware VR12 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_VR18 0x0078 /* Voxware VR18 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_TQ40 0x0079 /* Voxware TQ40 (obsolete) */ +#define WAVE_FORMAT_SOFTSOUND 0x0080 /* Softsound */ +#define WAVE_FORMAT_VOXWARE_TQ60 0x0081 /* Voxware TQ60 (obsolete) */ +#define WAVE_FORMAT_MSRT24 0x0082 /* MSRT24 */ +#define WAVE_FORMAT_G729A 0x0083 /* G.729A */ +#define WAVE_FORMAT_MVI_MV12 0x0084 /* MVI MV12 */ +#define WAVE_FORMAT_DF_G726 0x0085 /* DF G.726 */ +#define WAVE_FORMAT_DF_GSM610 0x0086 /* DF GSM610 */ +#define WAVE_FORMAT_ISIAUDIO 0x0088 /* ISIAudio */ +#define WAVE_FORMAT_ONLIVE 0x0089 /* Onlive */ +#define WAVE_FORMAT_SBC24 0x0091 /* SBC24 */ +#define WAVE_FORMAT_DOLBY_AC3_SPDIF 0x0092 /* Dolby AC3 SPDIF */ +#define WAVE_FORMAT_MEDIASONIC_G723 0x0093 /* MediaSonic */ +#define WAVE_FORMAT_PROSODY_8KBPS 0x0094 /* Aculab plc */ +#define WAVE_FORMAT_ZYXEL_ADPCM 0x0097 /* ZyXEL ADPCM */ +#define WAVE_FORMAT_PHILIPS_LPCBB 0x0098 /* Philips LPCBB */ +#define WAVE_FORMAT_PACKED 0x0099 /* Packed */ +#define WAVE_FORMAT_MALDEN_PHONYTALK 0x00A0 /* Malden Electronics Ltd. */ +#define WAVE_FORMAT_RHETOREX_ADPCM 0x0100 /* Rhetorex ADPCM */ +#define WAVE_FORMAT_IRAT 0x0101 /* BeCubed Software's IRAT */ +#define WAVE_FORMAT_VIVO_G723 0x0111 /* Vivo G.723 */ +#define WAVE_FORMAT_VIVO_SIREN 0x0112 /* Vivo Siren */ +#define WAVE_FORMAT_DIGITAL_G723 0x0123 /* Digital G.723 */ +#define WAVE_FORMAT_SANYO_LD_ADPCM 0x0125 /* Sanyo Electric Co., Ltd. */ +#define WAVE_FORMAT_SIPROLAB_ACEPLNET 0x0130 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_ACELP4800 0x0131 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_ACELP8V3 0x0132 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_G729 0x0133 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_G729A 0x0134 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_KELVIN 0x0135 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_G726ADPCM 0x0140 /* Dictaphone Corporation */ +#define WAVE_FORMAT_QUALCOMM_PUREVOICE 0x0150 /* Qualcomm, Inc. */ +#define WAVE_FORMAT_QUALCOMM_HALFRATE 0x0151 /* Qualcomm, Inc. */ +#define WAVE_FORMAT_TUBGSM 0x0155 /* Ring Zero Systems, Inc. */ +#define WAVE_FORMAT_MSAUDIO1 0x0160 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAUDIO2 0x0161 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAUDIO3 0x0162 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAUDIO_LOSSLESS 0x0163 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMASPDIF 0x0164 /* Microsoft Corporation */ +#define WAVE_FORMAT_UNISYS_NAP_ADPCM 0x0170 /* Unisys Corp. */ +#define WAVE_FORMAT_UNISYS_NAP_ULAW 0x0171 /* Unisys Corp. */ +#define WAVE_FORMAT_UNISYS_NAP_ALAW 0x0172 /* Unisys Corp. */ +#define WAVE_FORMAT_UNISYS_NAP_16K 0x0173 /* Unisys Corp. */ +#define WAVE_FORMAT_CREATIVE_ADPCM 0x0200 /* Creative ADPCM */ +#define WAVE_FORMAT_CREATIVE_FASTSPEECH8 0x0202 /* Creative FastSpeech8 */ +#define WAVE_FORMAT_CREATIVE_FASTSPEECH10 0x0203 /* Creative FastSpeech10 */ +#define WAVE_FORMAT_UHER_ADPCM 0x0210 /* UHER informatic GmbH */ +#define WAVE_FORMAT_QUARTERDECK 0x0220 /* Quarterdeck */ +#define WAVE_FORMAT_ILINK_VC 0x0230 /* I-link Worldwide */ +#define WAVE_FORMAT_RAW_SPORT 0x0240 /* Aureal Semiconductor */ +#define WAVE_FORMAT_ESST_AC3 0x0241 /* ESS Technology, Inc. */ +#define WAVE_FORMAT_GENERIC_PASSTHRU 0x0249 +#define WAVE_FORMAT_IPI_HSX 0x0250 /* Interactive Products, Inc. */ +#define WAVE_FORMAT_IPI_RPELP 0x0251 /* Interactive Products, Inc. */ +#define WAVE_FORMAT_CS2 0x0260 /* Consistent Software */ +#define WAVE_FORMAT_SONY_SCX 0x0270 /* Sony Corp. */ +#define WAVE_FORMAT_FM_TOWNS_SND 0x0300 /* FM Towns Snd */ +#define WAVE_FORMAT_BTV_DIGITAL 0x0400 /* BTV Digital */ +#define WAVE_FORMAT_QDESIGN_MUSIC 0x0450 /* QDesign Corporation */ +#define WAVE_FORMAT_VME_VMPCM 0x0680 /* VME VMPCM */ +#define WAVE_FORMAT_TPC 0x0681 /* AT&T Labs, Inc. */ +#define WAVE_FORMAT_OLIGSM 0x1000 /* OLIGSM */ +#define WAVE_FORMAT_OLIADPCM 0x1001 /* OLIADPCM */ +#define WAVE_FORMAT_OLICELP 0x1002 /* OLICELP */ +#define WAVE_FORMAT_OLISBC 0x1003 /* OLISBC */ +#define WAVE_FORMAT_OLIOPR 0x1004 /* OLIOPR */ +#define WAVE_FORMAT_LH_CODEC 0x1100 /* LH Codec */ +#define WAVE_FORMAT_NORRIS 0x1400 /* Norris */ +//#define WAVE_FORMAT_ISIAUDIO 0x1401 /* ISIAudio */ +#define WAVE_FORMAT_SOUNDSPACE_MUSICOMPRESS 0x1500 /* Soundspace Music Compression */ +#define WAVE_FORMAT_MPEG_ADTS_AAC 0x1600 /* Microsoft Corporation */ +#define WAVE_FORMAT_MPEG_RAW_AAC 0x1601 /* Microsoft Corporation */ +#define WAVE_FORMAT_NOKIA_MPEG_ADTS_AAC 0x1608 /* Microsoft Corporation */ +#define WAVE_FORMAT_NOKIA_MPEG_RAW_AAC 0x1609 /* Microsoft Corporation */ +#define WAVE_FORMAT_VODAFONE_MPEG_ADTS_AAC 0x160A /* Microsoft Corporation */ +#define WAVE_FORMAT_VODAFONE_MPEG_RAW_AAC 0x160B /* Microsoft Corporation */ +#define WAVE_FORMAT_DVM 0x2000 /* DVM */ +#define WAVE_FORMAT_EXTENSIBTSMIRACAST 0xFFFC /* LSZHANG TS Miracast WIFI*/ +#define WAVE_FORMAT_EXTENSIBTS 0xFFFD /* LSZHANG TS */ +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* SubFormat */ +#define WAVE_FORMAT_DVD_LPCM 0xFFA0 /* Added by Khan for DVD-LPCM*/ + +#define WAVE_FORMAT_DEVELOPMENT 0xFFFF /* Development */ + +//user define adpcm codec type from video file +#define ADPCM_CODEC_ID_IMA_QT 0xE000 +#define ADPCM_CODEC_ID_IMA_WAV 0xE001 /* from avi file format */ +#define ADPCM_CODEC_ID_IMA_DK3 0xE002 +#define ADPCM_CODEC_ID_IMA_DK4 0xE003 +#define ADPCM_CODEC_ID_IMA_WS 0xE004 +#define ADPCM_CODEC_ID_IMA_SMJPEG 0xE005 +#define ADPCM_CODEC_ID_MS 0xE006 +#define ADPCM_CODEC_ID_4XM 0xE007 +#define ADPCM_CODEC_ID_XA 0xE008 +#define ADPCM_CODEC_ID_ADX 0xE009 +#define ADPCM_CODEC_ID_EA 0xE00A +#define ADPCM_CODEC_ID_G726 0xE00B +#define ADPCM_CODEC_ID_CT 0xE00C +#define ADPCM_CODEC_ID_SWF 0xE00D /* from flv/swf file format */ +#define ADPCM_CODEC_ID_YAMAHA 0xE00E +#define ADPCM_CODEC_ID_SBPRO_4 0xE00F +#define ADPCM_CODEC_ID_SBPRO_3 0xE010 +#define ADPCM_CODEC_ID_SBPRO_2 0xE011 + +#define AMR_FORMAT_NONE 0 // undefine amr format +#define AMR_FORMAT_NARROWBAND 1 // narrow band amr format +#define AMR_FORMAT_WIDEBAND 2 // wide band amr format + +#define ADECODER_MAX_LANG_CHAR_SIZE (64) + +typedef struct Cedar_raw_data CdxPlaybkCfg; + +enum AUIDO_RAW_DATA_TYPE +{ + AUDIO_RAW_DATA_UNKOWN = 0, + AUDIO_RAW_DATA_PCM = 1, + AUDIO_RAW_DATA_AC3 = 2, + AUDIO_RAW_DATA_MPEG1 = 3, + AUDIO_RAW_DATA_MP3 = 4, + AUDIO_RAW_DATA_MPEG2 = 5, + AUDIO_RAW_DATA_AAC = 6, + AUDIO_RAW_DATA_DTS = 7, + AUDIO_RAW_DATA_ATRAC = 8, + AUDIO_RAW_DATA_ONE_BIT_AUDIO = 9, + AUDIO_RAW_DATA_DOLBY_DIGITAL_PLUS = 10, + AUDIO_RAW_DATA_DTS_HD = 11, + AUDIO_RAW_DATA_MAT = 12, + AUDIO_RAW_DATA_DST = 13, + AUDIO_RAW_DATA_WMAPRO = 14 +}; + +struct Cedar_raw_data +{ + int nRoutine;//UI set 0:pcm;1:hdmi raw data;2:spdif raw data; + int nNeedDirect;//if init flag 0:no init raw;1:init raw + int nChannels; + int nSamplerate; + int nBitpersample; + enum AUIDO_RAW_DATA_TYPE nDataType; +}; + +typedef struct AUDIOSTREAMINFO +{ + enum EAUDIOCODECFORMAT eCodecFormat; + int eSubCodecFormat; // + int nChannelNum; + int nBitsPerSample; + int nSampleRate; + int nAvgBitrate; + int nMaxBitRate; + unsigned int nFileSize; + int eAudioBitstreamSource; + int eDataEncodeType; + unsigned char strLang[ADECODER_MAX_LANG_CHAR_SIZE]; + int nCodecSpecificDataLen; + char* pCodecSpecificData; + int nFlags; + int nBlockAlign; + CdxPlaybkCfg raw_data; +}AudioStreamInfo; + +typedef struct __BsInFor +{ + int TotalplayTime; + int NowPlayTime; + int Samplerate; + int bitrate; + int chan; + int CBRflag;//1 cbr 0 vbr + int framesize; + int framecount; + int oldfs; + int oldbs; + int firstflag; + int framepcms; + int modeflag;//flag 0bits: 1:raw data 0:pcm + int ulMode;//decode flag 0:pcm ,>raw data out ,1:hdmi,2:spdif + int bitpersample;//bits per sample + //add for control from ad_cedar_ctx + int nBitStreamUnderFlow; + int nShowBitsReturn; + int out_channels; + int out_samplerate; + //global + int nDecodeMode; + int nDemuxType; + int nIsHwCodec; + int64_t NowPTSTime; + +}BsInFor; + +typedef struct AudioDecoder AudioDecoder; +struct AudioDecoder +{ + int nPrivFlag;//0:play,1:reset,2:file end + int nGetAudioInfoFlag; + int nAudioChannel; + int volumegain; + int mute; + int nEnableResample; + int RawPlayFlag; +}; + +int ParserRequestBsBuffer(AudioDecoder* pDecoder, + int nRequireSize, + unsigned char** ppBuf, + int* pBufSize, + unsigned char** ppRingBuf, + int* pRingBufSize, + int* nOffset); + +int ParserUpdateBsBuffer(AudioDecoder* pDecoder, + int nFilledLen, + int64_t nTimeStamp, + int nOffset); + +void BsQueryQuality(AudioDecoder* pDecoder, + int* pValidPercent, + int* vbv); + +int AudioStreamDataSize(AudioDecoder* pDecoder); + +int AudioStreamBufferSize(void); + +int AudioStreamBufferMaxFrameNum(void); + +int AudioPCMDataSize(AudioDecoder* pDecoder); + +int DecRequestPcmBuffer(AudioDecoder* pDecoder, char **pOutWritePtr); + +int DecUpdatePcmBuffer(AudioDecoder* pDecoder, int nPcmOutSize); + +int PlybkRequestPcmBuffer(AudioDecoder* pDecoder, unsigned char **pOutReadPtr, int *psize); + +int PlybkUpdatePcmBuffer(AudioDecoder* pDecoder, int nPcmOutSize); + +int64_t PlybkRequestPcmPts(AudioDecoder* pDecoder); + +void PcmQueryQuality(AudioDecoder* pDecoder, int* pValidPercent, int* vbv); + +void AudioDecoderSeek(AudioDecoder* pDecoder, int64_t nSeekTime); + +int InitializeAudioDecoder(AudioDecoder* pDecoder, + AudioStreamInfo* pAudioStreamInfo, + BsInFor* pBsInFor); + +int ResetAudioDecoder(AudioDecoder* pDecoder, int64_t nSeekTime); + +int DecodeAudioStream(AudioDecoder* pDecoder, + AudioStreamInfo* pAudioStreamInfo, + char* ppBuf, + int* pBufSize); + +int DestroyAudioDecoder(AudioDecoder* pDecoder); + +AudioDecoder* CreateAudioDecoder(void); +#ifdef OS_LINUX +void SetRawPlayParam(AudioDecoder* pDecoder,void *self,int flag); +#else +void SetRawPlayParam(AudioDecoder* pDecoder,void *self); +#endif + +#ifdef CEDARX_SUPPORT_SOUNDTOUCH +void AudioSoundTouchSetPitch(AudioDecoder* pDecoder, float pitchDelta); +#endif + +#if VOLUME_SUPPORT +#ifdef OS_LINUX +int SetAudioVolume(AudioDecoder* pDecoder, int32_t nVolume); +#endif +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/auGaincom.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/auGaincom.h new file mode 100644 index 0000000000..35cfed4b78 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/auGaincom.h @@ -0,0 +1,15 @@ + +#ifndef ___AUGAINCOM_H__ +#define ___AUGAINCOM_H__ + +typedef struct ___AudioGain__{ +//input para + int preamp;//-20 -- 20 db + int InputChan; + short *InputPtr; + int InputLen;//total byte + int OutputChan;//0 1: only 2 3: double left 4:double right + short *OutputPtr; +}AudioGain; +int do_AudioGain(AudioGain *AGX); +#endif//___AUGAINCOM_H__ \ No newline at end of file diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/aumixcom.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/aumixcom.h new file mode 100644 index 0000000000..6849f175f0 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/aumixcom.h @@ -0,0 +1,32 @@ + +#ifndef ___aumixcommon__ +#define ___aumixcommon__ +typedef struct __PcmInfo__{ +//input infor + unsigned int SampleRate; + short *PCMPtr; + unsigned int PcmLen; + unsigned int Chan; +}PcmInfo; + +typedef struct ___AudioMix__{ +//input para + PcmInfo *InputA; + PcmInfo *InputB; + PcmInfo *TempBuf; + PcmInfo *Output; + unsigned int ByPassflag; + //output para + short *MixbufPtr; + unsigned int MixLen; + unsigned int Mixch; + void* RESI; + +}AudioMix; +#if MIX_SUPPORT +int do_AuMIX(AudioMix *AMX); +#endif +void* Init_ResampleInfo(); +void Destroy_ResampleInfo(void * ri); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/cedar_abs_packet_hdr.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/cedar_abs_packet_hdr.h new file mode 100644 index 0000000000..4f4d88df3a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/cedar_abs_packet_hdr.h @@ -0,0 +1,63 @@ +/* +********************************************************************************************************* +* eMOD +* the Easy Portable/Player Operation System +* mod_mmp sub-system +* +* (c) Copyright 2008-2009, Kevin.Z China +* All Rights Reserved +* +* File : cedar_abs_packet_hdr.h +* Version: V1.0 +* By : kevin.z +* Date : 2009-4-17 10:23 +********************************************************************************************************* +*/ +#ifndef _CEDAR_ABS_PACKET_HDR_H_ +#define _CEDAR_ABS_PACKET_HDR_H_ + +#include "adecoder.h" +#include "ad_cedarlib_com.h" + +int AdCedarBuildAACPacketHdr(unsigned char* extraData, + int extraDataLen , + int uPacketLen, + unsigned char* pBuf, + int* pHdrLen, + int channels, + int sampleRate); + +int AdCedarUpdateAACPacketHdr(unsigned char* pBuf, int uHdrLen, int uPacketLen); + +int split_xiph_headers(unsigned char* codec_priv, + int codec_priv_size, + char** extradata, + int* extradata_size); + +int SetAudioBsHeader_PCM(AudioStreamInfo* tmpAbsFmt, Ac320FileRead* FileReadInfo); + +/* +-------------------------------------------------------------------------------- +AAC ADTS HEADER BIT INFORMATION DEFINE, BASED ON BIT STREAM +-------------------------------------------------------------------------------- +syncword:12 0xfff +id :1 0x0 +layer :2 0x0 +protect :1 0x1 +profile :2 +fsidx :4 +priv :1 0x0 +chncfg :3 +origcpy :1 0x0 +home :1 0x0 + +cpybit :1 0x0 +cpystart:1 0x0 +frmlen :13 +buffull :11 0x7ff +rawblk :2 0x1 +-------------------------------------------------------------------------------- +*/ + + +#endif //_CEDAR_ABS_PACKET_HDR_H_ diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/log.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/log.h new file mode 100644 index 0000000000..44e772abf4 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/log.h @@ -0,0 +1,119 @@ +#ifndef LOG_H +#define LOG_H +#ifndef LOG_TAG +#define LOG_TAG "AllwinnerAudioCodec" +#endif + +#include "cdx_malloc_dbg.h" + + +// temp define +#define MP3_SUPPORT (1) +#define AMR_SUPPORT (1) + +#define OPTION_LOG_LEVEL_CLOSE +#define IOT_CEDARX_DECODE_LIB (1) +#define VOLUME_SUPPORT (0) +#define MIX_SUPPORT (0) +#define OS_LINUX + +#define OS_FREERTOS + +#ifdef OS_ANDROID + #include + + #define LOG_LEVEL_ERROR ANDROID_LOG_ERROR + #define LOG_LEVEL_WARNING ANDROID_LOG_WARN + #define LOG_LEVEL_INFO ANDROID_LOG_INFO + #define LOG_LEVEL_VERBOSE ANDROID_LOG_VERBOSE + #define LOG_LEVEL_DEBUG ANDROID_LOG_DEBUG + + #define AWLOG(level, fmt, arg...) \ + LOG_PRI(level, LOG_TAG, "<%s:%u>: "fmt, __FUNCTION__, __LINE__, ##arg) + +#elif (defined OS_LINUX) + #include + #include + + #ifndef LOG_LEVEL_ERROR + #define LOG_LEVEL_ERROR "error " + #endif + #ifndef LOG_LEVEL_WARNING + #define LOG_LEVEL_WARNING "warning" + #endif + #ifndef LOG_LEVEL_INFO + #define LOG_LEVEL_INFO "info " + #endif + #ifndef LOG_LEVEL_VERBOSE + #define LOG_LEVEL_VERBOSE "verbose" + #endif + #ifndef LOG_LEVEL_DEBUG + #define LOG_LEVEL_DEBUG "debug " + #endif + + int wrap_printf(const char *fmt, ...); + #define AWLOG(level, fmt, arg...) \ + wrap_printf("%s: %s <%s:%u>: "fmt"\n", level, LOG_TAG, __FUNCTION__, __LINE__, ##arg)/* printf("%s: %s <%s:%u>: "fmt"\n", level, LOG_TAG, __FUNCTION__, __LINE__, ##arg) */ +#elif (defined OS_FREERTOS) + #include + #include + + #define LOG_LEVEL_ERROR "error " + #define LOG_LEVEL_WARNING "warning" + #define LOG_LEVEL_INFO "info " + #define LOG_LEVEL_VERBOSE "verbose" + #define LOG_LEVEL_DEBUG "debug " + + #define AWLOG(level, fmt, arg...) \ + printf("%s: %s <%s:%u>: "fmt"\n", level, LOG_TAG, __func__, __LINE__, ##arg) +#else + #error "invalid configuration of os." +#endif + +#define logd(fmt, arg...) //AWLOG(LOG_LEVEL_DEBUG, fmt, ##arg) + +#ifdef OPTION_LOG_LEVEL_CLOSE + +#define loge(fmt, arg...) +#define logw(fmt, arg...) +#define logi(fmt, arg...) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_ERROR) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) +#define logi(fmt, arg...) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_WARNING) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_DEFAULT) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) AWLOG(LOG_LEVEL_INFO, fmt, ##arg) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_DETAIL) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) AWLOG(LOG_LEVEL_INFO, fmt, ##arg) +#define logv(fmt, arg...) AWLOG(LOG_LEVEL_VERBOSE, fmt, ##arg) + +#else + #error "invalid configuration of debug level." +#endif + +#define printf wrap_printf +#define PRINTF printf +#define CDX_FAILED() //PRINTF("[%s failed] line %d\n", __func__, __LINE__) + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/rw_data_api.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/rw_data_api.h new file mode 100644 index 0000000000..436df1ff3f --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/include/rw_data_api.h @@ -0,0 +1,31 @@ +#ifndef RW_DATA_API_H +#define RW_DATA_API_H +#include +#include +#include +#include "ad_cedarlib_com.h" +#include "AudioDec_Decode.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int ShowAbsBits(void *buf, int Len, Ac320FileRead *FileInfo); + +void FlushAbsBits(int Len, Ac320FileRead *FileInfo); + +int FREAD_AC320(void *buf, int Len, Ac320FileRead *FileInfo); + +int FSeek_AC320(int Len, Ac320FileRead *FileInfo); + +int FSeek_AC320_Origin(int Len, Ac320FileRead *FileInfo, int origin); + +void FlushPtsAtOnce(Ac320FileRead *FileInfo); + +int BigLitEndianCheck(Ac320FileRead *FileInfo, short data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/tools/memcheck/memcheck.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/tools/memcheck/memcheck.h new file mode 100644 index 0000000000..1d6b67bd4a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/tools/memcheck/memcheck.h @@ -0,0 +1,32 @@ +#ifndef MEMCHECK_H +#define MEMCHECK_H +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include +#include +#include + +#define RECSIZE 8*1024 + +typedef struct _mymeminfo mymeminfo; + +struct _mymeminfo +{ + int size; + unsigned int ptr; + const char* name; + int line; + int malloc; + int free; +}; + +void* ckmalloc(int size, const char* name, int line); +void ckfree(void* ptr); +int getmallocsz(); +int getfreesz(); +void showmeinfo(); +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif \ No newline at end of file diff --git a/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/tools/memcheck/memname.h b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/tools/memcheck/memname.h new file mode 100644 index 0000000000..88896cabb2 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Cdx2.0Plugin/tools/memcheck/memname.h @@ -0,0 +1,7 @@ +#ifndef MEMNAME_H +#define MEMNAME_H + +#define malloc(a) ckmalloc(a, __func__, __LINE__) +#define free(a) ckfree(a) + +#endif \ No newline at end of file diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/Android.mk b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/Android.mk new file mode 100644 index 0000000000..7767b75d8a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/Android.mk @@ -0,0 +1,38 @@ +LOCAL_PATH:= $(call my-dir) + +include $(CLEAR_VARS) + +include $(LOCAL_PATH)/../../../config.mk + +LOCAL_MODULE_TAGS := optional + +LOCAL_SRC_FILES:= \ + $(notdir $(wildcard $(LOCAL_PATH)/*.c)) \ + $(notdir $(wildcard $(LOCAL_PATH)/*.cpp)) + +LOCAL_C_INCLUDES := \ + $(LOCAL_PATH) \ + $(LOCAL_PATH)/include \ + $(LOCAL_PATH)/../../../VE/include \ + $(LOCAL_PATH)/../../../MEMORY/include \ + $(LOCAL_PATH)/../../../ \ + + +LOCAL_SHARED_LIBRARIES := \ + libcutils \ + libutils \ + libVE \ + libMemAdapter + +LOCAL_LDLIBS := -llog + +LOCAL_LDFLAGS += $(LOCAL_PATH)/lib_a4.4/static/libaacenc.a \ + $(LOCAL_PATH)/lib_a4.4/static/libadpcmenc.a \ + $(LOCAL_PATH)/lib_a4.4/static/libmp3enc.a \ +# +# $(LOCAL_PATH)/lib_a4.4/static/libpcmenc.a + + +LOCAL_MODULE:= libaencoder + +include $(BUILD_SHARED_LIBRARY) diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/Makefile b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/Makefile new file mode 100644 index 0000000000..f4381fab2d --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/Makefile @@ -0,0 +1,176 @@ +AudioEncBASE = /home/$(USER)/SVNAudioLib/dev/audiodec/codec/CdxEncPlugin +AudioLibBASE = /home/$(USER)/SVNAudioLib/dev/audiodec/codec/AudioLib + +include $(AudioEncBASE)/config.mk + +################################################################################ +## set flags for golobal compile and link setting. +################################################################################ + +CONFIG_FOR_COMPILE = +CONFIG_FOR_LINK = + +################################################################################ +## set target. +################################################################################ + +TargetName = libaencoder.so +Target = $(LIBPATH)/$(TargetName) + +################################################################################ +## build configures print. +################################################################################ + +$(warning "#################################################") +$(warning "# Allwinner audio codec compile information ") +$(warning "# ") +$(warning "# OS_PLATFORM is $(OS_PLATFORM)") +$(warning "# CONFIG_CC is $(CONFIG_CC)") +$(warning "# CONFIG_LOG_LEVEL is $(CONFIG_LOG_LEVEL)") +$(warning "# OS_DEBUG_CONFIG is $(OS_DEBUG_CONFIG)") +$(warning "# OS_CHECK_MEMORY_CONFIG is $(OS_CHECK_MEMORY_CONFIG)") +$(warning "# TargetName is $(TargetName)") +$(warning "# Target generated at $(LIBPATH)") +$(warning "# ") +$(warning "#################################################") + +################################################################################ +## set build path and build target. +################################################################################ + +ifneq ($(LIBPATH),wildcard($(LIBPATH))) +a := $(shell mkdir -p $(LIBPATH)) +endif +ifneq ($(BUILDPATH),wildcard($(BUILDPATH))) +a := $(shell mkdir -p $(BUILDPATH)) +endif + +################################################################################ +## set the source files, object files and dependency files +################################################################################ + +## set the source files. +SourceFiles = aencoder.c pcm_enc.c +$(warning "SourceFiles : $(SourceFiles)") + +################################################################################ +## set obj files, mkdir respect build dir +################################################################################ + +SourcePath = $(foreach src_dir, $(SourceFiles), $(dir $(src_dir))) +$(foreach src_dir, $(SourcePath), $(shell mkdir -p $(BUILDPATH)/$(src_dir))) + +ObjectFiles = $(addprefix $(BUILDPATH)/, $(addsuffix .o ,$(basename $(SourceFiles)))) + +## set the include path for compile flags. +SourceIncludePath = $(foreach dir,$(SourcePath),-I$(dir)) \ + -I../../../ \ + -I./include \ + +## set compile flags +CompileFlags = $(CONFIG_FOR_COMPILE) $(SourceIncludePath) -O1 -fPIC -ldl +#-mfpu=neon + +ifeq ($(OS_PLATFORM), OS_LINUX) +CompileFlags += -DOS_LINUX $(EXTRA_FLAG) +endif + +ifeq ($(OS_DEBUG_CONFIG), true) +CompileFlags += -D__AD_CEDAR_DBG_WRITEOUT_BITSTREAM +CompileFlags += -D__AD_CEDAR_DBG_WRITEOUT_PCM_BUFFER +endif + +ifeq ($(CONFIG_LOG_LEVEL), OPTION_LOG_LEVEL_CLOSE) +CompileFlags += -DOPTION_LOG_LEVEL_CLOSE +endif + +ifeq ($(CONFIG_LOG_LEVEL), OPTION_LOG_LEVEL_ERROR) +CompileFlags += -DOPTION_LOG_LEVEL_ERROR +endif + +ifeq ($(CONFIG_LOG_LEVEL), OPTION_LOG_LEVEL_WARNING) +CompileFlags += -DOPTION_LOG_LEVEL_WARNING +endif + +ifeq ($(CONFIG_LOG_LEVEL), OPTION_LOG_LEVEL_DEFAULT) +CompileFlags += -DOPTION_LOG_LEVEL_DEFAULT +endif + +ifeq ($(CONFIG_LOG_LEVEL), OPTION_LOG_LEVEL_DETAIL) +CompileFlags += -DOPTION_LOG_LEVEL_DETAIL +endif + +## set link flags +LoadFlags = $(CONFIG_FOR_LINK) -ldl -shared + +LoadFlags += -lpthread -laacenc -lmp3enc -lpcmenc -lm +#-lstdc++ -Wl,--whole-archive -Wl,--no-whole-archive + +ifeq ($(CONFIG_CC), OPTION_CC_GNUEABIHF) +LoadFlags += -Llib/build_by_arm_linux_gnueabihf_static +endif + +ifeq ($(CONFIG_CC),OPTION_CC_GNUEABI) +LoadFlags += -Llib/linuxgnueabi/ +endif + +ifeq ($(CONFIG_CC),OPTION_CC_UCGNUEABI) +LoadFlags += -Llib/uclgnueabi/ +endif + +ifeq ($(CONFIG_CC),OPTION_CC_LINUX_UCGNUEABI) +LoadFlags += -Llib/linuxgnueabi/ +endif + +ifeq ($(CONFIG_CC),OPTION_CC_LINUX_MUSLGNUEABI) +LoadFlags +=-Llib/arm926_musl +#LoadFlags +=-L./lib/muslgnueabi +endif + +ifeq ($(CONFIG_CC),OPTION_CC_LINUX_MUSLGNUEABI64) +LoadFlags +=-Llib/muslgnueabi64 +endif + +ifeq ($(CONFIG_CC),OPTION_CC_AARCH64_OPENWRT_MUSL) +LoadFlags +=-Llib/aarch64_openwrt_linux_musl_gcc +endif + +################################################################################ +## make commands, all/clean/cleanall +################################################################################ + +## define commands for make, sush as all, clean +.PHONY: all clean cleantarget cleanall +all:$(Target) + @echo Make $(TargetName) over... + @echo Target path : $(LIBPATH) + +clean: + -rm -rf $(ObjectFiles) + -rm -rf $(Target) + +cleanall: clean + -rm -rf $(BUILDPATH) + + +################################################################################ +## define target , ld target. +################################################################################ + +## compile source files to object files. +$(BUILDPATH)/%.o:%.c + $(CC) $(CompileFlags) -o $@ -c $< + +## link object files to the target share library. +$(Target):$(ObjectFiles) + $(LD) -o $@ $^ $(LoadFlags) + + +## include the .d files to set dependency rules. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(MAKECMDGOALS),cleantarget) +ifneq ($(MAKECMDGOALS),cleanall) +-include $(DependFiles) +endif +endif +endif diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/aacencApi.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/aacencApi.h new file mode 100644 index 0000000000..6ca73a7b30 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/aacencApi.h @@ -0,0 +1,18 @@ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __AAC_ENC_LIB_API__ +#define __AAC_ENC_LIB_API__ + +#include + +extern struct __AudioENC_AC320 *AudioAACENCEncInit(); +extern int AudioAACENCEncExit(struct __AudioENC_AC320 *p); + +#endif // __AAC_ENC_LIB_API__ + +#ifdef __cplusplus +} +#endif diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/aenc_sw_lib.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/aenc_sw_lib.h new file mode 100644 index 0000000000..a4bc7abd50 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/aenc_sw_lib.h @@ -0,0 +1,106 @@ +/* +******************************************************************************** +* eMOD +* the Easy Portable/Player Develop Kits +* mod_herb sub-system +* (module name, e.g.mpeg4 decoder plug-in) module +* +* (c) Copyright 2009-2010, Allwinner Microelectronic Co., Ltd. +* All Rights Reserved +* +* File : aenc_sw_lib.h +* Version: V1.0 +* By : Eric_wang +* Date : 2010-4-26 +* Description: +******************************************************************************** +*/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "aencoder.h" + +#ifndef _AENC_SW_LIB_H_ +#define _AENC_SW_LIB_H_ + +#define FIFO_LEVEL (4)//(32) + +#define BS_BUFFER_SIZE (12*1024)//(128*1024) +//#define PCM_FRAME_SIZE (32*1024) +#define BS_HEADER_SIZE (1*1024) + +//#define OUT_BUFFER_SIZE (512*1024) +#define OUT_ENCODE_BUFFER_SIZE (2*1024)//(4*1024) //byte +#define MAXDECODESAMPLE (1024) + +//encode input data information +typedef struct __audio_enc_inf_t +{ + int InSamplerate; //fs + int InChan; //pcm chan 1:mon 2:stereo + int bitrate; //bs + int SamplerBits; //only for 16bits + int OutSamplerate; //fs,now OutSamplerate must equal InSamplerate + int OutChan; // chan + int frame_style; //for aac: 0:add head,1:raw data; for pcm: 2:mpegTs pcm(big endian), other: common pcm(little endian) + +}__audio_enc_inf_t; + +//#define BsBuffLEN 20*1024 +typedef struct __PCM_BUF_MANAGER +{ + unsigned char *pBufStart; //buffer׵ַ + int uBufTotalLen; //ܳ + unsigned char *pBufReadPtr; //ڶָ + int uDataLen; //Чݳ + unsigned char *pBufWritPtr; //дָ + int uFreeBufSize; //೤ + int uDataFlowflag; //Ƿ񳬹Ԥ룬10֡0ûг + void *parent; // encode use,not lib use; + +} __pcm_buf_manager_t; + + +typedef struct __COM_INTERNAL_PARAMETER +{ + unsigned int ulNowTimeMS; //ǰʱms + unsigned int ulPCMgainSet; //PCM + unsigned int framecount; //frames + + unsigned int ulEncCom; //0: normal enc 1: ff end 5: stop + unsigned char BsHeaderBuf[BS_HEADER_SIZE]; + unsigned int ValidHeaderLen; + unsigned int *pEncInfoSet; // encode lib use; + +} __com_internal_prameter_t; + + +typedef struct __AudioENC_AC320 +{ + __pcm_buf_manager_t *pPcmBufManager; + __audio_enc_inf_t *AudioBsEncInf; + __com_internal_prameter_t *EncoderCom; + int Encinitedflag; + + int (*EncInit)(struct __AudioENC_AC320 *p); + int (*EncFrame)(struct __AudioENC_AC320 *p,char *OutBuffer,int *OutBuffLen); + int (*EncExit)(struct __AudioENC_AC320 *p); + +}AudioEnc_AC320; + +extern struct __AudioENC_AC320 *EncInit(void); +extern int EncExit(struct __AudioENC_AC320 *p); + +struct __AudioENC_AC320 *AudioMP3ENCEncInit(void); +int AudioMP3ENCEncExit(struct __AudioENC_AC320 *p); + +//Ҫϲģʵֵĺ +extern int GetPcmDataSize(__pcm_buf_manager_t *pPcmMan); +extern int ReadPcmDataForEnc(void *pBuf, int uGetLen, __pcm_buf_manager_t *pPcmMan); + +#endif /* _AENC_SW_LIB_H_ */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/amrencApi.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/amrencApi.h new file mode 100644 index 0000000000..140bb09f13 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/amrencApi.h @@ -0,0 +1,18 @@ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __AMR_ENC_LIB_API__ +#define __AMR_ENC_LIB_API__ + +#include + +struct __AudioENC_AC320 *AudioAMRENCEncInit(void); +int AudioAMRENCEncExit(struct __AudioENC_AC320 *p); + +#endif // __AMR_ENC_LIB_API__ + +#ifdef __cplusplus +} +#endif diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/config.mk b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/config.mk new file mode 100644 index 0000000000..5013b0ae1a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/config.mk @@ -0,0 +1,140 @@ +######## Config for Your platform ########### +# You can choose follows for osplaform +#OS_LINUX +#OS_ANDROID_4_4 +#OS_ANDROID_5_0 +#OS_ANDROID_6_0 + +# You can choose follows for osplaform log level +#OPTION_LOG_LEVEL_CLOSE +#OPTION_LOG_LEVEL_ERROR +#OPTION_LOG_LEVEL_WARNING +#OPTION_LOG_LEVEL_DEFAULT +#OPTION_LOG_LEVEL_DETAIL + +OS_PLATFORM = OS_LINUX +CONFIG_LOG_LEVEL = OPTION_LOG_LEVEL_DEFAULT +OS_CHECK_MEMORY_CONFIG = false +OS_DEBUG_CONFIG = false +USE_IP_PROTECTION = false + + +######## Config for Your compile tool ######## +# You can choose follows for your compile tools +#OPTION_CC_GNUEABIHF +#OPTION_CC_GNUEABI +#OPTION_CC_ARM_GNUEABI +#OPTION_CC_ARM_OPENWRT_UCLIBCGNUEABI +#OPTION_CC_ARM_OPENWRT_MUSLGNUEABI +#OPTION_CC_UCLIBC_ARM926_STATIC +#OPTION_CC_X86_ANDROID +#OPTION_CC_AARCH64_OPENWRT_MUSL + +CONFIG_CC = OPTION_CC_GNUEABI + +ifeq ($(CONFIG_CC), OPTION_CC_GNUEABI) + +########## set compile tool chains to be arm-linux-gnueabihf- set. +CC = arm-linux-gnueabi-gcc +CPP = arm-linux-gnueabi-g++ +STRIP = arm-linux-gnueabi-strip +AR = arm-linux-gnueabi-ar +AS = arm-linux-gnueabi-as +LD = arm-linux-gnueabi-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_AARCH64_OPENWRT_MUSL) + +########## set compile tool chains to be arm-linux-gnueabihf- set. +CC = aarch64-openwrt-linux-musl-gcc +CPP = aarch64-openwrt-linux-musl-g++ +STRIP = aarch64-openwrt-linux-musl-strip +AR = aarch64-openwrt-linux-musl-ar +AS = aarch64-openwrt-linux-musl-as +LD = aarch64-openwrt-linux-musl-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_GNUEABIHF) + +########## set compile tool chains to be arm-linux-gnueabihf- set. +CC = arm-linux-gnueabihf-gcc +CPP = arm-linux-gnueabihf-g++ +STRIP = arm-linux-gnueabihf-strip +AR = arm-linux-gnueabihf-ar +AS = arm-linux-gnueabihf-as +LD = arm-linux-gnueabihf-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_GNUEABI) + +# set compile tool chains to be arm-none-linux-gnueabi- set. +CC = arm-none-linux-gnueabi-gcc +CPP = arm-none-linux-gnueabi-g++ +STRIP = arm-none-linux-gnueabi-strip +AR = arm-none-linux-gnueabi-ar +AS = arm-none-linux-gnueabi-as +LD = arm-none-linux-gnueabi-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_ARM_GNUEABI) + +# set compile tool chains to be arm-linux-gnueabi- set. +CC = arm-linux-gnueabi-gcc +CPP = arm-linux-gnueabi-g++ +STRIP = arm-linux-gnueabi-strip +AR = arm-linux-gnueabi-ar +AS = arm-linux-gnueabi-as +LD = arm-linux-gnueabi-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_ARM_OPENWRT_UCLIBCGNUEABI) + +# set compile tool chains to be arm-openwrt-linux-uclibcgnueabi- set. +CC = arm-openwrt-linux-uclibcgnueabi-gcc +CPP = arm-openwrt-linux-uclibcgnueabi-g++ +STRIP = arm-openwrt-linux-uclibcgnueabi-strip +AR = arm-openwrt-linux-uclibcgnueabi-ar +AS = arm-openwrt-linux-uclibcgnueabi-as +LD = arm-openwrt-linux-uclibcgnueabi-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_ARM_OPENWRT_MUSLGNUEABI) + +# set compile tool chains to be arm-openwrt-linux-muslgnueabi- set. +CC = arm-openwrt-linux-muslgnueabi-gcc +CPP = arm-openwrt-linux-muslgnueabi-g++ +STRIP = arm-openwrt-linux-muslgnueabi-strip +AR = arm-openwrt-linux-muslgnueabi-ar +AS = arm-openwrt-linux-muslgnueabi-as +LD = arm-openwrt-linux-muslgnueabi-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_UCLIBC_ARM926_STATIC) + +# set compile tool chains to be arm-buildroot-linux-uclibcgnueabi- set. +CC = arm-buildroot-linux-uclibcgnueabi-gcc +CPP = arm-buildroot-linux-uclibcgnueabi-g++ +STRIP = arm-buildroot-linux-uclibcgnueabi-strip +AR = arm-buildroot-linux-uclibcgnueabi-ar +AS = arm-buildroot-linux-uclibcgnueabi-as +LD = arm-buildroot-linux-uclibcgnueabi-ld +endif + +ifeq ($(CONFIG_CC), OPTION_CC_X86_ANDROID) + +# set compile tool chains to be i686-linux-android- set. +CC = i686-linux-android-gcc +CPP = i686-linux-android-g++ +STRIP = i686-linux-android-strip +AR = i686-linux-android-ar +AS = i686-linux-android-as +LD = i686-linux-android-ld +endif +########## set out lib path +LIBPATH = /home/${USER}/libs_for_linux + +########## set build objects path +BUILDPATH = ./build + +########## set extra compile flag +EXTRA_FLAG = -g diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/include/aencoder.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/include/aencoder.h new file mode 100644 index 0000000000..8c23262c92 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/include/aencoder.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : aencoder.h + * Description : audio encoder api + * History : + * + */ + +#ifndef AUDIO_ENCODER_H +#define AUDIO_ENCODER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMR_ENCODER (1) +#define PCM_ENCODER (1) +#define OTHER_ENCODER (0) + +typedef enum __AUDIO_ENC_RESULT +{ + ERR_AUDIO_ENC_ABSEND = -2, + ERR_AUDIO_ENC_UNKNOWN = -1, + ERR_AUDIO_ENC_NONE = 0, //decode successed, no error + ERR_AUDIO_ENC_PCMUNDERFLOW = 1, //pcm data is underflow + ERR_AUDIO_ENC_OUTFRAME_UNDERFLOW = 2, //out frame buffer is underflow. + ERR_AUDIO_ENC_ +} __audio_enc_result_t; + + +enum AUDIO_ENCODER_TYPE +{ +#if OTHER_ENCODER + AUDIO_ENCODER_AAC_TYPE, + AUDIO_ENCODER_LPCM_TYPE, //only used by mpeg2ts + AUDIO_ENCODER_MP3_TYPE, +#endif +#if PCM_ENCODER + AUDIO_ENCODER_PCM_TYPE, +#endif +#if AMR_ENCODER + AUDIO_ENCODER_AMR_TYPE, +#endif +}; + +typedef enum AUDIO_ENCODER_TYPE AUDIO_ENCODER_TYPE; + +typedef struct AudioEncConfig +{ + AUDIO_ENCODER_TYPE nType; + int nInSamplerate; //fs + int nInChan; //pcm chan 1:mon 2:stereo + int nBitrate; //bs + int nSamplerBits; //only for 16bits + int nOutSamplerate; //fs,now OutSamplerate must equal InSamplerate + int nOutChan; // chan + + //for aac: 0:add head,1:raw data; + //for pcm: 2:mpegTs pcm(big endian), + //other: common pcm(little endian) + int nFrameStyle; +}AudioEncConfig; + +typedef void* AudioEncoder; + +AudioEncoder* CreateAudioEncoder(); +void DestroyAudioEncoder(AudioEncoder* pEncoder); +int InitializeAudioEncoder(AudioEncoder *pEncoder, AudioEncConfig *pConfig); +int ResetAudioEncoder(AudioEncoder* pEncoder); +int EncodeAudioStream(AudioEncoder *pEncoder); +int WriteAudioStreamBuffer(AudioEncoder *pEncoder, char* pBuf, int len); +int RequestAudioFrameBuffer(AudioEncoder *pEncoder, char **pOutBuf, + unsigned int *size, long long *pts, int *bufId); +int ReturnAudioFrameBuffer(AudioEncoder *pEncoder, char *pOutBuf, + unsigned int size, long long pts, int bufId); + + +#ifdef __cplusplus +} +#endif + +#endif // AUDIO_ENC_API_H diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/include/log.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/include/log.h new file mode 100644 index 0000000000..8235a22b45 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/include/log.h @@ -0,0 +1,108 @@ +#ifndef LOG_H +#define LOG_H +#ifndef LOG_TAG +#define LOG_TAG "AllwinnerAudioCodec" +#endif + +#include "cdx_malloc_dbg.h" + +#define OPTION_LOG_LEVEL_WARNING + +#if 0 +#ifdef OS_ANDROID + #include + + #define LOG_LEVEL_ERROR ANDROID_LOG_ERROR + #define LOG_LEVEL_WARNING ANDROID_LOG_WARN + #define LOG_LEVEL_INFO ANDROID_LOG_INFO + #define LOG_LEVEL_VERBOSE ANDROID_LOG_VERBOSE + #define LOG_LEVEL_DEBUG ANDROID_LOG_DEBUG + + #define AWLOG(level, fmt, arg...) \ + LOG_PRI(level, LOG_TAG, "<%s:%u>: "fmt, __FUNCTION__, __LINE__, ##arg) + +#elif (defined OS_LINUX) + #include + #include + + #define LOG_LEVEL_ERROR "error " + #define LOG_LEVEL_WARNING "warning" + #define LOG_LEVEL_INFO "info " + #define LOG_LEVEL_VERBOSE "verbose" + #define LOG_LEVEL_DEBUG "debug " + + #define AWLOG(level, fmt, arg...) \ + printf("%s: %s <%s:%u>: "fmt"\n", level, LOG_TAG, __FUNCTION__, __LINE__, ##arg) +#else + #error "invalid configuration of os." +#endif +#endif + + + + #ifndef LOG_LEVEL_ERROR + #define LOG_LEVEL_ERROR "error " + #endif + #ifndef LOG_LEVEL_WARNING + #define LOG_LEVEL_WARNING "warning" + #endif + #ifndef LOG_LEVEL_INFO + #define LOG_LEVEL_INFO "info " + #endif + #ifndef LOG_LEVEL_VERBOSE + #define LOG_LEVEL_VERBOSE "verbose" + #endif + #ifndef LOG_LEVEL_DEBUG + #define LOG_LEVEL_DEBUG "debug " + #endif + +int wrap_printf(const char *fmt, ...); +#define AWLOG(level, fmt, arg...) \ + wrap_printf("%s: %s <%s:%u>: "fmt"\n", level, LOG_TAG, __func__, __LINE__, ##arg) + +void __printf_time(const char *f, unsigned int l); +#define printf_time() __printf_time(__func__, __LINE__) + +#define logd(fmt, arg...) //AWLOG(LOG_LEVEL_DEBUG, fmt, ##arg) + +#ifdef OPTION_LOG_LEVEL_CLOSE + +#define loge(fmt, arg...) +#define logw(fmt, arg...) +#define logi(fmt, arg...) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_ERROR) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) +#define logi(fmt, arg...) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_WARNING) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_DEFAULT) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) AWLOG(LOG_LEVEL_INFO, fmt, ##arg) +#define logv(fmt, arg...) + +#elif (defined OPTION_LOG_LEVEL_DETAIL) + +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m"fmt"\033[0m", ##arg) +#define logw(fmt, arg...) AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) AWLOG(LOG_LEVEL_INFO, fmt, ##arg) +#define logv(fmt, arg...) AWLOG(LOG_LEVEL_VERBOSE, fmt, ##arg) + +#else + #error "invalid configuration of debug level." +#endif + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/mp3encApi.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/mp3encApi.h new file mode 100644 index 0000000000..c0be828b1f --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/mp3encApi.h @@ -0,0 +1,18 @@ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __MP3_ENC_LIB_API__ +#define __MP3_ENC_LIB_API__ + +#include + +extern struct __AudioENC_AC320 *AudioMP3ENCEncInit(void); +extern int AudioMP3ENCEncExit(struct __AudioENC_AC320 *p); + +#endif // __MP3_ENC_LIB_API__ + +#ifdef __cplusplus +} +#endif diff --git a/platform/mcu/xr871/src/cedarx/CdxEncPlugin/pcm_enc.h b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/pcm_enc.h new file mode 100644 index 0000000000..557cdc7e2a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/CdxEncPlugin/pcm_enc.h @@ -0,0 +1,16 @@ +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PCM_ENC_H +#define PCM_ENC_H +#include "aenc_sw_lib.h" + +extern struct __AudioENC_AC320 *AudioPCMEncInit(); +extern int AudioPCMEncExit(struct __AudioENC_AC320 *p); + +#endif /* PCM_ENC_H */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/mcu/xr871/src/cedarx/Makefile b/platform/mcu/xr871/src/cedarx/Makefile new file mode 100644 index 0000000000..d573828e41 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/Makefile @@ -0,0 +1,28 @@ +# +# Rules for building library +# + +# ---------------------------------------------------------------------------- +# common rules +# ---------------------------------------------------------------------------- +ROOT_PATH := ../.. + +include $(ROOT_PATH)/gcc.mk + +# ---------------------------------------------------------------------------- +# library and objects +# ---------------------------------------------------------------------------- +LIBS := libcedarx.a + +DIRS := $(shell find . -maxdepth 4 -type d) +DIRS += . + +SRCS := $(basename $(foreach dir,$(DIRS),$(wildcard $(dir)/*.[csS]))) + +OBJS := $(addsuffix .o,$(SRCS)) + +# extra include path +INCLUDE_PATHS += $(foreach dir, $(DIRS), -I$(dir)) + +# library make rules +include $(LIB_MAKE_RULES) diff --git a/platform/mcu/xr871/src/cedarx/awrecorder/AudioEncodeComponent.h b/platform/mcu/xr871/src/cedarx/awrecorder/AudioEncodeComponent.h new file mode 100644 index 0000000000..97756001f3 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/awrecorder/AudioEncodeComponent.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : AudioEncodeComponent.h + * Description : AudioEncodeComponent + * History : + * + */ + +#ifndef AUDIO_ENCODE_COMPONENT_H +#define AUDIO_ENCODE_COMPONENT_H + +#include "aencoder.h" +#include "awencoder.h" + +typedef void* AudioEncodeComp; + + +enum AUDIOENCODERNOTIFY +{ + AUDIO_ENCODE_NOTIFY_ERROR, + AUDIO_ENCODE_NOTIFY_CRASH, + AUDIO_ENCODE_NOTIFY_EOS, +}; + +typedef int (*AudioEncodeCallback)(void* pUserData, int eMessageId, void* param); +AudioEncodeComp* AudioEncodeCompCreate(); +int AudioEncodeCompInit(AudioEncodeComp* p, AudioEncodeConfig* config); +void AudioEncodeCompDestory(AudioEncodeComp* p); +int AudioEncodeCompStart(AudioEncodeComp *p); +int AudioEncodeCompStop(AudioEncodeComp *p); +int AudioEncodeCompReset(AudioEncodeComp* p); +int AudioEncodeCompInputBuffer(AudioEncodeComp *p, AudioInputBuffer *buf); +int AudioEncodeCompRequestBuffer(AudioEncodeComp *p, AudioEncOutBuffer *bufInfo); +int AudioEncodeCompReturnBuffer(AudioEncodeComp *p, AudioEncOutBuffer *bufInfo); +int AudioEncodeCompSetCallback(AudioEncodeComp *p, AudioEncodeCallback notifier, void* pUserData); +#endif diff --git a/platform/mcu/xr871/src/cedarx/awrecorder/EncDataComponent.h b/platform/mcu/xr871/src/cedarx/awrecorder/EncDataComponent.h new file mode 100644 index 0000000000..a3d3869a36 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/awrecorder/EncDataComponent.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : EncDataComponent.h + * Description : EncDataComponent + * History : + * + */ + +#ifndef __MUX_COMP_H__ +#define __MUX_COMP_H__ + +#include "CdxMuxer.h" +#include "AudioEncodeComponent.h" +//#include "VideoEncodeComponent.h" + +enum MUXERNOTIFY +{ + ENCDATA_NOTIFY_ERROR, + ENCDATA_NOTIFY_ENCODE_PACKET, +}; + +typedef void* EncDataComp; +typedef int (*MuxerCallback)(void* pUserData, int eMessageId, void* param); + +EncDataComp* EncDataCompCreate(void * app); +int EncDataCompInit(EncDataComp *v,VideoEncodeConfig *videoConfig, + AudioEncodeConfig *audioConfig, EncDataCallBackOps *ops); +void EncDataCompDestory(EncDataComp* p); +int EncDataCompStart(EncDataComp *p); +int EncDataCompStop(EncDataComp *p); +int EncDataCompReset(EncDataComp *p); +int EncDataCompSetAudioEncodeComp(EncDataComp *p, AudioEncodeComp* pAudioEncoder); +#if VIDEO_SUPPORT +int EncDataCompSetVideoEncodeComp(EncDataComp *p, VideoEncodeComp* pVideoEncoder); +#endif +int EncDataCompSetCallback(EncDataComp* v, MuxerCallback callback, void* pUserData); + +#endif /* __VIDEO_RESIZER_MUXER_H__ */ + diff --git a/platform/mcu/xr871/src/cedarx/awrecorder/Makefile.am b/platform/mcu/xr871/src/cedarx/awrecorder/Makefile.am new file mode 100644 index 0000000000..160ebb9ba6 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/awrecorder/Makefile.am @@ -0,0 +1,31 @@ + +include $(top_srcdir)/Makefile.inc + +lib_LTLIBRARIES = libawrecorder.la + +libawrecorder_la_SOURCES = AudioEncodeComponent.c \ + awencoder.c \ + EncDataComponent.c \ + VideoEncodeComponent.c + +libawrecorder_la_CFLAGS = $(CFLAGS_CDXG) +libawrecorder_la_CPPFLAGS = $(CPPFLAGS_CDXG) +LOCAL_INCLUDE = -I$(top_srcdir) \ + -I$(top_srcdir)/libcore/include \ + -I$(top_srcdir)/libcore/base/include \ + -I$(top_srcdir)/libcore/muxer/include \ + -I$(top_srcdir)/external/include/aencoder \ + -I$(top_srcdir)/../libcedarc/include + +libawrecorder_la_CFLAGS += $(LOCAL_INCLUDE) +libawrecorder_la_CPPFLAGS += $(LOCAL_INCLUDE) + +libawrecorder_la_LDFLAGS = $(LDFLAGS_CDXG) + +libawrecorder_la_LIBADD = \ + $(top_srcdir)/libcore/base/libcdx_base.la \ + $(top_srcdir)/libcore/muxer/base/libcdx_muxer.la + +LOCAL_LIB = -lpthread -dl -lcdc_vencoder -laencoder -lcdc_memory +libawrecorder_la_LDFLAGS += $(LOCAL_LIB) + diff --git a/platform/mcu/xr871/src/cedarx/awrecorder/awencoder.h b/platform/mcu/xr871/src/cedarx/awrecorder/awencoder.h new file mode 100644 index 0000000000..c3c1f36ffc --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/awrecorder/awencoder.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : awencoder.h + * Description : encoder + * History : + * + */ + +#ifndef __AW_RECORDER_H__ +#define __AW_RECORDER_H__ + +//#include +//#include +#include +//#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMR_ENCODER (1) +#define PCM_ENCODER (1) +#define OTHER_ENCODER (0) + +typedef void* AwEncoder; + +typedef enum AwEncoderIndexType +{ + AwEncoder_SetFrameRate = 0x0, + AwEncoder_SetBitRate, + +}AwEncoderIndexType; + +enum ERECORDERINTERNALNOTIFY //* +{ + AWENCODER_VIDEO_ENCODER_NOTIFY_STREAM_UNDERFLOW = 32, + AWENCODER_VIDEO_ENCODER_NOTIFY_CRASH, + AWENCODER_VIDEO_ENCODER_NOTIFY_EOS, + AWENCODER_VIDEO_ENCODER_NOTIFY_OUT_BUFFER, + AWENCODER_VIDEO_ENCODER_NOTIFY_RETURN_BUFFER, + + AWENCODER_AUDIO_ENCODER_NOTIFY_STREAM_UNDERFLOW = 96, + AWENCODER_AUDIO_ENCODER_NOTIFY_CRASH, + AWENCODER_AUDIO_ENCODER_NOTIFY_EOS, + AWENCODER_AUDIO_ENCODER_NOTIFY_OUT_BUFFER, + + AWENCODER_MUXER_NOTIFY_FIRST_FRAME = 128, + AWENCODER_MUXER_NOTIFY_EOS, + AWENCODER_MUXER_NOTIFY_PTS_AND_CACHETIME, +}; + +typedef enum VIDEO_ENCODE_TYPE +{ + VIDEO_ENCODE_H264, + VIDEO_ENCODE_JPEG, +}VIDEO_ENCODE_TYPE; + +typedef enum AUDIO_ENCODE_TYPE +{ +#if PCM_ENCODER + AUDIO_ENCODE_PCM_TYPE, +#endif +#if OTHER_ENCODER + AUDIO_ENCODE_AAC_TYPE, + AUDIO_ENCODE_LPCM_TYPE, //only used by mpeg2ts + AUDIO_ENCODE_MP3_TYPE, +#endif +#if AMR_ENCODER + AUDIO_ENCODE_AMR_TYPE, +#endif +}AUDIO_ENCODE_TYPE; + +typedef struct AudioEncodeConfig +{ + AUDIO_ENCODE_TYPE nType; + int nInSamplerate; //??fs + int nInChan; //??pcm chan 1:mon 2:stereo + int nBitrate; //bs + int nSamplerBits; //only for 16bits + int nOutSamplerate; //?3?fs,now OutSamplerate must equal InSamplerate + int nOutChan; //???3? chan + //for aac: 0:add head,1:raw data; + //for pcm: 2:mpegTs pcm(big endian), + //other: common pcm(little endian) + int nFrameStyle; +}AudioEncodeConfig; + +typedef struct VideoEncodeConfig +{ + VIDEO_ENCODE_TYPE nType; + int nFrameRate; + int nBitRate; + int nOutWidth; + int nOutHeight; + int nSrcFrameRate; + int nSrcWidth; + int nSrcHeight; + int bUsePhyBuf; +}VideoEncodeConfig; + +typedef struct VideoInputBuffer +{ + unsigned char* pData; //virtual data buff + int nLen; //data len + long long nPts; //pts + + unsigned long nID; + unsigned char* pAddrPhyY; + unsigned char* pAddrPhyC; +}VideoInputBuffer; + +typedef struct AudioInputBuffer +{ + char *pData; //data buff + int nLen; //data len + long long nPts; //pts +}AudioInputBuffer; + +typedef struct VideoOutBuffer +{ + unsigned int nSize0; + unsigned int nSize1; + unsigned char* pData0; + unsigned char* pData1; +}VideoOutBuffer; + +typedef struct AudioEncOutBuffer +{ + char *pBuf; + unsigned int len; + long long pts; + int bufId; +}AudioEncOutBuffer; + +typedef struct EncDataCallBackOps +{ + int (*onVideoDataEnc)(void *app,CdxMuxerPacketT *buff); + int (*onAudioDataEnc)(void *app,CdxMuxerPacketT *buff); +} EncDataCallBackOps; + +typedef void (*EncoderNotifyCallback)(void* pUserData, int msg, void* param); + +AwEncoder* AwEncoderCreate(void * app); +void AwEncoderDestory(AwEncoder* p); +int AwEncoderInit(AwEncoder* p, + VideoEncodeConfig *videoConfig, + AudioEncodeConfig *audioConfig, + EncDataCallBackOps *ops); + +int AwEncoderGetExtradata(AwEncoder* v, unsigned char** buf, unsigned int* length); +int AwEncoderSetParamete(AwEncoder* p, AwEncoderIndexType nIndexType, void* para); +int AwEncoderStart(AwEncoder* p); +int AwEncoderStop(AwEncoder* p); +int AwEncoderReset(AwEncoder* p); + +int AwEncoderWriteYUVdata(AwEncoder* p, VideoInputBuffer* buf); +int AwEncoderWritePCMdata(AwEncoder* p, AudioInputBuffer* buf); + +int AwEncoderSetNotifyCallback(AwEncoder* p, + EncoderNotifyCallback notifier, + void* pUserData); + +#ifdef __cplusplus +} +#endif + +#endif /* __RECORDER_H__ */ + diff --git a/platform/mcu/xr871/src/cedarx/base/include/AwMessageQueue.h b/platform/mcu/xr871/src/cedarx/base/include/AwMessageQueue.h new file mode 100644 index 0000000000..922e6e65f8 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/AwMessageQueue.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxMessageQueue.h + * Description : message queue + * History : + * + */ + +#ifndef MESSAGE_QUEUE_H +#define MESSAGE_QUEUE_H + +#include +//#include +#include "pthread.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct MessageQueueContext AwMessageQueue; + +#ifndef uintptr_t +typedef size_t uintptr_t; +#endif + +typedef struct AwMessage AwMessage; +typedef void (*msgHandlerT)(AwMessage *msg, void *arg); + +/* Define your own struct AwMessage and put AWMESSAGE_COMMON_MEMBERS at the + * beginning + */ +#define AWMESSAGE_COMMON_MEMBERS \ + int messageId; \ + msgHandlerT execute; \ + +/** + * @param nMaxMessageNum How many messages the message queue can hold + * @param pName The name of the message queue which is used in log output + * @param nMessageSize sizeof(struct AwMessage) + */ +AwMessageQueue* AwMessageQueueCreate__(int nMaxMessageNum, const char* pName, + size_t nMessageSize); +#define AwMessageQueueCreate(nMaxMessageNum, pName) \ + AwMessageQueueCreate__(nMaxMessageNum, pName, sizeof(AwMessage)) + +void AwMessageQueueDestroy(AwMessageQueue* mq); + +int AwMessageQueuePostMessage(AwMessageQueue* mq, AwMessage* m); + +int AwMessageQueueWaitMessage(AwMessageQueue* mq, int64_t timeout); + +int AwMessageQueueGetMessage(AwMessageQueue* mq, AwMessage* m); + +int AwMessageQueueTryGetMessage(AwMessageQueue* mq, AwMessage* m, int64_t timeout); + +int AwMessageQueueFlush(AwMessageQueue* mq); + +int AwMessageQueueGetCount(AwMessageQueue* mq); + +//* define a semaphore timedwait method for common use. +int SemTimedWait(sem_t* sem, int64_t time_ms); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/AwPool.h b/platform/mcu/xr871/src/cedarx/base/include/AwPool.h new file mode 100644 index 0000000000..225bbd6207 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/AwPool.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : AwPool.h + * Description : Pool + * History : + * + */ + +#ifndef AW_POOL_H +#define AW_POOL_H + +#include +#include + +typedef struct AwPoolS AwPoolT; + +#define Palloc(pool, size) \ + AwPalloc(pool, size, __FILE__, __LINE__) + +#define Pfree(pool, p) \ + AwPfree(pool, p) + +#define Pstrdup(pool, str) \ + AwStrDup(pool, str, __FILE__, __LINE__) + +#define Prealloc(pool, p, size) \ + AwRealloc(pool, p, size, __FILE__, __LINE__) + +#ifdef __cplusplus +extern "C" +{ +#endif + +AwPoolT *__AwPoolCreate(AwPoolT *father, char *file, int line); + +#define AwPoolCreate(father) __AwPoolCreate(father, __FILE__, __LINE__) + +void AwPoolDestroy(AwPoolT *pool); + +void *AwPalloc(AwPoolT *pool, int size, char *file, int line); + +void AwPfree(AwPoolT *pool, void *p); + +void AwPoolReset(void); + +static inline char *AwStrDup(AwPoolT *pool, const char *str, char *file, int line) +{ + char *ret = NULL; + int strLen = 0; +// CDX_CHECK(str); + + strLen = strlen(str); + + ret = (char *)AwPalloc(pool, strLen + 1, file, line); + strcpy(ret, str); + ret[strLen] = 0; + return ret; +} + +void *AwRealloc(AwPoolT *pool, void *p, int size, char *file, int line); + +#ifdef __cplusplus +} +#endif + +#endif /* AW_POOL_H */ + diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxAtomic.h b/platform/mcu/xr871/src/cedarx/base/include/CdxAtomic.h new file mode 100644 index 0000000000..5c086f12f5 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxAtomic.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxAtomic.h + * Description : Atomic + * History : + * + */ + +#ifndef CDX_ATOMIC_H +#define CDX_ATOMIC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + volatile cdx_ssize counter; +} cdx_atomic_t; + +/*ü+ 1 ؽֵ*/ +static inline cdx_int32 CdxAtomicInc(cdx_atomic_t *ref) +{ + return __sync_add_and_fetch(&ref->counter, 1L); +} + +static inline cdx_int32 CdxAtomicAdd(cdx_atomic_t *ref, cdx_ssize val) +{ + return __sync_add_and_fetch(&ref->counter, val); +} + +/*ü- 1 ؽֵ*/ +static inline cdx_int32 CdxAtomicDec(cdx_atomic_t *ref) +{ + return __sync_sub_and_fetch(&ref->counter, 1L); +} + +static inline cdx_int32 CdxAtomicSub(cdx_atomic_t *ref, cdx_ssize val) +{ + return __sync_sub_and_fetch(&ref->counter, val); +} + +/*üΪvalǰֵ*/ +static inline cdx_int32 CdxAtomicSet(cdx_atomic_t *ref, cdx_ssize val) +{ + return __sync_lock_test_and_set(&ref->counter, val); +} + +/*ȡüֵ*/ +static inline cdx_int32 CdxAtomicRead(cdx_atomic_t *ref) +{ + return __sync_or_and_fetch(&ref->counter, 0L); +} + +static inline cdx_bool CdxAtomicCAS(cdx_atomic_t *ref, cdx_ssize oldVal, cdx_ssize newVal) +{ + return __sync_bool_compare_and_swap(&ref->counter, oldVal, newVal); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxBase64.h b/platform/mcu/xr871/src/cedarx/base/include/CdxBase64.h new file mode 100644 index 0000000000..cb96dedcc1 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxBase64.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxBase64.h + * Description : Base64 + * History : + * + */ + +#ifndef CDX_BASE_64_H +#define CDX_BASE_64_H +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +CdxBufferT *CdxDecodeBase64(AwPoolT *pool, const cdx_char *s); + +cdx_char *CdxEncodeBase64(AwPoolT *pool, const void *_data, cdx_size size); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxBinary.h b/platform/mcu/xr871/src/cedarx/base/include/CdxBinary.h new file mode 100644 index 0000000000..620a3c83b5 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxBinary.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxBinary.h + * Description : Binary + * History : + * + */ + +#ifndef CDX_BINARY_H +#define CDX_BINARY_H +#include + +static inline cdx_uint32 GetU8(const cdx_uint8 *data) +{ + return (cdx_uint32)(*data); +} + +static inline cdx_uint32 GetLE16(const cdx_uint8 *data) +{ + return GetU8(data) | (GetU8(data + 1) << 8); +} + +static inline cdx_uint32 GetLE32(const cdx_uint8 *data) +{ + return GetLE16(data) | (GetLE16(data + 2) << 16); +} + +static inline cdx_uint64 GetLE64(const cdx_uint8 *data) +{ + return ((cdx_uint64)GetLE32(data)) | (((cdx_uint64)GetLE32(data + 4)) << 32); +} + +static inline cdx_uint32 GetBE16(const cdx_uint8 *data) +{ + return (GetU8(data) << 8) | GetU8(data + 1); +} + +static inline cdx_uint32 GetBE32(const cdx_uint8 *data) +{ + return (GetBE16(data) << 16) | GetBE16(data + 2); +} + +static inline cdx_uint64 GetBE64(const cdx_uint8 *data) +{ + return (((cdx_uint64)GetBE32(data)) << 32) | ((cdx_uint64)GetBE32(data + 4)); +} + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxBitReader.h b/platform/mcu/xr871/src/cedarx/base/include/CdxBitReader.h new file mode 100644 index 0000000000..8f9def153d --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxBitReader.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxBitReader.h + * Description : BitReader + * History : + * + */ + +#ifndef CDX_BIT_READER_H +#define CDX_BIT_READER_H + +#include + +typedef struct CdxBitReaderS CdxBitReaderT; + +struct CdxBitReaderOpsS +{ + void (*destroy)(CdxBitReaderT *); + + cdx_uint32 (*getBits)(CdxBitReaderT *, cdx_uint32); + + void (*skipBits)(CdxBitReaderT *, cdx_uint32); + + void (*putBits)(CdxBitReaderT *, cdx_uint32, cdx_uint32); + + cdx_uint32 (*numBitsLeft)(CdxBitReaderT *) ; + + const cdx_uint8 *(*data)(CdxBitReaderT *); +}; + +struct CdxBitReaderS +{ + struct CdxBitReaderOpsS *ops; +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +CdxBitReaderT *CdxBitReaderCreate(const cdx_uint8 *data, cdx_uint32 size); +void CdxBitReaderDestroy(struct CdxBitReaderS *br); +cdx_uint32 CdxBitReaderGetBits(struct CdxBitReaderS *br, cdx_uint32 n); +void CdxBitReaderSkipBits(struct CdxBitReaderS *br, cdx_uint32 n); +void CdxBitReaderPutBits(struct CdxBitReaderS *br, cdx_uint32 x, cdx_uint32 n); +cdx_uint32 CdxBitReaderNumBitsLeft(struct CdxBitReaderS *br) ; +const cdx_uint8 *CdxBitReaderData(struct CdxBitReaderS *br); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxBuffer.h b/platform/mcu/xr871/src/cedarx/base/include/CdxBuffer.h new file mode 100644 index 0000000000..e8c0b2185c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxBuffer.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxBuffer.h + * Description : Buffer + * History : + * + */ + +#ifndef CDX_BUFFER_H +#define CDX_BUFFER_H +#include +#include +#include +#include +#include + +/* + *溯ʧܵʱ򣬶Ӧbuf ǺϷ + *ԼʹãȻҲҪͷš + */ + +struct CdxBufferItemS +{ + CdxBufferT *val; + CdxListNodeT node; +}; + +struct CdxBufferOpsS +{ + CdxBufferT *(*incRef)(CdxBufferT *); + void (*decRef)(CdxBufferT *); + cdx_uint8 *(*getData)(CdxBufferT *); + cdx_uint8 *(*getBase)(CdxBufferT *); + cdx_uint32 (*getSize)(CdxBufferT *); + void (*append)(CdxBufferT *, const cdx_uint8 * /*data*/, cdx_uint32 /*len*/ ); + void (*insert)(CdxBufferT *, const cdx_uint8 * /*data*/, cdx_uint32 /*len*/ ); + void (*setRange)(CdxBufferT *, cdx_uint32 /*offset*/, cdx_uint32/*len*/); + void (*seekRange)(CdxBufferT *, cdx_int32 /*left*/, cdx_int32/*right*/); + CdxMetaT *(*getMeta)(CdxBufferT *); +}; + +struct CdxBufferS +{ + struct CdxBufferOpsS *ops; +}; + +static inline CdxBufferT *CdxBufferIncRef(CdxBufferT *buf) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->incRef); + return buf->ops->incRef(buf); +} + +static inline void CdxBufferDecRef(CdxBufferT *buf) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->decRef); + return buf->ops->decRef(buf); +} + +static inline cdx_uint8 *CdxBufferGetData(CdxBufferT *buf) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->getData); + return buf->ops->getData(buf); +} + +static inline cdx_uint8 *CdxBufferGetBase(CdxBufferT *buf) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->getBase); + return buf->ops->getBase(buf); +} + +static inline cdx_uint32 CdxBufferGetSize(CdxBufferT *buf) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->getSize); + return buf->ops->getSize(buf); +} + +static inline void CdxBufferAppend(CdxBufferT *buf, const cdx_uint8 *data, + cdx_uint32 len) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->append); + buf->ops->append(buf, data, len); +} + +static inline void CdxBufferInsert(CdxBufferT *buf, + cdx_uint8 *data, cdx_uint32 len) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->insert); + buf->ops->insert(buf, data, len); +} + +static inline CdxMetaT *CdxBufferGetMeta(CdxBufferT *buf) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->getMeta); + return buf->ops->getMeta(buf); +} + +static inline void CdxBufferSetRange(CdxBufferT *buf, + cdx_uint32 offset, cdx_uint32 len) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->setRange); + buf->ops->setRange(buf, offset, len); +} + +static inline void CdxBufferSeekRange(CdxBufferT *buf, + cdx_int32 left, cdx_int32 right) +{ + CDX_CHECK(buf); + CDX_CHECK(buf->ops); + CDX_CHECK(buf->ops->seekRange); + buf->ops->seekRange(buf, left, right); +} + +#define CdxBufferDump(buf) \ + CDX_BUF_DUMP(CdxBufferGetData(buf), CdxBufferGetSize(buf)) + +#define CdxBufferSetInt32(buf, name, val) \ + CdxMetaSetInt32(CdxBufferGetMeta(buf), name, val) + +#define CdxBufferFindInt32(buf, name, pVal) \ + CdxMetaFindInt32(CdxBufferGetMeta(buf), name, pVal) + +#define CdxBufferRemoveInt32(buf, name) \ + CdxMetaRemoveInt32(CdxBufferGetMeta(buf), name) + +#define CdxBufferSetInt64(buf, name, val) \ + CdxMetaSetInt64(CdxBufferGetMeta(buf), name, val) + +#define CdxBufferFindInt64(buf, name, pVal) \ + CdxMetaFindInt64(CdxBufferGetMeta(buf), name, pVal) + +typedef CdxBufferT CdxStringT; + +#define CdxStringCreate(pool) \ + CdxBufferCreate(pool, 1024, NULL, 0) + +#define CdxStringDestroy(str) \ + CdxBufferDestroy(str) + +static inline void CdxStringAppend(CdxStringT *str, cdx_char *val) +{ + CDX_CHECK(val); + CdxBufferAppend(str, (cdx_uint8 *)(val), strlen(val) + 1); + CdxBufferSetRange(str, 0, CdxBufferGetSize(str) - 1); +} + +#define CdxStringGet(str) \ + (cdx_char *)CdxBufferGetData(str) + +#define CdxBufferCreate(pool, capacity, initData, len) \ + __CdxBufferCreate(pool, capacity, initData, len, __FILE__, __LINE__) + +#ifdef __cplusplus +extern "C" { +#endif + +CdxBufferT *__CdxBufferCreate(AwPoolT *pool, cdx_uint32 capacity, cdx_uint8 *initData, + cdx_uint32 len, char *file, int line); + +void CdxBufferDestroy(CdxBufferT *buf); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif // CDX_BUFFER_H diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxDebug.h b/platform/mcu/xr871/src/cedarx/base/include/CdxDebug.h new file mode 100644 index 0000000000..9471cd7509 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxDebug.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxDebug.h + * Description : Debug + * History : + * + */ + +#ifndef CDX_DEBUG_H +#define CDX_DEBUG_H +#include +#ifdef LINUX_PLATFORM +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef LINUX_PLATFORM +#define gettid() syscall(__NR_gettid) + +void CdxDumpThreadStack(pthread_t tid); + +void CdxCallStack(void); +#else + +static inline void CdxDumpThreadStack(pthread_t tid) { + +} + +static inline void CdxCallStack(pthread_t tid) { + +} +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxEnumCommon.h b/platform/mcu/xr871/src/cedarx/base/include/CdxEnumCommon.h new file mode 100644 index 0000000000..2735ee5664 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxEnumCommon.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxEnumCommon.h + * Description : helper for some public enum type + * History : + * + */ + +#ifndef CDX_ENUM_COMMON_H +#define CDX_ENUM_COMMON_H + +enum SPLIT_PUBLIC_ENUM_RANGE { + MEDIA_EVENT_VALID_RANGE_MIN = 0, + MEDIA_EVENT_VALID_RANGE_MAX = 255, + + PARSER_NOTIFY_VALID_RANGE_MIN = 256, + PARSER_NOTIFY_VALID_RANGE_MAX = 500, + + DEMUX_NOTIFY_VALID_RANGE_MIN = 512, + DEMUX_NOTIFY_VALID_RANGE_MAX = 1000, + + PLAYBACK_NOTIFY_VALID_RANGE_MIN = 1024, + PLAYBACK_NOTIFY_VALID_RANGE_MAX = 1500, + + SUBTITLE_CALLBACK_VALID_RANGE_MIN = 1600, + SUBTITLE_CALLBACK_VALID_RANGE_MAX = 2000, + + STREAM_EVENT_VALID_RANGE_MIN = 4096, + STREAM_EVENT_VALID_RANGE_MAX = 4500, +}; + +#define CHECK_MEDIA_EVENT_MAX_VALID(x) \ + typedef char MEDIA_EVENT_MAX_VALID[(int)MEDIA_EVENT_VALID_RANGE_MAX - (int)x]; + +#define CHECK_PARSER_NOTIFY_MAX_VALID(x) \ + typedef char PARSER_NOTIFY_MAX_VALID[(int)PARSER_NOTIFY_VALID_RANGE_MAX - (int)x]; + +#define CHECK_DEMUX_NOTIFY_MAX_VALID(x) \ + typedef char DEMUX_NOTIFY_MAX_VALID[(int)DEMUX_NOTIFY_VALID_RANGE_MAX - (int)x]; + +#define CHECK_PLAYBACK_NOTIFY_MAX_VALID(x) \ + typedef char PLAYBACK_NOTIFY_MAX_VALID[(int)PLAYBACK_NOTIFY_VALID_RANGE_MAX - (int)x]; + +#define CHECK_SUBTITLE_CALLBACK_MAX_VALID(x) \ + typedef char SUBTITLE_CALLBACK_MAX_VALID[(int)SUBTITLE_CALLBACK_VALID_RANGE_MAX - (int)x]; + +#define CHECK_STREAM_EVENT_MAX_VALID(x) \ + typedef char STREAM_EVENT_MAX_VALID[(int)STREAM_EVENT_VALID_RANGE_MAX - (int)x]; + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxISOLang.h b/platform/mcu/xr871/src/cedarx/base/include/CdxISOLang.h new file mode 100644 index 0000000000..6fd21724a8 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxISOLang.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxISOLang.h + * Description : iso639 standard for language names + * History : + * + */ + +#ifndef CDX_ISO_LANG_H +#define CDX_ISO_LANG_H + +typedef struct Cdx_ISO_639_Lang_t { + const char *eng_name; /* Description in English */ + const char iso639_1[3]; /* ISO-639-1 (2 characters) code */ + const char iso639_2T[4]; /* ISO-639-2/T (3 characters) English code */ + const char iso639_2B[4]; /* ISO-639-2/B (3 characters) native code */ +} Cdx_ISO_639_Lang_t; + +extern const Cdx_ISO_639_Lang_t CDX_ISO_639_LANGS[]; + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxKeyedVector.h b/platform/mcu/xr871/src/cedarx/base/include/CdxKeyedVector.h new file mode 100644 index 0000000000..ae8b4499c6 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxKeyedVector.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxKeyedVector.h + * Description : KeyVector + * History : + * + */ + +#ifndef __CDX_KEY_VECTOR_H +#define __CDX_KEY_VECTOR_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef struct CdxKeyedVectorS CdxKeyedVectorT; +typedef struct KeyValuePairS KeyValuePairT; + +struct KeyValuePairS { + char *key; + char *val; +}; + +struct CdxKeyedVectorS { + int size; + int index; + KeyValuePairT item[0]; +}; + + +/* return NULL on error */ +CdxKeyedVectorT *CdxKeyedVectorCreate(int num); + +void CdxKeyedVectorDestroy(CdxKeyedVectorT *keyedVector); + +/* For the following four functions, keyedVector must not be NULL. */ + +/* return 0 on success, -1 on error */ +int CdxKeyedVectorAdd(CdxKeyedVectorT *keyedVector, + const char *key, const char *val); + +int CdxKeyedVectorGetSize(CdxKeyedVectorT *keyedVector); + +char *CdxKeyedVectorGetKey(CdxKeyedVectorT *keyedVector, int index); + +char *CdxKeyedVectorGetValue(CdxKeyedVectorT *keyedVector, int index); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxList.h b/platform/mcu/xr871/src/cedarx/base/include/CdxList.h new file mode 100644 index 0000000000..7146c23330 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxList.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxList.h + * Description : List + * History : + * + */ + +#ifndef CDX_LIST_H +#define CDX_LIST_H +#include + +#define CDX_LIST_POISON1 ((void *) 0x00100100) +#define CDX_LIST_POISON2 ((void *) 0x00200200) + +struct CdxListNodeS +{ + struct CdxListNodeS *next; + struct CdxListNodeS *prev; +}; + +struct CdxListS +{ + struct CdxListNodeS *head; + struct CdxListNodeS *tail; +}; + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ +#define CdxListInit(list) do { \ + (list)->head = (list)->tail = (struct CdxListNodeS *)(list);\ + }while (0) + +#define CdxListNodeInit(node) do { \ + (node)->next = (node)->prev = (node);\ + }while (0) + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef AWP_DEBUG +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +void __CdxListAdd(struct CdxListNodeS *new , struct CdxListNodeS *prev, struct CdxListNodeS *next); + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +void CdxListAdd(struct CdxListNodeS *new , struct CdxListS *list); + +void CdxListAddBefore(struct CdxListNodeS *new , struct CdxListNodeS *pos); + +void CdxListAddAfter(struct CdxListNodeS *new , struct CdxListNodeS *pos); + +void CdxListAddTail(struct CdxListNodeS *new , struct CdxListS *list); + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +void __CdxListDel(struct CdxListNodeS *prev, struct CdxListNodeS *next); + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +void __CdxListDelEntry(struct CdxListNodeS *node); + +void CdxListDel(struct CdxListNodeS *node); + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ + void CdxListReplace(struct CdxListNodeS *old, struct CdxListNodeS *new ); + +void CdxListReplaceInit(struct CdxListNodeS *old, struct CdxListNodeS *new ); + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +void CdxListDelInit(struct CdxListNodeS *node); + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +void CdxListMove(struct CdxListNodeS *node, struct CdxListS *list); + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +void CdxListMoveTail(struct CdxListNodeS *node, struct CdxListS *list); + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +int CdxListIsLast(const struct CdxListNodeS *node, const struct CdxListS *list); + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +int CdxListEmpty(const struct CdxListS *list); + +/** + * list_rotate_left - rotate the list to the left + * @head: the head of the list + */ +void CdxListRotateLeft(struct CdxListS *list); + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +int CdxListIsSingular(const struct CdxListS *list); + +#else +#include +#endif + +#ifdef __cplusplus +} +#endif + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define CdxListEntry(ptr, type, member) \ + CdxContainerOf(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define CdxListFirstEntry(ptr, type, member) \ + CdxListEntry((ptr)->head, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define CdxListForEach(pos, list) \ + for (pos = (list)->head; \ + pos != (struct CdxListNodeS *)(list);\ + pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define CdxListForEachPrev(pos, list) \ + for (pos = (list)->tail; \ + pos != (struct CdxListNodeS *)(list); \ + pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define CdxListForEachSafe(pos, n, list) \ + for (pos = (list)->head, n = pos->next; \ + pos != (struct CdxListNodeS *)(list); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define CdxListForEachPrevSafe(pos, n, list) \ + for (pos = (list)->tail, n = pos->prev; \ + pos != (struct CdxListNodeS *)(list); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define CdxListForEachEntry(pos, list, member) \ + for (pos = CdxListEntry((list)->head, typeof(*pos), member); \ + &pos->member != (struct CdxListNodeS *)(list); \ + pos = CdxListEntry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define CdxListForEachEntryReverse(pos, list, member) \ + for (pos = CdxListEntry((list)->tail, typeof(*pos), member); \ + &pos->member != (struct CdxListNodeS *)(list); \ + pos = CdxListEntry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define CdxListForEachEntrySafe(pos, n, list, member) \ + for (pos = CdxListEntry((list)->head, typeof(*pos), member), \ + n = CdxListEntry(pos->member.next, typeof(*pos), member); \ + &pos->member != (struct CdxListNodeS *)(list); \ + pos = n, n = CdxListEntry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define CdxListForEachEntrySafeReverse(pos, n, list, member) \ + for (pos = CdxListEntry((list)->prev, typeof(*pos), member), \ + n = CdxListEntry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (struct CdxListNodeS *)(list); \ + pos = n, n = CdxListEntry(n->member.prev, typeof(*n), member)) + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxList.i b/platform/mcu/xr871/src/cedarx/base/include/CdxList.i new file mode 100644 index 0000000000..6b91616fe8 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxList.i @@ -0,0 +1,177 @@ +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +CDX_INTERFACE void __CdxListAdd(struct CdxListNodeS *new, + struct CdxListNodeS *prev, struct CdxListNodeS *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +CDX_INTERFACE void CdxListAdd(struct CdxListNodeS *new, struct CdxListS *list) +{ + __CdxListAdd(new, (struct CdxListNodeS *)list, list->head); +} + +CDX_INTERFACE void CdxListAddBefore(struct CdxListNodeS *new, + struct CdxListNodeS *pos) +{ + __CdxListAdd(new, pos->prev, pos); +} + +CDX_INTERFACE void CdxListAddAfter(struct CdxListNodeS *new, + struct CdxListNodeS *pos) +{ + __CdxListAdd(new, pos, pos->next); +} + +CDX_INTERFACE void CdxListAddTail(struct CdxListNodeS *new, struct CdxListS *list) +{ + __CdxListAdd(new, list->tail, (struct CdxListNodeS *)list); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +CDX_INTERFACE void __CdxListDel(struct CdxListNodeS *prev, struct CdxListNodeS *next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +CDX_INTERFACE void __CdxListDelEntry(struct CdxListNodeS *node) +{ + __CdxListDel(node->prev, node->next); +} + +CDX_INTERFACE void CdxListDel(struct CdxListNodeS *node) +{ + __CdxListDel(node->prev, node->next); + node->next = CDX_LIST_POISON1; + node->prev = CDX_LIST_POISON2; +} + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +CDX_INTERFACE void CdxListReplace(struct CdxListNodeS *old, + struct CdxListNodeS *new) +{ + new->next = old->next; + new->next->prev = new; + new->prev = old->prev; + new->prev->next = new; +} + +CDX_INTERFACE void CdxListReplaceInit(struct CdxListNodeS *old, + struct CdxListNodeS *new) +{ + CdxListReplace(old, new); + CdxListNodeInit(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +CDX_INTERFACE void CdxListDelInit(struct CdxListNodeS *node) +{ + __CdxListDelEntry(node); + CdxListNodeInit(node); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +CDX_INTERFACE void CdxListMove(struct CdxListNodeS *node, struct CdxListS *list) +{ + __CdxListDelEntry(node); + CdxListAdd(node, list); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +CDX_INTERFACE void CdxListMoveTail(struct CdxListNodeS *node, + struct CdxListS *list) +{ + __CdxListDelEntry(node); + CdxListAddTail(node, list); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +CDX_INTERFACE int CdxListIsLast(const struct CdxListNodeS *node, + const struct CdxListS *list) +{ + return node->next == (struct CdxListNodeS *)list; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +CDX_INTERFACE int CdxListEmpty(const struct CdxListS *list) +{ + return (list->head == (struct CdxListNodeS *)list) + && (list->tail == (struct CdxListNodeS *)list); +} + +/** + * list_rotate_left - rotate the list to the left + * @head: the head of the list + */ +CDX_INTERFACE void CdxListRotateLeft(struct CdxListS *list) +{ + struct CdxListNodeS *first; + + if (!CdxListEmpty(list)) { + first = list->head; + CdxListMoveTail(first, list); + } +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +CDX_INTERFACE int CdxListIsSingular(const struct CdxListS *list) +{ + return !CdxListEmpty(list) && (list->head == list->tail); +} + + diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxLock.h b/platform/mcu/xr871/src/cedarx/base/include/CdxLock.h new file mode 100644 index 0000000000..4da45d7e74 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxLock.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxLock.h + * Description : Lock + * History : + * + */ + +#ifndef CDX_LOCK_H +#define CDX_LOCK_H +#include + +typedef pthread_mutex_t CdxMutexT; +typedef pthread_cond_t CdxCondT; + +#define CdxMutexInit(mutex) pthread_mutex_init(mutex, NULL) +#define CdxMutexDestroy(mutex) pthread_mutex_destroy(mutex) +#define CdxMutexLock(mutex) pthread_mutex_lock(mutex) +#define CdxMutexTrylock(mutex)pthread_mutex_trylock(mutex) +#define CdxMutexUnlock(mutex) pthread_mutex_unlock(mutex) + +#define CdxCondInit(cond) pthread_cond_init(cond, NULL) +#define CdxCondDestroy(cond) pthread_cond_destroy(cond) +#define CdxCondWait(cond, mutex) pthread_cond_wait(cond, mutex) +#define CdxCondTimedwait(cond, mutex, time) \ + pthread_cond_timedwait(cond, mutex, time) +#define CdxCondSignal(cond) pthread_cond_signal(cond) +#define CdxCondBroadcast(cond) pthread_cond_broadcast(cond) + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxMemory.h b/platform/mcu/xr871/src/cedarx/base/include/CdxMemory.h new file mode 100644 index 0000000000..2ba3709edd --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxMemory.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxMemory.h + * Description : Memory + * History : + * + */ + +#ifndef CDX_MEMORY_H +#define CDX_MEMORY_H +#include +#include + +#define CdxMalloc(size) malloc(size) +#define CdxFree(ptr) free(ptr) +#define CdxRealloc(ptr, size) realloc(ptr, size) + +//#define CdxMemcpy(dest, src, n) memcpy(dest, src, n) +//#define CdxMemset(s, c, n) memset(s, c, n) +#define CdxStrdup(s) strdup(s) +//#define CdxStrlen(s) strlen(s) +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxMessage.h b/platform/mcu/xr871/src/cedarx/base/include/CdxMessage.h new file mode 100644 index 0000000000..69f33bd610 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxMessage.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxMessage.h + * Description : Message + * History : + * + */ + +#ifndef CDX_MESSAGE_H +#define CDX_MESSAGE_H +#include +#include +#include + +typedef struct CdxMessageS CdxMessageT; +typedef struct CdxHandlerS CdxHandlerT; +typedef struct CdxDeliverS CdxDeliverT; + +struct CdxDeliverOpsS +{ + cdx_int32 (*postUS)(CdxDeliverT *, CdxMessageT *, cdx_uint64/*timeUs*/); +}; + +struct CdxDeliverS +{ + struct CdxDeliverOpsS *ops; +}; + +CdxDeliverT *CdxDeliverCreate(); + +void CdxDeliverDestroy(CdxDeliverT *deliver); + +void CdxDeliverReset(void); + +static inline cdx_int32 CdxDeliverPostUs(CdxDeliverT *deliver, CdxMessageT *msg, + cdx_uint64 timeUs) +{ + CDX_CHECK(deliver); + CDX_CHECK(deliver->ops); + CDX_CHECK(deliver->ops->postUS); + return deliver->ops->postUS(deliver, msg, timeUs); +} + +/** + *ĿǰmsgijǴеģдеҪ + *Ǽ + */ + +/* sizeof(name) < 32 */ +struct CdxMessageOpsS +{ + CdxMessageT *(*incRef)(CdxMessageT *); + + void (*decRef)(CdxMessageT *); + + CdxMetaT *(*getMeta)(CdxMessageT *); + + cdx_int32 (*what)(CdxMessageT *); + + cdx_err (*postUs)(CdxMessageT *, cdx_uint64); /* asynchronous */ + + CdxMessageT *(*dup)(CdxMessageT *); + + void (*deliver)(CdxMessageT *); +}; + +struct CdxMessageS +{ + struct CdxMessageOpsS *ops; +}; + +static inline CdxMessageT *CdxMessageIncRef(CdxMessageT *msg) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->incRef); + return msg->ops->incRef(msg); +} + +static inline void CdxMessageDecRef(CdxMessageT *msg) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->decRef); + return msg->ops->decRef(msg); +} + +static inline CdxMetaT *CdxMessageGetMeta(CdxMessageT *msg) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->getMeta); + return msg->ops->getMeta(msg); +} + +static inline void CdxMessageDeliver(CdxMessageT *msg) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->deliver); + return msg->ops->deliver(msg); +} + +#define CdxMessageFastNotify(pool, what, hdr) \ + do \ + { \ + CdxMessageT *_notifyMsg = CdxMessageCreate(pool, what, hdr); \ + CDX_FORCE_CHECK(_notifyMsg); \ + CdxMessagePost(_notifyMsg); \ + }while (0) + +#define CdxMessageSetInt32(msg, name, val) \ + CdxMetaSetInt32(CdxMessageGetMeta(msg), name, val) + +#define CdxMessageFindInt32(msg, name, pVal) \ + CdxMetaFindInt32(CdxMessageGetMeta(msg), name, pVal) + +#define CdxMessageSetInt64(msg, name, val) \ + CdxMetaSetInt64(CdxMessageGetMeta(msg), name, val) + +#define CdxMessageFindInt64(msg, name, pVal) \ + CdxMetaFindInt64(CdxMessageGetMeta(msg), name, pVal) + +#define CdxMessageSetString(msg, name, val) \ + CdxMetaSetString(CdxMessageGetMeta(msg), name, val) + +#define CdxMessageFindString(msg, name, pVal) \ + CdxMetaFindString(CdxMessageGetMeta(msg), name, pVal) + +#define CdxMessageSetObject(msg, name, val) \ + CdxMetaSetObject(CdxMessageGetMeta(msg), name, val) + +#define CdxMessageFindObject(msg, name, pVal) \ + CdxMetaFindObject(CdxMessageGetMeta(msg), name, (void **)(pVal)) + +#define CdxMessageRemoveObject(msg, name) \ + CdxMetaRemoveObject(CdxMessageGetMeta(msg), name) + +#define CdxMessageClearMeta(msg) \ + CdxMetaClear(CdxMessageGetMeta(msg)) + +static inline cdx_int32 CdxMessageWhat(CdxMessageT *msg) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->what); + return msg->ops->what(msg); +} + +static inline cdx_err CdxMessagePostUs(CdxMessageT *msg, cdx_uint64 timeOut) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->postUs); + return msg->ops->postUs(msg, timeOut); +} + +static inline CdxMessageT *CdxMessageDup(CdxMessageT *msg) +{ + CDX_CHECK(msg); + CDX_CHECK(msg->ops); + CDX_CHECK(msg->ops->dup); + return msg->ops->dup(msg); +} + +#define CdxMessagePost(msg) \ + CdxMessagePostUs(msg, 0) + +#ifdef __cplusplus +extern "C" { +#endif +#define CdxMessageCreate(pool, what, handler) \ + __CdxMessageCreate(pool, what, handler, __FILE__, __LINE__) + +CdxMessageT *__CdxMessageCreate(AwPoolT *pool, cdx_int32 what, CdxHandlerT *handler, + char *file, int line); + +void CdxMessageDestroy(CdxMessageT *msg); + +/*-----------------------------msg handler-----------------------------*/ +typedef struct CdxHandlerItfS CdxHandlerItfT; + +struct CdxHandlerItfOpsS +{ + void (*msgRecv)(CdxHandlerItfT *, CdxMessageT *); +}; + +struct CdxHandlerItfS +{ + struct CdxHandlerItfOpsS *ops; +}; + +struct CdxHandlerOpsS +{ + cdx_int32 (*postUs)(CdxHandlerT *, CdxMessageT *, cdx_uint64); + + void (*msgRecv)(CdxHandlerT *, CdxMessageT *); +}; + +struct CdxHandlerS +{ + struct CdxHandlerOpsS *ops; +}; + +static inline cdx_int32 CdxHandlerPostUs(CdxHandlerT *hdr, CdxMessageT *msg, + cdx_uint64 timeUs) +{ + CDX_CHECK(hdr); + CDX_CHECK(hdr->ops); + return hdr->ops->postUs(hdr, msg, timeUs); +} + +static inline void CdxHandlerMsgRecv(CdxHandlerT *hdr, CdxMessageT *msg) +{ + CDX_CHECK(hdr); + CDX_CHECK(hdr->ops); + return hdr->ops->msgRecv(hdr, msg); +} + +CdxHandlerT *CdxHandlerCreate(AwPoolT *pool, CdxHandlerItfT *itf, CdxDeliverT *deliver); + +void CdxHandlerDestroy(CdxHandlerT *hdr); + +/*--------------------------msg handler end----------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif // A_MESSAGE_H_ diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxMeta.h b/platform/mcu/xr871/src/cedarx/base/include/CdxMeta.h new file mode 100644 index 0000000000..da0d54b35b --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxMeta.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxMeta.h + * Description : Meta + * History : + * + */ + +#ifndef CDX_META_H +#define CDX_META_H +#include +#include +#include + +#define CDX_META_ITEM_NAMESIZE 32 + +//typedef void (*pfObjDtor)(void *); +typedef struct CdxMetaS CdxMetaT; + +/* sizeof(name) < 32 */ +struct CdxMetaOpsS +{ + CdxMetaT *(*incRef)(CdxMetaT *); + void (*decRef)(CdxMetaT *); + + cdx_err (*setInt32)(CdxMetaT *, cdx_char * /*name*/, cdx_int32); + cdx_err (*findInt32)(CdxMetaT *, cdx_char * /*name*/, cdx_int32 *); + cdx_err (*removeInt32)(CdxMetaT *, cdx_char * /*name*/); + + cdx_err (*setInt64)(CdxMetaT *, cdx_char * /*name*/, cdx_int64); + cdx_err (*findInt64)(CdxMetaT *, cdx_char * /*name*/, cdx_int64 *); + cdx_err (*removeInt64)(CdxMetaT *, cdx_char * /*name*/); + + cdx_err (*setString)(CdxMetaT *, cdx_char * /*name*/, cdx_char *); + cdx_err (*findString)(CdxMetaT *, cdx_char * /*name*/, cdx_char **); + cdx_err (*appendString)(CdxMetaT *, cdx_char * /*name*/, cdx_char *); + cdx_err (*removeString)(CdxMetaT *, cdx_char * /*name*/); + + cdx_err (*setData)(CdxMetaT *, cdx_char * /*name*/, cdx_uint8 *, cdx_uint32); + cdx_err (*findData)(CdxMetaT *, cdx_char * /*name*/, cdx_uint8 **, cdx_uint32*); + cdx_err (*removeData)(CdxMetaT *, cdx_char * /*name*/); + + cdx_err (*setObject)(CdxMetaT *, cdx_char * /*name*/, void *); + cdx_err (*findObject)(CdxMetaT *, cdx_char * /*name*/, void **); + cdx_err (*removeObject)(CdxMetaT *, cdx_char * /*name*/); + + CdxMetaT *(*dup)(CdxMetaT *); + void (*clear)(CdxMetaT *); +}; + +struct CdxMetaS +{ + struct CdxMetaOpsS *ops; +}; + +static inline CdxMetaT *CdxMetaIncRef(CdxMetaT *meta) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->incRef); + return meta->ops->incRef(meta); +} + +static inline void CdxMetaDecRef(CdxMetaT *meta) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->decRef); + return meta->ops->decRef(meta); +} + +static inline cdx_err CdxMetaSetInt32(CdxMetaT *meta, + cdx_char *name, cdx_int32 val) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->setInt32); + return meta->ops->setInt32(meta, name, val); +} + +static inline cdx_err CdxMetaFindInt32(CdxMetaT *meta, + cdx_char *name, cdx_int32 *pVal) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->findInt32); + return meta->ops->findInt32(meta, name, pVal); +} + +static inline cdx_err CdxMetaRemoveInt32(CdxMetaT *meta, cdx_char *name) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->removeInt32); + return meta->ops->removeInt32(meta, name); +} + +static inline cdx_err CdxMetaSetInt64(CdxMetaT *meta, + cdx_char *name, cdx_int64 val) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->setInt64); + return meta->ops->setInt64(meta, name, val); +} + +static inline cdx_err CdxMetaFindInt64(CdxMetaT *meta, + cdx_char *name, cdx_int64 *pVal) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->findInt64); + return meta->ops->findInt64(meta, name, pVal); +} + +static inline cdx_err CdxMetaSetString(CdxMetaT *meta, + cdx_char *name, cdx_char *val) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->setString); + return meta->ops->setString(meta, name, val); +} + +/** + *ͨλҪstring + *ûҪеCdxFree()ͷſռ + */ +static inline cdx_err CdxMetaFindString(CdxMetaT *meta, + cdx_char *name, cdx_char **pVal) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->findString); + return meta->ops->findString(meta, name, pVal); +} + +static inline cdx_err CdxMetaAppendString(CdxMetaT *meta, + cdx_char *name, cdx_char *val) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->appendString); + return meta->ops->appendString(meta, name, val); +} + +static inline cdx_err CdxMetaSetData(CdxMetaT *meta, cdx_char *name, + cdx_uint8 *val, cdx_uint32 size) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->setData); + return meta->ops->setData(meta, name, val, size); +} + +/** + *ͨλҪstring + *ûҪеCdxFree()ͷſռ + */ +static inline cdx_err CdxMetaFindData(CdxMetaT *meta, cdx_char *name, + cdx_uint8 **pVal, cdx_uint32 *pSize) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->findData); + return meta->ops->findData(meta, name, pVal, pSize); +} + +static inline cdx_err CdxMetaSetObject(CdxMetaT *meta, cdx_char *name, void *val) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->setObject); + return meta->ops->setObject(meta, name, val); +} + +/** + *ͨλҪĶľ + *meta,Ч + *ҪڱʹõĻü+1 + *߱渱 + */ +static inline cdx_err CdxMetaFindObject(CdxMetaT *meta, + cdx_char *name, void **pVal) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->findObject); + return meta->ops->findObject(meta, name, pVal); +} + +static inline cdx_err CdxMetaRemoveObject(CdxMetaT *meta, cdx_char *name) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->removeObject); + return meta->ops->removeObject(meta, name); +} + +static inline CdxMetaT *CdxMetaDup(CdxMetaT *meta) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->dup); + return meta->ops->dup(meta); +} + +static inline void CdxMetaClear(CdxMetaT *meta) +{ + CDX_CHECK(meta); + CDX_CHECK(meta->ops); + CDX_CHECK(meta->ops->clear); + meta->ops->clear(meta); + return ; +} + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define CdxMetaCreate(pool) \ + __CdxMetaCreate(pool, __FILE__, __LINE__) + +CdxMetaT *__CdxMetaCreate(AwPoolT *pool, char *file, int line); + +void CdxMetaDestroy(CdxMetaT *meta); + +#ifdef __cplusplus +} +#endif + +#endif // A_MESSAGE_H_ diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxQueue.h b/platform/mcu/xr871/src/cedarx/base/include/CdxQueue.h new file mode 100644 index 0000000000..39820d301a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxQueue.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxQueue.h + * Description : Queue + * History : + * + */ + +#ifndef CDX_QUEUE_H +#define CDX_QUEUE_H +#include +#include +#include + +typedef struct CdxQueueS CdxQueueT; +typedef void * CdxQueueDataT; + +struct CdxQueueOpsS +{ + CdxQueueDataT (*pop)(CdxQueueT *); + cdx_err (*push)(CdxQueueT *, CdxQueueDataT); + cdx_bool (*empty)(CdxQueueT *); + +}; + +struct CdxQueueS +{ + struct CdxQueueOpsS *ops; +}; + +static inline CdxQueueDataT CdxQueuePop(CdxQueueT *queue) +{ + CDX_CHECK(queue); + CDX_CHECK(queue->ops); + CDX_CHECK(queue->ops->pop); + return queue->ops->pop(queue); +} + +static inline cdx_err CdxQueuePush(CdxQueueT *queue, CdxQueueDataT data) +{ + CDX_CHECK(queue); + CDX_CHECK(queue->ops); + CDX_CHECK(queue->ops->push); + return queue->ops->push(queue, data); +} + +static inline cdx_bool CdxQueueEmpty(CdxQueueT *queue) +{ + CDX_CHECK(queue); + CDX_CHECK(queue->ops); + CDX_CHECK(queue->ops->empty); + return queue->ops->empty(queue); +} + +#ifdef __cplusplus +extern "C" +{ +#endif +/*this is a look free queue*/ +CdxQueueT *CdxQueueCreate(AwPoolT *pool); + +void CdxQueueDestroy(CdxQueueT *queue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxSocketUtil.h b/platform/mcu/xr871/src/cedarx/base/include/CdxSocketUtil.h new file mode 100644 index 0000000000..fd08dc827d --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxSocketUtil.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxSocketUtil.h + * Description : SocketUtil + * History : + * + */ + +#ifndef CDX_SOCKET_UTIL_H +#define CDX_SOCKET_UTIL_H +#include + +#include /* See NOTES */ +#include "lwip/sockets.h" +//#include +#include "lwip/inet.h" + +#define CDX_SELECT_TIMEOUT 100000L /*100 ms*/ + +#ifdef __cplusplus +extern "C" +{ +#endif +cdx_int32 CdxSockSetBlocking(cdx_int32 sockfd, cdx_int32 blocking); + +cdx_err CdxMakeSocketBlocking(cdx_int32 s, cdx_bool blocking); + +void CdxSocketMakePortPair(cdx_int32 *rtpSocket, cdx_int32 *rtcpSocket, + cdx_uint32 *rtpPort); + +cdx_int32 CdxSockAddrConstruct(struct sockaddr_in *dest, char *ip, cdx_int32 port); + +cdx_ssize CdxSockNoblockRecv(cdx_int32 sockfd, void *buf, cdx_size len); + +cdx_ssize CdxSockAsynRecv(cdx_int32 sockfd, void *buf, cdx_size len, + cdx_long timeoutUs, cdx_int32 *pForceStop); + +cdx_ssize CdxSockAsynSend(cdx_int32 sockfd, const void *buf, cdx_size len, + cdx_long timeoutUs, cdx_int32 *pForceStop); + +cdx_int32 CdxAsynSocket(int domain, cdx_int32 *nRecvBufLen); + +cdx_int32 CdxSockAsynConnect(cdx_int32 sockfd, const struct sockaddr *addr, + socklen_t addrlen, cdx_long timeoutUs, cdx_int32 *pForceStop); + +cdx_int32 CdxSockIsBlocking(cdx_int32 sockfd); + +void CdxSockDisableTcpKeepalive(cdx_int32 sockfd); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxStrUtil.h b/platform/mcu/xr871/src/cedarx/base/include/CdxStrUtil.h new file mode 100644 index 0000000000..0697dfbab1 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxStrUtil.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxStrUtil.h + * Description : StrUtil + * History : + * + */ + +#ifndef CDX_STR_UTIL_H +#define CDX_STR_UTIL_H + +#include +#include +#include + +struct CdxStrItemS +{ + CdxListNodeT node; + cdx_char *val; +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +void CdxStrTrimTail(cdx_char *str); + +void CdxStrTrimHead(cdx_char *str); + +void CdxStrTrim(cdx_char *str); + +void CdxStrTolower(cdx_char *str); + +cdx_char *CdxStrAttributeOfKey(AwPoolT *pool, const cdx_char *str, cdx_char *key, cdx_char sepa); + +cdx_uint32 CdxStrSplit(AwPoolT *pool, cdx_char *str, char sepa, CdxListT *itemList); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxSysinfo.h b/platform/mcu/xr871/src/cedarx/base/include/CdxSysinfo.h new file mode 100644 index 0000000000..8d33c1fff7 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxSysinfo.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxSysinfo.h + * Description : Sysinfo + * History : + * + */ + +#ifndef CDX_SYS_INFO_H +#define CDX_SYS_INFO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if 0 +//* get current ddr frequency, if it is too slow, we will cut some spec off. +int MemAdapterGetDramFreq(); + +enum CHIPID +{ + SI_CHIP_UNKNOWN = 0, + SI_CHIP_H3s = 1, + SI_CHIP_H3 = 2, + SI_CHIP_H2 = 3, + SI_CHIP_H2PLUS = 4, +}; + +int SysinfoChipId(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxTime.h b/platform/mcu/xr871/src/cedarx/base/include/CdxTime.h new file mode 100644 index 0000000000..6ee1aaa67c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxTime.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxTime.h + * Description : Time + * History : + * + */ + +#ifndef CDX_TIME_H +#define CDX_TIME_H + +#include + +/* Wall Clock: it's not monotonic and may have discontinuities */ +CDX_API cdx_int64 CdxGetNowUs(void); + +/* Monotonic clock */ +CDX_API cdx_int64 CdxMonoTimeUs(void); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxTypes.h b/platform/mcu/xr871/src/cedarx/base/include/CdxTypes.h new file mode 100644 index 0000000000..2c8f606bfa --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxTypes.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxTypes.h + * Description : Types + * History : + * + */ + +#ifndef CDX_TYPES_H +#define CDX_TYPES_H + +/* This is not safe as ((void*)0) for C, and you cannot define NULL as + * ((void*)0) for C++, so don't bother to define your own NULL. +#ifdef NULL +#undef NULL +#endif +#define NULL 0 +*/ + +#define CDX_SUCCESS 0 +#define CDX_FAILURE (-1) + +typedef long long cdx_int64; +typedef unsigned long long cdx_uint64; + +typedef int cdx_int32; +typedef unsigned int cdx_uint32; + +typedef short cdx_int16; +typedef unsigned short cdx_uint16; + +typedef unsigned char cdx_uint8; + +/* For gcc, char is default to unsigned on ARM and signed on x86 platform. So + * typedef char cdx_int8 is wrong. + */ +typedef signed char cdx_int8; + +typedef unsigned long cdx_ulong; +typedef long cdx_long; + +typedef char cdx_char; +typedef int cdx_bool; +typedef unsigned long cdx_size; +typedef signed long cdx_ssize; + +typedef float cdx_float; + +typedef struct CdxBufferS CdxBufferT; +typedef struct CdxListNodeS CdxListNodeT; +typedef struct CdxListS CdxListT; + +#ifdef AWP_DEBUG +#define CDX_INTERFACE +#else +#define CDX_INTERFACE static inline +#endif + +#ifdef __cplusplus +#define CDX_EXTERN extern "C" +#else +#define CDX_EXTERN +#endif + +#define CDX_API CDX_EXTERN + +typedef cdx_int32 cdx_err; + +#define CDX_TRUE 1 +#define CDX_FALSE 0 + +#define CedarXMin(a, b) ((a) < (b) ? (a) : (b)) + +#define CdxOffsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#define CdxContainerOf(ptr, type, member) ({ \ + const typeof(((type *)0)->member) *__mptr = (ptr); \ + (type *)((char *)__mptr - CdxOffsetof(type,member) ); }) + +enum CdxMediaTypeE +{ + CDX_MEDIA_UNKNOWN = -1, + CDX_MEDIA_VIDEO = 0, + CDX_MEDIA_AUDIO, + CDX_MEDIA_SUBTITLE, + CDX_MEDIA_METADATA, + CDX_MEDIA_DATA, +}; + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/CdxUrl.h b/platform/mcu/xr871/src/cedarx/base/include/CdxUrl.h new file mode 100644 index 0000000000..c3d83585cb --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/CdxUrl.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxUrl.h + * Description : Url + * History : + * + */ + +#ifndef CDX_URL +#define CDX_URL + +typedef struct AW_URL +{ + char* url; + char* protocol; + char* hostname; + char* file; + unsigned int port; + char* username; + char* password; + char* noauth_url; +}CdxUrlT; + +CdxUrlT* CdxUrlNew(char* url); +void CdxUrlPrintf(CdxUrlT* url); +void CdxUrlFree(CdxUrlT* curUrl); + +void CdxUrlEscapeString(char *outbuf, const char *inbuf); + +void CdxUrlUnescapeString(char *outbuf, const char *inbuf); + +void CdxUrlEscapeStringPart(char *outbuf, const char *inbuf); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/SmartDnsService.h b/platform/mcu/xr871/src/cedarx/base/include/SmartDnsService.h new file mode 100644 index 0000000000..2fa4e6ada7 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/SmartDnsService.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : SmartDnsService.h + * Description : SmartDnsService + * History : + * + */ + +#ifndef SMART_DNS_SERVICE_H +#define SMART_DNS_SERVICE_H + +typedef void (*ResponeHook)(void * /* userhdr */, int /* ret */ , struct addrinfo * /* ret */); + +enum SDSReturnValueE +{ + SDS_OK, + SDS_PENDING, + SDS_ERROR, +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +int SDSRequest(const char *hostname, int port, struct addrinfo **pAddr, + void *userHdr, ResponeHook hook); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/cdx_log.h b/platform/mcu/xr871/src/cedarx/base/include/cdx_log.h new file mode 100644 index 0000000000..46b12c808a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/cdx_log.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : cdx_log.h + * Description : Log + * History : + * + */ + +#ifndef CDX_LOG_H +#define CDX_LOG_H + +#ifndef LOG_TAG +#define LOG_TAG "awplayer" +#endif + +#include "cdx_malloc_dbg.h" + +#define CDX_DEBUG 1 + +/* temp define to develop */ +#define VIDEO_SUPPORT 0 //might be needed in the camera application. but it's not realized. +#define SUBTITLE_SUPPORT 0 //almost impossible +#define ONLINE_SUPPORT 0 //should be change to cache support +#define FD_SUPPORT 0 //might not support in future +#define ID3_IOT_IMPLEMENT 1 //revise for IOT. +#define LIVEMODE_VIDEO 0 //almost impossible +#define SOUNDCTRL_NULL 0 //only for test +#define CAPTURECTRL_NULL 0 //only for test +#define CDX_IOT_AWPOOL 0 //revise for IOT, but can be used for revise memory allocating. +#define CDX_IOT_OLD_SOCKET 0 //revise for IOT, 0: connect every time. +#define CDX_IOT_DNS_CACHE 0 //revise for IOT, 0: using Lwip Dns. 1: using Cedarx Dns. +#define CDX_IOT_CMCC_LOG 0 //log string callback to user. +#define CDX_LWIP_SELECT_ERR 0 //Lwip not support error teller function. +#define SET_SPEED_SUPPORT 0 +#define SECURE_BUFFER_SUPPORT 0 + +#ifndef DEF_CDX_LOG_LEVEL_TYPE +#define DEF_CDX_LOG_LEVEL_TYPE +enum CDX_LOG_LEVEL_TYPE { + LOG_LEVEL_VERBOSE = 2, + LOG_LEVEL_DEBUG = 3, + LOG_LEVEL_INFO = 4, + LOG_LEVEL_WARNING = 5, + LOG_LEVEL_ERROR = 6, +}; +#endif + +#include +int printf_lock_init(); +int wrap_printf(const char *fmt, ...); +int printf_lock_deinit(); + +int log_file_reset(const char *path); +int log_file(const char *path, unsigned char *buf, unsigned int len); + +void __printf_time(const char *f, unsigned int l); +#define printf_time() __printf_time(__func__, __LINE__) + +#define printf wrap_printf + +extern enum CDX_LOG_LEVEL_TYPE GLOBAL_LOG_LEVEL; + +#ifndef CONFIG_LOG_LEVEL +#define CONFIG_LOG_LEVEL (0xFFFF) +#endif + +#ifdef __ANDROID__ +#include + +#define CDX_LOG_ORDER \ + ((unsigned)LOG_LEVEL_ERROR == (unsigned)ANDROID_LOG_ERROR) && \ + ((unsigned)LOG_LEVEL_WARNING == (unsigned)ANDROID_LOG_WARN) && \ + ((unsigned)LOG_LEVEL_INFO == (unsigned)ANDROID_LOG_INFO) && \ + ((unsigned)LOG_LEVEL_DEBUG == (unsigned)ANDROID_LOG_DEBUG) && \ + ((unsigned)LOG_LEVEL_VERBOSE == (unsigned)ANDROID_LOG_VERBOSE) + +typedef char CHECK_LOG_LEVEL_EQUAL_TO_ANDROID[CDX_LOG_ORDER > 0 ? 1 : -1]; + +#define AWLOG(level, fmt, arg...) \ + do { \ + if (level >= GLOBAL_LOG_LEVEL || level >= CONFIG_LOG_LEVEL) \ + LOG_PRI(level, LOG_TAG, "<%s:%u>: " fmt, __FUNCTION__, __LINE__, ##arg); \ + } while (0) + +#define CDX_TRACE() \ + CDX_LOGI("<%s:%u> tid(%d)", __FUNCTION__, __LINE__, gettid()) + +/*check when realease version*/ +#define CDX_FORCE_CHECK(e) \ + LOG_ALWAYS_FATAL_IF( \ + !(e), \ + "<%s:%d>CDX_CHECK(%s) failed.", \ + __FUNCTION__, __LINE__, #e) + +#define CDX_TRESPASS() \ + LOG_ALWAYS_FATAL("Should not be here.") + +#define CDX_LOG_FATAL(fmt, arg...) \ + LOG_ALWAYS_FATAL("<%s:%d>" fmt, \ + __FUNCTION__, __LINE__, ##arg) + +#define CDX_LOG_CHECK(e, fmt, arg...) \ + LOG_ALWAYS_FATAL_IF( \ + !(e), \ + "<%s:%d>check (%s) failed:" fmt, \ + __FUNCTION__, __LINE__, #e, ##arg) + +#ifdef AWP_DEBUG +#define CDX_CHECK(e) \ + LOG_ALWAYS_FATAL_IF( \ + !(e), \ + "<%s:%d>CDX_CHECK(%s) failed.", \ + __FUNCTION__, __LINE__, #e) + +#else +#define CDX_CHECK(e) +#endif + +#else + +#include +#include +//#include +#include "unistd.h" + +extern const char *CDX_LOG_LEVEL_NAME[]; + +#if CDX_DEBUG +#define AWLOG(level, fmt, arg...) \ + do { \ + if ((level >= GLOBAL_LOG_LEVEL || level >= CONFIG_LOG_LEVEL) && \ + level <= LOG_LEVEL_ERROR) \ + printf("%s: %s <%s:%u>: " fmt "\n", \ + CDX_LOG_LEVEL_NAME[level], LOG_TAG, __FUNCTION__, __LINE__, ##arg); \ + } while (0) +#else +#define AWLOG(level, fmt, arg...) +#endif + +#define CDX_TRESPASS() + +#define CDX_FORCE_CHECK(e) CDX_CHECK(e) + +#define CDX_LOG_CHECK(e, fmt, arg...) \ + do { \ + if (!(e)) \ + { \ + CDX_LOGE("check (%s) failed:"fmt, #e, ##arg); \ + } \ + } while (0) + +#ifdef AWP_DEBUG +#define CDX_CHECK(e) \ + do { \ + if (!(e)) \ + { \ + CDX_LOGE("check (%s) failed.", #e); \ + assert(0); \ + } \ + } while (0) +#else +#define CDX_CHECK(e) (void)(e) +#endif + +#endif + +#define CDX_LOGV(fmt, arg...) logv(fmt, ##arg) +#define CDX_LOGD(fmt, arg...) logd(fmt, ##arg) +#define CDX_LOGI(fmt, arg...) logi(fmt, ##arg) +#define CDX_LOGW(fmt, arg...) logw(fmt, ##arg) +#define CDX_LOGE(fmt, arg...) loge(fmt, ##arg) + +#if CDX_DEBUG +#define CDX_BUF_DUMP(buf, len) \ + do { \ + char *_buf = (char *)buf;\ + char str[1024] = {0};\ + unsigned int index = 0, _len;\ + _len = (unsigned int)len;\ + snprintf(str, 1024, ":%d:[", _len);\ + for (index = 0; index < _len; index++)\ + {\ + snprintf(str + strlen(str), 1024 - strlen(str), "%02hhx ", _buf[index]);\ + }\ + str[strlen(str) - 1] = ']';\ + CDX_LOGD("%s", str);\ + }while (0) +#else +#define CDX_BUF_DUMP(buf, len) +#endif + +#define CDX_ITF_CHECK(base, itf) \ + CDX_CHECK(base); \ + CDX_CHECK(base->ops); \ + CDX_CHECK(base->ops->itf) + +#define CDX_UNUSE(param) (void)param +#define CEDARX_UNUSE(param) (void)param + +#define logd(fmt, arg...) //AWLOG(LOG_LEVEL_DEBUG, fmt, ##arg) +#define loge(fmt, arg...) AWLOG(LOG_LEVEL_ERROR, "\033[40;31m" fmt "\033[0m", ##arg) +#define logw(fmt, arg...) //AWLOG(LOG_LEVEL_WARNING, fmt, ##arg) +#define logi(fmt, arg...) //AWLOG(LOG_LEVEL_INFO, fmt, ##arg) +#define logv(fmt, arg...) //AWLOG(LOG_LEVEL_VERBOSE, fmt, ##arg) + +#define CDX_ENTRY() //PRINTF("[%s entry] line %d\n", __func__, __LINE__) +#define CDX_EXIT(ret) //PRINTF("[%s exit] line %d, return %d\n", __func__, __LINE__, (int)ret) + +#define CDX_FAILED() //PRINTF("[%s failed] line %d\n", __func__, __LINE__) + + +#ifdef __cplusplus +extern "C" +{ +#endif + +void log_set_level(unsigned level); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/base/include/cdx_malloc_dbg.h b/platform/mcu/xr871/src/cedarx/base/include/cdx_malloc_dbg.h new file mode 100644 index 0000000000..1a51b3057d --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/base/include/cdx_malloc_dbg.h @@ -0,0 +1,42 @@ + +#ifndef CDX_MALLOC_DBG_H +#define CDX_MALLOC_DBG_H + +#define DBG_MALLOC 0 +#define DBG_MALLOC_TOTAL 1 +#define DBG_MALLOC_LIST 0 +#define DBG_MALLOC_OVERFLOW 1 +#define DBG_MALLOC_LOG_ALL 0 +#define FREE_NULL_WARNING 0 + +#if DBG_MALLOC_LOG_ALL +extern int wrap_printf(const char *fmt, ...); +#define DBG_MALLOC_PRINTF(fmt, arg...) wrap_printf(fmt, ##arg) +#else +#define DBG_MALLOC_PRINTF(fmt, arg...) +#endif + +#include +#include +void *dbg_malloc(unsigned int size, const char *func, int line); +void dbg_free(void *p, const char *func, int line); +void *dbg_calloc(unsigned int n, unsigned int size, const char *func, int line); +void *dbg_strdup(const char *s, const char *func, int line); +#if DBG_MALLOC_TOTAL +void *dbg_realloc(void *ptr, unsigned int newsize, const char *func, int line); +#endif + +#if DBG_MALLOC +#define malloc(s) dbg_malloc(s, __func__, __LINE__) +#define calloc(n,s) dbg_calloc(n, s, __func__, __LINE__) +#define free(p) dbg_free(p, __func__, __LINE__) +#define strdup(s) dbg_strdup(s, __func__, __LINE__) +#if DBG_MALLOC_TOTAL +#define realloc(p,s) dbg_realloc(p, s, __func__, __LINE__) +#endif +#endif + + + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/cedarx.a b/platform/mcu/xr871/src/cedarx/cedarx.a new file mode 100644 index 0000000000000000000000000000000000000000..f69656fdd029c1fc7858797add9e9362e4b4a891 GIT binary patch literal 1989960 zcmeFa3w&HvwLiYk%p{q~Bxzo4(>5)WK2zE}nwGXeA4!w6O%I5$`OhaO-@Vsfd+oK?-e>Q9UTasai6;97*X7qmvVY4?TXtIg@|7!AogRtQ>m>L8 zNMzaa`uYY<-;=MD?@XmuJoUzpk3Ou_8#(@btx_jBtn;2%Cp|u;lr`D$+>o*+Ieb+C zHSV|x)%@boiH|>2DBpkb@W1zVo!I3*{ z+kgJJCav;vuKuq*KDbon{S8O3>M1quxbTDuzTWXuh_J81*I`0c=>cyY=43speaxIPsAk?${+~K#t-n_NR~?ntDfRa}W`BKD{S8OcSbsdxI?|Wu zk2NQTN1KzeXga1m)V7g$+DmJRrP7JyAuqWr9Zino?Mf#`y^Ni)RBRk$M|3PTLFuDo z=?!B81F__IAs386kI53#W66<;)4F2m=IGE+Z?tcpYC2%*pR_A)$DJzL1Y-v~wkeiw zJ(x~L`=jY-MhGN#M3d3s7|m$2id8aE+QW{CCG6@|tfL5-!(aS|Z)jS=;&7N)2?XgrUx;M6SEH)N1cJ1jwmEC0O zluV!pWl=j4skCr;QqGRXCrRl}9ztVGoNLmAjYDIpK~E82ZcdDiq*X^EF|>o{ggGC2 zdYTT9@LNr5Q+MnLc4WFNA|{4PmhZh+c%D=Er}vrd?L-s zXPczCWp__oS9{OO<)`;-Yud4?i+XL19g6jz73;&Wk;&&GI+?RroBI1bnW0Bl{KD9H zDrAi(o)sM$le%q=j`R=3lI&r-x=b~Mv^}-AGuF3XwZw+v`(w%O_;4(#Pa&u+G`HcT zr)6p(1iJ=qF|7wNcDlq2#iB_R=OWp;GE7c~5%n?!3Bk@XXlm3xno`5&gk!MZ)Plji zLy6ufdaACL+Ur(qbAQsLOuC)K>72CHqF6D@N>&*a3!`2V;HvR&*p22jelj#LifMJc;hZ zbl14zL~WxWd3$tUtSiyC52qPU%zdJhp)jo@k;Et+Pckp5=w!*}#0bWtF(aQuoEYBR zZ7DaUDRpSX$h76O#8c7Up;&j{=+;mhKsf?T-zqQQZ@IsA^A~D}@8e=xC3j zW+nE=bTV@f#D`)%NxcNHqv(txDUDK8fA8L&VKbUC*p~^StLovFWVBd6x+;Tuz}2~8 z!#(LlIyz+Qz|m-1`=*|4t!K4v>)Fw?z11bXCo!TnZEN4qv@OH4Y#c>(wRCmH^kPH7 ze5qJcVjEJjz%bNZqnNg14sk;Y9W{Aq=NP&|TGmQ9M`F=o4%T`U(=#fjdxy{x>l4`> zeZwLgG$T1f>KHoIi>{$n@=#xgwF46ma*WpurC`cScEw`*6i2@}w7xK=6_g~UN2V-_ zNzo)zGYq0=mBgVeE;GJlk@UQCpkpX{$n-~-2$`5T$d99Lj~?8}&B%FC zo7dea#vIw{dal$><|@Ex0!K`ijWoNHL@RY28tI$ZQrqIaumjDhPNa37W~P5sTW{%CT;SbV6zsj0aGOWatR zgS{k(Iov5Jp6@*e>(v}IGvAywBnsb4PYf+pdnJDxAFvHuxrYC^du+7sI8*VX!Hm4*+ z5(h?vWtUzcfVOLN*GL@0kkGYJCCnAO1iRvUN1|rliVdR;u`DyIkLF%I-srkC_jbpI z96FoU=FujnsODZBG>W?k_Ux|(WwM%#nwTj^m(qE*Hd*J{%|i)XbV9aAvWePqF<1BX z48+oXgFRSu^+d5O^^j6yyp2iri6EMx2QhRYB)6<7r1kq&7q#THjsy+@i2YUt*?0t3w^IN|YIl#+V zCzj&eV)Lch*mk5(x5D07IvwvEj`X2n(IM>U`3cMlb|l7YB|FlO z%ZDP9!Yi08}2@{yxNz1aSL!H2+OzY`QCZhd)Q5ecyh-1$z;yB4YDKpe% zap`WQEt5soltc!`AxC3o?Ezf+;FIU zV1OrRbU3LOCrKIiO~f_u8$ug97REW@H4Wj!^=RnCI+D14Nur(fVpmTMUA)DDOGCNM zuq!>VY-KtDSiLPavNt_Q(JrDymp2$5Pc)OIiHrG-$;9xk?v1O-7^`hAVpV! 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j2ArKe(AR)_3BxZZjGggL#m=$|>ib~={rG@`r|>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> CedarX <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n" + "tag : %s\n" + "branch: %s\n" + "commit: %s\n" + "date : %s\n" + "author: %s\n" + "----------------------------------------------------------------------\n", + REPO_TAG, REPO_BRANCH, REPO_COMMIT, REPO_DATE, RELEASE_AUTHOR); +} + +/* usage: TagVersionInfo(myLibTag) */ +#define TagVersionInfo(tag) \ + static void VersionInfo_##tag(void) __attribute__((constructor));\ + void VersionInfo_##tag(void) \ + { \ + logd("-------library tag: %s-------", #tag);\ + LogVersionInfo(); \ + } + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/platform/mcu/xr871/src/cedarx/common/iniparser/iniparserapi.h b/platform/mcu/xr871/src/cedarx/common/iniparser/iniparserapi.h new file mode 100644 index 0000000000..c92839db17 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/common/iniparser/iniparserapi.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : iniparserapi.h + * Description : iniparserapi + * History : + * + */ + +#ifndef INI_PARSER_API_H +#define INI_PARSER_API_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*-------------------------------------------------------------------------*/ +/** + @brief IniParser to load /system/etc/cedarx.conf config file + @return integer 1 parse success, 0 parse fail + + The dictionary will save int a global vale g_ini. + This function will be called automatically when other api funcion is called + firstly. + **/ +/*--------------------------------------------------------------------------*/ +static inline int IniParserInit() { + return 0; +} + +/*-------------------------------------------------------------------------*/ +/** + @brief Free all memory associated + @return void + + Free all memory associated to ini dictionary. + */ +/*--------------------------------------------------------------------------*/ +static inline void IniParserDestory() { + +} + +/*-------------------------------------------------------------------------*/ +/** + @brief Get the string associated to a key + @param key Key string to look for + @param def Default value to return if key not found. + @return pointer to statically allocated character string + + This function queries for a key. A key as read from an + ini file is given as "section:key". If the key cannot be found, + the pointer passed as 'def' is returned. + The returned char pointer is pointing to a string allocated in + the dictionary, do not free or modify it. + */ +/*--------------------------------------------------------------------------*/ +/*static inline const char * IniParserGetString(const char * key, const char * def) { + +}*/ + +/*-------------------------------------------------------------------------*/ +/** + @brief Get the string associated to a key, convert to an int + @param key Key string to look for + @param notfound Value to return in case of error + @return integer + + This function queries for a key. A key as read from an + ini file is given as "section:key". If the key cannot be found, + the notfound value is returned. + + Supported values for integers include the usual C notation + so decimal, octal (starting with 0) and hexadecimal (starting with 0x) + are supported. Examples: + + - "42" -> 42 + - "042" -> 34 (octal -> decimal) + - "0x42" -> 66 (hexa -> decimal) + + Warning: the conversion may overflow in various ways. Conversion is + totally outsourced to strtol(), see the associated man page for overflow + handling. + */ +/*--------------------------------------------------------------------------*/ +static inline int IniParserGetInt(const char * key, int notfound) { + return notfound; +} + +/*-------------------------------------------------------------------------*/ +/** + @brief Get the string associated to a key, convert to a double + @param key Key string to look for + @param notfound Value to return in case of error + @return double + + This function queries a dictionary for a key. A key as read from an + ini file is given as "section:key". If the key cannot be found, + the notfound value is returned. + */ +/*--------------------------------------------------------------------------*/ +static inline double IniparserGetDouble(const char * key, double notfound) { + return notfound; +} + +/*-------------------------------------------------------------------------*/ +/** + @brief Get the string associated to a key, convert to a boolean + @param key Key string to look for + @param notfound Value to return in case of error + @return integer + + This function queries for a key. A key as read from an + ini file is given as "section:key". If the key cannot be found, + the notfound value is returned. + + A true boolean is found if one of the following is matched: + + - A string starting with 'y' + - A string starting with 'Y' + - A string starting with 't' + - A string starting with 'T' + - A string starting with '1' + + A false boolean is found if one of the following is matched: + + - A string starting with 'n' + - A string starting with 'N' + - A string starting with 'f' + - A string starting with 'F' + - A string starting with '0' + + The notfound value returned if no boolean is identified, does not + necessarily have to be 0 or 1. + */ +/*--------------------------------------------------------------------------*/ +static inline int IniParserGetBoolean(const char * key, int notfound) { + return notfound; +} + +/*-------------------------------------------------------------------------*/ +/** + @brief Finds out if a given entry exists + @param entry Name of the entry to look for + @return integer 1 if entry exists, 0 otherwise + + Finds out if a given entry exists in the dictionary. Since sections + are stored as keys with NULL associated values, this is the only way + of querying for the presence of sections in a dictionary. + */ +/*--------------------------------------------------------------------------*/ +//int IniParserFindEntry(const char * entry); + +static inline int GetConfigParamterInt(const char * key, int notfound) { + return notfound; +} + +//const char * GetConfigParamterString(const char * key, const char * def); + +static inline double GetConfigParamterDouble(const char * key, double notfound) { + return notfound; +} +//int GetConfigParamterBoolean(const char * key, int notfound); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/external/include/adecoder/adecoder.h b/platform/mcu/xr871/src/cedarx/external/include/adecoder/adecoder.h new file mode 100644 index 0000000000..a26c8667c0 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/external/include/adecoder/adecoder.h @@ -0,0 +1,434 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : adecoder.h +* Description : +* History : +* Author : gvc-al2 +* Date : long long ago +*/ + +#ifndef ADECODER_H +#define ADECODER_H + +#include "unistd.h" +//#include +//typedef signed long long int64_t; +//typedef int int32_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#define AUDIO_BITSTREAM_BUFFER_SIZE (1024 * 6)//(1024*4096) +#define AUDIO_BITSTREAM_BUFFER_MAX_FRAME_NUM (6)//(4096) +#define AUDIO_PCM_BUFFER_SIZE (16 * 1024)//(512*1024) + +typedef enum __AUDIO_DEC_RESULT +{ + ERR_AUDIO_DEC_EXIT = -4, // exit + ERR_AUDIO_DEC_ENDINGCHKFAIL = -3, //big ending or little ending check failed + ERR_AUDIO_DEC_ABSEND = -2, //audio bitstream decode end + ERR_AUDIO_DEC_ONEFRMFAIL = -1, //decode one frame failed, can try again + + ERR_AUDIO_DEC_NONE = 0, //decode successed, no error + ERR_AUDIO_DEC_FFREVRETURN = 1, //return from fast-forward or fast-reverse + ERR_AUDIO_DEC_RETAPOINT = 2, //return from A point under A/B play mode + ERR_AUDIO_DEC_RETTAG = 3, //return from the first frame of tag play + ERR_AUDIO_DEC_VIDEOJUMP = 4, //0X88 maybe return 4 or 0 + ERR_AUDIO_DEC_NO_BITSTREAM = 5, //No enough bitstream ,try again + ERR_AUDIO_DEC_ + +} __audio_dec_result_t; + +enum EAUDIOCODECFORMAT +{ + AUDIO_CODEC_FORMAT_UNKNOWN = 0, + AUDIO_CODEC_FORMAT_MP1, + AUDIO_CODEC_FORMAT_MP2, + AUDIO_CODEC_FORMAT_MP3, + AUDIO_CODEC_FORMAT_MPEG_AAC_LC, + AUDIO_CODEC_FORMAT_AC3, //* not supported. + AUDIO_CODEC_FORMAT_DTS, //* not supported. + AUDIO_CODEC_FORMAT_LPCM_V, + AUDIO_CODEC_FORMAT_LPCM_A, + AUDIO_CODEC_FORMAT_ADPCM, + AUDIO_CODEC_FORMAT_PCM, + AUDIO_CODEC_FORMAT_WMA_STANDARD, + AUDIO_CODEC_FORMAT_FLAC, + AUDIO_CODEC_FORMAT_APE, + AUDIO_CODEC_FORMAT_OGG, + AUDIO_CODEC_FORMAT_RAAC, + AUDIO_CODEC_FORMAT_COOK, + AUDIO_CODEC_FORMAT_SIPR, + AUDIO_CODEC_FORMAT_ATRC, + AUDIO_CODEC_FORMAT_AMR, + AUDIO_CODEC_FORMAT_RA, + AUDIO_CODEC_FORMAT_PPCM, //* not supported. + AUDIO_CODEC_FORMAT_WMA_LOSS, //* not supported. + AUDIO_CODEC_FORMAT_WMA_PRO, //* not supported. + AUDIO_CODEC_FORMAT_MP3_PRO, //* not supported. + AUDIO_CODEC_FORMAT_ALAC, + AUDIO_CODEC_FORMAT_G729, + AUDIO_CODEC_FORMAT_DSD, + AUDIO_CODEC_FORMAT_OPUS, + AUDIO_CODEC_FORMAT_MLP = AUDIO_CODEC_FORMAT_AC3, + AUDIO_CODEC_FORMAT_ = -1, +}; + +//**************************************************************************// +//* Below are definition for sub codec types. +//**************************************************************************// +#define ABS_EDIAN_FLAG_MASK ((unsigned int)(1<<16)) +#define ABS_EDIAN_FLAG_BIG ((unsigned int)(1<<16)) + +/* Windows WAVE File Encoding Tags */ +#define WAVE_FORMAT_UNKNOWN 0x0000 /* Unknown Format */ +#define WAVE_FORMAT_PCM 0x0001 /* PCM */ +#define WAVE_FORMAT_ADPCM 0x0002 /* Microsoft ADPCM Format */ +#define WAVE_FORMAT_IEEE_FLOAT 0x0003 /* IEEE Float */ +#define WAVE_FORMAT_VSELP 0x0004 /* Compaq Computer's VSELP */ +#define WAVE_FORMAT_IBM_CVSD 0x0005 /* IBM CVSD */ +#define WAVE_FORMAT_ALAW 0x0006 /* ALAW */ +#define WAVE_FORMAT_MULAW 0x0007 /* MULAW */ +#define WAVE_FORMAT_DTS 0x0008 /* Microsoft Corporation */ +#define WAVE_FORMAT_DRM 0x0009 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAVOICE9 0x000A /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAVOICE10 0x000B /* Microsoft Corporation */ +#define WAVE_FORMAT_OKI_ADPCM 0x0010 /* OKI ADPCM */ +#define WAVE_FORMAT_DVI_ADPCM 0x0011 /* Intel's DVI ADPCM */ +#define WAVE_FORMAT_IMA_ADPCM (WAVE_FORMAT_DVI_ADPCM) /* Intel Corporation */ +#define WAVE_FORMAT_MEDIASPACE_ADPCM 0x0012 /* Videologic's MediaSpace ADPCM*/ +#define WAVE_FORMAT_SIERRA_ADPCM 0x0013 /* Sierra ADPCM */ +#define WAVE_FORMAT_G723_ADPCM 0x0014 /* G.723 ADPCM */ +#define WAVE_FORMAT_DIGISTD 0x0015 /* DSP Solution's DIGISTD */ +#define WAVE_FORMAT_DIGIFIX 0x0016 /* DSP Solution's DIGIFIX */ +#define WAVE_FORMAT_DIALOGIC_OKI_ADPCM 0x0017 /* Dialogic OKI ADPCM */ +#define WAVE_FORMAT_MEDIAVISION_ADPCM 0x0018 /* MediaVision ADPCM */ +#define WAVE_FORMAT_CU_CODEC 0x0019 /* HP CU */ +#define WAVE_FORMAT_YAMAHA_ADPCM 0x0020 /* Yamaha ADPCM */ +#define WAVE_FORMAT_SONARC 0x0021 /* Speech Compression's Sonarc */ +#define WAVE_FORMAT_TRUESPEECH 0x0022 /* DSP Group's True Speech */ +#define WAVE_FORMAT_ECHOSC1 0x0023 /* Echo Speech's EchoSC1 */ +#define WAVE_FORMAT_AUDIOFILE_AF36 0x0024 /* Audiofile AF36 */ +#define WAVE_FORMAT_APTX 0x0025 /* APTX */ +#define WAVE_FORMAT_AUDIOFILE_AF10 0x0026 /* AudioFile AF10 */ +#define WAVE_FORMAT_PROSODY_1612 0x0027 /* Prosody 1612 */ +#define WAVE_FORMAT_LRC 0x0028 /* LRC */ +#define WAVE_FORMAT_AC2 0x0030 /* Dolby AC2 */ +#define WAVE_FORMAT_GSM610 0x0031 /* GSM610 */ +#define WAVE_FORMAT_MSNAUDIO 0x0032 /* MSNAudio */ +#define WAVE_FORMAT_ANTEX_ADPCME 0x0033 /* Antex ADPCME */ +#define WAVE_FORMAT_CONTROL_RES_VQLPC 0x0034 /* Control Res VQLPC */ +#define WAVE_FORMAT_DIGIREAL 0x0035 /* Digireal */ +#define WAVE_FORMAT_DIGIADPCM 0x0036 /* DigiADPCM */ +#define WAVE_FORMAT_CONTROL_RES_CR10 0x0037 /* Control Res CR10 */ +#define WAVE_FORMAT_VBXADPCM 0x0038 /* NMS VBXADPCM */ +#define WAVE_FORMAT_ROLAND_RDAC 0x0039 /* Roland RDAC */ +#define WAVE_FORMAT_ECHOSC3 0x003A /* EchoSC3 */ +#define WAVE_FORMAT_ROCKWELL_ADPCM 0x003B /* Rockwell ADPCM */ +#define WAVE_FORMAT_ROCKWELL_DIGITALK 0x003C /* Rockwell Digit LK */ +#define WAVE_FORMAT_XEBEC 0x003D /* Xebec */ +#define WAVE_FORMAT_G721_ADPCM 0x0040 /* Antex Electronics G.721 */ +#define WAVE_FORMAT_G728_CELP 0x0041 /* G.728 CELP */ +#define WAVE_FORMAT_MSG723 0x0042 /* MSG723 */ +#define WAVE_FORMAT_MPEG 0x0050 /* MPEG Layer 1,2 */ +#define WAVE_FORMAT_RT24 0x0051 /* RT24 */ +#define WAVE_FORMAT_PAC 0x0051 /* PAC */ +#define WAVE_FORMAT_MPEGLAYER3 0x0055 /* MPEG Layer 3 */ +//#define WAVE_FORMAT_CIRRUS 0x0059 /* Cirrus */ +#define WAVE_FORMAT_LUCENT_G723 0x0059 /* Lucent Technologies */ +#define WAVE_FORMAT_CIRRUS 0x0060 /* Cirrus Logic */ +#define WAVE_FORMAT_ESPCM 0x0061 /* ESPCM */ +#define WAVE_FORMAT_VOXWARE 0x0062 /* Voxware (obsolete) */ +#define WAVE_FORMAT_CANOPUS_ATRAC 0x0063 /* Canopus Atrac */ +#define WAVE_FORMAT_G726_ADPCM 0x0064 /* G.726 ADPCM */ +#define WAVE_FORMAT_G722_ADPCM 0x0065 /* G.722 ADPCM */ +#define WAVE_FORMAT_DSAT 0x0066 /* DSAT */ +#define WAVE_FORMAT_DSAT_DISPLAY 0x0067 /* DSAT Display */ +#define WAVE_FORMAT_VOXWARE_BYTE_ALIGNED 0x0069 /* Voxware Byte Aligned (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC8 0x0070 /* Voxware AC8 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC10 0x0071 /* Voxware AC10 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC16 0x0072 /* Voxware AC16 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_AC20 0x0073 /* Voxware AC20 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_RT24 0x0074 /* Voxware MetaVoice (obsolete) */ +#define WAVE_FORMAT_VOXWARE_RT29 0x0075 /* Voxware MetaSound (obsolete) */ +#define WAVE_FORMAT_VOXWARE_RT29HW 0x0076 /* Voxware RT29HW (obsolete) */ +#define WAVE_FORMAT_VOXWARE_VR12 0x0077 /* Voxware VR12 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_VR18 0x0078 /* Voxware VR18 (obsolete) */ +#define WAVE_FORMAT_VOXWARE_TQ40 0x0079 /* Voxware TQ40 (obsolete) */ +#define WAVE_FORMAT_SOFTSOUND 0x0080 /* Softsound */ +#define WAVE_FORMAT_VOXWARE_TQ60 0x0081 /* Voxware TQ60 (obsolete) */ +#define WAVE_FORMAT_MSRT24 0x0082 /* MSRT24 */ +#define WAVE_FORMAT_G729A 0x0083 /* G.729A */ +#define WAVE_FORMAT_MVI_MV12 0x0084 /* MVI MV12 */ +#define WAVE_FORMAT_DF_G726 0x0085 /* DF G.726 */ +#define WAVE_FORMAT_DF_GSM610 0x0086 /* DF GSM610 */ +#define WAVE_FORMAT_ISIAUDIO 0x0088 /* ISIAudio */ +#define WAVE_FORMAT_ONLIVE 0x0089 /* Onlive */ +#define WAVE_FORMAT_SBC24 0x0091 /* SBC24 */ +#define WAVE_FORMAT_DOLBY_AC3_SPDIF 0x0092 /* Dolby AC3 SPDIF */ +#define WAVE_FORMAT_MEDIASONIC_G723 0x0093 /* MediaSonic */ +#define WAVE_FORMAT_PROSODY_8KBPS 0x0094 /* Aculab plc */ +#define WAVE_FORMAT_ZYXEL_ADPCM 0x0097 /* ZyXEL ADPCM */ +#define WAVE_FORMAT_PHILIPS_LPCBB 0x0098 /* Philips LPCBB */ +#define WAVE_FORMAT_PACKED 0x0099 /* Packed */ +#define WAVE_FORMAT_MALDEN_PHONYTALK 0x00A0 /* Malden Electronics Ltd. */ +#define WAVE_FORMAT_RHETOREX_ADPCM 0x0100 /* Rhetorex ADPCM */ +#define WAVE_FORMAT_IRAT 0x0101 /* BeCubed Software's IRAT */ +#define WAVE_FORMAT_VIVO_G723 0x0111 /* Vivo G.723 */ +#define WAVE_FORMAT_VIVO_SIREN 0x0112 /* Vivo Siren */ +#define WAVE_FORMAT_DIGITAL_G723 0x0123 /* Digital G.723 */ +#define WAVE_FORMAT_SANYO_LD_ADPCM 0x0125 /* Sanyo Electric Co., Ltd. */ +#define WAVE_FORMAT_SIPROLAB_ACEPLNET 0x0130 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_ACELP4800 0x0131 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_ACELP8V3 0x0132 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_G729 0x0133 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_G729A 0x0134 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_SIPROLAB_KELVIN 0x0135 /* Sipro Lab Telecom Inc. */ +#define WAVE_FORMAT_G726ADPCM 0x0140 /* Dictaphone Corporation */ +#define WAVE_FORMAT_QUALCOMM_PUREVOICE 0x0150 /* Qualcomm, Inc. */ +#define WAVE_FORMAT_QUALCOMM_HALFRATE 0x0151 /* Qualcomm, Inc. */ +#define WAVE_FORMAT_TUBGSM 0x0155 /* Ring Zero Systems, Inc. */ +#define WAVE_FORMAT_MSAUDIO1 0x0160 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAUDIO2 0x0161 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAUDIO3 0x0162 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMAUDIO_LOSSLESS 0x0163 /* Microsoft Corporation */ +#define WAVE_FORMAT_WMASPDIF 0x0164 /* Microsoft Corporation */ +#define WAVE_FORMAT_UNISYS_NAP_ADPCM 0x0170 /* Unisys Corp. */ +#define WAVE_FORMAT_UNISYS_NAP_ULAW 0x0171 /* Unisys Corp. */ +#define WAVE_FORMAT_UNISYS_NAP_ALAW 0x0172 /* Unisys Corp. */ +#define WAVE_FORMAT_UNISYS_NAP_16K 0x0173 /* Unisys Corp. */ +#define WAVE_FORMAT_CREATIVE_ADPCM 0x0200 /* Creative ADPCM */ +#define WAVE_FORMAT_CREATIVE_FASTSPEECH8 0x0202 /* Creative FastSpeech8 */ +#define WAVE_FORMAT_CREATIVE_FASTSPEECH10 0x0203 /* Creative FastSpeech10 */ +#define WAVE_FORMAT_UHER_ADPCM 0x0210 /* UHER informatic GmbH */ +#define WAVE_FORMAT_QUARTERDECK 0x0220 /* Quarterdeck */ +#define WAVE_FORMAT_ILINK_VC 0x0230 /* I-link Worldwide */ +#define WAVE_FORMAT_RAW_SPORT 0x0240 /* Aureal Semiconductor */ +#define WAVE_FORMAT_ESST_AC3 0x0241 /* ESS Technology, Inc. */ +#define WAVE_FORMAT_GENERIC_PASSTHRU 0x0249 +#define WAVE_FORMAT_IPI_HSX 0x0250 /* Interactive Products, Inc. */ +#define WAVE_FORMAT_IPI_RPELP 0x0251 /* Interactive Products, Inc. */ +#define WAVE_FORMAT_CS2 0x0260 /* Consistent Software */ +#define WAVE_FORMAT_SONY_SCX 0x0270 /* Sony Corp. */ +#define WAVE_FORMAT_FM_TOWNS_SND 0x0300 /* FM Towns Snd */ +#define WAVE_FORMAT_BTV_DIGITAL 0x0400 /* BTV Digital */ +#define WAVE_FORMAT_QDESIGN_MUSIC 0x0450 /* QDesign Corporation */ +#define WAVE_FORMAT_VME_VMPCM 0x0680 /* VME VMPCM */ +#define WAVE_FORMAT_TPC 0x0681 /* AT&T Labs, Inc. */ +#define WAVE_FORMAT_OLIGSM 0x1000 /* OLIGSM */ +#define WAVE_FORMAT_OLIADPCM 0x1001 /* OLIADPCM */ +#define WAVE_FORMAT_OLICELP 0x1002 /* OLICELP */ +#define WAVE_FORMAT_OLISBC 0x1003 /* OLISBC */ +#define WAVE_FORMAT_OLIOPR 0x1004 /* OLIOPR */ +#define WAVE_FORMAT_LH_CODEC 0x1100 /* LH Codec */ +#define WAVE_FORMAT_NORRIS 0x1400 /* Norris */ +//#define WAVE_FORMAT_ISIAUDIO 0x1401 /* ISIAudio */ +#define WAVE_FORMAT_SOUNDSPACE_MUSICOMPRESS 0x1500 /* Soundspace Music Compression */ +#define WAVE_FORMAT_MPEG_ADTS_AAC 0x1600 /* Microsoft Corporation */ +#define WAVE_FORMAT_MPEG_RAW_AAC 0x1601 /* Microsoft Corporation */ +#define WAVE_FORMAT_NOKIA_MPEG_ADTS_AAC 0x1608 /* Microsoft Corporation */ +#define WAVE_FORMAT_NOKIA_MPEG_RAW_AAC 0x1609 /* Microsoft Corporation */ +#define WAVE_FORMAT_VODAFONE_MPEG_ADTS_AAC 0x160A /* Microsoft Corporation */ +#define WAVE_FORMAT_VODAFONE_MPEG_RAW_AAC 0x160B /* Microsoft Corporation */ +#define WAVE_FORMAT_DVM 0x2000 /* DVM */ +#define WAVE_FORMAT_EXTENSIBTSMIRACAST 0xFFFC /* LSZHANG TS Miracast WIFI*/ +#define WAVE_FORMAT_EXTENSIBTS 0xFFFD /* LSZHANG TS */ +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* SubFormat */ +#define WAVE_FORMAT_DEVELOPMENT 0xFFFF /* Development */ +#define WAVE_FORMAT_DVD_LPCM 0xFFA0 /* Added by Khan for DVD-LPCM*/ + +//user define adpcm codec type from video file +#define ADPCM_CODEC_ID_IMA_QT 0xE000 +#define ADPCM_CODEC_ID_IMA_WAV 0xE001 /* from avi file format */ +#define ADPCM_CODEC_ID_IMA_DK3 0xE002 +#define ADPCM_CODEC_ID_IMA_DK4 0xE003 +#define ADPCM_CODEC_ID_IMA_WS 0xE004 +#define ADPCM_CODEC_ID_IMA_SMJPEG 0xE005 +#define ADPCM_CODEC_ID_MS 0xE006 +#define ADPCM_CODEC_ID_4XM 0xE007 +#define ADPCM_CODEC_ID_XA 0xE008 +#define ADPCM_CODEC_ID_ADX 0xE009 +#define ADPCM_CODEC_ID_EA 0xE00A +#define ADPCM_CODEC_ID_G726 0xE00B +#define ADPCM_CODEC_ID_CT 0xE00C +#define ADPCM_CODEC_ID_SWF 0xE00D /* from flv/swf file format */ +#define ADPCM_CODEC_ID_YAMAHA 0xE00E +#define ADPCM_CODEC_ID_SBPRO_4 0xE00F +#define ADPCM_CODEC_ID_SBPRO_3 0xE010 +#define ADPCM_CODEC_ID_SBPRO_2 0xE011 + +#define AMR_FORMAT_NONE 0 // undefine amr format +#define AMR_FORMAT_NARROWBAND 1 // narrow band amr format +#define AMR_FORMAT_WIDEBAND 2 // wide band amr format + +#define ADECODER_MAX_LANG_CHAR_SIZE (64) + +typedef struct Cedar_raw_data CdxPlaybkCfg; + +enum AUIDO_RAW_DATA_TYPE +{ + AUDIO_RAW_DATA_UNKOWN = 0, + AUDIO_RAW_DATA_PCM = 1, + AUDIO_RAW_DATA_AC3 = 2, + AUDIO_RAW_DATA_MPEG1 = 3, + AUDIO_RAW_DATA_MP3 = 4, + AUDIO_RAW_DATA_MPEG2 = 5, + AUDIO_RAW_DATA_AAC = 6, + AUDIO_RAW_DATA_DTS = 7, + AUDIO_RAW_DATA_ATRAC = 8, + AUDIO_RAW_DATA_ONE_BIT_AUDIO = 9, + AUDIO_RAW_DATA_DOLBY_DIGITAL_PLUS = 10, + AUDIO_RAW_DATA_DTS_HD = 11, + AUDIO_RAW_DATA_MAT = 12, + AUDIO_RAW_DATA_DST = 13, + AUDIO_RAW_DATA_WMAPRO = 14 +}; + +struct Cedar_raw_data +{ + int nRoutine;//UI set 0:pcm;1:hdmi raw data;2:spdif raw data; + int nNeedDirect;//if init flag 0:no init raw;1:init raw + int nChannels; + int nSamplerate; + int nBitpersample; + enum AUIDO_RAW_DATA_TYPE nDataType; +}; + +typedef struct AUDIOSTREAMINFO +{ + enum EAUDIOCODECFORMAT eCodecFormat; + int eSubCodecFormat; // + int nChannelNum; + int nBitsPerSample; + int nSampleRate; + int nAvgBitrate; + int nMaxBitRate; + unsigned int nFileSize; + int eAudioBitstreamSource; + int eDataEncodeType; + unsigned char strLang[ADECODER_MAX_LANG_CHAR_SIZE]; + int nCodecSpecificDataLen; + char* pCodecSpecificData; + int nFlags; + int nBlockAlign; + CdxPlaybkCfg raw_data; +}AudioStreamInfo; + +typedef struct __BsInFor +{ + int TotalplayTime; + int NowPlayTime; + int Samplerate; + int bitrate; + int chan; + int CBRflag;//1 cbr 0 vbr + int framesize; + int framecount; + int oldfs; + int oldbs; + int firstflag; + int framepcms; + int modeflag;//flag 0bits: 1:raw data 0:pcm + int ulMode;//decode flag 0:pcm ,>raw data out ,1:hdmi,2:spdif + int bitpersample;//bits per sample + //add for control from ad_cedar_ctx + int nBitStreamUnderFlow; + int nShowBitsReturn; + int out_channels; + int out_samplerate; + //global + int nDecodeMode; + int nDemuxType; + int nIsHwCodec; + int64_t NowPTSTime; + +}BsInFor; + +typedef struct AudioDecoder AudioDecoder; +struct AudioDecoder +{ + int nPrivFlag;//0:play,1:reset,2:file end + int nGetAudioInfoFlag; + int nAudioChannel; + int volumegain; + int mute; + int nEnableResample; + int RawPlayFlag; +}; + +int ParserRequestBsBuffer(AudioDecoder* pDecoder, + int nRequireSize, + unsigned char** ppBuf, + int* pBufSize, + unsigned char** ppRingBuf, + int* pRingBufSize, + int* nOffset); + +int ParserUpdateBsBuffer(AudioDecoder* pDecoder, + int nFilledLen, + int64_t nTimeStamp, + int nOffset); + +void BsQueryQuality(AudioDecoder* pDecoder, + int* pValidPercent, + int* vbv); + +int AudioStreamDataSize(AudioDecoder* pDecoder); + +int AudioStreamBufferSize(void); + +int AudioStreamBufferMaxFrameNum(void); + +int AudioPCMDataSize(AudioDecoder* pDecoder); + +int DecRequestPcmBuffer(AudioDecoder* pDecoder, char **pOutWritePtr); + +int DecUpdatePcmBuffer(AudioDecoder* pDecoder, int nPcmOutSize); + +int PlybkRequestPcmBuffer(AudioDecoder* pDecoder, unsigned char **pOutReadPtr, int *psize); + +int PlybkUpdatePcmBuffer(AudioDecoder* pDecoder, int nPcmOutSize); + +int64_t PlybkRequestPcmPts(AudioDecoder* pDecoder); + +void PcmQueryQuality(AudioDecoder* pDecoder, int* pValidPercent, int* vbv); + +void AudioDecoderSeek(AudioDecoder* pDecoder, int64_t nSeekTime); + +int InitializeAudioDecoder(AudioDecoder* pDecoder, + AudioStreamInfo* pAudioStreamInfo, + BsInFor* pBsInFor); + +int ResetAudioDecoder(AudioDecoder* pDecoder, int64_t nSeekTime); + +int DecodeAudioStream(AudioDecoder* pDecoder, + AudioStreamInfo* pAudioStreamInfo, + char* ppBuf, + int* pBufSize); + +int DestroyAudioDecoder(AudioDecoder* pDecoder); + +AudioDecoder* CreateAudioDecoder(void); + +#if defined(__ANDROID__) +void SetRawPlayParam(AudioDecoder* pDecoder,void *self); +#else +void SetRawPlayParam(AudioDecoder* pDecoder,void *self,int flag); +#endif + +#if defined(__ANDROID__) +void AudioSoundTouchSetPitch(AudioDecoder* pDecoder, float pitchDelta); +#endif + +#if !defined(__ANDROID__) +int SetAudioVolume(AudioDecoder* pDecoder, int32_t nVolume); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/external/include/aencoder/aencoder.h b/platform/mcu/xr871/src/cedarx/external/include/aencoder/aencoder.h new file mode 100644 index 0000000000..297dea61db --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/external/include/aencoder/aencoder.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : aencoder.h + * Description : audio encoder api + * History : + * + */ + +#ifndef AUDIO_ENCODER_H +#define AUDIO_ENCODER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMR_ENCODER (1) +#define PCM_ENCODER (1) + +typedef enum __AUDIO_ENC_RESULT +{ + ERR_AUDIO_ENC_ABSEND = -2, + ERR_AUDIO_ENC_UNKNOWN = -1, + ERR_AUDIO_ENC_NONE = 0, //decode successed, no error + ERR_AUDIO_ENC_PCMUNDERFLOW = 1, //pcm data is underflow + ERR_AUDIO_ENC_OUTFRAME_UNDERFLOW = 2, //out frame buffer is underflow. + ERR_AUDIO_ENC_ +} __audio_enc_result_t; + + +enum AUDIO_ENCODER_TYPE +{ +#if OTHER_ENCODER + AUDIO_ENCODER_AAC_TYPE, + AUDIO_ENCODER_LPCM_TYPE, //only used by mpeg2ts + AUDIO_ENCODER_MP3_TYPE, +#endif +#if PCM_ENCODER + AUDIO_ENCODER_PCM_TYPE, +#endif +#if AMR_ENCODER + AUDIO_ENCODER_AMR_TYPE, +#endif +}; + +typedef enum AUDIO_ENCODER_TYPE AUDIO_ENCODER_TYPE; + +typedef struct AudioEncConfig +{ + AUDIO_ENCODER_TYPE nType; + int nInSamplerate; //fs + int nInChan; //pcm chan 1:mon 2:stereo + int nBitrate; //bs + int nSamplerBits; //only for 16bits + int nOutSamplerate; //fs,now OutSamplerate must equal InSamplerate + int nOutChan; // chan + + //for aac: 0:add head,1:raw data; + //for pcm: 2:mpegTs pcm(big endian), + //other: common pcm(little endian) + int nFrameStyle; +}AudioEncConfig; + +typedef void* AudioEncoder; + +AudioEncoder* CreateAudioEncoder(); +void DestroyAudioEncoder(AudioEncoder* pEncoder); +int InitializeAudioEncoder(AudioEncoder *pEncoder, AudioEncConfig *pConfig); +int ResetAudioEncoder(AudioEncoder* pEncoder); +int EncodeAudioStream(AudioEncoder *pEncoder); +int WriteAudioStreamBuffer(AudioEncoder *pEncoder, char* pBuf, int len); +int RequestAudioFrameBuffer(AudioEncoder *pEncoder, char **pOutBuf, + unsigned int *size, long long *pts, int *bufId); +int ReturnAudioFrameBuffer(AudioEncoder *pEncoder, char *pOutBuf, + unsigned int size, long long pts, int bufId); + + +#ifdef __cplusplus +} +#endif + +#endif // AUDIO_ENC_API_H + diff --git a/platform/mcu/xr871/src/cedarx/external/include/zlib/zconf.h b/platform/mcu/xr871/src/cedarx/external/include/zlib/zconf.h new file mode 100644 index 0000000000..996fff2921 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/external/include/zlib/zconf.h @@ -0,0 +1,511 @@ +/* zconf.h -- configuration of the zlib compression library + * Copyright (C) 1995-2013 Jean-loup Gailly. + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* @(#) $Id$ */ + +#ifndef ZCONF_H +#define ZCONF_H + +/* + * If you *really* need a unique prefix for all types and library functions, + * compile with -DZ_PREFIX. The "standard" zlib should be compiled without it. + * Even better than compiling with -DZ_PREFIX would be to use configure to set + * this permanently in zconf.h using "./configure --zprefix". + */ +#ifdef Z_PREFIX /* may be set to #if 1 by ./configure */ +# define Z_PREFIX_SET + +/* all linked symbols */ +# define _dist_code z__dist_code +# define _length_code z__length_code +# define _tr_align z__tr_align +# define _tr_flush_bits z__tr_flush_bits +# define _tr_flush_block z__tr_flush_block +# define _tr_init z__tr_init +# define _tr_stored_block z__tr_stored_block +# define _tr_tally z__tr_tally +# define adler32 z_adler32 +# define adler32_combine z_adler32_combine +# define adler32_combine64 z_adler32_combine64 +# ifndef Z_SOLO +# define compress z_compress +# define compress2 z_compress2 +# define compressBound z_compressBound +# endif +# define crc32 z_crc32 +# define crc32_combine z_crc32_combine +# define crc32_combine64 z_crc32_combine64 +# define deflate z_deflate +# define deflateBound z_deflateBound +# define deflateCopy z_deflateCopy +# define deflateEnd z_deflateEnd +# define deflateInit2_ z_deflateInit2_ +# define deflateInit_ z_deflateInit_ +# define deflateParams z_deflateParams +# define deflatePending z_deflatePending +# define deflatePrime z_deflatePrime +# define deflateReset z_deflateReset +# define deflateResetKeep z_deflateResetKeep +# define deflateSetDictionary z_deflateSetDictionary +# define deflateSetHeader z_deflateSetHeader +# define deflateTune z_deflateTune +# define deflate_copyright z_deflate_copyright +# define get_crc_table z_get_crc_table +# ifndef Z_SOLO +# define gz_error z_gz_error +# define gz_intmax z_gz_intmax +# define gz_strwinerror z_gz_strwinerror +# define gzbuffer z_gzbuffer +# define gzclearerr z_gzclearerr +# define gzclose z_gzclose +# define gzclose_r z_gzclose_r +# define gzclose_w z_gzclose_w +# define gzdirect z_gzdirect +# define gzdopen z_gzdopen +# define gzeof z_gzeof +# define gzerror z_gzerror +# define gzflush z_gzflush +# define gzgetc z_gzgetc +# define gzgetc_ z_gzgetc_ +# define gzgets z_gzgets +# define gzoffset z_gzoffset +# define gzoffset64 z_gzoffset64 +# define gzopen z_gzopen +# define gzopen64 z_gzopen64 +# ifdef _WIN32 +# define gzopen_w z_gzopen_w +# endif +# define gzprintf z_gzprintf +# define gzvprintf z_gzvprintf +# define gzputc z_gzputc +# define gzputs z_gzputs +# define gzread z_gzread +# define gzrewind z_gzrewind +# define gzseek z_gzseek +# define gzseek64 z_gzseek64 +# define gzsetparams z_gzsetparams +# define gztell z_gztell +# define gztell64 z_gztell64 +# define gzungetc z_gzungetc +# define gzwrite z_gzwrite +# endif +# define inflate z_inflate +# define inflateBack z_inflateBack +# define inflateBackEnd z_inflateBackEnd +# define inflateBackInit_ z_inflateBackInit_ +# define inflateCopy z_inflateCopy +# define inflateEnd z_inflateEnd +# define inflateGetHeader z_inflateGetHeader +# define inflateInit2_ z_inflateInit2_ +# define inflateInit_ z_inflateInit_ +# define inflateMark z_inflateMark +# define inflatePrime z_inflatePrime +# define inflateReset z_inflateReset +# define inflateReset2 z_inflateReset2 +# define inflateSetDictionary z_inflateSetDictionary +# define inflateGetDictionary z_inflateGetDictionary +# define inflateSync z_inflateSync +# define inflateSyncPoint z_inflateSyncPoint +# define inflateUndermine z_inflateUndermine +# define inflateResetKeep z_inflateResetKeep +# define inflate_copyright z_inflate_copyright +# define inflate_fast z_inflate_fast +# define inflate_table z_inflate_table +# ifndef Z_SOLO +# define uncompress z_uncompress +# endif +# define zError z_zError +# ifndef Z_SOLO +# define zcalloc z_zcalloc +# define zcfree z_zcfree +# endif +# define zlibCompileFlags z_zlibCompileFlags +# define zlibVersion z_zlibVersion + +/* all zlib typedefs in zlib.h and zconf.h */ +# define Byte z_Byte +# define Bytef z_Bytef +# define alloc_func z_alloc_func +# define charf z_charf +# define free_func z_free_func +# ifndef Z_SOLO +# define gzFile z_gzFile +# endif +# define gz_header z_gz_header +# define gz_headerp z_gz_headerp +# define in_func z_in_func +# define intf z_intf +# define out_func z_out_func +# define uInt z_uInt +# define uIntf z_uIntf +# define uLong z_uLong +# define uLongf z_uLongf +# define voidp z_voidp +# define voidpc z_voidpc +# define voidpf z_voidpf + +/* all zlib structs in zlib.h and zconf.h */ +# define gz_header_s z_gz_header_s +# define internal_state z_internal_state + +#endif + +#if defined(__MSDOS__) && !defined(MSDOS) +# define MSDOS +#endif +#if (defined(OS_2) || defined(__OS2__)) && !defined(OS2) +# define OS2 +#endif +#if defined(_WINDOWS) && !defined(WINDOWS) +# define WINDOWS +#endif +#if defined(_WIN32) || defined(_WIN32_WCE) || defined(__WIN32__) +# ifndef WIN32 +# define WIN32 +# endif +#endif +#if (defined(MSDOS) || defined(OS2) || defined(WINDOWS)) && !defined(WIN32) +# if !defined(__GNUC__) && !defined(__FLAT__) && !defined(__386__) +# ifndef SYS16BIT +# define SYS16BIT +# endif +# endif +#endif + +/* + * Compile with -DMAXSEG_64K if the alloc function cannot allocate more + * than 64k bytes at a time (needed on systems with 16-bit int). + */ +#ifdef SYS16BIT +# define MAXSEG_64K +#endif +#ifdef MSDOS +# define UNALIGNED_OK +#endif + +#ifdef __STDC_VERSION__ +# ifndef STDC +# define STDC +# endif +# if __STDC_VERSION__ >= 199901L +# ifndef STDC99 +# define STDC99 +# endif +# endif +#endif +#if !defined(STDC) && (defined(__STDC__) || defined(__cplusplus)) +# define STDC +#endif +#if !defined(STDC) && (defined(__GNUC__) || defined(__BORLANDC__)) +# define STDC +#endif +#if !defined(STDC) && (defined(MSDOS) || defined(WINDOWS) || defined(WIN32)) +# define STDC +#endif +#if !defined(STDC) && (defined(OS2) || defined(__HOS_AIX__)) +# define STDC +#endif + +#if defined(__OS400__) && !defined(STDC) /* iSeries (formerly AS/400). */ +# define STDC +#endif + +#ifndef STDC +# ifndef const /* cannot use !defined(STDC) && !defined(const) on Mac */ +# define const /* note: need a more gentle solution here */ +# endif +#endif + +#if defined(ZLIB_CONST) && !defined(z_const) +# define z_const const +#else +# define z_const +#endif + +/* Some Mac compilers merge all .h files incorrectly: */ +#if defined(__MWERKS__)||defined(applec)||defined(THINK_C)||defined(__SC__) +# define NO_DUMMY_DECL +#endif + +/* Maximum value for memLevel in deflateInit2 */ +#ifndef MAX_MEM_LEVEL +# ifdef MAXSEG_64K +# define MAX_MEM_LEVEL 8 +# else +# define MAX_MEM_LEVEL 9 +# endif +#endif + +/* Maximum value for windowBits in deflateInit2 and inflateInit2. + * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files + * created by gzip. (Files created by minigzip can still be extracted by + * gzip.) + */ +#ifndef MAX_WBITS +# define MAX_WBITS 15 /* 32K LZ77 window */ +#endif + +/* The memory requirements for deflate are (in bytes): + (1 << (windowBits+2)) + (1 << (memLevel+9)) + that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values) + plus a few kilobytes for small objects. For example, if you want to reduce + the default memory requirements from 256K to 128K, compile with + make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7" + Of course this will generally degrade compression (there's no free lunch). + + The memory requirements for inflate are (in bytes) 1 << windowBits + that is, 32K for windowBits=15 (default value) plus a few kilobytes + for small objects. +*/ + + /* Type declarations */ + +#ifndef OF /* function prototypes */ +# ifdef STDC +# define OF(args) args +# else +# define OF(args) () +# endif +#endif + +#ifndef Z_ARG /* function prototypes for stdarg */ +# if defined(STDC) || defined(Z_HAVE_STDARG_H) +# define Z_ARG(args) args +# else +# define Z_ARG(args) () +# endif +#endif + +/* The following definitions for FAR are needed only for MSDOS mixed + * model programming (small or medium model with some far allocations). + * This was tested only with MSC; for other MSDOS compilers you may have + * to define NO_MEMCPY in zutil.h. If you don't need the mixed model, + * just define FAR to be empty. + */ +#ifdef SYS16BIT +# if defined(M_I86SM) || defined(M_I86MM) + /* MSC small or medium model */ +# define SMALL_MEDIUM +# ifdef _MSC_VER +# define FAR _far +# else +# define FAR far +# endif +# endif +# if (defined(__SMALL__) || defined(__MEDIUM__)) + /* Turbo C small or medium model */ +# define SMALL_MEDIUM +# ifdef __BORLANDC__ +# define FAR _far +# else +# define FAR far +# endif +# endif +#endif + +#if defined(WINDOWS) || defined(WIN32) + /* If building or using zlib as a DLL, define ZLIB_DLL. + * This is not mandatory, but it offers a little performance increase. + */ +# ifdef ZLIB_DLL +# if defined(WIN32) && (!defined(__BORLANDC__) || (__BORLANDC__ >= 0x500)) +# ifdef ZLIB_INTERNAL +# define ZEXTERN extern __declspec(dllexport) +# else +# define ZEXTERN extern __declspec(dllimport) +# endif +# endif +# endif /* ZLIB_DLL */ + /* If building or using zlib with the WINAPI/WINAPIV calling convention, + * define ZLIB_WINAPI. + * Caution: the standard ZLIB1.DLL is NOT compiled using ZLIB_WINAPI. + */ +# ifdef ZLIB_WINAPI +# ifdef FAR +# undef FAR +# endif +# include + /* No need for _export, use ZLIB.DEF instead. */ + /* For complete Windows compatibility, use WINAPI, not __stdcall. */ +# define ZEXPORT WINAPI +# ifdef WIN32 +# define ZEXPORTVA WINAPIV +# else +# define ZEXPORTVA FAR CDECL +# endif +# endif +#endif + +#if defined (__BEOS__) +# ifdef ZLIB_DLL +# ifdef ZLIB_INTERNAL +# define ZEXPORT __declspec(dllexport) +# define ZEXPORTVA __declspec(dllexport) +# else +# define ZEXPORT __declspec(dllimport) +# define ZEXPORTVA __declspec(dllimport) +# endif +# endif +#endif + +#ifndef ZEXTERN +# define ZEXTERN extern +#endif +#ifndef ZEXPORT +# define ZEXPORT +#endif +#ifndef ZEXPORTVA +# define ZEXPORTVA +#endif + +#ifndef FAR +# define FAR +#endif + +#if !defined(__MACTYPES__) +typedef unsigned char Byte; /* 8 bits */ +#endif +typedef unsigned int uInt; /* 16 bits or more */ +typedef unsigned long uLong; /* 32 bits or more */ + +#ifdef SMALL_MEDIUM + /* Borland C/C++ and some old MSC versions ignore FAR inside typedef */ +# define Bytef Byte FAR +#else + typedef Byte FAR Bytef; +#endif +typedef char FAR charf; +typedef int FAR intf; +typedef uInt FAR uIntf; +typedef uLong FAR uLongf; + +#ifdef STDC + typedef void const *voidpc; + typedef void FAR *voidpf; + typedef void *voidp; +#else + typedef Byte const *voidpc; + typedef Byte FAR *voidpf; + typedef Byte *voidp; +#endif + +#if !defined(Z_U4) && !defined(Z_SOLO) && defined(STDC) +# include +# if (UINT_MAX == 0xffffffffUL) +# define Z_U4 unsigned +# elif (ULONG_MAX == 0xffffffffUL) +# define Z_U4 unsigned long +# elif (USHRT_MAX == 0xffffffffUL) +# define Z_U4 unsigned short +# endif +#endif + +#ifdef Z_U4 + typedef Z_U4 z_crc_t; +#else + typedef unsigned long z_crc_t; +#endif + +#if 1 /* was set to #if 1 by ./configure */ +# define Z_HAVE_UNISTD_H +#endif + +#if 1 /* was set to #if 1 by ./configure */ +# define Z_HAVE_STDARG_H +#endif + +#ifdef STDC +# ifndef Z_SOLO +# include /* for off_t */ +# endif +#endif + +#if defined(STDC) || defined(Z_HAVE_STDARG_H) +# ifndef Z_SOLO +# include /* for va_list */ +# endif +#endif + +#ifdef _WIN32 +# ifndef Z_SOLO +# include /* for wchar_t */ +# endif +#endif + +/* a little trick to accommodate both "#define _LARGEFILE64_SOURCE" and + * "#define _LARGEFILE64_SOURCE 1" as requesting 64-bit operations, (even + * though the former does not conform to the LFS document), but considering + * both "#undef _LARGEFILE64_SOURCE" and "#define _LARGEFILE64_SOURCE 0" as + * equivalently requesting no 64-bit operations + */ +#if defined(_LARGEFILE64_SOURCE) && -_LARGEFILE64_SOURCE - -1 == 1 +# undef _LARGEFILE64_SOURCE +#endif + +#if defined(__WATCOMC__) && !defined(Z_HAVE_UNISTD_H) +# define Z_HAVE_UNISTD_H +#endif +#ifndef Z_SOLO +# if defined(Z_HAVE_UNISTD_H) || defined(_LARGEFILE64_SOURCE) +# include /* for SEEK_*, off_t, and _LFS64_LARGEFILE */ +# ifdef VMS +# include /* for off_t */ +# endif +# ifndef z_off_t +# define z_off_t off_t +# endif +# endif +#endif + +#if defined(_LFS64_LARGEFILE) && _LFS64_LARGEFILE-0 +# define Z_LFS64 +#endif + +#if defined(_LARGEFILE64_SOURCE) && defined(Z_LFS64) +# define Z_LARGE64 +#endif + +#if defined(_FILE_OFFSET_BITS) && _FILE_OFFSET_BITS-0 == 64 && defined(Z_LFS64) +# define Z_WANT64 +#endif + +#if !defined(SEEK_SET) && !defined(Z_SOLO) +# define SEEK_SET 0 /* Seek from beginning of file. */ +# define SEEK_CUR 1 /* Seek from current position. */ +# define SEEK_END 2 /* Set file pointer to EOF plus "offset" */ +#endif + +#ifndef z_off_t +# define z_off_t long +#endif + +#if !defined(_WIN32) && defined(Z_LARGE64) +# define z_off64_t off64_t +#else +# if defined(_WIN32) && !defined(__GNUC__) && !defined(Z_SOLO) +# define z_off64_t __int64 +# else +# define z_off64_t z_off_t +# endif +#endif + +/* MVS linker does not support external names larger than 8 bytes */ +#if defined(__MVS__) + #pragma map(deflateInit_,"DEIN") + #pragma map(deflateInit2_,"DEIN2") + #pragma map(deflateEnd,"DEEND") + #pragma map(deflateBound,"DEBND") + #pragma map(inflateInit_,"ININ") + #pragma map(inflateInit2_,"ININ2") + #pragma map(inflateEnd,"INEND") + #pragma map(inflateSync,"INSY") + #pragma map(inflateSetDictionary,"INSEDI") + #pragma map(compressBound,"CMBND") + #pragma map(inflate_table,"INTABL") + #pragma map(inflate_fast,"INFA") + #pragma map(inflate_copyright,"INCOPY") +#endif + +#endif /* ZCONF_H */ diff --git a/platform/mcu/xr871/src/cedarx/external/include/zlib/zlib.h b/platform/mcu/xr871/src/cedarx/external/include/zlib/zlib.h new file mode 100644 index 0000000000..3e0c7672ac --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/external/include/zlib/zlib.h @@ -0,0 +1,1768 @@ +/* zlib.h -- interface of the 'zlib' general purpose compression library + version 1.2.8, April 28th, 2013 + + Copyright (C) 1995-2013 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + Jean-loup Gailly Mark Adler + jloup@gzip.org madler@alumni.caltech.edu + + + The data format used by the zlib library is described by RFCs (Request for + Comments) 1950 to 1952 in the files http://tools.ietf.org/html/rfc1950 + (zlib format), rfc1951 (deflate format) and rfc1952 (gzip format). +*/ + +#ifndef ZLIB_H +#define ZLIB_H + +#include "zconf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ZLIB_VERSION "1.2.8" +#define ZLIB_VERNUM 0x1280 +#define ZLIB_VER_MAJOR 1 +#define ZLIB_VER_MINOR 2 +#define ZLIB_VER_REVISION 8 +#define ZLIB_VER_SUBREVISION 0 + +/* + The 'zlib' compression library provides in-memory compression and + decompression functions, including integrity checks of the uncompressed data. + This version of the library supports only one compression method (deflation) + but other algorithms will be added later and will have the same stream + interface. + + Compression can be done in a single step if the buffers are large enough, + or can be done by repeated calls of the compression function. In the latter + case, the application must provide more input and/or consume the output + (providing more output space) before each call. + + The compressed data format used by default by the in-memory functions is + the zlib format, which is a zlib wrapper documented in RFC 1950, wrapped + around a deflate stream, which is itself documented in RFC 1951. + + The library also supports reading and writing files in gzip (.gz) format + with an interface similar to that of stdio using the functions that start + with "gz". The gzip format is different from the zlib format. gzip is a + gzip wrapper, documented in RFC 1952, wrapped around a deflate stream. + + This library can optionally read and write gzip streams in memory as well. + + The zlib format was designed to be compact and fast for use in memory + and on communications channels. The gzip format was designed for single- + file compression on file systems, has a larger header than zlib to maintain + directory information, and uses a different, slower check method than zlib. + + The library does not install any signal handler. The decoder checks + the consistency of the compressed data, so the library should never crash + even in case of corrupted input. +*/ + +typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size)); +typedef void (*free_func) OF((voidpf opaque, voidpf address)); + +struct internal_state; + +typedef struct z_stream_s { + z_const Bytef *next_in; /* next input byte */ + uInt avail_in; /* number of bytes available at next_in */ + uLong total_in; /* total number of input bytes read so far */ + + Bytef *next_out; /* next output byte should be put there */ + uInt avail_out; /* remaining free space at next_out */ + uLong total_out; /* total number of bytes output so far */ + + z_const char *msg; /* last error message, NULL if no error */ + struct internal_state FAR *state; /* not visible by applications */ + + alloc_func zalloc; /* used to allocate the internal state */ + free_func zfree; /* used to free the internal state */ + voidpf opaque; /* private data object passed to zalloc and zfree */ + + int data_type; /* best guess about the data type: binary or text */ + uLong adler; /* adler32 value of the uncompressed data */ + uLong reserved; /* reserved for future use */ +} z_stream; + +typedef z_stream FAR *z_streamp; + +/* + gzip header information passed to and from zlib routines. See RFC 1952 + for more details on the meanings of these fields. +*/ +typedef struct gz_header_s { + int text; /* true if compressed data believed to be text */ + uLong time; /* modification time */ + int xflags; /* extra flags (not used when writing a gzip file) */ + int os; /* operating system */ + Bytef *extra; /* pointer to extra field or Z_NULL if none */ + uInt extra_len; /* extra field length (valid if extra != Z_NULL) */ + uInt extra_max; /* space at extra (only when reading header) */ + Bytef *name; /* pointer to zero-terminated file name or Z_NULL */ + uInt name_max; /* space at name (only when reading header) */ + Bytef *comment; /* pointer to zero-terminated comment or Z_NULL */ + uInt comm_max; /* space at comment (only when reading header) */ + int hcrc; /* true if there was or will be a header crc */ + int done; /* true when done reading gzip header (not used + when writing a gzip file) */ +} gz_header; + +typedef gz_header FAR *gz_headerp; + +/* + The application must update next_in and avail_in when avail_in has dropped + to zero. It must update next_out and avail_out when avail_out has dropped + to zero. The application must initialize zalloc, zfree and opaque before + calling the init function. All other fields are set by the compression + library and must not be updated by the application. + + The opaque value provided by the application will be passed as the first + parameter for calls of zalloc and zfree. This can be useful for custom + memory management. The compression library attaches no meaning to the + opaque value. + + zalloc must return Z_NULL if there is not enough memory for the object. + If zlib is used in a multi-threaded application, zalloc and zfree must be + thread safe. + + On 16-bit systems, the functions zalloc and zfree must be able to allocate + exactly 65536 bytes, but will not be required to allocate more than this if + the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS, pointers + returned by zalloc for objects of exactly 65536 bytes *must* have their + offset normalized to zero. The default allocation function provided by this + library ensures this (see zutil.c). To reduce memory requirements and avoid + any allocation of 64K objects, at the expense of compression ratio, compile + the library with -DMAX_WBITS=14 (see zconf.h). + + The fields total_in and total_out can be used for statistics or progress + reports. After compression, total_in holds the total size of the + uncompressed data and may be saved for use in the decompressor (particularly + if the decompressor wants to decompress everything in a single step). +*/ + + /* constants */ + +#define Z_NO_FLUSH 0 +#define Z_PARTIAL_FLUSH 1 +#define Z_SYNC_FLUSH 2 +#define Z_FULL_FLUSH 3 +#define Z_FINISH 4 +#define Z_BLOCK 5 +#define Z_TREES 6 +/* Allowed flush values; see deflate() and inflate() below for details */ + +#define Z_OK 0 +#define Z_STREAM_END 1 +#define Z_NEED_DICT 2 +#define Z_ERRNO (-1) +#define Z_STREAM_ERROR (-2) +#define Z_DATA_ERROR (-3) +#define Z_MEM_ERROR (-4) +#define Z_BUF_ERROR (-5) +#define Z_VERSION_ERROR (-6) +/* Return codes for the compression/decompression functions. Negative values + * are errors, positive values are used for special but normal events. + */ + +#define Z_NO_COMPRESSION 0 +#define Z_BEST_SPEED 1 +#define Z_BEST_COMPRESSION 9 +#define Z_DEFAULT_COMPRESSION (-1) +/* compression levels */ + +#define Z_FILTERED 1 +#define Z_HUFFMAN_ONLY 2 +#define Z_RLE 3 +#define Z_FIXED 4 +#define Z_DEFAULT_STRATEGY 0 +/* compression strategy; see deflateInit2() below for details */ + +#define Z_BINARY 0 +#define Z_TEXT 1 +#define Z_ASCII Z_TEXT /* for compatibility with 1.2.2 and earlier */ +#define Z_UNKNOWN 2 +/* Possible values of the data_type field (though see inflate()) */ + +#define Z_DEFLATED 8 +/* The deflate compression method (the only one supported in this version) */ + +#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */ + +#define zlib_version zlibVersion() +/* for compatibility with versions < 1.0.2 */ + + + /* basic functions */ + +ZEXTERN const char * ZEXPORT zlibVersion OF((void)); +/* The application can compare zlibVersion and ZLIB_VERSION for consistency. + If the first character differs, the library code actually used is not + compatible with the zlib.h header file used by the application. This check + is automatically made by deflateInit and inflateInit. + */ + +/* +ZEXTERN int ZEXPORT deflateInit OF((z_streamp strm, int level)); + + Initializes the internal stream state for compression. The fields + zalloc, zfree and opaque must be initialized before by the caller. If + zalloc and zfree are set to Z_NULL, deflateInit updates them to use default + allocation functions. + + The compression level must be Z_DEFAULT_COMPRESSION, or between 0 and 9: + 1 gives best speed, 9 gives best compression, 0 gives no compression at all + (the input data is simply copied a block at a time). Z_DEFAULT_COMPRESSION + requests a default compromise between speed and compression (currently + equivalent to level 6). + + deflateInit returns Z_OK if success, Z_MEM_ERROR if there was not enough + memory, Z_STREAM_ERROR if level is not a valid compression level, or + Z_VERSION_ERROR if the zlib library version (zlib_version) is incompatible + with the version assumed by the caller (ZLIB_VERSION). msg is set to null + if there is no error message. deflateInit does not perform any compression: + this will be done by deflate(). +*/ + + +ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush)); +/* + deflate compresses as much data as possible, and stops when the input + buffer becomes empty or the output buffer becomes full. It may introduce + some output latency (reading input without producing any output) except when + forced to flush. + + The detailed semantics are as follows. deflate performs one or both of the + following actions: + + - Compress more input starting at next_in and update next_in and avail_in + accordingly. If not all input can be processed (because there is not + enough room in the output buffer), next_in and avail_in are updated and + processing will resume at this point for the next call of deflate(). + + - Provide more output starting at next_out and update next_out and avail_out + accordingly. This action is forced if the parameter flush is non zero. + Forcing flush frequently degrades the compression ratio, so this parameter + should be set only when necessary (in interactive applications). Some + output may be provided even if flush is not set. + + Before the call of deflate(), the application should ensure that at least + one of the actions is possible, by providing more input and/or consuming more + output, and updating avail_in or avail_out accordingly; avail_out should + never be zero before the call. The application can consume the compressed + output when it wants, for example when the output buffer is full (avail_out + == 0), or after each call of deflate(). If deflate returns Z_OK and with + zero avail_out, it must be called again after making room in the output + buffer because there might be more output pending. + + Normally the parameter flush is set to Z_NO_FLUSH, which allows deflate to + decide how much data to accumulate before producing output, in order to + maximize compression. + + If the parameter flush is set to Z_SYNC_FLUSH, all pending output is + flushed to the output buffer and the output is aligned on a byte boundary, so + that the decompressor can get all input data available so far. (In + particular avail_in is zero after the call if enough output space has been + provided before the call.) Flushing may degrade compression for some + compression algorithms and so it should be used only when necessary. This + completes the current deflate block and follows it with an empty stored block + that is three bits plus filler bits to the next byte, followed by four bytes + (00 00 ff ff). + + If flush is set to Z_PARTIAL_FLUSH, all pending output is flushed to the + output buffer, but the output is not aligned to a byte boundary. All of the + input data so far will be available to the decompressor, as for Z_SYNC_FLUSH. + This completes the current deflate block and follows it with an empty fixed + codes block that is 10 bits long. This assures that enough bytes are output + in order for the decompressor to finish the block before the empty fixed code + block. + + If flush is set to Z_BLOCK, a deflate block is completed and emitted, as + for Z_SYNC_FLUSH, but the output is not aligned on a byte boundary, and up to + seven bits of the current block are held to be written as the next byte after + the next deflate block is completed. In this case, the decompressor may not + be provided enough bits at this point in order to complete decompression of + the data provided so far to the compressor. It may need to wait for the next + block to be emitted. This is for advanced applications that need to control + the emission of deflate blocks. + + If flush is set to Z_FULL_FLUSH, all output is flushed as with + Z_SYNC_FLUSH, and the compression state is reset so that decompression can + restart from this point if previous compressed data has been damaged or if + random access is desired. Using Z_FULL_FLUSH too often can seriously degrade + compression. + + If deflate returns with avail_out == 0, this function must be called again + with the same value of the flush parameter and more output space (updated + avail_out), until the flush is complete (deflate returns with non-zero + avail_out). In the case of a Z_FULL_FLUSH or Z_SYNC_FLUSH, make sure that + avail_out is greater than six to avoid repeated flush markers due to + avail_out == 0 on return. + + If the parameter flush is set to Z_FINISH, pending input is processed, + pending output is flushed and deflate returns with Z_STREAM_END if there was + enough output space; if deflate returns with Z_OK, this function must be + called again with Z_FINISH and more output space (updated avail_out) but no + more input data, until it returns with Z_STREAM_END or an error. After + deflate has returned Z_STREAM_END, the only possible operations on the stream + are deflateReset or deflateEnd. + + Z_FINISH can be used immediately after deflateInit if all the compression + is to be done in a single step. In this case, avail_out must be at least the + value returned by deflateBound (see below). Then deflate is guaranteed to + return Z_STREAM_END. If not enough output space is provided, deflate will + not return Z_STREAM_END, and it must be called again as described above. + + deflate() sets strm->adler to the adler32 checksum of all input read + so far (that is, total_in bytes). + + deflate() may update strm->data_type if it can make a good guess about + the input data type (Z_BINARY or Z_TEXT). In doubt, the data is considered + binary. This field is only for information purposes and does not affect the + compression algorithm in any manner. + + deflate() returns Z_OK if some progress has been made (more input + processed or more output produced), Z_STREAM_END if all input has been + consumed and all output has been produced (only when flush is set to + Z_FINISH), Z_STREAM_ERROR if the stream state was inconsistent (for example + if next_in or next_out was Z_NULL), Z_BUF_ERROR if no progress is possible + (for example avail_in or avail_out was zero). Note that Z_BUF_ERROR is not + fatal, and deflate() can be called again with more input and more output + space to continue compressing. +*/ + + +ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm)); +/* + All dynamically allocated data structures for this stream are freed. + This function discards any unprocessed input and does not flush any pending + output. + + deflateEnd returns Z_OK if success, Z_STREAM_ERROR if the + stream state was inconsistent, Z_DATA_ERROR if the stream was freed + prematurely (some input or output was discarded). In the error case, msg + may be set but then points to a static string (which must not be + deallocated). +*/ + + +/* +ZEXTERN int ZEXPORT inflateInit OF((z_streamp strm)); + + Initializes the internal stream state for decompression. The fields + next_in, avail_in, zalloc, zfree and opaque must be initialized before by + the caller. If next_in is not Z_NULL and avail_in is large enough (the + exact value depends on the compression method), inflateInit determines the + compression method from the zlib header and allocates all data structures + accordingly; otherwise the allocation will be deferred to the first call of + inflate. If zalloc and zfree are set to Z_NULL, inflateInit updates them to + use default allocation functions. + + inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not enough + memory, Z_VERSION_ERROR if the zlib library version is incompatible with the + version assumed by the caller, or Z_STREAM_ERROR if the parameters are + invalid, such as a null pointer to the structure. msg is set to null if + there is no error message. inflateInit does not perform any decompression + apart from possibly reading the zlib header if present: actual decompression + will be done by inflate(). (So next_in and avail_in may be modified, but + next_out and avail_out are unused and unchanged.) The current implementation + of inflateInit() does not process any header information -- that is deferred + until inflate() is called. +*/ + + +ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush)); +/* + inflate decompresses as much data as possible, and stops when the input + buffer becomes empty or the output buffer becomes full. It may introduce + some output latency (reading input without producing any output) except when + forced to flush. + + The detailed semantics are as follows. inflate performs one or both of the + following actions: + + - Decompress more input starting at next_in and update next_in and avail_in + accordingly. If not all input can be processed (because there is not + enough room in the output buffer), next_in is updated and processing will + resume at this point for the next call of inflate(). + + - Provide more output starting at next_out and update next_out and avail_out + accordingly. inflate() provides as much output as possible, until there is + no more input data or no more space in the output buffer (see below about + the flush parameter). + + Before the call of inflate(), the application should ensure that at least + one of the actions is possible, by providing more input and/or consuming more + output, and updating the next_* and avail_* values accordingly. The + application can consume the uncompressed output when it wants, for example + when the output buffer is full (avail_out == 0), or after each call of + inflate(). If inflate returns Z_OK and with zero avail_out, it must be + called again after making room in the output buffer because there might be + more output pending. + + The flush parameter of inflate() can be Z_NO_FLUSH, Z_SYNC_FLUSH, Z_FINISH, + Z_BLOCK, or Z_TREES. Z_SYNC_FLUSH requests that inflate() flush as much + output as possible to the output buffer. Z_BLOCK requests that inflate() + stop if and when it gets to the next deflate block boundary. When decoding + the zlib or gzip format, this will cause inflate() to return immediately + after the header and before the first block. When doing a raw inflate, + inflate() will go ahead and process the first block, and will return when it + gets to the end of that block, or when it runs out of data. + + The Z_BLOCK option assists in appending to or combining deflate streams. + Also to assist in this, on return inflate() will set strm->data_type to the + number of unused bits in the last byte taken from strm->next_in, plus 64 if + inflate() is currently decoding the last block in the deflate stream, plus + 128 if inflate() returned immediately after decoding an end-of-block code or + decoding the complete header up to just before the first byte of the deflate + stream. The end-of-block will not be indicated until all of the uncompressed + data from that block has been written to strm->next_out. The number of + unused bits may in general be greater than seven, except when bit 7 of + data_type is set, in which case the number of unused bits will be less than + eight. data_type is set as noted here every time inflate() returns for all + flush options, and so can be used to determine the amount of currently + consumed input in bits. + + The Z_TREES option behaves as Z_BLOCK does, but it also returns when the + end of each deflate block header is reached, before any actual data in that + block is decoded. This allows the caller to determine the length of the + deflate block header for later use in random access within a deflate block. + 256 is added to the value of strm->data_type when inflate() returns + immediately after reaching the end of the deflate block header. + + inflate() should normally be called until it returns Z_STREAM_END or an + error. However if all decompression is to be performed in a single step (a + single call of inflate), the parameter flush should be set to Z_FINISH. In + this case all pending input is processed and all pending output is flushed; + avail_out must be large enough to hold all of the uncompressed data for the + operation to complete. (The size of the uncompressed data may have been + saved by the compressor for this purpose.) The use of Z_FINISH is not + required to perform an inflation in one step. However it may be used to + inform inflate that a faster approach can be used for the single inflate() + call. Z_FINISH also informs inflate to not maintain a sliding window if the + stream completes, which reduces inflate's memory footprint. If the stream + does not complete, either because not all of the stream is provided or not + enough output space is provided, then a sliding window will be allocated and + inflate() can be called again to continue the operation as if Z_NO_FLUSH had + been used. + + In this implementation, inflate() always flushes as much output as + possible to the output buffer, and always uses the faster approach on the + first call. So the effects of the flush parameter in this implementation are + on the return value of inflate() as noted below, when inflate() returns early + when Z_BLOCK or Z_TREES is used, and when inflate() avoids the allocation of + memory for a sliding window when Z_FINISH is used. + + If a preset dictionary is needed after this call (see inflateSetDictionary + below), inflate sets strm->adler to the Adler-32 checksum of the dictionary + chosen by the compressor and returns Z_NEED_DICT; otherwise it sets + strm->adler to the Adler-32 checksum of all output produced so far (that is, + total_out bytes) and returns Z_OK, Z_STREAM_END or an error code as described + below. At the end of the stream, inflate() checks that its computed adler32 + checksum is equal to that saved by the compressor and returns Z_STREAM_END + only if the checksum is correct. + + inflate() can decompress and check either zlib-wrapped or gzip-wrapped + deflate data. The header type is detected automatically, if requested when + initializing with inflateInit2(). Any information contained in the gzip + header is not retained, so applications that need that information should + instead use raw inflate, see inflateInit2() below, or inflateBack() and + perform their own processing of the gzip header and trailer. When processing + gzip-wrapped deflate data, strm->adler32 is set to the CRC-32 of the output + producted so far. The CRC-32 is checked against the gzip trailer. + + inflate() returns Z_OK if some progress has been made (more input processed + or more output produced), Z_STREAM_END if the end of the compressed data has + been reached and all uncompressed output has been produced, Z_NEED_DICT if a + preset dictionary is needed at this point, Z_DATA_ERROR if the input data was + corrupted (input stream not conforming to the zlib format or incorrect check + value), Z_STREAM_ERROR if the stream structure was inconsistent (for example + next_in or next_out was Z_NULL), Z_MEM_ERROR if there was not enough memory, + Z_BUF_ERROR if no progress is possible or if there was not enough room in the + output buffer when Z_FINISH is used. Note that Z_BUF_ERROR is not fatal, and + inflate() can be called again with more input and more output space to + continue decompressing. If Z_DATA_ERROR is returned, the application may + then call inflateSync() to look for a good compression block if a partial + recovery of the data is desired. +*/ + + +ZEXTERN int ZEXPORT inflateEnd OF((z_streamp strm)); +/* + All dynamically allocated data structures for this stream are freed. + This function discards any unprocessed input and does not flush any pending + output. + + inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state + was inconsistent. In the error case, msg may be set but then points to a + static string (which must not be deallocated). +*/ + + + /* Advanced functions */ + +/* + The following functions are needed only in some special applications. +*/ + +/* +ZEXTERN int ZEXPORT deflateInit2 OF((z_streamp strm, + int level, + int method, + int windowBits, + int memLevel, + int strategy)); + + This is another version of deflateInit with more compression options. The + fields next_in, zalloc, zfree and opaque must be initialized before by the + caller. + + The method parameter is the compression method. It must be Z_DEFLATED in + this version of the library. + + The windowBits parameter is the base two logarithm of the window size + (the size of the history buffer). It should be in the range 8..15 for this + version of the library. Larger values of this parameter result in better + compression at the expense of memory usage. The default value is 15 if + deflateInit is used instead. + + windowBits can also be -8..-15 for raw deflate. In this case, -windowBits + determines the window size. deflate() will then generate raw deflate data + with no zlib header or trailer, and will not compute an adler32 check value. + + windowBits can also be greater than 15 for optional gzip encoding. Add + 16 to windowBits to write a simple gzip header and trailer around the + compressed data instead of a zlib wrapper. The gzip header will have no + file name, no extra data, no comment, no modification time (set to zero), no + header crc, and the operating system will be set to 255 (unknown). If a + gzip stream is being written, strm->adler is a crc32 instead of an adler32. + + The memLevel parameter specifies how much memory should be allocated + for the internal compression state. memLevel=1 uses minimum memory but is + slow and reduces compression ratio; memLevel=9 uses maximum memory for + optimal speed. The default value is 8. See zconf.h for total memory usage + as a function of windowBits and memLevel. + + The strategy parameter is used to tune the compression algorithm. Use the + value Z_DEFAULT_STRATEGY for normal data, Z_FILTERED for data produced by a + filter (or predictor), Z_HUFFMAN_ONLY to force Huffman encoding only (no + string match), or Z_RLE to limit match distances to one (run-length + encoding). Filtered data consists mostly of small values with a somewhat + random distribution. In this case, the compression algorithm is tuned to + compress them better. The effect of Z_FILTERED is to force more Huffman + coding and less string matching; it is somewhat intermediate between + Z_DEFAULT_STRATEGY and Z_HUFFMAN_ONLY. Z_RLE is designed to be almost as + fast as Z_HUFFMAN_ONLY, but give better compression for PNG image data. The + strategy parameter only affects the compression ratio but not the + correctness of the compressed output even if it is not set appropriately. + Z_FIXED prevents the use of dynamic Huffman codes, allowing for a simpler + decoder for special applications. + + deflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough + memory, Z_STREAM_ERROR if any parameter is invalid (such as an invalid + method), or Z_VERSION_ERROR if the zlib library version (zlib_version) is + incompatible with the version assumed by the caller (ZLIB_VERSION). msg is + set to null if there is no error message. deflateInit2 does not perform any + compression: this will be done by deflate(). +*/ + +ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm, + const Bytef *dictionary, + uInt dictLength)); +/* + Initializes the compression dictionary from the given byte sequence + without producing any compressed output. When using the zlib format, this + function must be called immediately after deflateInit, deflateInit2 or + deflateReset, and before any call of deflate. When doing raw deflate, this + function must be called either before any call of deflate, or immediately + after the completion of a deflate block, i.e. after all input has been + consumed and all output has been delivered when using any of the flush + options Z_BLOCK, Z_PARTIAL_FLUSH, Z_SYNC_FLUSH, or Z_FULL_FLUSH. The + compressor and decompressor must use exactly the same dictionary (see + inflateSetDictionary). + + The dictionary should consist of strings (byte sequences) that are likely + to be encountered later in the data to be compressed, with the most commonly + used strings preferably put towards the end of the dictionary. Using a + dictionary is most useful when the data to be compressed is short and can be + predicted with good accuracy; the data can then be compressed better than + with the default empty dictionary. + + Depending on the size of the compression data structures selected by + deflateInit or deflateInit2, a part of the dictionary may in effect be + discarded, for example if the dictionary is larger than the window size + provided in deflateInit or deflateInit2. Thus the strings most likely to be + useful should be put at the end of the dictionary, not at the front. In + addition, the current implementation of deflate will use at most the window + size minus 262 bytes of the provided dictionary. + + Upon return of this function, strm->adler is set to the adler32 value + of the dictionary; the decompressor may later use this value to determine + which dictionary has been used by the compressor. (The adler32 value + applies to the whole dictionary even if only a subset of the dictionary is + actually used by the compressor.) If a raw deflate was requested, then the + adler32 value is not computed and strm->adler is not set. + + deflateSetDictionary returns Z_OK if success, or Z_STREAM_ERROR if a + parameter is invalid (e.g. dictionary being Z_NULL) or the stream state is + inconsistent (for example if deflate has already been called for this stream + or if not at a block boundary for raw deflate). deflateSetDictionary does + not perform any compression: this will be done by deflate(). +*/ + +ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest, + z_streamp source)); +/* + Sets the destination stream as a complete copy of the source stream. + + This function can be useful when several compression strategies will be + tried, for example when there are several ways of pre-processing the input + data with a filter. The streams that will be discarded should then be freed + by calling deflateEnd. Note that deflateCopy duplicates the internal + compression state which can be quite large, so this strategy is slow and can + consume lots of memory. + + deflateCopy returns Z_OK if success, Z_MEM_ERROR if there was not + enough memory, Z_STREAM_ERROR if the source stream state was inconsistent + (such as zalloc being Z_NULL). msg is left unchanged in both source and + destination. +*/ + +ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm)); +/* + This function is equivalent to deflateEnd followed by deflateInit, + but does not free and reallocate all the internal compression state. The + stream will keep the same compression level and any other attributes that + may have been set by deflateInit2. + + deflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent (such as zalloc or state being Z_NULL). +*/ + +ZEXTERN int ZEXPORT deflateParams OF((z_streamp strm, + int level, + int strategy)); +/* + Dynamically update the compression level and compression strategy. The + interpretation of level and strategy is as in deflateInit2. This can be + used to switch between compression and straight copy of the input data, or + to switch to a different kind of input data requiring a different strategy. + If the compression level is changed, the input available so far is + compressed with the old level (and may be flushed); the new level will take + effect only at the next call of deflate(). + + Before the call of deflateParams, the stream state must be set as for + a call of deflate(), since the currently available input may have to be + compressed and flushed. In particular, strm->avail_out must be non-zero. + + deflateParams returns Z_OK if success, Z_STREAM_ERROR if the source + stream state was inconsistent or if a parameter was invalid, Z_BUF_ERROR if + strm->avail_out was zero. +*/ + +ZEXTERN int ZEXPORT deflateTune OF((z_streamp strm, + int good_length, + int max_lazy, + int nice_length, + int max_chain)); +/* + Fine tune deflate's internal compression parameters. This should only be + used by someone who understands the algorithm used by zlib's deflate for + searching for the best matching string, and even then only by the most + fanatic optimizer trying to squeeze out the last compressed bit for their + specific input data. Read the deflate.c source code for the meaning of the + max_lazy, good_length, nice_length, and max_chain parameters. + + deflateTune() can be called after deflateInit() or deflateInit2(), and + returns Z_OK on success, or Z_STREAM_ERROR for an invalid deflate stream. + */ + +ZEXTERN uLong ZEXPORT deflateBound OF((z_streamp strm, + uLong sourceLen)); +/* + deflateBound() returns an upper bound on the compressed size after + deflation of sourceLen bytes. It must be called after deflateInit() or + deflateInit2(), and after deflateSetHeader(), if used. This would be used + to allocate an output buffer for deflation in a single pass, and so would be + called before deflate(). If that first deflate() call is provided the + sourceLen input bytes, an output buffer allocated to the size returned by + deflateBound(), and the flush value Z_FINISH, then deflate() is guaranteed + to return Z_STREAM_END. Note that it is possible for the compressed size to + be larger than the value returned by deflateBound() if flush options other + than Z_FINISH or Z_NO_FLUSH are used. +*/ + +ZEXTERN int ZEXPORT deflatePending OF((z_streamp strm, + unsigned *pending, + int *bits)); +/* + deflatePending() returns the number of bytes and bits of output that have + been generated, but not yet provided in the available output. The bytes not + provided would be due to the available output space having being consumed. + The number of bits of output not provided are between 0 and 7, where they + await more bits to join them in order to fill out a full byte. If pending + or bits are Z_NULL, then those values are not set. + + deflatePending returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent. + */ + +ZEXTERN int ZEXPORT deflatePrime OF((z_streamp strm, + int bits, + int value)); +/* + deflatePrime() inserts bits in the deflate output stream. The intent + is that this function is used to start off the deflate output with the bits + leftover from a previous deflate stream when appending to it. As such, this + function can only be used for raw deflate, and must be used before the first + deflate() call after a deflateInit2() or deflateReset(). bits must be less + than or equal to 16, and that many of the least significant bits of value + will be inserted in the output. + + deflatePrime returns Z_OK if success, Z_BUF_ERROR if there was not enough + room in the internal buffer to insert the bits, or Z_STREAM_ERROR if the + source stream state was inconsistent. +*/ + +ZEXTERN int ZEXPORT deflateSetHeader OF((z_streamp strm, + gz_headerp head)); +/* + deflateSetHeader() provides gzip header information for when a gzip + stream is requested by deflateInit2(). deflateSetHeader() may be called + after deflateInit2() or deflateReset() and before the first call of + deflate(). The text, time, os, extra field, name, and comment information + in the provided gz_header structure are written to the gzip header (xflag is + ignored -- the extra flags are set according to the compression level). The + caller must assure that, if not Z_NULL, name and comment are terminated with + a zero byte, and that if extra is not Z_NULL, that extra_len bytes are + available there. If hcrc is true, a gzip header crc is included. Note that + the current versions of the command-line version of gzip (up through version + 1.3.x) do not support header crc's, and will report that it is a "multi-part + gzip file" and give up. + + If deflateSetHeader is not used, the default gzip header has text false, + the time set to zero, and os set to 255, with no extra, name, or comment + fields. The gzip header is returned to the default state by deflateReset(). + + deflateSetHeader returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent. +*/ + +/* +ZEXTERN int ZEXPORT inflateInit2 OF((z_streamp strm, + int windowBits)); + + This is another version of inflateInit with an extra parameter. The + fields next_in, avail_in, zalloc, zfree and opaque must be initialized + before by the caller. + + The windowBits parameter is the base two logarithm of the maximum window + size (the size of the history buffer). It should be in the range 8..15 for + this version of the library. The default value is 15 if inflateInit is used + instead. windowBits must be greater than or equal to the windowBits value + provided to deflateInit2() while compressing, or it must be equal to 15 if + deflateInit2() was not used. If a compressed stream with a larger window + size is given as input, inflate() will return with the error code + Z_DATA_ERROR instead of trying to allocate a larger window. + + windowBits can also be zero to request that inflate use the window size in + the zlib header of the compressed stream. + + windowBits can also be -8..-15 for raw inflate. In this case, -windowBits + determines the window size. inflate() will then process raw deflate data, + not looking for a zlib or gzip header, not generating a check value, and not + looking for any check values for comparison at the end of the stream. This + is for use with other formats that use the deflate compressed data format + such as zip. Those formats provide their own check values. If a custom + format is developed using the raw deflate format for compressed data, it is + recommended that a check value such as an adler32 or a crc32 be applied to + the uncompressed data as is done in the zlib, gzip, and zip formats. For + most applications, the zlib format should be used as is. Note that comments + above on the use in deflateInit2() applies to the magnitude of windowBits. + + windowBits can also be greater than 15 for optional gzip decoding. Add + 32 to windowBits to enable zlib and gzip decoding with automatic header + detection, or add 16 to decode only the gzip format (the zlib format will + return a Z_DATA_ERROR). If a gzip stream is being decoded, strm->adler is a + crc32 instead of an adler32. + + inflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough + memory, Z_VERSION_ERROR if the zlib library version is incompatible with the + version assumed by the caller, or Z_STREAM_ERROR if the parameters are + invalid, such as a null pointer to the structure. msg is set to null if + there is no error message. inflateInit2 does not perform any decompression + apart from possibly reading the zlib header if present: actual decompression + will be done by inflate(). (So next_in and avail_in may be modified, but + next_out and avail_out are unused and unchanged.) The current implementation + of inflateInit2() does not process any header information -- that is + deferred until inflate() is called. +*/ + +ZEXTERN int ZEXPORT inflateSetDictionary OF((z_streamp strm, + const Bytef *dictionary, + uInt dictLength)); +/* + Initializes the decompression dictionary from the given uncompressed byte + sequence. This function must be called immediately after a call of inflate, + if that call returned Z_NEED_DICT. The dictionary chosen by the compressor + can be determined from the adler32 value returned by that call of inflate. + The compressor and decompressor must use exactly the same dictionary (see + deflateSetDictionary). For raw inflate, this function can be called at any + time to set the dictionary. If the provided dictionary is smaller than the + window and there is already data in the window, then the provided dictionary + will amend what's there. The application must insure that the dictionary + that was used for compression is provided. + + inflateSetDictionary returns Z_OK if success, Z_STREAM_ERROR if a + parameter is invalid (e.g. dictionary being Z_NULL) or the stream state is + inconsistent, Z_DATA_ERROR if the given dictionary doesn't match the + expected one (incorrect adler32 value). inflateSetDictionary does not + perform any decompression: this will be done by subsequent calls of + inflate(). +*/ + +ZEXTERN int ZEXPORT inflateGetDictionary OF((z_streamp strm, + Bytef *dictionary, + uInt *dictLength)); +/* + Returns the sliding dictionary being maintained by inflate. dictLength is + set to the number of bytes in the dictionary, and that many bytes are copied + to dictionary. dictionary must have enough space, where 32768 bytes is + always enough. If inflateGetDictionary() is called with dictionary equal to + Z_NULL, then only the dictionary length is returned, and nothing is copied. + Similary, if dictLength is Z_NULL, then it is not set. + + inflateGetDictionary returns Z_OK on success, or Z_STREAM_ERROR if the + stream state is inconsistent. +*/ + +ZEXTERN int ZEXPORT inflateSync OF((z_streamp strm)); +/* + Skips invalid compressed data until a possible full flush point (see above + for the description of deflate with Z_FULL_FLUSH) can be found, or until all + available input is skipped. No output is provided. + + inflateSync searches for a 00 00 FF FF pattern in the compressed data. + All full flush points have this pattern, but not all occurrences of this + pattern are full flush points. + + inflateSync returns Z_OK if a possible full flush point has been found, + Z_BUF_ERROR if no more input was provided, Z_DATA_ERROR if no flush point + has been found, or Z_STREAM_ERROR if the stream structure was inconsistent. + In the success case, the application may save the current current value of + total_in which indicates where valid compressed data was found. In the + error case, the application may repeatedly call inflateSync, providing more + input each time, until success or end of the input data. +*/ + +ZEXTERN int ZEXPORT inflateCopy OF((z_streamp dest, + z_streamp source)); +/* + Sets the destination stream as a complete copy of the source stream. + + This function can be useful when randomly accessing a large stream. The + first pass through the stream can periodically record the inflate state, + allowing restarting inflate at those points when randomly accessing the + stream. + + inflateCopy returns Z_OK if success, Z_MEM_ERROR if there was not + enough memory, Z_STREAM_ERROR if the source stream state was inconsistent + (such as zalloc being Z_NULL). msg is left unchanged in both source and + destination. +*/ + +ZEXTERN int ZEXPORT inflateReset OF((z_streamp strm)); +/* + This function is equivalent to inflateEnd followed by inflateInit, + but does not free and reallocate all the internal decompression state. The + stream will keep attributes that may have been set by inflateInit2. + + inflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent (such as zalloc or state being Z_NULL). +*/ + +ZEXTERN int ZEXPORT inflateReset2 OF((z_streamp strm, + int windowBits)); +/* + This function is the same as inflateReset, but it also permits changing + the wrap and window size requests. The windowBits parameter is interpreted + the same as it is for inflateInit2. + + inflateReset2 returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent (such as zalloc or state being Z_NULL), or if + the windowBits parameter is invalid. +*/ + +ZEXTERN int ZEXPORT inflatePrime OF((z_streamp strm, + int bits, + int value)); +/* + This function inserts bits in the inflate input stream. The intent is + that this function is used to start inflating at a bit position in the + middle of a byte. The provided bits will be used before any bytes are used + from next_in. This function should only be used with raw inflate, and + should be used before the first inflate() call after inflateInit2() or + inflateReset(). bits must be less than or equal to 16, and that many of the + least significant bits of value will be inserted in the input. + + If bits is negative, then the input stream bit buffer is emptied. Then + inflatePrime() can be called again to put bits in the buffer. This is used + to clear out bits leftover after feeding inflate a block description prior + to feeding inflate codes. + + inflatePrime returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent. +*/ + +ZEXTERN long ZEXPORT inflateMark OF((z_streamp strm)); +/* + This function returns two values, one in the lower 16 bits of the return + value, and the other in the remaining upper bits, obtained by shifting the + return value down 16 bits. If the upper value is -1 and the lower value is + zero, then inflate() is currently decoding information outside of a block. + If the upper value is -1 and the lower value is non-zero, then inflate is in + the middle of a stored block, with the lower value equaling the number of + bytes from the input remaining to copy. If the upper value is not -1, then + it is the number of bits back from the current bit position in the input of + the code (literal or length/distance pair) currently being processed. In + that case the lower value is the number of bytes already emitted for that + code. + + A code is being processed if inflate is waiting for more input to complete + decoding of the code, or if it has completed decoding but is waiting for + more output space to write the literal or match data. + + inflateMark() is used to mark locations in the input data for random + access, which may be at bit positions, and to note those cases where the + output of a code may span boundaries of random access blocks. The current + location in the input stream can be determined from avail_in and data_type + as noted in the description for the Z_BLOCK flush parameter for inflate. + + inflateMark returns the value noted above or -1 << 16 if the provided + source stream state was inconsistent. +*/ + +ZEXTERN int ZEXPORT inflateGetHeader OF((z_streamp strm, + gz_headerp head)); +/* + inflateGetHeader() requests that gzip header information be stored in the + provided gz_header structure. inflateGetHeader() may be called after + inflateInit2() or inflateReset(), and before the first call of inflate(). + As inflate() processes the gzip stream, head->done is zero until the header + is completed, at which time head->done is set to one. If a zlib stream is + being decoded, then head->done is set to -1 to indicate that there will be + no gzip header information forthcoming. Note that Z_BLOCK or Z_TREES can be + used to force inflate() to return immediately after header processing is + complete and before any actual data is decompressed. + + The text, time, xflags, and os fields are filled in with the gzip header + contents. hcrc is set to true if there is a header CRC. (The header CRC + was valid if done is set to one.) If extra is not Z_NULL, then extra_max + contains the maximum number of bytes to write to extra. Once done is true, + extra_len contains the actual extra field length, and extra contains the + extra field, or that field truncated if extra_max is less than extra_len. + If name is not Z_NULL, then up to name_max characters are written there, + terminated with a zero unless the length is greater than name_max. If + comment is not Z_NULL, then up to comm_max characters are written there, + terminated with a zero unless the length is greater than comm_max. When any + of extra, name, or comment are not Z_NULL and the respective field is not + present in the header, then that field is set to Z_NULL to signal its + absence. This allows the use of deflateSetHeader() with the returned + structure to duplicate the header. However if those fields are set to + allocated memory, then the application will need to save those pointers + elsewhere so that they can be eventually freed. + + If inflateGetHeader is not used, then the header information is simply + discarded. The header is always checked for validity, including the header + CRC if present. inflateReset() will reset the process to discard the header + information. The application would need to call inflateGetHeader() again to + retrieve the header from the next gzip stream. + + inflateGetHeader returns Z_OK if success, or Z_STREAM_ERROR if the source + stream state was inconsistent. +*/ + +/* +ZEXTERN int ZEXPORT inflateBackInit OF((z_streamp strm, int windowBits, + unsigned char FAR *window)); + + Initialize the internal stream state for decompression using inflateBack() + calls. The fields zalloc, zfree and opaque in strm must be initialized + before the call. If zalloc and zfree are Z_NULL, then the default library- + derived memory allocation routines are used. windowBits is the base two + logarithm of the window size, in the range 8..15. window is a caller + supplied buffer of that size. Except for special applications where it is + assured that deflate was used with small window sizes, windowBits must be 15 + and a 32K byte window must be supplied to be able to decompress general + deflate streams. + + See inflateBack() for the usage of these routines. + + inflateBackInit will return Z_OK on success, Z_STREAM_ERROR if any of + the parameters are invalid, Z_MEM_ERROR if the internal state could not be + allocated, or Z_VERSION_ERROR if the version of the library does not match + the version of the header file. +*/ + +typedef unsigned (*in_func) OF((void FAR *, + z_const unsigned char FAR * FAR *)); +typedef int (*out_func) OF((void FAR *, unsigned char FAR *, unsigned)); + +ZEXTERN int ZEXPORT inflateBack OF((z_streamp strm, + in_func in, void FAR *in_desc, + out_func out, void FAR *out_desc)); +/* + inflateBack() does a raw inflate with a single call using a call-back + interface for input and output. This is potentially more efficient than + inflate() for file i/o applications, in that it avoids copying between the + output and the sliding window by simply making the window itself the output + buffer. inflate() can be faster on modern CPUs when used with large + buffers. inflateBack() trusts the application to not change the output + buffer passed by the output function, at least until inflateBack() returns. + + inflateBackInit() must be called first to allocate the internal state + and to initialize the state with the user-provided window buffer. + inflateBack() may then be used multiple times to inflate a complete, raw + deflate stream with each call. inflateBackEnd() is then called to free the + allocated state. + + A raw deflate stream is one with no zlib or gzip header or trailer. + This routine would normally be used in a utility that reads zip or gzip + files and writes out uncompressed files. The utility would decode the + header and process the trailer on its own, hence this routine expects only + the raw deflate stream to decompress. This is different from the normal + behavior of inflate(), which expects either a zlib or gzip header and + trailer around the deflate stream. + + inflateBack() uses two subroutines supplied by the caller that are then + called by inflateBack() for input and output. inflateBack() calls those + routines until it reads a complete deflate stream and writes out all of the + uncompressed data, or until it encounters an error. The function's + parameters and return types are defined above in the in_func and out_func + typedefs. inflateBack() will call in(in_desc, &buf) which should return the + number of bytes of provided input, and a pointer to that input in buf. If + there is no input available, in() must return zero--buf is ignored in that + case--and inflateBack() will return a buffer error. inflateBack() will call + out(out_desc, buf, len) to write the uncompressed data buf[0..len-1]. out() + should return zero on success, or non-zero on failure. If out() returns + non-zero, inflateBack() will return with an error. Neither in() nor out() + are permitted to change the contents of the window provided to + inflateBackInit(), which is also the buffer that out() uses to write from. + The length written by out() will be at most the window size. Any non-zero + amount of input may be provided by in(). + + For convenience, inflateBack() can be provided input on the first call by + setting strm->next_in and strm->avail_in. If that input is exhausted, then + in() will be called. Therefore strm->next_in must be initialized before + calling inflateBack(). If strm->next_in is Z_NULL, then in() will be called + immediately for input. If strm->next_in is not Z_NULL, then strm->avail_in + must also be initialized, and then if strm->avail_in is not zero, input will + initially be taken from strm->next_in[0 .. strm->avail_in - 1]. + + The in_desc and out_desc parameters of inflateBack() is passed as the + first parameter of in() and out() respectively when they are called. These + descriptors can be optionally used to pass any information that the caller- + supplied in() and out() functions need to do their job. + + On return, inflateBack() will set strm->next_in and strm->avail_in to + pass back any unused input that was provided by the last in() call. The + return values of inflateBack() can be Z_STREAM_END on success, Z_BUF_ERROR + if in() or out() returned an error, Z_DATA_ERROR if there was a format error + in the deflate stream (in which case strm->msg is set to indicate the nature + of the error), or Z_STREAM_ERROR if the stream was not properly initialized. + In the case of Z_BUF_ERROR, an input or output error can be distinguished + using strm->next_in which will be Z_NULL only if in() returned an error. If + strm->next_in is not Z_NULL, then the Z_BUF_ERROR was due to out() returning + non-zero. (in() will always be called before out(), so strm->next_in is + assured to be defined if out() returns non-zero.) Note that inflateBack() + cannot return Z_OK. +*/ + +ZEXTERN int ZEXPORT inflateBackEnd OF((z_streamp strm)); +/* + All memory allocated by inflateBackInit() is freed. + + inflateBackEnd() returns Z_OK on success, or Z_STREAM_ERROR if the stream + state was inconsistent. +*/ + +ZEXTERN uLong ZEXPORT zlibCompileFlags OF((void)); +/* Return flags indicating compile-time options. + + Type sizes, two bits each, 00 = 16 bits, 01 = 32, 10 = 64, 11 = other: + 1.0: size of uInt + 3.2: size of uLong + 5.4: size of voidpf (pointer) + 7.6: size of z_off_t + + Compiler, assembler, and debug options: + 8: DEBUG + 9: ASMV or ASMINF -- use ASM code + 10: ZLIB_WINAPI -- exported functions use the WINAPI calling convention + 11: 0 (reserved) + + One-time table building (smaller code, but not thread-safe if true): + 12: BUILDFIXED -- build static block decoding tables when needed + 13: DYNAMIC_CRC_TABLE -- build CRC calculation tables when needed + 14,15: 0 (reserved) + + Library content (indicates missing functionality): + 16: NO_GZCOMPRESS -- gz* functions cannot compress (to avoid linking + deflate code when not needed) + 17: NO_GZIP -- deflate can't write gzip streams, and inflate can't detect + and decode gzip streams (to avoid linking crc code) + 18-19: 0 (reserved) + + Operation variations (changes in library functionality): + 20: PKZIP_BUG_WORKAROUND -- slightly more permissive inflate + 21: FASTEST -- deflate algorithm with only one, lowest compression level + 22,23: 0 (reserved) + + The sprintf variant used by gzprintf (zero is best): + 24: 0 = vs*, 1 = s* -- 1 means limited to 20 arguments after the format + 25: 0 = *nprintf, 1 = *printf -- 1 means gzprintf() not secure! + 26: 0 = returns value, 1 = void -- 1 means inferred string length returned + + Remainder: + 27-31: 0 (reserved) + */ + +#ifndef Z_SOLO + + /* utility functions */ + +/* + The following utility functions are implemented on top of the basic + stream-oriented functions. To simplify the interface, some default options + are assumed (compression level and memory usage, standard memory allocation + functions). The source code of these utility functions can be modified if + you need special options. +*/ + +ZEXTERN int ZEXPORT compress OF((Bytef *dest, uLongf *destLen, + const Bytef *source, uLong sourceLen)); +/* + Compresses the source buffer into the destination buffer. sourceLen is + the byte length of the source buffer. Upon entry, destLen is the total size + of the destination buffer, which must be at least the value returned by + compressBound(sourceLen). Upon exit, destLen is the actual size of the + compressed buffer. + + compress returns Z_OK if success, Z_MEM_ERROR if there was not + enough memory, Z_BUF_ERROR if there was not enough room in the output + buffer. +*/ + +ZEXTERN int ZEXPORT compress2 OF((Bytef *dest, uLongf *destLen, + const Bytef *source, uLong sourceLen, + int level)); +/* + Compresses the source buffer into the destination buffer. The level + parameter has the same meaning as in deflateInit. sourceLen is the byte + length of the source buffer. Upon entry, destLen is the total size of the + destination buffer, which must be at least the value returned by + compressBound(sourceLen). Upon exit, destLen is the actual size of the + compressed buffer. + + compress2 returns Z_OK if success, Z_MEM_ERROR if there was not enough + memory, Z_BUF_ERROR if there was not enough room in the output buffer, + Z_STREAM_ERROR if the level parameter is invalid. +*/ + +ZEXTERN uLong ZEXPORT compressBound OF((uLong sourceLen)); +/* + compressBound() returns an upper bound on the compressed size after + compress() or compress2() on sourceLen bytes. It would be used before a + compress() or compress2() call to allocate the destination buffer. +*/ + +ZEXTERN int ZEXPORT uncompress OF((Bytef *dest, uLongf *destLen, + const Bytef *source, uLong sourceLen)); +/* + Decompresses the source buffer into the destination buffer. sourceLen is + the byte length of the source buffer. Upon entry, destLen is the total size + of the destination buffer, which must be large enough to hold the entire + uncompressed data. (The size of the uncompressed data must have been saved + previously by the compressor and transmitted to the decompressor by some + mechanism outside the scope of this compression library.) Upon exit, destLen + is the actual size of the uncompressed buffer. + + uncompress returns Z_OK if success, Z_MEM_ERROR if there was not + enough memory, Z_BUF_ERROR if there was not enough room in the output + buffer, or Z_DATA_ERROR if the input data was corrupted or incomplete. In + the case where there is not enough room, uncompress() will fill the output + buffer with the uncompressed data up to that point. +*/ + + /* gzip file access functions */ + +/* + This library supports reading and writing files in gzip (.gz) format with + an interface similar to that of stdio, using the functions that start with + "gz". The gzip format is different from the zlib format. gzip is a gzip + wrapper, documented in RFC 1952, wrapped around a deflate stream. +*/ + +typedef struct gzFile_s *gzFile; /* semi-opaque gzip file descriptor */ + +/* +ZEXTERN gzFile ZEXPORT gzopen OF((const char *path, const char *mode)); + + Opens a gzip (.gz) file for reading or writing. The mode parameter is as + in fopen ("rb" or "wb") but can also include a compression level ("wb9") or + a strategy: 'f' for filtered data as in "wb6f", 'h' for Huffman-only + compression as in "wb1h", 'R' for run-length encoding as in "wb1R", or 'F' + for fixed code compression as in "wb9F". (See the description of + deflateInit2 for more information about the strategy parameter.) 'T' will + request transparent writing or appending with no compression and not using + the gzip format. + + "a" can be used instead of "w" to request that the gzip stream that will + be written be appended to the file. "+" will result in an error, since + reading and writing to the same gzip file is not supported. The addition of + "x" when writing will create the file exclusively, which fails if the file + already exists. On systems that support it, the addition of "e" when + reading or writing will set the flag to close the file on an execve() call. + + These functions, as well as gzip, will read and decode a sequence of gzip + streams in a file. The append function of gzopen() can be used to create + such a file. (Also see gzflush() for another way to do this.) When + appending, gzopen does not test whether the file begins with a gzip stream, + nor does it look for the end of the gzip streams to begin appending. gzopen + will simply append a gzip stream to the existing file. + + gzopen can be used to read a file which is not in gzip format; in this + case gzread will directly read from the file without decompression. When + reading, this will be detected automatically by looking for the magic two- + byte gzip header. + + gzopen returns NULL if the file could not be opened, if there was + insufficient memory to allocate the gzFile state, or if an invalid mode was + specified (an 'r', 'w', or 'a' was not provided, or '+' was provided). + errno can be checked to determine if the reason gzopen failed was that the + file could not be opened. +*/ + +ZEXTERN gzFile ZEXPORT gzdopen OF((int fd, const char *mode)); +/* + gzdopen associates a gzFile with the file descriptor fd. File descriptors + are obtained from calls like open, dup, creat, pipe or fileno (if the file + has been previously opened with fopen). The mode parameter is as in gzopen. + + The next call of gzclose on the returned gzFile will also close the file + descriptor fd, just like fclose(fdopen(fd, mode)) closes the file descriptor + fd. If you want to keep fd open, use fd = dup(fd_keep); gz = gzdopen(fd, + mode);. The duplicated descriptor should be saved to avoid a leak, since + gzdopen does not close fd if it fails. If you are using fileno() to get the + file descriptor from a FILE *, then you will have to use dup() to avoid + double-close()ing the file descriptor. Both gzclose() and fclose() will + close the associated file descriptor, so they need to have different file + descriptors. + + gzdopen returns NULL if there was insufficient memory to allocate the + gzFile state, if an invalid mode was specified (an 'r', 'w', or 'a' was not + provided, or '+' was provided), or if fd is -1. The file descriptor is not + used until the next gz* read, write, seek, or close operation, so gzdopen + will not detect if fd is invalid (unless fd is -1). +*/ + +ZEXTERN int ZEXPORT gzbuffer OF((gzFile file, unsigned size)); +/* + Set the internal buffer size used by this library's functions. The + default buffer size is 8192 bytes. This function must be called after + gzopen() or gzdopen(), and before any other calls that read or write the + file. The buffer memory allocation is always deferred to the first read or + write. Two buffers are allocated, either both of the specified size when + writing, or one of the specified size and the other twice that size when + reading. A larger buffer size of, for example, 64K or 128K bytes will + noticeably increase the speed of decompression (reading). + + The new buffer size also affects the maximum length for gzprintf(). + + gzbuffer() returns 0 on success, or -1 on failure, such as being called + too late. +*/ + +ZEXTERN int ZEXPORT gzsetparams OF((gzFile file, int level, int strategy)); +/* + Dynamically update the compression level or strategy. See the description + of deflateInit2 for the meaning of these parameters. + + gzsetparams returns Z_OK if success, or Z_STREAM_ERROR if the file was not + opened for writing. +*/ + +ZEXTERN int ZEXPORT gzread OF((gzFile file, voidp buf, unsigned len)); +/* + Reads the given number of uncompressed bytes from the compressed file. If + the input file is not in gzip format, gzread copies the given number of + bytes into the buffer directly from the file. + + After reaching the end of a gzip stream in the input, gzread will continue + to read, looking for another gzip stream. Any number of gzip streams may be + concatenated in the input file, and will all be decompressed by gzread(). + If something other than a gzip stream is encountered after a gzip stream, + that remaining trailing garbage is ignored (and no error is returned). + + gzread can be used to read a gzip file that is being concurrently written. + Upon reaching the end of the input, gzread will return with the available + data. If the error code returned by gzerror is Z_OK or Z_BUF_ERROR, then + gzclearerr can be used to clear the end of file indicator in order to permit + gzread to be tried again. Z_OK indicates that a gzip stream was completed + on the last gzread. Z_BUF_ERROR indicates that the input file ended in the + middle of a gzip stream. Note that gzread does not return -1 in the event + of an incomplete gzip stream. This error is deferred until gzclose(), which + will return Z_BUF_ERROR if the last gzread ended in the middle of a gzip + stream. Alternatively, gzerror can be used before gzclose to detect this + case. + + gzread returns the number of uncompressed bytes actually read, less than + len for end of file, or -1 for error. +*/ + +ZEXTERN int ZEXPORT gzwrite OF((gzFile file, + voidpc buf, unsigned len)); +/* + Writes the given number of uncompressed bytes into the compressed file. + gzwrite returns the number of uncompressed bytes written or 0 in case of + error. +*/ + +ZEXTERN int ZEXPORTVA gzprintf Z_ARG((gzFile file, const char *format, ...)); +/* + Converts, formats, and writes the arguments to the compressed file under + control of the format string, as in fprintf. gzprintf returns the number of + uncompressed bytes actually written, or 0 in case of error. The number of + uncompressed bytes written is limited to 8191, or one less than the buffer + size given to gzbuffer(). The caller should assure that this limit is not + exceeded. If it is exceeded, then gzprintf() will return an error (0) with + nothing written. In this case, there may also be a buffer overflow with + unpredictable consequences, which is possible only if zlib was compiled with + the insecure functions sprintf() or vsprintf() because the secure snprintf() + or vsnprintf() functions were not available. This can be determined using + zlibCompileFlags(). +*/ + +ZEXTERN int ZEXPORT gzputs OF((gzFile file, const char *s)); +/* + Writes the given null-terminated string to the compressed file, excluding + the terminating null character. + + gzputs returns the number of characters written, or -1 in case of error. +*/ + +ZEXTERN char * ZEXPORT gzgets OF((gzFile file, char *buf, int len)); +/* + Reads bytes from the compressed file until len-1 characters are read, or a + newline character is read and transferred to buf, or an end-of-file + condition is encountered. If any characters are read or if len == 1, the + string is terminated with a null character. If no characters are read due + to an end-of-file or len < 1, then the buffer is left untouched. + + gzgets returns buf which is a null-terminated string, or it returns NULL + for end-of-file or in case of error. If there was an error, the contents at + buf are indeterminate. +*/ + +ZEXTERN int ZEXPORT gzputc OF((gzFile file, int c)); +/* + Writes c, converted to an unsigned char, into the compressed file. gzputc + returns the value that was written, or -1 in case of error. +*/ + +ZEXTERN int ZEXPORT gzgetc OF((gzFile file)); +/* + Reads one byte from the compressed file. gzgetc returns this byte or -1 + in case of end of file or error. This is implemented as a macro for speed. + As such, it does not do all of the checking the other functions do. I.e. + it does not check to see if file is NULL, nor whether the structure file + points to has been clobbered or not. +*/ + +ZEXTERN int ZEXPORT gzungetc OF((int c, gzFile file)); +/* + Push one character back onto the stream to be read as the first character + on the next read. At least one character of push-back is allowed. + gzungetc() returns the character pushed, or -1 on failure. gzungetc() will + fail if c is -1, and may fail if a character has been pushed but not read + yet. If gzungetc is used immediately after gzopen or gzdopen, at least the + output buffer size of pushed characters is allowed. (See gzbuffer above.) + The pushed character will be discarded if the stream is repositioned with + gzseek() or gzrewind(). +*/ + +ZEXTERN int ZEXPORT gzflush OF((gzFile file, int flush)); +/* + Flushes all pending output into the compressed file. The parameter flush + is as in the deflate() function. The return value is the zlib error number + (see function gzerror below). gzflush is only permitted when writing. + + If the flush parameter is Z_FINISH, the remaining data is written and the + gzip stream is completed in the output. If gzwrite() is called again, a new + gzip stream will be started in the output. gzread() is able to read such + concatented gzip streams. + + gzflush should be called only when strictly necessary because it will + degrade compression if called too often. +*/ + +/* +ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile file, + z_off_t offset, int whence)); + + Sets the starting position for the next gzread or gzwrite on the given + compressed file. The offset represents a number of bytes in the + uncompressed data stream. The whence parameter is defined as in lseek(2); + the value SEEK_END is not supported. + + If the file is opened for reading, this function is emulated but can be + extremely slow. If the file is opened for writing, only forward seeks are + supported; gzseek then compresses a sequence of zeroes up to the new + starting position. + + gzseek returns the resulting offset location as measured in bytes from + the beginning of the uncompressed stream, or -1 in case of error, in + particular if the file is opened for writing and the new starting position + would be before the current position. +*/ + +ZEXTERN int ZEXPORT gzrewind OF((gzFile file)); +/* + Rewinds the given file. This function is supported only for reading. + + gzrewind(file) is equivalent to (int)gzseek(file, 0L, SEEK_SET) +*/ + +/* +ZEXTERN z_off_t ZEXPORT gztell OF((gzFile file)); + + Returns the starting position for the next gzread or gzwrite on the given + compressed file. This position represents a number of bytes in the + uncompressed data stream, and is zero when starting, even if appending or + reading a gzip stream from the middle of a file using gzdopen(). + + gztell(file) is equivalent to gzseek(file, 0L, SEEK_CUR) +*/ + +/* +ZEXTERN z_off_t ZEXPORT gzoffset OF((gzFile file)); + + Returns the current offset in the file being read or written. This offset + includes the count of bytes that precede the gzip stream, for example when + appending or when using gzdopen() for reading. When reading, the offset + does not include as yet unused buffered input. This information can be used + for a progress indicator. On error, gzoffset() returns -1. +*/ + +ZEXTERN int ZEXPORT gzeof OF((gzFile file)); +/* + Returns true (1) if the end-of-file indicator has been set while reading, + false (0) otherwise. Note that the end-of-file indicator is set only if the + read tried to go past the end of the input, but came up short. Therefore, + just like feof(), gzeof() may return false even if there is no more data to + read, in the event that the last read request was for the exact number of + bytes remaining in the input file. This will happen if the input file size + is an exact multiple of the buffer size. + + If gzeof() returns true, then the read functions will return no more data, + unless the end-of-file indicator is reset by gzclearerr() and the input file + has grown since the previous end of file was detected. +*/ + +ZEXTERN int ZEXPORT gzdirect OF((gzFile file)); +/* + Returns true (1) if file is being copied directly while reading, or false + (0) if file is a gzip stream being decompressed. + + If the input file is empty, gzdirect() will return true, since the input + does not contain a gzip stream. + + If gzdirect() is used immediately after gzopen() or gzdopen() it will + cause buffers to be allocated to allow reading the file to determine if it + is a gzip file. Therefore if gzbuffer() is used, it should be called before + gzdirect(). + + When writing, gzdirect() returns true (1) if transparent writing was + requested ("wT" for the gzopen() mode), or false (0) otherwise. (Note: + gzdirect() is not needed when writing. Transparent writing must be + explicitly requested, so the application already knows the answer. When + linking statically, using gzdirect() will include all of the zlib code for + gzip file reading and decompression, which may not be desired.) +*/ + +ZEXTERN int ZEXPORT gzclose OF((gzFile file)); +/* + Flushes all pending output if necessary, closes the compressed file and + deallocates the (de)compression state. Note that once file is closed, you + cannot call gzerror with file, since its structures have been deallocated. + gzclose must not be called more than once on the same file, just as free + must not be called more than once on the same allocation. + + gzclose will return Z_STREAM_ERROR if file is not valid, Z_ERRNO on a + file operation error, Z_MEM_ERROR if out of memory, Z_BUF_ERROR if the + last read ended in the middle of a gzip stream, or Z_OK on success. +*/ + +ZEXTERN int ZEXPORT gzclose_r OF((gzFile file)); +ZEXTERN int ZEXPORT gzclose_w OF((gzFile file)); +/* + Same as gzclose(), but gzclose_r() is only for use when reading, and + gzclose_w() is only for use when writing or appending. The advantage to + using these instead of gzclose() is that they avoid linking in zlib + compression or decompression code that is not used when only reading or only + writing respectively. If gzclose() is used, then both compression and + decompression code will be included the application when linking to a static + zlib library. +*/ + +ZEXTERN const char * ZEXPORT gzerror OF((gzFile file, int *errnum)); +/* + Returns the error message for the last error which occurred on the given + compressed file. errnum is set to zlib error number. If an error occurred + in the file system and not in the compression library, errnum is set to + Z_ERRNO and the application may consult errno to get the exact error code. + + The application must not modify the returned string. Future calls to + this function may invalidate the previously returned string. If file is + closed, then the string previously returned by gzerror will no longer be + available. + + gzerror() should be used to distinguish errors from end-of-file for those + functions above that do not distinguish those cases in their return values. +*/ + +ZEXTERN void ZEXPORT gzclearerr OF((gzFile file)); +/* + Clears the error and end-of-file flags for file. This is analogous to the + clearerr() function in stdio. This is useful for continuing to read a gzip + file that is being written concurrently. +*/ + +#endif /* !Z_SOLO */ + + /* checksum functions */ + +/* + These functions are not related to compression but are exported + anyway because they might be useful in applications using the compression + library. +*/ + +ZEXTERN uLong ZEXPORT adler32 OF((uLong adler, const Bytef *buf, uInt len)); +/* + Update a running Adler-32 checksum with the bytes buf[0..len-1] and + return the updated checksum. If buf is Z_NULL, this function returns the + required initial value for the checksum. + + An Adler-32 checksum is almost as reliable as a CRC32 but can be computed + much faster. + + Usage example: + + uLong adler = adler32(0L, Z_NULL, 0); + + while (read_buffer(buffer, length) != EOF) { + adler = adler32(adler, buffer, length); + } + if (adler != original_adler) error(); +*/ + +/* +ZEXTERN uLong ZEXPORT adler32_combine OF((uLong adler1, uLong adler2, + z_off_t len2)); + + Combine two Adler-32 checksums into one. For two sequences of bytes, seq1 + and seq2 with lengths len1 and len2, Adler-32 checksums were calculated for + each, adler1 and adler2. adler32_combine() returns the Adler-32 checksum of + seq1 and seq2 concatenated, requiring only adler1, adler2, and len2. Note + that the z_off_t type (like off_t) is a signed integer. If len2 is + negative, the result has no meaning or utility. +*/ + +ZEXTERN uLong ZEXPORT crc32 OF((uLong crc, const Bytef *buf, uInt len)); +/* + Update a running CRC-32 with the bytes buf[0..len-1] and return the + updated CRC-32. If buf is Z_NULL, this function returns the required + initial value for the crc. Pre- and post-conditioning (one's complement) is + performed within this function so it shouldn't be done by the application. + + Usage example: + + uLong crc = crc32(0L, Z_NULL, 0); + + while (read_buffer(buffer, length) != EOF) { + crc = crc32(crc, buffer, length); + } + if (crc != original_crc) error(); +*/ + +/* +ZEXTERN uLong ZEXPORT crc32_combine OF((uLong crc1, uLong crc2, z_off_t len2)); + + Combine two CRC-32 check values into one. For two sequences of bytes, + seq1 and seq2 with lengths len1 and len2, CRC-32 check values were + calculated for each, crc1 and crc2. crc32_combine() returns the CRC-32 + check value of seq1 and seq2 concatenated, requiring only crc1, crc2, and + len2. +*/ + + + /* various hacks, don't look :) */ + +/* deflateInit and inflateInit are macros to allow checking the zlib version + * and the compiler's view of z_stream: + */ +ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level, + const char *version, int stream_size)); +ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm, + const char *version, int stream_size)); +ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int level, int method, + int windowBits, int memLevel, + int strategy, const char *version, + int stream_size)); +ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int windowBits, + const char *version, int stream_size)); +ZEXTERN int ZEXPORT inflateBackInit_ OF((z_streamp strm, int windowBits, + unsigned char FAR *window, + const char *version, + int stream_size)); +#define deflateInit(strm, level) \ + deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream)) +#define inflateInit(strm) \ + inflateInit_((strm), ZLIB_VERSION, (int)sizeof(z_stream)) +#define deflateInit2(strm, level, method, windowBits, memLevel, strategy) \ + deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\ + (strategy), ZLIB_VERSION, (int)sizeof(z_stream)) +#define inflateInit2(strm, windowBits) \ + inflateInit2_((strm), (windowBits), ZLIB_VERSION, \ + (int)sizeof(z_stream)) +#define inflateBackInit(strm, windowBits, window) \ + inflateBackInit_((strm), (windowBits), (window), \ + ZLIB_VERSION, (int)sizeof(z_stream)) + +#ifndef Z_SOLO + +/* gzgetc() macro and its supporting function and exposed data structure. Note + * that the real internal state is much larger than the exposed structure. + * This abbreviated structure exposes just enough for the gzgetc() macro. The + * user should not mess with these exposed elements, since their names or + * behavior could change in the future, perhaps even capriciously. They can + * only be used by the gzgetc() macro. You have been warned. + */ +struct gzFile_s { + unsigned have; + unsigned char *next; + z_off64_t pos; +}; +ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ +#ifdef Z_PREFIX_SET +# undef z_gzgetc +# define z_gzgetc(g) \ + ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : gzgetc(g)) +#else +# define gzgetc(g) \ + ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : gzgetc(g)) +#endif + +/* provide 64-bit offset functions if _LARGEFILE64_SOURCE defined, and/or + * change the regular functions to 64 bits if _FILE_OFFSET_BITS is 64 (if + * both are true, the application gets the *64 functions, and the regular + * functions are changed to 64 bits) -- in case these are set on systems + * without large file support, _LFS64_LARGEFILE must also be true + */ +#ifdef Z_LARGE64 + ZEXTERN gzFile ZEXPORT gzopen64 OF((const char *, const char *)); + ZEXTERN z_off64_t ZEXPORT gzseek64 OF((gzFile, z_off64_t, int)); + ZEXTERN z_off64_t ZEXPORT gztell64 OF((gzFile)); + ZEXTERN z_off64_t ZEXPORT gzoffset64 OF((gzFile)); + ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off64_t)); + ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off64_t)); +#endif + +#if !defined(ZLIB_INTERNAL) && defined(Z_WANT64) +# ifdef Z_PREFIX_SET +# define z_gzopen z_gzopen64 +# define z_gzseek z_gzseek64 +# define z_gztell z_gztell64 +# define z_gzoffset z_gzoffset64 +# define z_adler32_combine z_adler32_combine64 +# define z_crc32_combine z_crc32_combine64 +# else +# define gzopen gzopen64 +# define gzseek gzseek64 +# define gztell gztell64 +# define gzoffset gzoffset64 +# define adler32_combine adler32_combine64 +# define crc32_combine crc32_combine64 +# endif +# ifndef Z_LARGE64 + ZEXTERN gzFile ZEXPORT gzopen64 OF((const char *, const char *)); + ZEXTERN z_off_t ZEXPORT gzseek64 OF((gzFile, z_off_t, int)); + ZEXTERN z_off_t ZEXPORT gztell64 OF((gzFile)); + ZEXTERN z_off_t ZEXPORT gzoffset64 OF((gzFile)); + ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off_t)); +# endif +#else + ZEXTERN gzFile ZEXPORT gzopen OF((const char *, const char *)); + ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile, z_off_t, int)); + ZEXTERN z_off_t ZEXPORT gztell OF((gzFile)); + ZEXTERN z_off_t ZEXPORT gzoffset OF((gzFile)); + ZEXTERN uLong ZEXPORT adler32_combine OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine OF((uLong, uLong, z_off_t)); +#endif + +#else /* Z_SOLO */ + + ZEXTERN uLong ZEXPORT adler32_combine OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine OF((uLong, uLong, z_off_t)); + +#endif /* !Z_SOLO */ + +/* hack for buggy compilers */ +#if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL) + struct internal_state {int dummy;}; +#endif + +/* undocumented functions */ +ZEXTERN const char * ZEXPORT zError OF((int)); +ZEXTERN int ZEXPORT inflateSyncPoint OF((z_streamp)); +ZEXTERN const z_crc_t FAR * ZEXPORT get_crc_table OF((void)); +ZEXTERN int ZEXPORT inflateUndermine OF((z_streamp, int)); +ZEXTERN int ZEXPORT inflateResetKeep OF((z_streamp)); +ZEXTERN int ZEXPORT deflateResetKeep OF((z_streamp)); +#if defined(_WIN32) && !defined(Z_SOLO) +ZEXTERN gzFile ZEXPORT gzopen_w OF((const wchar_t *path, + const char *mode)); +#endif +#if defined(STDC) || defined(Z_HAVE_STDARG_H) +# ifndef Z_SOLO +ZEXTERN int ZEXPORTVA gzvprintf Z_ARG((gzFile file, + const char *format, + va_list va)); +# endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ZLIB_H */ diff --git a/platform/mcu/xr871/src/cedarx/muxer/Makefile.am b/platform/mcu/xr871/src/cedarx/muxer/Makefile.am new file mode 100644 index 0000000000..7a36b24f19 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/Makefile.am @@ -0,0 +1,2 @@ + +SUBDIRS = aac mp4 ts base diff --git a/platform/mcu/xr871/src/cedarx/muxer/RecoderCbWriter.h b/platform/mcu/xr871/src/cedarx/muxer/RecoderCbWriter.h new file mode 100644 index 0000000000..c96eb0efc5 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/RecoderCbWriter.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : RecoderWriter.h + * Description : RecoderWriter + * History : + * + */ + + +#ifndef __RECODER_CBWRITER_H__ +#define __RECODER_CBWRITER_H__ + +#include "CdxWriter.h" + +typedef uint32_t (*CdxWriterCb)(void *buf, uint32_t size); + +typedef struct RecoderCbWriter RecoderCbWriterT; +struct RecoderCbWriter +{ + CdxWriterT cdx_writer; + int file_mode; + int fd_file; + CdxWriterCb cb; +}; + +typedef struct WriterDataDest { + char *pUrl; + void *pArg; +} WriterDataDest; + +CdxWriterT *CdxCbWriterCreat(WriterDataDest *dataDest); +void CdxCbWriterDestroy(CdxWriterT *writer); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/muxer/RecoderWriter.h b/platform/mcu/xr871/src/cedarx/muxer/RecoderWriter.h new file mode 100644 index 0000000000..69b20bb809 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/RecoderWriter.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : RecoderWriter.h + * Description : RecoderWriter + * History : + * + */ + + +#ifndef __RECODER_WRITER_H__ +#define __RECODER_WRITER_H__ + +#include "CdxWriter.h" +#include "cedarx_fs.h" + +typedef enum CDX_FILE_MODE +{ +#if FD_SUPPORT + FD_FILE_MODE, +#endif + FP_FILE_MODE +}CDX_FILE_MODE; + +typedef struct RecoderWriter RecoderWriterT; +struct RecoderWriter +{ + CdxWriterT cdx_writer; + int file_mode; + int fd_file; + FILE *fp_file; + char *file_path; +}; + +int RWOpen(CdxWriterT *writer); +int RWClose(CdxWriterT *writer); +CdxWriterT *CdxWriterCreat(char* pUrl); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/muxer/aac/CdxAacMuxer.h b/platform/mcu/xr871/src/cedarx/muxer/aac/CdxAacMuxer.h new file mode 100644 index 0000000000..3222c57994 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/aac/CdxAacMuxer.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxAacMuxer.h + * Description : Allwinner AAC Muxer Definition + * History : + * + */ + +#ifndef CDX_AAC_MUXER_H +#define CDX_AAC_MUXER_H + +#include +#include "CdxMuxer.h" +#include "CdxMuxerBaseDef.h" + +#endif /* CDX_AAC_MUXER_H */ diff --git a/platform/mcu/xr871/src/cedarx/muxer/aac/Makefile.am b/platform/mcu/xr871/src/cedarx/muxer/aac/Makefile.am new file mode 100644 index 0000000000..c14686d636 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/aac/Makefile.am @@ -0,0 +1,27 @@ + +include $(top_srcdir)/Makefile.inc + +noinst_LTLIBRARIES = libcdx_aac_muxer.la + +## set the source files. +libcdx_aac_muxer_la_SOURCES = CdxAacMuxer.c + +libcdx_aac_muxer_la_CFLAGS = $(CFLAGS_CDXG) +LOCAL_INCLUDE = -I../include \ + -I../../include \ + -I../../base/include \ + -I../base \ + -I$(top_srcdir)/external/include/aencoder \ + -I$(top_srcdir)/../libcedarc/include \ + -I$(top_srcdir)/ + +libcdx_aac_muxer_la_CFLAGS += $(LOCAL_INCLUDE) + + +libcdx_aac_muxer_la_LDFLAGS = $(LDFLAGS_CDXG) + +libcdx_aac_muxer_la_LIBADD = $(top_srcdir)/libcore/base/libcdx_base.la + +#LOCAL_LIB = -lpthread +libcdx_aac_muxer_la_LDFLAGS += $(LOCAL_LIB) + diff --git a/platform/mcu/xr871/src/cedarx/muxer/base/CdxMuxerBaseDef.h b/platform/mcu/xr871/src/cedarx/muxer/base/CdxMuxerBaseDef.h new file mode 100644 index 0000000000..283317273f --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/base/CdxMuxerBaseDef.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxMuxerBaseDef.h + * Description : Allwinner Muxer Base Definition + * History : + * + */ + +#ifndef CDX_MUXER_BASE_DEF_H +#define CDX_MUXER_BASE_DEF_H + +typedef enum { + CODEC_TYPE_UNKNOWN = -1, + CODEC_TYPE_VIDEO = 0, //don't change it! + CODEC_TYPE_AUDIO = 1, //don't change it! + CODEC_TYPE_SUBTITLE, + CODEC_TYPE_DATA +}CodecType; + +typedef enum { + MUX_CODEC_ID_MPEG4 = 32, + MUX_CODEC_ID_H264 = 33, + MUX_CODEC_ID_MJPEG = 108, + MUX_CODEC_ID_AAC = 64, + MUX_CODEC_ID_MP3 = 105, + MUX_CODEC_ID_PCM, // 16-bit little-endian, twos-complement + MUX_CODEC_ID_ADPCM, // DVI/Intel IMAADPCM-ACM code 17 +}MuxCodecID; + +#endif /* CDX_MUXER_BASE_DEF_H */ diff --git a/platform/mcu/xr871/src/cedarx/muxer/base/CdxTsemaphore.h b/platform/mcu/xr871/src/cedarx/muxer/base/CdxTsemaphore.h new file mode 100644 index 0000000000..49e59266b3 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/base/CdxTsemaphore.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxTsemaphore.h + * Description : Allwinner Muxer Writer with Thread Operation + * History : + * Author : Q Wang + * Date : 2014/12/17 + * Comment : ʼ汾V3 CedarX_1.0 + * + * Author : GJ Wu + * Date : 2016/04/18 + * Comment_: ޸ֲCedarX_2.0 + */ + +#ifndef __CDX_TSEMAPHORE_H__ +#define __CDX_TSEMAPHORE_H__ + +#include + +typedef struct CdxSem +{ + pthread_cond_t condition; + pthread_mutex_t mutex; + unsigned int semval; +}CdxSemT; + +int CdxSemInit(CdxSemT *tsem, unsigned int val); +void CdxSemDeinit(CdxSemT *tsem); +void CdxSemDown(CdxSemT *tsem); +void CdxSemUp(CdxSemT *tsem); +void CdxSemUpUnique(CdxSemT *tsem); +void CdxSemReset(CdxSemT *tsem); +void CdxSemWait(CdxSemT *tsem); +void CdxSemSignal(CdxSemT *tsem); +unsigned int CdxSemGetVal(CdxSemT *tsem); + + +#define cdx_mutex_lock(x) pthread_mutex_lock(x) +#define cdx_mutex_unlock(x) pthread_mutex_unlock(x) + +#define cdx_cond_wait_while_exp(tsem, expression) \ + pthread_mutex_lock(&tsem.mutex); \ + while (expression) { \ + pthread_cond_wait(&tsem.condition, &tsem.mutex); \ + } \ + pthread_mutex_unlock(&tsem.mutex); + +#define cdx_cond_wait_if_exp(tsem, expression) \ + pthread_mutex_lock(&tsem.mutex); \ + if (expression) { \ + pthread_cond_wait(&tsem.condition, &tsem.mutex); \ + } \ + pthread_mutex_unlock(&tsem.mutex); + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/muxer/base/Makefile.am b/platform/mcu/xr871/src/cedarx/muxer/base/Makefile.am new file mode 100644 index 0000000000..55a994ce79 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/base/Makefile.am @@ -0,0 +1,38 @@ +include $(top_srcdir)/Makefile.inc + +lib_LTLIBRARIES = libcdx_muxer.la + +## set the source files. +libcdx_muxer_la_SOURCES = CdxFsCache.c \ + CdxFsSimpleCache.c \ + CdxFsWriteDirect.c \ + CdxFsWriter.c \ + CdxMuxer.c \ + CdxTsemaphore.c + +libcdx_muxer_la_CFLAGS = $(CFLAGS_CDXG) +LOCAL_INCLUDE = -I../include \ + -I../../include \ + -I../../base/include \ + -I../base \ + -I$(top_srcdir)/external/include/aencoder \ + -I$(top_srcdir)/../libcedarc/include \ + -I$(top_srcdir)/ + +libcdx_muxer_la_CFLAGS += $(LOCAL_INCLUDE) + + +libcdx_muxer_la_LDFLAGS = $(LDFLAGS_CDXG) + +libcdx_muxer_la_LIBADD = $(top_srcdir)/libcore/muxer/aac/libcdx_aac_muxer.la \ + $(top_srcdir)/libcore/muxer/mp4/libcdx_mp4_muxer.la \ + $(top_srcdir)/libcore/muxer/ts/libcdx_ts_muxer.la \ + $(top_srcdir)/libcore/base/libcdx_base.la + +# $(top_srcdir)/libcore/muxer/mp4ex/libcdx_mp4ex_muxer.la + +LOCAL_LIB = -lpthread -laencoder -lcdc_vencoder +libcdx_muxer_la_LDFLAGS += $(LOCAL_LIB) + + + diff --git a/platform/mcu/xr871/src/cedarx/muxer/include/CdxMuxer.h b/platform/mcu/xr871/src/cedarx/muxer/include/CdxMuxer.h new file mode 100644 index 0000000000..b62493a1b5 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/include/CdxMuxer.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxMuxer.h + * Description : Allwinner Muxer Definition + * History : + * + */ + +#ifndef CDX_MUXER_H +#define CDX_MUXER_H + +#include +#include +//#include +#include +#include +#include +#include + +typedef enum { + UNKNOWN_CMD = 0, + SET_CACHE_MEM, + SET_FS_WRITE_MODE, + SET_FS_SIMPLE_CACHE_SIZE, + SET_MP4_TMP_PATH, + SET_PLAY_TIME_LENGTH, + SET_IS_SDCARD_DISAPPEAR, + GET_IS_SDCARD_DISAPPEAR +} MuxCtrlCommads; + +typedef enum tag_FSWRITEMODE { + FSWRITEMODE_CACHETHREAD = 0, + FSWRITEMODE_SIMPLECACHE, + FSWRITEMODE_DIRECT, +}FSWRITEMODE; + +typedef struct CdxFsCacheMemInfo +{ + cdx_uint8 *mp_cache; + cdx_uint32 m_cache_size; +}CdxFsCacheMemInfo; + +enum CdxMuxerTypeE +{ + CDX_MUXER_UNKNOW = -1, + CDX_MUXER_MOV, + CDX_MUXER_TS, + CDX_MUXER_AVI, + CDX_MUXER_AAC, + CDX_MUXER_MP3, + CDX_MUXER_MOV_EX, + CDX_MUXER_AMR, //add +}; + +#define FS_WRITER (0) + +typedef struct CdxMuxerCreatorS CdxMuxerCreatorT; +typedef struct CdxMuxerS CdxMuxerT; +typedef enum CdxMuxerTypeE CdxMuxerTypeT; +typedef struct CdxMuxerMediaInfoS CdxMuxerMediaInfoT; +typedef struct MuxerVideoStreamInfoS MuxerVideoStreamInfoT; +typedef struct MuxerAudioStreamInfoS MuxerAudioStreamInfoT; +typedef struct CdxMuxerPacketS CdxMuxerPacketT; + +struct CdxMuxerCreatorS +{ + CdxMuxerT *(*create)(CdxWriterT* /* stream */); +}; + +struct CdxMuxerPacketS +{ + void *buf; + cdx_int32 buflen; + cdx_int64 pts; + cdx_int64 duration; + cdx_int32 type; + cdx_int32 length; + cdx_int32 streamIndex; +}; + +struct CdxMuxerOpsS +{ + cdx_int32 (*writeExtraData)(CdxMuxerT *, unsigned char* /* extradata */, + int /* extradataLen */, int idx); + cdx_int32 (*writeHeader)(CdxMuxerT *); + cdx_int32 (*writePacket)(CdxMuxerT *, CdxMuxerPacketT * /* pkt */); + cdx_int32 (*writeTrailer)(CdxMuxerT *); + cdx_int32 (*control)(CdxMuxerT *, int /* uCmd */, void * /* pParam*/); + cdx_int32 (*close)(CdxMuxerT *); + cdx_int32 (*setMediaInfo)(CdxMuxerT *, CdxMuxerMediaInfoT *); +}; + +struct CdxMuxerS +{ + enum CdxMuxerTypeE type; + struct CdxMuxerOpsS *ops; +}; + +#if VIDEO_SUPPORT +struct MuxerVideoStreamInfoS +{ + VENC_CODEC_TYPE eCodeType; + int nWidth; + int nHeight; + int nFrameRate; + int nCreatTime; + int nRotateDegree; +}; +#endif + +#define ADECODER_MAX_LANG_CHAR_SIZE (64) +struct MuxerAudioStreamInfoS +{ + AUDIO_ENCODER_TYPE eCodecFormat; + int nChannelNum; + int nBitsPerSample; + int nSampleCntPerFrame; + int nSampleRate; + int nAvgBitrate; + int nMaxBitRate; + unsigned char strLang[ADECODER_MAX_LANG_CHAR_SIZE]; +}; + +#if VIDEO_SUPPORT +#define MAX_VIDEO_NUM 2 +#endif +#define MAX_AUDIO_NUM 2 +struct CdxMuxerMediaInfoS +{ + int audioNum; +#if VIDEO_SUPPORT + int videoNum; + MuxerVideoStreamInfoT video; +#endif + MuxerAudioStreamInfoT audio; + int geo_available; + int latitudex; + int longitudex; + FSWRITEMODE writer_mode; +}; + +#if FS_WRITER +#define ByteIOContext CdxFsWriter +#else +#define ByteIOContext CdxWriterT +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +CdxMuxerT *CdxMuxerCreate(CdxMuxerTypeT type, CdxWriterT *stream); + +static inline int CdxMuxerSetMediaInfo(CdxMuxerT *mux, CdxMuxerMediaInfoT *mediaInfo) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->setMediaInfo); + return mux->ops->setMediaInfo(mux, mediaInfo); +} + +static inline int CdxMuxerWriteExtraData(CdxMuxerT *mux, unsigned char* pdata, + int data_len, int index) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->writeHeader); + return mux->ops->writeExtraData(mux, pdata, data_len, index); +} + +static inline int CdxMuxerWriteHeader(CdxMuxerT *mux) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->writeHeader); + return mux->ops->writeHeader(mux); +} + +static inline int CdxMuxerWritePacket(CdxMuxerT *mux, CdxMuxerPacketT *pkt) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->writePacket); + return mux->ops->writePacket(mux, pkt); +} + +static inline int CdxMuxerWriteTrailer(CdxMuxerT *mux) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->writeTrailer); + return mux->ops->writeTrailer(mux); +} + +static inline int CdxMuxerControl(CdxMuxerT *mux, int uCmd, void * pParam) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->control); + return mux->ops->control(mux, uCmd, pParam); +} + +static inline int CdxMuxerClose(CdxMuxerT *mux) +{ + CDX_CHECK(mux); + CDX_CHECK(mux->ops); + CDX_CHECK(mux->ops->close); + return mux->ops->close(mux); +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/mcu/xr871/src/cedarx/muxer/include/CdxWriter.h b/platform/mcu/xr871/src/cedarx/muxer/include/CdxWriter.h new file mode 100644 index 0000000000..a1b9339098 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/muxer/include/CdxWriter.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxWriter.h + * Description : Allwinner Muxer Writer Definition + * History : + * + */ + +#ifndef __CDX_WRITER_H__ +#define __CDX_WRITER_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct CdxWriterS CdxWriterT; +struct CdxWriterOps{ + int (*read)(CdxWriterT *thiz, void *buf, int size); + int (*write)(CdxWriterT *thiz, void *buf, int size); + long (*seek)(CdxWriterT *thiz, long moffset, int mwhere); + long (*tell)(CdxWriterT *thiz); + int (*close)(CdxWriterT *thiz); +}; + +struct CdxWriterS +{ + struct CdxWriterOps* ops; + char* uri; +}; + +static inline int CdxWriterRead(CdxWriterT *w, void *buf, int size) +{ + CDX_CHECK(w); + CDX_CHECK(w->ops); + CDX_CHECK(w->ops->read); + return w->ops->read(w, buf, size); +} + +static inline int CdxWriterWrite(CdxWriterT *w, void *buf, int size) +{ + CDX_CHECK(w); + CDX_CHECK(w->ops); + CDX_CHECK(w->ops->write); + return w->ops->write(w, buf, size); +} + +static inline int CdxWriterSeek(CdxWriterT *w, long moffset, int mwhere) +{ + CDX_CHECK(w); + CDX_CHECK(w->ops); + CDX_CHECK(w->ops->seek); + return w->ops->seek(w, moffset, mwhere); +} + +static inline int CdxWriterTell(CdxWriterT *w) +{ + CDX_CHECK(w); + CDX_CHECK(w->ops); + CDX_CHECK(w->ops->tell); + return w->ops->tell(w); +} + +static inline int CdxWriterClose(CdxWriterT *w) +{ + CDX_CHECK(w); + CDX_CHECK(w->ops); + CDX_CHECK(w->ops->close); + return w->ops->close(w); +} + + +//CdxWriterT *CdxWriterCreat(); +void CdxWriterDestroy(CdxWriterT *writer); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/os_glue/include/atomic.h b/platform/mcu/xr871/src/cedarx/os_glue/include/atomic.h new file mode 100644 index 0000000000..797181c40c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/os_glue/include/atomic.h @@ -0,0 +1,41 @@ +#ifndef _OS_GLUE_ATOMIC +#define _OS_GLUE_ATOMIC +#include +#include "sys/interrupt.h" + +#define ENTER_CRITICAL() arch_irq_disable() + +#define EXIT_CRITICAL() arch_irq_enable() + +#define __sync_fetch_and_add sync_fetch_and_add +#define __sync_fetch_and_sub sync_fetch_and_sub +#define __sync_fetch_and_or sync_fetch_and_or +#define __sync_fetch_and_and sync_fetch_and_and +#define __sync_fetch_and_xor sync_fetch_and_xor +#define __sync_fetch_and_nand sync_fetch_and_nand +#define __sync_add_and_fetch sync_add_and_fetch +#define __sync_sub_and_fetch sync_sub_and_fetch +#define __sync_or_and_fetch sync_or_and_fetch +#define __sync_and_and_fetch sync_and_and_fetch +#define __sync_xor_and_fetch sync_xor_and_fetch +#define __sync_nand_and_fetch sync_nand_and_fetch +#define __sync_lock_test_and_set sync_lock_test_and_set +#define __sync_bool_compare_and_swap sync_bool_compare_and_swap +#define __sync_bool_compare_and_swap sync_bool_compare_and_swap + +signed long sync_fetch_and_add(volatile signed long *ptr, signed long value); +signed long sync_fetch_and_sub(volatile signed long *ptr, signed long value); +signed long sync_fetch_and_or(volatile signed long *ptr, signed long value); +signed long sync_fetch_and_and(volatile signed long *ptr, signed long value); +signed long sync_fetch_and_xor(volatile signed long *ptr, signed long value); +signed long sync_fetch_and_nand(volatile signed long *ptr,signed long value); +signed long sync_add_and_fetch(volatile signed long *ptr, signed long value); +signed long sync_sub_and_fetch(volatile signed long *ptr, signed long value); +signed long sync_or_and_fetch(volatile signed long *ptr, signed long value); +signed long sync_and_and_fetch(volatile signed long *ptr, signed long value); +signed long sync_xor_and_fetch(volatile signed long *ptr, signed long value); +signed long sync_nand_and_fetch(volatile signed long *ptr,signed long value); +signed long sync_lock_test_and_set(volatile signed long *ptr,signed long value); +int sync_bool_compare_and_swap(volatile signed long *ptr,signed long oldvalue, signed long newvalue); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/os_glue/include/cedarx_fs.h b/platform/mcu/xr871/src/cedarx/os_glue/include/cedarx_fs.h new file mode 100644 index 0000000000..fb0ce98cf5 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/os_glue/include/cedarx_fs.h @@ -0,0 +1,56 @@ +#ifndef _FS_ +#define _FS_ +//#include +//#include +//#include + +#include "cdx_log.h" +#include "fs/fatfs/ff.h" + +//#define O_RDONLY 00000000 +//#define O_WRONLY 00000001 +//#define O_RDWR 00000002 +//#define O_CREAT 00000100 /* not fcntl */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#define FILE FIL + +#define SEEK_SET 0 +#define SEEK_CUR 1 +#define SEEK_END 2 + +FILE * cedarx_fopen(const char * filename, const char * mode); +int cedarx_fseek(FILE * stream, long long offset, int whence); +long long cedarx_ftell(FILE * stream); +int cedarx_fclose(FILE * stream); +int cedarx_fwrite(const void * ptr, int size, int nmemb, FILE * stream); +int cedarx_fread(void * ptr, int size, int nmemb, FILE * stream); + +#define fopen cedarx_fopen +#define fseek cedarx_fseek +#define ftell cedarx_ftell +#define fclose cedarx_fclose +#define fwrite cedarx_fwrite +#define fread cedarx_fread + + +#if 0 +int fputc(int c, ES_FILE *fp); +#endif + +#if FD_SUPPORT +int open(const char *name, int flag, int prems); +int close(int fd); +int read(int fd, void *buf, unsigned count); +int sscanf( const char *, const char *, ...); +signed long long lseek(int fd, signed long long offset, int whence); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/os_glue/include/list.h b/platform/mcu/xr871/src/cedarx/os_glue/include/list.h new file mode 100644 index 0000000000..b8d2b47f60 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/os_glue/include/list.h @@ -0,0 +1,193 @@ +#ifndef __MELIS_PTHREAD_LIST_H__ +#define __MELIS_PTHREAD_LIST_H__ + +#define prefetch(x) x +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +#define INIT_LIST_HEAD(ptr) do { \ + (ptr)->next = (ptr); (ptr)->prev = (ptr); \ +} while (0) + + +static __inline void __list_add(struct list_head * new, + struct list_head * prev, + struct list_head * next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static __inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static __inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static __inline void __list_del(struct list_head * prev, + struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty on entry does not return true after this, the entry is in an undefined state. + */ +static __inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static __inline void list_del_init(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + INIT_LIST_HEAD(entry); +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static __inline int list_empty(struct list_head *head) +{ + return head->next == head; +} + +/** + * list_splice - join two lists + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static __inline void list_splice(struct list_head *list, struct list_head *head) +{ + struct list_head *first = list->next; + + if (first != list) { + struct list_head *last = list->prev; + struct list_head *at = head->next; + + first->prev = head; + head->next = first; + + last->next = at; + at->prev = last; + } +} + +static __inline int list_valid_check(struct list_head *head) +{ + struct list_head *next = head->next; + if(next == head) + return 0; + while(next!=head) + { + next = next->next; + if(next == next->prev) + { + return -1; + } + } + return 1; +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop counter. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next /*, prefetch(pos->next)*/; pos != (head); \ + pos = pos->next /*, prefetch(pos->next)*/) +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop counter. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; /*prefetch(pos->prev), */pos != (head); \ + pos = pos->prev) + + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop counter. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop counter. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) + +#endif /* __MELIS_PTHREAD_LIST_H__ */ + diff --git a/platform/mcu/xr871/src/cedarx/os_glue/include/pthread.h b/platform/mcu/xr871/src/cedarx/os_glue/include/pthread.h new file mode 100644 index 0000000000..2922412a3c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/os_glue/include/pthread.h @@ -0,0 +1,290 @@ +#ifndef _PTHREAD_H_ +#define _PTHREAD_H_ +//#include +//#include +#include +#include +//#include +#include "kernel/os/os.h" + +#define ONCE_INITIALIZING (1 << 0) +#define ONCE_COMPLETED (1 << 1) +#define PTHREAD_ONCE_INIT 0 + + +#if defined(__LP64__) + #define __RESERVED_INITIALIZER , {0} +#else + #define __RESERVED_INITIALIZER +#endif + +typedef long long int64_t; +typedef int pthread_key_t; +typedef void * pthread_t; +typedef volatile int pthread_once_t; +typedef int pid_t; +typedef long time_t; + +typedef enum MELIS_2_PTHREAD_OS_STATE +{ + PTHREAD_TASK_STATE_READY = 0, + PTHREAD_TASK_STATE_RUNNING, + PTHREAD_TASK_STATE_EXIT, + PTHREAD_TASK_STATE_INVALID, +}pthread_osstate_t; + + +/*typedef struct { + unsigned int flag; + unsigned int entercnt; + pthread_t owner; + __krnl_event_t* lock; +}pthread_mutex_t;*/ + +typedef struct { +// unsigned int flag; +// unsigned int entercnt; +// pthread_t owner; + OS_Mutex_t lock; +} pthread_mutex_t; + +typedef struct { + int cnt; + int wait; + OS_Semaphore_t sem; +} sem_t; + +/*struct timespec { + long tv_sec; + long tv_nsec; +}; + +struct timeval{ + long tv_sec; + long tv_usec; +}; + +struct timezone { + int tz_minuteswest; + int tz_dsttime; +};*/ + +//#define CLOCK_REALTIME 0 +#define CLOCK_MONOTONIC (CLOCK_REALTIME + 1) +#define SEM_MAX_VALUE 0xffff +#define ETIMEOUT 21 +#define EINVAL 22 +#define __PTHREAD_MUTEX_INIT_VALUE 0 +#define __PTHREAD_RECURSIVE_MUTEX_INIT_VALUE 0x4000 +#define __PTHREAD_ERRORCHECK_MUTEX_INIT_VALUE 0x8000 + +#define PTHREAD_MUTEX_INITIALIZER {__PTHREAD_MUTEX_INIT_VALUE __RESERVED_INITIALIZER} +#define PTHREAD_RECURSIVE_MUTEX_INITIALIZER {__PTHREAD_RECURSIVE_MUTEX_INIT_VALUE __RESERVED_INITIALIZER} +#define PTHREAD_ERRORCHECK_MUTEX_INITIALIZER {__PTHREAD_ERRORCHECK_MUTEX_INIT_VALUE __RESERVED_INITIALIZER} + +enum { + PTHREAD_MUTEX_NORMAL = 0, + PTHREAD_MUTEX_RECURSIVE = 1, + PTHREAD_MUTEX_ERRORCHECK = 2, + + PTHREAD_MUTEX_ERRORCHECK_NP = PTHREAD_MUTEX_ERRORCHECK, + PTHREAD_MUTEX_RECURSIVE_NP = PTHREAD_MUTEX_RECURSIVE, + + PTHREAD_MUTEX_DEFAULT = PTHREAD_MUTEX_NORMAL +}; + +enum +{ + PTHREAD_EVENT_SET_0 = 1<<0, + PTHREAD_EVENT_SET_1 = 1<<1, + PTHREAD_EVENT_SET_2 = 1<<2, + PTHREAD_EVENT_SET_3 = 1<<3, + PTHREAD_EVENT_SET_4 = 1<<4, + PTHREAD_EVENT_SET_5 = 1<<5, + PTHREAD_EVENT_SET_6 = 1<<6 +}; + + +typedef sem_t pthread_cond_t; + +#define PTHREAD_COND_INITIALIZER {0 __RESERVED_INITIALIZER} + +typedef struct { + unsigned int flags; + void* stack_base; + size_t stack_size; + size_t guard_size; + int sched_policy; + int sched_priority; +#ifdef __LP64__ + char __reserved[16]; +#endif +} pthread_attr_t; + +typedef long pthread_mutexattr_t; +typedef long pthread_condattr_t; + +typedef long pthread_rwlockattr_t; + +typedef struct { +#if !defined(__LP64__) + pthread_mutex_t __unused_lock; + pthread_cond_t __unused_cond; +#endif + volatile int state; // 0=unlock, -1=writer lock, +n=reader lock + volatile int writer_thread_id; + volatile int pending_readers; + volatile int pending_writers; + int attr; +#ifdef __LP64__ + char __reserved[36]; +#else + char __reserved[12]; +#endif + +} pthread_rwlock_t; + +#ifdef __LP64__ + #define PTHREAD_RWLOCK_INITIALIZER { 0, 0, 0, 0, 0, { 0 } } +#else + #define PTHREAD_RWLOCK_INITIALIZER { PTHREAD_MUTEX_INITIALIZER, PTHREAD_COND_INITIALIZER, 0, 0, 0, 0, 0, { 0 } } +#endif + +#define PTHREAD_ONCE_INIT 0 + +#if defined(__LP64__) +#define PTHREAD_STACK_MIN (4 * PAGE_SIZE) +#else +#define PTHREAD_STACK_MIN (2 * PAGE_SIZE) +#endif + +#define PTHREAD_CREATE_DETACHED 0x00000001 +#define PTHREAD_CREATE_JOINABLE 0x00000000 + +#define PTHREAD_PROCESS_PRIVATE 0 +#define PTHREAD_PROCESS_SHARED 1 + +#define PTHREAD_SCOPE_SYSTEM 0 +#define PTHREAD_SCOPE_PROCESS 1 + +typedef void (*__pthread_cleanup_func_t)(void*); + +typedef struct __pthread_cleanup_t { + struct __pthread_cleanup_t* __cleanup_prev; + __pthread_cleanup_func_t __cleanup_routine; + void* __cleanup_arg; +} __pthread_cleanup_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + pid_t gettid(void); + int pthread_atfork(void (*)(void), void (*)(void), void(*)(void)); + int pthread_attr_destroy(pthread_attr_t*); + int pthread_attr_getdetachstate(const pthread_attr_t*, int*); + int pthread_attr_getguardsize(const pthread_attr_t*, size_t*); + int pthread_attr_getschedpolicy(const pthread_attr_t*, int*); + int pthread_attr_getscope(const pthread_attr_t*, int*); + int pthread_attr_getstack(const pthread_attr_t*, void**, size_t*); + int pthread_attr_getstacksize(const pthread_attr_t*, size_t*) ; + int pthread_attr_init(pthread_attr_t*); + int pthread_attr_setdetachstate(pthread_attr_t*, int); + int pthread_attr_setguardsize(pthread_attr_t*, size_t); + int pthread_attr_setschedpolicy(pthread_attr_t*, int); + int pthread_attr_setscope(pthread_attr_t*, int); + int pthread_attr_setstack(pthread_attr_t*, void*, size_t); + int pthread_attr_setstacksize(pthread_attr_t*, size_t stack_size); + + int pthread_condattr_destroy(pthread_condattr_t*); + int pthread_condattr_getpshared(const pthread_condattr_t*, int*); + int pthread_condattr_init(pthread_condattr_t*); + int pthread_condattr_setpshared(pthread_condattr_t*, int); + + int pthread_cond_broadcast(pthread_cond_t*); + int pthread_cond_destroy(pthread_cond_t*); + int pthread_cond_init(pthread_cond_t*, const pthread_condattr_t*); + int pthread_cond_signal(pthread_cond_t*); + int pthread_cond_timedwait(pthread_cond_t*, pthread_mutex_t*, const struct timespec*); + int pthread_cond_wait(pthread_cond_t*, pthread_mutex_t*); + + int pthread_create(pthread_t*, pthread_attr_t const*, void *(*)(void*), void*); + int pthread_detach(pthread_t); + void pthread_exit(void*); + + int pthread_equal(pthread_t, pthread_t); + + int pthread_getattr_np(pthread_t, pthread_attr_t*); + void* pthread_getspecific(pthread_key_t); + + pid_t pthread_gettid_np(pthread_t); + + int pthread_join(pthread_t, void**); + + int pthread_key_create(pthread_key_t*, void (*)(void*)); + int pthread_key_delete(pthread_key_t); + + int pthread_kill(pthread_t, int); + + int pthread_mutexattr_destroy(pthread_mutexattr_t*); + int pthread_mutexattr_getpshared(const pthread_mutexattr_t*, int*); + int pthread_mutexattr_gettype(const pthread_mutexattr_t*, int*); + int pthread_mutexattr_init(pthread_mutexattr_t*) ; + int pthread_mutexattr_setpshared(pthread_mutexattr_t*, int); + int pthread_mutexattr_settype(pthread_mutexattr_t*, int); + + int pthread_mutex_destroy(pthread_mutex_t*); + int pthread_mutex_init(pthread_mutex_t*, const pthread_mutexattr_t*); + int pthread_mutex_lock(pthread_mutex_t*) ; + int pthread_mutex_timedlock(pthread_mutex_t*, const struct timespec*); + int pthread_mutex_trylock(pthread_mutex_t*) ; + int pthread_mutex_unlock(pthread_mutex_t*) ; + + int pthread_once(pthread_once_t*, void (*)(void)); + + int pthread_rwlockattr_destroy(pthread_rwlockattr_t*); + int pthread_rwlockattr_getpshared(const pthread_rwlockattr_t*, int*); + int pthread_rwlockattr_init(pthread_rwlockattr_t*); + int pthread_rwlockattr_setpshared(pthread_rwlockattr_t*, int); + + int pthread_rwlock_destroy(pthread_rwlock_t*); + int pthread_rwlock_init(pthread_rwlock_t*, const pthread_rwlockattr_t*) ; + int pthread_rwlock_rdlock(pthread_rwlock_t*) ; + int pthread_rwlock_timedrdlock(pthread_rwlock_t*, const struct timespec*); + int pthread_rwlock_timedwrlock(pthread_rwlock_t*, const struct timespec*); + int pthread_rwlock_tryrdlock(pthread_rwlock_t*); + int pthread_rwlock_trywrlock(pthread_rwlock_t*); + int pthread_rwlock_unlock(pthread_rwlock_t *rwlock); + int pthread_rwlock_wrlock(pthread_rwlock_t*); + time_t time(time_t *t); + + pthread_t pthread_self(void); + + int pthread_setname_np(pthread_t, const char*); + int pthread_setspecific(pthread_key_t, const void*); + + + + extern void __pthread_cleanup_push(__pthread_cleanup_t* c, __pthread_cleanup_func_t, void*); + extern void __pthread_cleanup_pop(__pthread_cleanup_t*, int); + + int sem_init(sem_t *sem, int pshared, unsigned int value); + int sem_destroy(sem_t *sem); + int sem_wait (sem_t *sem); + int sem_timedwait(sem_t *sem, const struct timespec *abs_timeout); + int sem_post(sem_t *sem); + int sem_trywait(sem_t *sem); + int sem_getvalue(sem_t *sem, int *sval); + int sem_unlink(const char* name); + int sem_close(sem_t *sem); + sem_t *sem_open(const char *name, int oflag, ...); +#define gettimeofday __gettimeofday + int __gettimeofday(struct timeval* tv, struct timezone* tz); + void cdx_abort(void); + int clock_gettime(int a,struct timespec *t); + void exit(int status); +#ifdef __cplusplus +} +#endif + +#endif /* _PTHREAD_H_ */ diff --git a/platform/mcu/xr871/src/cedarx/os_glue/include/unistd.h b/platform/mcu/xr871/src/cedarx/os_glue/include/unistd.h new file mode 100644 index 0000000000..3b0318f37c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/os_glue/include/unistd.h @@ -0,0 +1,26 @@ +#ifndef _UNISTD_H_ +#define _UNISTD_H_ +#include "kernel/os/os.h" + +#ifdef __cplusplus +extern "C" +{ +#endif +static inline int usleep(unsigned int usecs) { + OS_MSleep((usecs + 999) / 1000); +// OS_MSleep((usecs + 1023) & (~1023)); + return 0; +} +static inline int msleep(unsigned int msecs) { + OS_MSleep(msecs); + return 0; +} +static inline void sleep(int seconds) { + OS_Sleep(seconds); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/amr/CdxAmrParser.h b/platform/mcu/xr871/src/cedarx/parser/amr/CdxAmrParser.h new file mode 100644 index 0000000000..6532d23a76 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/amr/CdxAmrParser.h @@ -0,0 +1,50 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : CdxAmrParser.h +* Description : Amr Parser +* History : +* +*/ +#ifndef CDX_AMR_PARSER_H +#define CDX_AMR_PARSER_H + +#define SEEK_TABLE_LEN 10 /* i think it's useless when we don't need parser seekto, + but i'm not sure. origin is 300 */ +#define CODEC_ID_AMR_NB 1 +#define CODEC_ID_AMR_WB 2 + +typedef struct AmrParserImplS +{ + //audio common + CdxParserT base; + CdxStreamT *stream; + cdx_int64 ulDuration;//ms + pthread_cond_t cond; + cdx_int64 fileSize;//total file length + cdx_int64 file_offset; //now read location + cdx_int32 mErrno; //Parser Status + cdx_uint32 flags; //cmd + //amr base + cdx_int64 pts; + cdx_int32 head_len; + cdx_int32 framecounts;//samples + cdx_int32 framepcms; + cdx_int32 chans; + cdx_int32 sample_rate; + cdx_int32 is_wide; + cdx_int32 seek_table_len; + cdx_int64 seek_table[SEEK_TABLE_LEN]; + +}AmrParserImplS; + +static const char AMR_header [] = "#!AMR\n"; +static const char AMRWB_header [] = "#!AMR-WB\n"; + +static const cdx_uint8 block_size_NB[16] = { 12, 13, 15, 17, 19, 20, 26, + 31, 5, 0, 0, 0, 0, 0, 0, 0 }; +static const cdx_uint8 block_size_WB[16] = {18, 24, 33, 37, 41, 47, 51, + 59, 61, 6, 6, 0, 0, 0, 1, 1}; + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/base/id3base/BaseUtils.h b/platform/mcu/xr871/src/cedarx/parser/base/id3base/BaseUtils.h new file mode 100644 index 0000000000..1fbabc0e94 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/base/id3base/BaseUtils.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2008-2017 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : BaseUtils.h +* Description : +* History : +* Author : Khan +* Date : 2017/3/2 +*/ + +#ifndef BASEUTILS_H +#define BASEUTILS_H + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum _kbool +{ + kfalse = 0, + ktrue +}kbool; + +typedef enum _kerrno +{ + KERR_NONE = 0, + KERR_NULL_PTR = -1000, + KERR_INVAILD_DATA, + KERR_OUT_OF_RANGE, + KERR_NO_DATA, + KERR_NO_MEM, + KERR_RESERVED, +}kerrno; + +static __inline cdx_uint16 U16_AT(const cdx_uint8 *ptr) { + return ptr[0] << 8 | ptr[1]; +} + +static __inline cdx_uint32 U32_AT(const cdx_uint8 *ptr) { + return ptr[0] << 24 | ptr[1] << 16 | ptr[2] << 8 | ptr[3]; +} + +static __inline cdx_uint64 U64_AT(const cdx_uint8 *ptr) { + return ((cdx_uint64)U32_AT(ptr)) << 32 | U32_AT(ptr + 4); +} + +static __inline cdx_uint16 bswap16(cdx_uint16 x) +{ + x= (x>>8) | (x<<8); + return x; +} + + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/base/id3base/CdxMetaData.h b/platform/mcu/xr871/src/cedarx/parser/base/id3base/CdxMetaData.h new file mode 100644 index 0000000000..d7ac9a58fd --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/base/id3base/CdxMetaData.h @@ -0,0 +1,70 @@ +/* +* Copyright (c) 2008-2017 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : CdxMetaData.h +* Description : +* History : +* Author : Khan +* Date : 2017/3/7 +*/ +#include "BaseUtils.h" + +#ifndef CDXMETADATA_H +#define CDXMETADATA_H + +#define META_MKTAG(a,b,c,d) ((a) | ((b) << 8) | ((c) << 16) | ((unsigned)(d) << 24)) +#define META_MKBETAG(a,b,c,d) ((d) | ((c) << 8) | ((b) << 16) | ((unsigned)(a) << 24)) + +typedef struct _Map Map; + +enum _META_TITLE_KINDS +{ + ARTIST = 0, + ALBUM, + ALBUM_ARTIST, + TITLE, + COMPOSER, + GENRE, + YEAR, + AUTHOR, + CDTRACKNUMBER, + DISCNUMBER, + COMPILATION, + DATE, +}; + +enum _key_string +{ + CdxMetaKeyAlbum = META_MKBETAG('a','l','b','u'), // cstring + CdxMetaKeyArtist = META_MKBETAG('a','r','t','i'), // cstring + CdxMetaKeyAlbumArtist = META_MKBETAG('a','a','r','t'), // cstring + CdxMetaKeyComposer = META_MKBETAG('c','o','m','p'), // cstring + CdxMetaKeyGenre = META_MKBETAG('g','e','n','r'), // cstring + CdxMetaKeyTitle = META_MKBETAG('t','i','t','l'), // cstring + CdxMetaKeyYear = META_MKBETAG('y','e','a','r'), // cstring + CdxMetaKeyAlbumArt = META_MKBETAG('a','l','b','A'), // compressed image data + CdxMetaKeyAlbumArtMIME = META_MKBETAG('a','l','A','M'), // cstring + CdxMetaKeyAuthor = META_MKBETAG('a','u','t','h'), // cstring + CdxMetaKeyCDTrackNumber = META_MKBETAG('c','d','t','r'), // cstring + CdxMetaKeyDiscNumber = META_MKBETAG('d','n','u','m'), // cstring + CdxMetaKeyDate = META_MKBETAG('d','a','t','e'), // cstring + CdxMetaKeyWriter = META_MKBETAG('w','r','i','t'), // cstring + CdxMetaKeyCompilation = META_MKBETAG('c','p','i','l'), // cstring + CdxMetaKeyLocation = META_MKBETAG('l','o','c',' '), // cstring + CdxMetaKeyTimeScale = META_MKBETAG('t','m','s','l'), // cdx_int32 +}; + +typedef enum _META_TITLE_KINDS META_IDX; +typedef enum _key_string CdxMetaKeyString; + +struct _Map{ + META_IDX idx; + CdxMetaKeyString key; + const char *tag1; + const char *tag2; +}; + +void SetMetaData(CdxMediaInfoT *mediaInfo, META_IDX idx, const char* content); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/base/id3base/CdxUtfCode.h b/platform/mcu/xr871/src/cedarx/parser/base/id3base/CdxUtfCode.h new file mode 100644 index 0000000000..bfbeccf7ea --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/base/id3base/CdxUtfCode.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2008-2017 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxUtfCode.h + * Description : Parse Utf Code head file + * History : + * + */ + +#ifndef UTF_CODE_H +#define UTF_CODE_H + +#include +#include +#include +#include +#include "BaseUtils.h" + +void CdxUtf16toUtf8(const cdx_uint16* src, size_t src_len, char* dst); +void CdxUtf32toUtf8(const cdx_uint32* src, size_t src_len, char* dst); + +int32_t CdxUtf16toUtf8Length(const cdx_uint16 *src, size_t src_len); +int32_t CdxUtf32toUtf8Length(const cdx_uint32 *src, size_t src_len); + +char* CdxAllocFromUTF8(const char* in, size_t len); +char* CdxAllocFromUTF16(const cdx_uint16* in, size_t len); +char* CdxAllocFromUTF32(const cdx_uint32* in, size_t len); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/base/id3base/Id3Base.h b/platform/mcu/xr871/src/cedarx/parser/base/id3base/Id3Base.h new file mode 100644 index 0000000000..77ff99412a --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/base/id3base/Id3Base.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2008-2017 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : Id3Base.h + * Description : Id3_v1 and Id3_v2 parser head file + * History : + * + */ + +#ifndef ID3_H +#define ID3_H + +#include +#include +#include +#include +#include "StringContainer.h" +#include "CdxMetaData.h" + +#define IS_VERSION_2(v) ((v >= ID3_V2_2) && (v <= ID3_V2_4)) +#define IS_VERSION_1(v) ((v >= ID3_V1) && (v <= ID3_V1_1)) + +#define V1_TAG_SIZE 128 + +typedef struct _ID3 ID3; +typedef struct _Iterator Iterator; +typedef struct _id3_header id3_header; + +struct _Iterator { + ID3 *mParent;//get from parent, parent to free + char *mID; + size_t mOffset; + const cdx_uint8 *mFrameData;//get from parent, parent to free + size_t mFrameSize; + int encoding; + + kbool (*done)(void* hself); + kerrno (*getID)(void* hself, StringCtn *id); + kerrno (*getString)(void* hself, StringCtn *s, StringCtn *ss/*NULL*/); + kerrno (*getStringInternal)(void* hself, StringCtn *s, kbool secondhalf); + const cdx_uint8* (*getData)(void* hself, size_t *length); + kerrno (*next)(void* hself); + kerrno (*findFrame)(void* hself); + size_t (*getHeaderLength)(void* hself); +}; + +enum _Version { + ID3_UNKNOWN, + ID3_V1, + ID3_V1_1, + ID3_V2_2, + ID3_V2_3, + ID3_V2_4, +}; + +typedef enum _Version Version; + +struct _id3_header { + char id[3]; + cdx_uint8 version_major; + cdx_uint8 version_minor; + cdx_uint8 flags; + cdx_uint8 enc_size[4]; +}; + +struct _ID3 { + kbool mIsValid; + cdx_uint8 *mData; + size_t mSize; + size_t mFirstFrameOffset; + Version mVersion; + + // size of the ID3 tag including header before any unsynchronization. + // only valid for IDV2+ + size_t mRawSize; + + kbool (*isValid)(void* hself); + Version (*version)(void* hself); + void * (*getAlbumArt)(void* hself, size_t *length, StringCtn *mime); + size_t (*rawSize)(void* hself); + kbool (*doParseV1)(void* hself); + kbool (*doParseV2)(void* hself); + kerrno (*doRemoveUnsynchronization)(void* hself); + kbool (*doRemoveUnsynchronizationV2_4)(void* hself, kbool iTunesHack); + + CdxStreamT* stream; + cdx_uint8* extraBuf; + size_t extraBufRange; + size_t extraBufOffset; + size_t extraBufValidSz; + size_t (*read)(void* hself, void* buf, size_t sz); + size_t (*readAt)(void* hself, int64_t offset, void* buf, size_t sz); + kbool (*getsize)(void* hself, int64_t* sz); + int64_t (*tell)(void* hself); +}; + +Iterator* GenerateIterator(ID3* parent, const char *id); +kbool EraseIterator(void* arg); +ID3* GenerateId3(CdxStreamT* in, cdx_uint8* init_buf, size_t buf_sz, + kbool ignoreV1); +kbool EraseId3(void* arg); + +void Id3BaseGetMetaData(CdxMediaInfoT *mediaInfo, ID3* id3Base); + +void Id3BaseExtraAlbumPic(CdxMediaInfoT *mediaInfo, ID3* id3Base); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/base/id3base/StringContainer.h b/platform/mcu/xr871/src/cedarx/parser/base/id3base/StringContainer.h new file mode 100644 index 0000000000..b69c332a96 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/base/id3base/StringContainer.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2008-2017 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : StringContainer.h +* Description : +* History : +* Author : Khan +* Date : 2017/3/2 +*/ + +#ifndef STRINGCONTAINER_H +#define STRINGCONTAINER_H + +#include +#include +#include +#include +#include "BaseUtils.h" + +typedef struct _StringCtn StringCtn; +struct _StringCtn +{ + char* mString; + kbool (*setTo8)(void* hself, const char*, size_t); + kbool (*setTo16)(void* hself, const cdx_uint16*, size_t); + void (*clear)(void* hself); + const char* (*string)(void* hself); +}; + +StringCtn* GenerateStringContainer(void); +kbool EraseStringContainer(void*); +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/id3v2/CdxId3v2Parser.h b/platform/mcu/xr871/src/cedarx/parser/id3v2/CdxId3v2Parser.h new file mode 100644 index 0000000000..e75d7d364f --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/id3v2/CdxId3v2Parser.h @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : CdxId3Parser.h +* Description : +* History : +* Author : Khan +* Date : 2014/12/08 +*/ + +#ifndef CDX_ID3_PARSER_H +#define CDX_ID3_PARSER_H + +#define INFLEN 1024*8//less than 8k +#define ID3TAGNUM 8 +#define SKIPLEN 1024 +#define ID3v2_HEADER_SIZE 10 + +#include "Id3Base.h" + +typedef struct __language_coding +{ + char language[4]; + cdx_int32 coding; +} language_coding_t; + +typedef enum { + IMG_FORMAT_BMP =0, + IMG_FORMAT_JPG, + IMG_FORMAT_GIF, + IMG_FORMAT_PNG, + IMG_FORMAT_UNSUPPORT = -1 +}img_format_t; + +typedef struct CDX_ID3_IMAGE_INFO +{ + int length; //image length + int FileLocation; //image location + img_format_t img_format; + int pic_type; //picture type; + int img_high; + int img_width; + int otherdata; + +}cdx_id3_image_info_t; + +typedef enum CDX_A_AUDIO_FONTTYPE +{ + A_AUDIO_FONTTYPE_ISOIEC8859_1 = 0, //ISO/IEC 8859-1 + A_AUDIO_FONTTYPE_UTF_16LE,// + A_AUDIO_FONTTYPE_UTF_16BE, + A_AUDIO_FONTTYPE_UTF_8,// + A_AUDIO_FONTTYPE_ISOIEC8859_2,// + A_AUDIO_FONTTYPE_ISOIEC8859_3,// + A_AUDIO_FONTTYPE_ISOIEC8859_4,// + A_AUDIO_FONTTYPE_ISOIEC8859_5,// + A_AUDIO_FONTTYPE_ISOIEC8859_6, + A_AUDIO_FONTTYPE_ISOIEC8859_7, + A_AUDIO_FONTTYPE_ISOIEC8859_8, + A_AUDIO_FONTTYPE_ISOIEC8859_9, + A_AUDIO_FONTTYPE_ISOIEC8859_10, + A_AUDIO_FONTTYPE_ISOIEC8859_11, + A_AUDIO_FONTTYPE_ISOIEC8859_12, + A_AUDIO_FONTTYPE_ISOIEC8859_13, + A_AUDIO_FONTTYPE_ISOIEC8859_14, + A_AUDIO_FONTTYPE_ISOIEC8859_15, + A_AUDIO_FONTTYPE_ISOIEC8859_16, + A_AUDIO_FONTTYPE_WINDOWS_1250, + A_AUDIO_FONTTYPE_WINDOWS_1251,// + A_AUDIO_FONTTYPE_WINDOWS_1252, + A_AUDIO_FONTTYPE_WINDOWS_1253, + A_AUDIO_FONTTYPE_WINDOWS_1254, + A_AUDIO_FONTTYPE_WINDOWS_1255, + A_AUDIO_FONTTYPE_WINDOWS_1256, + A_AUDIO_FONTTYPE_WINDOWS_1257, + A_AUDIO_FONTTYPE_WINDOWS_1258, + A_AUDIO_FONTTYPE_KOI8_R, + A_AUDIO_FONTTYPE_KOI8_U, + A_AUDIO_FONTTYPE_GB2312, + A_AUDIO_FONTTYPE_GBK, + A_AUDIO_FONTTYPE_BIG5, + A_AUDIO_FONTTYPE_ = -1 +}cdx_audio_fonttype_e; + +struct Id3Pic +{ + cdx_uint8* addr; + cdx_int32 lenth; + struct Id3Pic* father; +}; + +typedef struct Id3v2ParserImplS +{ + //audio common + CdxParserT base; + CdxStreamT *stream; + cdx_int32 mErrno; //Parser Status + cdx_uint32 flags; //cmd + cdx_int32 forceStop; + //id3 base + CdxParserT *child;/*Ϊparserһýļparsermp3 parser*/ + cdx_int32 shareStreamWithChild; + cdx_char * keyinfo; +// cdx_char newurl[128]; + cdx_int64 fdoffset; + cdx_int64 file_size; + CdxDataSourceT cdxDataSource; + cdx_int32 Id3v2len; + cdx_int64 file_offset; + CdxStreamT *childStream; + pthread_mutex_t lock; + +#if 0 + /*ID3*/ + cdx_int32 mGenre_sz; // + char *mGenre; // pop soft... + cdx_audio_fonttype_e mGenreCharEncode; + + cdx_int32 mtitle_sz; // + char *mtitle; + cdx_audio_fonttype_e mtitleCharEncode; + + cdx_int32 mauthor_sz; // ݳ + char *mauthor; + cdx_audio_fonttype_e mauthorCharEncode; + + cdx_int32 mAlbum_sz; // ר + char *mAlbum; + cdx_audio_fonttype_e mAlbumCharEncode; + + cdx_int32 mYear_sz; // Ʒ + char *mYear; + cdx_audio_fonttype_e mYearCharEncode; + + cdx_int32 mAPic_sz; // attached picture + cdx_id3_image_info_t *mAPic; + cdx_audio_fonttype_e mAPicCharEncode; + + cdx_int32 mInforBufLeftLength; + cdx_uint8 *mInforBuf; + cdx_uint8 mInfor[INFLEN]; + struct Id3Pic *pAlbumArt; + cdx_int32 pAlbumArtid; +#endif + + ID3* id3v2; +}Id3v2ParserImplS; + +#endif diff --git a/platform/mcu/xr871/src/cedarx/parser/include/CdxParser.h b/platform/mcu/xr871/src/cedarx/parser/include/CdxParser.h new file mode 100644 index 0000000000..26f62a01c0 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/include/CdxParser.h @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxParser.h + * Description : Parser + * History : + * + */ + +#ifndef CDX_PARSER_H +#define CDX_PARSER_H + +#include +#include +#include +#include +#include +#include +//#include +#include +//#include +#include + +#ifdef __ANDROID__ +#include +#endif + +enum CdxParserTypeE +{ + CDX_PARSER_UNKNOW = -1, + CDX_PARSER_MOV, + CDX_PARSER_MKV, + CDX_PARSER_ASF, + CDX_PARSER_TS, + CDX_PARSER_AVI, + CDX_PARSER_FLV, + CDX_PARSER_PMP, + + CDX_PARSER_HLS, + CDX_PARSER_DASH, + CDX_PARSER_MMS, + CDX_PARSER_BD, + CDX_PARSER_OGG, + CDX_PARSER_M3U9, + CDX_PARSER_RMVB, + CDX_PARSER_PLAYLIST, + CDX_PARSER_APE, + CDX_PARSER_FLAC, + CDX_PARSER_AMR, + CDX_PARSER_ATRAC, + CDX_PARSER_MP3, + CDX_PARSER_DTS, + CDX_PARSER_AC3, + CDX_PARSER_AAC, + CDX_PARSER_WAV, + CDX_PARSER_REMUX, /* rtsp, etc... */ + CDX_PARSER_WVM, + CDX_PARSER_MPG, + CDX_PARSER_MMSHTTP, + CDX_PARSER_AWTS, + CDX_PARSER_SSTR, + CDX_PARSER_CAF, + CDX_PARSER_G729, + CDX_PARSER_DSD, + CDX_PARSER_AIFF, + CDX_PARSER_ID3V2, + CDX_PARSER_ENV, + CDX_PARSER_SSTR_PLAYREADY, + CDX_PARSER_AWRAWSTREAM, + CDX_PARSER_AWSPECIALSTREAM, +}; + +typedef struct CdxPacketS CdxPacketT; +typedef struct CdxMediaInfoS CdxMediaInfoT; +typedef enum CdxParserTypeE CdxParserTypeT; +typedef struct CdxParserCreatorS CdxParserCreatorT; +typedef struct CdxParserS CdxParserT; +//typedef struct ParserMetaDataS ParserMetaDataT; + +#define MINOR_STREAM 0x0001 /*0 major stream, 1 minor stream*/ +#define FIRST_PART 0x0002 +#define LAST_PART 0x0004 +#define KEY_FRAME 0x0008 + +struct CdxPacketS +{ + void *buf; + void *ringBuf; + cdx_int32 buflen; + cdx_int32 ringBufLen; + int64_t pts; + cdx_int64 duration; + cdx_int32 type; + cdx_int32 length; + cdx_uint32 flags; /* MINOR_STREAM, FIRST_PART, LAST_PART, etc... */ + cdx_int32 streamIndex; + cdx_int64 pcr; + cdx_int32 infoVersion; + void *info;//VideoInfo/AudioInfo/SubtitleInfo +}; + +//#define PARSER_METADATA_ORGINAL_URI "parser.orginalUri" +//#define PARSER_METADATA_REDIRECT_URI "parser.redirectUri" +//#define PARSER_METADATA_ACCESSIBLE_URI "parser.accessibleUri" + +struct ParserCacheStateS +{ + cdx_int32 nCacheCapacity; + cdx_int32 nCacheSize; + cdx_int32 nBandwidthKbps; + cdx_int32 nPercentage; /* current_caching_positioin / duration */ +}; + +struct StreamSeekPos +{ + cdx_int64 pos; + cdx_int64 time; + cdx_int64 startTime; +}; + +enum EPARSERNOTIFY //* notify. +{ + PARSER_NOTIFY_VIDEO_STREAM_CHANGE = PARSER_NOTIFY_VALID_RANGE_MIN, + PARSER_NOTIFY_AUDIO_STREAM_CHANGE, + PARSER_NOTIFY_TIMESHIFT_END_INFO, + PARSER_NOTIFY_META_DATA, + PARSER_NOTIFY_MAX, +}; +CHECK_PARSER_NOTIFY_MAX_VALID(PARSER_NOTIFY_MAX) + +enum CdxParserCommandE +{ + CDX_PSR_CMD_SWITCH_AUDIO, + CDX_PSR_CMD_SWITCH_SUBTITLE, + + CDX_PSR_CMD_DISABLE_AUDIO, + CDX_PSR_CMD_DISABLE_VIDEO, + CDX_PSR_CMD_DISABLE_SUBTITLE, + + CDX_PSR_CMD_SET_DURATION, + CDX_PSR_CMD_REPLACE_STREAM, + CDX_PSR_CMD_SET_LASTSEGMENT_FLAG, + CDX_PSR_CMD_CLR_INFO, + + CDX_PSR_CMD_STREAM_SEEK, + CDX_PSR_CMD_GET_CACHESTATE, + + CDX_PSR_CMD_SET_FORCESTOP, + CDX_PSR_CMD_CLR_FORCESTOP, + CDX_PSR_CMD_UPDATE_PARSER, + CDX_PSR_CMD_SET_HDCP, + CDX_PSR_CMD_SET_SECURE_BUFFER_COUNT, + CDX_PSR_CMD_SET_SECURE_BUFFERS, + CDX_PSR_CMD_GET_STREAM_EXTRADATA, + +#if LIVEMODE_VIDEO + // get the shiftTimeUrl for cmcc livemode1&2 seekTo + CDX_PSR_CMD_GET_REDIRECT_URL, +#endif + + // for cmcc get the stream url in LogRecorder + CDX_PSR_CMD_GET_URL, + // get the statusCode of http + CDX_PSR_CMD_GET_STREAM_STATUSCODE, + // for Ali YUNOS get TS info + CDX_PSR_CMD_GET_TS_M3U_BANDWIDTH, + CDX_PSR_CMD_GET_TS_SEQ_NUM, + CDX_PSR_CMD_GET_TS_LENGTH, + CDX_PSR_CMD_GET_TS_DURATION, + CDX_PSR_CMD_SET_YUNOS_UUID, + + // for cmcc timeShift set lastSeqNum + CDX_PSR_CMD_SET_TIMESHIFT_LAST_SEQNUM, + + // parser and stream use the same setCallback cmd, + // the code below must be the end of this structure + CDX_PSR_CMD_SET_CALLBACK = STREAM_CMD_SET_CALLBACK, +}; + +enum CdxParserStatusE +{ + PSR_OK, + PSR_INVALID, + PSR_OPEN_FAIL, + PSR_IO_ERR, + PSR_USER_CANCEL, + PSR_INVALID_OPERATION, + PSR_UNKNOWN_ERR, + PSR_EOS, + /*other error info*/ +}; + +#define AUDIO_STREAM_LIMIT 1 +#define VIDEO_STREAM_LIMIT 1 +#define SUBTITLE_STREAM_LIMIT 32 + +#if VIDEO_SUPPORT +struct VideoInfo +{ + cdx_atomic_t ref; + cdx_int32 videoNum; + VideoStreamInfo video[VIDEO_STREAM_LIMIT]; +}; +#endif + +struct AudioInfo +{ + cdx_atomic_t ref; + cdx_int32 audioNum; + AudioStreamInfo audio[AUDIO_STREAM_LIMIT]; +}; + +#if SUBTITLE_SUPPORT +struct SubtitleInfo +{ + cdx_atomic_t ref; + cdx_int32 subtitleNum; + SubtitleStreamInfo subtitle[SUBTITLE_STREAM_LIMIT]; +}; +#endif + +struct CdxProgramS +{ + cdx_int32 id; + cdx_uint32 flags; + cdx_uint32 duration; //unit: ms + + cdx_int32 audioNum, audioIndex; + AudioStreamInfo audio[AUDIO_STREAM_LIMIT]; + cdx_uint64 audioIndexMask; + +#if VIDEO_SUPPORT + cdx_int32 videoNum, videoIndex; + VideoStreamInfo video[VIDEO_STREAM_LIMIT]; + cdx_uint64 videoIndexMask; +#endif + +#if SUBTITLE_SUPPORT + cdx_int32 subtitleNum, subtitleIndex; + SubtitleStreamInfo subtitle[SUBTITLE_STREAM_LIMIT]; +#endif + + cdx_int64 firstPts; + cdx_int32 metadataNum; +}; + +#define PROGRAM_LIMIT 1 //no switch program interface now, so limit 1 + +struct CdxMediaInfoS +{ + cdx_int64 fileSize; + cdx_uint32 bitrate; + cdx_bool bSeekable; + cdx_int32 programNum, programIndex; + + struct CdxProgramS program[PROGRAM_LIMIT]; + + void *privData; + +/* cdx_uint8 album[64]; + cdx_int32 albumsz; + + cdx_uint8 author[64]; + cdx_int32 authorsz; + + cdx_uint8 genre[64]; + cdx_int32 genresz; + + cdx_uint8 title[64]; + cdx_int32 titlesz; + + cdx_uint8 year[64]; + cdx_int32 yearsz; + + cdx_uint8 composer[64]; + cdx_int32 composersz; + + cdx_uint8 date[64]; + cdx_int32 datesz; + + cdx_uint8 artist[64]; + cdx_int32 artistsz; + + cdx_uint8 writer[64]; + cdx_int32 writersz; + + cdx_uint8 albumArtist[64]; + cdx_int32 albumArtistsz; + + cdx_uint8 compilation[64]; + cdx_int32 compilationsz; + + cdx_uint8 cdTrackNumber[64]; + cdx_int32 cdTrackNumbersz;*/ + + cdx_uint8 location[64]; + cdx_uint8 rotate[4]; + cdx_int32 discNumber; + cdx_uint8 *pAlbumArtBuf; + cdx_int32 nAlbumArtBufSize; + + int id3v2HadParsed; +}; + +#define MUTIL_AUDIO 0x0001U /*will disable switch audio*/ +//#define MUTIL_VIDEO 0x0002U /*will disable switch video*/ +#define MUTIL_SUBTITLE 0x0004U /*will disable switch subtitle*/ + +#define DISABLE_AUDIO 0x0008U +#define DISABLE_VIDEO 0x0010U +#define DISABLE_SUBTITLE 0x0020U +#define NO_NEED_DURATION 0x0040U + +#define BD_BASE 0x0080U +#define BD_DEPENDENT 0x0100U +#define BD_TXET 0x0180U + +// for DASH +#define SEGMENT_MP4 0x0200U + +// for mms playlist +#define NO_NEED_CLOSE_STREAM 0x0400U +// for miracast +#define MIRACST 0x0800U + +// for smooth streaming +#define SEGMENT_SMS 0x1000U + +// for cmcc timeShift +#define CMCC_TIME_SHIFT 0x2000U + +#define NOT_LASTSEGMENT 0x4000U + +// for playready sstr +#define SEGMENT_PLAYREADY 0x8000U + +#define MutilAudioStream(flags) (!!(flags & MUTIL_AUDIO)) + +typedef struct HdcpOpsS HdcpOps; +struct HdcpOpsS +{ + int (*init)(void **); + void (*deinit)(void *); + cdx_uint32 (*decrypt)(void *handle, const cdx_uint8 privateData[16], + const cdx_uint8 *in, cdx_uint8 *out, cdx_uint32 len, int streamType); +}; +typedef struct DownloadObjectS DownloadObject; +struct DownloadObjectS +{ + int seqNum; + char *uri; + int statusCode; //http statusCode + cdx_int64 seqSize; //segment size, byte + cdx_int64 seqDuration;//segment duration, us + cdx_int64 spendTime; //ms + cdx_int64 rate; //bps +}; + +typedef struct TimeShiftEndInfoS TimeShiftEndInfoT; +struct TimeShiftEndInfoS +{ + int timeShiftLastSeqNum; + cdx_int64 timeShiftDuration; +}; + +struct CdxParserCreatorS +{ + CdxParserT *(*create)(CdxStreamT *, cdx_uint32 /*flags*/); + cdx_uint32 (*probe)(CdxStreamProbeDataT *);/*return score(0-100)*/ +}; + +struct CdxParserOpsS +{ + cdx_int32 (*control)(CdxParserT *, cdx_int32 /* cmd */, void * /* param */); + + cdx_int32 (*prefetch)(CdxParserT *, CdxPacketT * /* pkt */); + + cdx_int32 (*read)(CdxParserT *, CdxPacketT * /* pkt */); + + cdx_int32 (*getMediaInfo)(CdxParserT *, CdxMediaInfoT * /* MediaInfo */); + + cdx_int32 (*seekTo)(CdxParserT *, cdx_int64 /* timeUs */); + + cdx_uint32 (*attribute)(CdxParserT *); /*return falgs define as open's falgs*/ + + cdx_int32 (*getStatus)(CdxParserT *); /*return enum CdxPrserStatusE*/ + + cdx_int32 (*close)(CdxParserT *); + + cdx_int32 (*init)(CdxParserT *); +}; + +struct CdxParserS +{ + enum CdxParserTypeE type; + struct CdxParserOpsS *ops; +}; + +struct ParserUriKeyInfoS +{ + const char *comment; + const char *scheme[10]; + const char *suffix[10]; + const char *attr[10]; +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +int AwParserRegister(CdxParserCreatorT *creator, CdxParserTypeT type, + struct ParserUriKeyInfoS *keyInfo); + +int CdxParserPrepare(CdxDataSourceT *source, cdx_uint32 flags, pthread_mutex_t *mutex, + cdx_bool *exit, CdxParserT **parser, CdxStreamT **stream, + ContorlTask *parserTasks, ContorlTask *streamTasks); +CdxParserT *CdxParserCreate(CdxStreamT *, cdx_uint32 /*flags*/); +int CdxParserOpen(CdxStreamT *stream, cdx_uint32 flags, pthread_mutex_t *mutex, cdx_bool *exit, + CdxParserT **parser, ContorlTask *parserTasks); +#define CdxParserForceStop(parser) \ + (CdxParserControl(parser, CDX_PSR_CMD_SET_FORCESTOP, NULL)) + +#define CdxParserClrForceStop(parser) \ + (CdxParserControl(parser, CDX_PSR_CMD_CLR_FORCESTOP, NULL)) + +static inline cdx_int32 CdxParserControl(CdxParserT *parser, cdx_int32 cmd, void *param) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->control); + return parser->ops->control(parser, cmd, param); +} + +static inline cdx_int32 CdxParserPrefetch(CdxParserT *parser, CdxPacketT *pkt) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->prefetch); + return parser->ops->prefetch(parser, pkt); +} + +static inline cdx_int32 CdxParserRead(CdxParserT *parser, CdxPacketT *pkt) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->read); + return parser->ops->read(parser, pkt); +} + +static void PrintMediaInfo(CdxMediaInfoT *mediaInfo) +{ + CDX_LOGD("*********PrintMediaInfo begin*********"); + struct CdxProgramS *program = &mediaInfo->program[0]; + + CDX_LOGD("fileSize = %lld, " + "bSeekable = %d, " + "duration = %d, " + "audioNum = %d, " +#if VIDEO_SUPPORT + "videoNum = %d, " +#endif +#if SUBTITLE_SUPPORT + "subtitleNum = %d " +#endif + , + mediaInfo->fileSize, + mediaInfo->bSeekable, + program->duration, + program->audioNum +#if VIDEO_SUPPORT + ,program->videoNum +#endif +#if SUBTITLE_SUPPORT + ,program->subtitleNum +#endif + ); + + int i; +#if VIDEO_SUPPORT + for (i = 0; i < VIDEO_STREAM_LIMIT && i < program->videoNum; i++) + { + VideoStreamInfo *video = program->video + i; + CDX_LOGD("***Video[%d]*** " + "eCodecFormat = 0x%x, " + "nWidth = %d, " + "nHeight = %d, " + "nFrameRate = %d, " + "nFrameDuration = %d, " + "bIs3DStream = %d ", + i, + video->eCodecFormat, + video->nWidth, + video->nHeight, + video->nFrameRate, + video->nFrameDuration, + video->bIs3DStream); + + } +#endif + + for (i = 0; i < AUDIO_STREAM_LIMIT && i < program->audioNum; i++) + { + AudioStreamInfo *audio = program->audio + i; + CDX_UNUSE(audio); + CDX_LOGD("***Audio[%d]*** " + "eCodecFormat = 0x%x, " + "eSubCodecFormat = 0x%x, " + "nChannelNum = %d, " + "nBitsPerSample = %d, " + "nSampleRate = %d ", + i, + audio->eCodecFormat, + audio->eSubCodecFormat, + audio->nChannelNum, + audio->nBitsPerSample, + audio->nSampleRate); + + } + +#if SUBTITLE_SUPPORT + for (i = 0; i < SUBTITLE_STREAM_LIMIT && i < program->subtitleNum; i++) + { + SubtitleStreamInfo *subtitle = program->subtitle + i; + + CDX_LOGD("***Subtitle[%d]*** " + "eCodecFormat = 0x%x, " + "strLang = (%s) ", + i, + subtitle->eCodecFormat, + subtitle->strLang); + } +#endif + + CDX_LOGD("*********PrintMediaInfo end*********"); +} + +#ifdef __ANDROID__ +#define ACODEC "ro.codec.audio." +#define VCODEC "ro.codec.video." +static int AudioCodecIsForbidden(int eCodecFormat) +{ + char value[PROP_VALUE_MAX] = {0}; + switch (eCodecFormat) + { + case AUDIO_CODEC_FORMAT_AC3: + case AUDIO_CODEC_FORMAT_DTS: + property_get(ACODEC "dts", value, "0"); + if (!strcmp(value, "off")) + return 1; + break; + case AUDIO_CODEC_FORMAT_COOK: + property_get(ACODEC "cook", value, "0"); + if (!strcmp(value, "off")) + return 1; + break; + case AUDIO_CODEC_FORMAT_WMA_STANDARD: + case AUDIO_CODEC_FORMAT_WMA_LOSS: + case AUDIO_CODEC_FORMAT_WMA_PRO: + property_get(ACODEC "wma", value, "0"); + if (!strcmp(value, "off")) + return 1; + break; + default: + break; + } + + return 0; +} + +#if VIDEO_SUPPORT +static int VideoCodecIsForbidden(int eCodecFormat) +{ + char value[PROP_VALUE_MAX] = {0}; + switch (eCodecFormat) + { + case VIDEO_CODEC_FORMAT_DIVX5: + property_get(VCODEC "divx5", value, "0"); + if (!strcmp(value, "off")) + return 1; + break; + case VIDEO_CODEC_FORMAT_RX: + property_get(VCODEC "rx", value, "0"); + if (!strcmp(value, "off")) + return 1; + break; + case VIDEO_CODEC_FORMAT_WMV3: + property_get(VCODEC "vc-1", value, "0"); + if (!strcmp(value, "off")) + return 1; + break; + default: + break; + } + + return 0; +} +#endif + +static int FilterForbiddenStream(CdxMediaInfoT *mediaInfo) +{ + struct CdxProgramS *program = &mediaInfo->program[0]; + int i; + + int videoNum = program->videoNum; + program->videoIndexMask = 0; + for (i = 0; i < videoNum && i < VIDEO_STREAM_LIMIT; i++) + { + VideoStreamInfo *video = program->video + i; + if (VideoCodecIsForbidden(video->eCodecFormat)) + { + logw("video codec %d is forbidden", video->eCodecFormat); + program->videoIndexMask |= 1 << i; + } + } + + int audioNum = program->audioNum; + program->audioIndexMask = 0; + for (i = 0; i < audioNum && i < AUDIO_STREAM_LIMIT; i++) + { + AudioStreamInfo *audio = program->audio + i; + if (AudioCodecIsForbidden(audio->eCodecFormat)) + { + logw("audio codec %d is forbidden", audio->eCodecFormat); + /* Todo: forbidden the evil one, not anyone */ + program->audioIndexMask |= 1 << i; + } + } + + return 0; +} +#endif + +/** + * Get the information of the media from the parser. + * + * @param parser A parser which is prepared. + * @param mediaInfo A struct hold the information of the media. + * + * @return 0 for success. + * + * @warning Don't allocate memory for member variables like pCodecSpecificData + * of mediaInfo in the parser's implementation of this interface. + * pCodecSpecificData won't be freed after the function return, so the + * memory will lose if you do that. Just set pCodecSpecificData point + * to the area which will be freed by the parser, for example, when + * the parser is closed. + */ +static inline cdx_int32 CdxParserGetMediaInfo(CdxParserT *parser, CdxMediaInfoT *mediaInfo) +{ + int ret; + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->getMediaInfo); + ret = parser->ops->getMediaInfo(parser, mediaInfo); + PrintMediaInfo(mediaInfo); +#ifdef __ANDROID__ + FilterForbiddenStream(mediaInfo); +#endif + return ret; +} + +static inline cdx_int32 CdxParserSeekTo(CdxParserT *parser, cdx_int64 timeUs) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->seekTo); + return parser->ops->seekTo(parser, timeUs); +} + +static inline cdx_uint32 CdxParserAttribute(CdxParserT *parser) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->attribute); + return parser->ops->attribute(parser); +} + +static inline cdx_int32 CdxParserGetStatus(CdxParserT *parser) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->getStatus); + return parser->ops->getStatus(parser); +} + +static inline cdx_int32 CdxParserClose(CdxParserT *parser) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->close); + return parser->ops->close(parser); +} + +static inline cdx_int32 CdxParserInit(CdxParserT *parser) +{ + CDX_CHECK(parser); + CDX_CHECK(parser->ops); + CDX_CHECK(parser->ops->init); + return parser->ops->init(parser); +} +enum { + PROBE_SPECIFIC_DATA_ERROR =-3, + PROBE_SPECIFIC_DATA_NONE =-2, + PROBE_SPECIFIC_DATA_UNCOMPELETE = -1, + PROBE_SPECIFIC_DATA_SUCCESS = 1, +}; + +#if VIDEO_SUPPORT +cdx_int32 ProbeVideoSpecificData(VideoStreamInfo* pVideoInfo, cdx_uint8* pDataBuf, + cdx_uint32 dataLen, cdx_uint32 eVideoCodecFormat, enum CdxParserTypeE type); +cdx_int32 probeH265RefPictureNumber(cdx_uint8* pDataBuf, cdx_uint32 nDataLen); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/parser/mp3/CdxMp3Parser.h b/platform/mcu/xr871/src/cedarx/parser/mp3/CdxMp3Parser.h new file mode 100644 index 0000000000..2f011d0bc7 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/parser/mp3/CdxMp3Parser.h @@ -0,0 +1,179 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : CdxMp3Parser.h +* Description : +* History : +* Author : Khan +* Date : 2014/08/08 +*/ + +#ifndef _CDX_MP3_PARSER_H_ +#define _CDX_MP3_PARSER_H_ + +#include "Id3Base.h" + +#define ENABLE_INFO_DEBUG 1 +#define ENABLE_FILE_DEBUG 0 +#define AV_TIME_BASE 1000000 + +#define MP3_PROBE_SIZE 10 * 1024 +#define MP3_PACKET_SIZE 1024 +#define AVPROBE_SCORE_MAX 100 + +#define ID3v2_HEADER_SIZE 10 +#define MPA_STEREO 0 +#define MPA_JSTEREO 1 +#define MPA_DUAL 2 +#define MPA_MONO 3 + +#define INFLEN 1024*8 +#define ID3TAGNUM 8 +#define SKIPLEN 1024 + +typedef enum mp3_sta_ { + MP3_STA_IDLE, + MP3_STA_SEEKING, + MP3_STA_PREFETCHING, + MP3_STA_READING, + MP3_STA_INITING, +}mp3_sta; + +#define MKTAG(a,b,c,d) ((a) | ((b) << 8) | ((c) << 16) | ((unsigned)(d) << 24)) + +const uint16_t CdxMpaFreqTab[3] = { 44100, 48000, 32000 }; + +const uint16_t CdxMpaBitrateTab[2][3][15] = { + { {0, 32, 64, 96, 128, 160, 192, 224, 256, 288, 320, 352, 384, 416, 448 }, + {0, 32, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384 }, + {0, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320 } }, + { {0, 32, 48, 56, 64, 80, 96, 112, 128, 144, 160, 176, 192, 224, 256}, + {0, 8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 144, 160}, + {0, 8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 144, 160} + } +}; + +#define MPADECODEHEADER \ + int mFrameSize; \ + int errorProtection; \ + int layer; \ + int mSampleRate; \ + int mSampleRateIndex; /* between 0 and 8 */ \ + int mBitRate; \ + int nChannels; \ + int mode; \ + int modeExt; \ + int lsf; + +typedef struct MPADecodeHeader { + MPADECODEHEADER +} MPADecodeHeader; +#if 0 +static int CdxId3v2Match(const cdx_uint8 *buf) +{ + return ('I' == buf[0]) && + ('D' == buf[1]) && + ('3' == buf[2]) && + (0xff != buf[3]) && + (0xff != buf[4]) && + (0 == (buf[6] & 0x80)) && + (0 == (buf[7] & 0x80)) && + (0 == (buf[8] & 0x80)) && + (0 == (buf[9] & 0x80)); +} + +static int CdxId3v2TagLen(const uint8_t * buf) +{ + int len = ((buf[9] & 0x7f) + + ((buf[6] & 0x7f) << 21) + + ((buf[7] & 0x7f) << 14) + + (buf[8] & 0x7f) << 7) + + ID3v2_HEADER_SIZE; + + if (buf[5] & 0x10) + len += ID3v2_HEADER_SIZE; + return len; +} +#endif + +typedef struct __language_coding +{ + char language[4]; + cdx_int32 coding; +}anguage_coding_s; + +typedef enum { + IMG_FORMAT_BMP =0, + IMG_FORMAT_JPG, + IMG_FORMAT_GIF, + IMG_FORMAT_PNG, + IMG_FORMAT_UNSUPPORT = -1 +}img_format_t; + +typedef struct CDX_ID3_IMAGE_INFO +{ + int length; //image length + int FileLocation; //image location + img_format_t img_format; + int pic_type; //picture type; + int img_high; + int img_width; + int otherdata; + +}cdx_id3_image_info_t; + +typedef struct XINGSeeker { + int64_t mFirstFramePos; + int64_t mDurationUs; + int32_t mSizeBytes; + int32_t mEncoderDelay; + int32_t mEncoderPadding; + + // TOC entries in XING header. Skip the first one since it's always 0. + unsigned char mTOC[99]; + cdx_bool mTOCValid; +}XINGSeeker; + +typedef struct VBRISeeker { + int64_t mBasePos; + int64_t mDurationUs; + cdx_uint32 mSegmentsize; + cdx_uint32 mSegments[1024]; +}VBRISeeker; + +typedef struct MP3ParserImpl{ + // Cdx Struct + CdxParserT base; + CdxStreamT *stream; + + int mStatus; + int mErrno; // errno + int exitFlag; + + pthread_cond_t cond; + + XINGSeeker *mXINGSeeker; + VBRISeeker *mVBRISeeker; + + cdx_int64 mFileSize; + cdx_uint64 mFirstFramePos; + cdx_uint32 mFixedHeader; + int64_t mCurrentPos; + cdx_uint16 mChannels; + cdx_uint32 mSampleRate; + cdx_int32 mBitRate; + cdx_int32 mavgBitRate; + cdx_uint32 mFrameSize; + cdx_int32 readPacketSize; + /*Duration*/ + cdx_uint64 mDuration; + + cdx_uint32 mSeeking; + cdx_int64 mSeekingTime; + int teeFd; + + ID3* id3v1; +} MP3ParserImpl; + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/audioDecComponent.h b/platform/mcu/xr871/src/cedarx/playback/audioDecComponent.h new file mode 100644 index 0000000000..d31342b030 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/audioDecComponent.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : audioDecComponent.h + * Description : audio decoder component + * History : + * + */ + +#ifndef AUDIO_DECODE_COMPONENT +#define AUDIO_DECODE_COMPONENT + +#include "player_i.h" +#include "avtimer.h" +#include "adecoder.h" + +typedef struct AUDIOSTREAMDATAINFO +{ + char* pData; + int nLength; + int64_t nPts; + int64_t nPcr; + int bIsFirstPart; + int bIsLastPart; +}AudioStreamDataInfo; + +typedef struct AudioDecComp AudioDecComp; + +AudioDecComp* AudioDecCompCreate(void); + +int AudioDecCompDestroy(AudioDecComp* a); + +int AudioDecCompStart(AudioDecComp* a); + +int AudioDecCompStop(AudioDecComp* a); + +int AudioDecCompPause(AudioDecComp* a); + +enum EPLAYERSTATUS AudioDecCompGetStatus(AudioDecComp* a); + +int AudioDecCompReset(AudioDecComp* a, int64_t nSeekTime); + +int AudioDecCompSetEOS(AudioDecComp* a); + +int AudioDecCompSetCallback(AudioDecComp* a, PlayerCallback callback, void* pUserData); + +int AudioDecCompSetAudioStreamInfo(AudioDecComp* a, + AudioStreamInfo* pStreamInfo, + int nStreamCount, + int nDefaultStreamIndex); + +int AudioDecCompAddAudioStream(AudioDecComp* a, AudioStreamInfo* pStreamInfo); + +int AudioDecCompGetAudioStreamCnt(AudioDecComp* a); + +int AudioDecCompCurrentStreamIndex(AudioDecComp* a); + +int AudioDecCompGetAudioStreamInfo(AudioDecComp* a, int* pStreamNum, + AudioStreamInfo** ppStreamInfo); + +int AudioDecCompGetAudioSampleRate(AudioDecComp* a, unsigned int* pSampleRate, + unsigned int* pChannelNum, unsigned int* pBitRate); + +int AudioDecCompSetTimer(AudioDecComp* a, AvTimer* timer); + +int AudioDecCompRequestStreamBuffer(AudioDecComp* a, + int nRequireSize, + char** ppBuf, + int* pBufSize, + char** ppRingBuf, + int* pRingBufSize, + int nStreamIndex); + +int AudioDecCompSubmitStreamData(AudioDecComp* a, + AudioStreamDataInfo* pDataInfo, + int nStreamIndex); + +int AudioDecCompStreamBufferSize(AudioDecComp* a, int nStreamIndex); + +int AudioDecCompStreamDataSize(AudioDecComp* a, int nStreamIndex); + +int AudioDecCompStreamFrameNum(AudioDecComp* a, int nStreamIndex); + +int AudioDecCompRequestPcmData(AudioDecComp* a, + unsigned char** ppData, + unsigned int* pSize, + int64_t* pPts, + CdxPlaybkCfg* cfg); + +int AudioDecCompReleasePcmData(AudioDecComp* a, int nReleaseSize); + +int AudioDecCompPcmDataSize(AudioDecComp* a, int nStreamIndex); + +int AudioDecCompSwitchStream(AudioDecComp* a, int nStreamIndex); + +void AudioDecRawSendCmdToHalClbk(void *pself,void *param); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/audioRenderComponent.h b/platform/mcu/xr871/src/cedarx/playback/audioRenderComponent.h new file mode 100644 index 0000000000..10c7aa6638 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/audioRenderComponent.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : audioRenderComponent.h + * Description : audio render component + * History : + * + */ + +#ifndef AUDIO_RENDER_H +#define AUDIO_RENDER_H + +#include "player_i.h" +#include "audioDecComponent.h" +#include "soundControl.h" + +typedef struct AudioRenderComp AudioRenderComp; + +AudioRenderComp* AudioRenderCompCreate(void); + +int AudioRenderCompDestroy(AudioRenderComp* a); + +int AudioRenderCompStart(AudioRenderComp* a); + +int AudioRenderCompStop(AudioRenderComp* a); + +int AudioRenderCompPause(AudioRenderComp* a); + +enum EPLAYERSTATUS AudioRenderCompGetStatus(AudioRenderComp* a); + +int AudioRenderCompReset(AudioRenderComp* a); + +int AudioRenderCompSetEOS(AudioRenderComp* a); + +int AudioRenderCompSetCallback(AudioRenderComp* a, PlayerCallback callback, void* pUserData); + +int AudioRenderCompSetTimer(AudioRenderComp* a, AvTimer* timer); + +int AudioRenderCompSetAudioSink(AudioRenderComp* a, SoundCtrl* pAudioSink); + +int AudioRenderCompSetDecodeComp(AudioRenderComp* a, AudioDecComp* d); + +int64_t AudioRenderCompCacheTimeUs(AudioRenderComp* a); + +int AudioRenderCompGetAudioOutBalance(AudioRenderComp* a); + +//* set audio balance, 1 means left channel, 2 means right channel, 3 means stereo. +int AudioRenderCompSetAudioOutBalance(AudioRenderComp* a, int nBalance); + +//* set audio mute, bMute = 1 means mute audio, 0 means resume from mute. +int AudioRenderCompSetAudioMute(AudioRenderComp* a, int bMute); + +//* get the audio mute setting, 1 means audio muted, 0 means not muted. +int AudioRenderCompGetAudioMuteFlag(AudioRenderComp* a); + +int AudioRenderCompSetForceWriteToDeviceFlag(AudioRenderComp* a, int bForceFlag); + +int AudioRenderCompSetPlaybackRate(AudioRenderComp* a,const XAudioPlaybackRate* rate); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/avtimer.h b/platform/mcu/xr871/src/cedarx/playback/avtimer.h new file mode 100644 index 0000000000..ba1b6a71e9 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/avtimer.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : avtimer.h + * Description : audio-video synchronization timer + * History : + * + */ + +#ifndef AVTIMER_H +#define AVTIMER_H + +#include + +//************************************************************// +//***************** define status of a timer *****************// +//************************************************************// +#define TIMER_STATUS_START 0x55 +#define TIMER_STATUS_STOP 0xaa + +typedef struct AvTimer AvTimer; +struct AvTimer +{ + //* set clock counting speed. + int (*SetSpeed)(AvTimer* t, int speed); + + //* get the current counting speed. + int (*GetSpeed)(AvTimer* t); + + //* set time. + int (*SetTime)(AvTimer* t, int64_t time); + + //* get the current time. + int64_t (*GetTime)(AvTimer* t); + + //* trasform pts to system time + //* Careful: this interface should only be used by video render + int64_t (*PtsToSystemTime)(AvTimer* t, int64_t pts); + + //* run the timer, start clock counting at 'start_time' and running at speed 'speed'. + int (*Start)(AvTimer* t); + + //* stop the timer. + void (*Stop)(AvTimer* t); + + int (*GetStatus)(AvTimer* t); + + int (*SetPlayRate)(AvTimer* t, float rate); + +}; + +//* create a timer, which is implemented in file 'avtimer.c'. +AvTimer* AvTimerCreate(void); + +void AvTimerDestroy(AvTimer*); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/baseComponent.h b/platform/mcu/xr871/src/cedarx/playback/baseComponent.h new file mode 100644 index 0000000000..410c7ef499 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/baseComponent.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : baseComponent.h + * Description : base component + * History : + * Date : 2016/08/03 + * Comment : first version + */ + +#ifndef BASE_COMPONENT_H +#define BASE_COMPONENT_H + +#include +//#include +#include "pthread.h" +#include + +struct AwMessage { + AWMESSAGE_COMMON_MEMBERS + + sem_t *replySem; + int *result; + union { + int64_t seekTime; + void *opaque; + int64_t int64Value; + }; +}; + +typedef struct BaseMsgHandler { + msgHandlerT start; + msgHandlerT stop; + msgHandlerT pause; + msgHandlerT reset; + msgHandlerT setEos; + msgHandlerT quit; + union { + msgHandlerT continueWork; + msgHandlerT decode; + msgHandlerT encode; + msgHandlerT mux; + msgHandlerT render; + }; +} BaseMsgHandler; + +enum MESSAGE_ID { + MESSAGE_ID_START = 0, + MESSAGE_ID_STOP = 1, + MESSAGE_ID_PAUSE = 2, + MESSAGE_ID_QUIT = 3, + MESSAGE_ID_RESET = 4, + MESSAGE_ID_EOS = 5, + + /* continue decoder/encoder/mux/render */ + MESSAGE_ID_CONTINUE = 6, + + MESSAGE_ID_SET_WINDOW, + MESSAGE_ID_SET_3D_MODE, + MESSAGE_ID_SET_AUDIO_SINK, + MESSAGE_ID_SET_VIDEO_HIDE, + MESSAGE_ID_SET_HOLD_LAST_PICTURE, + MESSAGE_ID_SET_TIMESHIFT, + MESSAGE_ID_SET_LAYER_INFO, + MESSAGE_ID_SET_SUB_RENDER, + MESSAGE_ID_SET_DI, +}; + +typedef struct BaseCompCtx { + /** + * It should point to a string literal. + */ + const char *name; + + /** + * This mq should be initialized before call BaseCompInit() + */ + AwMessageQueue *mq; + + /* continueWork doesn't need a reply */ + sem_t replySem[MESSAGE_ID_EOS + 1]; + BaseMsgHandler handler; +} BaseCompCtx; + +int BaseCompInit(BaseCompCtx *p, const char *name, + AwMessageQueue *mq, BaseMsgHandler *handler); + +void BaseCompDestroy(BaseCompCtx *p); + +typedef void (*task_t)(void *); + +int BaseCompStart(BaseCompCtx *p, task_t afterPostBeforeWait, void *arg); + +int BaseCompStop(BaseCompCtx *p, task_t afterPostBeforeWait, void *arg); + +int BaseCompPause(BaseCompCtx *p, task_t afterPostBeforeWait, void *arg); + +int BaseCompReset(BaseCompCtx *p, int64_t nSeekTime, + task_t afterPostBeforeWait, void *arg); + +int BaseCompSetEos(BaseCompCtx *p, task_t afterPostBeforeWait, void *arg); + +int BaseCompQuit(BaseCompCtx *p, task_t afterPostBeforeWait, void *arg); + +int BaseCompContinue(BaseCompCtx *p); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/bitrateEstimater.h b/platform/mcu/xr871/src/cedarx/playback/bitrateEstimater.h new file mode 100644 index 0000000000..85ecea049f --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/bitrateEstimater.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : bitrateEstimater.h + * Description : bitrate estimater + * History : + * + */ + +#ifndef BITRATE_ESTIMATER_H +#define BITRATE_ESTIMATER_H + +#include +#include +#include + +#define BITRATE_ARRAY_SIZE 50 +#define BITRATE_ESTIMATE_INTERVAL 5 +#define PTS_DISCONTINUE_INTERVAL 1000000 + +typedef struct BR_ESTIMATER_NODE +{ + int64_t nFramePts; + int nFrameLen; +}BitrateEstimateNode; + +typedef struct BitrateEstimater +{ + pthread_mutex_t mutex; + int nBitrate; + int nWritePos; + int nValidNodeCnt; + int nWritePosLastEstimate; + BitrateEstimateNode nodes[BITRATE_ARRAY_SIZE]; +}BitrateEstimater; + +BitrateEstimater* BitrateEstimaterCreate(void); + +void BitrateEstimaterDestroy(BitrateEstimater* be); + +void BitrateEstimaterUpdate(BitrateEstimater* be, int64_t nPts, int nFrameLen); + +int BitrateEstimaterGetBitrate(BitrateEstimater* be); + +void BitrateEstimaterReset(BitrateEstimater* be); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/framerateEstimater.h b/platform/mcu/xr871/src/cedarx/playback/framerateEstimater.h new file mode 100644 index 0000000000..1ef054e445 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/framerateEstimater.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : framerateEstimater.h + * Description : framerate estimater + * History : + * + */ + +#ifndef FRAME_ESTIMATER_H +#define FRAME_ESTIMATER_H + +#include +#include +#include + +#define FRAMERATE_ARRAY_SIZE 4 +#define FRAMERATE_START_ESTIMATE_SIZE 2 + +typedef struct FramerateEstimater +{ + int64_t nPts[FRAMERATE_ARRAY_SIZE]; + int nWritePos; + int nValidPtsCnt; + int nFrameDuration; + float fPlayRate; + pthread_mutex_t mutex; +}FramerateEstimater; + +FramerateEstimater* FramerateEstimaterCreate(void); + +void FramerateEstimaterDestroy(FramerateEstimater* fe); + +void FramerateEstimaterUpdate(FramerateEstimater* fe, int64_t nPts); + +int FramerateEstimaterGetFramerate(FramerateEstimater* fe); + +int FramerateEstimaterGetFrameDuration(FramerateEstimater* fe); //* in unit of us. + +int FramerateEstimaterSetPlayrate(FramerateEstimater* fe,float rate); + +void FramerateEstimaterReset(FramerateEstimater* fe); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/include/player.h b/platform/mcu/xr871/src/cedarx/playback/include/player.h new file mode 100644 index 0000000000..5c754c0214 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/include/player.h @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : player.h + * Description : player + * History : + * + */ + +#ifndef PLAYER_H +#define PLAYER_H + +#include "cdx_log.h" +//#include "cdx_config.h" + +#if VIDEO_SUPPORT +#include "vdecoder.h" +#include "layerControl.h" +#include "deinterlace.h" +#endif +#include "adecoder.h" +#include "soundControl.h" +#if SUBTITLE_SUPPORT +#include "sdecoder.h" +#include "subtitleControl.h" +#endif + + +#include + +enum EPLAYERNOTIFY { + PLAYBACK_NOTIFY_EOS = PLAYBACK_NOTIFY_VALID_RANGE_MIN, + + //* param == NULL; + PLAYBACK_NOTIFY_FIRST_PICTURE, + + //* width = ((int*)param)[0]; height = ((int*)param)[1]; + PLAYBACK_NOTIFY_VIDEO_SIZE, + //* leftOffset = ((int*)param)[0; topOffset = ((int*)param)[1]; + //* cropWidth = ((int*)param)[2]; cropHeight = ((int*)param)[3]; + PLAYBACK_NOTIFY_VIDEO_CROP, + + //* subtitle_id = ((unsigned int*)param)[0]; + //* pSubtitleItem = (SubtitleItem*)((unsigned int*)param)[1]; + PLAYBACK_NOTIFY_SUBTITLE_ITEM_AVAILABLE, + //* subtitle_id = (unsigned int)param; + PLAYBACK_NOTIFY_SUBTITLE_ITEM_EXPIRED, + + //* video stream not supported, video decoder crash. + PLAYBACK_NOTIFY_VIDEO_UNSUPPORTED, + //* audio stream not supported, audio decoder crash. + PLAYBACK_NOTIFY_AUDIO_UNSUPPORTED, + //* subtitle stream not supported, subtitle decoder crash. + PLAYBACK_NOTIFY_SUBTITLE_UNSUPPORTED, + PLAYBACK_NOTIFY_AUDIORAWPLAY, + + PLAYBACK_NOTIFY_SET_SECURE_BUFFER_COUNT, + PLAYBACK_NOTIFY_SET_SECURE_BUFFERS, + + PLAYBACK_NOTIFY_AUDIO_INFO, + + PLAYBACK_NOTIFY_VIDEO_RENDER_FRAME, + + PLAYBACK_NOTIFY_MAX, +}; +CHECK_PLAYBACK_NOTIFY_MAX_VALID(PLAYBACK_NOTIFY_MAX) + +enum EPLAYERSTATUS +{ + PLAYER_STATUS_STOPPED = 0, + PLAYER_STATUS_STARTED, + PLAYER_STATUS_PAUSED +}; + +enum EMEDIATYPE +{ + MEDIA_TYPE_VIDEO = 0, + MEDIA_TYPE_AUDIO, + MEDIA_TYPE_SUBTITLE, + MEDIA_TYPE_METADATA +}; + +enum EPICTURE3DMODE +{ + PICTURE_3D_MODE_NONE = 0, + PICTURE_3D_MODE_TWO_SEPERATED_PICTURE, + PICTURE_3D_MODE_SIDE_BY_SIDE, + PICTURE_3D_MODE_TOP_TO_BOTTOM, + PICTURE_3D_MODE_LINE_INTERLEAVE, + PICTURE_3D_MODE_COLUME_INTERLEAVE +}; + +enum EDISPLAY3DMODE +{ + DISPLAY_3D_MODE_2D = 0, + DISPLAY_3D_MODE_3D, + DISPLAY_3D_MODE_HALF_PICTURE +}; + +enum EDISPLAYRATIO +{ + DISPLAY_RATIO_FULL_SCREEN, + DISPLAY_RATIO_LETTERBOX, + //* add new mode. +}; + +typedef struct MEDIASTREAMDATAINFO +{ + char* pData; + int nLength; + int64_t nPts; + int64_t nPcr; + int bIsFirstPart; + int bIsLastPart; + int64_t nDuration; //* in unit of us. + int nStreamChangeFlag; + int nStreamChangeNum; + void *pStreamInfo; +}MediaStreamDataInfo; + +typedef int (*PlayerCallback)(void* pUserData, int eMessageId, void* param); + +typedef void* Player; + + +#ifdef __cplusplus +extern "C" { +#endif + +Player* PlayerCreate(void); + +void PlayerDestroy(Player* pl); + +int PlayerSetCallback(Player* pl, PlayerCallback callback, void* pUserData); + + +//******************************* START **********************************// +//** Play Control APIs. +//** + +int PlayerStart(Player* pl); + +int PlayerStop(Player* pl); //* media stream information is still kept by the player. + +int PlayerPause(Player* pl); + +//* for seek operation, mute be called under paused status. +int PlayerReset(Player* pl, int64_t nSeekTimeUs); + +//* must be called under stopped status, all stream information cleared. +int PlayerClear(Player* pl); + +#if VIDEO_SUPPORT +//* set player playback in fast mode. +//* in fast mode, video is showed directly without any synchronization, and +//* audio is should not send in. +int PlayerFast(Player* pl, int bDecodeKeyframeOnly); + +//* return from fast mode, the player is set to started status when return. +int PlayerStopFast(Player* pl); +#endif + +enum EPLAYERSTATUS PlayerGetStatus(Player* pl); + +int64_t PlayerGetPosition(Player* pl); //* current time positon in us. + +int64_t PlayerGetPositionCMCC(Player* pl); //* current time positon in us. + +int64_t PlayerGetPts(Player* pl); //* current presentation time stamp. + +int PlayerSetDiscardAudio(Player* pl, int f); // for IPTV, discard audi in fast mode + +//******************************** END ***********************************// + +//******************************* START **********************************// +//** Streaming Control APIs. +//** + +int PlayerRequestStreamBuffer(Player* pl, + int nRequireSize, + void** ppBuf, + int* pBufSize, + void** ppRingBuf, + int* pRingBufSize, + enum EMEDIATYPE eMediaType, + int nStreamIndex); + +int PlayerSubmitStreamData(Player* pl, + MediaStreamDataInfo* pDataInfo, + enum EMEDIATYPE eMediaType, + int nStreamIndex); + +int PlayerSetEos(Player* pl); + +int PlayerSetFirstPts(Player* pl, int64_t nFirstPts); + +#if VIDEO_SUPPORT +//* estimated by pts and stream data size. +int PlayerGetVideoBitrate(Player* pl); + +//* estimated by pts. +int PlayerGetVideoFrameRate(Player* pl); + +//* estimated by pts. +int PlayerGetVideoFrameDuration(Player* pl); + +//* how much video stream data in stream buffere. +int PlayerGetVideoStreamDataSize(Player* pl); + +//* the size of video stream buffer +int PlayerGetVideoStreamBufferSize(Player* pl); + +//* how many stream frame in buffer. +int PlayerGetVideoStreamFrameNum(Player* pl); + +//* how many picture has been decoded and waiting to show. +int PlayerGetValidPictureNum(Player* pl); +#endif + +//* estimated by pts and stream data size. +int PlayerGetAudioBitrate(Player* pl); + +//* get audio sample rate, channel count and how many bits per sample of pcm data. +int PlayerGetAudioParam(Player* pl, int* pSampleRate, int* pChannelCount, int* pBitsPerSample); + +//* how much audio stream data in stream buffer. +int PlayerGetAudioStreamDataSize(Player* pl); + +//* how many stream frame in buffer. +int PlayerGetAudioStreamFrameNum(Player* pl); + +//* how much audio pcm data has been decoded to the pcm buffer. +int PlayerGetAudioPcmDataSize(Player* pl); + +//* how much audio pcm data cached in audio device. +int PlayerGetAudioCacheTimeInSoundDevice(Player* pl); + +//******************************** END ***********************************// + +//******************************* START **********************************// +//** Video APIs. +//** +#if VIDEO_SUPPORT +int PlayerSetVideoStreamInfo(Player* pl, VideoStreamInfo* pStreamInfo); + +int PlayerCanSupportVideoStream(Player* pl, VideoStreamInfo* pStreamInfo); + +int PlayerHasVideo(Player* pl); + +int PlayerConfigVideoScaleDownRatio(Player* pl, int nHorizonRatio, int nVerticalRatio); + +int PlayerConfigVideoRotateDegree(Player* pl, int nDegree); + +int PlayerConfigVideoDeinterlace(Player* pl, int bOpenDeinterlace); +int PlayerConfigDispErrorFrame(Player* pl, int bDispErrorFrame); +int PlayerConfigDropDelayFrame(Player* pl, int bDropDelayFrame); +int PlayerConfigTvStreamFlag(Player* pl, int bFlag); +#endif +//******************************** END ***********************************// + +//******************************* START **********************************// +//** Audio APIs. +//** + +int PlayerSetAudioStreamInfo(Player* pl, AudioStreamInfo* pStreamInfo, + int nStreamNum, int nDefaultStream); + +int PlayerAddAudioStream(Player* pl, AudioStreamInfo* pStreamInfo); + +int PlayerCanSupportAudioStream(Player* pl, AudioStreamInfo* pStreamInfo); + +int PlayerGetAudioStreamCnt(Player* pl); + +int PlayerGetAudioStreamInfo(Player* pl, int* pStreamNum, AudioStreamInfo** ppStreamInfo); + +int PlayerHasAudio(Player* pl); + +int PlayerSwitchAudio(Player* pl, int nStreamIndex); + +//hkw switch audio track for IPTV +int PlayerStopAudio(Player* pl); + +int PlayerStartAudio(Player* pl); + +//******************************** END ***********************************// + +//******************************* START **********************************// +//** Subtitle APIs. +//** +#if SUBTITLE_SUPPORT +int PlayerSetSubtitleStreamInfo(Player* pl, SubtitleStreamInfo* pStreamInfo, + int nStreamNum, int nDefaultStream); + +int PlayerAddSubtitleStream(Player* pl, SubtitleStreamInfo* pStreamInfo); + +int PlayerCanSupportSubtitleStream(Player* pl, SubtitleStreamInfo* pStreamInfo); + +int PlayerGetSubtitleStreamCnt(Player* pl); + +/* stream info array is allocated inside, user need to free the memory by + * calling free(*ppStreamInfo); + */ +int PlayerGetSubtitleStreamInfo(Player* pl, int* pStreamNum, SubtitleStreamInfo** ppStreamInfo); + +/* stream info array is allocated inside, user need to free the memory by + * calling free(*ppStreamInfo); + */ +int PlayerProbeSubtitleStreamInfo(const char* strFileName, + int* pStreamNum, + SubtitleStreamInfo** ppStreamInfo); + +/* stream info array is allocated inside, user need to free the memory by + * calling free(*ppStreamInfo); + */ +int PlayerProbeSubtitleStreamInfoFd(int fd, int offset, int len, int* pStreamNum, + SubtitleStreamInfo** ppStreamInfo); + +int PlayerSwitchSubtitle(Player* pl, int nStreamIndex); + +//* adjust subtitle show time, in +int PlayerSetSubtitleShowTimeAdjustment(Player* pl, int nTimeMs); + +//* get the adjustment of subtitle show time, in unit of ms. +int PlayerGetSubtitleShowTimeAdjustment(Player* pl); + +//* set subRender +int PlayerSetSubCtrl(Player* pl, SubCtrl* pSubCtrl); +#endif +//******************************** END ***********************************// + +//******************************* START **********************************// +//** Display Control APIs. +//** +#if VIDEO_SUPPORT +int PlayerSetWindow(Player* pl, LayerCtrl* pLc); + +//* this API is not used in new display +int PlayerSet3DMode(Player* pl, enum EPICTURE3DMODE ePicture3DMode, + enum EDISPLAY3DMODE eDisplay3DMode); + +int PlayerGet3DMode(Player* pl, enum EPICTURE3DMODE* ePicture3DMode, + enum EDISPLAY3DMODE* eDisplay3DMode); + +//* some times you need to know the picture size from the decoder under player. +int PlayerGetPictureSize(Player* pl, int* pWidth, int* pHeight); + +//* Get the video crop window. +int PlayerGetPictureCrop(Player* pl, int* pLeftOff, int* pTopOff, + int* pCropWidth, int* pCropHeight); + +//* Hide video layer. +int PlayerVideoHide(Player* pl); + +//* show video layer. +int PlayerVideoShow(Player* pl); + +//* set whether keep last picture when player stopped. +//* the last picture is hold in default. +int PlayerSetHoldLastPicture(Player* pl, int bHold); + +//* set video window. +int PlayerSetVideoRegion(Player* pl, int x, int y, int nWidth, int nHeight); + +//* set picture display ratio, full stream, letter box or other modes. +int PlayerSetDisplayRatio(Player* pl, enum EDISPLAYRATIO eDisplayRatio); + +//* set deinterlace +int PlayerSetDeinterlace(Player* pl, Deinterlace* pDi); +#endif +//******************************** END ***********************************// + +//******************************* START **********************************// +//** Audio Output Control APIs. +//** +int PlayerSetAudioSink(Player* pl, SoundCtrl* pAudioSink); + +//* get audio balance, return 1 means left channel, 2 means right channel, 3 means stereo. +int PlayerGetAudioBalance(Player* pl); + +//* set audio balance, 1 means left channel, 2 means right channel, 3 means stereo. +int PlayerSetAudioBalance(Player* pl, int nAudioBalance); + +//* mute the audio, bMute = 1 means mute the audio, 0 means resume from muted. +int PlayerSetAudioMute(Player* pl, int bMute); + +/* get the audio mute setting, 1 means audio muted, 0 means not muted, -1 means + * there is no audio stream. + */ +int PlayerGetAudioMuteFlag(Player* pl); + +int PlayerSetAudioForceWriteToDeviceFlag(Player* pl, int bForceFlag); + +int PlayerConfigExtraScaleInfo(Player* pl, int nWidthTh, int nHeightTh, + int nHorizontalScaleRatio, int nVerticalScaleRatio); + +int PlayerSetPlayBackSettings(Player* pl,const struct XAudioPlaybackRate* rate); + +int PlayerGetPlayBackSettings(Player* pl,XAudioPlaybackRate* rate); + +//******************************** END ***********************************// + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/include/soundControl.h b/platform/mcu/xr871/src/cedarx/playback/include/soundControl.h new file mode 100644 index 0000000000..5f16007018 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/include/soundControl.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : soundControl.h + * Description : soundControl + * History : + * + */ + +#ifndef SOUND_CONTROL_H +#define SOUND_CONTROL_H +#include "cdx_log.h" +#include "adecoder.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum XAudioTimestretchStretchMode { + AUDIO_TIMESTRETCH_STRETCH_DEFAULT = 0, + AUDIO_TIMESTRETCH_STRETCH_SPEECH = 1, +} XAudioTimestretchStretchMode; + +typedef enum XAudioTimestretchFallbackMode { + XAUDIO_TIMESTRETCH_FALLBACK_CUT_REPEAT = -1, + XAUDIO_TIMESTRETCH_FALLBACK_DEFAULT = 0, + XAUDIO_TIMESTRETCH_FALLBACK_MUTE = 1, + XAUDIO_TIMESTRETCH_FALLBACK_FAIL = 2, +} XAudioTimestretchFallbackMode; + +typedef struct XAudioPlaybackRate { + float mSpeed; + float mPitch; + enum XAudioTimestretchStretchMode mStretchMode; + enum XAudioTimestretchFallbackMode mFallbackMode; +}XAudioPlaybackRate; + +typedef struct SoundCtrl SoundCtrl; + +typedef struct SoundControlOpsS SoundControlOpsT; + +struct SoundControlOpsS +{ + void (*destroy)(SoundCtrl* s); + + void (*setFormat)(SoundCtrl* s, CdxPlaybkCfg* cfg); + + int (*start)(SoundCtrl* s); + + int (*stop)(SoundCtrl* s); + + int (*pause)(SoundCtrl* s); + + int (*flush)(SoundCtrl* s, void *block); + + int (*write)(SoundCtrl* s, void* pData, int nDataSize); + + int (*reset)(SoundCtrl* s); + + int (*getCachedTime)(SoundCtrl* s); + + int (*getFrameCount)(SoundCtrl* s); + + int (*setPlaybackRate)(SoundCtrl* s,const XAudioPlaybackRate *rate); + +}; + +struct SoundCtrl +{ + struct SoundControlOpsS* ops; +}; + +static inline void SoundDeviceDestroy(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->destroy); + return s->ops->destroy(s); +} + +static inline void SoundDeviceSetFormat(SoundCtrl* s, CdxPlaybkCfg* cfg) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->setFormat); + return s->ops->setFormat(s, cfg); +} + +static inline int SoundDeviceStart(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->start); + return s->ops->start(s); +} + +static inline int SoundDeviceStop(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->stop); + return s->ops->stop(s); +} + +static inline int SoundDevicePause(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->pause); + return s->ops->pause(s); +} + +static inline int SoundDeviceFlush(SoundCtrl* s, void* block) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->flush); + return s->ops->flush(s, block); +} + +static inline int SoundDeviceWrite(SoundCtrl* s, void* pData, int nDataSize) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->write); + return s->ops->write(s, pData, nDataSize); +} + +static inline int SoundDeviceReset(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->reset); + return s->ops->reset(s); +} + +static inline int SoundDeviceGetCachedTime(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->getCachedTime); + return s->ops->getCachedTime(s); +} + +static inline int SoundDeviceGetFrameCount(SoundCtrl* s) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + CDX_CHECK(s->ops->getFrameCount); + return s->ops->getFrameCount(s); +} + +static inline int SoundDeviceSetPlaybackRate(SoundCtrl* s,const XAudioPlaybackRate *rate) +{ + CDX_CHECK(s); + CDX_CHECK(s->ops); + return s->ops->setPlaybackRate(s,rate); +} + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/playback/player_i.h b/platform/mcu/xr871/src/cedarx/playback/player_i.h new file mode 100644 index 0000000000..a3c0cd9b66 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/player_i.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : player_i.h + * Description : player_i + * History : + * + */ + +#ifndef PLAYER_I_H +#define PLAYER_I_H + +#include "player.h" +#include +#include +#include + +enum EPLAYERINTERNALNOTIFY //* player internal notify. +{ + PLAYER_VIDEO_DECODER_NOTIFY_STREAM_UNDERFLOW = 32, + PLAYER_VIDEO_DECODER_NOTIFY_CRASH, + PLAYER_VIDEO_DECODER_NOTIFY_EOS, + PLAYER_VIDEO_DECODER_NOTIFY_SET_SECURE_BUFFER_COUNT, + PLAYER_VIDEO_DECODER_NOTIFY_SET_SECURE_BUFFERS, + + PLAYER_VIDEO_RENDER_NOTIFY_FIRST_PICTURE = 64, + PLAYER_VIDEO_RENDER_NOTIFY_PICTURE_PTS, + PLAYER_VIDEO_RENDER_NOTIFY_EOS, + PLAYER_VIDEO_RENDER_NOTIFY_VIDEO_SIZE, + PLAYER_VIDEO_RENDER_NOTIFY_VIDEO_CROP, + PLAYER_VIDEO_RENDER_NOTIFY_VIDEO_FRAME, + PLAYER_VIDEO_RENDER_NOTIFY_CRASH, + + PLAYER_AUDIO_DECODER_NOTIFY_STREAM_UNDERFLOW = 96, + PLAYER_AUDIO_DECODER_NOTIFY_CRASH, + PLAYER_AUDIO_DECODER_NOTIFY_EOS, + PLAYER_AUDIO_DECODER_NOTIFY_AUDIORAWPLAY, + + PLAYER_AUDIO_RENDER_NOTIFY_FIRST_FRAME = 128, + PLAYER_AUDIO_RENDER_NOTIFY_EOS, + PLAYER_AUDIO_RENDER_NOTIFY_PTS_AND_CACHETIME, + PLAYER_AUDIO_RENDER_NOTIFY_AUDIO_INFO, + + PLAYER_SUBTITLE_DECODER_NOTIFY_STREAM_UNDERFLOW = 160, + PLAYER_SUBTITLE_DECODER_NOTIFY_CRASH, + PLAYER_SUBTITLE_DECODER_NOTIFY_EOS, + + PLAYER_SUBTITLE_RENDER_NOTIFY_ITEM_PTS_AND_DURATION = 192, + PLAYER_SUBTITLE_RENDER_NOTIFY_ITEM_AVAILABLE, + PLAYER_SUBTITLE_RENDER_NOTIFY_ITEM_EXPIRED, + PLAYER_SUBTITLE_RENDER_NOTIFY_EOS, +}; + +// report every 5 seconds. +#define CONFIG_AUDIO_RENDER_TIME_DIFFERENCE_REPORT_PERIOD (5000000) + +// choose the larger pts of nFirstVideoPts and nFirstAudioPts as the player start time. +#define CONFIG_USE_LARGER_PTS_AS_START_TIME (1) + +// if pts difference is more than 4 seconds, we judge there is a pts jump(loop back) event. +#define CONFIG_THREASHOLD_OF_PTS_DIFFERENCE_TO_JUDGE_PTS_jUMP (4000000) + +// if pts difference is more than 1.5 seconds, we judge there is a pts jump(loop back) event. +#define CONFIG_THREASHOLD_OF_PTS_DIFFERENCE_TO_JUDGE_PTS_jUMP_DTMB (1500000) + +/* don't wait for synchronization for too long, should not smaller than + * CONFIG_THREASHOLD_OF_PTS_DIFFERENCE_TO_JUDGE_PTS_jUMP. + */ +#define CONFIG_MAX_WAIT_TIME_FOR_SYNC (4000000) + +// 20 seconds. +#define CONFIG_THREASHOLD_OF_PTS_DIFFERENCE_TO_JUDGE_PTS_jUMP_FOR_SUBTITLE (20000000) + +#define TIMER_DROP_AUDIO_DATA 0x04 +#define TIMER_DROP_VIDEO_DATA 0x05 +#define TIMER_NEED_NOTIFY_AGAIN 0x06 + +/*static int64_t GetSysTime(void) +{ + int64_t time; + struct timeval t; + gettimeofday(&t, NULL); + time = (int64_t)t.tv_sec * 1000000; + time += t.tv_usec; + return time; +}*/ + +#define CDX_PLAYER_UNUSE(param) (void)param + +#endif diff --git a/platform/mcu/xr871/src/cedarx/playback/streamManager.h b/platform/mcu/xr871/src/cedarx/playback/streamManager.h new file mode 100644 index 0000000000..71519c217c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/playback/streamManager.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : streamManager.h + * Description : stream manager + * History : + * + */ + +#ifndef STREAM_MANAGER_H +#define STREAM_MANAGER_H + +#include + +typedef struct StreamFrameS StreamFrame; +struct StreamFrameS { + void* pData; + int nLength; + int64_t nPts; + int64_t nPcr; + int64_t nDuration; +}; + +typedef struct StreamManager StreamManager; + +StreamManager* StreamManagerCreate(int nMaxBufferSize, int nMaxFrameNum, int nStreamID); + +void StreamManagerDestroy(StreamManager* pSm); + +void StreamManagerReset(StreamManager* pSm); + +int StreamManagerBufferSize(StreamManager* pSm); + +int StreamManagerStreamFrameNum(StreamManager* pSm); + +int StreamManagerStreamDataSize(StreamManager* pSm); + +int StreamManagerRequestBuffer(StreamManager* pSm, int nRequireSize, char** ppBuf, int* pBufSize); + +int StreamManagerAddStream(StreamManager* pSm, StreamFrame* pStreamFrame); + +StreamFrame* StreamManagerRequestStream(StreamManager* pSm); + +StreamFrame* StreamManagerGetFrameInfo(StreamManager* pSm, int nFrameIndex); + +int StreamManagerReturnStream(StreamManager* pSm, StreamFrame* pStreamFrame); + +/* This function is deprecated. It does nothing. */ +int StreamManagerFlushStream(StreamManager* pSm, StreamFrame* pStreamFrame); + +/* Rewind the stream to a specific position/time. You should call this function + * after switch track. + */ +int StreamManagerRewind(StreamManager *p, int64_t curTime); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/record/include/CaptureControl.h b/platform/mcu/xr871/src/cedarx/record/include/CaptureControl.h new file mode 100644 index 0000000000..03d27cc46e --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/record/include/CaptureControl.h @@ -0,0 +1,77 @@ +#ifndef CAPTURE_CONTROL_H +#define CAPTURE_CONTROL_H +#include "cdx_log.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + int nChannels; + int nSamplerate; + int nBitpersample; +} CdxCapbkCfg; + +typedef struct CaptureCtrl CaptureCtrl; + +struct CaptureControlOpsS +{ + void (*destroy)(CaptureCtrl* c); + void (*setFormat)(CaptureCtrl* c, CdxCapbkCfg* cfg); + int (*start)(CaptureCtrl* c); + int (*stop)(CaptureCtrl* c); + int (*read)(CaptureCtrl* c, void* pData, int nDataSize); +}; + +struct CaptureCtrl +{ + struct CaptureControlOpsS* ops; +}; + +CaptureCtrl* CaptureDeviceCreate(); + +static inline void CaptureDeviceDestroy(CaptureCtrl* c) +{ + CDX_CHECK(c); + CDX_CHECK(c->ops); + CDX_CHECK(c->ops->destroy); + return c->ops->destroy(c); +} + +static inline void CaptureDeviceSetFormat(CaptureCtrl* c, CdxCapbkCfg* cfg) +{ + CDX_CHECK(c); + CDX_CHECK(c->ops); + CDX_CHECK(c->ops->setFormat); + return c->ops->setFormat(c, cfg); +} + +static inline int CaptureDeviceStart(CaptureCtrl* c) +{ + CDX_CHECK(c); + CDX_CHECK(c->ops); + CDX_CHECK(c->ops->start); + return c->ops->start(c); +} + +static inline int CaptureDeviceStop(CaptureCtrl* c) +{ + CDX_CHECK(c); + CDX_CHECK(c->ops); + CDX_CHECK(c->ops->stop); + return c->ops->stop(c); +} + +static inline int CaptureDeviceRead(CaptureCtrl* c, void* pData, int nDataSize) +{ + CDX_CHECK(c); + CDX_CHECK(c->ops); + CDX_CHECK(c->ops->read); + return c->ops->read(c, pData, nDataSize); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/mcu/xr871/src/cedarx/stream/http/CdxHttpStream.h b/platform/mcu/xr871/src/cedarx/stream/http/CdxHttpStream.h new file mode 100644 index 0000000000..e5d235a5be --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/stream/http/CdxHttpStream.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxHttpStream.h + * Description : Part of http stream. + * History : + * + */ + +#ifndef CDX_HTTP_STREAM_H +#define CDX_HTTP_STREAM_H + +#include +#include +#include +#include +#include +#include + +#define __SAVE_BITSTREAMS (0) + +//#define closesocket close + +#define __CONFIG_ZLIB (0) + +#define CONFIG_ALI_YUNOS (0) + +struct HttpHeaderField +{ + const char *key; + const char *val; +}; + +typedef struct AW_HTTP_FIELD_TYPE +{ + char *fieldName; + struct AW_HTTP_FIELD_TYPE *next; +}CdxHttpFieldT; + +typedef struct AW_HTTP_HEADER +{ + char *protocol; + char *method; + char *uri; + unsigned int statusCode; + char *reasonPhrase; + unsigned int httpMinorVersion; + // Field variables + CdxHttpFieldT *firstField; + CdxHttpFieldT *lastField; + unsigned int fieldNb; + char *fieldSearch; + CdxHttpFieldT *fieldSearchPos; + // Body variables + char *body; + size_t bodySize; + char *buffer; + size_t bufferSize; + unsigned int isParsed; + // + char *cookies; + int posHdrSep; + } CdxHttpHeaderT; + +typedef struct BandwidthEntry +{ + cdx_int64 mDelayUs; + cdx_int32 mNumBytes; +}BandwidthEntryT; + +enum HttpStreamStateE +{ + HTTP_STREAM_IDLE = 0x00L, + HTTP_STREAM_CONNECTING = 0x01L, + HTTP_STREAM_READING = 0x02L, + HTTP_STREAM_SEEKING = 0x03L, +}; + +typedef struct CdxHttpStreamImpl +{ + CdxStreamT base; + CdxStreamT *tcpStream; + + CdxStreamProbeDataT probeData; + cdx_int32 ioState; //for interface use + int seekAble; //seekable flag. + CdxUrlT* url; //scheme,port,etc + cdx_int32 exitFlag; //when close, exit + cdx_int32 forceStopFlag; //forceStop, not exit GetNetworkData + cdx_int64 totalSize; //content-length + cdx_int64 bufPos; //stream data is buffered to this file pos. + cdx_int64 readPos; //stream data is read to this pos. + cdx_int32 eosFlag; //for internal use. + //all stream data is read from network + void *data; //point to response(2K) + cdx_char *sourceUri; //the source uri + + char *httpDataBuffer; //databuf, store one group data. + //1) 4KB, store response entity+probeData; + //2) 1024*n Bytes: normal data. + int httpDataSize; //total data size of httpDataBuffer + + char *httpDataBufferChunked; // store parsed data from chunked data; + int httpDataSizeChunked; // valid data size of httpDataBufferChunked + int httpDataBufferPosChunked; // read pos of httpDataBufferChunked, + // 0~httpDataSizeChunked-1 + int restChunkSize; // when chunked, during CdxStreamOpen, + // httpDataBuffer may not store the whole chunk, + // this variable store rest size of the chunk. + int dataCRLF; // data\r\n, next chunk need to get rid of \r\n. + cdx_char tmpChunkedLen[10]; // store temp chunked len while force stop. + // eg: abcd\r\n, ab + int tmpChunkedSize; // size of temp chunked len while force stop. + // eg: ab is 2 bytes + int lenCRLF; // len\r\n, next chunk need to get rid of \r\n. + int chunkedLen; // while force stop, store current chunked len. + // len\r\n + + const cdx_char *ua; // UA + int nHttpHeaderSize; //header number to be added + struct CdxHttpHeaderField *pHttpHeader; //http header + ExtraDataContainerT hfsContainer; + int chunkedFlag; //set when "Transfer-Encoding: chunked" + cdx_atomic_t ref; //reference count, for free resource while + //still blocking. + pthread_t threadId; + + pthread_t getNetworkDataThreadId; + int seekFlag; + int pauseReadDataFlag; + pthread_mutex_t bufferMutex; + pthread_cond_t bufferCond; + pthread_mutex_t seekMutex; + pthread_cond_t seekCond; + pthread_mutex_t pauseReadDataMutex; + pthread_cond_t pauseReadDataCond; + + pthread_mutex_t lock; //for break blocking operation + pthread_cond_t cond; + + cdx_char *buffer; //httpStream's buffer + cdx_int64 maxBufSize; //max buffer size + cdx_int64 validDataSize; + cdx_char *bufReadPtr; //read pointer + cdx_char *bufWritePtr; //write pointer + cdx_char *bufEndPtr; //point to the end of buffer + + cdx_int64 mTotalTransferTimeUs; //for bandwidth measurement. + cdx_int32 mTotalTransferBytes; + cdx_int32 mBandwidthTimes; + BandwidthEntryT bandWidthHistory[100]; + cdx_int32 index; + + //cdx_char *protectAreaPtr; //protect area, not cover, for seek back. + cdx_int64 protectAreaPos; //protectArea begin file pos. + //readPos-protectAreaPos: 0~maxProtectAreaSize + cdx_int64 protectAreaSize; //Size of protectArea + cdx_int32 maxProtectAreaSize; + cdx_int32 bufFullFlag; //buffer full flag. + cdx_int32 getNetworkDataFlag; //in GetNetworkData loop flag. + + enum HttpStreamStateE state; + AwPoolT *pool; + cdx_int32 bStreamReadEos; //CdxStreamRead eos. + + //cdx_int32 nResponseDataSize; //when reconnect, store the size of data + //in response entity. +#if __SAVE_BITSTREAMS + FILE *fp_http; + cdx_int32 streamIndx; + cdx_char location[256]; +#endif + + ParserCallback callback; + void *pUserData; + cdx_int64 downloadStart; + cdx_int64 downloadEnd; + cdx_int64 downloadTimeMs; + +#if CONFIG_ALI_YUNOS + cdx_int64 downloadFirstTime; + cdx_int64 downloadLastTime; + int mYunOSstatusCode; + char tcpIp[128]; +#endif + + int isHls; + cdx_int64 baseOffset; //* for id3 parser + +#if __CONFIG_ZLIB + int compressed; + z_stream inflateStream; + cdx_uint8 *inflateBuffer; +#endif + + int keepAlive; + int isAuth; + cdx_bool isDTMB; + cdx_bool enoughData; +}CdxHttpStreamImplT; + +typedef struct CdxHttpSendBuffer +{ + void *size; + void *buf; +}CdxHttpSendBufferT; + +extern CdxHttpHeaderT *CdxHttpNewHeader(void); +extern char *CdxHttpGetField(CdxHttpHeaderT *httpHdr, const char *fieldName); +extern char* CdxHttpBuildRequest(CdxHttpHeaderT *httpHdr); +extern CdxUrlT *CdxUrlRedirect(CdxUrlT **url, char *redir); +extern const char *GetUA(int n, CdxHttpHeaderFieldT *pHttpHeader); +extern CdxUrlT* CdxUrlNew(char* url); +extern void CdxHttpSetUri(CdxHttpHeaderT *httpHdr, const char *uri); +extern void CdxHttpSetField(CdxHttpHeaderT *httpHdr, const char *fieldName); +extern void CdxHttpFree(CdxHttpHeaderT *httpHdr); +extern int CdxHttpResponseAppend(CdxHttpHeaderT *httpHdr, char *response, int length); +extern int CdxHttpIsHeaderEntire(CdxHttpHeaderT *httpHdr); +extern int CdxHttpResponseParse(CdxHttpHeaderT *httpHdr); +extern int CdxHttpAuthenticate(CdxHttpHeaderT *httpHdr, CdxUrlT *url, int *authRetry); +extern cdx_int32 ReadChunkedSize(CdxStreamT *stream, cdx_char tmpLen[], cdx_int32* size); +extern cdx_int32 ReadChunkedData(CdxStreamT *stream, void *ptr, cdx_int32 size); +extern char *RmSpace(char *str); +extern int CdxHttpAddBasicAuthentication(CdxHttpHeaderT *httpHdr, const char *username, + const char *password); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/stream/include/CdxSeqBuffer.h b/platform/mcu/xr871/src/cedarx/stream/include/CdxSeqBuffer.h new file mode 100644 index 0000000000..5117d517af --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/stream/include/CdxSeqBuffer.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxSeqBuffer.h + * Description : SeqBuffer + * History : + * + */ + +#ifndef CDX_SEQ_BUFFER_H +#define CDX_SEQ_BUFFER_H +#include +#include +#include +#include + +struct SeqBufferS +{ + CdxListNodeT node; + CdxBufferT *val; + cdx_uint32 seqNum; +}; + +#define SeqBufferDel(buf)\ + CdxListDel(&buf->node); \ + CdxBufferDestroy(buf->val); \ + CdxFree(buf) + +static inline void SeqBufferClear(CdxListT *seqBufList) +{ + struct SeqBufferS *posSeqBuf, *tmpSeqBuf; + + CdxListForEachEntrySafe(posSeqBuf, tmpSeqBuf, seqBufList, node) + { + SeqBufferDel(posSeqBuf); + } + return ; +} + +static inline cdx_err SeqBufferInsert(CdxListT *seqBufList, struct SeqBufferS *seqBuf) +{ + struct SeqBufferS *posSeqBuf; + CdxListForEachEntryReverse(posSeqBuf, seqBufList, node) + { + if (posSeqBuf->seqNum <= seqBuf->seqNum) + { + break; + } + } + + if (posSeqBuf->seqNum == seqBuf->seqNum) + { + CDX_LOGW("Discarding duplicate buffer (%u, %u)", + posSeqBuf->seqNum, seqBuf->seqNum); + return CDX_FAILURE; + } + + CdxListAddAfter(&seqBuf->node, &posSeqBuf->node); + return CDX_SUCCESS; +} + +#endif diff --git a/platform/mcu/xr871/src/cedarx/stream/include/CdxStream.h b/platform/mcu/xr871/src/cedarx/stream/include/CdxStream.h new file mode 100644 index 0000000000..15c7df272d --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/stream/include/CdxStream.h @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxStream.h + * Description : Stream + * History : + * + */ + +/* +********************************************************************** +* File Name : CdxStream.h +* Author : bzchen@allwinnertech.com +* Version : 1.0 +* Data : 2013.08.29 +* Description: This file define data structure and interface of the stream module. +**********************************************************************/ + +#ifndef CDX_STREAM_H +#define CDX_STREAM_H +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct CdxStreamProbeDataS CdxStreamProbeDataT; +typedef struct CdxStreamCreatorS CdxStreamCreatorT; + +#define STREAM_SEEK_SET 0 //* offset from the file start. +#define STREAM_SEEK_CUR 1 //* offset from current file position. +#define STREAM_SEEK_END 2 //* offset from the file end. + +#define CDX_STREAM_FLAG_SEEK 0x01U +#define CDX_STREAM_FLAG_STT 0x02U /*seek to time*/ +#define CDX_STREAM_FLAG_NET 0x04U /*net work stream*/ +#define CDX_STREAM_FLAG_DTMB 0x08U /*dtmb live stream */ + +typedef struct CdxDataSourceS CdxDataSourceT; +typedef struct CdxStreamS CdxStreamT; +typedef CdxStreamT CustomerStream; + +enum DSExtraDataTypeE +{ + EXTRA_DATA_UNKNOWN, + EXTRA_DATA_HTTP_HEADER, + EXTRA_DATA_APPOINTED_TS, + EXTRA_DATA_RTP, + EXTRA_DATA_AES, + EXTRA_DATA_BDMV, + EXTRA_DATA_RTSP, + EXTRA_DATA_HTTP, //download spend time etc. + EXTRA_DATA_HLS, +}; + +struct CdxDataSourceS +{ + void* pHTTPServer; + cdx_char *uri; /* format : "scheme://..." */ + void *extraData; /* extra data for some stream, ex: http header for http stream */ + enum DSExtraDataTypeE extraDataType; + cdx_int64 offset; /* for id3 parser */ + int probeSize; +}; + +#if 1 +/* These two struct is deprecated, you should use CdxKeyedVectorT interface */ +typedef struct CdxHttpHeaderField +{ + const char *key; + const char *val; +}CdxHttpHeaderFieldT; + +typedef struct CdxHttpHeaderFields +{ + int num; + CdxHttpHeaderFieldT *pHttpHeader; +}CdxHttpHeaderFieldsT; +#endif + +typedef struct ExtraDataContainerS +{ + void *extraData; + enum DSExtraDataTypeE extraDataType; +}ExtraDataContainerT; + +/*------------------------BDMV stream header---------------------------*/ +struct IoOperationS +{ + int (*openDir)(void * /*cbhdr*/, const char * /*name*/, void ** /*dir handler*/); + int (*readDir)(void * /*cbhdr*/, void * /*dir handler*/, char * /*dname*/, int /*dnameLen*/); + int (*closeDir)(void * /*cbhdr*/, void * /*dir handler*/); + + int (*openFile)(void * /*cbhdr*/, const char * /*pathname*/, int /*flags*/); + int (*accessFile)(void * /*cbhdr*/, const char * /*pathname*/, int /*mode*/); +}; + +struct BdmvExtraDataS +{ + struct IoOperationS *ioCb; + void *cbHdr; +}; +/*------------------------RTP end-------------------------------------*/ + +/*------------------------RTP stream header----------------------------*/ +typedef struct RtpStreamItfS RtpStreamItfT; +struct RtpStreamItfOpsS +{ + int (*filter)(RtpStreamItfT *, CdxBufferT * /*in*/, CdxListT ** /*out*/); + void (*destroy)(RtpStreamItfT *); +}; + +struct RtpStreamItfS +{ + struct RtpStreamItfOpsS *ops; +}; + +struct RtpStreamExtraDataS +{ + RtpStreamItfT *itf; + cdx_uint32 timeScale; + cdx_bool multicast; +}; +/*------------------------RTP end-------------------------------------*/ + +/*------------------------AES stream header----------------------------*/ +enum PaddingType +{ + CDX_PKCS7, +}; + +typedef struct AesStreamExtraDataS +{ + cdx_uint8 key[16]; + cdx_uint8 iv[16]; + enum PaddingType paddingType; + void *extraData; /* extra data for some stream, ex: http header for http stream */ + enum DSExtraDataTypeE extraDataType; +}AesStreamExtraDataT; +/*------------------------AES end------------------------------------*/ + +//***********************************************************// +//* Define IO status. +//***********************************************************// +enum CdxIOStateE +{ + CDX_IO_STATE_OK = 0, //* nothing wrong of the data accession. + CDX_IO_STATE_INVALID, + CDX_IO_STATE_ERROR, //* unknown error, can't access the media file. + CDX_IO_STATE_EOS, /*end of stream*/ + CDX_IO_STATE_CLEAR // for mms playlist +}; + +/*for stream->control*/ +enum CdxStreamCommandE +{ + STREAM_CMD_GET_DURATION = 0x101, + /* Get the duration of the media file. + *param is a pointer to a int64_t variable, duration = *(int64_t*)param. + *return 0 if OK, return -1 if not supported by the stream handler. + */ + + STREAM_CMD_READ_NOBLOCK = 0x102, + /* for sock recv in seek operation, return as soon as possible. + * return 0 if OK, return -1 if not support. + */ + + STREAM_CMD_GET_SOCKRECVBUFLEN = 0x103, + /* Get the socket recv buf len, *(cdx_int32*)param. + * return 0 if OK, return -1 if not support. + */ + /* To Add More commands here.*/ + + /* struct StreamCacheStateS */ + STREAM_CMD_GET_CACHESTATE = 0x104, + + STREAM_CMD_SET_FORCESTOP = 0x105, + /* Force stop the stream running job. */ + + STREAM_CMD_CLR_FORCESTOP = 0x106, + /* Resume the stream running job. */ + + STREAM_CMD_RESET_STREAM = 0x107, + /*for mms playlist*/ + + STREAM_CMD_EXT_IO_OPERATION = 0x108, + /*for bdmv io operation: opendir, readdir, closedir, open, access*/ + + STREAM_CMD_SET_CALLBACK = 0x109, + /*for setting callback*/ + STREAM_CMD_SET_ISHLS= 0x110, + /*for setting hls parser flag*/ + + STREAM_CMD_GET_IP = 0x110, + /* For get tcp ip*/ + STREAM_CMD_REQUEST_WRITE_INFO = 0x120, + STREAM_CMD_UPDATE_WRITE_INFO = 0x121, + STREAM_CMD_SET_EOF = 0x122, + STREAM_CMD_SET_RELATIVE_START_POS, + STREAM_CMD_SET_RELATIVE_FILE_SIZE, +}; + +/*stream event*/ +enum CdxStreamEventE +{ + STREAM_EVT_DOWNLOAD_START = STREAM_EVENT_VALID_RANGE_MIN, + STREAM_EVT_DOWNLOAD_END, + STREAM_EVT_DOWNLOAD_ERROR, + STREAM_EVT_NET_DISCONNECT, + STREAM_EVT_DOWNLOAD_RESPONSE_HEADER, + STREAM_EVT_DOWNLOAD_START_TIME, + STREAM_EVT_DOWNLOAD_FIRST_TIME, + STREAM_EVT_DOWNLOAD_END_TIME, + STREAM_EVT_DOWNLOAD_GET_TCP_IP, + STREAM_EVT_DOWNLOAD_DOWNLOAD_ERROR, + STREAM_EVT_CMCC_LOG_RECORD, + + STREAM_EVT_MAX, +}; +CHECK_STREAM_EVENT_MAX_VALID(STREAM_EVT_MAX) + +/* STREAM_CMD_EXT_IO_OPERATION param */ +enum ExtIoctlCmdE +{ + EXT_IO_OPERATION_OPENDIR = 0, + EXT_IO_OPERATION_READDIR, + EXT_IO_OPERATION_CLOSEDIR, + + EXT_IO_OPERATION_OPENFILE, + EXT_IO_OPERATION_READFILE, + EXT_IO_OPERATION_CLOSEFILE, + + EXT_IO_OPERATION_ACCESS, +}; + +struct ExtIoctlParamS +{ + int cmd; + + void *inHdr; /* (int)'dirId', (int)'fd', 'DIR *' */ + char *inPath; + + char *inBuf; + int inBufLen; + + void *outHdr; /* (int)'dirid', (int)'fd', 'DIR *' */ + int outRet; +}; + +typedef enum CdxIOStateE CdxIOStateT; +typedef enum CdxStreamCommandE CdxStreamCommandT; + +struct StreamCacheStateS +{ + cdx_int32 nCacheCapacity; + cdx_int32 nCacheSize; + cdx_int32 nBandwidthKbps; + cdx_int32 nPercentage; /* ((100 * download_offset)/totle_size)*/ +}; + +struct CdxStreamProbeDataS +{ + cdx_char *buf; + cdx_uint32 len; + + /* maybe we should define it as char private[0]? */ + cdx_char *uri[0]; +}; + +typedef int (*ParserCallback)(void* pUserData, int eMessageId, void* param); +struct CallBack +{ + ParserCallback callback; + void *pUserData; +}; + +typedef struct ContorlTaskS ContorlTask; +struct ContorlTaskS +{ + cdx_int32 cmd; + void *param; + ContorlTask *next; +}; +struct CdxStreamCreatorS +{ + CdxStreamT *(*create)(CdxDataSourceT *); +}; + +struct CdxStreamOpsS +{ + cdx_int32 (*connect)(CdxStreamT * /*stream*/); + + CdxStreamProbeDataT *(*getProbeData)(CdxStreamT * /*stream*/); + + cdx_int32 (*stream_read)(CdxStreamT * /*stream*/, void * /*buf*/, cdx_uint32 /*len*/); + + cdx_int32 (*stream_close)(CdxStreamT * /*stream*/); + + cdx_int32 (*getIOState)(CdxStreamT * /*stream*/); + + cdx_uint32 (*attribute)(CdxStreamT * /*stream*/); + + cdx_int32 (*control)(CdxStreamT * /*stream*/, cdx_int32 /*cmd*/, void * /*param*/); + + /*Ͻӿڱʵ*/ + + cdx_int32 (*stream_write)(CdxStreamT *, void * /*buf*/, cdx_uint32 /*len*/); + + cdx_int32 (*getMetaData)(CdxStreamT *, const cdx_char * /*key*/, void ** /*pVal*/); + + cdx_int32 (*seek)(CdxStreamT * /*stream*/, cdx_int64 /*offset*/, cdx_int32 /*whence*/); + + cdx_int32 (*seekToTime)(CdxStreamT * /*stream*/, cdx_int64 /*time us*/); + + cdx_bool (*eos)(CdxStreamT * /*stream*/); + + cdx_int64 (*tell)(CdxStreamT * /*stream*/); + + cdx_int64 (*size)(CdxStreamT * /*stream*/); + + //cdx_int32 (*forceStop)(CdxStreamT * /*stream*/); + + /*cut Size/CachedSize/SetBufferSize/GetBufferSize */ +}; + +struct CdxStreamS +{ + struct CdxStreamOpsS *ops; +}; + +int AwStreamRegister(CdxStreamCreatorT *creator, cdx_char *type); + +CdxStreamT *CdxStreamCreate(CdxDataSourceT *source); + +/**************************************************************************** + * Danger! Danger! Danger! + * + * CdxStreamOpen() includes two parts: create() and connect(). + * create(): It is (or should) nonblock, and unlikely to fail. + * connect(): It can block, and has a great chance to fail. + * + * After create() return, you can use the stream to force stop connect(). This + * is why we separate CdxStreamOpen() into two parts. + * + * So, you must call CdxStreamClose() even when CdxStreamOpen() failed. Or you + * will suffer from memory and file descriptor leak. Yes, it's pain in the ass! + * + ***************************************************************************/ +int CdxStreamOpen(CdxDataSourceT *source, pthread_mutex_t *mutex, cdx_bool *exit, + CdxStreamT **stream, ContorlTask *streamTasks); + +static inline cdx_int32 CdxStreamConnect(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->connect); + return stream->ops->connect(stream); +} + +static inline CdxStreamProbeDataT *CdxStreamGetProbeData(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->getProbeData); + return stream->ops->getProbeData(stream); +} + +static inline cdx_int32 CdxStreamRead(CdxStreamT *stream, void *buf, cdx_int32 len) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->stream_read); + return stream->ops->stream_read(stream, buf, len); +} + +static inline cdx_int32 CdxStreamWrite(CdxStreamT *stream, void *buf, cdx_int32 len) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->stream_write ? stream->ops->stream_write(stream, buf, len) : -1; +} + +static inline cdx_int32 CdxStreamClose(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->stream_close); + return stream->ops->stream_close(stream); +} + +static inline cdx_int32 CdxStreamGetIoState(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->getIOState); + return stream->ops->getIOState(stream); +} + +static inline cdx_uint32 CdxStreamAttribute(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->attribute); + return stream->ops->attribute(stream); +} + +static inline cdx_int32 CdxStreamControl(CdxStreamT *stream, + cdx_int32 cmd, void *param) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + CDX_CHECK(stream->ops->control); + return stream->ops->control(stream, cmd, param); +} + +//#define STREAM_METADATA_ORGINAL_URI "stream.orginalUri" +#define STREAM_METADATA_REDIRECT_URI "stream.redirectUri" +#define STREAM_METADATA_ACCESSIBLE_URI "stream.accessibleUri" + +static inline cdx_int32 CdxStreamGetMetaData(CdxStreamT *stream, + const cdx_char *key, void **pVal) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + return stream->ops->getMetaData ? + stream->ops->getMetaData(stream, key, pVal) : + -1; +} + +static inline cdx_int32 CdxStreamSeek(CdxStreamT *stream, cdx_int64 offset, + cdx_int32 whence) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->seek ? stream->ops->seek(stream, offset, whence) : -1; +} + +static inline cdx_int32 CdxStreamSeekToTime(CdxStreamT *stream, cdx_int64 timeUs) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->seekToTime ? stream->ops->seekToTime(stream, timeUs) : -1; +} + +static inline cdx_bool CdxStreamEos(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->eos ? stream->ops->eos(stream) : CDX_FALSE; +} + +static inline cdx_int64 CdxStreamTell(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->tell ? stream->ops->tell(stream) : -1; +} +/* +CDX_INTERFACE cdx_int32 CdxStreamForceStop(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->forceStop ? stream->ops->forceStop(stream) : -1; +} +*/ + +static inline cdx_int64 CdxStreamSize(CdxStreamT *stream) +{ + CDX_CHECK(stream); + CDX_CHECK(stream->ops); + + return stream->ops->size ? stream->ops->size(stream) : (-1LL); +} + +#define CdxStreamSeekAble(stream) \ + (!!(CdxStreamAttribute(stream) & CDX_STREAM_FLAG_SEEK)) + +#define CdxStreamIsNetStream(stream) \ + (!!(CdxStreamAttribute(stream) & CDX_STREAM_FLAG_NET)) + +#define CdxStreamForceStop(stream) \ + (CdxStreamControl(stream, STREAM_CMD_SET_FORCESTOP, NULL)) + +#define CdxStreamClrForceStop(stream) \ + (CdxStreamControl(stream, STREAM_CMD_CLR_FORCESTOP, NULL)) + +#define CdxStreamIsDtmbStream(stream) \ + (!!(CdxStreamAttribute(stream) & CDX_STREAM_FLAG_DTMB)) + +static inline cdx_int32 CdxStreamSkip(CdxStreamT *stream, cdx_uint32 len) +{ + if (len == 0) + { + return 0; + } + if (CdxStreamSeekAble(stream)) + { + return CdxStreamSeek(stream, (cdx_int64)len, STREAM_SEEK_CUR); + } + else + { + cdx_int32 ret = 0; + int i = 0, skipSize = 0, unitSize = 0; + cdx_char dummyBuf[512]; + if (len > 512 * 10) + { + CDX_LOGE("too large(%u) to dummy for a unseekable stream", len); + return -1; + } + + skipSize = len; + for (i = 0; i < 10; i++) + { + unitSize = (skipSize > 512) ? 512 : skipSize; + ret = CdxStreamRead(stream, dummyBuf, unitSize); + if (ret != unitSize) + { + return -1; + } + skipSize -= ret; + if (skipSize == 0) + { + break; + } + } + return CDX_SUCCESS; + } +} + +#define CdxStreamGetU8(stream) \ + ({cdx_uint8 data; CdxStreamRead(stream, &data, 1); GetU8(&data);}) + +#define CdxStreamGetLE16(stream) \ + ({cdx_uint8 data[2]; CdxStreamRead(stream, data, 2); GetLE16(data);}) + +#define CdxStreamGetLE32(stream) \ + ({cdx_uint8 data[4]; CdxStreamRead(stream, data, 4); GetLE32(data);}) + +#define CdxStreamGetLE64(stream) \ + ({cdx_uint8 data[8]; CdxStreamRead(stream, data, 8); GetLE64(data);}) + +#define CdxStreamGetBE16(stream) \ + ({cdx_uint8 data[2]; CdxStreamRead(stream, data, 2); GetBE16(data);}) + +#define CdxStreamGetBE32(stream) \ + ({cdx_uint8 data[4]; CdxStreamRead(stream, data, 4); GetBE32(data);}) + +#define CdxStreamGetBE64(stream) \ + ({cdx_uint8 data[8]; CdxStreamRead(stream, data, 8); GetBE64(data);}) + +typedef struct REQUEST_BUFFER_INFO +{ + unsigned char* bufPtr; + unsigned int bufLen; +}StreamBufferInfo; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/stream/include/CdxStreamErrno.h b/platform/mcu/xr871/src/cedarx/stream/include/CdxStreamErrno.h new file mode 100644 index 0000000000..21abd4c1fa --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/stream/include/CdxStreamErrno.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. + * All rights reserved. + * + * File : CdxStreamErrno.h + * Description : StreamErrno + * History : + * + */ + +#ifndef CDX_STREAM_ERRNO_H +#define CDX_STREAM_ERRNO_H + +enum CdxStreamErrno +{ + CEDARX_STREAM_ERR_BASE = 0x04670000, + /*㶨ģÿģӦͳһ*/ + CEDARX_STREAM_ERR_REGISTER, + CEDARX_STREAM_ERR_NOT_REGISTER, + CEDARX_STREAM_ERR_CONN_TIMEOUT, + CEDARX_STREAM_ERR_PARAMETER_INVAILD, +}; + +#endif diff --git a/platform/mcu/xr871/src/cedarx/xplayer/cache.h b/platform/mcu/xr871/src/cedarx/xplayer/cache.h new file mode 100644 index 0000000000..1351399781 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/xplayer/cache.h @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : cache.h +* Description : cache policy for net stream +* History : +* Author : AL3 +* Date : 2015/05/05 +* Comment : first version +* +*/ + +#ifndef CACHE_H +#define CACHE_H + +//#include +#include +#include +#include "CdxParser.h" +#if VIDEO_SUPPORT +#include "vdecoder.h" +#endif +#include "player.h" + +#define likely(p) __builtin_expect(!!(p), 1) +#define unlikely(p) __builtin_expect(!!(p), 0) + +typedef struct CacheNode_t CacheNode; +struct CacheNode_t +{ + unsigned char* pData; + int nLength; + int64_t nPts; + int64_t nPcr; + int bIsFirstPart; + int bIsLastPart; + int eMediaType; + int nStreamIndex; + int nFlags; + int64_t nDuration; + int infoVersion; + void* info; + CacheNode* pNext; +}; + +typedef struct StreamCache_t +{ + pthread_mutex_t mutex; + int nMaxBufferSize; + int nStartPlaySize; + + int nDataSize; + int nFrameNum; +#if VIDEO_SUPPORT + int nVideoFrameNum; +#endif + CacheNode* pHead; + CacheNode* pTail; + + int nPassedDataSize; + int nPassedFrameNum; +#if VIDEO_SUPPORT + int nPassedVideoFrameNum; +#endif + CacheNode* pPassedHead; + + int64_t nLastValidPts; + CacheNode* pNodeWithLastValidPts; + int64_t nLastValidPcr; + CacheNode* pNodeWithLastValidPcr; + int64_t nFirstPts; + + int nBitrate; //* for ts/m2ts stream seek processing. + Player* pPlayer; //* for ts/m2ts stream seek processing. + CdxParserTypeT eContainerFormat; //* for seek processing. +#if VIDEO_SUPPORT + enum EVIDEOCODECFORMAT eVideoCodecFormat; //* for finding key frame in cache when seek. +#endif +}StreamCache; + +StreamCache* StreamCacheCreate(void); + +void StreamCacheDestroy(StreamCache* c); + +void StreamCacheSetSize(StreamCache* c, int nStartPlaySize, int nMaxBufferSize); + +int StreamCacheGetSize(StreamCache* c); + +int StreamCacheUnderflow(StreamCache* c); + +int StreamCacheOverflow(StreamCache* c); + +int StreamCacheDataEnough(StreamCache* c); + +CacheNode* StreamCacheNextFrame(StreamCache* c); + +void StreamCacheFlushOneFrame(StreamCache* c); + +int StreamCacheAddOneFrame(StreamCache* c, CacheNode* node); + +void StreamCacheFlushAll(StreamCache* c); + +int StreamCacheGetBufferFullness(StreamCache* c); + +int StreamCacheGetLoadingProgress(StreamCache* c); + +int StreamCacheSetMediaFormat(StreamCache* c, + CdxParserTypeT eContainerFormat, +#if VIDEO_SUPPORT + enum EVIDEOCODECFORMAT eVideoCodecFormat, +#else + int eVideoCodecFormat, +#endif + int nBitrate); + +int StreamCacheSetPlayer(StreamCache* c, Player* pPlayer); + +int64_t StreamCacheSeekTo(StreamCache* c, int64_t nSeekTimeUs); + +#endif diff --git a/platform/mcu/xr871/src/cedarx/xplayer/demuxComponent.h b/platform/mcu/xr871/src/cedarx/xplayer/demuxComponent.h new file mode 100644 index 0000000000..ee498102da --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/xplayer/demuxComponent.h @@ -0,0 +1,159 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : demuxComponent.h +* Description : stream control and video stream demux +* History : +* Author : AL3 +* Date : 2015/05/05 +* Comment : first version +* +*/ + +#ifndef DEMUX_COMPONENT_H +#define DEMUX_COMPONENT_H + +#if 0 +#include +#include +#include +#include +#include +#endif + +#include "player.h" //* player library in "android/hardware/aw/" +#include "mediaInfo.h" +#include + +typedef void* DemuxComp; + +#define SOURCE_TYPE_URL 0x1 +#define SOURCE_TYPE_FD 0x2 +#define SOURCE_TYPE_ISTREAMSOURCE 0x3 + +enum EDEMUXNOTIFY //* player internal notify. +{ + DEMUX_NOTIFY_PREPARED = DEMUX_NOTIFY_VALID_RANGE_MIN, + DEMUX_NOTIFY_EOS, + DEMUX_NOTIFY_IOERROR, + DEMUX_NOTIFY_RESET_PLAYER, + DEMUX_NOTIFY_SEEK_FINISH, + DEMUX_NOTIFY_CACHE_STAT, + DEMUX_NOTIFY_BUFFER_START, + DEMUX_NOTIFY_BUFFER_END, + DEMUX_NOTIFY_PAUSE_PLAYER, + DEMUX_NOTIFY_RESUME_PLAYER, + + DEMUX_IOREQ_ACCESS, + DEMUX_IOREQ_OPEN, + DEMUX_IOREQ_OPENDIR, + DEMUX_IOREQ_READDIR, + DEMUX_IOREQ_CLOSEDIR, + DEMUX_VIDEO_STREAM_CHANGE, + DEMUX_AUDIO_STREAM_CHANGE, + + //for cmcc + DEMUX_NOTIFY_HLS_DOWNLOAD_START, + DEMUX_NOTIFY_HLS_DOWNLOAD_ERROR, + DEMUX_NOTIFY_HLS_DOWNLOAD_END, + + //* CMCC 2.1.7.12-m3 log + DEMUX_NOTIFY_LOG_RECORDER, + + // for timeShift end + DEMUX_NOTIFY_TIMESHIFT_DURATION, + DEMUX_NOTIFY_METADATA, + DEMUX_NOTIFY_MAX, +}; +CHECK_DEMUX_NOTIFY_MAX_VALID(DEMUX_NOTIFY_MAX) + +enum EDEMUXERROR +{ + DEMUX_ERROR_NONE = 0, + DEMUX_ERROR_UNKNOWN = -1, + DEMUX_ERROR_IO = -2, + DEMUX_ERROR_USER_CANCEL = -3, +}; + +enum ECACHEPOLICY +{ + CACHE_POLICY_ADAPTIVE = 0, + CACHE_POLICY_SMOOTH = 2, +}; + +typedef int (*DemuxCallback)(void* pUserData, int eMessageId, void* param); + +DemuxComp* DemuxCompCreate(void); + +void DemuxCompDestroy(DemuxComp* d); + +void DemuxCompClear(DemuxComp* d); //* clear the data source, like just created. + +int DemuxCompSetUrlSource(DemuxComp* d, void* pHTTPServer, + const char* pUrl, const CdxKeyedVectorT* pHeaders); + +int DemuxCompSetFdSource(DemuxComp* d, int fd, int64_t nOffset, int64_t nLength); + +int DemuxCompSetStreamSource(DemuxComp* d, const char* pUri); + +int DemuxCompSetPlayer(DemuxComp* d, Player* player); + +int DemuxCompSetHdcpOps(DemuxComp* d, struct HdcpOpsS* pHdcp); + +int DemuxCompSetCallback(DemuxComp* d, DemuxCallback callback, void* pUserData); + +int DemuxCompPrepareAsync(DemuxComp* d); + +int DemuxCompCancelPrepare(DemuxComp* d); //* should call back DEMUX_PREPARE_FINISH message. + +#if VIDEO_SUPPORT +int DemuxProbeH265RefPictureNumber(char* pDataBuf, int nDataLen); +#endif + +MediaInfo* DemuxCompGetMediaInfo(DemuxComp* d); + +int DemuxCompStart(DemuxComp* d); + +int DemuxCompStop(DemuxComp* d); //* close the data source, must call prepare again to restart. + +int DemuxCompPause(DemuxComp* d); //* no pause status in demux component, return OK immediately. + +int DemuxCompGetStatus(DemuxComp* d); + +int DemuxCompSeekTo(DemuxComp* d, int nSeekTimeMs); + +int DemuxCompCancelSeek(DemuxComp* d); //* should not call back DEMUX_SEEK_FINISH message. + +int DemuxCompNotifyFirstFrameShowed(DemuxComp* d); //* notify video first frame showed. + +#if ONLINE_SUPPORT +int DemuxCompSetCacheStatReportInterval(DemuxComp* d, int ms); + +int DemuxCompSetCachePolicy(DemuxComp* d, + enum ECACHEPOLICY eCachePolicy, + int nStartPlaySize, + int nStartPlayTimeMs, + int nMaxBufferSize); +#endif + +#if SECURE_BUFFER_SUPPORT +int DemuxCompSetSecureBufferCount(DemuxComp* d, void* param); + +int DemuxCompSetSecureBuffers(DemuxComp* d,void* param); +#endif + +int DemuxCompSeekToResetUrl(DemuxComp* d, int nSeekTimeMs); + +int DemuxCompGetLiveMode(DemuxComp* d); + +int DemuxCompSetLiveMode(DemuxComp* d, int liveMode); + +#if ONLINE_SUPPORT +int DemuxCompGetCacheSize(DemuxComp* d); +#endif + +int DemuxCompSetHdcpOps(DemuxComp* d, struct HdcpOpsS* pHdcpOps); + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/xplayer/include/mediaInfo.h b/platform/mcu/xr871/src/cedarx/xplayer/include/mediaInfo.h new file mode 100644 index 0000000000..8156fd2508 --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/xplayer/include/mediaInfo.h @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : mediainfo.h +* Description : media infomation +* History : +* Author : AL3 +* Date : 2015/05/05 +* Comment : first version +* +*/ + +#ifndef MEDIA_INFO_H +#define MEDIA_INFO_H + +#include "player.h" //* player library in "LIBRARY/PLAYER/" +#include "CdxParser.h" //* parser library in "LIBRARY/DEMUX/PARSER/include/" + +#define WIDTH_4K 3840 +#define HEIGHT_4K 2160 +#define WIDTH_1080P 1920 +#define HEIGHT_1080P 1080 + +enum ECONTAINER +{ + CONTAINER_TYPE_MOV = CDX_PARSER_MOV, + CONTAINER_TYPE_MKV = CDX_PARSER_MKV, + CONTAINER_TYPE_ASF = CDX_PARSER_ASF, + CONTAINER_TYPE_MPG = CDX_PARSER_MPG, + CONTAINER_TYPE_TS = CDX_PARSER_TS, + CONTAINER_TYPE_AVI = CDX_PARSER_AVI, + CONTAINER_TYPE_FLV = CDX_PARSER_FLV, + CONTAINER_TYPE_PMP = CDX_PARSER_PMP, + + CONTAINER_TYPE_HLS = CDX_PARSER_HLS, + CONTAINER_TYPE_DASH = CDX_PARSER_DASH, + CONTAINER_TYPE_MMS = CDX_PARSER_MMS, + CONTAINER_TYPE_BD = CDX_PARSER_BD, + CONTAINER_TYPE_OGG = CDX_PARSER_OGG, + CONTAINER_TYPE_M3U9 = CDX_PARSER_M3U9, + CONTAINER_TYPE_RMVB = CDX_PARSER_RMVB, + CONTAINER_TYPE_PLAYLIST = CDX_PARSER_PLAYLIST, + CONTAINER_TYPE_WAV = CDX_PARSER_WAV, + CONTAINER_TYPE_APE = CDX_PARSER_APE, + CONTAINER_TYPE_AMR = CDX_PARSER_AMR, + CONTAINER_TYPE_ATRAC = CDX_PARSER_ATRAC, + CONTAINER_TYPE_MP3 = CDX_PARSER_MP3, + CONTAINER_TYPE_DTS = CDX_PARSER_DTS, + CONTAINER_TYPE_AC3 = CDX_PARSER_AC3, + CONTAINER_TYPE_AAC = CDX_PARSER_AAC, + CONTAINER_TYPE_WVM = CDX_PARSER_WVM, + //* multiple stream source of media es stream, such as rtsp. + CONTAINER_TYPE_RTSP = CDX_PARSER_REMUX, + CONTAINER_TYPE_MMSHTTP = CDX_PARSER_MMSHTTP, + + CONTAINER_TYPE_UNKNOWN = 0x100, + CONTAINER_TYPE_RAW = 0x101, +}; + +typedef struct MEDIAINFO +{ + int64_t nFileSize; + int64_t nDurationMs; + int nBitrate; + unsigned char cRotation[4]; + int64_t nFirstPts; + + enum ECONTAINER eContainerType; + int bSeekable; +#if VIDEO_SUPPORT + int nVideoStreamNum; +#endif + int nAudioStreamNum; +#if SUBTITLE_SUPPORT + int nSubtitleStreamNum; +#endif + +#if VIDEO_SUPPORT + VideoStreamInfo* pVideoStreamInfo; +#endif + AudioStreamInfo* pAudioStreamInfo; +#if SUBTITLE_SUPPORT + SubtitleStreamInfo* pSubtitleStreamInfo; +#endif +}MediaInfo; + +#endif + diff --git a/platform/mcu/xr871/src/cedarx/xplayer/include/xplayer.h b/platform/mcu/xr871/src/cedarx/xplayer/include/xplayer.h new file mode 100644 index 0000000000..994d25689c --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/xplayer/include/xplayer.h @@ -0,0 +1,233 @@ +/* +* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd. +* All rights reserved. +* +* File : xplayer.h +* Description : xplayer +* History : +* Author : AL3 +* Date : 2015/05/05 +* Comment : first version +* +*/ + +#ifndef XPLAYER_H +#define XPLAYER_H + +//#include +//#include +#include "pthread.h" +#include +#include "CdxKeyedVector.h" +//#include "cdx_config.h" //* configuration file in "LiBRARY/" +#include "mediaInfo.h" +#include + +#define AWPLAYER_CONFIG_DISABLE_VIDEO 1 +#define AWPLAYER_CONFIG_DISABLE_AUDIO 0 +#define AWPLAYER_CONFIG_DISABLE_SUBTITLE 1 +#define AWPLAYER_CONFIG_DISALBE_MULTI_AUDIO 0 + +#ifdef __cplusplus +extern "C" { +#endif + +/* Since xplayer is operating system independent, there is no benefit and no + * simple method to keep items in MediaEventType have the same value as items + * in media_event_type of Android. + */ +enum MediaEventType { + AWPLAYER_MEDIA_NOP = MEDIA_EVENT_VALID_RANGE_MIN, // = 0, interface test message + AWPLAYER_MEDIA_PREPARED, + AWPLAYER_MEDIA_PLAYBACK_COMPLETE, + AWPLAYER_MEDIA_BUFFERING_UPDATE, + AWPLAYER_MEDIA_SEEK_COMPLETE, + AWPLAYER_MEDIA_SET_VIDEO_SIZE, + AWPLAYER_MEDIA_STARTED, + AWPLAYER_MEDIA_PAUSED, + AWPLAYER_MEDIA_STOPPED, + AWPLAYER_MEDIA_SKIPPED, + AWPLAYER_MEDIA_TIMED_TEXT, + AWPLAYER_MEDIA_ERROR, + AWPLAYER_MEDIA_INFO, + AWPLAYER_MEDIA_SUBTITLE_DATA, + + AWPLAYER_MEDIA_LOG_RECORDER, + + AWPLAYER_EXTEND_MEDIA_INFO, + AWPLAYER_MEDIA_META_DATA, + AWPLAYER_MEDIA_EVENT_MAX, +}; +CHECK_MEDIA_EVENT_MAX_VALID(AWPLAYER_MEDIA_EVENT_MAX) + +// av/include/media/mediaplayer.h +enum MediaInfoType +{ + AW_MEDIA_INFO_UNKNOWN = 1, + AW_MEDIA_INFO_STARTED_AS_NEXT = 2, + AW_MEDIA_INFO_RENDERING_START = 3, + AW_MEDIA_INFO_BUFFERING_START = 701, + AW_MEDIA_INFO_BUFFERING_END = 702, + + AW_MEDIA_INFO_NOT_SEEKABLE = 801, + + AW_MEDIA_INFO_DOWNLOAD_START = 10086, + AW_MEDIA_INFO_DOWNLOAD_END = 10087, + AW_MEDIA_INFO_DOWNLOAD_ERROR = 10088, +}; + +enum ExMediaInfoType +{ + AW_EX_IOREQ_ACCESS = 1, + AW_EX_IOREQ_OPEN = 2, + AW_EX_IOREQ_OPENDIR = 3, + AW_EX_IOREQ_READDIR = 4, + AW_EX_IOREQ_CLOSEDIR = 5, +}; + + +// 0xx: Reserved +// 1xx: Android Player errors. Something went wrong inside the MediaPlayer. +// 2xx: Media errors (e.g Codec not supported). There is a problem with the +// media itself. +// 3xx: Runtime errors. Some extraordinary condition arose making the playback +// impossible. +// +enum MediaErrorType +{ + // 0xx + AW_MEDIA_ERROR_UNKNOWN = 1, + // 1xx + AW_MEDIA_ERROR_SERVER_DIED = 100, + // 2xx + AW_MEDIA_ERROR_NOT_VALID_FOR_PROGRESSIVE_PLAYBACK = 200, + // 3xx + // 9xx + AW_MEDIA_ERROR_OUT_OF_MEMORY = 900, + // 4xx + AW_MEDIA_ERROR_IO = -1004, + AW_MEDIA_ERROR_MALFORMED = -1007, + AW_MEDIA_ERROR_UNSUPPORTED = -1010, + AW_MEDIA_ERROR_TIMED_OUT = -110, +}; + + +typedef enum AwApplicationType { + APP_DEFAULT, + APP_STREAMING, // for miracast and so on + APP_CMCC_WASU, + APP_CMCC_LOCAL, +} AwApplicationType; + +typedef int (*XPlayerNotifyCallback)(void* pUser, + int msg, int ext1, void* para); + +typedef struct XPlayerConfig_t { + AwApplicationType appType; + int livemode; +} XPlayerConfig_t; + +typedef enum XPlayerTimeoutType { + XPLAYER_PLAYBACK_TIMEOUT, + XPLAYER_PREPARE_TIMEOUT, +} XPlayerTimeoutType; + +typedef struct PlayerContext XPlayer; + +XPlayer* XPlayerCreate(); + +void XPlayerDestroy(XPlayer* p); + +int XPlayerConfig(XPlayer* p, const XPlayerConfig_t *config); + +int XPlayerSetNotifyCallback(XPlayer* p, + XPlayerNotifyCallback notifier, + void* pUserData); + +int XPlayerInitCheck(XPlayer* p); + +int XPlayerSetUID(XPlayer* p, int nUid); + +//* we must set hdcp ops before setDataSource +int XPlayerSetHdcpOps(XPlayer* p, struct HdcpOpsS* pHdcp); + +int XPlayerSetDataSourceUrl(XPlayer* p, const char* pUrl, + void* httpService, const CdxKeyedVectorT* pHeaders); + +int XPlayerSetDataSourceFd(XPlayer* p, int fd, + int64_t nOffset, int64_t nLength); + +// for IStreamSource in android +int XPlayerSetDataSourceStream(XPlayer* p, const char* pStreamUri); + +int XPlayerPrepare(XPlayer* p); + +int XPlayerPrepareAsync(XPlayer* p); + +int XPlayerStart(XPlayer* p); + +int XPlayerStop(XPlayer* p); + +int XPlayerPause(XPlayer* p); + +int XPlayerIsPlaying(XPlayer* p); + +int XPlayerSeekTo(XPlayer* p, int nSeekTimeMs); + +int XPlayerSetSpeed(XPlayer* p, int nSpeed); + +int XPlayerGetCurrentPosition(XPlayer* p, int* msec); + +int XPlayerGetDuration(XPlayer* p, int* msec); + +int XPlayerReset(XPlayer* p); + +int XPlayerSetLooping(XPlayer* p, int bLoop); + +/* + Recommand prepare timeout is multi-times to playback timeout, and + playback timeout is over 100ms. +*/ +int XPlayerSetTimeout(XPlayer* p, XPlayerTimeoutType type, int timeout_ms); + +#if SUBTITLE_SUPPORT +int XPlayerGetSubDelay(XPlayer* p); + +int XPlayerSetSubDelay(XPlayer* p, int nTimeMs); + +int XPlayerGetSubCharset(XPlayer* p, char *charset); + +int XPlayerSetSubCharset(XPlayer* p, const char* strFormat); + +void XPlayerSetSubCtrl(XPlayer* p, const SubCtrl* subctrl); + +int XPlayerSwitchSubtitle(XPlayer* pl, int nStreamIndex); + +int XPlayerSetExternalSubUrl(XPlayer* p, const char* fileName); + +int XPlayerSetExternalSubFd(XPlayer* p, int fd, int64_t offset, int64_t len, int fdSub); +#endif + +#if VIDEO_SUPPORT +int XPlayerSetVideoSurfaceTexture(XPlayer* p, const LayerCtrl* surfaceTexture); +#endif + +void XPlayerSetAudioSink(XPlayer* p, const SoundCtrl* audioSink); + +#if VIDEO_SUPPORT +void XPlayerSetDeinterlace(XPlayer* p, const Deinterlace* di); +#endif + +MediaInfo* XPlayerGetMediaInfo(XPlayer* p); + +int XPlayerSwitchAudio(XPlayer* p, int nStreamIndex); + +int XPlayerGetPlaybackSettings(XPlayer* p,XAudioPlaybackRate *rate); + +int XPlayerSetPlaybackSettings(XPlayer* p,const XAudioPlaybackRate *rate); + +#ifdef __cplusplus +} +#endif + +#endif // AWPLAYER diff --git a/platform/mcu/xr871/src/cedarx/xrecoder/include/xrecord.h b/platform/mcu/xr871/src/cedarx/xrecoder/include/xrecord.h new file mode 100644 index 0000000000..e97533fa2d --- /dev/null +++ b/platform/mcu/xr871/src/cedarx/xrecoder/include/xrecord.h @@ -0,0 +1,47 @@ +#ifndef XRECORD_H +#define XRECORD_H + +#include "CdxKeyedVector.h" +#include "CaptureControl.h" + + +#define AUDIO_INPUT (1) +#define VIDEO_INPUT (0) + +typedef struct RecoderContext XRecord; + +typedef enum XRECODER_AUDIO_ENCODE_TYPE +{ + XRECODER_AUDIO_ENCODE_AMR_TYPE, + XRECODER_AUDIO_ENCODE_PCM_TYPE, +} XRECODER_AUDIO_ENCODE_TYPE; + +typedef enum +{ + XRECODER_STATE_INIT, + XRECODER_STATE_PREPARED, + XRECODER_STATE_STARTED, + XRECODER_STATE_STOPED, + XRECODER_STATE_DESTROYED, +} XRECODER_STATE; + +XRecord* XRecordCreate(); + +int XRecordSetDataDstUrl(XRecord* p, + const char* pUrl, + void* arg, + const CdxKeyedVectorT* pHeaders); + +int XRecordDestroy(XRecord* p); + +void XRecordSetAudioCap(XRecord* p, const CaptureCtrl* audioSrc); + +int XRecordSetAudioEncodeType(XRecord* p, XRECODER_AUDIO_ENCODE_TYPE type, AudioEncodeConfig *config); + +int XRecordPrepare(XRecord* p); + +int XRecordStart(XRecord* p); + +int XRecordStop(XRecord* p); + +#endif /* XRECORD_H */ \ No newline at end of file diff --git a/platform/mcu/xr871/src/console/Makefile b/platform/mcu/xr871/src/console/Makefile new file mode 100644 index 0000000000..a9dfc86a0c --- /dev/null +++ b/platform/mcu/xr871/src/console/Makefile @@ -0,0 +1,24 @@ +# +# Rules for building library +# + +# ---------------------------------------------------------------------------- +# common rules +# ---------------------------------------------------------------------------- +ROOT_PATH := ../.. + +include $(ROOT_PATH)/gcc.mk + +# ---------------------------------------------------------------------------- +# library and objects +# ---------------------------------------------------------------------------- +LIBS := libconsole.a + +DIRS := . + +SRCS := $(basename $(foreach dir,$(DIRS),$(wildcard $(dir)/*.[csS]))) + +OBJS := $(addsuffix .o,$(SRCS)) + +# library make rules +include $(LIB_MAKE_RULES) diff --git a/platform/mcu/xr871/src/console/console.c b/platform/mcu/xr871/src/console/console.c new file mode 100644 index 0000000000..d7f9d8559f --- /dev/null +++ b/platform/mcu/xr871/src/console/console.c @@ -0,0 +1,396 @@ +/** + * @file console.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "kernel/os/os.h" +#include "console/console.h" +#include "console_debug.h" + + +#define CONSOLE_EMPTY_CMD_SUPPORT 1 + +#define CONSOLE_CMD_LINE_MAX_LEN 256 +#define CONSOLE_CMD_LINE_BUF_NUM 2 + +typedef enum { + CONSOLE_STATE_STOP = 0, + CONSOLE_STATE_START, + CONSOLE_STATE_TERMINATE, /* to be terminated */ +} console_state; + +static uint8_t g_console_buf[CONSOLE_CMD_LINE_BUF_NUM * CONSOLE_CMD_LINE_MAX_LEN]; + +typedef struct console_priv { + UART_ID uart_id; + console_state state; + + uint8_t free_buf_bitmap[CONSOLE_CMD_LINE_BUF_NUM]; + uint8_t ready_buf_bitmap[CONSOLE_CMD_LINE_BUF_NUM]; + uint8_t last_cmd_buf_idx; + uint8_t rx_buf_idx; + uint32_t rx_data_cnt; + + uint8_t *buf[CONSOLE_CMD_LINE_BUF_NUM]; + + OS_Semaphore_t cmd_sem; + + console_cmd_exec_func cmd_exec; +} console_priv_t; + +static console_priv_t g_console; + +#define CONSOLE_SET_BUF_BITMAP_VALID(bitmap, idx) ((bitmap)[idx] = 1) +#define CONSOLE_SET_BUF_BITMAP_INVALID(bitmap, idx) ((bitmap)[idx] = 0) +#define CONSOLE_IS_BUF_BITMAP_VALID(bitmap, idx) ((bitmap)[idx] == 1) + +#define CONSOLE_INVALID_BUF_IDX CONSOLE_CMD_LINE_BUF_NUM + +#define CONSOLE_BUF(console, buf_idx) ((console)->buf[buf_idx]) + + +static uint8_t console_get_valid_buf_idx(uint8_t *bitmap, uint8_t last_idx) +{ + uint8_t loop = CONSOLE_CMD_LINE_BUF_NUM; + uint8_t idx = last_idx; + + while (loop > 0) { + idx = (idx + 1) % CONSOLE_CMD_LINE_BUF_NUM; + if (CONSOLE_IS_BUF_BITMAP_VALID(bitmap, idx)) { + CONSOLE_SET_BUF_BITMAP_INVALID(bitmap, idx); + return idx; + } + --loop; + } + + return CONSOLE_INVALID_BUF_IDX; +} + +/* called after receive a valid command line */ +static __inline void console_rx_cmdline(console_priv_t *console) +{ + /* buf state change: rx --> ready */ + CONSOLE_SET_BUF_BITMAP_VALID(console->ready_buf_bitmap, console->rx_buf_idx); + + /* try to get a new rx buf from free list */ + console->rx_buf_idx = console_get_valid_buf_idx(console->free_buf_bitmap, + console->rx_buf_idx); + console->rx_data_cnt = 0; + + /* notify console task that a new command is ready */ + OS_SemaphoreRelease(&console->cmd_sem); +} + +/* Note: only support line end with "\r\n" or "\n", not support "\r" */ +static void console_rx_callback(void *arg) +{ + console_priv_t *console; + UART_T *uart; + uint8_t *rx_buf; + uint32_t cnt; + uint8_t data; + + uart = (UART_T *)arg; + console = &g_console; + + if (console->rx_buf_idx != CONSOLE_INVALID_BUF_IDX) { +retry: + rx_buf = CONSOLE_BUF(console, console->rx_buf_idx); + cnt = console->rx_data_cnt; + rx_buf += cnt; + + while (cnt < CONSOLE_CMD_LINE_MAX_LEN) { + if (HAL_UART_IsRxReady(uart)) { + data = HAL_UART_GetRxData(uart); + if (data == '\n') { /* command line end */ + if (cnt > 0 && (*(rx_buf - 1)) == '\r') { /* skip last '\r' */ + --rx_buf; + --cnt; + } +#if (!CONSOLE_EMPTY_CMD_SUPPORT) + if (cnt > 0) +#endif + { /* valid command */ + *rx_buf = '\0'; /* C style string */ + CONS_DBG("rx cmd (%u char): '%s'\n", cnt, + CONSOLE_BUF(console, console->rx_buf_idx)); +#if CONS_CHECK_OVERFLOW + if (rx_buf - CONSOLE_BUF(console, console->rx_buf_idx) + >= CONSOLE_CMD_LINE_MAX_LEN) { + CONS_ERR("rx buf %d overflow\n", console->rx_buf_idx); + } +#endif + console_rx_cmdline(console); + return; + } + } else { + if (isprint(data) || (data == '\r')) { /* valid char */ + *rx_buf = data; +#if CONS_CHECK_OVERFLOW + if (rx_buf - CONSOLE_BUF(console, console->rx_buf_idx) + >= CONSOLE_CMD_LINE_MAX_LEN) { + CONS_ERR("rx buf %d overflow\n", console->rx_buf_idx); + } +#endif + ++rx_buf; + ++cnt; + } else { /* invalid char */ + CONS_DBG("rx illegal char 0x%x\n", data); + console->rx_data_cnt = 0; /* reset rx buffer */ + goto retry; + } + } + } else { + break; /* no more data */ + } + } + + if (cnt >= CONSOLE_CMD_LINE_MAX_LEN) { + /* rx buffer full but no valid command */ + console->rx_data_cnt = 0; /* reset rx buffer */ + CONS_DBG("cmd too long, max %d\n", CONSOLE_CMD_LINE_MAX_LEN - 1); + goto retry; + } + console->rx_data_cnt = cnt; + } else { + CONS_WARN("no buf for rx, discard received data\n"); + while (HAL_UART_IsRxReady(uart)) { + HAL_UART_GetRxData(uart); + } + } +} + +#define CONSOLE_THREAD_STACK_SIZE (2 * 1024) +static OS_Thread_t g_console_thread; + +static void console_task(void *arg) +{ + uint8_t cmd_buf_idx; + uint8_t *cmd_buf; + console_priv_t *console; + + CONS_DBG("%s() start...\n", __func__); + + console = &g_console; + + while (1) { + if (OS_SemaphoreWait(&console->cmd_sem, OS_WAIT_FOREVER) != OS_OK) + continue; + + if (console->state != CONSOLE_STATE_START) + break; + + arch_irq_disable(); + cmd_buf_idx = console_get_valid_buf_idx(console->ready_buf_bitmap, + console->last_cmd_buf_idx); + arch_irq_enable(); + + if (cmd_buf_idx != CONSOLE_INVALID_BUF_IDX) { + cmd_buf = CONSOLE_BUF(console, cmd_buf_idx); + + CONS_DBG("exec cmd (idx %d): '%s'\n", cmd_buf_idx, cmd_buf); + if (console->cmd_exec) + console->cmd_exec((char *)cmd_buf); + + console->last_cmd_buf_idx = cmd_buf_idx; + + arch_irq_disable(); + if (console->rx_buf_idx == CONSOLE_INVALID_BUF_IDX) { + /* no buf for rx, set the used one for rx directly */ + console->rx_buf_idx = cmd_buf_idx; + console->rx_data_cnt = 0; + } else { + /* buf state change: ready --> free */ + CONSOLE_SET_BUF_BITMAP_VALID(console->free_buf_bitmap, cmd_buf_idx); + } + arch_irq_enable(); + + } else { + CONS_WARN("no valid command\n"); + } + } + + CONS_DBG("%s() exit\n", __func__); + OS_ThreadDelete(&g_console_thread); +} + +/** + * @brief Start the console according to the specified parameters + * @param[in] param Pointer to console_param_t structure + * @return 0 on success, -1 on failure + * + * @note Before starting the console, the related UART specified by + * console_param_t::uart_id MUST be inited. + * @note After starting the console, all UART's input data are read and + * processed by the console. + */ +int console_start(console_param_t *param) +{ + int i; + UART_T *uart; + console_priv_t *console; + + console = &g_console; + if (console->state != CONSOLE_STATE_STOP) { + CONS_ERR("console state %d\n", console->state); + return -1; + } + + memset(console, 0, sizeof(*console)); + console->uart_id = param->uart_id; + console->cmd_exec = param->cmd_exec; + + for (i = 0; i < CONSOLE_CMD_LINE_BUF_NUM; ++i) { + console->buf[i] = &g_console_buf[i * CONSOLE_CMD_LINE_MAX_LEN]; + CONSOLE_SET_BUF_BITMAP_VALID(console->free_buf_bitmap, i); + CONSOLE_SET_BUF_BITMAP_INVALID(console->ready_buf_bitmap, i); + } + + console->last_cmd_buf_idx = CONSOLE_CMD_LINE_BUF_NUM - 1; + + /* set rx buf */ + console->rx_buf_idx = 0; + console->rx_data_cnt = 0; + CONSOLE_SET_BUF_BITMAP_INVALID(console->free_buf_bitmap, console->rx_buf_idx); + + if (OS_SemaphoreCreate(&console->cmd_sem, 0, OS_SEMAPHORE_MAX_COUNT) != OS_OK) { + CONS_ERR("create semaphore failed\n"); + return -1; + } + + /* start console task */ + if (OS_ThreadCreate(&g_console_thread, + "", + console_task, + NULL, + OS_THREAD_PRIO_CONSOLE, + CONSOLE_THREAD_STACK_SIZE) != OS_OK) { + CONS_ERR("create console task failed\n"); + return -1; + } + + + uart = HAL_UART_GetInstance(console->uart_id); + HAL_UART_EnableRxCallback(console->uart_id, console_rx_callback, uart); + console->state = CONSOLE_STATE_START; + + return 0; +} + +/** + * @brief Stop the console + * @return None + */ +void console_stop(void) +{ + console_priv_t *console; + + console = &g_console; + HAL_UART_DisableRxCallback(console->uart_id); + console->state = CONSOLE_STATE_TERMINATE; + OS_SemaphoreRelease(&console->cmd_sem); + + while (OS_ThreadIsValid(&g_console_thread)) { + OS_MSleep(1); /* wait for thread termination */ + } + + OS_SemaphoreDelete(&console->cmd_sem); + console->state = CONSOLE_STATE_STOP; +} + +/** + * @brief Write out an amount of data through the console's UART + * @param[in] buf Pointer to the data buffer + * @param[in] len Number of bytes to be written out + * @return Number of bytes written out, -1 on error + */ +int console_write(uint8_t *buf, int32_t len) +{ + console_priv_t *console; + + console = &g_console; + return HAL_UART_Transmit_Poll(console->uart_id, buf, len); +} + +/** + * @brief Disable the console's input function + * @note This function is used to disable the console's input function + * temporarily when the console is running. When the console is diable, + * all UART's input data are no long read or processed by the console. + * @return None + */ +void console_disable(void) +{ + console_priv_t *console; + + console = &g_console; + if (console->state == CONSOLE_STATE_START) { + HAL_UART_DisableRxCallback(console->uart_id); + } +} + +/** + * @brief Enable the console's input function + * @note This function is used to enable the console's input function if it is + * disabled before. The console's input function is enable by default + * after starting. + * @return None + */ +void console_enable(void) +{ + console_priv_t *console; + UART_T *uart; + + console = &g_console; + if (console->state == CONSOLE_STATE_START) { + uart = HAL_UART_GetInstance(console->uart_id); + HAL_UART_EnableRxCallback(console->uart_id, console_rx_callback, uart); + } +} + +/** + * @brief Get the console's related UART ID + * @retval UART_ID, UART_INVALID_ID on failure + */ +UART_ID console_get_uart_id(void) +{ + console_priv_t *console; + + console = &g_console; + if (console->state == CONSOLE_STATE_START) { + return console->uart_id; + } else { + return UART_INVALID_ID; + } +} diff --git a/platform/mcu/xr871/src/console/console.mk b/platform/mcu/xr871/src/console/console.mk new file mode 100644 index 0000000000..42aaf6a221 --- /dev/null +++ b/platform/mcu/xr871/src/console/console.mk @@ -0,0 +1,8 @@ + + +NAME := console + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := \ + console.c + diff --git a/platform/mcu/xr871/src/console/console_debug.h b/platform/mcu/xr871/src/console/console_debug.h new file mode 100644 index 0000000000..48ddb80805 --- /dev/null +++ b/platform/mcu/xr871/src/console/console_debug.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CONSOLE_DEBUG_H_ +#define _CONSOLE_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONS_DBG_ON 0 +#define CONS_WARN_ON 1 +#define CONS_ERR_ON 1 + +#define CONS_CHECK_OVERFLOW 1 + +#define CONS_SYSLOG printf +#define CONS_ABORT() do { } while (1) //sys_abort() + +#define CONS_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + CONS_SYSLOG(fmt, ##arg); \ + } while (0) + +#define CONS_DBG(fmt, arg...) CONS_LOG(CONS_DBG_ON, "[console] "fmt, ##arg) +#define CONS_WARN(fmt, arg...) CONS_LOG(CONS_WARN_ON, "[console WARN] "fmt, ##arg) +#define CONS_ERR(fmt, arg...) \ + do { \ + CONS_LOG(CONS_ERR_ON, "[console ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (CONS_ERR_ON) \ + CONS_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _CONSOLE_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/chip.mk b/platform/mcu/xr871/src/driver/chip/chip.mk new file mode 100644 index 0000000000..b241b0b45f --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/chip.mk @@ -0,0 +1,44 @@ +NAME := chip + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := \ + codec/hal_ac101.c \ + codec/hal_codec.c \ + flashchip/flash_chip.c \ + flashchip/flash_default.c \ + hal_adc.c \ + hal_board.c \ + hal_ccm.c \ + hal_crypto.c \ + hal_csi.c \ + hal_dma.c \ + hal_dmic.c \ + hal_efuse.c \ + hal_flash.c \ + hal_flashcache.c \ + hal_flashctrl.c \ + hal_global.c \ + hal_gpio.c \ + hal_i2c.c \ + hal_i2s.c \ + hal_irrx.c \ + hal_irtx.c \ + hal_mbox.c \ + hal_nvic.c \ + hal_prcm.c \ + hal_pwm.c \ + hal_rtc.c \ + hal_spi.c \ + hal_spinlock.c \ + hal_timer.c \ + hal_uart.c \ + hal_util.c \ + hal_wakeup.c \ + hal_wdg.c \ + hal_xip.c \ + ir_nec.c \ + sdmmc/core.c \ + sdmmc/hal_sdhost.c \ + sdmmc/sd.c \ + system_chip.c + diff --git a/platform/mcu/xr871/src/driver/chip/codec/codec.h b/platform/mcu/xr871/src/driver/chip/codec/codec.h new file mode 100644 index 0000000000..112d00d5c5 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/codec/codec.h @@ -0,0 +1,115 @@ +/** + * @file codec.h + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_CODEC_H_ +#define _DRIVER_CHIP_CODEC_H_ + +#include "driver/chip/hal_codec.h" + +#ifdef __cplusplus + extern "C" { +#endif + +typedef struct { + uint8_t level; + uint8_t reg_val; +} Volume; + +typedef enum { + HAL_CODEC_INIT = 0, + HAL_CODEC_DEINIT +} CODEC_Req; + +/** + * @brief DAI pll/clock/format configuration, all optional.. + * Called by codec drivers. + */ +struct codec_dai_ops { + int32_t (*startup)(AUDIO_Device device); + int32_t (*setPll)(DAI_FmtParam *fmtParam); + int32_t (*setClkdiv)(DAI_FmtParam *fmtParam,uint32_t sampleRate); + int32_t (*setFormat)(DAI_FmtParam *fmtParam); + int32_t (*shutDown)(bool playOn, bool recordOn); +}; + +/** + * @brief Stream path/volume/trigger configuration, all optional. + * Called by codec drivers. + */ +struct codec_ctl_ops { + int32_t (*setRoute)(AUDIO_Device device); + int32_t (*setVolume)(AUDIO_Device dev, uint32_t volume); + int32_t (*setTrigger)(AUDIO_Device dev, uint32_t on); +}; + +/** + * @brief Stream path/volume/trigger configuration, all optional. + * Called by codec drivers. + */ +struct codec_ops { + int32_t (*setPower)(CODEC_Req req, void *arg); + int32_t (*setSysClk)(CODEC_Req req, void *arg); + int32_t (*setInitParam)(CODEC_Req req, void *arg); + int32_t (*jackDetect)(CODEC_Req req, void *arg); +}; + +/** + * @brief Codec info structure definition + */ +typedef struct { + uint8_t name[10]; /*!< Name of codec */ + uint8_t devAddr; /*!< Address of I2C device */ + uint8_t RegLength; /*!< I2C registers length */ + uint8_t RegValLength; /*!< I2C registers values length */ + struct codec_ops *ops; /*!< Init the low level hardware : GPIO, CLOCK, POWER, JACK...etc */ + struct codec_dai_ops *dai_ops; /*!< Init codec pcm interface */ + struct codec_ctl_ops *ctl_ops; /*!< Config stream volume and path */ +} CODEC,*CODECP; + +int32_t snd_soc_read(uint32_t reg); +int32_t snd_soc_write(uint32_t reg, uint32_t reg_val); +int32_t snd_soc_update_bits(uint32_t reg, uint32_t mask,uint32_t value); + +#define CODEC_I2C_REG_LENGTH8 1 +#define CODEC_I2C_REGVAL_LENGTH8 1 +#define CODEC_I2C_REGVAL_LENGTH16 2 + +#define MCLK1 1 +#define BCLK1 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_CODEC_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/codec/hal_ac101.c b/platform/mcu/xr871/src/driver/chip/codec/hal_ac101.c new file mode 100644 index 0000000000..f6b249469c --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/codec/hal_ac101.c @@ -0,0 +1,907 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "sys/io.h" +#include "kernel/os/os.h" +#include "../hal_base.h" +#include "codec.h" +#include "hal_ac101.h" + +#define AC101_DBG_ON 1 + +#if (AC101_DBG_ON == 1) +#define AC101_DEBUG(fmt, arg...) HAL_LOG(AC101_DBG_ON, "[AC101] "fmt, ##arg) +#else +#define AC101_DEBUG(fmt, arg...) +#endif +#define AC101_ERROR(fmt, arg...) HAL_LOG(1, "[AC101] "fmt, ##arg) + +/* PLL divisors */ +typedef struct { + uint32_t pll_in; + uint32_t pll_out; + uint32_t m; + uint32_t n_i; + uint32_t n_f; +} PLL_Div; + +typedef struct { + uint32_t samplerate; + uint32_t aif1_bclk_div; + uint32_t aif1_srbit; +} AIF1_Fs; + +typedef struct { + uint32_t aif1_lrlk_div; + uint32_t aif1_lrlk_bit; +} AIF1_Lrck; + +typedef struct { + uint32_t aif1_wsize_val; + uint32_t aif1_wsize_bit; +} AIF1_WordSize; + +#define AGC_ENABLE 0 +#define DRC_ENABLE 0 +#define AC101_I2C_ADDR 0x1a + +/* + * Note : pll code from original tdm/i2s driver. + * freq_out = freq_in * N/(m*(2k+1)) , k=1,N=N_i+N_f,N_f=factor*0.2; + */ +static const PLL_Div codec_pll_div[] = { + {128000, 22579200, 1, 529, 1}, + {192000, 22579200, 1, 352, 4}, + {256000, 22579200, 1, 264, 3}, + {384000, 22579200, 1, 176, 2},/*((176+2*0.2)*6000000)/(38*(2*1+1))*/ + {6000000, 22579200, 38, 429, 0},/*((429+0*0.2)*6000000)/(38*(2*1+1))*/ + {13000000, 22579200, 19, 99, 0}, + {19200000, 22579200, 25, 88, 1}, + {128000, 24576000, 1, 576, 0}, + {192000, 24576000, 1, 384, 0}, + {256000, 24576000, 1, 288, 0}, + {384000, 24576000, 1, 192, 0}, + {2048000, 24576000, 1, 36, 0}, + {6000000, 24576000, 25, 307, 1}, + {13000000, 24576000, 42, 238, 1}, + {19200000, 24576000, 25, 88, 1}, +}; + +static const AIF1_Fs codec_aif1_fs[] = { + {44100, 4, 7}, + {48000, 4, 8}, + {8000, 9, 0}, + {11025, 8, 1}, + {12000, 8, 2}, + {16000, 7, 3}, + {22050, 6, 4}, + {24000, 6, 5}, + {32000, 5, 6}, + {96000, 2, 9}, + {192000, 1, 10}, +}; + +static const AIF1_Lrck codec_aif1_lrck[] = { + {16, 0}, + {32, 1}, + {64, 2}, + {128, 3}, + {256, 4}, +}; + +static const AIF1_WordSize codec_aif1_wsize[] = { + {8, 0}, + {16, 1}, + {20, 2}, + {24, 3}, +}; + +static Volume spk_vol[] = { + {VOLUME_LEVEL0, 0}, + {VOLUME_LEVEL1, 1}, + {VOLUME_LEVEL2, 2}, + {VOLUME_LEVEL3, 3}, + {VOLUME_LEVEL4, 4}, + {VOLUME_LEVEL5, 5}, + {VOLUME_LEVEL6, 6}, + {VOLUME_LEVEL7, 7}, + {VOLUME_LEVEL8, 8}, + {VOLUME_LEVEL9, 9}, + {VOLUME_LEVEL10, 10}, + {VOLUME_LEVEL11, 11}, + {VOLUME_LEVEL12, 12}, + {VOLUME_LEVEL13, 13}, + {VOLUME_LEVEL14, 14}, + {VOLUME_LEVEL15, 15}, + {VOLUME_LEVEL16, 16}, + {VOLUME_LEVEL17, 17}, + {VOLUME_LEVEL18, 18}, + {VOLUME_LEVEL19, 19}, + {VOLUME_LEVEL20, 20}, + {VOLUME_LEVEL21, 21}, + {VOLUME_LEVEL22, 22}, + {VOLUME_LEVEL23, 23}, + {VOLUME_LEVEL24, 24}, + {VOLUME_LEVEL25, 25}, + {VOLUME_LEVEL26, 26}, + {VOLUME_LEVEL27, 27}, + {VOLUME_LEVEL28, 28}, + {VOLUME_LEVEL29, 29}, + {VOLUME_LEVEL30, 30}, + {VOLUME_LEVEL31, 31}, +}; + +static Volume phone_vol[] = { + {VOLUME_LEVEL0, 0}, + {VOLUME_LEVEL1, 2}, + {VOLUME_LEVEL2, 4}, + {VOLUME_LEVEL3, 6}, + {VOLUME_LEVEL4, 8}, + {VOLUME_LEVEL5, 10}, + {VOLUME_LEVEL6, 12}, + {VOLUME_LEVEL7, 14}, + {VOLUME_LEVEL8, 16}, + {VOLUME_LEVEL9, 18}, + {VOLUME_LEVEL10, 20}, + {VOLUME_LEVEL11, 22}, + {VOLUME_LEVEL12, 24}, + {VOLUME_LEVEL13, 26}, + {VOLUME_LEVEL14, 28}, + {VOLUME_LEVEL15, 30}, + {VOLUME_LEVEL16, 32}, + {VOLUME_LEVEL17, 34}, + {VOLUME_LEVEL18, 36}, + {VOLUME_LEVEL19, 38}, + {VOLUME_LEVEL20, 40}, + {VOLUME_LEVEL21, 42}, + {VOLUME_LEVEL22, 44}, + {VOLUME_LEVEL23, 46}, + {VOLUME_LEVEL24, 48}, + {VOLUME_LEVEL25, 50}, + {VOLUME_LEVEL26, 52}, + {VOLUME_LEVEL27, 54}, + {VOLUME_LEVEL28, 56}, + {VOLUME_LEVEL29, 58}, + {VOLUME_LEVEL30, 60}, + {VOLUME_LEVEL31, 63}, +}; + +static uint8_t speaker_double_used = 0; + +static void agc_config() +{ + snd_soc_update_bits(0xb4, (0x3<<6), (0x3<<6)); + snd_soc_update_bits(0x84, (0x3f<<8)|(0xff<<0), (0x31<<8)|(0x28<<0)); + snd_soc_update_bits(0x85, (0x3f<<8)|(0xff<<0), (0x31<<8)|(0x28<<0)); + snd_soc_update_bits(0x8a, (0x7fff<<0), (0x24<<0)); + snd_soc_update_bits(0x8b, (0x7fff<<0), 0x2<<0); + snd_soc_update_bits(0x8c, (0x7fff<<0), 0x24<<0); + snd_soc_update_bits(0x8d, (0x7fff<<0),(0x2<<0)); + snd_soc_update_bits(0x8e, (0x1f<<8)|(0x1f<<0),(0xf<<8)|(0xf<<0)); + snd_soc_update_bits(0x93, (0x7ff<<0),(0xfc<<0)); + snd_soc_write(0x94, 0xabb3); +} + +static void drc_config() +{ + snd_soc_update_bits(0xa3, (0x7ff<<0),(1<<0)); + snd_soc_write(0xa4, 0x2baf); + snd_soc_update_bits(0xa5, (0x7ff<<0),(1<<0)); + snd_soc_write(0xa6, 0x2baf); + snd_soc_update_bits(0xa7, (0x7ff<<0),(0<<0)); + snd_soc_write(0xa8, 0x44a); + snd_soc_update_bits(0xa9, (0x7ff<<0),(0<<0)); + snd_soc_write(0xaa, 0x1e06); + snd_soc_update_bits(0xab, (0x7ff<<0),(0x352<<0)); + snd_soc_write(0xac, 0x6910); + snd_soc_update_bits(0xad, (0x7ff<<0),(0x77a<<0)); + snd_soc_write(0xae, 0xaaaa); + snd_soc_update_bits(0xaf, (0x7ff<<0),(0x2de<<0)); + snd_soc_write(0xb0, 0xc982); + snd_soc_write(0x16, 0x9f9f); +} + +static void agc_enable(bool on) +{ + if (on) { + snd_soc_update_bits(MOD_CLK_ENA, (0x1<<7),(0x1<<7)); + snd_soc_update_bits(MOD_RST_CTRL, (0x1<<7),(0x1<<7)); + + snd_soc_update_bits(0x82, (0xf<<0)|(0x7<<12),(0x6<<0)|(0x7<<12)); + snd_soc_update_bits(0x83, (0xf<<0)|(0x7<<12),(0x6<<0)|(0x7<<12)); + } else { + snd_soc_update_bits(MOD_CLK_ENA, (0x1<<7),(0x0<<7)); + snd_soc_update_bits(MOD_RST_CTRL, (0x1<<7),(0x0<<7)); + + snd_soc_update_bits(0x82, (0xf<<0)|(0x7<<12),(0x0<<0)|(0x0<<12)); + snd_soc_update_bits(0x83, (0xf<<0)|(0x7<<12),(0x0<<0)|(0x0<<12)); + } +} + +static void drc_enable(bool on) +{ + if (on) { + snd_soc_write(0xb5, 0x80); + snd_soc_update_bits(MOD_CLK_ENA, (0x1<<6),(0x1<<6)); + snd_soc_update_bits(MOD_RST_CTRL, (0x1<<6),(0x1<<6)); + snd_soc_update_bits(0xa0, (0x7<<0),(0x7<<0)); + } else { + snd_soc_write(0xb5, 0x0); + snd_soc_update_bits(MOD_CLK_ENA, (0x1<<6),(0x0<<6)); + snd_soc_update_bits(MOD_RST_CTRL, (0x1<<6),(0x0<<6)); + snd_soc_update_bits(0xa0, (0x7<<0),(0x0<<0)); + } +} + +/* + * Set clock split ratio according to the pcm parameter. + */ +static int32_t AC101_SetClkdiv(DAI_FmtParam *fmtParam,uint32_t sampleRate) +{ + uint32_t i = 0; + uint32_t aif1_word_size = fmtParam->wordWidth; + uint32_t aif1_lrlk_div = 2*fmtParam->slotWidth; + + /*set BCLK/LRCK ratio*/ + for (i = 0; i < ARRAY_SIZE(codec_aif1_lrck); i++) { + if (codec_aif1_lrck[i].aif1_lrlk_div == aif1_lrlk_div) { + snd_soc_update_bits(AIF1_CLK_CTRL, (0x7<freqIn < 128000) || (fmtParam->freqIn > 24576000)) { + return HAL_INVALID; + } else if ((fmtParam->freqIn == 24576000) || (fmtParam->freqIn == 22579200)) { + switch (fmtParam->pllId) { + case MCLK1: + /*select aif1 clk source from mclk1 and enable aif1*/ + snd_soc_update_bits(SYSCLK_CTRL, (0x3<pllId) { + case MCLK1: + /*pll source from MCLK1*/ + snd_soc_update_bits(SYSCLK_CTRL, (0x3<freqIn) && (codec_pll_div[i].pll_out == fmtParam->freqOut)) { + m = codec_pll_div[i].m; + n_i = codec_pll_div[i].n_i; + n_f = codec_pll_div[i].n_f; + break; + } + } + /*config pll m*/ + snd_soc_update_bits(PLL_CTRL1, (0x3f<clkMode){ + case DAIFMT_CBM_CFM: /* codec clk & frm master, ap is slave*/ + reg_val |= (0x0<transferFormat){ + case DAIFMT_I2S: /* I2S1 mode */ + reg_val |= (0x0<signalInterval){ + case DAIFMT_NB_NF: /* normal bit clock + nor frame */ + reg_val &= ~(0x1<speaker_double_used) { + snd_soc_update_bits(SPKOUT_CTRL, (0x1f<double_speaker_val<single_speaker_val<speaker_double_used; + + snd_soc_update_bits(HPOUT_CTRL, (0x3f<headset_val<mainmic_val<headsetmic_val< VOLUME_MAX_LEVEL) + return -1; + uint32_t volume_val = 0; + switch (dev) { + case AUDIO_DEVICE_HEADPHONE: + volume_val = phone_vol[volume].reg_val; + snd_soc_update_bits(HPOUT_CTRL, (0x3f<RegValLength == CODEC_I2C_REGVAL_LENGTH16) + regValLength = 2; + else if (priv->RegValLength == CODEC_I2C_REGVAL_LENGTH8) + regValLength = 1; + else + return -1; + + if (priv->RegLength != CODEC_I2C_REG_LENGTH8) + return -1; + + ret = priv->read(priv->i2cId,priv->devAddr,reg,val,regValLength); + if (ret != regValLength) + return -1; + + uint16_t *reg_val = (uint16_t *)val; + if (regValLength == CODEC_I2C_REGVAL_LENGTH16) + return ((((*reg_val)&0xFF) << 8) |(((*reg_val)&0xFF00)>>8)); + else if(regValLength == CODEC_I2C_REGVAL_LENGTH8) + return ((*reg_val)&0xFF); + else + return -1; +} + +int32_t snd_soc_write(uint32_t reg, uint32_t reg_val) +{ + uint32_t ret; + CODEC_Priv *priv = &gCodecPriv; + uint8_t val[5]; + + int8_t regValLength = 0; + + if (priv->RegLength != CODEC_I2C_REG_LENGTH8) + return -1; + + if (priv->RegValLength == CODEC_I2C_REGVAL_LENGTH16) { + regValLength = 2; + val[0] = (reg_val & 0xFF00) >> 8; + val[1] = reg_val & 0xFF; + }else if (priv->RegValLength == CODEC_I2C_REGVAL_LENGTH8) { + regValLength = 1; + val[0] = reg_val & 0xFF; + } else + return -1; + + ret = priv->write(priv->i2cId,priv->devAddr, reg, val,regValLength); + if (ret != regValLength) + return -1; + else + return 0; +} + +/** + * @internal + * @brief update codec register bits. + * @param reg: codec register. + * @param mask: register mask. + * @param value: new value. + * @retval Returns 1 for change, 0 for no change, or negative error code. + */ +int32_t snd_soc_update_bits(uint32_t reg, uint32_t mask, uint32_t value) +{ + bool change; + uint32_t old, new; + int ret; + ret = snd_soc_read(reg); + if (ret < 0) + return ret; + old = ret; + new = (old & ~mask) | (value & mask); + change = old != new; + if (change) + ret = snd_soc_write(reg, new); + if (ret < 0) + return ret; + return change; +} + +/** + * @brief Enable or Disable output device. + * @param AUDIO_Device: audio device. + * @param on: enable or disable. + * @retval HAL state + */ +HAL_Status HAL_CODEC_Trigger(AUDIO_Device dev, uint32_t on) +{ + if (dev != AUDIO_DEVICE_HEADPHONE && dev != AUDIO_DEVICE_SPEAKER) + return HAL_ERROR; + CODEC_Priv *priv = &gCodecPriv; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (priv->spk_cfg && dev == AUDIO_DEVICE_SPEAKER) { + HAL_GPIO_WritePin(priv->spk_cfg->ctrl_port, + priv->spk_cfg->ctrl_pin, + on ? priv->spk_cfg->ctrl_on_state : + priv->spk_cfg->ctrl_off_state); + } else {//headphone set in codec file + + if (priv->ctl_ops->setTrigger) + priv->ctl_ops->setTrigger(dev, on); + } + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Set output device mute or unmute. + * @param AUDIO_Device: audio device. + * @param mute: mute flag. + * @retval HAL state + */ +HAL_Status HAL_CODEC_Mute(AUDIO_Device dev, uint32_t mute) +{ + if (dev > AUDIO_DEVICE_MAINMIC || dev < AUDIO_DEVICE_HEADPHONE) + return HAL_ERROR; + + CODEC_Priv *priv = &gCodecPriv; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + + if (dev == AUDIO_DEVICE_SPEAKER && priv->spk_cfg) { + HAL_GPIO_WritePin(priv->spk_cfg->ctrl_port, + priv->spk_cfg->ctrl_pin, + mute ? priv->spk_cfg->ctrl_off_state : + priv->spk_cfg->ctrl_on_state); + } + + if (dev == AUDIO_DEVICE_HEADPHONE) { + } + + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Set current stream output device or input device. + * @param AUDIO_Device: audio device. + * @retval HAL state + */ +HAL_Status HAL_CODEC_ROUTE_Set(AUDIO_Device dev) +{ + if (dev > AUDIO_DEVICE_MAINMIC || dev < AUDIO_DEVICE_HEADPHONE) + return HAL_ERROR; + + CODEC_Priv *priv = &gCodecPriv; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (priv->spk_cfg && dev == AUDIO_DEVICE_HEADPHONE) { + HAL_GPIO_WritePin(priv->spk_cfg->ctrl_port, + priv->spk_cfg->ctrl_pin, + priv->spk_cfg->ctrl_off_state); + } + if (priv->ctl_ops->setRoute) + priv->ctl_ops->setRoute(dev); + + if (priv->spk_cfg && dev == AUDIO_DEVICE_SPEAKER) { + HAL_GPIO_WritePin(priv->spk_cfg->ctrl_port, + priv->spk_cfg->ctrl_pin, + priv->spk_cfg->ctrl_on_state); + } + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Set output device's volume gain when stream on. + * @param AUDIO_Device: audio output device. + * @param volume: the audio gain. + * @retval HAL state + */ +HAL_Status HAL_CODEC_VOLUME_LEVEL_Set(AUDIO_Device dev,int volume) +{ + CODEC_Priv *priv = &gCodecPriv; + if (volume > VOLUME_MAX_LEVEL) + return HAL_INVALID; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (priv->ctl_ops->setVolume) + priv->ctl_ops->setVolume(dev, volume); + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Init output device's volume gain. + * @param AUDIO_Device: audio output device. + * @param volume: the audio gain. + * @retval HAL state + */ +HAL_Status HAL_CODEC_INIT_VOLUME_Set(AUDIO_Device dev,int volume) +{ + CODEC_Priv *priv = &gCodecPriv; + + if (volume > VOLUME_MAX_LEVEL) + return HAL_INVALID; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + g_init_volume_value = volume; + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Init the codec mute state + * @param status: The status of output device. + * @retval HAL state + */ +HAL_Status HAL_CODEC_MUTE_STATUS_Init(int status) +{ + CODEC_Priv *priv = &gCodecPriv; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + g_init_mute_status = status; + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Return the codec output device(mute or unmute) state + * @retval device state + */ +uint32_t HAL_CODEC_MUTE_STATUS_Get() +{ + return g_init_mute_status; +} + +/** + * @brief Open the Codec module according to the specified parameters + * in the DATA_Param. + * @param param: pointer to a DATA_Param structure that contains + * data format information + * @retval HAL status + */ +HAL_Status HAL_CODEC_Open(DATA_Param *param) +{ + if (!param) + return HAL_INVALID; + + CODEC_DEBUG("CODEC Open..\n"); + + CODEC_Priv *priv = &gCodecPriv; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (!param->fmtParam) + priv->fmtParam = &gFmtParam; + else + priv->fmtParam = param->fmtParam; + + if (param->sampleRate) + priv->sampleRate = param->sampleRate; + else + priv->sampleRate = 48000; + + switch (param->audioDev) { + case AUDIO_DEVICE_HEADPHONE: + case AUDIO_DEVICE_SPEAKER: + priv->playBack = 1; + break; + case AUDIO_DEVICE_HEADPHONEMIC: + case AUDIO_DEVICE_MAINMIC: + priv->record = 1; + break; + default: + HAL_MutexUnlock(&priv->Lock); + return HAL_INVALID; + } + + if (priv->dai_ops->startup) + priv->dai_ops->startup(param->audioDev); + if (priv->dai_ops->setPll) + priv->dai_ops->setPll(priv->fmtParam); + if (priv->dai_ops->setClkdiv) + priv->dai_ops->setClkdiv(priv->fmtParam,priv->sampleRate); + if (priv->dai_ops->setFormat) + priv->dai_ops->setFormat(priv->fmtParam); + if (priv->ctl_ops->setRoute) + priv->ctl_ops->setRoute(param->audioDev); + if (priv->ctl_ops->setVolume && (param->audioDev < AUDIO_DEVICE_HEADPHONEMIC)) + priv->ctl_ops->setVolume(param->audioDev, g_init_volume_value); + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +/** + * @brief Close the Codec module + * + * @note The module is closed at the end of transaction to avoid power consumption + * @retval none + */ +HAL_Status HAL_CODEC_Close(uint32_t dir) +{ + CODEC_Priv *priv = &gCodecPriv; + + CODEC_DEBUG("CODEC Close..\n"); + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (dir == 0) { + priv->playBack = 0; + } else { + priv->record = 0; + } + if (priv->dai_ops->shutDown) + priv->dai_ops->shutDown(priv->playBack, priv->record); + HAL_MutexUnlock(&priv->Lock); + + return HAL_OK; +} + +#ifdef CONFIG_PM +static int codec_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + CODEC_Priv *priv = &gCodecPriv; + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + + if (priv->ops->setInitParam) + priv->ops->setInitParam(HAL_CODEC_DEINIT,NULL); + if (priv->ops->jackDetect) + priv->ops->jackDetect(HAL_CODEC_DEINIT,NULL); + if (priv->ops->setSysClk) + priv->ops->setSysClk(HAL_CODEC_DEINIT,NULL); + if (priv->ops->setPower) + priv->ops->setPower(HAL_CODEC_DEINIT,NULL); + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, + HAL_MKDEV(HAL_DEV_MAJOR_AUDIO_CODEC, 0), 0); + + HAL_MutexUnlock(&priv->Lock); + + break; + default: + break; + } + return 0; +} + +static int codec_resume(struct soc_device *dev, enum suspend_state_t state) +{ + CODEC_Priv *priv = &gCodecPriv; + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + + if (priv->ops->setPower) + priv->ops->setPower(HAL_CODEC_INIT,NULL); + if (priv->ops->setSysClk) + priv->ops->setSysClk(HAL_CODEC_INIT,NULL); + if (priv->ops->setInitParam) + priv->ops->setInitParam(HAL_CODEC_INIT,(void *)priv->initParam); + if (priv->ops->jackDetect) + priv->ops->jackDetect(HAL_CODEC_INIT,NULL); + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, + HAL_MKDEV(HAL_DEV_MAJOR_AUDIO_CODEC, 0), 0); + + HAL_MutexUnlock(&priv->Lock); + break; + + default: + break; + } + return 0; +} + +static struct soc_device_driver codec_drv = { + .name = "CODEC", + .suspend = codec_suspend, + .resume = codec_resume, +}; + +static struct soc_device codec_dev = { + .name = "CODEC", + .driver = &codec_drv, +}; + +#define CODEC_DEV (&codec_dev) +#else +#define CODEC_DEV NULL +#endif + +/** + * @brief Initializes the CODEC according to the specified parameters + * in the CODEC_Param. + * @param param: pointer to a CODEC_Param structure that contains + * the configuration information for CODEC module + * @retval HAL status + */ +HAL_Status HAL_CODEC_Init(const CODEC_Param *param) +{ + if (!param) + return HAL_INVALID; + + CODEC_DEBUG("CODEC INIT..\n"); + + CODEC_Priv *priv = &gCodecPriv; + memset(priv,0,sizeof(*priv)); + /* set i2s read/write interface */ + priv->read= param->read; + priv->write = param->write; + priv->i2cId = param->i2cId; + + if (!param->param) + priv->initParam = &gInitParam; + else + priv->initParam = param->param; + + int i = 0; + CODECP codec = NULL; + for (i = 0; strlen((char *)(codecs[i].name)); i++) { + if (strncmp((char *)(param->name), (char *)(codecs[i].name), + strlen((char *)(codecs[i].name))) == 0) { + codec = codecs[i].dev; + } + } + if (!codec) + return HAL_ERROR; + + HAL_MutexInit(&priv->Lock); + priv->ops = codec->ops; + priv->dai_ops = codec->dai_ops; + priv->ctl_ops = codec->ctl_ops; + priv->name = codec->name; + priv->devAddr = codec->devAddr; + priv->RegValLength = codec->RegValLength; + priv->RegLength = codec->RegLength; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (priv->ops->setPower) + priv->ops->setPower(HAL_CODEC_INIT,NULL); + if (priv->ops->setSysClk) + priv->ops->setSysClk(HAL_CODEC_INIT,NULL); + + if (priv->ops->setInitParam) + priv->ops->setInitParam(HAL_CODEC_INIT,(void *)priv->initParam); + + if (priv->ops->jackDetect) + priv->ops->jackDetect(HAL_CODEC_INIT,NULL); +#ifdef CONFIG_PM + pm_register_ops(CODEC_DEV); +#endif + HAL_MutexUnlock(&priv->Lock); + + HAL_BoardIoctl(HAL_BIR_GET_CFG, + HAL_MKDEV(HAL_DEV_MAJOR_AUDIO_CODEC, 0), + (uint32_t)&priv->spk_cfg); + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, + HAL_MKDEV(HAL_DEV_MAJOR_AUDIO_CODEC, 0), 0); + return HAL_OK; +} + +/** + * @brief DeInitializes the CODEC peripheral(power, clk, jack) + * @retval HAL status + */ +HAL_Status HAL_CODEC_DeInit() +{ + CODEC_Priv *priv = &gCodecPriv; + + HAL_MutexLock(&priv->Lock, OS_WAIT_FOREVER); + if (priv->ops->setPower) + priv->ops->setPower(HAL_CODEC_DEINIT,NULL); + + if (priv->ops->setSysClk) + priv->ops->setSysClk(HAL_CODEC_DEINIT,NULL); + + if (priv->ops->setInitParam) + priv->ops->setInitParam(HAL_CODEC_DEINIT,NULL); + + if (priv->ops->jackDetect) + priv->ops->jackDetect(HAL_CODEC_DEINIT,NULL); + HAL_MutexUnlock(&priv->Lock); + + HAL_MutexDeinit(&priv->Lock); + return HAL_OK; +} diff --git a/platform/mcu/xr871/src/driver/chip/flashchip/flash_chip.c b/platform/mcu/xr871/src/driver/chip/flashchip/flash_chip.c new file mode 100644 index 0000000000..b9a30c46cd --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/flashchip/flash_chip.c @@ -0,0 +1,962 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "driver/chip/flashchip/flash_chip.h" +#include "driver/chip/hal_flash.h" +#include "driver/chip/hal_xip.h" +#include "../hal_base.h" +#include "flash_default.h" + +#define FLASH_DEBUG(fmt, arg...) XR_DEBUG((DBG_OFF | XR_LEVEL_ALL), NOEXPAND, "[Flash chip debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define FLASH_ALERT(fmt, arg...) XR_ALERT((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash chip alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define FLASH_ERROR(fmt, arg...) XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash chip error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define FLASH_NOWAY() XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash chip should not be here] <%s : %d> \n", __func__, __LINE__) +#define FLASH_NOTSUPPORT() FLASH_ALERT("not support command") + +typedef enum { + FLASH_INSTRUCTION_WREN = 0x06, /* write enable */ + FLASH_INSTRUCTION_WRDI = 0x04, /* write disable */ + FLASH_INSTRUCTION_RDID = 0x9F, /* jedec id */ + FLASH_INSTRUCTION_RDSR1 = 0x05, /* read status register-1 */ + FLASH_INSTRUCTION_WRSR1 = 0x01, /* write status register-1 */ + FLASH_INSTRUCTION_READ = 0x03, /* read data */ + FLASH_INSTRUCTION_FAST_READ = 0x0B, /* fast read */ + FLASH_INSTRUCTION_PP = 0x02, /* page program */ + FLASH_INSTRUCTION_ERASE_64KB = 0xD8, /* erase block(sector) 64k */ + FLASH_INSTRUCTION_ERASE_32KB = 0x52, /* erase block(sector) 32k */ + FLASH_INSTRUCTION_ERASE_4KB = 0x20, /* erase sector 4k */ + FLASH_INSTRUCTION_ERASE_CHIP = 0xC7, /* chip erase */ + FLASH_INSTRUCTION_WRSR = 0X01, /* write status register */ + FLASH_INSTRUCTION_FAST_READ_DO = 0x3B, /* fast read dual output */ + FLASH_INSTRUCTION_RDSR2 = 0x35, + FLASH_INSTRUCTION_RDSR3 = 0x15, + FLASH_INSTRUCTION_WRSR2 = 0x31, + FLASH_INSTRUCTION_WRSR3 = 0x11, + FLASH_INSTRUCTION_SRWREN = 0x50, + FLASH_INSTRUCTION_CE = 0x60, + FLASH_INSTRUCTION_EPSP = 0x75, + FLASH_INSTRUCTION_EPRS = 0x7A, + FLASH_INSTRUCTION_PWDN = 0xB9, + FLASH_INSTRUCTION_REL = 0xAB, + FLASH_INSTRUCTION_FAST_READ_DIO = 0xBB, + FLASH_INSTRUCTION_FAST_READ_QO = 0x6B, + FLASH_INSTRUCTION_FAST_READ_QIO = 0xEB, + FLASH_INSTRUCTION_EN_QPI = 0x38, + FLASH_INSTRUCTION_DIS_QPI = 0xFF, + FLASH_INSTRUCTION_RSEN = 0x66, + FLASH_INSTRUCTION_RESET = 0x99, + FLASH_INSTRUCTION_QPP = 0x32, + FLASH_INSTRUCTION_SRP = 0xC0, +} eSF_Instruction; + +FlashChipCtor *flashChipList[] = { + &DefaultFlashChip, /*default chip must be at the last*/ +}; + + +#define INSTRUCT_ZCREATE(cmd, addr, dummy, data) \ + InstructionField cmd, addr, dummy, data; \ + do { \ + HAL_Memset(&cmd, 0, sizeof(InstructionField)); \ + HAL_Memset(&addr, 0, sizeof(InstructionField)); \ + HAL_Memset(&dummy, 0, sizeof(InstructionField)); \ + HAL_Memset(&data, 0, sizeof(InstructionField)); \ + } while (0) + + +static uint32_t getJedecID(FlashDrvierBase *driver) +{ + int ret; + PCHECK(driver); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_RDID; + cmd.len = 1; + cmd.line = 1; + data.pdata = (uint8_t *)&data.data; + data.line = 1; + data.len = 3; + + driver->open(driver); + ret = driver->read(driver, &cmd, NULL, NULL, &data); + if (ret != HAL_OK) + FLASH_ERROR("driver go some wrong: %d", ret); + driver->close(driver); + + return data.data; +} + +FlashChipBase *FlashChipCreate(FlashDrvierBase *driver) +{ + uint32_t list_size = sizeof(flashChipList) / sizeof(flashChipList[0]); + uint32_t jedec = getJedecID(driver); + FlashChipBase *base = NULL; + FlashChipCtor *ctor = NULL; + + FLASH_DEBUG("jedec: 0x%x, list_size: %d", jedec, list_size); + + while (list_size--) + { + ctor = flashChipList[list_size]; + if (ctor->mJedecId == jedec) + break; + } + + base = ctor->create(jedec); +/* base->writeEnable = defaultWriteEnable; + base->writeDisable = defaultWriteDisable; + base->readStatus = defaultReadStatus; + base->erase = defaultErase; + base->jedecID = defaultGetJedecID; + base->pageProgram = defaultPageProgram; + base->read = defaultRead; + + base->driverWrite = defaultDriverWrite; + base->driverRead = defaultdriverRead; + base->setFreq = defaultSetFreq; + base->switchReadMode = defaultSwitchReadMode; + base->enableXIP = defaultEnableXIP; + base->disableXIP = defaultDisableXIP; + base->isBusy = defaultIsBusy; + base->control = defaultControl; + base->minEraseSize = defaultGetMinEraseSize; + + base->writeStatus = NULL; + base->suspendErasePageprogram = NULL; + base->resumeErasePageprogram = NULL; + base->powerDown = NULL; + base->releasePowerDown = NULL; + base->enableQPIMode = NULL; + base->disableQPIMode = NULL; + base->enableReset = NULL; + base->reset = NULL; + base->uniqueID = NULL;*/ + ctor->init(base); + base->mDriver = driver; + + return base; +} + + +/* + Default Flash Chip Interface +*/ +typedef struct { + uint8_t SRP0: 1; + uint8_t SEC: 1; + uint8_t TB: 1; + uint8_t BP2: 1; + uint8_t BP1: 1; + uint8_t BP0: 1; + uint8_t WEL: 1; + uint8_t BUSY: 1; +} DefaultFlash_StatusRegister1; //this can be different in different flash chip. + +typedef struct { + union { + struct { + uint8_t SRP1: 1; + uint8_t QE: 1; + uint8_t RESERVED: 1; + uint8_t LB1: 1; + uint8_t LB2: 1; + uint8_t LB3: 1; + uint8_t CMP: 1; + uint8_t SUS: 1; + }; + uint8_t status; + }; +} DefaultFlash_StatusRegister2; //this can be different in different flash chip. + + +void defaultWriteEnable(FlashChipBase *base) +{ + PCHECK(base); + InstructionField cmd, addr, dummy, data; + + memset(&cmd, 0, sizeof(InstructionField)); + memset(&addr, 0, sizeof(InstructionField)); + memset(&dummy, 0, sizeof(InstructionField)); + memset(&data, 0, sizeof(InstructionField)); + + cmd.data = FLASH_INSTRUCTION_WREN; + cmd.line = 1; + + base->driverWrite(base, &cmd, NULL, NULL, NULL); +} + +void defaultWriteDisable(FlashChipBase *base) +{ + PCHECK(base); + InstructionField cmd, addr, dummy, data; + + memset(&cmd, 0, sizeof(InstructionField)); + memset(&addr, 0, sizeof(InstructionField)); + memset(&dummy, 0, sizeof(InstructionField)); + memset(&data, 0, sizeof(InstructionField)); + + cmd.data = FLASH_INSTRUCTION_WRDI; + cmd.line = 1; + + base->driverWrite(base, &cmd, NULL, NULL, NULL); +} + +int defaultReadStatus(FlashChipBase *base, FlashStatus reg, uint8_t *status) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + if (!(reg & base->mReadStausSupport)) { + FLASH_NOTSUPPORT(); + return -1; + } + + if (reg == FLASH_STATUS1) + { + cmd.data = FLASH_INSTRUCTION_RDSR1; + } + else if (reg == FLASH_STATUS2) + { + cmd.data = FLASH_INSTRUCTION_RDSR2; + } + else if (reg == FLASH_STATUS3) + { + cmd.data = FLASH_INSTRUCTION_RDSR3; + } + else + FLASH_NOWAY(); + + data.pdata = (uint8_t *)status; + data.len = 1; + data.line = 1; + + return base->driverRead(base, &cmd, NULL, NULL, &data); +} + +int defaultWriteStatus(FlashChipBase *base, FlashStatus reg, uint8_t *status) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + if (!(reg & base->mWriteStatusSupport)) { + FLASH_NOTSUPPORT(); + return HAL_INVALID; + } + + cmd.data = FLASH_INSTRUCTION_SRWREN; + cmd.line = 1; + + base->driverWrite(base, &cmd, NULL, NULL, NULL); + + + memset(&cmd, 0, sizeof(InstructionField)); + memset(&addr, 0, sizeof(InstructionField)); + memset(&dummy, 0, sizeof(InstructionField)); + memset(&data, 0, sizeof(InstructionField)); + + if (reg == FLASH_STATUS1) + { + cmd.data = FLASH_INSTRUCTION_WRSR1; + } + else if (reg == FLASH_STATUS2) + { + cmd.data = FLASH_INSTRUCTION_WRSR2; + } + else if (reg == FLASH_STATUS3) + { + cmd.data = FLASH_INSTRUCTION_WRSR3; + } + else + FLASH_NOWAY(); + + data.pdata = (uint8_t *)status; + data.len = 1; + data.line = 1; + + return base->driverWrite(base, &cmd, NULL, NULL, &data); +} + +int defaultErase(FlashChipBase *base, FlashEraseMode mode, uint32_t eaddr) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + if (!(mode & base->mEraseSizeSupport)) { + FLASH_NOTSUPPORT(); + return HAL_INVALID; + } + + FLASH_DEBUG("mode: 0x%x; base->mEraseSizeSupport: 0x%x", mode, base->mEraseSizeSupport); + + if (mode == FLASH_ERASE_CHIP) + { + cmd.data = FLASH_INSTRUCTION_ERASE_CHIP; + base->driverWrite(base, &cmd, NULL, NULL, NULL); + return 0; + } + else if (mode == FLASH_ERASE_32KB) + { + cmd.data = FLASH_INSTRUCTION_ERASE_32KB; + } + else if (mode == FLASH_ERASE_64KB) + { + cmd.data = FLASH_INSTRUCTION_ERASE_64KB; + } + else if (mode == FLASH_ERASE_4KB) + { + cmd.data = FLASH_INSTRUCTION_ERASE_4KB; + } + else + FLASH_NOWAY(); + + addr.data = eaddr; + addr.line = 1; + + return base->driverWrite(base, &cmd, &addr, NULL, NULL); +} + +int defaultSuspendErasePageprogram(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_EPSP; + return base->driverWrite(base, &cmd, NULL, NULL, NULL); +} + +int defaultResumeErasePageprogram(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_EPRS; + return base->driverWrite(base, &cmd, NULL, NULL, NULL); +} + +int defaultPowerDown(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_PWDN; + return base->driverWrite(base, &cmd, NULL, NULL, NULL); +} + +int defaultReleasePowerDown(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_REL; + dummy.len = 3; + dummy.line = 1; + data.len = 1; + data.line = 1; + + return base->driverWrite(base, &cmd, NULL, &dummy, &data); +} + +int defaultGetJedecID(FlashChipBase *base, uint32_t *jedec) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_RDID; + data.pdata = (uint8_t *)jedec; + data.line = 1; + data.len = 3; + return base->driverRead(base, &cmd, NULL, NULL, &data); +} + +int defaultEnableQPIMode(FlashChipBase *base) +{ + int ret; + uint32_t tmp; + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_EN_QPI; + ret = base->driverWrite(base, &cmd, NULL, NULL, NULL); + + if (ret >= 0) + base->mFlashStatus |= FLASH_READ_QPI_MODE; + else + return ret; + + tmp = 0x03; + ret = base->control(base, DEFAULT_FLASH_SET_QPI_READ_P5P4, &tmp); + if (ret >= 0) + base->mDummyCount = 4; + + return ret; +} + +int defaultDisableQPIMode(FlashChipBase *base) +{ + int ret; + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_DIS_QPI; + cmd.line = 4; + ret = base->driverWrite(base, &cmd, NULL, NULL, NULL); + if (ret == 0) + base->mFlashStatus &= ~FLASH_READ_QPI_MODE; + return ret; +} + +/* +int defaultEnableReset(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_RSEN; + return base->driverWrite(base, &cmd, NULL, NULL, NULL); +} +*/ + +int defaultReset(FlashChipBase *base) +{ + int ret; + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_RSEN; + ret = base->driverWrite(base, &cmd, NULL, NULL, NULL); + if (ret < 0) + return ret; + + HAL_Memset(&cmd, 0, sizeof(InstructionField)); + cmd.data = FLASH_INSTRUCTION_RESET; + return base->driverWrite(base, &cmd, NULL, NULL, NULL); +} + +int defaultGetUniqueID(FlashChipBase *base, uint8_t uid[8]) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_RESET; + dummy.line = 1; + dummy.len = 4; + data.pdata = uid; + data.line = 1; + data.len = 8; + return base->driverRead(base, &cmd, NULL, &dummy, &data); +} + +int defaultPageProgram(FlashChipBase *base, FlashPageProgramMode mode, uint32_t waddr, uint8_t *wdata, uint32_t size) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + if (size > base->mPageSize) + return -1; + + if (!(mode & base->mPageProgramSupport)) { + FLASH_NOTSUPPORT(); + return HAL_INVALID; + } + + if (((waddr + size) > base->mSize) || (size > base->mPageSize)) + return -1; + + if (mode == FLASH_PAGEPROGRAM) + { + cmd.data = FLASH_INSTRUCTION_PP; + data.line = 1; + } + else if (mode == FLASH_QUAD_PAGEPROGRAM) + { + cmd.data = FLASH_INSTRUCTION_QPP; + data.line = 4; + } + else + FLASH_NOWAY(); + + addr.data = waddr; + addr.line = 1; + data.pdata = wdata; + data.len = size; + return base->driverWrite(base, &cmd, &addr, NULL, &data); +} + +int defaultRead(FlashChipBase *base, FlashReadMode mode, uint32_t raddr, uint8_t *rdata, uint32_t size) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + if (!(mode & base->mReadSupport)) { + FLASH_DEBUG("this flash chip not support read mode: %d", mode); + FLASH_NOTSUPPORT(); + return HAL_INVALID; + } + + if ((raddr + size) > base->mSize) + return -1; + + FLASH_DEBUG("size: %d; mode: %d", size, (uint32_t)mode); + + switch (mode) + { + /* !!! NOTICE: m7~m0 is count to dummy byte. !!! */ + case FLASH_READ_NORMAL_MODE: + cmd.data = FLASH_INSTRUCTION_READ; + addr.line = 1; + data.line = 1; + dummy.len = 0; + break; + case FLASH_READ_FAST_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ; + addr.line = 1; + data.line = 1; + dummy.len = 1; + dummy.line = 1; + break; + case FLASH_READ_DUAL_O_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_DO; + addr.line = 1; + data.line = 2; + dummy.len = 1; + dummy.line = 1; + break; + case FLASH_READ_DUAL_IO_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_DIO; + addr.line = 2; + data.line = 2; + dummy.len = 1; + dummy.line = 2; + break; + case FLASH_READ_QUAD_O_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_QO; + addr.line = 1; + data.line = 4; + dummy.len = 1; + dummy.line = 1; + break; + case FLASH_READ_QUAD_IO_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_QIO; + addr.line = 4; + data.line = 4; + dummy.len = 3; + dummy.line = 4; + break; + case FLASH_READ_QPI_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_QIO; + cmd.line = 4; + data.line = 4; + dummy.len = base->mDummyCount; + dummy.line = 4; + break; + default: + return -1; + } + + addr.data = raddr; + data.pdata = rdata; + data.len = size; + return base->driverRead(base, &cmd, &addr, &dummy, &data); +} + +int defaultDriverWrite(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + if (base == NULL || cmd == NULL) + return -1; + + if (!(base->mFlashStatus & FLASH_READ_QPI_MODE)) + { + cmd->len = 1; + cmd->line = 1; //not in QPI + + if (addr != NULL) + addr->len = 3; + if (data != NULL && data->pdata == NULL && data->len <= 4) + data->pdata = (uint8_t *)&data->data; + } + else + { + cmd->len = 1; + cmd->line = 4; //not in QPI + + if (addr != NULL) + { + addr->len = 3; + addr->line = 4; + } + if (dummy != NULL) + dummy->line = 4; + if (data != NULL) + data->line = 4; + if (data != NULL && data->pdata == NULL && data->len <= 4) + data->pdata = (uint8_t *)&data->data; + } + + if (base->mDriver == NULL || base->mDriver->write == NULL) + return -1; + + FLASH_DEBUG("cmd: 0x%x", cmd->data); + + return base->mDriver->write(base->mDriver, cmd, addr, dummy, data); +} + +int defaultDriverRead(FlashChipBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + if (base == NULL || cmd == NULL) + return -1; + + if (!(base->mFlashStatus & FLASH_READ_QPI_MODE)) + { + cmd->len = 1; + cmd->line = 1; //not in QPI + + if (addr != NULL) + addr->len = 3; + if (data != NULL && data->pdata == NULL && data->len <= 4) + data->pdata = (uint8_t *)&data->data; + } + else /* in QPI mode */ + { + cmd->len = 1; + cmd->line = 4; //not in QPI + + if (addr != NULL) + { + addr->len = 3; + addr->line = 4; + } + if (dummy != NULL) + dummy->line = 4; + if (data != NULL) + data->line = 4; + if (data != NULL && data->pdata == NULL && data->len <= 4) + data->pdata = (uint8_t *)&data->data; + } + + if (base->mDriver == NULL || base->mDriver->read == NULL) + return -1; + + FLASH_DEBUG("cmd: 0x%x", cmd->data); + + return base->mDriver->read(base->mDriver, cmd, addr, dummy, data); +} + +int defaultXipDriverCfg(FlashChipBase *base, FlashReadMode mode) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + uint32_t continueMode = 0; /* flashc exit continue mode, needed a read with dummy */ + + if (base->mXip == NULL) + return -1; + + cmd.len = 1; + cmd.line = 1; //not in QPI + addr.len = 3; + switch (mode) + { + /* !!! NOTICE: m7~m0 is count to dummy byte. !!! */ + case FLASH_READ_NORMAL_MODE: + cmd.data = FLASH_INSTRUCTION_READ; + addr.line = 1; + data.line = 1; + dummy.len = 0; + dummy.line = 1; + continueMode = 0; + break; + case FLASH_READ_FAST_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ; + addr.line = 1; + data.line = 1; + dummy.len = 1; + dummy.line = 1; + continueMode = 0; + break; + case FLASH_READ_DUAL_O_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_DO; + addr.line = 1; + data.line = 2; + dummy.len = 1; + dummy.line = 1; + continueMode = 0; + break; + case FLASH_READ_DUAL_IO_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_DIO; + addr.line = 2; + data.line = 2; + dummy.len = 1; + dummy.line = 2; + break; + case FLASH_READ_QUAD_O_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_QO; + addr.line = 1; + data.line = 4; + dummy.len = 1; + dummy.line = 1; + continueMode = 0; + break; + case FLASH_READ_QUAD_IO_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_QIO; + addr.line = 4; + data.line = 4; + dummy.len = 3; + dummy.line = 4; + break; + case FLASH_READ_QPI_MODE: + cmd.data = FLASH_INSTRUCTION_FAST_READ_QIO; + cmd.line = 4; + data.line = 4; + dummy.len = base->mDummyCount; + dummy.line = 4; + addr.line = 4; + break; + default: + return -1; + } + + base->mXip->setCmd(base->mXip, &cmd, &addr, &dummy, &data); + base->mXip->setContinue(base->mXip, continueMode, NULL); + /*TODO: xip set delay*/ + + return 0; +} + +int defaultSetFreq(FlashChipBase *base, uint32_t freq) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + return base->mDriver->setFreq(base->mDriver, freq); +} + +int defaultSwitchReadMode(FlashChipBase *base, FlashReadMode mode) +{ + PCHECK(base); + uint8_t status; + int ret; + + if (!(mode & base->mReadSupport)) { + FLASH_NOTSUPPORT(); + return HAL_INVALID; + } + + if (mode == FLASH_READ_QUAD_O_MODE || mode == FLASH_READ_QUAD_IO_MODE || mode == FLASH_READ_QPI_MODE) + { + ret = base->readStatus(base, FLASH_STATUS2, &status); + if (ret < 0) + return -1; + status |= 1 << 1; + ret = base->writeStatus(base, FLASH_STATUS2, &status); + } + else + { + ret = base->readStatus(base, FLASH_STATUS2, &status); + if (ret < 0) + return -1; + status &= ~(1 << 1); + ret = base->writeStatus(base, FLASH_STATUS2, &status); + } + + return ret; +} + +int defaultEnableXIP(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + /*TODO:*/ + + return 0; +} + +int defaultDisableXIP(FlashChipBase *base) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + /*TODO:*/ + + return 0; +} + +int defaultIsBusy(FlashChipBase *base) +{ + PCHECK(base); + uint8_t status; + int ret; + + ret = base->readStatus(base, FLASH_STATUS1, &status); + if (ret < 0) + return -1; + + return !!(status & (1 << 0)); +} + +static int defaultSetReadParam(FlashChipBase *base, uint8_t param) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + cmd.data = FLASH_INSTRUCTION_SRP; + data.pdata = (uint8_t *)¶m; + data.line = 4; + data.len = 1; + return base->driverWrite(base, &cmd, NULL, NULL, &data); +} + +int defaultControl(FlashChipBase *base, int op, void *param) +{ + PCHECK(base); + INSTRUCT_ZCREATE(cmd, addr, dummy, data); + + switch (op) + { + case DEFAULT_FLASH_SET_QPI_READ_P5P4: + if (*(uint8_t *)param > 0x03) + return -1; + defaultSetReadParam(base, (*(uint8_t *)param) << 4); + break; + } + + return 0; +} + +FlashEraseMode defaultGetMinEraseSize(FlashChipBase *base) +{ + PCHECK(base); + + if (base->mEraseSizeSupport & FLASH_ERASE_4KB) + return FLASH_ERASE_4KB; + else if (base->mEraseSizeSupport & FLASH_ERASE_32KB) + return FLASH_ERASE_32KB; + else if (base->mEraseSizeSupport & FLASH_ERASE_64KB) + return FLASH_ERASE_64KB; + else + return FLASH_ERASE_NOSUPPORT; +} + + +/* + Default Flash Chip, Only support basic Interface +*/ +#if 0 +typedef struct DefaultFlash +{ + FlashChipBase base; +} DefaultFlash; + +static int DefaultFlashInit(FlashChipBase * base) +{ + PCHECK(base); + + DefaultFlash *impl = __containerof(base, DefaultFlash, base); + impl->base.writeEnable = defaultWriteEnable; + impl->base.writeDisable = defaultWriteDisable; + impl->base.readStatus = defaultReadStatus; + impl->base.erase = defaultErase; + impl->base.jedecID = defaultGetJedecID; + impl->base.pageProgram = defaultPageProgram; + impl->base.read = defaultRead; + + impl->base.driverWrite = defaultDriverWrite; + impl->base.driverRead = defaultDriverRead; + impl->base.xipDriverCfg = defaultXipDriverCfg; + impl->base.setFreq = defaultSetFreq; + impl->base.switchReadMode = defaultSwitchReadMode; + impl->base.enableXIP = defaultEnableXIP; + impl->base.disableXIP = defaultDisableXIP; + impl->base.isBusy = defaultIsBusy; + impl->base.control = defaultControl; + impl->base.minEraseSize = defaultGetMinEraseSize; + + impl->base.writeStatus = NULL; + impl->base.suspendErasePageprogram = NULL; + impl->base.resumeErasePageprogram = NULL; + impl->base.powerDown = NULL; + impl->base.releasePowerDown = NULL; + impl->base.enableQPIMode = NULL; + impl->base.disableQPIMode = NULL; + impl->base.enableReset = NULL; + impl->base.reset = NULL; + impl->base.uniqueID = NULL; + /*TODO: a NULL interface for showing invalid interface*/ + + FLASH_DEBUG("default chip inited"); + + return 0; +} + +static int DefaultFlashDeinit(FlashChipBase * base) +{ + PCHECK(base); + + DefaultFlash *impl = __containerof(base, DefaultFlash, base); + free(impl); + + return 0; +} + +static FlashChipBase *DefaultFlashCtor(void) +{ + DefaultFlash *impl = malloc(sizeof(DefaultFlash)); + PCHECK(impl); + memset(impl, 0, sizeof(DefaultFlash)); + + FLASH_DEBUG("create default chip"); + + impl->base.mPageSize = 256; + impl->base.mSize = -1; + impl->base.mMaxFreq = -1; + impl->base.mMaxReadFreq = -1; +/* + impl->base.mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_CHIP; + impl->base.mPageProgramSupport = FLASH_PAGEPROGRAM; + impl->base.mReadStausSupport = FLASH_STATUS1; + impl->base.mWriteStatusSupport = FLASH_STATUS1; + impl->base.mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE; +*/ + impl->base.mEraseSizeSupport = FLASH_ERASE_4KB | FLASH_ERASE_32KB | FLASH_ERASE_64KB | FLASH_ERASE_CHIP; + impl->base.mPageProgramSupport = FLASH_PAGEPROGRAM; + impl->base.mReadStausSupport = FLASH_STATUS1; + impl->base.mWriteStatusSupport = FLASH_STATUS1; + impl->base.mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE; + + return &impl->base; +} + +static FlashChipCtor DefaultFlashChip = { + .mJedecId = 0, + .create = DefaultFlashCtor, + .init = DefaultFlashInit, + .destory = DefaultFlashDeinit, +}; +#endif diff --git a/platform/mcu/xr871/src/driver/chip/flashchip/flash_default.c b/platform/mcu/xr871/src/driver/chip/flashchip/flash_default.c new file mode 100644 index 0000000000..58dadf73ae --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/flashchip/flash_default.c @@ -0,0 +1,275 @@ +/* + * flash_default.c + * + * Created on: 2017821 + * Author: lijunjie + */ + +#include +#include +#include "driver/chip/flashchip/flash_chip.h" +#include "flash_default.h" +#include "../hal_base.h" +#include "sys/xr_debug.h" + + +#define FLASH_DEBUG(fmt, arg...) XR_DEBUG((DBG_OFF | XR_LEVEL_ALL), NOEXPAND, "[Flash chip debug] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define FLASH_ALERT(fmt, arg...) XR_ALERT((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash chip alert] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define FLASH_ERROR(fmt, arg...) XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash chip error] <%s : %d> " fmt "\n", __func__, __LINE__, ##arg) +#define FLASH_NOWAY() XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash chip should not be here] <%s : %d> \n", __func__, __LINE__) +#define FLASH_NOTSUPPORT() FLASH_ALERT("not support command") + + +typedef struct SimpleFlashChipCfg +{ + uint32_t mJedec; + uint32_t mSize; + + uint32_t mEraseSizeSupport; + uint16_t mReadStausSupport; + uint8_t mWriteStatusSupport; + uint8_t mPageProgramSupport; + uint16_t mReadSupport; + + uint32_t mMaxFreq; + uint32_t mMaxReadFreq; +} SimpleFlashChipCfg; + +static const SimpleFlashChipCfg simpleFlashChip[] = +{ +/* +* #ifdef FLASH_xxxxx +* { +* .mJedec = 0x ID7-ID0 ID15-ID8 M7-M0 from jedec id, +* .mSize = total flash memory size, +* .mEraseSizeSupport = the flash erase commands is supported, +* .mPageProgramSupport = the flash pageprogram commands is supported, +* .mReadStausSupport = the flash status registers can be read, +* .mWriteStatusSupport = the flash status registers can be written, +* .mReadSupport = the flash read commands (modes) is supported, +* .mMaxFreq = max operation frequency to flash, +* .mMaxReadFreq = max read command frequency(only read command: 0x03h), +* }, +* #endif +*/ + { + /* default config must be at first */ + .mJedec = 0, /* ID7-ID0 ID15-ID8 M7-M0 */ + .mSize = -1, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_32KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM, + .mReadStausSupport = FLASH_STATUS1 | FLASH_STATUS2 | FLASH_STATUS3, + .mWriteStatusSupport = FLASH_STATUS1 | FLASH_STATUS2 | FLASH_STATUS3, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE + | FLASH_READ_DUAL_IO_MODE | FLASH_READ_QUAD_O_MODE | FLASH_READ_QUAD_IO_MODE | FLASH_READ_QPI_MODE, + .mMaxFreq = -1, + .mMaxReadFreq = -1, + }, +#ifdef FLASH_PN25F16B + { + /* FLASH_PN25F16B */ + .mJedec = 0x15405E, + .mSize = 32 * 16 * 0x1000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_32KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM, + .mReadStausSupport = FLASH_STATUS1, + .mWriteStatusSupport = FLASH_STATUS1, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE, + .mMaxFreq = 100 * 1000 * 1000, + .mMaxReadFreq = 55 * 1000 * 1000, + }, +#endif +#ifdef FLASH_M25P64 + { + /* FLASH_M25P64 */ + .mJedec = 0x172020, + .mSize = 128 * 0x10000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM, + .mReadStausSupport = FLASH_STATUS1, + .mWriteStatusSupport = 0, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE, + .mMaxFreq = 50 * 1000 * 1000, + .mMaxReadFreq = 20 * 1000 * 1000, + }, +#endif +#ifdef FLASH_W25Q16FW + { + /* FLASH_W25Q16FW */ + .mJedec = 0x1560EF, + .mSize = 32 *16 * 0x1000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_32KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM, + .mReadStausSupport = FLASH_STATUS1 | FLASH_STATUS2 | FLASH_STATUS3, + .mWriteStatusSupport = FLASH_STATUS1 | FLASH_STATUS2 | FLASH_STATUS3, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE + | FLASH_READ_DUAL_IO_MODE | FLASH_READ_QUAD_O_MODE | FLASH_READ_QUAD_IO_MODE, + .mMaxFreq = 80 * 1000 * 1000, + .mMaxReadFreq = 50 * 1000 * 1000, + }, +#endif +#ifdef FLASH_PN25F08 + { + /* FLASH_PN25F08 */ + .mJedec = 0x1440E0, + .mSize = 16 * 16 * 0x1000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_32KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM, + .mReadStausSupport = FLASH_STATUS1 | FLASH_STATUS2, + .mWriteStatusSupport = FLASH_STATUS1 /* write status2 need to rewrite writeStatus */, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE + | FLASH_READ_DUAL_IO_MODE | FLASH_READ_QUAD_O_MODE | FLASH_READ_QUAD_IO_MODE, + .mMaxFreq = 108 * 1000 * 1000, + .mMaxReadFreq = 55 * 1000 * 1000, + }, +#endif +#ifdef FLASH_PN25F16 + { + /* FLASH_PN25F16 */ + .mJedec = 0x1540E0, + .mSize = 32 * 16 * 0x1000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_32KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM, + .mReadStausSupport = FLASH_STATUS1 | FLASH_STATUS2, + .mWriteStatusSupport = FLASH_STATUS1 /* write status2 need to rewrite writeStatus */, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE + | FLASH_READ_DUAL_IO_MODE | FLASH_READ_QUAD_O_MODE | FLASH_READ_QUAD_IO_MODE, + .mMaxFreq = 108 * 1000 * 1000, + .mMaxReadFreq = 55 * 1000 * 1000, + }, +#endif +#ifdef FLASH_MX25L1636E + { + /* FLASH_MX25L1636E */ + .mJedec = 0x1525C2, + .mSize = 32 * 16 * 0x1000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM /* QPP need to rewrite pageProgram */, + .mReadStausSupport = FLASH_STATUS1, + .mWriteStatusSupport = FLASH_STATUS1, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE | FLASH_READ_DUAL_O_MODE + | FLASH_READ_DUAL_IO_MODE | FLASH_READ_QUAD_IO_MODE, + .mMaxFreq = 108 * 1000 * 1000, + .mMaxReadFreq = 50 * 1000 * 1000, + }, +#endif +#ifdef FLASH_MX25L1633E + { + /* FLASH_MX25L1633E */ + .mJedec = 0x1524C2, + .mSize = 32 * 16 * 0x1000, + .mEraseSizeSupport = FLASH_ERASE_64KB | FLASH_ERASE_4KB | FLASH_ERASE_CHIP, + .mPageProgramSupport = FLASH_PAGEPROGRAM /* QPP need to rewrite pageProgram */, + .mReadStausSupport = FLASH_STATUS1, + .mWriteStatusSupport = FLASH_STATUS1, + .mReadSupport = FLASH_READ_NORMAL_MODE | FLASH_READ_FAST_MODE + | FLASH_READ_DUAL_IO_MODE | FLASH_READ_QUAD_IO_MODE, + .mMaxFreq = 85 * 1000 * 1000, + .mMaxReadFreq = 33 * 1000 * 1000, + }, +#endif +}; + + +/* + Default Flash Chip, Only support basic Interface +*/ +typedef struct DefaultFlash +{ + FlashChipBase base; +} DefaultFlash; + +static int DefaultFlashInit(FlashChipBase * base) +{ + PCHECK(base); + + DefaultFlash *impl = __containerof(base, DefaultFlash, base); + + impl->base.writeEnable = defaultWriteEnable; + impl->base.writeDisable = defaultWriteDisable; + impl->base.readStatus = defaultReadStatus; + impl->base.erase = defaultErase; + impl->base.jedecID = defaultGetJedecID; + impl->base.pageProgram = defaultPageProgram; + impl->base.read = defaultRead; + + impl->base.driverWrite = defaultDriverWrite; + impl->base.driverRead = defaultDriverRead; + impl->base.xipDriverCfg = defaultXipDriverCfg; + impl->base.setFreq = defaultSetFreq; + impl->base.switchReadMode = defaultSwitchReadMode; + impl->base.enableXIP = defaultEnableXIP; + impl->base.disableXIP = defaultDisableXIP; + impl->base.isBusy = defaultIsBusy; + impl->base.control = defaultControl; + impl->base.minEraseSize = defaultGetMinEraseSize; + impl->base.writeStatus = defaultWriteStatus; + impl->base.enableQPIMode = defaultEnableQPIMode; + impl->base.disableQPIMode = defaultDisableQPIMode; +// impl->base.enableReset = defaultEnableReset; + impl->base.reset = defaultReset; + + impl->base.suspendErasePageprogram = NULL; + impl->base.resumeErasePageprogram = NULL; + impl->base.powerDown = NULL; + impl->base.releasePowerDown = NULL; + impl->base.uniqueID = NULL; + /*TODO: a NULL interface for showing invalid interface*/ + + FLASH_DEBUG("default chip inited"); + + return 0; +} + +static int DefaultFlashDeinit(FlashChipBase * base) +{ + PCHECK(base); + + DefaultFlash *impl = __containerof(base, DefaultFlash, base); + free(impl); + + return 0; +} + +static FlashChipBase *DefaultFlashCtor(uint32_t arg) +{ + DefaultFlash *impl = malloc(sizeof(DefaultFlash)); +// SimpleFlashChipCfg *cfg = NULL; + uint32_t simpleChipVecSize = sizeof(simpleFlashChip) / sizeof(simpleFlashChip[0]); + uint32_t i = simpleChipVecSize; + + PCHECK(impl); + HAL_Memset(impl, 0, sizeof(DefaultFlash)); + + while (--i > 0) + { + if (simpleFlashChip[i].mJedec == arg) + break; + } + const SimpleFlashChipCfg *cfg = &simpleFlashChip[i]; + if (i == 0) + FLASH_ALERT("!!this chip is not in my support chip list, using default flash chip now!!"); + FLASH_DEBUG("create simple flash chip%d: 0x%x", i, cfg->mJedec); + + impl->base.mJedec = cfg->mJedec; + impl->base.mPageSize = 256; + impl->base.mSize = cfg->mSize; + impl->base.mMaxFreq = cfg->mMaxFreq; + impl->base.mMaxReadFreq = cfg->mMaxReadFreq; + impl->base.mEraseSizeSupport = cfg->mEraseSizeSupport; + impl->base.mPageProgramSupport = cfg->mPageProgramSupport; + impl->base.mReadStausSupport = cfg->mReadStausSupport; + impl->base.mWriteStatusSupport = cfg->mWriteStatusSupport; + impl->base.mReadSupport = cfg->mReadSupport; + impl->base.mFlashStatus = 0; + impl->base.mDummyCount = 1; + + return &impl->base; +} + +FlashChipCtor DefaultFlashChip = { + .mJedecId = 0, + .create = DefaultFlashCtor, + .init = DefaultFlashInit, + .destory = DefaultFlashDeinit, +}; diff --git a/platform/mcu/xr871/src/driver/chip/flashchip/flash_default.h b/platform/mcu/xr871/src/driver/chip/flashchip/flash_default.h new file mode 100644 index 0000000000..5f22cb27d7 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/flashchip/flash_default.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FLASH_DEFAULT_H_ +#define FLASH_DEFAULT_H_ + +#include "driver/chip/flashchip/flash_chip.h" + +#define FLASH_M25P64 + +#define FLASH_PN25F16B + +#define FLASH_W25Q16FW + +#define FLASH_PN25F08 + +#define FLASH_PN25F16 + + +extern FlashChipCtor DefaultFlashChip; + + +#endif diff --git a/platform/mcu/xr871/src/driver/chip/hal_adc.c b/platform/mcu/xr871/src/driver/chip/hal_adc.c new file mode 100644 index 0000000000..28cbbb2e70 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_adc.c @@ -0,0 +1,879 @@ +/** + * @file hal_adc.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_adc.h" +#include "hal_base.h" +#include "pm/pm.h" + +typedef enum { + ADC_STATE_INVALID = 0, + ADC_STATE_INIT = 1, /* Initializing */ + ADC_STATE_DEINIT = 2, /* Deinitializing */ + ADC_STATE_READY = 3, + ADC_STATE_BUSY = 4 +} ADC_State; + +typedef struct { + uint16_t chanPinMux; + ADC_State state; + + uint32_t lowPending; + uint32_t highPending; + uint32_t dataPending; + + ADC_IRQCallback IRQCallback[ADC_CHANNEL_NUM]; + void *arg[ADC_CHANNEL_NUM]; +} ADC_Private; + +static ADC_Private gADCPrivate; + +#define ADC_ASSERT_CHANNEL(chan) HAL_ASSERT_PARAM((chan) < ADC_CHANNEL_NUM) + +#ifdef CONFIG_PM +static ADC_InitParam hal_adc_param; +static struct adc_chan_config{ + uint8_t is_config; + uint8_t select; + uint8_t mode; + uint32_t lowValue; + uint32_t highValue; +} hal_adc_chan_config[ADC_CHANNEL_NUM]; +static uint8_t hal_adc_suspending = 0; + +static int adc_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + hal_adc_suspending = 1; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + HAL_ADC_DeInit(); + break; + default: + break; + } + + return 0; +} + +static int adc_resume(struct soc_device *dev, enum suspend_state_t state) +{ + static ADC_Channel chan; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_ADC_Init(&hal_adc_param); + for (chan = ADC_CHANNEL_0; chan < ADC_CHANNEL_NUM; chan++) { + if (hal_adc_chan_config[chan].is_config) + HAL_ADC_ConfigChannel(chan, + (ADC_Select)hal_adc_chan_config[chan].select, + (ADC_IRQMode)hal_adc_chan_config[chan].mode, + hal_adc_chan_config[chan].lowValue, + hal_adc_chan_config[chan].highValue); + } + break; + default: + break; + } + + hal_adc_suspending = 0; + + return 0; +} + +static struct soc_device_driver adc_drv = { + .name = "adc", + .suspend_noirq = adc_suspend, + .resume_noirq = adc_resume, +}; + +static struct soc_device adc_dev = { + .name = "adc", + .driver = &adc_drv, +}; + +#define ADC_DEV (&adc_dev) +#else +#define ADC_DEV NULL +#endif + +__STATIC_INLINE void ADC_SetChanPinMux(ADC_Channel chan) +{ + HAL_SET_BIT(gADCPrivate.chanPinMux, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_ClrChanPinMux(ADC_Channel chan) +{ + HAL_CLR_BIT(gADCPrivate.chanPinMux, HAL_BIT(chan)); +} + +__STATIC_INLINE uint8_t ADC_GetChanPinMux(ADC_Channel chan) +{ + return !!HAL_GET_BIT(gADCPrivate.chanPinMux, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_SetSampleRate(uint32_t fsDiv, uint32_t tAcq) +{ + ADC->SAMPLE_RATE = (HAL_GET_BIT(fsDiv << ADC_FS_DIV_SHIFT, ADC_FS_DIV_MASK) + | HAL_GET_BIT(tAcq << ADC_TACQ_SHIFT, ADC_TACQ_MASK)); +} + +__STATIC_INLINE void ADC_SetFirstDelay(uint32_t firstDelay) +{ + HAL_MODIFY_REG(ADC->CTRL, ADC_FIRST_DELAY_MASK, + HAL_GET_BIT(firstDelay << ADC_FIRST_DELAY_SHIFT, ADC_FIRST_DELAY_MASK)); +} + +__STATIC_INLINE void ADC_SetOPBias(uint32_t opBias) +{ + HAL_MODIFY_REG(ADC->CTRL, ADC_OP_BIAS_MASK, + HAL_GET_BIT(opBias << ADC_OP_BIAS_SHIFT, ADC_OP_BIAS_MASK)); +} + +__STATIC_INLINE void ADC_SetWorkMode(ADC_WorkMode workMode) +{ + HAL_MODIFY_REG(ADC->CTRL, ADC_WORK_MODE_MASK, + HAL_GET_BIT(workMode << ADC_WORK_MODE_SHIFT, ADC_WORK_MODE_MASK)); +} + +__STATIC_INLINE void ADC_EnableCalib(void) +{ + HAL_SET_BIT(ADC->CTRL, ADC_CALIB_EN_BIT); +} + +__STATIC_INLINE uint32_t ADC_GetCalibState(void) +{ + return !!HAL_GET_BIT(ADC->CTRL, ADC_CALIB_EN_BIT); +} + +__STATIC_INLINE void ADC_EnableADC(void) +{ + HAL_SET_BIT(ADC->CTRL, ADC_EN_BIT); +} + +__STATIC_INLINE void ADC_DisableADC(void) +{ + HAL_CLR_BIT(ADC->CTRL, ADC_EN_BIT); +} + +__STATIC_INLINE void ADC_EnableVbatDetec(void) +{ + HAL_SET_BIT(ADC->CTRL, ADC_VBAT_EN_BIT); +} + +__STATIC_INLINE void ADC_DisableVbatDetec(void) +{ + HAL_CLR_BIT(ADC->CTRL, ADC_VBAT_EN_BIT); +} + +__STATIC_INLINE void ADC_EnableLDO(void) +{ + HAL_SET_BIT(ADC->CTRL, ADC_LDO_EN_BIT); +} + +__STATIC_INLINE void ADC_DisableLDO(void) +{ + HAL_CLR_BIT(ADC->CTRL, ADC_LDO_EN_BIT); +} + +__STATIC_INLINE void ADC_EnableChanCmp(ADC_Channel chan) +{ + HAL_SET_BIT(ADC->CMP_SEL_EN, HAL_BIT(ADC_CMP_EN_SHIFT + chan)); +} + +__STATIC_INLINE void ADC_DisableChanCmp(ADC_Channel chan) +{ + HAL_CLR_BIT(ADC->CMP_SEL_EN, HAL_BIT(ADC_CMP_EN_SHIFT + chan)); +} + +__STATIC_INLINE void ADC_DisableAllChanCmp(void) +{ + HAL_CLR_BIT(ADC->CMP_SEL_EN, ADC_CMP_EN_MASK); +} + +__STATIC_INLINE void ADC_EnableChanSel(ADC_Channel chan) +{ + HAL_SET_BIT(ADC->CMP_SEL_EN, HAL_BIT(ADC_SEL_EN_SHIFT + chan)); +} + +__STATIC_INLINE void ADC_DisableChanSel(ADC_Channel chan) +{ + HAL_CLR_BIT(ADC->CMP_SEL_EN, HAL_BIT(ADC_SEL_EN_SHIFT + chan)); +} + +__STATIC_INLINE void ADC_DisableAllChanSel(void) +{ + HAL_CLR_BIT(ADC->CMP_SEL_EN, ADC_SEL_EN_MASK); +} + +__STATIC_INLINE void ADC_EnableChanLowIRQ(ADC_Channel chan) +{ + HAL_SET_BIT(ADC->LOW_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_DisableChanLowIRQ(ADC_Channel chan) +{ + HAL_CLR_BIT(ADC->LOW_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE uint8_t ADC_GetChanLowIRQ(ADC_Channel chan) +{ + return !!HAL_GET_BIT(ADC->LOW_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_EnableChanHighIRQ(ADC_Channel chan) +{ + HAL_SET_BIT(ADC->HIGH_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_DisableChanHighIRQ(ADC_Channel chan) +{ + HAL_CLR_BIT(ADC->HIGH_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE uint8_t ADC_GetChanHighIRQ(ADC_Channel chan) +{ + return !!HAL_GET_BIT(ADC->HIGH_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_EnableChanDataIRQ(ADC_Channel chan) +{ + HAL_SET_BIT(ADC->DATA_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_DisableChanDataIRQ(ADC_Channel chan) +{ + HAL_CLR_BIT(ADC->DATA_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE uint8_t ADC_GetChanDataIRQ(ADC_Channel chan) +{ + return !!HAL_GET_BIT(ADC->DATA_CONFIG, HAL_BIT(chan)); +} + +__STATIC_INLINE void ADC_DisableAllChanIRQ(void) +{ + HAL_CLR_BIT(ADC->LOW_CONFIG, ADC_LOW_IRQ_MASK); + HAL_CLR_BIT(ADC->HIGH_CONFIG, ADC_HIGH_IRQ_MASK); + HAL_CLR_BIT(ADC->DATA_CONFIG, ADC_DATA_IRQ_MASK); +} + +__STATIC_INLINE uint32_t ADC_GetLowPending(void) +{ + return HAL_GET_BIT(ADC->LOW_STATUS, ADC_LOW_PENDING_MASK); +} + +__STATIC_INLINE void ADC_ClrLowPending(uint32_t lowPending) +{ + ADC->LOW_STATUS = lowPending; +} + +__STATIC_INLINE uint32_t ADC_GetHighPending(void) +{ + return HAL_GET_BIT(ADC->HIGH_STATUS, ADC_HIGH_PENDING_MASK); +} + +__STATIC_INLINE void ADC_ClrHighPending(uint32_t highPending) +{ + ADC->HIGH_STATUS = highPending; +} + +__STATIC_INLINE uint32_t ADC_GetDataPending(void) +{ + return HAL_GET_BIT(ADC->DATA_STATUS, ADC_DATA_PENDING_MASK); +} + +__STATIC_INLINE void ADC_ClrDataPending(uint32_t dataPending) +{ + ADC->DATA_STATUS = dataPending; +} + +__STATIC_INLINE void ADC_SetHighValue(ADC_Channel chan, uint32_t value) +{ + HAL_MODIFY_REG(ADC->CMP_DATA[chan], ADC_HIGH_DATA_MASK, + HAL_GET_BIT(value << ADC_HIGH_DATA_SHIFT, ADC_HIGH_DATA_MASK)); +} + +__STATIC_INLINE void ADC_SetLowValue(ADC_Channel chan, uint32_t value) +{ + HAL_MODIFY_REG(ADC->CMP_DATA[chan], ADC_LOW_DATA_MASK, + HAL_GET_BIT(value << ADC_LOW_DATA_SHIFT, ADC_LOW_DATA_MASK)); +} + +__STATIC_INLINE uint32_t ADC_GetValue(ADC_Channel chan) +{ + return HAL_GET_BIT(ADC->DATA[chan], ADC_DATA_MASK); +} + +void GPADC_IRQHandler(void) +{ + uint32_t i; + + gADCPrivate.lowPending = ADC_GetLowPending(); + gADCPrivate.highPending = ADC_GetHighPending(); + gADCPrivate.dataPending = ADC_GetDataPending(); + + ADC_ClrLowPending(gADCPrivate.lowPending); + ADC_ClrHighPending(gADCPrivate.highPending); + ADC_ClrDataPending(gADCPrivate.dataPending); + + for (i = ADC_CHANNEL_0; i < ADC_CHANNEL_NUM; i++) { + if (((HAL_GET_BIT(gADCPrivate.dataPending, HAL_BIT(i)) && ADC_GetChanDataIRQ(i)) + || (HAL_GET_BIT(gADCPrivate.lowPending, HAL_BIT(i)) && ADC_GetChanLowIRQ(i)) + || (HAL_GET_BIT(gADCPrivate.highPending, HAL_BIT(i)) && ADC_GetChanHighIRQ(i))) + && (gADCPrivate.IRQCallback[i])) { + gADCPrivate.IRQCallback[i](gADCPrivate.arg[i]); + } + } +} + +/** + * @brief Initialize the ADC according to the specified parameters + * @param[in] initParam Pointer to ADC_InitParam structure + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_Init(ADC_InitParam *initParam) +{ + unsigned long flags; + ADC_Private *priv; + uint32_t hoscClk; + uint32_t fsDiv; + uint32_t tAcq; + + if ((initParam->freq < 1000) | (initParam->freq > 1000000)) { + HAL_ERR("invalid parameter, freq: %d\n", initParam->freq); + return HAL_ERROR; + } + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if (priv->state == ADC_STATE_INVALID) + priv->state = ADC_STATE_INIT; + else + priv = NULL; + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_BUSY; + } + +#ifdef CONFIG_PM + if (!hal_adc_suspending) { + pm_register_ops(ADC_DEV); + HAL_Memcpy(&hal_adc_param, initParam, sizeof(ADC_InitParam)); + HAL_Memset(hal_adc_chan_config, 0, ADC_CHANNEL_NUM * sizeof(struct adc_chan_config)); + } +#endif + + priv->chanPinMux = 0; + priv->lowPending = 0; + priv->highPending = 0; + priv->dataPending = 0; +#ifdef CONFIG_PM + if (!hal_adc_suspending) { + HAL_Memset(priv->IRQCallback, 0, ADC_CHANNEL_NUM * sizeof(ADC_IRQCallback)); + HAL_Memset(priv->arg, 0, ADC_CHANNEL_NUM * sizeof(void *)); + } +#else + HAL_Memset(priv->IRQCallback, 0, ADC_CHANNEL_NUM * sizeof(ADC_IRQCallback)); + HAL_Memset(priv->arg, 0, ADC_CHANNEL_NUM * sizeof(void *)); +#endif + + /* enable ADC clock and release reset */ + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_GPADC); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_GPADC); + HAL_CCM_GPADC_SetMClock(CCM_APB_PERIPH_CLK_SRC_LFCLK, CCM_PERIPH_CLK_DIV_N_1, CCM_PERIPH_CLK_DIV_M_1); + HAL_CCM_GPADC_EnableMClock(); + + hoscClk = HAL_GetHFClock(); + fsDiv = hoscClk / initParam->freq - 1; + if (initParam->freq <= 300000) + tAcq = hoscClk / 500000 - 1; + else if (initParam->freq <= 600000) + tAcq = hoscClk / 1000000 - 1; + else + tAcq = hoscClk / 2000000 - 1; + ADC_SetSampleRate(fsDiv, tAcq); + + ADC_SetFirstDelay(initParam->delay); + ADC_SetWorkMode(ADC_CONTI_CONV); + ADC_EnableLDO(); + + ADC_DisableAllChanSel(); + ADC_DisableAllChanCmp(); + ADC_DisableAllChanIRQ(); + + ADC_EnableCalib(); + while (ADC_GetCalibState()) + ; + + /* enable NVIC IRQ */ + HAL_NVIC_SetPriority(GPADC_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(GPADC_IRQn); + + flags = HAL_EnterCriticalSection(); + priv->state = ADC_STATE_READY; + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + +/** + * @brief DeInitialize the ADC + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_DeInit(void) +{ + unsigned long flags; + ADC_Private *priv; + ADC_Channel chan; + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if (priv->state == ADC_STATE_READY) + priv->state = ADC_STATE_DEINIT; + else + priv = NULL; + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } + +#ifdef CONFIG_PM + if (!hal_adc_suspending) { + pm_unregister_ops(ADC_DEV); + } +#endif + + HAL_NVIC_DisableIRQ(GPADC_IRQn); + + ADC_DisableLDO(); + + /* disable ADC clock and force reset */ + HAL_CCM_GPADC_DisableMClock(); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_GPADC); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_GPADC); + + if (gADCPrivate.chanPinMux) { + for (chan = ADC_CHANNEL_0; chan < ADC_CHANNEL_NUM; chan++) { + if (ADC_GetChanPinMux(chan) && (chan != ADC_CHANNEL_8)) { + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_ADC, chan), 0); + ADC_ClrChanPinMux(chan); + if (!gADCPrivate.chanPinMux) + break; + } + } + } + + flags = HAL_EnterCriticalSection(); + priv->state = ADC_STATE_INVALID; + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + +/** + * @brief The specified ADC channel convert once in polling mode + * @param[in] chan The specified ADC channel + * @param[in] data Pointer to the output data + * @param[in] msec Timeout value in millisecond of conversion + * HAL_WAIT_FOREVER for no timeout + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_Conv_Polling(ADC_Channel chan, uint32_t *data, uint32_t msec) +{ + unsigned long flags; + ADC_Private *priv; + uint32_t stopTime; + uint8_t isTimeout; + + ADC_ASSERT_CHANNEL(chan); + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if (priv->state == ADC_STATE_READY) + priv->state = ADC_STATE_BUSY; + else + priv = NULL; + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } + + if ((!ADC_GetChanPinMux(chan)) && (chan != ADC_CHANNEL_8)) { + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_ADC, chan), 0); + ADC_SetChanPinMux(chan); + } + + ADC_DisableAllChanSel(); + ADC_DisableAllChanCmp(); + ADC_DisableAllChanIRQ(); + + if (chan == ADC_CHANNEL_8) + ADC_EnableVbatDetec(); + + ADC_EnableChanSel(chan); + + if (msec == HAL_WAIT_FOREVER) + stopTime = 0xFFFFFFFF; + else + stopTime = HAL_TicksToMSecs(HAL_Ticks()) + msec; + + if (stopTime < msec) { + HAL_ERR("stopTime overflow.\n"); + return HAL_ERROR; + } + + isTimeout = 1; + ADC_EnableADC(); + while (HAL_TicksToMSecs(HAL_Ticks()) <= stopTime) { + if (HAL_GET_BIT(ADC_GetDataPending(), HAL_BIT(chan))) { + *data = ADC_GetValue(chan); + ADC_ClrDataPending(ADC_GetDataPending()); + isTimeout = 0; + break; + } + } + ADC_DisableADC(); + ADC_DisableChanSel(chan); + + if (chan == ADC_CHANNEL_8) + ADC_DisableVbatDetec(); + + if (ADC_GetChanPinMux(chan) && (chan != ADC_CHANNEL_8)) { + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_ADC, chan), 0); + ADC_ClrChanPinMux(chan); + } + + flags = HAL_EnterCriticalSection(); + priv->state = ADC_STATE_READY; + HAL_ExitCriticalSection(flags); + + if (isTimeout) { + HAL_WRN("ADC timeout.\n"); + return HAL_TIMEOUT; + } else { + return HAL_OK; + } +} + +/** + * @brief Enable interrupt callback function for the specified ADC channel + * @param[in] chan The specified ADC channel + * @param[in] cb The interrupt callback function + * @param[in] arg Argument of the interrupt callback function + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_EnableIRQCallback(ADC_Channel chan, ADC_IRQCallback cb, void *arg) +{ + unsigned long flags; + ADC_Private *priv; + + ADC_ASSERT_CHANNEL(chan); + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if ((priv->state == ADC_STATE_READY) || (priv->state == ADC_STATE_BUSY)) { + priv->arg[chan] = arg; + priv->IRQCallback[chan] = cb; + } else { + priv = NULL; + } + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable interrupt callback function for the specified ADC channel + * @param[in] chan The specified ADC channel + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_DisableIRQCallback(ADC_Channel chan) +{ + unsigned long flags; + ADC_Private *priv; + + ADC_ASSERT_CHANNEL(chan); + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if ((priv->state == ADC_STATE_READY) || (priv->state == ADC_STATE_BUSY)) { + priv->IRQCallback[chan] = NULL; + priv->arg[chan] = NULL; + } else { + priv = NULL; + } + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the specified ADC channel for conversion in interrupt mode + * @param[in] chan The specified ADC channel + * @param[in] select ADC channel selected state + * @param[in] mode ADC interrupt mode + * @param[in] lowValue lower limit value in interrupt mode of ADC_IRQ_LOW, + * ADC_IRQ_LOW_DATA, ADC_IRQ_LOW_HIGH or ADC_IRQ_LOW_HIGH_DATA + * @param[in] highValue Upper limit value in interrupt mode of ADC_IRQ_HIGH, + * ADC_IRQ_HIGH_DATA, ADC_IRQ_LOW_HIGH or ADC_IRQ_LOW_HIGH_DATA + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_ConfigChannel(ADC_Channel chan, ADC_Select select, ADC_IRQMode mode, uint32_t lowValue, uint32_t highValue) +{ + unsigned long flags; + + ADC_ASSERT_CHANNEL(chan); + + if (((mode == ADC_IRQ_LOW_HIGH_DATA) || (mode == ADC_IRQ_LOW_HIGH)) && (lowValue > highValue)) { + HAL_ERR("lowValue greater than highValue.\n"); + return HAL_ERROR; + } + +#ifdef CONFIG_PM + hal_adc_chan_config[chan].is_config = 1; + hal_adc_chan_config[chan].select = select; + hal_adc_chan_config[chan].mode = mode; + hal_adc_chan_config[chan].lowValue = lowValue; + hal_adc_chan_config[chan].highValue = highValue; +#endif + + flags = HAL_EnterCriticalSection(); + if ((gADCPrivate.state == ADC_STATE_READY) || (gADCPrivate.state == ADC_STATE_BUSY)) { + if (gADCPrivate.state == ADC_STATE_BUSY) + ADC_DisableADC(); + if (select == ADC_SELECT_DISABLE) { + ADC_DisableChanSel(chan); + if (chan == ADC_CHANNEL_8) + ADC_DisableVbatDetec(); + ADC_DisableChanDataIRQ(chan); + ADC_DisableChanCmp(chan); + ADC_DisableChanLowIRQ(chan); + ADC_DisableChanHighIRQ(chan); + if (ADC_GetChanPinMux(chan) && (chan != ADC_CHANNEL_8)) { + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_ADC, chan), 0); + ADC_ClrChanPinMux(chan); + } + } else { + if ((!ADC_GetChanPinMux(chan)) && (chan != ADC_CHANNEL_8)) { + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_ADC, chan), 0); + ADC_SetChanPinMux(chan); + } + if (chan == ADC_CHANNEL_8) + ADC_EnableVbatDetec(); + ADC_EnableChanSel(chan); + switch (mode) { + case ADC_IRQ_NONE: + ADC_DisableChanDataIRQ(chan); + ADC_DisableChanCmp(chan); + ADC_DisableChanLowIRQ(chan); + ADC_DisableChanHighIRQ(chan); + break; + case ADC_IRQ_DATA: + ADC_EnableChanDataIRQ(chan); + ADC_DisableChanCmp(chan); + ADC_DisableChanLowIRQ(chan); + ADC_DisableChanHighIRQ(chan); + break; + case ADC_IRQ_LOW: + ADC_DisableChanDataIRQ(chan); + ADC_EnableChanCmp(chan); + ADC_EnableChanLowIRQ(chan); + ADC_SetLowValue(chan, lowValue); + ADC_DisableChanHighIRQ(chan); + break; + case ADC_IRQ_HIGH: + ADC_DisableChanDataIRQ(chan); + ADC_EnableChanCmp(chan); + ADC_DisableChanLowIRQ(chan); + ADC_EnableChanHighIRQ(chan); + ADC_SetHighValue(chan, highValue); + break; + case ADC_IRQ_LOW_DATA: + ADC_EnableChanDataIRQ(chan); + ADC_EnableChanCmp(chan); + ADC_EnableChanLowIRQ(chan); + ADC_SetLowValue(chan, lowValue); + ADC_DisableChanHighIRQ(chan); + break; + case ADC_IRQ_HIGH_DATA: + ADC_EnableChanDataIRQ(chan); + ADC_EnableChanCmp(chan); + ADC_DisableChanLowIRQ(chan); + ADC_EnableChanHighIRQ(chan); + ADC_SetHighValue(chan, highValue); + break; + case ADC_IRQ_LOW_HIGH: + ADC_DisableChanDataIRQ(chan); + ADC_EnableChanCmp(chan); + ADC_EnableChanLowIRQ(chan); + ADC_SetLowValue(chan, lowValue); + ADC_EnableChanHighIRQ(chan); + ADC_SetHighValue(chan, highValue); + break; + case ADC_IRQ_LOW_HIGH_DATA: + ADC_EnableChanDataIRQ(chan); + ADC_EnableChanCmp(chan); + ADC_EnableChanLowIRQ(chan); + ADC_SetLowValue(chan, lowValue); + ADC_EnableChanHighIRQ(chan); + ADC_SetHighValue(chan, highValue); + break; + } + } + if (gADCPrivate.state == ADC_STATE_BUSY) + ADC_EnableADC(); + HAL_ExitCriticalSection(flags); + return HAL_OK; + } else { + HAL_ExitCriticalSection(flags); + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } +} + +/** + * @brief Start the ADC conversion in interrupt mode + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_Start_Conv_IT(void) +{ + unsigned long flags; + ADC_Private *priv; + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if (priv->state == ADC_STATE_READY) { + ADC_EnableADC(); + priv->state = ADC_STATE_BUSY; + } else { + priv = NULL; + } + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Stop the ADC conversion in interrupt mode + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_ADC_Stop_Conv_IT(void) +{ + unsigned long flags; + ADC_Private *priv; + + flags = HAL_EnterCriticalSection(); + priv = &gADCPrivate; + if (priv->state == ADC_STATE_BUSY) { + ADC_DisableADC(); + priv->state = ADC_STATE_READY; + } else { + priv = NULL; + } + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("ADC state: %d\n", gADCPrivate.state); + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get interrupt mode of the specified ADC channel + * @param[in] chan The specified ADC channel + * @retval HAL_Status, HAL_OK on success + */ +ADC_IRQState HAL_ADC_GetIRQState(ADC_Channel chan) +{ + ADC_ASSERT_CHANNEL(chan); + + if (HAL_GET_BIT(gADCPrivate.dataPending, HAL_BIT(chan)) && ADC_GetChanDataIRQ(chan)) { + if (HAL_GET_BIT(gADCPrivate.lowPending, HAL_BIT(chan)) && ADC_GetChanLowIRQ(chan)) + return ADC_LOW_DATA_IRQ; + if (HAL_GET_BIT(gADCPrivate.highPending, HAL_BIT(chan)) && ADC_GetChanHighIRQ(chan)) + return ADC_HIGH_DATA_IRQ; + else + return ADC_DATA_IRQ; + } else { + if (HAL_GET_BIT(gADCPrivate.lowPending, HAL_BIT(chan)) && ADC_GetChanLowIRQ(chan)) + return ADC_LOW_IRQ; + if (HAL_GET_BIT(gADCPrivate.highPending, HAL_BIT(chan)) && ADC_GetChanHighIRQ(chan)) + return ADC_HIGH_IRQ; + else + return ADC_NO_IRQ; + } +} + +/** + * @brief Get digital value of the specified ADC channel + * @param[in] chan The specified ADC channel + * @return Digital value converted by the specified ADC channel + */ +uint32_t HAL_ADC_GetValue(ADC_Channel chan) +{ + ADC_ASSERT_CHANNEL(chan); + + return ADC_GetValue(chan); +} + diff --git a/platform/mcu/xr871/src/driver/chip/hal_base.h b/platform/mcu/xr871/src/driver/chip/hal_base.h new file mode 100644 index 0000000000..08c453f5a3 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_base.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_BASE_H_ +#define _DRIVER_CHIP_HAL_BASE_H_ + +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_nvic.h" +#include "driver/chip/hal_clock.h" +#include "driver/chip/hal_prcm.h" +#include "driver/chip/hal_ccm.h" +#include "driver/chip/hal_util.h" + +#include "driver/hal_board.h" +#include "driver/hal_dev.h" + +#include "hal_debug.h" +#include "hal_os.h" + +#endif /* _DRIVER_CHIP_HAL_BASE_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/hal_board.c b/platform/mcu/xr871/src/driver/chip/hal_board.c new file mode 100644 index 0000000000..5e875ed70e --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_board.c @@ -0,0 +1,65 @@ +/** + * @file hal_board.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/hal_board.h" + +static HAL_BoardIoctlCb gBoardIoctlCb; + +/** + * @brief Register HAL board I/O control callback function + * @param[in] cb Callback function to be registered + * @return The previous callback function + */ +HAL_BoardIoctlCb HAL_BoardIoctlCbRegister(HAL_BoardIoctlCb cb) +{ + HAL_BoardIoctlCb old = gBoardIoctlCb; + gBoardIoctlCb = cb; + return old; +} + +/** + * @brief Execute HAL board I/O control request + * @note The registered callback function is called actually + * @param[in] req HAL board I/O control request + * @param[in] param0 Defined by HAL board I/O control request and driver + * @param[in] param1 Defined by HAL board I/O control request and driver + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_BoardIoctl(HAL_BoardIoctlReq req, uint32_t param0, uint32_t param1) +{ + if (gBoardIoctlCb) + return gBoardIoctlCb(req, param0, param1); + else + return HAL_ERROR; +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_ccm.c b/platform/mcu/xr871/src/driver/chip/hal_ccm.c new file mode 100644 index 0000000000..38cf8b0e99 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_ccm.c @@ -0,0 +1,661 @@ +/** + * @file hal_ccmc + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal_base.h" +#include "pm/pm.h" +#include "sys/xr_debug.h" + +/** + * @brief Configure AHB2 and APB clock + * @param[in] AHB2Div AHB2 clock divider + * @param[in] APBSrc APB clock source + * @param[in] APBDiv APB clock divider + * @return None + */ +void HAL_CCM_BusSetClock(CCM_AHB2ClkDiv AHB2Div, CCM_APBClkSrc APBSrc, CCM_APBClkDiv APBDiv) +{ + CCM->CPU_BUS_CLKCFG = AHB2Div | APBSrc | APBDiv; +} + +/** + * @brief Get AHB1 clock + * @return AHB1 clock in Hz + */ +uint32_t HAL_CCM_BusGetAHB1Clock(void) +{ + return HAL_PRCM_GetCPUAClk(); +} + +/** + * @brief Get AHB2 clock + * @return AHB2 clock in Hz + */ +uint32_t HAL_CCM_BusGetAHB2Clock(void) +{ + uint32_t div = ((CCM->CPU_BUS_CLKCFG & CCM_AHB2_CLK_DIV_MASK) >> CCM_AHB2_CLK_DIV_SHIFT) + 1; + return HAL_PRCM_GetCPUAClk() / div; +} + +/** + * @brief Get APB clock + * @return APB clock in Hz + */ +uint32_t HAL_CCM_BusGetAPBClock(void) +{ + uint32_t reg = CCM->CPU_BUS_CLKCFG; + uint32_t freq, div; + + switch (reg & CCM_APB_CLK_SRC_MASK) { + case CCM_APB_CLK_SRC_HFCLK: + freq = HAL_GetHFClock(); + break; + case CCM_APB_CLK_SRC_LFCLK: + freq = HAL_GetLFClock(); + break; + case CCM_APB_CLK_SRC_AHB2CLK: + default: + freq = HAL_GetAHB2Clock(); + break; + } + + div = ((reg & CCM_APB_CLK_DIV_MASK) >> CCM_APB_CLK_DIV_SHIFT); + return (freq >> div); +} + +/** + * @brief Enable peripheral clock + * @param[in] periphMask Bitmask of peripherals, refer to CCM_BusPeriphBit + * @return None + */ +void HAL_CCM_BusEnablePeriphClock(uint32_t periphMask) +{ + HAL_SET_BIT(CCM->BUS_PERIPH_CLK_CTRL, periphMask); +} + +/** + * @brief Disable peripheral clock + * @param[in] periphMask Bitmask of peripherals, refer to CCM_BusPeriphBit + * @return None + */ +void HAL_CCM_BusDisablePeriphClock(uint32_t periphMask) +{ + HAL_CLR_BIT(CCM->BUS_PERIPH_CLK_CTRL, periphMask); +} + +/** + * @brief Disable all peripherals clock + * @return None + */ +void HAL_CCM_BusDisableAllPeriphClock(void) +{ + CCM->BUS_PERIPH_CLK_CTRL = 0U; +} + +/** + * @brief Force peripheral reset + * @param[in] periphMask Bitmask of peripherals, refer to CCM_BusPeriphBit + * @return None + */ +void HAL_CCM_BusForcePeriphReset(uint32_t periphMask) +{ + HAL_CLR_BIT(CCM->BUS_PERIPH_RST_CTRL, periphMask); +} + +/** + * @brief Release peripheral reset + * @param[in] periphMask Bitmask of peripherals, refer to CCM_BusPeriphBit + * @return None + */ +void HAL_CCM_BusReleasePeriphReset(uint32_t periphMask) +{ + HAL_SET_BIT(CCM->BUS_PERIPH_RST_CTRL, periphMask); +} + +/** + * @brief Force all peripherals reset + * @return None + */ +void HAL_CCM_BusForceAllPeriphReset(void) +{ + CCM->BUS_PERIPH_RST_CTRL = 0U; +} + +/** + * @brief Configure SPI0 module clock + * @param[in] src SPI0 module clock source + * @param[in] divN SPI0 module clock divider N + * @param[in] divM SPI0 module clock divider M + * @return None + */ +void HAL_CCM_SPI0_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->SPI0_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable SPI0 module clock + * @return None + */ +void HAL_CCM_SPI0_EnableMClock(void) +{ + HAL_SET_BIT(CCM->SPI0_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable SPI0 module clock + * @return None + */ +void HAL_CCM_SPI0_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->SPI0_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure SPI1 module clock + * @param[in] src SPI1 module clock source + * @param[in] divN SPI1 module clock divider N + * @param[in] divM SPI1 module clock divider M + * @return None + */ +void HAL_CCM_SPI1_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->SPI1_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable SPI1 module clock + * @return None + */ +void HAL_CCM_SPI1_EnableMClock(void) +{ + HAL_SET_BIT(CCM->SPI1_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable SPI1 module clock + * @return None + */ +void HAL_CCM_SPI1_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->SPI1_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure SD controller module clock + * @param[in] src SD controller module clock source + * @param[in] divN SD controller module clock divider N + * @param[in] divM SD controller module clock divider M + * @return None + */ +void HAL_CCM_SDC_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->SDC_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable SD controller module clock + * @return None + */ +void HAL_CCM_SDC_EnableMClock(void) +{ + HAL_SET_BIT(CCM->SDC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable SD controller module clock + * @return None + */ +void HAL_CCM_SDC_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->SDC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure Crypto Engine module clock + * @param[in] src Crypto Engine module clock source + * @param[in] divN Crypto Engine module clock divider N + * @param[in] divM Crypto Engine module clock divider M + * @return None + */ +void HAL_CCM_CE_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->CE_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable Crypto Engine module clock + * @return None + */ +void HAL_CCM_CE_EnableMClock(void) +{ + HAL_SET_BIT(CCM->CE_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable Crypto Engine module clock + * @return None + */ +void HAL_CCM_CE_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->CE_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure CSI output clock + * @param[in] src CSI output clock source + * @param[in] divN CSI output clock divider N + * @param[in] divM CSI output clock divider M + * @return None + */ +void HAL_CCM_CSI_SetOutClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->CSI_OCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable CSI output clock + * @return None + */ +void HAL_CCM_CSI_EnableOutClock(void) +{ + HAL_SET_BIT(CCM->CSI_OCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable CSI output clock + * @return None + */ +void HAL_CCM_CSI_DisableOutClock(void) +{ + HAL_CLR_BIT(CCM->CSI_OCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure Digital audio module clock + * @param[in] src Digital audio module source + * @return None + */ +void HAL_CCM_DAUDIO_SetMClock(CCM_DAudioClkSrc src) +{ + HAL_MODIFY_REG(CCM->DAUDIO_MCLK_CTRL, CCM_DAUDIO_MCLK_SRC_MASK, src); +} + +/** + * @brief Enable Digital audio module clock + * @return None + */ +void HAL_CCM_DAUDIO_EnableMClock(void) +{ + HAL_SET_BIT(CCM->DAUDIO_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable Digital audio module clock + * @return None + */ +void HAL_CCM_DAUDIO_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->DAUDIO_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure IR RX module clock + * @param[in] src IR RX module clock source + * @param[in] divN IR RX module clock divider N + * @param[in] divM IR RX module clock divider M + * @return None + */ +void HAL_CCM_IRRX_SetMClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->IRRX_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable IR RX module clock + * @return None + */ +void HAL_CCM_IRRX_EnableMClock(void) +{ + HAL_SET_BIT(CCM->IRRX_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable IR RX module clock + * @return None + */ +void HAL_CCM_IRRX_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->IRRX_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure IR TX module clock + * @param[in] src IR TX module clock source + * @param[in] divN IR TX module clock divider N + * @param[in] divM IR TX module clock divider M + * @return None + */ +void HAL_CCM_IRTX_SetMClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->IRTX_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable IR TX module clock + * @return None + */ +void HAL_CCM_IRTX_EnableMClock(void) +{ + HAL_SET_BIT(CCM->IRTX_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable IR TX module clock + * @return None + */ +void HAL_CCM_IRTX_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->IRTX_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure system tick reference clock + * @param[in] src system tick reference clock source + * @param[in] divN system tick reference clock divider N + * @param[in] divM system tick reference clock divider M + * @return None + */ +void HAL_CCM_SYSTICK_SetRefClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->SYSTICK_REFCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable system tick reference clock + * @return None + */ +void HAL_CCM_SYSTICK_EnableRefClock(void) +{ + HAL_SET_BIT(CCM->SYSTICK_REFCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable system tick reference clock + * @return None + */ +void HAL_CCM_SYSTICK_DisableRefClock(void) +{ + HAL_CLR_BIT(CCM->SYSTICK_REFCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Enable system tick reference + * @return None + */ +void HAL_CCM_SYSTICK_EnableRef(void) +{ + HAL_CLR_BIT(CCM->SYSTICK_CALIB_CTRL, CCM_SYSTICK_NOREF_BIT); +} + +/** + * @brief Disable system tick reference + * @return None + */ +void HAL_CCM_SYSTICK_DisableRef(void) +{ + HAL_SET_BIT(CCM->SYSTICK_CALIB_CTRL, CCM_SYSTICK_NOREF_BIT); +} + +/** + * @brief Enable system tick skew, which means calibration value is not exactly 10 ms + * @return None + */ +void HAL_CCM_SYSTICK_EnableSkew(void) +{ + HAL_SET_BIT(CCM->SYSTICK_CALIB_CTRL, CCM_SYSTICK_SKEW_BIT); +} + +/** + * @brief Disable system tick skew, which means calibration value is accurate + * @return None + */ +void HAL_CCM_SYSTICK_DisableSkew(void) +{ + HAL_CLR_BIT(CCM->SYSTICK_CALIB_CTRL, CCM_SYSTICK_SKEW_BIT); +} + +/** + * @brief Set calibration value for 10 ms + * @return None + */ +void HAL_CCM_SYSTICK_SetTENMS(uint32_t cnt) +{ + HAL_MODIFY_REG(CCM->SYSTICK_CALIB_CTRL, + CCM_SYSTICK_TENMS_MASK, + (cnt << CCM_SYSTICK_TENMS_SHIFT) & CCM_SYSTICK_TENMS_MASK); +} + +/** + * @brief Enable DMIC module clock + * @return None + */ +void HAL_CCM_DMIC_EnableMClock(void) +{ + HAL_SET_BIT(CCM->DMIC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable DMIC module clock + * @return None + */ +void HAL_CCM_DMIC_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->DMIC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure GPADC module clock + * @param[in] src GPADC module clock source + * @param[in] divN GPADC module clock divider N + * @param[in] divM GPADC module clock divider M + * @return None + */ +void HAL_CCM_GPADC_SetMClock(CCM_APBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->GPADC_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable GPADC module clock + * @return None + */ +void HAL_CCM_GPADC_EnableMClock(void) +{ + HAL_SET_BIT(CCM->GPADC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable GPADC module clock + * @return None + */ +void HAL_CCM_GPADC_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->GPADC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure CSI module clock + * @param[in] src CSI module clock source + * @param[in] divN CSI module clock divider N + * @param[in] divM CSI module clock divider M + * @return None + */ +void HAL_CCM_CSI_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->CSI_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable CSI module clock + * @return None + */ +void HAL_CCM_CSI_EnableMClock(void) +{ + HAL_SET_BIT(CCM->CSI_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable CSI module clock + * @return None + */ +void HAL_CCM_CSI_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->CSI_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Configure Flash controller module clock + * @param[in] src Flash controller module clock source + * @param[in] divN Flash controller module clock divider N + * @param[in] divM Flash controller module clock divider M + * @return None + */ +void HAL_CCM_FLASHC_SetMClock(CCM_AHBPeriphClkSrc src, CCM_PeriphClkDivN divN, CCM_PeriphClkDivM divM) +{ + HAL_MODIFY_REG(CCM->FLASHC_MCLK_CTRL, CCM_PERIPH_CLK_PARAM_MASK, src | divN | divM); +} + +/** + * @brief Enable Flash controller module clock + * @return None + */ +void HAL_CCM_FLASHC_EnableMClock(void) +{ + HAL_SET_BIT(CCM->FLASHC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +/** + * @brief Disable Flash controller module clock + * @return None + */ +void HAL_CCM_FLASHC_DisableMClock(void) +{ + HAL_CLR_BIT(CCM->FLASHC_MCLK_CTRL, CCM_PERIPH_CLK_EN_BIT); +} + +#ifdef CONFIG_PM +struct ccm_regs { + uint32_t cpu_bus_clkcfg; /* cpu bus clock configure register */ + uint32_t bus_clk_gating; /* bus clock gating control Register */ + uint32_t bus_reset_ctrl; /* bus device reset control register */ + uint32_t systick_refclk_ctrl; /* system tick reference clock register */ + uint32_t systick_calib_ctrl; /* system tick clock calibration register */ +}; +static struct ccm_regs ccm_reg_store; + +static int ccm_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + ccm_reg_store.bus_clk_gating = CCM->BUS_PERIPH_CLK_CTRL; /* it is better to do in every devices driver */ + ccm_reg_store.bus_reset_ctrl = CCM->BUS_PERIPH_RST_CTRL; + + ccm_reg_store.cpu_bus_clkcfg = CCM->CPU_BUS_CLKCFG; + ccm_reg_store.systick_refclk_ctrl = CCM->SYSTICK_REFCLK_CTRL; + ccm_reg_store.systick_calib_ctrl = CCM->SYSTICK_CALIB_CTRL; + HAL_DBG("%s ok\n", __func__); + break; + default: + break; + } + + return 0; +} + +static int ccm_resume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + CCM->CPU_BUS_CLKCFG = ccm_reg_store.cpu_bus_clkcfg; /* write directly is ok for cpu clk has been restored after resume */ + CCM->SYSTICK_REFCLK_CTRL = ccm_reg_store.systick_refclk_ctrl; + CCM->SYSTICK_CALIB_CTRL = ccm_reg_store.systick_calib_ctrl; + + CCM->BUS_PERIPH_RST_CTRL = ccm_reg_store.bus_reset_ctrl; + CCM->BUS_PERIPH_CLK_CTRL = ccm_reg_store.bus_clk_gating; + __DSB(); + __ISB(); + HAL_DBG("%s ok\n", __func__); + break; + default: + break; + } + + return 0; +} + +void ccm_print_regs(void) +{ + hex_dump_bytes(&ccm_reg_store, sizeof(ccm_reg_store)); +} + +static struct soc_device_driver ccm_drv = { + .name = "ccm", + .suspend_noirq = ccm_suspend, + .resume_noirq = ccm_resume, +}; + +static struct soc_device ccm_dev = { + .name = "ccm", + .driver = &ccm_drv, +}; + +#define CCM_DEV (&ccm_dev) +#endif /* CONFIG_PM */ + +/** + * @brief Initializes CCM module + * @return None + */ +void HAL_CCM_Init(void) +{ +#ifdef CONFIG_PM + pm_register_ops(CCM_DEV); +#endif +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_crypto.c b/platform/mcu/xr871/src/driver/chip/hal_crypto.c new file mode 100644 index 0000000000..1398af149e --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_crypto.c @@ -0,0 +1,1932 @@ +/** + * @file hal_crypto.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "driver/chip/hal_crypto.h" +#include "hal_base.h" +#include "sys/endian.h" +#include "pm/pm.h" + + +/*************************************** Debug *****************************************/ +#define CE_MODULE (DBG_OFF | XR_LEVEL_DEBUG) +#define CE_REG_DEBUG + +#define CE_ASSERT(condition) XR_ASSERT(condition, CE_MODULE, #condition " failed\n") + +#define CE_DEBUG(msg, arg...) XR_DEBUG(CE_MODULE, NOEXPAND, "[CE Debug] " msg, ##arg) + +#define CE_ALERT(msg, arg...) XR_ALERT(CE_MODULE, NOEXPAND, "[CE Alert] " msg, ##arg) + +#define CE_ENTRY() XR_ENTRY(CE_MODULE, "[CE Entry]") + +#define CE_EXIT(val) XR_RET(CE_MODULE, "[CE Exit]", val) + +extern bool reg_show; + +#ifdef CE_REG_DEBUG +#define CE_REG(reg) { \ + if (reg_show) \ + CE_DEBUG("register " #reg ": 0x%x.\n", reg); \ + } + +#define CE_REG_ALL(ce) { \ + CE_REG(ce->CTL); \ + CE_REG(ce->KEY[0]); \ + CE_REG(ce->KEY[1]); \ + CE_REG(ce->KEY[2]); \ + CE_REG(ce->KEY[3]); \ + CE_REG(ce->KEY[4]); \ + CE_REG(ce->KEY[5]); \ + CE_REG(ce->KEY[6]); \ + CE_REG(ce->KEY[7]); \ + CE_REG(ce->IV[0]); \ + CE_REG(ce->IV[1]); \ + CE_REG(ce->IV[2]); \ + CE_REG(ce->IV[3]); \ + CE_REG(ce->CNT[0]); \ + CE_REG(ce->CNT[1]); \ + CE_REG(ce->CNT[2]); \ + CE_REG(ce->CNT[3]); \ + CE_REG(ce->FCSR); \ + CE_REG(ce->ICSR); \ + CE_REG(ce->MD0); \ + CE_REG(ce->MD1); \ + CE_REG(ce->MD2); \ + CE_REG(ce->MD3); \ + CE_REG(ce->MD4); \ + CE_REG(ce->CTS_LEN); \ + CE_REG(ce->CRC_POLY); \ + CE_REG(ce->CRC_RESULT); \ + CE_REG(ce->MD5); \ + CE_REG(ce->MD6); \ + CE_REG(ce->MD7); \ + } + +#else +#define CE_REG_ALL(ce) + +#define CE_REG(reg) + +#endif + + +#define __CE_STATIC_INLINE__ static inline + +bool reg_show; + +/* + * @brief CE + */ +__CE_STATIC_INLINE__ +void CE_Enable(CE_T *ce) +{ + HAL_SET_BIT(ce->CTL, CE_CTL_ENABLE_MASK); +} + +__CE_STATIC_INLINE__ +void CE_Disable(CE_T *ce) +{ + HAL_CLR_BIT(ce->CTL, CE_CTL_ENABLE_MASK); +} + +__CE_STATIC_INLINE__ +uint8_t CE_GetInputAvailCnt(CE_T *ce) +{ + return HAL_GET_BIT_VAL(ce->FCSR, CE_FCSR_RXFIFO_EMP_CNT_SHIFT, CE_FCSR_RXFIFO_EMP_CNT_VMASK); +} + +__CE_STATIC_INLINE__ +uint8_t CE_GetOutputAvailCnt(CE_T *ce) +{ + return HAL_GET_BIT_VAL(ce->FCSR, CE_FCSR_TXFIFO_AVA_CNT_SHIFT, CE_FCSR_TXFIFO_AVA_CNT_VMASK); +} + +__CE_STATIC_INLINE__ +void CE_SetInputThreshold(CE_T *ce, uint8_t threshold) +{ + CE_ASSERT((threshold & ~CE_FCSR_TXFIFO_INT_TRIG_LEVEL_MASK) == 0); //rx vmask = tx vmask = tx mask + HAL_MODIFY_REG(ce->FCSR, CE_FCSR_RXFIFO_INT_TRIG_LEVEL_MASK, threshold << CE_FCSR_RXFIFO_INT_TRIG_LEVEL_SHIFT); +} + +__CE_STATIC_INLINE__ +void CE_SetOutputThreshold(CE_T *ce, uint8_t threshold) +{ + CE_ASSERT((threshold & ~CE_FCSR_TXFIFO_INT_TRIG_LEVEL_MASK) == 0); + HAL_MODIFY_REG(ce->FCSR, CE_FCSR_TXFIFO_INT_TRIG_LEVEL_MASK, threshold << CE_FCSR_TXFIFO_INT_TRIG_LEVEL_SHIFT); +} + +typedef enum { + CE_INT_TPYE_TXFIFO_AVA = CE_ICSR_TXFIFO_AVA_INT_EN_SHIFT, + CE_INT_TPYE_RXFIFO_EMP = CE_ICSR_RXFIFO_EMP_INT_EN_SHIFT, + CE_INT_TPYE_HASH_CRC_END = CE_ICSR_HASH_CRC_END_INT_EN_SHIFT +} CE_Int_Type; + +__CE_STATIC_INLINE__ +void CE_EnableInt(CE_T *ce, CE_Int_Type type) +{ + HAL_SET_BIT(ce->ICSR, 1 << type); +} + +__CE_STATIC_INLINE__ +void CE_DisableInt(CE_T *ce, CE_Int_Type type) +{ + HAL_CLR_BIT(ce->ICSR, 1 << type); +} + +__CE_STATIC_INLINE__ +bool CE_Status(CE_T *ce, CE_Int_Type type) +{ + return (bool)HAL_GET_BIT_VAL(ce->ICSR, CE_ICSR_TXFIFO_AVA_SHIFT + type, 1); +} + +__CE_STATIC_INLINE__ +void CE_EnableDMA(CE_T *ce) +{ + HAL_SET_BIT(ce->ICSR, CE_ICSR_DRQ_ENABLE_MASK); +} + +__CE_STATIC_INLINE__ +void CE_DisableDMA(CE_T *ce) +{ + HAL_CLR_BIT(ce->ICSR, CE_ICSR_DRQ_ENABLE_MASK); +} + +__CE_STATIC_INLINE__ +void CE_SetLength(CE_T *ce, uint32_t len) +{ + ce->CTS_LEN = len; +} + +/* + * @brief CRC + */ +__CE_STATIC_INLINE__ +HAL_Status CE_CRC_Init(CE_T *ce, + bool init_val, + bool xor_out, + bool ref_in, + bool ref_out, + CE_CTL_CRC_Width width, + uint32_t poly) +{ + bool last_pckt = 0; + + HAL_CLR_BIT(ce->CTL, CE_CTL_END_BIT_MASK); + HAL_MODIFY_REG(ce->CTL, + CE_CTL_CRC_INIT_MASK + | CE_CTL_CRC_REF_IN_MASK + | CE_CTL_CRC_REF_OUT_MASK + | CE_CTL_CRC_XOR_OUT_MASK + | CE_CTL_CRC_WIDTH_MASK + | CE_CTL_CRC_CONT_MASK + | CE_CTL_OP_DIR_MASK + | CE_CTL_METHOD_MASK, + (init_val << CE_CTL_CRC_INIT_SHIFT) + | (ref_in << CE_CTL_CRC_REF_IN_SHIFT) + | (ref_out << CE_CTL_CRC_REF_OUT_SHIFT) + | (xor_out << CE_CTL_CRC_XOR_OUT_SHIFT) + | (width) + | (last_pckt << CE_CTL_CRC_CONT_SHIFT) /* not the last packet */ + | CE_CRYPT_OP_ENCRYPTION + | CE_CTL_METHOD_CRC); + ce->CRC_POLY = poly; + return HAL_OK; +} + +__CE_STATIC_INLINE__ +void CE_CRC_Fill(CE_T *ce, uint32_t data) +{ + while (CE_GetInputAvailCnt(ce) == 0); + ce->RXFIFO = data; +} + +__CE_STATIC_INLINE__ +void CE_CRC_Finish(CE_T *ce) +{ + HAL_SET_BIT(ce->CTL, CE_CTL_END_BIT_MASK); +} + +__CE_STATIC_INLINE__ +void CE_CRC_Calc(CE_T *ce, uint32_t *crc) //_____________16bit mode is it generate a 16bits crc? +{ + *crc = ce->CRC_RESULT; +} + +__CE_STATIC_INLINE__ +void CE_CRC_Deinit(CE_T *ce) +{ + /*CE_Disable(ce);*/ +} + +__CE_STATIC_INLINE__ +void CE_CRC_SetResult(CE_T *ce, uint32_t crc) +{ + ce->CRC_RESULT = crc; +} + +/* +void CE_CRC_SetLength(CE_T *ce, uint32_t len) +{ + CE_SetLength(ce, len); +} +*/ + + +/* + * @brief AES/DES/3DES + */ +__CE_STATIC_INLINE__ +void CE_Crypto_Init(CE_T *ce, CE_CTL_Method algo, CE_CTL_Crypto_Mode mode, CE_Crypto_Op op) +{ + CE_ASSERT(algo > CE_CTL_METHOD_3DES); + + HAL_MODIFY_REG(ce->CTL, + CE_CTL_METHOD_MASK + | CE_CTL_OP_MODE_MASK + | CE_CTL_OP_DIR_MASK, + algo + | mode + | op); /* ce enable */ +} + +__CE_STATIC_INLINE__ +void CE_AES_SetKey(CE_T *ce, CE_CTL_KeySource src, CE_CTL_AES_KeySize size, uint32_t *key) +{ + uint8_t key_cnt; + uint8_t i = 0; + HAL_MODIFY_REG(ce->CTL, CE_CTL_KEY_SEL_MASK | CE_CTL_AES_KEY_SIZE_MASK, src | size); + if (size == CE_CTL_AES_KEYSIZE_128BITS) + key_cnt = 4; + else if (size == CE_CTL_AES_KEYSIZE_192BITS) + key_cnt = 6; + else if (size == CE_CTL_AES_KEYSIZE_256BITS) + key_cnt = 8; + else { + CE_ALERT("param is out of range\n"); + return; + } + + while (i < key_cnt) { + ce->KEY[i] = *(key++); + i++; + } +} + +__CE_STATIC_INLINE__ +void CE_DES_SetKey(CE_T *ce, CE_CTL_KeySource src, uint32_t key[2]) //56bit key? 64bit key? = 2 * 32bit reg? +{ + HAL_MODIFY_REG(ce->CTL, CE_CTL_KEY_SEL_MASK, src); + ce->KEY[0] = key[0]; + ce->KEY[1] = key[1]; +} + +__CE_STATIC_INLINE__ +void CE_3DES_SetKey(CE_T *ce, CE_CTL_KeySource src, uint32_t key[6]) //3 * 64bit key? = 6 * 32bit reg? +{ + uint8_t i = 0; + HAL_MODIFY_REG(ce->CTL, CE_CTL_KEY_SEL_MASK, src); + + while (i < CE_3DES_KEY_COUNT) { + ce->KEY[i] = *(key++); + i++; + } +} + +#ifdef CE_CTR_MODE +__CE_STATIC_INLINE__ +HAL_Status CE_Crypto_SetCounter(CE_T *ce, uint32_t *cnt, CE_CTL_CtrWidth size) +{ + HAL_MODIFY_REG(ce->CTL, CE_CTL_CTR_WIDTH_MASK, size); + switch (size) { + case CE_CTL_CTRWITDH_128BITS: + ce->CNT[3] = *(cnt + 3); + ce->CNT[2] = *(cnt + 2); + case CE_CTL_CTRWITDH_64BITS: + ce->CNT[1] = *(cnt + 1); + case CE_CTL_CTRWITDH_32BITS: + ce->CNT[0] = *(cnt + 0); + break; + case CE_CTL_CTRWITDH_16BITS: + ce->CNT[0] = *(cnt + 0) & 0xFFFF; + break; + default: + return HAL_INVALID; + } + return HAL_OK; +} +#endif + +__CE_STATIC_INLINE__ +void CE_Crypto_SetLength(CE_T *ce, uint32_t len) +{ + CE_SetLength(ce, len); +} + +__CE_STATIC_INLINE__ +void CE_Crypto_SetIV(CE_T *ce, uint32_t iv[4], uint8_t size) +{ + uint8_t i = size / 4; + while (i--) + ce->IV[i] = iv[i]; +} + +__CE_STATIC_INLINE__ +void CE_Crypto_Input(CE_T *ce, uint32_t data) +{ + while (CE_GetInputAvailCnt(ce) == 0); + ce->RXFIFO = data; +} + +__CE_STATIC_INLINE__ +void CE_Crypto_Output(CE_T *ce, uint32_t *data) +{ + while (CE_GetOutputAvailCnt(ce) == 0); + *data = ce->TXFIFO; +} + +__CE_STATIC_INLINE__ +void CE_Crypto_Deinit(CE_T *ce) +{ + CE_Disable(ce); +} + +__CE_STATIC_INLINE__ +volatile uint32_t *CE_Crypto_GetInputAddr(CE_T *ce) +{ + return &ce->RXFIFO; +} + +__CE_STATIC_INLINE__ +volatile const uint32_t *CE_Crypto_GetOutputAddr(CE_T *ce) +{ + return &ce->TXFIFO; +} + +/*HAL_Status CE_Crypto_GetOutput(CE_T *ce, uint32_t *data) +{} + +HAL_Status CE_Crypto_GetInput(CE_T *ce, uint32_t *data) +{}*/ + +__CE_STATIC_INLINE__ +void CE_Crypto_GetIV(CE_T *ce, uint32_t iv[4], uint8_t size) +{ + uint8_t i = size / 4; + while (i--) + iv[i] = ce->IV[i]; +} + +#ifdef CE_CTR_MODE +__CE_STATIC_INLINE__ +HAL_Status CE_Crypto_GetCounter(CE_T *ce, uint32_t cnt[4], CE_CTL_CtrWidth size) +{ + switch (size) { + case CE_CTL_CTRWITDH_128BITS: + cnt[2] = ce->CNT[2]; + cnt[3] = ce->CNT[3]; + case CE_CTL_CTRWITDH_64BITS: + cnt[1] = ce->CNT[1]; + case CE_CTL_CTRWITDH_32BITS: + case CE_CTL_CTRWITDH_16BITS: + cnt[0] = ce->CNT[0]; + break; + default: + return HAL_INVALID; + } + return HAL_OK; +} +#endif + +/* + * @brief MD5/sha1/sha256 + */ +void CE_Hash_Init(CE_T *ce, CE_CTL_Method algo) +{ + CE_ASSERT((algo != CE_CTL_METHOD_SHA1) && (algo != CE_CTL_METHOD_MD5) && (algo != CE_CTL_METHOD_SHA256)); + + HAL_CLR_BIT(ce->CTL, CE_CTL_END_BIT_MASK); + HAL_MODIFY_REG(ce->CTL, + CE_CTL_METHOD_MASK | CE_CTL_ENABLE_MASK | CE_CTL_OP_DIR_MASK, + algo | (1 << CE_CTL_ENABLE_SHIFT) | CE_CRYPT_OP_ENCRYPTION); +} + +void CE_Hash_SetIV(CE_T *ce, CE_CTL_IvMode_SHA_MD5 iv_src, uint32_t *iv, uint32_t iv_size) +{ + HAL_MODIFY_REG(ce->CTL, CE_CTL_IV_MODE_MASK, iv_src); + + if (iv_src == CE_CTL_IVMODE_SHA_MD5_FIPS180) { //necessary? + ce->IV[0] = 0; + ce->IV[1] = 0; + ce->IV[2] = 0; + ce->IV[3] = 0; + return; + } + + ce->IV[0] = iv[0]; + ce->IV[1] = iv[1]; + ce->IV[2] = iv[2]; + ce->IV[3] = iv[3]; + if (iv_size == 5) + ce->CNT[0] = iv[4]; + else if (iv_size == 8) { + ce->CNT[0] = iv[4]; + ce->CNT[1] = iv[5]; + ce->CNT[2] = iv[6]; + ce->CNT[3] = iv[7]; + } + +} + +__CE_STATIC_INLINE__ +void CE_Hash_Finish(CE_T *ce) +{ + HAL_SET_BIT(ce->CTL, CE_CTL_END_BIT_MASK); +} + +__CE_STATIC_INLINE__ +void CE_Hash_Fill(CE_T *ce, uint32_t data) +{ + while (CE_GetInputAvailCnt(ce) == 0); + ce->RXFIFO = data; +} + +void CE_Hash_Calc(CE_T *ce, CE_CTL_Method algo, uint32_t *digest) // md5[5] sha1[5] sha256[8] +{ + if (algo == CE_CTL_METHOD_SHA256) { + *(digest + 7) = ce->MD7; + *(digest + 6) = ce->MD6; + *(digest + 5) = ce->MD5; + *(digest + 4) = ce->MD4; + } else if (algo == CE_CTL_METHOD_SHA1) + *(digest + 4) = ce->MD4; + *(digest + 3) = ce->MD3; + *(digest + 2) = ce->MD2; + *(digest + 1) = ce->MD1; + *(digest + 0) = ce->MD0; +} + +__CE_STATIC_INLINE__ +void CE_Hash_Deinit(CE_T *ce) +{ + CE_Disable(ce); +} + + +/* + * @brief PRNG + */ +__CE_STATIC_INLINE__ +void CE_PRNG_Init(CE_T *ce, bool continue_mode) +{ + HAL_MODIFY_REG(ce->CTL, + CE_CTL_PRNG_MODE_MASK | CE_CTL_METHOD_MASK | CE_CTL_ENABLE_MASK, + (continue_mode << CE_CTL_PRNG_MODE_SHIFT) | CE_CTL_METHOD_PRNG | (1 << CE_CTL_ENABLE_SHIFT)); + +} + +__CE_STATIC_INLINE__ +void CE_PRNG_Seed(CE_T *ce, uint32_t seed[6]) +{ + ce->KEY[0] = seed[0]; + ce->KEY[1] = seed[1]; + ce->KEY[2] = seed[2]; + ce->KEY[3] = seed[3]; + ce->KEY[4] = seed[4]; + ce->KEY[5] = seed[5]; +} + +__CE_STATIC_INLINE__ +void CE_PRNG_Generate(CE_T *ce, uint32_t random[5]) +{ + HAL_SET_BIT(ce->CTL, CE_CTL_PRNG_START_MASK); + + while (HAL_GET_BIT(CE->CTL, CE_CTL_PRNG_START_MASK) != 0); + + random[0] = ce->MD0; + random[1] = ce->MD1; + random[2] = ce->MD2; + random[3] = ce->MD3; + random[4] = ce->MD4; +} + +__CE_STATIC_INLINE__ +void CE_PRNG_Deinit(CE_T *ce) +{ + CE_Disable(ce); +} + + +/************************ AES DES 3DES private **************************************/ +static HAL_Mutex ce_lock; +static HAL_Semaphore ce_block; + +__CE_STATIC_INLINE__ +void HAL_CE_EnableCCMU() +{ + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_CE); + HAL_CCM_CE_EnableMClock(); +} + +__CE_STATIC_INLINE__ +void HAL_CE_DisableCCMU() +{ + HAL_CCM_CE_DisableMClock(); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_CE); +} + +/*static void HAL_CE_InputCmpl(void *arg) +{ + CE_DEBUG("input by dma had been finished.\n"); +} + +static void HAL_CE_OutputCmpl(void *arg) +{ + HAL_SemaphoreRelease(&ce_block); + CE_DEBUG("output by dma had been finished.\n"); +}*/ + +static void HAL_CE_DMACmpl(void *arg) +{ + if (arg != NULL) + HAL_SemaphoreRelease(&ce_block); + CE_DEBUG("Transfer by dma had been finished.\n"); +} + +static HAL_Status HAL_Crypto_InitDMA(DMA_Channel *input, DMA_Channel *output) +{ + HAL_Status ret = HAL_OK; + DMA_ChannelInitParam Output_param; + DMA_ChannelInitParam Input_param; + memset(&Output_param, 0, sizeof(Output_param)); + memset(&Input_param, 0, sizeof(Input_param)); + CE_ENTRY(); + + if ((*output = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + CE_ALERT("DMA request failed \n"); + ret = HAL_INVALID; + goto out; + } + if ((*input = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + CE_ALERT("DMA request failed \n"); + HAL_DMA_Release(*output); + ret = HAL_INVALID; + goto out; + } + + Output_param.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_16, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_32BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_CE); + Output_param.irqType = DMA_IRQ_TYPE_END; + Output_param.endCallback = HAL_CE_DMACmpl; + Output_param.endArg = &ce_block; + + Input_param.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_16, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_32BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_CE, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM); + Input_param.irqType = DMA_IRQ_TYPE_END; + Input_param.endCallback = HAL_CE_DMACmpl; + Input_param.endArg = NULL; + + HAL_DMA_Init(*input, &Input_param); + HAL_DMA_Init(*output, &Output_param); + +out: + CE_EXIT(ret); + return ret; +} + +static inline void HAL_Crypto_DenitDMA(DMA_Channel input, DMA_Channel output) +{ + HAL_DMA_DeInit(input); + HAL_DMA_DeInit(output); + HAL_DMA_Release(input); + HAL_DMA_Release(output); +} + +static HAL_Status HAL_Crypto_Convey(uint8_t *input, uint8_t *output, uint32_t size, uint8_t block_size) +{ + HAL_Status ret = HAL_OK; + uint32_t align_len = size & (~(block_size - 1)); + uint32_t remain_len = size & (block_size - 1); + uint8_t padding[16] = {0}; + CE_ENTRY(); +// CE_DEBUG("align_len = %d, remain_len = %d, len = %d\n", align_len, remain_len, remain_len ? (align_len + block_size) : align_len); + + DMA_Channel Output_channel = DMA_CHANNEL_INVALID; + DMA_Channel Input_channel = DMA_CHANNEL_INVALID; + + /* data preprocess */ + memcpy(padding, &input[align_len], remain_len); + CE_Crypto_SetLength(CE, remain_len ? (align_len + block_size) : align_len); + CE_REG_ALL(CE); + + /* data transfer by DMA */ + if ((ret = HAL_Crypto_InitDMA(&Input_channel, &Output_channel)) != HAL_OK){ + CE_ALERT("DMA Request failed\n"); + goto out; + } + + CE_SetInputThreshold(CE, 0); + CE_SetOutputThreshold(CE, 0); + CE_EnableDMA(CE); + CE_Enable(CE); + + CE_REG_ALL(CE); + + if (align_len != 0) { + HAL_DMA_Start(Input_channel, (uint32_t)input, (uint32_t)CE_Crypto_GetInputAddr(CE), align_len); + HAL_DMA_Start(Output_channel, (uint32_t)CE_Crypto_GetOutputAddr(CE), (uint32_t)output, align_len); + if ((ret = HAL_SemaphoreWait(&ce_block, CE_WAIT_TIME)) != HAL_OK) { + CE_ALERT("DMA 1st transfer failed\n"); + HAL_DMA_Stop(Input_channel); + HAL_DMA_Stop(Output_channel); + goto failed; + } + HAL_DMA_Stop(Input_channel); + HAL_DMA_Stop(Output_channel); + } + + if (remain_len != 0) { + HAL_DMA_Start(Input_channel, (uint32_t)padding, (uint32_t)CE_Crypto_GetInputAddr(CE), block_size); + CE_REG_ALL(CE); + + HAL_DMA_Start(Output_channel, (uint32_t)CE_Crypto_GetOutputAddr(CE), (uint32_t)&output[align_len], block_size); + if ((ret = HAL_SemaphoreWait(&ce_block, CE_WAIT_TIME)) != HAL_OK) { + CE_ALERT("DMA 2nd transfer failed\n"); + CE_REG_ALL(CE); + HAL_DMA_Stop(Input_channel); + HAL_DMA_Stop(Output_channel); + goto failed; + } + CE_REG_ALL(CE); + HAL_DMA_Stop(Input_channel); + HAL_DMA_Stop(Output_channel); + } + +failed: + CE_Disable(CE); + CE_DisableDMA(CE); + HAL_Crypto_DenitDMA(Input_channel, Output_channel); + +out: + CE_EXIT(ret); + return ret; +} + +int ce_running = 0; +#ifdef CONFIG_PM +static int hal_ce_suspending = 0; + +static int ce_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + if (ce_running) + return -1; + hal_ce_suspending = 1; + + return 0; +} + +static int ce_resume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_CE_Init(); + break; + default: + break; + } + + hal_ce_suspending = 0; + + return 0; +} + +static struct soc_device_driver ce_drv = { + .name = "ce", + .suspend_noirq = ce_suspend, + .resume_noirq = ce_resume, +}; + +static struct soc_device ce_dev = { + .name = "ce", + .driver = &ce_drv, +}; + +#define CE_DEV (&ce_dev) +#else +#define CE_DEV NULL +#endif + + +/************************ public **************************************/ + +/** + * @brief Initialize the Crypto Engine Module. + * @param None + * @retval HAL_Status: The result status of initializtion + */ +HAL_Status HAL_CE_Init() +{ + HAL_Status ret = HAL_OK; + uint32_t clk; + uint32_t div; + CE_ENTRY(); + + HAL_CE_DisableCCMU(); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_CE); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_CE); + clk = HAL_GetDevClock(); + div = (clk - 1) / (80 * 1000 * 1000) + 1; + CE_DEBUG("CCMU src clk is %d, div is %d\n", clk, div); + + if (div > (8 * 16)) + return HAL_ERROR; + else if (div > (4 * 16)) + HAL_CCM_CE_SetMClock(CCM_AHB_PERIPH_CLK_SRC_DEVCLK, CCM_PERIPH_CLK_DIV_N_8, (CCM_PeriphClkDivM)((div >> 3) - 1)); + else if (div > (2 * 16)) + HAL_CCM_CE_SetMClock(CCM_AHB_PERIPH_CLK_SRC_DEVCLK, CCM_PERIPH_CLK_DIV_N_4, (CCM_PeriphClkDivM)((div >> 2) - 1)); + else if (div > (1 & 16)) + HAL_CCM_CE_SetMClock(CCM_AHB_PERIPH_CLK_SRC_DEVCLK, CCM_PERIPH_CLK_DIV_N_2, (CCM_PeriphClkDivM)((div >> 1) - 1)); + else + HAL_CCM_CE_SetMClock(CCM_AHB_PERIPH_CLK_SRC_DEVCLK, CCM_PERIPH_CLK_DIV_N_1, (CCM_PeriphClkDivM)((div >> 0) - 1)); + +#ifdef CONFIG_PM + if (!hal_ce_suspending) { +#endif + + if ((ret = HAL_MutexInit(&ce_lock)) != HAL_OK) + goto out; + if ((ret = HAL_SemaphoreInit(&ce_block, 0, 1)) != HAL_OK) { + HAL_MutexDeinit(&ce_lock); + goto out; + } + + ce_running = 0; + +#ifdef CONFIG_PM + pm_register_ops(CE_DEV); + } +#endif + +out: + CE_EXIT(ret); + return ret; +} + +/** + * @brief Deinitializes the Crypto Engine Module. + * @param None + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_CE_Deinit() +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + +#ifdef CONFIG_PM + if (!hal_ce_suspending) + pm_unregister_ops(CE_DEV); +#endif + + if ((ret = HAL_MutexDeinit(&ce_lock)) != HAL_OK) + goto out; + if ((ret = HAL_SemaphoreDeinit(&ce_block)) != HAL_OK) + goto out; +out: + CE_EXIT(ret); + return ret; +} + + +/** + * @brief Encrypt data by AES. + * @note AES128 & AES192 & AES256 limit the key size, oversize of key will be cut + * off. AES block size is 16 bytes. + * @param aes: + * @arg aes->mode: CE_CRYPT_MODE_ECB or CE_CRYPT_MODE_CBC + * @arg aes->iv[16]: initialization value, is same size as block size. + * CE_CRYPT_MODE_CBC mode need this param. + * @arg aes->src: CE_CTL_KEYSOURCE_INPUT: key is set from aes->key. + * CE_CTL_KEYSOURCE_SID: is not support for now. + * CE_CTL_KEYSOURCE_INTERNAL0~7: is not support for now. + * @arg aes->key[32]: store the key. please notice the size should same as + * the algorithm. example: AES128 should only use + * key[0]~key[15]. + * @arg aes->keysize: CE_CTL_AES_KEYSIZE_128BITS: algorithm of AES128. + * CE_CTL_AES_KEYSIZE_192BITS: algorithm of AES192. + * CE_CTL_AES_KEYSIZE_256BITS: algorithm of AES256. + * @param plain: plain data which is need to be encrypt. + * @param cipher: cipher data which is store the encrpyted data. the cipher data + * size is multiple of 16 bytes and no less than plain data size. + * @param size: size of plain data. if encrypt a segment of data, size should + * be multiple of 16 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_AES_Encrypt(CE_AES_Config *aes, uint8_t *plain, uint8_t *cipher, uint32_t size) +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + + /* CE config */ + CE_Crypto_Init(CE, CE_CTL_METHOD_AES, aes->mode, CE_CRYPT_OP_ENCRYPTION); + CE_AES_SetKey(CE, aes->src, aes->keysize, (uint32_t *)aes->key); + if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_SetIV(CE, (uint32_t *)aes->iv, 16); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_SetCounter(CE, (uint32_t *)aes->cnt, aes->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_SetIV(CE, (uint32_t *)aes->iv, 16); +#endif + + CE_REG_ALL(CE); + + /* plain data convey to CE and cipher data convey from CE */ + HAL_Crypto_Convey(plain, cipher, size, AES_BLOCK_SIZE); + + CE_REG_ALL(CE); + /* CE state storage */ + if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_GetIV(CE, (uint32_t *)aes->iv, 16); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTR) { + CE_Crypto_GetCounter(CE, (uint32_t *)aes->cnt, aes->width); + aes->cnt[15] += (size + 15) / 16; + } +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_GetIV(CE, (uint32_t *)aes->iv, 16); +#endif + + CE_Crypto_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); +out: + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Decrypt data by AES. + * @note AES128 & AES192 & AES256 limit the key size, oversize of key will be cut + * off. AES block size is 16 bytes. and please reset the aes config if doing + * a loopback(HAL_AES_Encrypt then HAL_AES_Decrypt). + * @param aes: + * @arg aes->mode: CE_CRYPT_MODE_ECB or CE_CRYPT_MODE_CBC + * @arg aes->iv[16]: initialization value, is same size as block size. + * CE_CRYPT_MODE_CBC mode need this param, and same as + * the encrypt side. + * @arg aes->src: CE_CTL_KEYSOURCE_INPUT: key is set from aes->key. + * CE_CTL_KEYSOURCE_SID: is not support for now. + * CE_CTL_KEYSOURCE_INTERNAL0~7: is not support for now. + * @arg aes->key[32]: store the key. please notice the size should same as + * the algorithm. example: AES128 should only use + * key[0]~key[15]. + * @arg aes->keysize: CE_CTL_AES_KEYSIZE_128BITS: algorithm of AES128. + * CE_CTL_AES_KEYSIZE_192BITS: algorithm of AES192. + * CE_CTL_AES_KEYSIZE_256BITS: algorithm of AES256. + * @param cipher: cipher data which is needed to be decrypted. the cipher data + * size must be multiple of 16 bytes. + * @param plain: plain data which store the decrypted data. the plain data size + * will be same as cipher data. + * @param size: size of cipher data. size must be multiple of 16 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_AES_Decrypt(CE_AES_Config *aes, uint8_t *cipher, uint8_t *plain, uint32_t size) +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + + /* CE config */ + CE_Crypto_Init(CE, CE_CTL_METHOD_AES, aes->mode, CE_CRYPT_OP_DECRYPTION); + CE_AES_SetKey(CE, aes->src, aes->keysize, (uint32_t *)aes->key); + if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_SetIV(CE, (uint32_t *)aes->iv, 16); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_SetCounter(CE, (uint32_t *)aes->cnt, aes->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_SetIV(CE, (uint32_t *)aes->iv, 16); +#endif + + CE_REG_ALL(CE); + + /* plain data convey to CE and cipher data convey from CE */ + HAL_Crypto_Convey(cipher, plain, size, AES_BLOCK_SIZE); + + CE_REG_ALL(CE); + + /* CE state storage */ + if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_GetIV(CE, (uint32_t *)aes->iv, 16); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTR) { + CE_Crypto_GetCounter(CE, (uint32_t *)aes->cnt, aes->width); + aes->cnt[15] += (size + 15) / 16; + } +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)aes->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_GetIV(CE, (uint32_t *)aes->iv, 16); +#endif + + CE_Crypto_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); +out: + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Encrypt data by DES. + * @note DES key size is 8 bytes. DES block size is 8 bytes. + * @param des: + * @arg des->mode: CE_CRYPT_MODE_ECB or CE_CRYPT_MODE_CBC + * @arg des->iv[8]: initialization value, is same size as block size. + * CE_CRYPT_MODE_CBC mode need this param. + * @arg des->src: CE_CTL_KEYSOURCE_INPUT: key is set from des->key. + * CE_CTL_KEYSOURCE_SID: is not support for now. + * CE_CTL_KEYSOURCE_INTERNAL0~7: is not support for now. + * @arg des->key[8]: store the key. + * @param plain: plain data which is need to be encrypt. + * @param cipher: cipher data which is store the encrpyted data. the cipher data + * size is multiple of 8 bytes and no less than plain data size. + * @param size: size of plain data. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_DES_Encrypt(CE_DES_Config *des, uint8_t *plain, uint8_t *cipher, uint32_t size) +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + + /* CE config */ + CE_Crypto_Init(CE, CE_CTL_METHOD_DES, des->mode, CE_CRYPT_OP_ENCRYPTION); + CE_DES_SetKey(CE, des->src, (uint32_t *)des->key); + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_SetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#endif + + /* plain data convey to CE and cipher data convey from CE */ + HAL_Crypto_Convey(plain, cipher, size, DES_BLOCK_SIZE); + + /* CE state storage */ + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_GetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#endif + + CE_Crypto_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); +out: + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Encrypt data by DES. + * @note DES key size is 8 bytes. DES block size is 8 bytes. + * @param des: + * @arg aes->mode: CE_CRYPT_MODE_ECB or CE_CRYPT_MODE_CBC + * @arg aes->iv[8]: initialization value, is same size as block size. + * CE_CRYPT_MODE_CBC mode need this param, and same as + * the encrypt side. + * @arg aes->src: CE_CTL_KEYSOURCE_INPUT: key is set from aes->key. + * CE_CTL_KEYSOURCE_SID: is not support for now. + * CE_CTL_KEYSOURCE_INTERNAL0~7: is not support for now. + * @arg aes->key[8]: store the key. + * @param cipher: cipher data which is needed to be decrypted. the cipher data + * size must be multiple of 8 bytes. + * @param plain: plain data which store the decrypted data. the plain data size + * will be same as cipher data. + * @param size: size of cipher data. size must be multiple of 8 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_DES_Decrypt(CE_DES_Config *des, uint8_t *cipher, uint8_t *plain, uint32_t size) +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + + /* CE config */ + CE_Crypto_Init(CE, CE_CTL_METHOD_DES, des->mode, CE_CRYPT_OP_DECRYPTION); + CE_DES_SetKey(CE, des->src, (uint32_t *)des->key); + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_SetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#endif + + /* plain data convey to CE and cipher data convey from CE */ + HAL_Crypto_Convey(cipher, plain, size, DES_BLOCK_SIZE); + + /* CE state storage */ + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_GetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#endif + + CE_Crypto_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); +out: + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Encrypt data by 3DES. + * @note 3DES key size is 24 bytes, or 3 * 8bytes(8bytes key). 3DES block size is 8 bytes. + * @param des: + * @arg des->mode: CE_CRYPT_MODE_ECB or CE_CRYPT_MODE_CBC + * @arg des->iv[8]: initialization value, is same size as block size. + * CE_CRYPT_MODE_CBC mode need this param. + * @arg des->src: CE_CTL_KEYSOURCE_INPUT: key is set from des->key. + * CE_CTL_KEYSOURCE_SID: is not support for now. + * CE_CTL_KEYSOURCE_INTERNAL0~7: is not support for now. + * @arg des->key[24]: store the key. some 3DES tool key size may be 8 bytes, is 3 + * copy of the key. + * @param plain: plain data which is need to be encrypt. + * @param cipher: cipher data which is store the encrpyted data. the cipher data + * size is multiple of 8 bytes and no less than plain data size. + * @param size: size of plain data. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_3DES_Encrypt(CE_3DES_Config *des, uint8_t *plain, uint8_t *cipher, uint32_t size) +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + + /* CE config */ + CE_Crypto_Init(CE, CE_CTL_METHOD_3DES, des->mode, CE_CRYPT_OP_ENCRYPTION); + CE_3DES_SetKey(CE, des->src, (uint32_t *)des->key); + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_SetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#endif + + /* plain data convey to CE and cipher data convey from CE */ + HAL_Crypto_Convey(plain, cipher, size, DES3_BLOCK_SIZE); + + /* CE state storage */ + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_GetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#endif + + CE_Crypto_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); +out: + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Encrypt data by 3DES. + * @note 3DES key size is 24 bytes, or 3 * 8bytes(8bytes key). 3DES block size + * is 8 bytes. + * @param des: + * @arg aes->mode: CE_CRYPT_MODE_ECB or CE_CRYPT_MODE_CBC + * @arg aes->iv[8]: initialization value, is same size as block size. + * CE_CRYPT_MODE_CBC mode need this param, and same as + * the encrypt side. + * @arg aes->src: CE_CTL_KEYSOURCE_INPUT: key is set from aes->key. + * CE_CTL_KEYSOURCE_SID: is not support for now. + * CE_CTL_KEYSOURCE_INTERNAL0~7: is not support for now. + * @arg des->key[24]: store the key. some 3DES tool key size may be 8 + * bytes, is 3 copy of the key. + * @param cipher: cipher data which is needed to be decrypted. the cipher data + * size must be multiple of 8 bytes. + * @param plain: plain data which store the decrypted data. the plain data size + * will be same as cipher data. + * @param size: size of cipher data. size must be multiple of 8 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_3DES_Decrypt(CE_3DES_Config *des, uint8_t *cipher, uint8_t *plain, uint32_t size) +{ + HAL_Status ret = HAL_OK; + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + + /* CE config */ + CE_Crypto_Init(CE, CE_CTL_METHOD_3DES, des->mode, CE_CRYPT_OP_DECRYPTION); + CE_3DES_SetKey(CE, des->src, (uint32_t *)des->key); + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_SetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_SetIV(CE, (uint32_t *)des->iv, 8); +#endif + + /* plain data convey to CE and cipher data convey from CE */ + HAL_Crypto_Convey(cipher, plain, size, 8); + + /* CE state storage */ + if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CBC) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#ifdef CE_CTR_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTR) + CE_Crypto_GetCounter(CE, (uint32_t *)des->cnt, des->width); +#endif +#ifdef CE_CTS_MODE + else if ((CE_CTL_Crypto_Mode)des->mode == CE_CTL_CRYPT_MODE_CTS) + CE_Crypto_GetIV(CE, (uint32_t *)des->iv, 8); +#endif + + CE_Crypto_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); +out: + ce_running = 0; + CE_EXIT(ret); + return ret; +} + + +/************************ CRC MD5 SHA1 SHA256 private **************************************/ +typedef struct { + CE_CTL_CRC_Width width; + uint32_t poly; + uint8_t init; + uint8_t refin; + uint8_t refout; + uint8_t xorout; +} CE_CRC_Config; + +static const CE_CRC_Config crc_cfg[] = { + {CE_CTL_CRC_WIDTH_16BITS, 0x8005, 0, 1, 1, 0}, /* CE_CRC16_IBM, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x8005, 0, 1, 1, 1}, /* CE_CRC16_MAXIM, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x8005, 1, 1, 1, 1}, /* CE_CRC16_USB, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x8005, 1, 1, 1, 0}, /* CE_CRC16_MODBUS, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x1021, 0, 1, 1, 0}, /* CE_CRC16_CCITT, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x1021, 1, 0, 0, 0}, /* CE_CRC16_CCITT_1 */ + {CE_CTL_CRC_WIDTH_16BITS, 0x1021, 1, 1, 1, 1}, /* CE_CRC16_X25, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x1021, 0, 0, 0, 0}, /* CE_CRC16_XMODEM, */ + {CE_CTL_CRC_WIDTH_16BITS, 0x3d65, 0, 1, 1, 1}, /* CE_CRC16_DNP, */ + {CE_CTL_CRC_WIDTH_32BITS, 0x04c11db7, 1, 1, 1, 1}, /* CE_CRC32, */ + {CE_CTL_CRC_WIDTH_32BITS, 0x04c11db7, 1, 0, 0, 0}, /* CE_CRC32_MPEG2, */ +}; + +static HAL_Status HAL_CRC_Hash_InitDMA(DMA_Channel *input) +{ + HAL_Status ret = HAL_OK; + DMA_ChannelInitParam Input_param; + memset(&Input_param, 0, sizeof(Input_param)); + CE_ENTRY(); + + if ((*input = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + CE_ALERT("DMA request failed \n"); + goto out; + } + + Input_param.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_16, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_32BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_CE, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_4, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM); + Input_param.irqType = DMA_IRQ_TYPE_END; + Input_param.endCallback = HAL_CE_DMACmpl; + Input_param.endArg = &ce_block; + + HAL_DMA_Init(*input, &Input_param); + CE_EnableDMA(CE); + +out: + CE_EXIT(ret); + return ret; +} + +static void HAL_CRC_Hash_DenitDMA(DMA_Channel input) +{ + CE_ENTRY(); + CE_DisableDMA(CE); + HAL_DMA_DeInit(input); + HAL_DMA_Release(input); + CE_EXIT(0); +} + +static HAL_Status HAL_CRC_Hash_Convey(DMA_Channel input, CE_Fifo_Align *align, uint8_t *data, uint32_t size) +{ + HAL_Status ret = HAL_OK; + uint32_t align_len; + uint32_t buf_left = 4 - align->word_size; + CE_ENTRY(); + CE_DEBUG("input size = %d, buf_left = %d\n", size, buf_left); + + if (size < buf_left) { + memcpy(align->word, data, size); + align->word_size += size; + CE_ASSERT(align->word_size < 4); + goto out; + } + + CE_SetInputThreshold(CE, 0); + + memcpy(&align->word[align->word_size], data, buf_left); + HAL_DMA_Start(input, (uint32_t)align->word, (uint32_t)CE_Crypto_GetInputAddr(CE), 4); + if ((ret = HAL_SemaphoreWait(&ce_block, CE_WAIT_TIME)) != HAL_OK) { + CE_ALERT("DMA transfer 1st block failed\n"); + goto out; + } + HAL_DMA_Stop(input); + + align->word_size = (size - buf_left) & 0x3; // len % 4 + align_len = size - buf_left - align->word_size; +// CE_DEBUG("align_len = %d, new buf_left should be = %d\n", align_len, align->word_size); + + if (align_len != 0) { + HAL_DMA_Start(input, (uint32_t)(data + buf_left), (uint32_t)CE_Crypto_GetInputAddr(CE), align_len); + if ((ret = HAL_SemaphoreWait(&ce_block, CE_WAIT_TIME)) != HAL_OK) { + CE_ALERT("DMA transfer 2rd block failed\n"); + goto out; + } + HAL_DMA_Stop(input); + } + +// CE_DEBUG("data copy from %d\n", size - align->word_size); + memset(align->word, 0, sizeof(align->word)); + memcpy(align->word, data + size - align->word_size, align->word_size); + +out: + CE_EXIT(ret); + return ret; +} + +HAL_Status HAL_MD5_Append(CE_MD5_Handler *hdl, uint8_t *data, uint32_t size); + +static void HAL_Hash_Finish(CE_MD5_Handler *hdl, uint64_t bit_size) +{ + uint32_t pad_size; + uint32_t remain_size = hdl->total_size & 0x3f; // len % 64 + uint32_t total_size = hdl->total_size; + uint8_t pad[128] = {0}; + + CE_ENTRY(); +// CE_DEBUG("total size before padding = %d, remain size = %d.\n", (uint32_t)hdl->total_size, (uint32_t)remain_size); + + if (remain_size < 56) + pad_size = 64 - remain_size - 8 - 1; + else + pad_size = 128 - remain_size - 8 - 1; + pad[0] = 0x80; + memcpy(&pad[1 + pad_size], &bit_size, 8); + +// CE_DEBUG("pad size = %d, buf size = %d, len copy to %d.\n", (uint32_t)pad_size, (uint32_t)hdl->word_size, (uint32_t)(1 + pad_size)); + + HAL_MD5_Append(hdl, pad, pad_size + 1 + 8); + + CE_ASSERT(((total_size + pad_size + 1 + 8) & 0x3f) == 0); +// CE_DEBUG("append size = %d, final total size = 0x%x.\n", (uint32_t)(pad_size + 1 + 8), (uint32_t)(total_size + pad_size + 1 + 8)); + + CE_Hash_Finish(CE); + CE_EXIT(0); +} +/************************ public **************************************/ + +/** + * @brief Initialize CRC module. + * @param hdl: It's a handler stored private info. created by user. + * @param type: CRC algorithm. + * @param total_size: the total size of data needed to calculate crc. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_CRC_Init1(CE_CRC_Handler *hdl, CE_CRC_Types type, uint32_t total_size) +{ + HAL_Status ret = HAL_OK; + const CE_CRC_Config *config = &crc_cfg[type]; + + CE_ENTRY(); + + if (total_size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + HAL_CE_EnableCCMU(); + + hdl->type = type; + hdl->crc = 0; + hdl->word_size = 0; + HAL_Memset(hdl->word, 0, sizeof(hdl->word)); + + CE_CRC_Init(CE, config->init, + config->xorout, + config->refin, + config->refout, + config->width, + config->poly); + CE_CRC_SetResult(CE, 0); + CE_SetLength(CE, total_size); + CE_Enable(CE); + + CE_REG_ALL(CE); + +out: + CE_EXIT(ret); + return ret; +} + +HAL_Status HAL_CRC_Init(CE_CRC_Handler *hdl, CE_CRC_Types type, uint32_t total_size) +{ + uint32_t crc; + + /* temperarily bug fixed */ + HAL_CRC_Init1(hdl, CE_CRC32, 1); + HAL_CRC_Append(hdl, (uint8_t *)hdl, 1); + HAL_CRC_Finish(hdl, &crc); + + HAL_Memset(hdl, 0, sizeof(*hdl)); + return HAL_CRC_Init1(hdl, type, total_size); +} + + +/** + * @brief Append data to calculate crc. it can be append several times before + * HAL_CRC_Finish. + * @param hdl: It's a handler stored private info. + * @param data: data needed to calculate crc. + * @param size: size of data. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_CRC_Append(CE_CRC_Handler *hdl, uint8_t *data, uint32_t size) +{ + HAL_Status ret = HAL_OK; + DMA_Channel input; + + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + if ((ret = HAL_CRC_Hash_InitDMA(&input)) != HAL_OK){ + CE_ALERT("DMA Request failed\n"); + goto out; + } + HAL_CRC_Hash_Convey(input, (CE_Fifo_Align *)(&hdl->word[0]), data, size); + HAL_CRC_Hash_DenitDMA(input); + + hdl->total_size += size; + +out: + CE_EXIT(ret); + return ret; +} + +/** + * @brief Calculate the crc of all appended data. + * @param hdl: It's a handler stored private info. + * @param crc: Store the result of calculation of crc. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_CRC_Finish(CE_CRC_Handler *hdl, uint32_t *crc) +{ + HAL_Status ret = HAL_OK; + uint8_t pad[4] = {0}; + + CE_ENTRY(); + + HAL_CRC_Append(hdl, pad, (4 - hdl->word_size) & 0x03); + + CE_CRC_Finish(CE); + while (CE_Status(CE, CE_INT_TPYE_HASH_CRC_END) == 0); // use irq would be better + CE_CRC_Calc(CE, crc); + CE_REG_ALL(CE); + CE_REG(CE->CRC_RESULT); + + CE_Disable(CE); + CE_CRC_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); + + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Initialize MD5 module. + * @param hdl: It's a handler stored private info. created by user. + * @param src: Selected IV source + * @arg CE_CTL_IVMODE_SHA_MD5_FIPS180: use FIPS180 IV. + * @arg CE_CTL_IVMODE_SHA_MD5_INPUT: IV from param iv[4]. + * @param iv: MD5 Initialization Value. size of iv must be 16 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_MD5_Init(CE_MD5_Handler *hdl, CE_Hash_IVsrc src, uint32_t iv[4]) +{ + HAL_Status ret = HAL_OK; + + CE_ENTRY(); + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + CE_Hash_Init(CE, CE_CTL_METHOD_MD5); + CE_Hash_SetIV(CE, src, iv, CE_MD5_IV_SIZE); + + hdl->total_size = 0; + hdl->word_size = 0; + memset(hdl->word, 0, sizeof(hdl->word)); + + CE_REG_ALL(CE); + +out: + CE_EXIT(ret); + return ret; +} + +/** + * @brief Append MD5 data to calculate. + * @param hdl: It's a handler stored private info. created by user. + * @param data: the data needed to calculate md5. + * @param size: size of data. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_MD5_Append(CE_MD5_Handler *hdl, uint8_t *data, uint32_t size) +{ + HAL_Status ret = HAL_OK; + DMA_Channel input; + + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + if ((ret = HAL_CRC_Hash_InitDMA(&input)) != HAL_OK){ + CE_ALERT("DMA Request failed\n"); + goto out; + } + HAL_CRC_Hash_Convey(input, (CE_Fifo_Align *)(&hdl->word[0]), data, size); + HAL_CRC_Hash_DenitDMA(input); + + hdl->total_size += size; + +out: + CE_EXIT(ret); + return ret; +} + +/** + * @brief Calculate the MD5 of all appended data. + * @param hdl: It's a handler stored private info. + * @param digest: Store the result of calculation of MD5, result + * need 16 bytes space. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_MD5_Finish(CE_MD5_Handler *hdl, uint32_t digest[4]) +{ + HAL_Status ret = HAL_OK; + uint64_t bit_size = htole64(hdl->total_size << 3); + + CE_ENTRY(); + + HAL_Hash_Finish(hdl, bit_size); + while (CE_Status(CE, CE_INT_TPYE_HASH_CRC_END) == 0); // use irq would be better + CE_REG_ALL(CE); + CE_Hash_Calc(CE, CE_CTL_METHOD_MD5, digest); + + CE_Hash_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); + + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Initialize SHA1 module. + * @param hdl: It's a handler stored private info. created by user. + * @param src: Selected IV source + * @arg CE_CTL_IVMODE_SHA_MD5_FIPS180: use FIPS180 IV. + * @arg CE_CTL_IVMODE_SHA_MD5_INPUT: IV from param iv[5]. + * @param iv: SHA1 Initialization Value. size of iv must be 20 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SHA1_Init(CE_SHA1_Handler *hdl, CE_Hash_IVsrc src, uint32_t iv[5]) +{ + HAL_Status ret = HAL_OK; + + CE_ENTRY(); + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + CE_Hash_Init(CE, CE_CTL_METHOD_SHA1); + CE_Hash_SetIV(CE, src, iv, CE_SHA1_IV_SIZE); + CE_REG_ALL(CE); + + hdl->total_size = 0; + hdl->word_size = 0; + memset(hdl->word, 0, sizeof(hdl->word)); + +out: + CE_EXIT(ret); + return ret; +} + +/** + * @brief Append SHA1 data to calculate. + * @param hdl: It's a handler stored private info. created by user. + * @param data: the data needed to calculate sha1. + * @param size: size of data. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SHA1_Append(CE_SHA1_Handler *hdl, uint8_t *data, uint32_t size) +{ + HAL_Status ret; + CE_ENTRY(); + + ret = HAL_MD5_Append(hdl, data, size); + + CE_EXIT(ret); + return ret; +} + +/** + * @brief Calculate the SHA1 of all appended data. + * @param hdl: It's a handler stored private info. + * @param digest: Store the result of calculation of SHA1, result + * need 20 bytes space. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SHA1_Finish(CE_SHA1_Handler *hdl, uint32_t digest[5]) +{ + HAL_Status ret = HAL_OK; + uint64_t bit_size = htobe64(hdl->total_size << 3); + CE_ENTRY(); + + HAL_Hash_Finish(hdl, bit_size); + while (CE_Status(CE, CE_INT_TPYE_HASH_CRC_END) == 0); // use irq + CE_REG_ALL(CE); + CE_Hash_Calc(CE, CE_CTL_METHOD_SHA1, digest); + + CE_Hash_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); + + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Initialize SHA256 module. + * @param hdl: It's a handler stored private info. created by user. + * @param src: Selected IV source + * @arg CE_CTL_IVMODE_SHA_MD5_FIPS180: use FIPS180 IV. + * @arg CE_CTL_IVMODE_SHA_MD5_INPUT: IV from param iv[8]. + * @param iv: SHA256 Initialization Value. size of iv must be 32 bytes. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SHA256_Init(CE_SHA256_Handler *hdl, CE_Hash_IVsrc src, uint32_t iv[8]) +{ + HAL_Status ret = HAL_OK; + + CE_ENTRY(); + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + + HAL_CE_EnableCCMU(); + CE_Hash_Init(CE, CE_CTL_METHOD_SHA256); + CE_Hash_SetIV(CE, src, iv, CE_SHA256_IV_SIZE); + CE_REG_ALL(CE); + + hdl->total_size = 0; + hdl->word_size = 0; + memset(hdl->word, 0, sizeof(hdl->word)); + +out: + CE_EXIT(ret); + return ret; +} + +/** + * @brief Append SHA256 data to calculate. + * @param hdl: It's a handler stored private info. created by user. + * @param data: the data needed to calculate sha256. + * @param size: size of data. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SHA256_Append(CE_SHA256_Handler *hdl, uint8_t *data, uint32_t size) +{ + HAL_Status ret; + CE_ENTRY(); + + ret = HAL_MD5_Append(hdl, data, size); + + CE_EXIT(ret); + return ret; +} + +/** + * @brief Calculate the SHA256 of all appended data. + * @param hdl: It's a handler stored private info. + * @param digest: Store the result of calculation of SHA256, result + * need 32 bytes space. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SHA256_Finish(CE_SHA256_Handler *hdl, uint32_t digest[8]) +{ + HAL_Status ret = HAL_OK; + uint64_t bit_size = htobe64(hdl->total_size << 3); + + CE_ENTRY(); + + HAL_Hash_Finish(hdl, bit_size); + while (CE_Status(CE, CE_INT_TPYE_HASH_CRC_END) == 0); // use irq would be better + CE_REG_ALL(CE); + CE_Hash_Calc(CE, CE_CTL_METHOD_SHA256, digest); + + CE_Hash_Deinit(CE); + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); + + ce_running = 0; + CE_EXIT(ret); + return ret; +} + +/** + * @brief Generate some random numbers. + * @param random: a buffer to store random number, create by user. + * @param size: size of random number to generate. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_PRNG_Generate(uint8_t *random, uint32_t size) +{ + HAL_Status ret = HAL_OK; + uint32_t seed[6]; + uint32_t rand[5]; + uint8_t *p = random; + uint32_t cpsize; + + CE_ENTRY(); + + if (size == 0) { + ret = HAL_INVALID; + goto out; + } + + ce_running = 1; + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + HAL_CE_EnableCCMU(); + + while (1) { + + seed[0] = HAL_Ticks(); + seed[1] = HAL_Ticks(); + seed[2] = HAL_Ticks(); + seed[3] = HAL_Ticks(); + seed[4] = HAL_Ticks(); + seed[5] = HAL_Ticks(); + + CE_PRNG_Init(CE, 0); + CE_PRNG_Seed(CE, seed); + CE_REG_ALL(CE); + CE_PRNG_Generate(CE, rand); + cpsize = (size > 20) ? 20 : size; + memcpy(p, (uint8_t *)rand, cpsize); + if (size <= 20) + break; + p += cpsize; + size -= cpsize; + } + + CE_REG_ALL(CE); + CE_PRNG_Deinit(CE); + + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); + + out: + ce_running = 0; + CE_EXIT(ret); + return ret; + +} +/* +HAL_Status HAL_PRNG_Generate(uint32_t random[5]) +{ + HAL_Status ret = HAL_OK; + uint32_t seed[6]; + uint32_t tick; + + CE_ENTRY(); + + if ((ret = HAL_MutexLock(&ce_lock, CE_WAIT_TIME)) != HAL_OK) + goto out; + HAL_CE_EnableCCMU(); + + tick = HAL_Ticks(); + + seed[0] = tick; + seed[2] = seed[2] ^ HAL_Ticks(); + seed[4] = seed[0] ^ seed[1] ^ seed[2] ^ seed[3] ^ HAL_Ticks(); + seed[5] = seed[0] ^ seed[4] ^ seed[2] ^ seed[3] ^ HAL_Ticks(); + + CE_PRNG_Init(CE, 0); + CE_PRNG_Seed(CE, seed); + CE_REG_ALL(CE); + CE_PRNG_Generate(CE, random); + + CE_REG_ALL(CE); + CE_PRNG_Deinit(CE); + + HAL_CE_DisableCCMU(); + HAL_MutexUnlock(&ce_lock); + +out: + CE_EXIT(ret); + return ret; +} +*/ + + diff --git a/platform/mcu/xr871/src/driver/chip/hal_csi.c b/platform/mcu/xr871/src/driver/chip/hal_csi.c new file mode 100644 index 0000000000..ad140a41b1 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_csi.c @@ -0,0 +1,393 @@ +/** + * @file hal_csi.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_csi.h" +#include "driver/chip/hal_gpio.h" +#include "driver/chip/hal_dma.h" +#include "hal_base.h" + +#define CSI_DEBUG 1 + +#define HAL_CSI_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + printf(fmt, ##arg); \ + } while (0) + + +#define HAL_CSI_DBG(fmt, arg...) \ + HAL_CSI_LOG(CSI_DEBUG, "[HAL_CSI] "fmt, ##arg) + + +uint8_t csi_is_run = 0; + +void CSI_ModuleEnable() +{ + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_CSI); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_CSI); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_CSI); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_CSI); +} + +void CSI_ModuleDisable() +{ + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_CSI); +} + +void CSI_InputFormat() //raw +{ + HAL_CLR_BIT(CSI->CSI_CFG_REG , CSI_CFG_INPUT_FORMAT); +} + +void CSI_Irq_Enable() +{ + HAL_NVIC_SetPriority(CSI_IRQn, 0); + HAL_NVIC_EnableIRQ(CSI_IRQn); +} + +void CSI_Irq_Disable() +{ + HAL_NVIC_DisableIRQ(CSI_IRQn); +} + +CSI_Call_Back private_csi_cb; + + +void CSI_IRQHandler() +{ + if(private_csi_cb.callBack != NULL) + private_csi_cb.callBack(private_csi_cb.arg); +} + +/** + *@private + *@brief Initializes the CSI peripheral according to the specified parameters + * in the CSI_Config *param. + * @note This function is used to configure the source clock and pins of the CSI. + * The source clock freq is the mclk output freq. + * @param param: + * @arg param->src_Clk.clk used for select the source clock of CSI + * @arg param->src_Clk.divN * param->src_Clk.divM = The clock division + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_CSI_Config(CSI_Config *param) +{ + if (csi_is_run) { + HAL_WRN("%s, %d csi is busy\n", __func__, __LINE__); + return HAL_BUSY; + } + CSI_ModuleEnable(); + HAL_CCM_CSI_SetMClock(param->src_Clk.clk, param->src_Clk.divN, param->src_Clk.divM); + HAL_CCM_CSI_EnableMClock(); + + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_CSI, 0), 0); + csi_is_run = 1; + CSI_InputFormat(); + return HAL_OK; +} + +/** + * @brief Deinitializes all CSI peripherals registers and pins to their default reset + * values. + * @param None + * @retval None + */ +void HAL_CSI_DeInit(void) +{ + HAL_CLR_BIT(CSI->CSI_EN_REG, CSI_EN); + HAL_CCM_CSI_DisableMClock(); + CSI_ModuleDisable(); + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_CSI, 0), 0); + csi_is_run = 0; +} + +/** + * @brief Enables or disables the CSI interface. + * @param ctrl: Controls the enable of CSI moudle. + * @arg This parameter can be: CSI_ENABLE or CSI_DISABLE. + * @retval None + */ +void HAL_CSI_Moudle_Enalbe(CSI_CTRL ctrl) +{ + if (CSI_ENABLE == ctrl) + HAL_SET_BIT(CSI->CSI_EN_REG, CSI_EN); + else + HAL_CLR_BIT(CSI->CSI_EN_REG, CSI_EN); +} + +/** + * @brief Configure the CSI sync signal polarity. + * @param signal: Set the polarity for vsync, herf,p_Clk. + * @retval None + */ +void HAL_CSI_Sync_Signal_Polarity_Cfg(CSI_Sync_Signal *signal) +{ + uint32_t csi_sync_pol; + csi_sync_pol = signal->vsync + (signal->herf << 1) + (signal->p_Clk << 2); + HAL_CLR_BIT(CSI->CSI_CFG_REG, CSI_CFG_SYNC_SIGNAL_POL); + HAL_SET_BIT(CSI->CSI_CFG_REG, csi_sync_pol); +} + +/** + * @brief Enables or disables the CSI capture data. + * @param mode: Select the capture mode. + * @arg CSI_STILL_MODE: capture one picture. + * @arg CSI_VIDEO_MODE:Continuous capture. + * @param ctrl: Controls the enable of CSI capture. + * @arg This parameter can be: CSI_ENABLE or CSI_DISABLE. + * @retval None + */ +void HAL_CSI_Capture_Enable(CSI_CAPTURE_MODE mode , CSI_CTRL ctrl) +{ + HAL_CLR_BIT(CSI->CSI_CAP_REG, CSI_CAP_MODE); + + if (CSI_ENABLE == ctrl) { + if (mode == CSI_STILL_MODE) { + HAL_SET_BIT(CSI->CSI_CAP_REG, HAL_BIT(0)); + } else if (mode == CSI_VIDEO_MODE) + HAL_SET_BIT(CSI->CSI_CAP_REG, HAL_BIT(1)); + } +} + +/** + * @brief Configure the CSI interval capture. + * @note This function is used to Configure interlaced acquisition and interlaced pixels. + * @param vermask: the interlaced pixels value. + * @param hor_mask: the interlaced acquisition. + * @retval None + */ +void HAL_CSI_Interval_Capture_Cfg(uint8_t ver_mask, uint16_t hor_mask) +{ + HAL_CLR_BIT(CSI->CSI_SCALE_REG, CSI_VER_MASK); + HAL_CLR_BIT(CSI->CSI_SCALE_REG, CSI_HER_MASK); + + HAL_SET_BIT(CSI->CSI_SCALE_REG, ver_mask << 24); + HAL_SET_BIT(CSI->CSI_SCALE_REG, hor_mask); +} + +/** + * @brief Select the next FIFO for cache data. + * @param fifo_num: + * @arg CSI_FIFO_0_A: Select CSI_FIFO_0_A. + * @arg CSI_FIFO_0_B: Select CSI_FIFO_0_B. + * @retval None + */ +void HAL_CSI_Selection_Next_FIFO (CSI_FIFO fifo_num) +{ + HAL_CLR_BIT(CSI->CSI_BUF_CTL_REG ,HAL_BIT(2)); + HAL_SET_BIT(CSI->CSI_BUF_CTL_REG , fifo_num << 2); +} + +/** + * @brief Gets the currently used FIFO. + * @param None. + * @retval CSI_FIFO: The FIFO that currently used. + */ +CSI_FIFO HAL_CSI_Current_FIFO() +{ + return (HAL_GET_BIT(CSI->CSI_BUF_CTL_REG, HAL_BIT(1)) >> 1); +} + +/** + * @brief Enables or disables used double FIFO for cache the data. + * @note If you disable the double FIFO mode, the CSI_FIFO_A will be always + * used for cache data. + * @param ctrl: Controls the enable of double FIFO mode. + * @arg This parameter can be: CSI_ENABLE or CSI_DISABLE. + * @retval None. + */ +void HAL_CSI_Double_FIFO_Mode_Enable(CSI_CTRL ctrl) +{ + HAL_CLR_BIT(CSI->CSI_BUF_CTL_REG, HAL_BIT(0)); + + if (CSI_ENABLE == ctrl) + HAL_SET_BIT(CSI->CSI_BUF_CTL_REG, HAL_BIT(0)); +} + +/** + * @brief Gets the CSI moudle status. + * @param None. + * @retval CSI_Status: The status of CSI. + */ +CSI_Status HAL_CSI_Status() +{ + CSI_Status sta; + sta.luminance = HAL_GET_BIT(CSI->CSI_BUF_STA_REG, LUM_STATIS) >> 8; + sta.still_Mode = HAL_GET_BIT(CSI->CSI_BUF_STA_REG, HAL_BIT(1)) >> 1; + sta.video_Mode = HAL_GET_BIT(CSI->CSI_BUF_STA_REG, HAL_BIT(0)); + return sta; +} + +/** + * @brief Configure the interrupt flag for CSI. + * @note Set the interrupt source for CSI. + * @param irq_signel: The interrupt flag of CSI. + * @param ctrl: Controls the enable of interrupt flag. + * @arg This parameter can be: CSI_ENABLE or CSI_DISABLE. + * @retval None. + */ +void HAL_CSI_Interrupt_Cfg(CSI_INTERRUPT_SIGNAL irq_signel, CSI_CTRL ctrl) +{ + if (ctrl == CSI_ENABLE) + HAL_SET_BIT(CSI->CSI_INT_EN_REG, irq_signel); + else + HAL_CLR_BIT(CSI->CSI_INT_EN_REG, irq_signel); +} + +/** + * @brief Gets the CSI IRQ status. + * @param None. + * @return The status of CSI IRQ. + * @arg CSI_CAPTURE_DONE_IRQ: The picture capture done. + * @arg CSI_FRAME_DONE_IRQ: The ftame done. + * @arg CSI_FIFO_0_OVERFLOW_IRQ: The FIFO is overflow. + * When this flag appears, you need to restart CSI. + * @arg CSI_ALL_FIFO_OVERFLOW_IRQ: ALL FIFO is overflow. + * When this flag appears, you need to restart CSI. + * @arg CSI_VSYNC_IRQ: Capture a vsync signal. + * @arg CSI_FIFO_0_A_READY_IRQ: The CSI_FIFO_A is ready for read. + * @arg CSI_FIFO_0_B_READY_IRQ: The CSI_FIFO_B is ready for read. + */ +__IO uint32_t HAL_CSI_Interrupt_Sta() +{ + return CSI->CSI_INT_STA_REG; +} + +/** + * @brief Clear the CSI interrupt flag. + * @param None. + * @retval None. + */ +void HAL_CSI_Interrupt_Clear() +{ + HAL_SET_BIT(CSI->CSI_INT_STA_REG, CSI->CSI_INT_STA_REG); +} + +/** + * @brief Sets the size of the captured image. + * @param size: Set the start capture position and the number of pixels per row. + * @arg size->start: start capture position, unit byte.. + * @arg size->hor_len: the number of bytes per row. + * @retval HAL_Status: + * The status of driver. + */ +HAL_Status HAL_CSI_Set_Picture_Size(CSI_Picture_Size *size) +{ + if (size->hor_start > (HAL_BIT(14) - 1)) { + HAL_WRN("%s, %d csi Picture size error hor_start = %d\n", + __func__, __LINE__, size->hor_start); + return HAL_ERROR; + } + + if (size->hor_len > (HAL_BIT(14) - 1)) { + HAL_WRN("%s, %d csi Picture size error hor_len = %d\n", + __func__, __LINE__, size->hor_len); + return HAL_ERROR; + } + + HAL_CLR_BIT(CSI->CSI_HSIZE_REG, CSI_SIZE_REG); + + HAL_SET_BIT(CSI->CSI_HSIZE_REG, size->hor_len << 16); + HAL_SET_BIT(CSI->CSI_HSIZE_REG, size->hor_start); + return HAL_OK; +} + +/** + * @brief Cached data length of FIFO. + * @param None + * @retval CSI_FIFO_Data_Len: The data length of CSI_FIFO_A and CSI_FIFO_B. + * @arg FIFO_0_A_Data_Len: The data length of CSI_FIFO_A. + * @arg FIFO_0_B_Data_Len: The data length of CSI_FIFO_B. + */ +CSI_FIFO_Data_Len HAL_CSI_FIFO_Data_Len() +{ + CSI_FIFO_Data_Len len; + len.FIFO_0_B_Data_Len = HAL_GET_BIT(CSI->CSI_TRUE_DATA_NUM, (CSI_VALID_DATA_LEN << 16)) >> 16; + len.FIFO_0_A_Data_Len = HAL_GET_BIT(CSI->CSI_TRUE_DATA_NUM, CSI_VALID_DATA_LEN); + return len; +} + +/** + * @private + * @brief Enables or disables the CSI JPEG mode. + * @param ctrl: Controls the enable of CSI JPEG mode. + * @arg This parameter can be: CSI_ENABLE or CSI_DISABLE. + * @retval None + */ +void HAL_CIS_JPEG_Mode_Enable(CSI_CTRL ctrl) +{ + if (CSI_ENABLE == ctrl) + HAL_SET_BIT(CSI->CSI_JPEG_MOD_SEL, HAL_BIT(0)); + else + HAL_CLR_BIT(CSI->CSI_JPEG_MOD_SEL, HAL_BIT(0)); +} + +/** + * @brief Enables or disables the CSI interrupt. + * @param cb: The CSI interrupt callback function. + * @param ctrl: Controls the enable of CSI interrupt. + * @arg This parameter can be: CSI_ENABLE or CSI_DISABLE. + * @retval None + */ +void HAL_CSI_Interrupt_Enable(CSI_Call_Back *cb, CSI_CTRL ctrl) +{ + if (CSI_ENABLE == ctrl) { + if (cb == NULL) { + private_csi_cb.callBack = NULL; + private_csi_cb.arg = NULL; + } else + private_csi_cb = *cb; + CSI_Irq_Enable(); + } else { + private_csi_cb.callBack = NULL; + private_csi_cb.arg = NULL; + CSI_Irq_Disable(); + } +} + +void CSI_Printf() +{ + printf("CSI_EN_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_EN_REG, CSI->CSI_EN_REG); + printf("CSI_CFG_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_CFG_REG, CSI->CSI_CFG_REG); + printf("CSI_CAP_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_CAP_REG, CSI->CSI_CAP_REG); + printf("CSI_SCALE_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_SCALE_REG, CSI->CSI_SCALE_REG); + printf("CSI_BUF_CTL_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_BUF_CTL_REG, CSI->CSI_BUF_CTL_REG); + printf("CSI_BUF_STA_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_BUF_STA_REG, CSI->CSI_BUF_STA_REG); + printf("CSI_INT_EN_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_INT_EN_REG, CSI->CSI_INT_EN_REG); + printf("CSI_INT_STA_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_INT_STA_REG, CSI->CSI_INT_STA_REG); + printf("CSI_HSIZE_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_HSIZE_REG, CSI->CSI_HSIZE_REG); + printf("CSI_BF_LEN_REG 0x%x 0x%x\n", (uint32_t)&CSI->CSI_BF_LEN_REG, CSI->CSI_BF_LEN_REG); + printf("CSI_TRUE_DATA_NUM 0x%x 0x%x\n", (uint32_t)&CSI->CSI_TRUE_DATA_NUM, CSI->CSI_TRUE_DATA_NUM); + printf("CSI_JPEG_MOD_SEL 0x%x 0x%x\n", (uint32_t)&CSI->CSI_JPEG_MOD_SEL, CSI->CSI_JPEG_MOD_SEL); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_debug.h b/platform/mcu/xr871/src/driver/chip/hal_debug.h new file mode 100644 index 0000000000..d0da8c6918 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_debug.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_DEBUG_H_ +#define _DRIVER_CHIP_HAL_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* debug */ +#define HAL_SYSLOG printf + +#define HAL_DBG_ON 1 +#define HAL_WRN_ON 1 +#define HAL_ERR_ON 1 +#define HAL_ABORT_ON 0 + +#define HAL_DBG_TIMER 0 +#define HAL_DBG_WDG 0 +#define HAL_DBG_MBOX 0 +#define HAL_DBG_I2C 0 + +#define HAL_ABORT() sys_abort() + +#define HAL_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + HAL_SYSLOG(fmt, ##arg); \ + } while (0) + + +#define HAL_DBG(fmt, arg...) HAL_LOG(HAL_DBG_ON, "[HAL] "fmt, ##arg) + +#define HAL_TIMER_DBG(fmt, arg...) \ + HAL_LOG(HAL_DBG_ON && HAL_DBG_TIMER, "[HAL TIMER] "fmt, ##arg) + +#define HAL_WDG_DBG(fmt, arg...) \ + HAL_LOG(HAL_DBG_ON && HAL_DBG_WDG, "[HAL WDG] "fmt, ##arg) + +#define HAL_MBOX_DBG(fmt, arg...) \ + HAL_LOG(HAL_DBG_ON && HAL_DBG_MBOX, "[HAL MBOX] "fmt, ##arg) + +#define HAL_I2C_DBG(fmt, arg...) \ + HAL_LOG(HAL_DBG_ON && HAL_DBG_I2C, "[HAL I2C] "fmt, ##arg) + +#define HAL_WRN(fmt, arg...) HAL_LOG(HAL_WRN_ON, "[HAL WRN] "fmt, ##arg) + +#define HAL_ERR(fmt, arg...) \ + do { \ + HAL_LOG(HAL_ERR_ON, "[HAL ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (HAL_ABORT_ON) \ + HAL_ABORT(); \ + } while (0) + +#define HAL_ASSERT_PARAM(exp) \ + do { \ + if (!(exp)) { \ + printf("Invalid param at %s:%d", __func__, __LINE__); \ + } \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/hal_dma.c b/platform/mcu/xr871/src/driver/chip/hal_dma.c new file mode 100644 index 0000000000..c95af32fa8 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_dma.c @@ -0,0 +1,328 @@ +/** + * @file hal_dma.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_dma.h" +#include "hal_base.h" + +#define DMA_IRQ_BITS(chan, type) ((uint32_t)type << ((uint32_t)chan << 1)) +#define DMA_IRQ_ALL_BITS ((1 << (DMA_CHANNEL_NUM << 1)) - 1) + +typedef struct { + DMA_IRQCallback endCallback; + void *endArg; +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + DMA_IRQCallback halfCallback; + void *halfArg; +#endif +} DMA_Private; + +static DMA_Private gDMAPrivate[DMA_CHANNEL_NUM]; + +static uint8_t gDMAChannelUsed = 0; + +void DMA_IRQHandler(void) +{ + uint32_t i; + uint32_t irqStatus; +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + uint32_t isHalfPending; +#endif + uint32_t isEndPending; + DMA_Private *priv; + + irqStatus = DMA->IRQ_STATUS & DMA->IRQ_EN & DMA_IRQ_ALL_BITS; /* get pending bits */ + DMA->IRQ_STATUS = irqStatus; /* clear pending bits */ + priv = gDMAPrivate; + + for (i = DMA_CHANNEL_0; i < DMA_CHANNEL_NUM && irqStatus != 0; ++i) { +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + isHalfPending = irqStatus & HAL_BIT(0); + if (isHalfPending && priv[i].halfCallback) { + priv[i].halfCallback(priv[i].halfArg); + } +#endif + isEndPending = irqStatus & HAL_BIT(1); + if (isEndPending && priv[i].endCallback) { + priv[i].endCallback(priv[i].endArg); + } + irqStatus >>= 2; + } +} + +void DMA_EnableIRQ(DMA_Channel chan, DMA_IRQType type) +{ + HAL_SET_BIT(DMA->IRQ_EN, DMA_IRQ_BITS(chan, type)); +} + +void DMA_DisableIRQ(DMA_Channel chan, DMA_IRQType type) +{ + HAL_CLR_BIT(DMA->IRQ_EN, DMA_IRQ_BITS(chan, type)); +} + +int DMA_IsPendingIRQ(DMA_Channel chan, DMA_IRQType type) +{ + return HAL_GET_BIT(DMA->IRQ_STATUS, DMA_IRQ_BITS(chan, type)); +} + +void DMA_ClearPendingIRQ(DMA_Channel chan, DMA_IRQType type) +{ + HAL_SET_BIT(DMA->IRQ_STATUS, DMA_IRQ_BITS(chan, type)); +} + +__STATIC_INLINE void DMA_DisableAllIRQ(DMA_Channel chan) +{ + HAL_CLR_BIT(DMA->IRQ_EN, DMA_IRQ_BITS(chan, DMA_IRQ_TYPE_VMASK)); +} + +__STATIC_INLINE void DMA_ClearAllPendingIRQ(DMA_Channel chan) +{ + uint32_t irqStatus = HAL_GET_BIT(DMA->IRQ_STATUS, + DMA_IRQ_BITS(chan, DMA_IRQ_TYPE_VMASK)); + if (irqStatus) { + DMA->IRQ_STATUS = irqStatus; + } +} + +static void DMA_Attach(void) +{ + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_DMA); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_DMA); +} + +static void DMA_Detach(void) +{ + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_DMA); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_DMA); +} + +/** + * @brief Request an available DMA channel + * @note Before using DMA, an available DMA channel MUST be requested first + * @retval DMA_Channel, DMA_CHANNEL_INVALID on failed + */ +DMA_Channel HAL_DMA_Request(void) +{ + DMA_Channel i; + DMA_Channel chan = DMA_CHANNEL_INVALID; + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + + if (gDMAChannelUsed == 0) { + DMA_Attach(); + } + + for (i = DMA_CHANNEL_0; i < DMA_CHANNEL_NUM; ++i) { + if ((gDMAChannelUsed & HAL_BIT(i)) == 0) { + HAL_SET_BIT(gDMAChannelUsed, HAL_BIT(i)); + chan = i; + break; + } + } + + HAL_ExitCriticalSection(flags); + + return chan; +} + +/** + * @brief Release the DMA channel + * @param[in] chan DMA channel to be released + * @return None + */ +void HAL_DMA_Release(DMA_Channel chan) +{ + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + + HAL_CLR_BIT(gDMAChannelUsed, HAL_BIT(chan)); + + if (gDMAChannelUsed == 0) { + DMA_Detach(); + } + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief Initialize the DMA channel according to the specified parameters + * @param[in] chan DMA channel + * @param[in] param Pointer to DMA_ChannelInitParam structure + * @return None + */ +void HAL_DMA_Init(DMA_Channel chan, const DMA_ChannelInitParam *param) +{ + DMA_Private *priv; + unsigned long flags; + + HAL_ASSERT_PARAM(chan < DMA_CHANNEL_NUM); + + flags = HAL_EnterCriticalSection(); + + priv = &gDMAPrivate[chan]; + + /* set configuration */ + DMA->CHANNEL[chan].CTRL = param->cfg; /* NB: it will stop/reset the DMA channel */ + + /* set callback */ + if (param->irqType & DMA_IRQ_TYPE_END) { + priv->endCallback = param->endCallback; + priv->endArg = param->endArg; + } else { + priv->endCallback = NULL; + priv->endArg = NULL; + } +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + if (param->irqType & DMA_IRQ_TYPE_HALF) { + priv->halfCallback = param->halfCallback; + priv->halfArg = param->halfArg; + } else { + priv->halfCallback = NULL; + priv->halfArg = NULL; + } +#endif + + /* clear pending bits */ +#if 0 + if (DMA_IsPendingIRQ(chan, param->irqType)) { + DMA_ClearPendingIRQ(chan, param->irqType); + } +#else + DMA_ClearAllPendingIRQ(chan); +#endif + + /* enable IRQ */ + if ((DMA->IRQ_EN & DMA_IRQ_ALL_BITS) == 0) { + HAL_NVIC_SetPriority(DMA_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(DMA_IRQn); + } + DMA_EnableIRQ(chan, param->irqType); + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief DeInitialize the specified DMA channel + * @param[in] chan DMA channel + * @return None + */ +void HAL_DMA_DeInit(DMA_Channel chan) +{ + DMA_Private *priv; + unsigned long flags; + + HAL_ASSERT_PARAM(chan < DMA_CHANNEL_NUM); + + flags = HAL_EnterCriticalSection(); + + priv = &gDMAPrivate[chan]; + + DMA_DisableAllIRQ(chan); + if ((DMA->IRQ_EN & DMA_IRQ_ALL_BITS) == 0) { + HAL_NVIC_DisableIRQ(DMA_IRQn); + } + DMA_ClearAllPendingIRQ(chan); + + priv->endCallback = NULL; + priv->endArg = NULL; +#if HAL_DMA_TRANSFER_HALF_IRQ_SUPPORT + priv->halfCallback = NULL; + priv->halfArg = NULL; +#endif + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief Start the DMA transfer of the specified DMA channel + * @param[in] chan DMA channel + * @param[in] srcAddr The source address of DMA transfer + * @param[in] dstAddr The destination address of DMA transfer + * @param[in] datalen The length of data to be transferred from source to destination + * @return None + * + * @note The source/destination address MUST be aligned to the + * source/destination DMA transaction data width defined by DMA_DataWidth. + * @note The date length MUST not be more than DMA_DATA_MAX_LEN. + */ +void HAL_DMA_Start(DMA_Channel chan, uint32_t srcAddr, uint32_t dstAddr, uint32_t datalen) +{ + HAL_ASSERT_PARAM(chan < DMA_CHANNEL_NUM); + HAL_ASSERT_PARAM(datalen <= DMA_DATA_MAX_LEN); + + /* TODO: check alignment of @srcAddr and @dstAddr */ + + DMA->CHANNEL[chan].SRC_ADDR = srcAddr; + DMA->CHANNEL[chan].DST_ADDR = dstAddr; + DMA->CHANNEL[chan].BYTE_CNT = datalen & DMA_BYTE_CNT_VMASK; + HAL_SET_BIT(DMA->CHANNEL[chan].CTRL, DMA_START_BIT); +} + +/** + * @brief Stop the DMA transfer of the specified DMA channel + * @param[in] chan DMA channel + * @return None + */ +void HAL_DMA_Stop(DMA_Channel chan) +{ + HAL_ASSERT_PARAM(chan < DMA_CHANNEL_NUM); + HAL_CLR_BIT(DMA->CHANNEL[chan].CTRL, DMA_START_BIT); /* NB: it will reset the channel */ +} + +/** + * @brief Check the busy status of the specified DMA channel + * @param[in] chan DMA channel + * @return 1 on busy, 0 on idle + */ +int HAL_DMA_IsBusy(DMA_Channel chan) +{ + HAL_ASSERT_PARAM(chan < DMA_CHANNEL_NUM); + return HAL_GET_BIT(DMA->CHANNEL[chan].CTRL, DMA_BUSY_BIT); +} + +/** + * @brief Get the byte counter of the specified DMA channel + * @param[in] chan DMA channel + * @return The byte counter of the specified DMA channel + * - If DMA byte count mode is DMA_BYTE_CNT_MODE_NORMAL, the return value + * is the data length set by HAL_DMA_Start(). + * - If DMA byte count mode is DMA_BYTE_CNT_MODE_REMAIN, the return value + * is the length of the remaining data not transferred. + */ +uint32_t HAL_DMA_GetByteCount(DMA_Channel chan) +{ + HAL_ASSERT_PARAM(chan < DMA_CHANNEL_NUM); + return (DMA->CHANNEL[chan].BYTE_CNT & DMA_BYTE_CNT_VMASK); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_dmic.c b/platform/mcu/xr871/src/driver/chip/hal_dmic.c new file mode 100644 index 0000000000..240d65755f --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_dmic.c @@ -0,0 +1,700 @@ +/** + * @file hal_dmic.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_dma.h" +#include "driver/chip/hal_dmic.h" +#include "sys/xr_debug.h" +#include "hal_base.h" +#include "sys/io.h" +#include "pm/pm.h" + +#define DMIC_DBG_ON 0 + +#if (DMIC_DBG_ON == 1) +#define DMIC_DEBUG(fmt, arg...) HAL_LOG(DMIC_DBG_ON, "[DMIC] "fmt, ##arg) +#else +#define DMIC_DEBUG(fmt, arg...) +#endif +#define DMIC_ERROR(fmt, arg...) HAL_LOG(1, "[DMIC] "fmt, ##arg) + +typedef struct { + bool isHwInit; + bool isInitiate; + bool isSemaphore; + volatile bool isRunning; + DMA_Channel DMAChan; + DMIC_HWParam *hwParam; + DMIC_DataParam dataParam; + uint8_t *usrBuf; + uint32_t length; + HAL_Semaphore rxReady; + volatile uint32_t halfCounter; + volatile uint32_t endCounter; + uint8_t *lastReadPointer; + uint8_t *dmaPointer; + HAL_Mutex devTriggerLock; + uint32_t audioPllParam; + uint32_t audioPllPatParam; +} DMIC_Private; + +typedef enum { + DMIC_PLL_24M = 0U, + DMIC_PLL_22M = 1U, +} DMIC_PLLMode; + +typedef struct { + uint32_t hosc; + uint32_t audio; + uint32_t pllParam; + uint32_t pllPatParam; +} HOSC_DMIC_Type; + +#define DMIC_MEMCPY memcpy +#define DMIC_MALLOC malloc +#define DMIC_FREE free +#define DMIC_MEMSET memset + +#define DMIC_OVERRUN_THRESHOLD 3 + +#ifdef RESERVERD_MEMORY_FOR_DMIC +static uint8_t DMIC_BUF[DMIC_BUF_LENGTH]; +#endif +DMIC_Private gDMICPrivate; +static uint32_t DMIC_BUF_LENGTH = 0; + +/* default hardware configuration */ +static DMIC_HWParam gHwParam = { + DMIC_CTLR_DMICFDT_5MS, + DMIC_FIFOCR_MODE1, + 0x40, + 0xB0, + 1, +}; + +static const HOSC_DMIC_Type dmic_hosc_aud_type[] = { + {HOSC_CLOCK_26M, DMIC_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC26M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC26M}, + {HOSC_CLOCK_26M, DMIC_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC26M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC26M}, + {HOSC_CLOCK_24M, DMIC_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC24M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC24M}, + {HOSC_CLOCK_24M, DMIC_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC24M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC24M}, + {HOSC_CLOCK_40M, DMIC_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC40M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC40M}, + {HOSC_CLOCK_40M, DMIC_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC40M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC40M}, + {HOSC_CLOCK_52M, DMIC_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC52M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC52M}, + {HOSC_CLOCK_52M, DMIC_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC52M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC52M}, +}; + +static uint32_t DMIC_PLLAUDIO_Update(DMIC_PLLMode pll) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + + if (pll != DMIC_PLL_24M && pll != DMIC_PLL_22M) + return -1; + + uint32_t hoscClock = HAL_PRCM_GetHFClock(); + + int i = 0; + for (i = 0; i < ARRAY_SIZE(dmic_hosc_aud_type); i++) { + if ((dmic_hosc_aud_type[i].hosc == hoscClock) && (dmic_hosc_aud_type[i].audio == pll)) { + dmicPrivate->audioPllParam = dmic_hosc_aud_type[i].pllParam; + dmicPrivate->audioPllPatParam = dmic_hosc_aud_type[i].pllPatParam; + break; + } + } + if (i == ARRAY_SIZE(dmic_hosc_aud_type)) { + DMIC_ERROR("Update audio pll failed....\n"); + return -1; + } + return 0; +} + +static void HAL_DMIC_Trigger(bool enable); + +static int DMIC_DMA_BUFFER_CHECK_Threshold() +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + if (dmicPrivate->halfCounter >= DMIC_OVERRUN_THRESHOLD || + dmicPrivate->endCounter >= DMIC_OVERRUN_THRESHOLD) { + HAL_DMIC_Trigger(0); + dmicPrivate->isRunning = 0; + dmicPrivate->halfCounter = 0; + dmicPrivate->endCounter = 0; + dmicPrivate->lastReadPointer = dmicPrivate->usrBuf; + DMIC_ERROR("Rx : overrun and stop dma rx....\n"); + return -1; + } + return 0; +} + +/** + * @internal + * @brief DMA DMIC receive process half complete callback + * @param arg: pointer to a HAL_Semaphore structure that contains + * semaphore. + * @retval None + */ +static void DMIC_DMAHalfCallback(void *arg) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + dmicPrivate->halfCounter ++; + if (DMIC_DMA_BUFFER_CHECK_Threshold() != 0) + return; + if (dmicPrivate->isSemaphore == true) { + dmicPrivate->isSemaphore = false; + HAL_SemaphoreRelease((HAL_Semaphore *)arg); + } +} + +/** + * @internal + * @brief DMA DMIC receive process complete callback + * @param arg: pointer to a HAL_Semaphore structure + * @retval None + */ +static void DMIC_DMAEndCallback(void *arg) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + dmicPrivate->endCounter ++; + if (DMIC_DMA_BUFFER_CHECK_Threshold() != 0) + return; + if (dmicPrivate->isSemaphore == true) { + dmicPrivate->isSemaphore = false; + HAL_SemaphoreRelease((HAL_Semaphore *)arg); + } +} + +/** + * @internal + * @brief Start the DMA Transfer + * @param chan: the specified DMA Channel. + * @param srcAddr: The source memory Buffer address. + * @param dstAddr: The destination memory Buffer address. + * @param datalen: The length of data to be transferred from source to destination. + * @retval None + */ +static void DMIC_DMAStart(DMA_Channel chan, uint32_t srcAddr, uint32_t dstAddr, uint32_t datalen) +{ + HAL_DMA_Start(chan, srcAddr, dstAddr, datalen); +} + +/** + * @internal + * @brief Stop DMA transfer. + * @param chan: the specified DMA Channel.. + * @retval None + */ +static void DMIC_DMAStop(DMA_Channel chan) +{ + HAL_DMA_Stop(chan); +} + +/** + * @internal + * @brief Sets the DMA Transfer parameter. + * @param channel: the specified DMA Channel. + * @param dir: Data transfer direction + * @retval none + */ +static void DMIC_DMASet(DMA_Channel channel) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + DMA_ChannelInitParam dmaParam; + HAL_Memset(&dmaParam, 0, sizeof(dmaParam)); + dmaParam.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_CIRCULAR, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_NORMAL, + DMA_DATA_WIDTH_16BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_16BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_DMIC); + + dmaParam.irqType = DMA_IRQ_TYPE_BOTH; + dmaParam.endCallback = DMIC_DMAEndCallback; + dmaParam.halfCallback = DMIC_DMAHalfCallback; + dmaParam.endArg = &(dmicPrivate->rxReady); + dmaParam.halfArg = &(dmicPrivate->rxReady); + + HAL_DMA_Init(channel, &dmaParam); +} + +/** + * @internal + * @brief enbale/disable DMIC controller. + * @param enable: enable or disable. + * @retval None + */ +static void HAL_DMIC_Trigger(bool enable) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + if (enable) { + HAL_SET_BIT(DMIC->FIFO_CTR, DMIC_FIFOCR_FIFO_FLUSH_BIT); + + if (dmicPrivate->dataParam.channels > 1) { + HAL_SET_BIT(DMIC->DMIC_EN, DMIC_ECR_DATA0_CHL_EN_BIT|DMIC_ECR_DATA0_CHR_EN_BIT); + } else { + HAL_SET_BIT(DMIC->DMIC_EN, DMIC_ECR_DATA0_CHL_EN_BIT); + } + HAL_SET_BIT(DMIC->DMIC_INTC, DMIC_ICR_FIFO_DRQ_EN_BIT); + DMIC_DMAStart(dmicPrivate->DMAChan, (uint32_t)&(DMIC->DMIC_DATA), + (uint32_t)dmicPrivate->usrBuf, dmicPrivate->length); + } else { + DMIC_DMAStop(dmicPrivate->DMAChan); + HAL_CLR_BIT(DMIC->DMIC_INTC, DMIC_ICR_FIFO_DRQ_EN_BIT); + HAL_CLR_BIT(DMIC->DMIC_EN, DMIC_ECR_DATA0_CHL_EN_BIT|DMIC_ECR_DATA0_CHR_EN_BIT); + } +} + +/** + * @brief Receive an amount of data with DMA + * @param buf: pointer to the Receive data buffer. + * @param Size: length of buf to be Receive: + * @retval length of receive data + */ +int32_t HAL_DMIC_Read_DMA(uint8_t *buf, uint32_t size) +{ + if (!buf || size < DMIC_BUF_LENGTH/2) + return HAL_INVALID; + + DMIC_Private *dmicPrivate = &gDMICPrivate; + uint8_t *readPointer = NULL; + uint32_t toRead = DMIC_BUF_LENGTH/2; + uint32_t readSize = 0; + uint8_t *writeBuf = buf; + uint8_t err_flag; /* temp solution to avoid outputing debug message when irq disabled */ + + while (size) { + if (size < toRead) + break; + if (!dmicPrivate->isRunning) { + dmicPrivate->lastReadPointer = dmicPrivate->usrBuf; + DMIC_DEBUG("Rx: record start...\n"); + dmicPrivate->isRunning = 1; + HAL_DMIC_Trigger(1); + } else { + err_flag = 0; + readPointer = dmicPrivate->lastReadPointer; + HAL_DisableIRQ(); + if (dmicPrivate->halfCounter && dmicPrivate->endCounter) { + dmicPrivate->halfCounter = 0; + dmicPrivate->endCounter = 0; + if (dmicPrivate->dmaPointer == dmicPrivate->usrBuf) { + readPointer = dmicPrivate->usrBuf + DMIC_BUF_LENGTH/2; + } else { + readPointer = dmicPrivate->usrBuf; + } + err_flag = 1; + } else if (dmicPrivate->halfCounter ) { + dmicPrivate->halfCounter --; + + } else if (dmicPrivate->endCounter) { + dmicPrivate->endCounter --; + } else { + dmicPrivate->isSemaphore = true; + HAL_EnableIRQ(); + HAL_SemaphoreWait(&dmicPrivate->rxReady, HAL_WAIT_FOREVER); + HAL_DisableIRQ(); + if (dmicPrivate->halfCounter) + dmicPrivate->halfCounter--; + if (dmicPrivate->endCounter) + dmicPrivate->endCounter--; + } + DMIC_MEMCPY(writeBuf, readPointer, toRead); + HAL_EnableIRQ(); + if (err_flag) { + DMIC_ERROR("overrun...\n"); + } + writeBuf += toRead; + size -= toRead; + readSize += toRead; + dmicPrivate->lastReadPointer = readPointer + toRead; + if (dmicPrivate->lastReadPointer >= dmicPrivate->usrBuf + DMIC_BUF_LENGTH) + dmicPrivate->lastReadPointer = dmicPrivate->usrBuf; + } + } + return readSize; +} + +/** + * @internal + * @brief DMIC peripheral Init + * @param param: pointer to a DMIC_HWParam structure that contains + * some hardware configuration information + * @retval HAL status + */ +static inline HAL_Status DMIC_HwInit(DMIC_HWParam *param) +{ + if (!param) + return HAL_INVALID; + /* Set delay time */ + HAL_MODIFY_REG(DMIC->DMIC_CTR, DMIC_CTLR_DMICFDT_MASK,param->delayTime); + /*Set fifo mode*/ + HAL_MODIFY_REG(DMIC->FIFO_CTR, DMIC_FIFOCR_MODE_MASK|DMIC_FIFOCR_TRG_LEVEL_MASK, + param->fifoMode|DMIC_FIFOCR_TRG_LEVEL(param->triggerLevel)); + /* Set volume gain*/ + HAL_MODIFY_REG(DMIC->DATA0_DATA1_VOL_CTR, DMIC_DATA0L_VOL_MASK|DMIC_DATA0R_VOL_MASK, + DMIC_DATA0L_VOL(param->volumeGain)|DMIC_DATA0R_VOL(param->volumeGain)); + if (param->hpfEnable) { + /* Set HPF*/ + HAL_SET_BIT(DMIC->HPF_EN_CTR, DMIC_HPF_DATA0_CHL_EN_BIT|DMIC_HPF_DATA0_CHR_EN_BIT); + } + /* Global enable */ + HAL_SET_BIT(DMIC->DMIC_EN, DMIC_ECR_GLOBE_EN); + return HAL_OK; +} + +/** + * @internal + * @brief DeInitializes the DMIC peripheral + * @param param: pointer to a DMIC_HWParam structure that contains + * some hardware configuration information. + * @retval HAL status + */ +static inline HAL_Status DMIC_HwDeInit(DMIC_HWParam *param) +{ + if (!param) + return HAL_INVALID; + if (param->hpfEnable) { + /* close HPF*/ + HAL_CLR_BIT(DMIC->HPF_EN_CTR, DMIC_HPF_DATA0_CHL_EN_BIT|DMIC_HPF_DATA0_CHR_EN_BIT); + } + /* Global disable */ + HAL_CLR_BIT(DMIC->DMIC_EN, DMIC_ECR_GLOBE_EN); + return HAL_OK; +} + +/** + * @brief Open the DMIC module according to the specified parameters + * in the DMIC_DataParam. + * @param param: pointer to a DMIC_DataParam structure that contains + * the data format information + * @retval HAL status + */ +HAL_Status HAL_DMIC_Open(DMIC_DataParam *param) +{ + DMIC_DEBUG("Dmic open.\n"); + + if (!param) + return HAL_INVALID; + DMIC_Private *dmicPrivate = &gDMICPrivate; + + if (dmicPrivate->isInitiate == true) { + DMIC_ERROR("DMIC opened already,faild...\n"); + return HAL_INVALID; + } + dmicPrivate->isInitiate = true; + + DMIC_MEMCPY(&(dmicPrivate->dataParam), param, sizeof(*param)); + + DMIC_BUF_LENGTH = param->bufSize; + dmicPrivate->DMAChan = DMA_CHANNEL_INVALID; + dmicPrivate->length = DMIC_BUF_LENGTH; +#ifdef RESERVERD_MEMORY_FOR_DMIC + dmicPrivate->usrBuf = DMIC_BUF; +#else + dmicPrivate->usrBuf = DMIC_MALLOC(DMIC_BUF_LENGTH); + if(dmicPrivate->usrBuf) + DMIC_MEMSET(dmicPrivate->usrBuf,0,DMIC_BUF_LENGTH); + else { + DMIC_ERROR("Malloc buf(for DMA),faild...\n"); + return HAL_ERROR; + } +#endif + /*request DMA channel*/ + dmicPrivate->DMAChan = HAL_DMA_Request(); + if (dmicPrivate->DMAChan == DMA_CHANNEL_INVALID) { + DMIC_ERROR("Request DMA channel(for DMIC),faild...\n"); + DMIC_FREE(dmicPrivate->usrBuf); + return HAL_ERROR; + } + HAL_SemaphoreInitBinary(&dmicPrivate->rxReady); + + HAL_MODIFY_REG(DMIC->CH_NUM, DMIC_CH_NUM_MASK,(param->channels - 1)); + + /* Enable chl chr(data0) */ + if (param->channels > 1) { + HAL_SET_BIT(DMIC->DMIC_EN, DMIC_ECR_DATA0_CHL_EN_BIT|DMIC_ECR_DATA0_CHR_EN_BIT); + + HAL_MODIFY_REG(DMIC->CH_MAP, DMIC_CMR_CH0_MAP_MASK(0)| DMIC_CMR_CH0_MAP_MASK(1), + DMIC_CMR_CH0_MAP(0)|DMIC_CMR_CH0_MAP(1)); + } else { + HAL_SET_BIT(DMIC->DMIC_EN, DMIC_ECR_DATA0_CHL_EN_BIT); + HAL_MODIFY_REG(DMIC->CH_MAP, DMIC_CMR_CH0_MAP_MASK(0),DMIC_CMR_CH0_MAP(0)); + } + + switch (param->sampleRate) { + case DMIC_SR48KHZ: + case DMIC_SR24KHZ: + case DMIC_SR12KHZ: + case DMIC_SR32KHZ: + case DMIC_SR16KHZ: + case DMIC_SR8KHZ: + DMIC_PLLAUDIO_Update(DMIC_PLL_24M); + HAL_PRCM_SetAudioPLLParam(dmicPrivate->audioPllParam); + HAL_PRCM_SetAudioPLLPatternParam(dmicPrivate->audioPllPatParam); + break; + case DMIC_SR44KHZ: + case DMIC_SR22KHZ: + case DMIC_SR11KHZ: + DMIC_PLLAUDIO_Update(DMIC_PLL_22M); + HAL_PRCM_SetAudioPLLParam(dmicPrivate->audioPllParam); + HAL_PRCM_SetAudioPLLPatternParam(dmicPrivate->audioPllPatParam); + break; + default: + DMIC_ERROR("Invalued Samplerate...\n"); + + } + + /* Set DMIC oversample rate*/ + switch (param->sampleRate) { + case DMIC_SR48KHZ: + case DMIC_SR24KHZ: + case DMIC_SR44KHZ: + case DMIC_SR22KHZ: + case DMIC_SR32KHZ: + HAL_MODIFY_REG(DMIC->DMIC_CTR, DMIC_CTLR_OVERSAMPLE_RATE_MASK, + DMIC_CTLR_OVERSAMPLE_RATE64); + break; + case DMIC_SR16KHZ: + case DMIC_SR12KHZ: + case DMIC_SR8KHZ: + case DMIC_SR11KHZ: + HAL_MODIFY_REG(DMIC->DMIC_CTR, DMIC_CTLR_OVERSAMPLE_RATE_MASK, + DMIC_CTLR_OVERSAMPLE_RATE128); + break; + } + + if (param->sampleRate == DMIC_SR44KHZ) { + param->sampleRate = DMIC_SR48KHZ; + } else if (param->sampleRate == DMIC_SR22KHZ) { + param->sampleRate = DMIC_SR24KHZ; + } else if (param->sampleRate == DMIC_SR11KHZ) { + param->sampleRate = DMIC_SR12KHZ; + } + + /* Set sample rate*/ + HAL_MODIFY_REG(DMIC->DMIC_SR, DMIC_SR_MASK,param->sampleRate); + + /* Set sample resolution */ + HAL_MODIFY_REG(DMIC->FIFO_CTR, DMIC_FIFOCR_SAMPLE_RES_MASK,param->resolution); + + /* init DMA*/ + if (dmicPrivate->DMAChan != DMA_CHANNEL_INVALID) + DMIC_DMASet(dmicPrivate->DMAChan); + + return HAL_OK; +} + +/** + * @brief Close the DMIC module + * @note The module is closed at the end of transaction to avoid power consumption + * @retval none + */ +void HAL_DMIC_Close() +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + HAL_DMIC_Trigger(false); + dmicPrivate->isRunning = false; + dmicPrivate->isInitiate = false; + + if (dmicPrivate->DMAChan != DMA_CHANNEL_INVALID) { + HAL_DMA_DeInit(dmicPrivate->DMAChan); + HAL_DMA_Release(dmicPrivate->DMAChan); + dmicPrivate->DMAChan = DMA_CHANNEL_INVALID; + } + DMIC_MEMSET(&(dmicPrivate->dataParam), 0, sizeof(DMIC_DataParam)); +#ifndef RESERVERD_MEMORY_FOR_DMIC + DMIC_FREE(dmicPrivate->usrBuf); +#endif + dmicPrivate->usrBuf= NULL; + dmicPrivate->length = 0; + dmicPrivate->halfCounter = 0; + dmicPrivate->endCounter = 0; +} + +/** + * @internal + * @brief DMIC PINS Init + * @retval HAL status + */ +static inline HAL_Status DMIC_PINS_Init() +{ + return HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_DMIC, 0), 0); +} + +/** + * @internal + * @brief DMIC PINS DeInit + * @retval HAL status + */ +static inline HAL_Status DMIC_PINS_DeInit() +{ + return HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_DMIC, 0), 0); +} + +#ifdef CONFIG_PM +static int dmic_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + DMIC_HwDeInit(dmicPrivate->hwParam); + DMIC_PINS_DeInit(); + HAL_CCM_DMIC_DisableMClock(); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_DMIC); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_DMIC); + HAL_PRCM_DisableAudioPLL(); + HAL_PRCM_DisableAudioPLLPattern(); + break; + default: + break; + } + return 0; +} + +static int dmic_resume(struct soc_device *dev, enum suspend_state_t state) +{ + DMIC_Private *dmicPrivate = &gDMICPrivate; + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + DMIC_PLLAUDIO_Update(DMIC_PLL_24M); + HAL_PRCM_SetAudioPLLParam(dmicPrivate->audioPllParam); + HAL_PRCM_SetAudioPLLPatternParam(dmicPrivate->audioPllPatParam); + HAL_PRCM_EnableAudioPLL(); + HAL_PRCM_EnableAudioPLLPattern(); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_DMIC); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_DMIC); + + /*init and enable clk*/ + HAL_CCM_DMIC_EnableMClock(); + /*init gpio*/ + DMIC_PINS_Init(); + DMIC_HwInit(dmicPrivate->hwParam); + break; + default: + break; + } + + return 0; +} + +static struct soc_device_driver dmic_drv = { + .name = "DMIC", + .suspend = dmic_suspend, + .resume = dmic_resume, +}; + +static struct soc_device dmic_dev = { + .name = "DMIC", + .driver = &dmic_drv, +}; + +#define DMIC_DEV (&dmic_dev) +#else +#define DMIC_DEV NULL +#endif + +/** + * @brief Initializes the DMIC according to the specified parameters + * in the DMIC_Param. + * @param param: pointer to a DMIC_Param structure that contains + * the hw configuration information for DMIC controller + * @retval HAL status + */ +HAL_Status HAL_DMIC_Init(DMIC_Param *param) +{ + int32_t ret = 0; + DMIC_DEBUG("Dmic init.\n"); + if (!param) + return HAL_INVALID; + + DMIC_Private *dmicPrivate = &gDMICPrivate; + + if (dmicPrivate->isHwInit) + return HAL_OK; + DMIC_MEMSET(dmicPrivate,0,sizeof(struct DMIC_Private *)); + dmicPrivate->isHwInit = true; + + if (!param->hwParam) + dmicPrivate->hwParam = &gHwParam; + else + dmicPrivate->hwParam = param->hwParam; + + /*init and enable clk*/ + DMIC_PLLAUDIO_Update(DMIC_PLL_24M); + HAL_PRCM_SetAudioPLLParam(dmicPrivate->audioPllParam); + HAL_PRCM_EnableAudioPLL(); + HAL_PRCM_SetAudioPLLPatternParam(dmicPrivate->audioPllPatParam); + HAL_PRCM_EnableAudioPLLPattern(); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_DMIC); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_DMIC); + /*init and enable clk*/ + HAL_CCM_DMIC_EnableMClock(); + + /*init gpio*/ + DMIC_PINS_Init(); +#ifdef CONFIG_PM + pm_register_ops(DMIC_DEV); +#endif + ret = DMIC_HwInit(dmicPrivate->hwParam); + return ret; +} + +/** + * @brief DeInitializes the DMIC module + * @retval + */ +void HAL_DMIC_DeInit() +{ + DMIC_DEBUG("Dmic deinit.\n"); + + DMIC_Private *dmicPrivate = &gDMICPrivate; + + DMIC_HwDeInit(dmicPrivate->hwParam); + DMIC_PINS_DeInit(); + + HAL_CCM_DMIC_DisableMClock(); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_DMIC); + HAL_PRCM_DisableAudioPLLPattern(); + HAL_PRCM_DisableAudioPLL(); + + DMIC_MEMSET(dmicPrivate,0,sizeof(struct DMIC_Private *)); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_efuse.c b/platform/mcu/xr871/src/driver/chip/hal_efuse.c new file mode 100644 index 0000000000..4ca13e58e4 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_efuse.c @@ -0,0 +1,320 @@ +/** + * @file hal_efuse.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_efuse.h" +#include "hal_base.h" + +typedef enum { + EFUSE_STATE_INVALID = 0, + EFUSE_STATE_READY = 1, + EFUSE_STATE_BUSY = 2 +} EFUSE_State; + +EFUSE_State gEfuseState = EFUSE_STATE_INVALID; + +__STATIC_INLINE void EFUSE_EnableClkGate(void) +{ + HAL_SET_BIT(EFUSE->CTRL, EFUSE_CLK_GATE_EN_BIT); +} + +__STATIC_INLINE void EFUSE_DisableClkGate(void) +{ + HAL_CLR_BIT(EFUSE->CTRL, EFUSE_CLK_GATE_EN_BIT); +} + +__STATIC_INLINE void EFUSE_SetIndex(uint32_t index) +{ + HAL_MODIFY_REG(EFUSE->CTRL, EFUSE_INDEX_MASK, + HAL_GET_BIT(index << EFUSE_INDEX_SHIFT, EFUSE_INDEX_MASK)); +} + +__STATIC_INLINE uint32_t EFUSE_GetHwReadStatus(void) +{ + return !!HAL_GET_BIT(EFUSE->CTRL, EFUSE_HW_READ_STATUS_BIT); +} + +__STATIC_INLINE void EFUSE_StartRead(void) +{ + HAL_MODIFY_REG(EFUSE->CTRL, EFUSE_OPERA_LOCK_MASK, + (EFUSE_OPERA_UNLOCK_VAL << EFUSE_OPERA_LOCK_SHIFT) | EFUSE_SW_READ_START_BIT); +} + +__STATIC_INLINE uint32_t EFUSE_GetSwReadStatus(void) +{ + return !!HAL_GET_BIT(EFUSE->CTRL, EFUSE_SW_READ_START_BIT); +} + +__STATIC_INLINE void EFUSE_StartProgram(void) +{ + HAL_MODIFY_REG(EFUSE->CTRL, EFUSE_OPERA_LOCK_MASK, + (EFUSE_OPERA_UNLOCK_VAL << EFUSE_OPERA_LOCK_SHIFT) | EFUSE_SW_PROG_START_BIT); +} + +__STATIC_INLINE uint32_t EFUSE_GetSwProgStatus(void) +{ + return !!HAL_GET_BIT(EFUSE->CTRL, EFUSE_SW_PROG_START_BIT); +} + +__STATIC_INLINE void EFUSE_ClrCtrlReg(void) +{ + HAL_CLR_BIT(EFUSE->CTRL, EFUSE_INDEX_MASK + | EFUSE_OPERA_LOCK_MASK + | EFUSE_SW_READ_START_BIT + | EFUSE_SW_PROG_START_BIT); +} + +__STATIC_INLINE void EFUSE_SetProgValue(uint32_t value) +{ + EFUSE->PROGRAM_VALUE = value; +} + +__STATIC_INLINE uint32_t EFUSE_GetReadValue(void) +{ + return EFUSE->READ_VALUE; +} + +__STATIC_INLINE void EFUSE_SetTimingParam(EFUSE_TimingParam timingParam) +{ + EFUSE->TIMING_CTRL = timingParam; +} + +static HAL_Status EFUSE_Init(void) +{ + uint32_t clk; + EFUSE_TimingParam timingParam; + + clk = HAL_GetHFClock(); + + if (clk == HOSC_CLOCK_24M) { + timingParam = EFUSE_TIMING_PARAM_24M; + } else if (clk == HOSC_CLOCK_26M) { + timingParam = EFUSE_TIMING_PARAM_26M; + } else { + HAL_ERR("unsupport HOSC %u\n", clk); + return HAL_ERROR; + } + + EFUSE_SetTimingParam(timingParam); + + return HAL_OK; +} + +static void EFUSE_ReadData(uint8_t index, uint32_t *pData) +{ + EFUSE_EnableClkGate(); + EFUSE_SetIndex(index << 2); + EFUSE_StartRead(); + + while (EFUSE_GetSwReadStatus()) + ; + + while (EFUSE_GetHwReadStatus()) + ; + + *pData = EFUSE_GetReadValue(); + EFUSE_ClrCtrlReg(); + EFUSE_DisableClkGate(); +} + +/** + * @brief Read an amount of data from EFUSE + * @param[in] start_bit The first bit to be read on EFUSE + * @param[in] bit_num Number of bits to be read + * @param[in] data Pointer to the data buffer + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_EFUSE_Read(uint32_t start_bit, uint32_t bit_num, uint8_t *data) +{ + if ((data == NULL) + || (start_bit >= HAL_EFUSE_BIT_NUM) + || (bit_num == 0) + || (bit_num > HAL_EFUSE_BIT_NUM) + || (start_bit + bit_num > HAL_EFUSE_BIT_NUM)) { + HAL_ERR("start bit %d, bit num %d, data %p\n", start_bit, bit_num, data); + return HAL_ERROR; + } + + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + if (gEfuseState == EFUSE_STATE_INVALID) { + gEfuseState = EFUSE_STATE_BUSY; + HAL_ExitCriticalSection(flags); + if (EFUSE_Init() != HAL_OK) { + flags = HAL_EnterCriticalSection(); + gEfuseState = EFUSE_STATE_INVALID; + HAL_ExitCriticalSection(flags); + return HAL_ERROR; + } + } else if (gEfuseState == EFUSE_STATE_READY) { + gEfuseState = EFUSE_STATE_BUSY; + HAL_ExitCriticalSection(flags); + } else { + HAL_ExitCriticalSection(flags); + HAL_WRN("EFUSE state %d\n", gEfuseState); + return HAL_BUSY; + } + + uint8_t *p_data = data; + uint32_t bit_shift = start_bit & (32 - 1); + uint32_t word_idx = start_bit >> 5; + + uint64_t buf = 0; + uint32_t *efuse_word = (uint32_t *)&buf; + uint32_t byte_num = (bit_num + 7) >> 3; + uint32_t byte_cnt = byte_num; + uint32_t bit_cnt; + uint32_t copy_size; + + HAL_Memset(data, 0, byte_num); + + while (byte_cnt > 0) { + EFUSE_ReadData((uint8_t)word_idx, &efuse_word[0]); + + if (word_idx + 1 < 64) { + EFUSE_ReadData((uint8_t)word_idx + 1, &efuse_word[1]); + } else { + efuse_word[1] = 0; + } + buf = buf >> bit_shift; + + copy_size = (byte_cnt > sizeof(efuse_word[0])) ? sizeof(efuse_word[0]) : byte_cnt; + HAL_Memcpy(p_data, &efuse_word[0], copy_size); + byte_cnt -= copy_size; + p_data += copy_size; + word_idx++; + } + + bit_cnt = bit_num & (8 - 1); + if (bit_cnt > 0) + data[byte_num - 1] &= ((1 << bit_cnt) - 1); + + flags = HAL_EnterCriticalSection(); + gEfuseState = EFUSE_STATE_READY; + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + +static void EFUSE_WriteData(uint8_t index, uint32_t data) +{ + EFUSE_EnableClkGate(); + EFUSE_SetIndex(index << 2); + EFUSE_SetProgValue(data); + EFUSE_StartProgram(); + + while (EFUSE_GetSwProgStatus()) + ; + + EFUSE_ClrCtrlReg(); + EFUSE_DisableClkGate(); +} + +/** + * @brief Write an amount of data to EFUSE + * @param[in] start_bit The first bit to be written on EFUSE + * @param[in] bit_num Number of bits to be written + * @param[in] data Pointer to the data buffer + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_EFUSE_Write(uint32_t start_bit, uint32_t bit_num, uint8_t *data) +{ + if ((data == NULL) + || (start_bit >= HAL_EFUSE_BIT_NUM) + || (bit_num == 0) + || (bit_num > HAL_EFUSE_BIT_NUM) + || (start_bit + bit_num > HAL_EFUSE_BIT_NUM)) { + HAL_ERR("start bit %d, bit num %d, data %p\n", start_bit, bit_num, data); + return HAL_ERROR; + } + + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + if (gEfuseState == EFUSE_STATE_INVALID) { + gEfuseState = EFUSE_STATE_BUSY; + HAL_ExitCriticalSection(flags); + if (EFUSE_Init() != HAL_OK) { + flags = HAL_EnterCriticalSection(); + gEfuseState = EFUSE_STATE_INVALID; + HAL_ExitCriticalSection(flags); + return HAL_ERROR; + } + } else if (gEfuseState == EFUSE_STATE_READY) { + gEfuseState = EFUSE_STATE_BUSY; + HAL_ExitCriticalSection(flags); + } else { + HAL_ExitCriticalSection(flags); + HAL_WRN("EFUSE state %d\n", gEfuseState); + return HAL_BUSY; + } + + uint8_t *p_data = data; + uint32_t bit_shift = start_bit & (32 - 1); + uint32_t word_idx = start_bit >> 5; + + uint64_t buf = 0; + uint32_t *efuse_word = (uint32_t *)&buf; + uint32_t bit_cnt = bit_num; + + HAL_Memcpy(&efuse_word[1], p_data, sizeof(efuse_word[1])); + if (bit_cnt < 32) + efuse_word[1] &= (1 << bit_cnt) - 1; + efuse_word[1] = efuse_word[1] << bit_shift; + + EFUSE_WriteData((uint8_t)word_idx, efuse_word[1]); + + word_idx++; + bit_cnt -= (bit_cnt <= 32 - bit_shift) ? bit_cnt : 32 - bit_shift; + + while (bit_cnt > 0) { + HAL_Memcpy(&buf, p_data, sizeof(buf)); + buf = buf << bit_shift; + if (bit_cnt < 32) + efuse_word[1] &= (1 << bit_cnt) - 1; + + EFUSE_WriteData((uint8_t)word_idx, efuse_word[1]); + + word_idx++; + p_data += 4; + bit_cnt -= (bit_cnt <= 32) ? bit_cnt : 32; + } + + flags = HAL_EnterCriticalSection(); + gEfuseState = EFUSE_STATE_READY; + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + diff --git a/platform/mcu/xr871/src/driver/chip/hal_flash.c b/platform/mcu/xr871/src/driver/chip/hal_flash.c new file mode 100644 index 0000000000..2143da61c5 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_flash.c @@ -0,0 +1,1158 @@ +/** + * @file hal_flash.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "sys/list.h" +#include "sys/param.h" +#include "sys/defs.h" + +#include "driver/chip/hal_spi.h" +#include "driver/chip/hal_flashctrl.h" +#include "driver/chip/hal_flash.h" +#include "hal_base.h" + +#include "pm/pm.h" + + +#define FD_DEBUG(msg, arg...) XR_DEBUG((DBG_OFF | XR_LEVEL_ALL), NOEXPAND, "[Flash Driver debug] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) +#define FD_ERROR(msg, arg...) XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash Driver error] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) +#define FD_INFO(msg, arg...) XR_DEBUG((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[Flash Driver info] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) + +#define FLASH_DMA_TRANSFER_MIN_SIZE (64) + +static FlashBoardCfg *getFlashBoardCfg(int minor); +#ifdef CONFIG_PM +static struct soc_device_driver flash_drv; +#endif + + +/* + SpiFlashDriver +*/ +typedef struct SpiFlashDriver +{ + FlashDrvierBase base; + SPI_Port port; + SPI_CS cs; + SPI_Config config; +} SpiFlashDriver; + +void HAL_XIP_Delay(unsigned int us); + + +HAL_Status spiFlashOpen(FlashDrvierBase *base) +{ + /*TODO: it should be suspend schedule and deinit xip when spi is using spi0 with xiping*/ + + return HAL_OK; +} + +HAL_Status spiFlashClose(FlashDrvierBase *base) +{ + /*TODO: it should be resume schedule and init xip when spi is using spi0 with xiping*/ + + return HAL_OK; +} + +#define FD_SPI_WRITE(impl, ins, line_max) \ + do { \ + ret = insToSpi(impl, ins, line_max, HAL_SPI_Transmit); \ + if (ret != HAL_OK) { \ + FD_ERROR("spi instruction param error"); \ + goto failed; \ + } \ + } while (0) + +#define FD_SPI_READ(impl, ins, line_max) \ + do { \ + ret = insToSpi(impl, ins, line_max, HAL_SPI_Receive); \ + if (ret != HAL_OK) { \ + FD_ERROR("spi instruction param error"); \ + goto failed; \ + } \ + } while (0) + +static HAL_Status insToSpi(SpiFlashDriver *impl, InstructionField *ins, uint32_t line_max, HAL_Status (*fun)(SPI_Port, uint8_t *, uint32_t)) +{ + uint8_t *p; + + if (ins) + { + if (ins->line > line_max) + return HAL_INVALID; + if (!ins->pdata && ins->len > 4) + return HAL_ERROR; + + p = ins->pdata ? ins->pdata : (uint8_t *)&ins->data; + return fun(impl->port, p, ins->len); + } + else + return HAL_OK; +} + +static HAL_Status spiFlashWrite(FlashDrvierBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + SpiFlashDriver *impl = __containerof(base, SpiFlashDriver, base); + InstructionField naddr = {0}; + HAL_Status ret; + + if (data && data->len >= (base->sizeToDma - 1)) + impl->config.opMode = SPI_OPERATION_MODE_DMA; + else + impl->config.opMode = SPI_OPERATION_MODE_POLL; + + ret = HAL_SPI_Open(impl->port, impl->cs, &impl->config, 5000); + if (ret != HAL_OK) { + FD_ERROR("spi open failed"); + return ret; + } + + HAL_SPI_CS(impl->port, 1); + FD_SPI_WRITE(impl, cmd, 1); + if (addr) + { + naddr.len = addr->len; + naddr.line = addr->line; + if (!addr->pdata) + addr->pdata = (uint8_t *)&addr->data; + naddr.data = ((addr->pdata)[2]) | ((addr->pdata)[1] << 8) | ((addr->pdata)[0] << 16); + FD_DEBUG("naddr.data: 0x%x", naddr.data); + FD_SPI_WRITE(impl, &naddr, 1); + } + FD_SPI_WRITE(impl, dummy, 1); + FD_SPI_WRITE(impl, data, 1); + HAL_SPI_CS(impl->port, 0); + +failed: + HAL_SPI_Close(impl->port); + return ret; +} + +static HAL_Status spiFlashRead(FlashDrvierBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + SpiFlashDriver *impl = __containerof(base, SpiFlashDriver, base); + InstructionField naddr = {0}; + HAL_Status ret; + + if (data && data->len >= (base->sizeToDma - 1)) + impl->config.opMode = SPI_OPERATION_MODE_DMA; + else + impl->config.opMode = SPI_OPERATION_MODE_POLL; + + ret = HAL_SPI_Open(impl->port, impl->cs, &impl->config, 5000); + if (ret != HAL_OK) { + FD_ERROR("spi open failed"); + return ret; + } + + if (data && data->line == 2) + HAL_SPI_Config(impl->port, SPI_ATTRIBUTION_IO_MODE, SPI_IO_MODE_DUAL_RX); + else + HAL_SPI_Config(impl->port, SPI_ATTRIBUTION_IO_MODE, SPI_IO_MODE_NORMAL); + + HAL_SPI_CS(impl->port, 1); + FD_SPI_WRITE(impl, cmd, 1); + if (addr) + { + naddr.len = addr->len; + naddr.line = addr->line; + if (!addr->pdata) + addr->pdata = (uint8_t *)&addr->data; + naddr.data = ((addr->pdata)[2]) | ((addr->pdata)[1] << 8) | ((addr->pdata)[0] << 16); + FD_DEBUG("naddr.data: 0x%x", naddr.data); + FD_SPI_WRITE(impl, &naddr, 1); + } + FD_SPI_WRITE(impl, dummy, 1); + FD_SPI_READ(impl, data, 2); + HAL_SPI_CS(impl->port, 0); + +failed: + HAL_SPI_Close(impl->port); + return ret; +} + +static HAL_Status spiFlashSetFreq(FlashDrvierBase *base, uint32_t freq) +{ + /* TODO: tbc... */ + return HAL_INVALID; +} + +void spiFlashMsleep(FlashDrvierBase *base, uint32_t ms) +{ + HAL_MSleep(ms); +} + +void spiFlashMsleepReuseFlashc(FlashDrvierBase *base, uint32_t ms) +{ + HAL_XIP_Delay(ms * 1000); +} + +static void spiFlashDestroy(FlashDrvierBase *base) +{ + SpiFlashDriver *impl = __containerof(base, SpiFlashDriver, base); + HAL_Free(impl); +} + +FlashDrvierBase *spiDriverCreate(int dev, FlashBoardCfg *bcfg) +{ + /*TODO: check read mode*/ + + SpiFlashDriver *impl = HAL_Malloc(sizeof(SpiFlashDriver)); + HAL_Memset(impl, 0, sizeof(*impl)); + + impl->port = bcfg->spi.port; + impl->cs = bcfg->spi.cs; + impl->config.sclk = bcfg->spi.clk; + impl->config.firstBit = SPI_TCTRL_FBS_MSB; + impl->config.mode = SPI_CTRL_MODE_MASTER; + impl->config.opMode = SPI_OPERATION_MODE_DMA; /*spi0 must be poll on xip;*/ + impl->config.sclkMode = SPI_SCLK_Mode0; + + FD_DEBUG("bcfg->type: %d; impl->port: %d; impl->cs: %d; impl->config.sclk: %d;", + bcfg->type, impl->port, impl->cs, impl->config.sclk); + + impl->base.dev = dev; + impl->base.open = spiFlashOpen; + impl->base.close = spiFlashClose; + impl->base.read = spiFlashRead; + impl->base.write = spiFlashWrite; + impl->base.setFreq = spiFlashSetFreq; + impl->base.destroy = spiFlashDestroy; + impl->base.sizeToDma = FLASH_DMA_TRANSFER_MIN_SIZE; + if (bcfg->spi.port == SPI1) + impl->base.msleep = spiFlashMsleep; + else + impl->base.msleep = spiFlashMsleepReuseFlashc; + + return &impl->base; +} + +/* + FlashcFlashDriver +*/ +typedef struct FlashcFlashDriver +{ + FlashDrvierBase base; + +} FlashcFlashDriver; + +/** + * @internal + * @brief Flash driver open. + * @param base: driver. + * @retval HAL_Status: The status of driver + */ +HAL_Status flashcFlashOpen(FlashDrvierBase *base) +{ + FD_DEBUG("open"); + return HAL_Flashc_Open(); +} + +/** + * @internal + * @brief Flash driver close. + * @param base: driver. + * @retval HAL_Status: The status of driver + */ +HAL_Status flashcFlashClose(FlashDrvierBase *base) +{ + HAL_Status ret = HAL_Flashc_Close(); + FD_DEBUG("close"); + return ret; +} + +void insToFcIns(InstructionField *ins, FC_InstructionField *fcins) +{ + if (ins == NULL) + return; + + if (ins->pdata) + fcins->pdata = ins->pdata; + else + fcins->pdata = (uint8_t *)&ins->data; + fcins->len = ins->len; + fcins->line = (FC_CycleBits)((ins->line == 4) ? FC_CYCLEBITS_4 : ins->line); +} + +#define INS_CMD (0) +#define INS_ADDR (1) +#define INS_DUM (2) +#define INS_DATA (3) + +/** + * @internal + * @brief Flash driver write. + * @param base: Driver. + * @param cmd: Instruction command field. + * @param addr: Instruction address field. + * @param dummy: Instruction dummy field. + * @param data: Instruction data field. + * @retval HAL_Status: The status of driver + */ +static HAL_Status flashcFlashWrite(FlashDrvierBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + int dma = 0; + FC_InstructionField tmp[4]; + HAL_Memset(tmp, 0, sizeof(tmp)); + + insToFcIns(cmd, &tmp[INS_CMD]); + insToFcIns(addr, &tmp[INS_ADDR]); + insToFcIns(dummy, &tmp[INS_DUM]); + insToFcIns(data, &tmp[INS_DATA]); + + if (tmp[INS_DATA].len >= (base->sizeToDma - 1) && tmp[INS_DATA].len < 128 * 1024) + dma = 1; + + return HAL_Flashc_Write(&tmp[INS_CMD], &tmp[INS_ADDR], &tmp[INS_DUM], &tmp[INS_DATA], dma); +} + +/** + * @internal + * @brief Flash driver read. + * @param base: Driver. + * @param cmd: Instruction command field. + * @param addr: Instruction address field. + * @param dummy: Instruction dummy field. + * @param data: Instruction data field. + * @retval HAL_Status: The status of driver + */ +static HAL_Status flashcFlashRead(FlashDrvierBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + int dma = 0; + FC_InstructionField tmp[4]; + HAL_Memset(tmp, 0, sizeof(tmp)); + + insToFcIns(cmd, &tmp[INS_CMD]); + insToFcIns(addr, &tmp[INS_ADDR]); + insToFcIns(dummy, &tmp[INS_DUM]); + insToFcIns(data, &tmp[INS_DATA]); + + if (tmp[INS_DATA].len >= (base->sizeToDma - 1) && tmp[INS_DATA].len < 128 * 1024) + dma = 1; + + return HAL_Flashc_Read(&tmp[INS_CMD], &tmp[INS_ADDR], &tmp[INS_DUM], &tmp[INS_DATA], dma); +} + +/** + * @internal + * @brief Flash driver set working frequency. + * @param base: Driver. + * @param freq: Device and driver working frequency. + * @retval HAL_Status: The status of driver + */ +static HAL_Status flashcFlashSetFreq(FlashDrvierBase *base, uint32_t freq) +{ + /* TODO: tbc... */ + return HAL_INVALID; +} + +/** + * @internal + * @brief Sleep realization by driver. + * @note For some reason(XIP), system sleep function can't be used in some + * case. So the realiztion of sleep should be performed by driver. + * @param base: Driver. + * @param ms: Sleep or wait sometime in millisecond. + * @retval HAL_Status: The status of driver + */ +void flashcFlashMsleep(FlashDrvierBase *base, uint32_t ms) +{ + HAL_XIP_Delay(ms * 1000); +} + +/** + * @internal + * @brief Destroy flash driver. + * @note This may not be used. + * @param base: Driver. + * @retval HAL_Status: The status of driver + */ +static void flashcFlashDestroy(FlashDrvierBase *base) +{ + FlashcFlashDriver *impl = __containerof(base, FlashcFlashDriver, base); + HAL_Flashc_Deinit(); + HAL_Free(impl); +} + +/** + * @internal + * @brief Create a flash driver. + * @param dev: Flash device number, but not minor number. + * @param bcfg: Config from board config. + * @retval HAL_Status: The status of driver + */ +static FlashDrvierBase *flashcDriverCreate(int dev, FlashBoardCfg *bcfg) +{ + FlashcFlashDriver *impl = HAL_Malloc(sizeof(FlashcFlashDriver)); + if (impl == NULL) + FD_ERROR("malloc failed"); + HAL_Memset(impl, 0, sizeof(*impl)); + + Flashc_Config cfg; + cfg.freq = bcfg->flashc.clk; + HAL_Flashc_Init(&cfg); + + impl->base.dev = dev; + impl->base.open = flashcFlashOpen; + impl->base.close = flashcFlashClose; + impl->base.read = flashcFlashRead; + impl->base.write = flashcFlashWrite; + impl->base.setFreq = flashcFlashSetFreq; + impl->base.msleep = flashcFlashMsleep; + impl->base.destroy = flashcFlashDestroy; + impl->base.sizeToDma = FLASH_DMA_TRANSFER_MIN_SIZE; + + return &impl->base; +} + + +/** + * @internal + * @brief Create a flash driver according board config. + * @param minor: flash number = flash minor number, from board config. + * @retval HAL_Status: The status of driver + */ +static FlashDrvierBase *flashDriverCreate(int minor) +{ + FlashDrvierBase *base = NULL; + FlashBoardCfg *cfg; + int dev = HAL_MKDEV(HAL_DEV_MAJOR_FLASH, minor); + + HAL_BoardIoctl(HAL_BIR_GET_CFG, dev, (uint32_t)&cfg); + if (cfg == NULL) + FD_ERROR("flash config error"); + +#if FLASH_FLASHC_ENABLE + if (cfg->type == FLASH_DRV_FLASHC) + base = flashcDriverCreate(dev, cfg); +#endif +#if FLASH_SPI_ENABLE + if (cfg->type == FLASH_DRV_SPI) + base = spiDriverCreate(dev, cfg); +#endif + if (base == NULL) + FD_ERROR("No Flash driver support"); + + if (base == NULL) + FD_ERROR("flash driver can't be create"); + + /*manage driver gpio. tbc...*/ + + return base; +} + +/** + * @internal + * @brief Destroy a flash driver. + * @param base: Driver. + * @retval HAL_Status: The status of driver + */ +static int flashDriverDestory(FlashDrvierBase *base) +{ + if (base == NULL) + return -1; + + base->destroy(base); + return 0; +} + + +/* + FlashBoard +*/ +static FlashBoardCfg *getFlashBoardCfg(int minor) +{ + FlashBoardCfg *cfg; + int dev = HAL_MKDEV(HAL_DEV_MAJOR_FLASH, minor); + + HAL_BoardIoctl(HAL_BIR_GET_CFG, dev, (uint32_t)&cfg); + if (cfg == NULL) + FD_ERROR("flash config error"); + + return cfg; +} + + +/* + Flash +*/ +struct FlashDev +{ + struct list_head node; + HAL_Mutex lock; + uint32_t usercnt; /*not thread safe*/ + + uint32_t flash; + FlashDrvierBase *drv; + FlashChipBase *chip; + FlashReadMode rmode; + FlashPageProgramMode wmode; + +#ifdef CONFIG_PM + struct soc_device *pm; +#endif +}; + +struct list_head flashNodeHead = { + .next = &flashNodeHead, + .prev = &flashNodeHead +}; + +FlashChipBase *getFlashChip(FlashDev *dev) +{ + return dev->chip; +} + +FlashReadMode getFlashMode(FlashDev *dev) +{ + return dev->rmode; +} + +FlashDev *getFlashDev(uint32_t flash) +{ + FlashDev *dev = NULL; + FlashDev *itor = NULL; + + list_for_each_entry(itor, &flashNodeHead, node) + { + if (itor->flash == flash) { + dev = itor; + break; + } + } + + if (dev == NULL) + FD_ERROR("no this flash or not inited"); + + return dev; +} + +static int deleteFlashDev(FlashDev *dev) +{ + if (dev == NULL) { + FD_ERROR("NULL flash device"); + return -1; + } + + list_del(&dev->node); + + return 0; +} + +static int addFlashDev(FlashDev *dev) +{ + if (dev == NULL) { + FD_ERROR("NULL flash device"); + return -1; + } + + list_add_tail(&dev->node, &flashNodeHead); + + return 0; +} + +/** + * @brief Initializes flash Device. + * @note The flash device configuration is in the board_config g_flash_cfg. + * Device number is the g_flash_cfg vector sequency number. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Init(uint32_t flash) +{ + HAL_Status ret; + FlashDrvierBase *drv = NULL; + FlashChipBase *chip = NULL; + FlashDev *dev = NULL; + FlashBoardCfg *cfg = NULL; + + cfg = getFlashBoardCfg(flash); + if (cfg == NULL) + { + FD_ERROR("getFlashBoardCfg failed"); + goto failed; + } + + drv = flashDriverCreate(flash); + if (drv == NULL) + { + FD_ERROR("flashDriverCreate failed"); + goto failed; + } + + chip = FlashChipCreate(drv); + if (chip == NULL) + { + FD_ERROR("FlashChipCreate failed"); + goto failed; + } + + dev = HAL_Malloc(sizeof(*dev)); + if (dev == NULL) + { + FD_ERROR("malloc dev failed"); + goto failed; + } + HAL_Memset(dev, 0, sizeof(*dev)); + + /*TODO: get read mode from board, and init*/ + + dev->chip = chip; + dev->drv = drv; + dev->flash = flash; + dev->rmode = cfg->mode; + dev->wmode = FLASH_PAGEPROGRAM; + dev->usercnt = 0; + INIT_LIST_HEAD(&dev->node); + ret = HAL_MutexInit(&dev->lock); + if (ret != HAL_OK) + { + FD_ERROR("mutex init failed: %d", ret); + goto failed; + } + + addFlashDev(dev); + + drv->open(drv); +// chip->setFreq(chip, ); + if (dev->rmode & (FLASH_READ_QUAD_O_MODE | FLASH_READ_QUAD_IO_MODE | FLASH_READ_QPI_MODE)) + { + chip->switchReadMode(chip, dev->rmode); + if (dev->rmode & FLASH_READ_QPI_MODE) + chip->enableQPIMode(chip); + } + drv->close(drv); + + FD_INFO("mode: 0x%x, freq: %dHz, drv: %d", cfg->mode, cfg->flashc.clk, cfg->type); + +#ifdef CONFIG_PM + struct soc_device *flash_pm = HAL_Malloc(sizeof(*flash_pm)); + HAL_Memset(flash_pm, 0, sizeof(*flash_pm)); + flash_pm->name = "Flash"; + flash_pm->driver = &flash_drv; + flash_pm->platform_data = (void *)flash; + dev->pm = flash_pm; + pm_register_ops(flash_pm); +#endif + + return HAL_OK; + +failed: + FD_ERROR("flash init failed"); + + if (drv != NULL) + flashDriverDestory(drv); + if (dev != NULL) + HAL_Free(dev); + + return HAL_ERROR; +} + +/** + * @brief Deinitializes flash Device. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Deinit(uint32_t flash) +{ + FlashDev *dev = getFlashDev(flash); + FlashDrvierBase *drv = dev->drv; + FlashChipBase *chip = dev->chip; + + /*not thread safe*/ + if (dev->usercnt != 0) + return HAL_TIMEOUT; + +#ifdef CONFIG_PM + pm_unregister_ops(dev->pm); +#endif + + drv->open(drv); + chip->reset(chip); + drv->close(drv); + + deleteFlashDev(dev); + HAL_MutexDeinit(&dev->lock); + if (dev->drv != NULL) + flashDriverDestory(dev->drv); + if (dev != NULL) + HAL_Free(dev); + + return HAL_OK; +} + +/** + * @brief Open flash Device. + * @note Opened a flash device, other user can't open again, so please + * close it while don't need the flash device. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number. + * @param timeout_ms: timeout in millisecond. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Open(uint32_t flash, uint32_t timeout_ms) +{ + FlashDev *dev = getFlashDev(flash); + HAL_Status ret = HAL_ERROR; + + ret = HAL_MutexLock(&dev->lock, timeout_ms); + if (ret == HAL_OK) + dev->usercnt++; + + return ret; +} + +/** + * @brief Close flash Device. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Close(uint32_t flash) +{ + FlashDev *dev = getFlashDev(flash); + HAL_Status ret = HAL_ERROR; + + ret = HAL_MutexUnlock(&dev->lock); + if (ret == HAL_OK) + dev->usercnt--; + + return ret; +} + +static HAL_Status HAL_Flash_WaitCompl(FlashDev *dev, int32_t timeout_ms) +{ +#define FLASH_WAIT_TIME (1) + while (dev->chip->isBusy(dev->chip) > 0) + { + dev->drv->msleep(dev->drv, FLASH_WAIT_TIME); + timeout_ms -= FLASH_WAIT_TIME; + if (timeout_ms <= 0) { + FD_ERROR("wait clr busy timeout!"); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Flash ioctl function. + * @note attr : arg + * others are not support for now. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @param attr: ioctl command + * @param arg: ioctl arguement + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Control(uint32_t flash, FlashControlCmd attr, uint32_t arg) +{ + FlashDev *dev = getFlashDev(flash); + + switch (attr) + { + /*TODO: 1.return min erase size */ + case FLASH_GET_MIN_ERASE_SIZE: + *((FlashEraseMode *)arg) = dev->chip->minEraseSize(dev->chip); + break; + /*TODO: tbc...*/ + default: + return HAL_INVALID; + } + + return HAL_OK; +} + +/** + * @brief Write flash Device memory, no need to erase first and other memory + * will not be change. Only can be used in the flash supported 4k erase. + * @note Only the flash supported 4k erase!! FDCM module is much fast than + * this function. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @param addr: the address of memory. + * @param data: the data needed to write to flash device. + * @param size: the data size needed to write. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Overwrite(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size) +{ + FlashDev *dev = getFlashDev(flash); + HAL_Status ret = HAL_ERROR; + uint8_t *buf = NULL; + uint8_t *ptr = data; + uint32_t paddr = addr; + int32_t left = (int32_t)size; + uint32_t pp_size; + uint32_t saddr; + + FD_DEBUG("dev->chip->mEraseSizeSupport 0x%x", dev->chip->mEraseSizeSupport); + if (!(dev->chip->mEraseSizeSupport & FLASH_ERASE_4KB)) + return HAL_INVALID; + + buf = HAL_Malloc(FLASH_ERASE_4KB); + if (buf == NULL) + goto out; + + while (left > 0) + { + HAL_Flash_MemoryOf(flash, FLASH_ERASE_4KB, paddr, &saddr); + HAL_Flash_Read(flash, saddr, buf, FLASH_ERASE_4KB); + ret = HAL_Flash_Erase(flash, FLASH_ERASE_4KB, saddr, 1); + if (ret != HAL_OK) + return ret; + + pp_size = MIN(left, FLASH_ERASE_4KB - (paddr - saddr)); + HAL_Memcpy(buf + (paddr - saddr), ptr, pp_size); + + ret = HAL_Flash_Write(flash, saddr, buf, FLASH_ERASE_4KB); + if (ret != HAL_OK) + goto out; + + ptr += pp_size; + paddr += pp_size; + left -= pp_size; + } + +out: + if (buf != NULL) + HAL_Free(buf); + + return ret; +} + +/** + * @brief Write flash Device memory, if this memory has been written before, + * the memory must be erase first by user. HAL_Flash_Check can check + * this memory whether is writable. + * @note If write a written memory, the memory data will a be error data. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @param addr: the address of memory. + * @param data: the data needed to write to flash device. + * @param size: the data size needed to write. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Write(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size) +{ + FlashDev *dev = getFlashDev(flash); + HAL_Status ret = HAL_ERROR; + uint32_t address = addr; + uint32_t left = size; + uint8_t *ptr = data; + uint32_t pp_size; + + FD_DEBUG("%d: w%d, a: 0x%x", flash, size, addr); + + if (dev == NULL) + return HAL_INVALID; + if (dev->chip->pageProgram == NULL) + return HAL_INVALID; + + while (left > 0) + { + pp_size = MIN(left, dev->chip->mPageSize - (address % dev->chip->mPageSize)); + + dev->drv->open(dev->drv); + + dev->chip->writeEnable(dev->chip); + FD_DEBUG("WE"); + ret = dev->chip->pageProgram(dev->chip, dev->wmode, address, ptr, pp_size); + FD_DEBUG("PP"); + dev->chip->writeDisable(dev->chip); + FD_DEBUG("WD"); + + if (ret < 0) + break; + + ret = HAL_Flash_WaitCompl(dev, 5000); + + dev->drv->close(dev->drv); + + if (ret < 0) + FD_ERROR("write failed: %d", ret); + + address += pp_size; + ptr += pp_size; + left -= pp_size; + } + + if (ret != 0) + FD_ERROR("write failed"); + + return ret; +} + +/** + * @brief Read flash device memory. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number + * @param addr: the address of memory. + * @param data: the data needed to write to flash device. + * @param size: the data size needed to write. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Read(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size) +{ + FlashDev *dev = getFlashDev(flash); + HAL_Status ret; + + FD_DEBUG("%d: r%d, a: 0x%x", flash, size, addr); + + if (dev == NULL) + return HAL_INVALID; + if (dev->chip->read == NULL) + return HAL_INVALID; + + dev->drv->open(dev->drv); + ret = dev->chip->read(dev->chip, dev->rmode, addr, data, size); + dev->drv->close(dev->drv); + + if (ret != 0) + FD_ERROR("read failed"); + + return ret; +} + +/** + * @brief Erase flash device memory. Flash can only erase sector or block or + * chip. + * @note Some flash is not support some erase mode, for example: FLASH M25P64 + * is only support FLASH_ERASE_CHIP and FLASH_ERASE_64KB. + * The erase address must be aligned to erase mode size, for example: + * the address should be n * 0x1000 in the erase 4kb mode, this address + * can be calculated in HAL_Flash_MemoryOf. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number. + * @param blk_size: + * @arg FLASH_ERASE_4KB: 4kbyte erase mode. + * @arg FLASH_ERASE_32KB: 32kbtye erase mode. + * @arg FLASH_ERASE_64KB: 64kbtye erase mode. + * @arg FLASH_ERASE_CHIP: erase whole flash chip. + * @param addr: the address of memory. + * @param blk_cnt: erase number of block or sector, no use in FLASH_ERASE_CHIP. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_Erase(uint32_t flash, FlashEraseMode blk_size, uint32_t addr, uint32_t blk_cnt) +{ + FlashDev *dev = getFlashDev(flash); + HAL_Status ret = HAL_ERROR; + uint32_t esize = blk_size; + uint32_t eaddr = addr; + + FD_DEBUG("%d: e%d * %d, a: 0x%x", flash, (uint32_t)blk_size, blk_cnt, addr); + + if ((addr + blk_size * blk_cnt) > dev->chip->mSize) { + FD_ERROR("erase memory is over flash memory\n"); + return HAL_INVALID; + } + if ((blk_size == FLASH_ERASE_CHIP) && (blk_cnt != 1)) + FD_DEBUG("chip erase will be execute more than 1"); + if (addr % blk_size) + FD_DEBUG("chip erase on a incompatible address"); + + while (blk_cnt-- > 0) + { + dev->drv->open(dev->drv); + + dev->chip->writeEnable(dev->chip); + ret = dev->chip->erase(dev->chip, blk_size, eaddr); + dev->chip->writeDisable(dev->chip); + + if (ret < 0) + FD_ERROR("erase failed: %d", ret); + + ret = HAL_Flash_WaitCompl(dev, 5000); + + dev->drv->close(dev->drv); + + if (ret < 0) + break; + eaddr += esize; + } + + return ret; +} + +/** + * @brief Calculate which block the flash address belong to, and output a + * block address to user. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number. + * @param blk_size: + * @arg FLASH_ERASE_4KB: 4kbyte erase mode. + * @arg FLASH_ERASE_32KB: 32kbtye erase mode. + * @arg FLASH_ERASE_64KB: 64kbtye erase mode. + * @arg FLASH_ERASE_CHIP: erase whole flash chip. + * @param addr: the address of memory. + * @param start: the address of the block contained the addr. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Flash_MemoryOf(uint32_t flash, FlashEraseMode size, uint32_t addr, uint32_t *start) +{ + FlashDev *dev = getFlashDev(flash); + uint32_t page_mask; + HAL_Status ret = HAL_OK; + + if (!(size & dev->chip->mEraseSizeSupport)) + return HAL_INVALID; + + page_mask = ~((uint32_t)(size - 1)); + *start = addr & page_mask; + + return ret; +} + +/** + * @brief Check the flash memory whether . + * @note The flash device configuration is in the board_config g_flash_cfg. + * Device number is the g_flash_cfg vector sequency number. + * @param flash: the flash device number, same as the g_flash_cfg vector + * sequency number. + * @param addr: the address of memory. + * @param data: the data needed to write to flash device. + * @param size: the data size needed to write. + * @retval int: 0: same as data, no need to write or erase; + * 1: write directly, no need to erase; + * 2: need to erase first; + */ +int HAL_Flash_Check(uint32_t flash, uint32_t addr, uint8_t *data, uint32_t size) +{ +#define FLASH_CHECK_BUF_SIZE (128) + + uint8_t *pdata = data; + uint8_t *pbuf; + uint8_t *buf; + uint8_t src; + uint8_t dst; + uint32_t left = size; + uint32_t paddr = addr; + int32_t ret = 0; + + buf = HAL_Malloc(FLASH_CHECK_BUF_SIZE); + pbuf = buf + FLASH_CHECK_BUF_SIZE; + if (buf == NULL) + return -1; + + while (left > 0) + { + if ((pbuf - buf) == FLASH_CHECK_BUF_SIZE) { + HAL_Flash_Read(flash, paddr, buf, FLASH_CHECK_BUF_SIZE); + pbuf = buf; + } + + src = *pbuf++; + dst = *pdata++; + left--; + paddr++; + + dst ^= src; + if (dst == 0) + continue; /* src == dst */ + + ret = 1; /* src != dst */ + if (dst & src) { + ret = 2; /* src has bit '1', need to erase */ + break; + } + } + + if (buf != NULL) + HAL_Free(buf); + + return ret; +} + + +#ifdef CONFIG_PM +//#define FLASH_POWERDOWN (PM_MODE_POWEROFF) + +static int PM_FlashSuspend(struct soc_device *dev, enum suspend_state_t state) +{ + /* + suspend condition: + (1) + (2) + */ + FlashDev *fdev = getFlashDev((uint32_t)dev->platform_data); + + if (fdev->usercnt != 0) + return -1; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + /* flash chip do not power down */ + break; + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + HAL_Flash_Deinit((uint32_t)dev->platform_data); + break; + default: + break; + } + + return 0; +} + +static int PM_FlashResume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + break; + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + HAL_Flash_Init((uint32_t)dev->platform_data); + break; + default: + break; + } + + return 0; +} + +static struct soc_device_driver flash_drv = { + .name = "Flash", + .suspend = PM_FlashSuspend, + .resume = PM_FlashResume, +}; +#endif + + diff --git a/platform/mcu/xr871/src/driver/chip/hal_flashcache.c b/platform/mcu/xr871/src/driver/chip/hal_flashcache.c new file mode 100644 index 0000000000..a00b2f8cae --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_flashcache.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "hal_base.h" +#include "driver/chip/hal_flashcache.h" + +#include "sys/xr_debug.h" + +#define FC_DEBUG(msg, arg...) XR_DEBUG((DBG_OFF | XR_LEVEL_ALL), NOEXPAND, "[FC Debug] " msg, ##arg) + +#define FC_REG(reg) FC_DEBUG("register " #reg ": 0x%x.\n", reg); + +#define FC_REG_ALL() { \ + FC_DEBUG("flash cache register:\n"); \ + FC_REG(FLASH_CACHE->COM_CTRL); \ + FC_REG(FLASH_CACHE->PREFETCH_CTRL); \ + FC_REG(FLASH_CACHE->PREFETCH_START_ADDR); \ + FC_REG(FLASH_CACHE->IV_PREFETCH_CTRL); \ + FC_REG(FLASH_CACHE->MIN_ADDR); \ + FC_REG(FLASH_CACHE->MAX_ADDR); \ + FC_REG(FLASH_CACHE->READ_BIAS_ADDR); \ + } + + + + + + +HAL_Status Hal_FlashCache_EnablePrefetch(FlashCache_PrefetchConfig *cfg) +{ +/* uint32_t cache_line = (cfg->prefetch_cache_size * 8 + 127) / 128; + if (cache_line >= CACHE_LINE_MAX) + return HAL_INVALID; +*/ + + HAL_MODIFY_REG(FLASH_CACHE->PREFETCH_START_ADDR, + FLASH_CACHE_PREFETCH_START_ADDR_MASK, + cfg->addr_prefetch_start << FLASH_CACHE_PREFETCH_START_ADDR_SHIFT); + HAL_MODIFY_REG(FLASH_CACHE->PREFETCH_CTRL, +// FLASH_CACHE_PREFETCH_CTRL_SIZE_MASK | + FLASH_CACHE_PREFETCH_CTRL_BRANCH_MASK | + FLASH_CACHE_PREFETCH_CTRL_STOP_MASK, +// (cache_line << FLASH_CACHE_PREFETCH_CTRL_SIZE_SHIFT) | + (cfg->prefetch_2nd_branch << FLASH_CACHE_PREFETCH_CTRL_BRANCH_SHIFT) | + (FLASH_CACHE_PREFETCH_ENABLE << FLASH_CACHE_PREFETCH_CTRL_STOP_SHIFT)); + + return HAL_OK; +} + +HAL_Status Hal_FlashCache_DisablePrefetch() +{ + HAL_MODIFY_REG(FLASH_CACHE->PREFETCH_CTRL, + FLASH_CACHE_PREFETCH_CTRL_STOP_MASK, + (FLASH_CACHE_PREFETCH_DISABLE << FLASH_CACHE_PREFETCH_CTRL_STOP_SHIFT)); + return HAL_OK; +} + +/* +HAL_Status Hal_FlashCache_PrefetchInt(FlashCache_PrefetchIntConfig * cfg) +{ + uint32_t cnt = 0; + + + + HAL_MODIFY_REG(FLASH_CACHE->IV_PREFETCH_CTRL, + FLASH_CACHE_IV_PREFETCH_CTRL_IV_NUM_MASK, + cnt << FLASH_CACHE_IV_PREFETCH_CTRL_IV_NUM_SHIFT); + + if (cnt != 0) + HAL_SET_BIT(FLASH_CACHE->IV_PREFETCH_CTRL, + FLASH_CACHE_IV_PREFETCH_CTRL_RELEASE_MASK | + FLASH_CACHE_IV_PREFETCH_CTRL_ENABLE_MASK); + else + HAL_CLR_BIT(FLASH_CACHE->IV_PREFETCH_CTRL, + FLASH_CACHE_IV_PREFETCH_CTRL_RELEASE_MASK | + FLASH_CACHE_IV_PREFETCH_CTRL_ENABLE_MASK); +} +*/ + + +HAL_Status Hal_FlashCache_Init(FlashCache_Config *cfg) +{ +// uint32_t cache_line = (cfg->cache_size * 8 + 127) / 128; +// uint32_t cache_line = (CACHE_SIZE * 8 + 127) / 128; + + /* check param */ + if (/*(cache_line > 0x1FF) || */(cfg->addr_bias & (~FLASH_CACHE_READ_BIAS_ADDR_MASK))) { + + return HAL_INVALID; + } + + /* CCMU Enable */ + +// HAL_MODIFY_REG(FLASH_CACHE, FLASH_CACHE_COM_CTRL_SIZE_MASK, cache_line << FLASH_CACHE_COM_CTRL_SIZE_SHIFT); + HAL_MODIFY_REG(FLASH_CACHE->MIN_ADDR, + FLASH_CACHE_MIN_ADDR_MASK, + CACHE_START_ADDR << FLASH_CACHE_MIN_ADDR_SHIFT); + HAL_MODIFY_REG(FLASH_CACHE->MAX_ADDR, + FLASH_CACHE_MAX_ADDR_MASK, + CACHE_END_ADDR << FLASH_CACHE_MAX_ADDR_SHIFT); + HAL_MODIFY_REG(FLASH_CACHE->READ_BIAS_ADDR, + FLASH_CACHE_READ_BIAS_ADDR_MASK, + cfg->addr_bias << FLASH_CACHE_READ_BIAS_ADDR_SHIFT); + + FC_REG_ALL(); + return HAL_OK; +} + +HAL_Status Hal_FlashCache_Deinit() +{ + return HAL_OK; +} + + diff --git a/platform/mcu/xr871/src/driver/chip/hal_flashctrl.c b/platform/mcu/xr871/src/driver/chip/hal_flashctrl.c new file mode 100644 index 0000000000..ef2b965939 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_flashctrl.c @@ -0,0 +1,1242 @@ +/** + * @file hal_flashctrl.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "hal_base.h" +#include "driver/chip/hal_flashctrl.h" +#include "driver/chip/hal_flashcache.h" +#include "driver/chip/hal_dma.h" + +#include "pm/pm.h" + +#include "sys/xr_debug.h" + +#define FC_DEBUG_ON (DBG_OFF) + +#define FC_DEBUG(msg, arg...) XR_DEBUG((FC_DEBUG_ON | XR_LEVEL_ALL), NOEXPAND, "[FC Debug] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) + +#define FC_ERROR(msg, arg...) XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[FC error] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) + +#define FC_REG(reg) FC_DEBUG("register " #reg " (addr: 0x%x): 0x%x.", (uint32_t)&(reg), reg); + +#define FC_REG_ALL() \ + { \ + FC_DEBUG("flash controller register:"); \ + FC_REG(FLASH_CTRL->COMMON_CFG); \ + FC_REG(FLASH_CTRL->I_CMD_CFG); \ + FC_REG(FLASH_CTRL->I_DUMMY_H); \ + FC_REG(FLASH_CTRL->I_DUMMY_L); \ + FC_REG(FLASH_CTRL->I_CS_WAIT); \ + FC_REG(FLASH_CTRL->I_IO_WAIT); \ + FC_REG(FLASH_CTRL->RESERVE0[0]); \ + FC_REG(FLASH_CTRL->FLASH_COMMON_CFG); \ + FC_REG(FLASH_CTRL->XIP_EXEC); \ + FC_REG(FLASH_CTRL->COMMON_ADD_CFG); \ + FC_REG(FLASH_CTRL->S_CMD_CFG); \ + FC_REG(FLASH_CTRL->S_ADDR_CFG); \ + FC_REG(FLASH_CTRL->S_WR_NUM); \ + FC_REG(FLASH_CTRL->S_RD_NUM); \ + FC_REG(FLASH_CTRL->S_DUMMY_H); \ + FC_REG(FLASH_CTRL->S_DUMMY_L); \ + FC_REG(FLASH_CTRL->FIFO_TRIG_LEVEL); \ + FC_REG(FLASH_CTRL->FIFO_STATUS); \ + FC_REG(FLASH_CTRL->S_IO_WAIT); \ + FC_REG(FLASH_CTRL->WRAP_MODE); \ + FC_REG(FLASH_CTRL->START_SEND); \ + FC_REG(FLASH_CTRL->INT_EN); \ + FC_REG(FLASH_CTRL->INT_STA); \ + } + +#if (FC_DEBUG_ON == DBG_ON) +#define FC_WHILE_TIMEOUT(cond, i) \ + i = 0x3FFFFFF; \ + do \ + { \ + if (--i == 0) { \ + FC_REG_ALL(); \ + return HAL_ERROR; \ + } \ + } while(cond) +#else +#define FC_WHILE_TIMEOUT(cond, i) \ + (void)i; \ + while(cond) +#endif + + +void udelay(unsigned int us); + +static HAL_Status HAL_Flashc_DMAWrite(uint8_t *data, uint32_t size); +static HAL_Status HAL_Flashc_PollWrite(uint8_t *data, uint32_t size); +static HAL_Status HAL_Flashc_DMARead(uint8_t *data, uint32_t size); +static HAL_Status HAL_Flashc_PollRead(uint8_t *data, uint32_t size); + +typedef enum { + FC_EN_CONTINUE = 1 << FC_CC_CONT_EN_SHIFT, + FC_EN_PREFETCH = 1 << FC_CC_PREFETCH_EN_SHIFT, + FC_EN_IBUS = 1 << FC_CC_IBUS_EN_SHIFT +} FC_En; + +static inline void FC_Ibus_Enable(uint32_t flash_ctrl_en) +{ + HAL_SET_BIT(FLASH_CTRL->COMMON_CFG, flash_ctrl_en); +} + +static inline void FC_Ibus_Disable(uint32_t flash_ctrl_en) +{ + HAL_CLR_BIT(FLASH_CTRL->COMMON_CFG, flash_ctrl_en); +} + +static inline bool FC_Ibus_IsXIP() +{ + return HAL_GET_BIT(FLASH_CTRL->XIP_EXEC, FC_XE_MASK); +} + +/*typedef enum { + FLASH_CTRL_READMODE_NORMAL_IO = () | () | (), + FLASH_CTRL_READMODE_DUAL_OUTPUT, + FLASH_CTRL_READMODE_DUAL_IO, + FLASH_CTRL_READMODE_QUAD_OUTPUT, + FLASH_CTRL_READMODE_QUAD_IO +} Flash_Ctrl_ReadMode;*/ + +static inline uint32_t FC_DefOutput(uint8_t io_num, FC_Io_Output io) +{ + uint32_t mask, shift; + + if (io_num == 1) { + mask = FC_CC_IO1_MASK; + shift = FC_CC_IO1_SHIFT; + } else if (io_num == 2) { + mask = FC_CC_IO2_MASK; + shift = FC_CC_IO2_SHIFT; + } else if (io_num == 3) { + mask = FC_CC_IO3_MASK; + shift = FC_CC_IO3_SHIFT; + } else + return -1; + + HAL_MODIFY_REG(FLASH_CTRL->COMMON_CFG, mask, io << shift); + + return 0; +} + +static inline void FC_Ibus_ReadConfig(uint8_t read_cmd, + FC_CycleBits cmd, + FC_CycleBits addr, + FC_CycleBits dummy, + FC_CycleBits data, + uint8_t dummy_byte) +{ + uint8_t dummy_width; +/* if (dummy == FC_CYCLEBITS_4) + dummy_width = dummy_cycle * 4; + else if (dummy == FC_CYCLEBITS_2) + dummy_width = dummy_cycle * 2;??????????????????? + else + dummy_width = dummy_cycle * dummy;*/ + + if (dummy_byte > 8) + dummy_byte = 8; + dummy_width = dummy_byte * 8; + + HAL_MODIFY_REG(FLASH_CTRL->I_CMD_CFG, + FC_ICC_CMD_MASK + | FC_ICC_CMD_BIT_MASK + | FC_ICC_ADDR_BIT_MASK + | FC_ICC_DUMMY_BIT_MASK + | FC_ICC_DATA_BIT_MASK + | FC_ICC_DUMMY_WIDTH_MASK, + (read_cmd << FC_ICC_CMD_SHIFT) + | (cmd << FC_ICC_CMD_BIT_SHIFT) + | (addr << FC_ICC_ADDR_BIT_SHIFT) + | (dummy << FC_ICC_DUMMY_BIT_SHIFT) + | (data << FC_ICC_DATA_BIT_SHIFT) + | (dummy_width << FC_ICC_DUMMY_WIDTH_SHIFT)); +} + +static inline void FC_Ibus_DummyData(uint32_t dummyh, uint32_t dummyl) +{ + FLASH_CTRL->I_DUMMY_H = dummyh; + FLASH_CTRL->I_DUMMY_L = dummyl; +} + +static inline void FC_Ibus_TransmitDelay(Flash_Ctrl_DelayCycle *delay) +{ + HAL_MODIFY_REG(FLASH_CTRL->I_CS_WAIT, + FC_ICW_BEGIN_MASK + | FC_ICW_OVER_MASK + | FC_ICW_DESEL_MASK, + (delay->cs_begin << FC_ICW_BEGIN_SHIFT) + | (delay->cs_over << FC_ICW_OVER_SHIFT) + | (delay->cs_deselect << FC_ICW_DESEL_SHIFT)); + HAL_MODIFY_REG(FLASH_CTRL->I_IO_WAIT, + FC_IIW_CMD_MASK + | FC_IIW_ADDR_MASK + | FC_IIW_DUM_MASK, + (delay->cmd_over << FC_IIW_CMD_SHIFT) + | (delay->addr_over << FC_IIW_ADDR_SHIFT) + | (delay->dummy_over << FC_IIW_DUM_SHIFT)); + HAL_MODIFY_REG(FLASH_CTRL->FLASH_COMMON_CFG, + FC_FCC_WAIT_DATA_MASK, + delay->data << FC_FCC_WAIT_DATA_SHIFT); +} + +static inline void FC_SetFlash(FC_Cs cs, FC_TCTRL_Fbs fbs, FC_Sclk_Mode mode) +{ + HAL_MODIFY_REG(FLASH_CTRL->FLASH_COMMON_CFG, + FC_FCC_CS_MASK + | FC_FCC_FBS_MASK + | FC_FCC_CPOL_MASK + | FC_FCC_CPHA_MASK, + cs | fbs | mode); +} + +/*static inline void FC_Ibus_SetCsDelay(uint8_t enable_cyc, uint8_t disable_cyc, uint8_t deselect_cyc) +{ + HAL_MODIFY_REG(FLASH_CTRL->I_CS_WAIT, + FC_ICW_BEGIN_MASK + | FC_ICW_DESEL_MASK + | FC_ICW_OVER_MASK, + (enable_cyc << FC_ICW_BEGIN_SHIFT) + | (disable_cyc << FC_ICW_OVER_SHIFT) + | (deselect_cyc << FC_ICW_DESEL_SHIFT)); +} + +static inline void FC_Sbus_SetCsDelay(uint8_t enable_cyc, uint8_t disable_cyc, uint8_t deselect_cyc) +{ + HAL_MODIFY_REG(FLASH_CTRL->I_CS_WAIT, + FC_ICW_BEGIN_MASK + | FC_ICW_OVER_MASK, + (enable_cyc << FC_ICW_BEGIN_SHIFT) + | (disable_cyc << FC_ICW_OVER_SHIFT)); + + HAL_MODIFY_REG(FLASH_CTRL->COMMON_ADD_CFG, + FC_CAC_CS_DESEL_WAIT_MASK, + deselect_cyc << FC_CAC_CS_DESEL_WAIT_SHIFT); +}*/ + +static inline void FC_Sbus_ResetFIFO(bool tx, bool rx) +{ + HAL_MODIFY_REG(FLASH_CTRL->COMMON_ADD_CFG, + FC_CAC_TX_FIFO_RESET_MASK | FC_CAC_RX_FIFO_RESET_MASK, + (tx << FC_CAC_TX_FIFO_RESET_SHIFT) | (rx << FC_CAC_RX_FIFO_RESET_SHIFT)); +} + +static inline void FC_WrapMode(bool enable) +{ + HAL_MODIFY_REG(FLASH_CTRL->COMMON_ADD_CFG, FC_CAC_WRAP_EN_MASK, enable << FC_CAC_WRAP_EN_SHIFT); +} + +static inline void FC_AddressMode(FC_Addr_Mode mode) +{ + HAL_MODIFY_REG(FLASH_CTRL->COMMON_ADD_CFG, FC_CAC_ADDR_SIZE_MODE_MASK, mode << FC_CAC_ADDR_SIZE_MODE_SHIFT); +} + +static inline void FC_Sbus_CommandConfig(FC_CycleBits cmd, + FC_CycleBits addr, + FC_CycleBits dummy, + FC_CycleBits data, + uint8_t dummy_byte) +{ + uint8_t dummy_width; + + if (dummy_byte > 8) + dummy_byte = 8; + dummy_width = dummy_byte * 8; + + HAL_MODIFY_REG(FLASH_CTRL->S_CMD_CFG, + FC_SCC_CMD_BIT_MASK + | FC_SCC_ADDR_BIT_MASK + | FC_SCC_DUMMY_BIT_MASK + | FC_SCC_DATA_BIT_MASK + | FC_SCC_DUMMY_DATA_BIT_MASK, + (cmd << FC_SCC_CMD_BIT_SHIFT) + | (addr << FC_SCC_ADDR_BIT_SHIFT) + | (dummy << FC_SCC_DUMMY_BIT_SHIFT) + | (data << FC_SCC_DATA_BIT_SHIFT) + | (dummy_width << FC_SCC_DUMMY_DATA_BIT_SHIFT)); +} + +static inline void FC_Sbus_Command(uint8_t cmd, uint32_t addr, uint32_t dummyh, uint32_t dummyl) +{ + HAL_MODIFY_REG(FLASH_CTRL->S_CMD_CFG, FC_SCC_CMD_MASK, cmd << FC_SCC_CMD_SHIFT); + HAL_MODIFY_REG(FLASH_CTRL->S_ADDR_CFG, FC_SAC_MASK, addr << FC_SAC_SHIFT); + HAL_MODIFY_REG(FLASH_CTRL->S_DUMMY_H, FC_SDH_MASK, dummyh << FC_SDH_SHIFT); + HAL_MODIFY_REG(FLASH_CTRL->S_DUMMY_L, FC_SDL_MASK, dummyl << FC_SDL_SHIFT); +} + +static inline void FC_Sbus_WriteSize(uint16_t size) +{ + if (size & (~0x1FF)) + FC_DEBUG("write number error"); + size &= 0x1FF; + HAL_MODIFY_REG(FLASH_CTRL->S_WR_NUM, FC_SWN_MASK, size << FC_SWN_SHIFT); +} + +static inline void FC_Sbus_ReadSize(uint32_t size) +{ + HAL_MODIFY_REG(FLASH_CTRL->S_RD_NUM, FC_SRN_MASK, size << FC_SRN_SHIFT); +} + +/*static inline void FC_Sbus_DummyData(uint32_t dummyh, uint32_t dummyl) +{ + FLASH_CTRL->S_DUMMY_H = dummyh; + FLASH_CTRL->S_DUMMY_L = dummyl; +}*/ + +static inline void FC_Sbus_TransmitDelay(Flash_Ctrl_DelayCycle *delay) +{ + HAL_MODIFY_REG(FLASH_CTRL->I_CS_WAIT, + FC_ICW_BEGIN_MASK + | FC_ICW_OVER_MASK, + (delay->cs_begin << FC_ICW_BEGIN_SHIFT) + | (delay->cs_over << FC_ICW_OVER_SHIFT)); + + HAL_MODIFY_REG(FLASH_CTRL->COMMON_ADD_CFG, + FC_CAC_CS_DESEL_WAIT_MASK, + delay->cs_deselect << FC_CAC_CS_DESEL_WAIT_SHIFT); + + HAL_MODIFY_REG(FLASH_CTRL->S_IO_WAIT, + FC_SIW_CMD_MASK + | FC_SIW_ADDR_MASK + | FC_SIW_DUMMY_MASK, + (delay->cmd_over << FC_SIW_CMD_SHIFT) + | (delay->addr_over << FC_SIW_ADDR_SHIFT) + | (delay->dummy_over << FC_SIW_DUMMY_SHIFT)); + + HAL_MODIFY_REG(FLASH_CTRL->FLASH_COMMON_CFG, + FC_FCC_WAIT_DATA_MASK, + delay->data << FC_FCC_WAIT_DATA_SHIFT); +} + +static inline void FC_Sbus_FIFOTriggerLevel(uint8_t txfull, uint8_t txempty, uint8_t rxfull, uint8_t rxempty) +{ + HAL_MODIFY_REG(FLASH_CTRL->FIFO_TRIG_LEVEL, + FC_FTL_RD_FIFO_EMPTY_MASK + | FC_FTL_RD_FIFO_FULL_MASK + | FC_FTL_WR_FIFO_EMPTY_MASK + | FC_FTL_WR_FIFO_FULL_MASK, + (txfull << FC_FTL_WR_FIFO_FULL_SHIFT) + | (txempty << FC_FTL_WR_FIFO_EMPTY_SHIFT) + | (rxfull << FC_FTL_RD_FIFO_FULL_SHIFT) + | (rxempty << FC_FTL_RD_FIFO_EMPTY_SHIFT)); +} + +typedef enum FC_Sbus_RW +{ + FC_SBUS_READ, + FC_SBUS_WRITE, +} FC_Sbus_RW; + +bool FC_Sbus_IsAvailable(FC_Sbus_RW rw) +{ + if (rw == FC_SBUS_WRITE) + return !!HAL_GET_BIT(FLASH_CTRL->FIFO_STATUS, FC_FS_WR_BUF_VALID_MASK); + else + return !!HAL_GET_BIT(FLASH_CTRL->FIFO_STATUS, FC_FS_RD_BUF_VALID_MASK); +} + +int FC_Sbus_GetBufCnt(FC_Sbus_RW rw) +{ + if (rw == FC_SBUS_WRITE) + return HAL_GET_BIT_VAL(FLASH_CTRL->FIFO_STATUS, FC_FS_WR_BUF_CNT_SHIFT, FC_FS_WR_BUF_CNT_VMASK); + else + return HAL_GET_BIT_VAL(FLASH_CTRL->FIFO_STATUS, FC_FS_RD_BUF_CNT_SHIFT, FC_FS_RD_BUF_CNT_VMASK); +} + +int FC_Sbus_GetFIFOCnt(FC_Sbus_RW rw) +{ + if (rw == FC_SBUS_WRITE) + return HAL_GET_BIT_VAL(FLASH_CTRL->FIFO_STATUS, FC_FS_WR_FIFO_CNT_SHIFT, FC_FS_WR_FIFO_CNT_VMASK); + else + return HAL_GET_BIT_VAL(FLASH_CTRL->FIFO_STATUS, FC_FS_RD_FIFO_CNT_SHIFT, FC_FS_RD_FIFO_CNT_VMASK); +} + +/* + Debug State: + 0x2 Send CMD; + 0x4 Send Address; + 0x6 Send Dummy; + 0x8 Send Data; + 0x9 Get Data; +*/ +static inline int FC_Sbus_GetDebugState() +{ + return HAL_GET_BIT_VAL(FLASH_CTRL->FIFO_STATUS, FC_FS_STATUS_DGB_SHIFT, FC_FS_STATUS_DGB_VMASK); +} + +#if (FC_DEBUG_ON == DBG_ON) +#define FC_DebugCheck(state) __FC_DebugCheck(state, __LINE__) +static int __FC_DebugCheck(int state, uint32_t line) +{ + int debug = FC_Sbus_GetDebugState(); + if (debug != state) { + HAL_UDelay(5000); + debug = FC_Sbus_GetDebugState(); + if (debug != state) { + FC_DEBUG("line: %d, error state: 0x%x", line, state); + FC_REG_ALL(); + return -1; + } + } + return 0; +} +#else +#define FC_DebugCheck(state) __FC_DebugCheck(state) +static inline int __FC_DebugCheck(int state) +{ + while(FC_Sbus_GetDebugState() != state); + return 0; +} + +#endif + +static inline bool FC_IsWrapMode() +{ + return !!HAL_GET_BIT(FLASH_CTRL->WRAP_MODE, FC_WM_MASK); +} + +static inline void FC_Sbus_StartSend() +{ + HAL_SET_BIT(FLASH_CTRL->START_SEND, FC_SS_MASK); +} + +static inline bool FC_Sbus_isSending() +{ + return !!HAL_GET_BIT(FLASH_CTRL->START_SEND, FC_SS_MASK); +} + +typedef enum FC_Sbus_IntType +{ + FC_INT_HREADY_TIMEOUT = 1 << 13, + FC_INT_TC = 1 << FC_IE_CMPL_SHIFT, + FC_INT_WR_FIFO_UNDERFLOW = 1 << FC_IE_WR_FIFO_UNDERFLOW_SHIFT, + FC_INT_WR_FIFO_OVERFLOW = 1 << FC_IE_WR_FIFO_OVERFLOW_SHIFT, + FC_INT_RD_FIFO_UNDERFLOW = 1 << FC_IE_RD_FIFO_UNDERFLOW_SHIFT, + FC_INT_RD_FIFO_OVERFLOW = 1 << FC_IE_RD_FIFO_OVERFLOW_SHIFT, + FC_INT_WR_FIFO_FULL = 1 << FC_IE_WR_FIFO_FULL_SHIFT, + FC_INT_WR_FIFO_EMPTY = 1 << FC_IE_WR_FIFO_EMPTY_SHIFT, + FC_INT_WR_FIFO_READY = 1 << FC_IE_WR_FIFO_READY_SHIFT, + FC_INT_RD_FIFO_FULL = 1 << FC_IE_RD_FIFO_FULL_SHIFT, + FC_INT_RD_FIFO_EMPTY = 1 << FC_IE_RD_FIFO_EMPTY_SHIFT, + FC_INT_RD_FIFO_READY = 1 << FC_IE_RD_FIFO_READY_SHIFT, +} FC_Sbus_IntType; + +static inline void FC_Sbus_EnableInt(FC_Sbus_IntType type) +{ + HAL_SET_BIT(FLASH_CTRL->INT_EN, type); +} + +static inline void FC_Sbus_DisableInt(FC_Sbus_IntType type) +{ + HAL_CLR_BIT(FLASH_CTRL->INT_EN, type); +} + +static inline int FC_Sbus_GetStatus(FC_Sbus_IntType type) +{ + return !!HAL_GET_BIT(FLASH_CTRL->INT_STA, type); +} + +static inline void FC_Sbus_ClrStatus(FC_Sbus_IntType type) +{ + HAL_CLR_BIT(FLASH_CTRL->INT_STA, type); +} + +static inline void FC_Sbus_Write(uint8_t data) +{ + *((uint8_t *)&FLASH_CTRL->S_WDATA) = data; +} + +static inline uint8_t FC_Sbus_Read(void) +{ + return *((uint8_t *)&FLASH_CTRL->S_RDATA); +} + +static inline uint8_t FC_GetDataDelay(uint32_t freq) +{ + if (freq < 48000000) + return 0; + else if (freq <= 64000000) + return 1; + else + return 2; +} + +/* + * @brief + */ +static uint8_t ccmu_on = 0; +static void HAL_Flashc_EnableCCMU() +{ + if (ccmu_on++ != 0) + return; + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_FLASHC); + HAL_CCM_FLASHC_EnableMClock(); +} + +/* + * @brief + */ +static void HAL_Flashc_DisableCCMU() +{ + if (--ccmu_on != 0) + return; + + FC_DEBUG("DISABLE CCMU"); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_FLASHC); + HAL_CCM_FLASHC_DisableMClock(); +} + +static inline void HAL_Flashc_ResetCCMU() +{ + CCM_BusPeriphBit ccm_flashc = CCM_BUS_PERIPH_BIT_FLASHC; /* spi_port translate to ccm_bit */ + HAL_CCM_BusForcePeriphReset(ccm_flashc); + HAL_CCM_BusReleasePeriphReset(ccm_flashc); +} + + +/* + * @brief + */ +static bool HAL_Flashc_ConfigCCMU(uint32_t clk) +{ + CCM_AHBPeriphClkSrc src; + uint32_t mclk; + uint32_t div; + + if (clk > HAL_GetHFClock()) + { + mclk = HAL_PRCM_GetDevClock(); + src = CCM_AHB_PERIPH_CLK_SRC_DEVCLK; + } + else + { + mclk = HAL_GetHFClock(); + src = CCM_AHB_PERIPH_CLK_SRC_HFCLK; + } + + div = (mclk + clk - 1) / clk; + div = div==0 ? 1 : div; + + if (div > (16 * 8)) + return 0; + + if (div > 64) + HAL_CCM_FLASHC_SetMClock(src, CCM_PERIPH_CLK_DIV_N_8, (CCM_PeriphClkDivM)((div >> 3) - 1)); + else if (div > 32) + HAL_CCM_FLASHC_SetMClock(src, CCM_PERIPH_CLK_DIV_N_4, (CCM_PeriphClkDivM)((div >> 2) - 1)); + else if (div > 16) + HAL_CCM_FLASHC_SetMClock(src, CCM_PERIPH_CLK_DIV_N_2, (CCM_PeriphClkDivM)((div >> 1) - 1)); + else + HAL_CCM_FLASHC_SetMClock(src, CCM_PERIPH_CLK_DIV_N_1, (CCM_PeriphClkDivM)((div >> 0) - 1)); + + return 1; +} + +#ifdef CONFIG_PM +static int hal_flashc_suspending = 0; +static XIP_Config pm_ibus_cfg; +static Flashc_Config pm_sbus_cfg; +static uint8_t pm_xip = 0; +static struct soc_device flashc_dev; +#endif + +static uint8_t xip_on = 0; +static uint8_t pin_inited = 0; +static FC_En xip_continue = 0; +static int sbusing = 0; + + +void HAL_XIP_Delay(unsigned int us); + +static void HAL_Flashc_PinInit() +{ +// unsigned long flags = HAL_EnterCriticalSection(); + if (pin_inited++ != 0) { +// HAL_ExitCriticalSection(flags); + return; + } + /* open io */ + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_FLASHC, 0), 0); +// HAL_ExitCriticalSection(flags); +} + +static void HAL_Flashc_PinDeinit() +{ +// unsigned long flags = HAL_EnterCriticalSection(); + if (--pin_inited != 0) { +// HAL_ExitCriticalSection(flags); + return; + } + //close io + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_FLASHC, 0), 0); +// HAL_ExitCriticalSection(flags); +} + +/** + * @brief Initialize Flash controller IBUS driver (XIP). + * @param cfg: + * @arg cfg->addr: Started address of XIP code in Flash. + * @arg cfg->freq: Flash working frequency. + * @arg cfg->delay: Delay of hardware. + * @arg cfg->ins: Instruction of XIP reading + * @arg cfg->cont_mode: Enable continue mode in reading or not. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Xip_Init(XIP_Config *cfg) +{ +#ifdef CONFIG_PM + if (!hal_flashc_suspending) + HAL_Memcpy(&pm_ibus_cfg, cfg, sizeof(pm_ibus_cfg)); + xip_on = 1; +#endif + + /* enable ccmu */ + HAL_Flashc_EnableCCMU(); + + /* open io */ + HAL_Flashc_PinInit(); + + FC_Ibus_Disable(FC_EN_CONTINUE | FC_EN_IBUS | FC_EN_PREFETCH); + + /* config flash controller */ + Flash_Ctrl_DelayCycle delay = {1, 0, 3, 0, 0, 0, 1}; + delay.data = FC_GetDataDelay(cfg->freq); + FC_Ibus_TransmitDelay(&delay); + + FC_SetFlash(FC_TCTRL_CS_LOW_ENABLE, FC_TCTRL_FBS_MSB, FC_SCLK_Mode0); + + FC_Ibus_ReadConfig(cfg->ins.cmd, + cfg->ins.cmd_line, + cfg->ins.addr_line, + cfg->ins.dummy_line, + cfg->ins.data_line, + cfg->ins.dum_btyes); + if (cfg->cont_mode) { + FC_Ibus_DummyData(0x20000000, 0); + FC_Ibus_Enable(FC_EN_CONTINUE | FC_EN_IBUS); + xip_continue = FC_EN_CONTINUE; + } else { + FC_Ibus_DummyData(0, 0); + FC_Ibus_Enable(FC_EN_IBUS); + } + + //config flash cache + FlashCache_Config cache_cfg = {cfg->addr}; + Hal_FlashCache_Init(&cache_cfg); + + FC_DEBUG("cfg->freq: %d; cfg->ins.cmd: %d; cfg->ins.cmd_line: %d", cfg->freq, cfg->ins.cmd, cfg->ins.cmd_line); + FC_DEBUG("cfg->ins.addr_line: %d; cfg->ins.dummy_line: %d; cfg->ins.data_line: %d", cfg->ins.addr_line, cfg->ins.dummy_line, cfg->ins.data_line); + FC_DEBUG("cfg->ins.dum_btyes: %d; cfg->cont_mode: %d; cfg->addr: %d", cfg->ins.dum_btyes, cfg->cont_mode, cfg->addr); + + FC_DEBUG("ccmu : %d", ccmu_on); + + FC_REG_ALL(); + + return HAL_OK; +} + +/** + * @brief Deinitialize Flash controller IBUS (XIP). + * @param None + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Xip_Deinit() +{ + unsigned long flags = HAL_EnterCriticalSection(); + //config flash controller + FC_Ibus_Disable(FC_EN_CONTINUE | FC_EN_IBUS | FC_EN_PREFETCH); + xip_on = 0; + HAL_ExitCriticalSection(flags); + + //close io + HAL_Flashc_PinDeinit(); + + //deinit flash cache + Hal_FlashCache_Deinit(); + + //disable ccmu + HAL_Flashc_DisableCCMU(); + + return HAL_OK; +} + +/** + * @internal + * @brief Flash controller IBUS (XIP) Enable without Pin initialization. + * @note Most for Flash controller SBUS. It will resume system schedule. + * @param None + * @retval None + */ +void HAL_Flashc_Xip_RawEnable() +{ + if (!xip_on) + return; + +// HAL_UDelay(100); +// FC_Ibus_Enable(FC_EN_IBUS | xip_continue); + + FC_Ibus_Enable(xip_continue); + OS_ThreadResumeScheduler(); +} + +/** + * @internal + * @brief Flash controller IBUS (XIP) Enable with Pin initialization. + * @note Most for SPI. It will resume system schedule. + * @param None + * @retval None + */ +void HAL_Flashc_Xip_Enable() +{ + /* open io */ + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_FLASHC, 0), 0); + HAL_Flashc_Xip_RawEnable(); +} + +/** + * @internal + * @brief Flash controller IBUS (XIP) Enable without Pin deinitialization. + * @note Most for Flash controller SBUS. It will suspend system schedule. + * @param None + * @retval None + */ +void HAL_Flashc_Xip_RawDisable() +{ + if (!xip_on) + return; + + OS_ThreadSuspendScheduler(); +// HAL_UDelay(100); +// FC_Ibus_Disable(FC_EN_IBUS | xip_continue); + while((FC_Sbus_GetDebugState() != 0x0c) && (FC_Sbus_GetDebugState() != 0x00)); + FC_Ibus_Disable(xip_continue); +} + +/** + * @internal + * @brief Flash controller IBUS (XIP) Enable with Pin deinitialization. + * @note Most for SPI. It will suspend system schedule. + * @param None + * @retval None + */ +void HAL_Flashc_Xip_Disable() +{ + HAL_Flashc_Xip_RawDisable(); + + //close io + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_FLASHC, 0), 0); +} + + +/** + * @brief Delay realization in Flash controller IBUS (XIP). + * @note Delay can be system sleep while it's not in XIP, but must be a while + * delay without system interface while it's in XIP. + * @param us: delay time in microsecond. + * @retval None + */ +void HAL_XIP_Delay(unsigned int us) +{ + if (us == 0) + return; + + if (xip_on) + { + HAL_UDelay(us); + } + else + { + us += 1023; + unsigned int ms = us >> 10; + HAL_MSleep(ms); + } +} + +/** + * @brief Initialize Flash controller SBUS. + * @param cfg: + * @arg cfg->freq: Flash working frequency. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Init(const Flashc_Config *cfg) +{ + /* enable ccmu */ + HAL_Flashc_ResetCCMU(); + HAL_Flashc_ConfigCCMU(cfg->freq); + HAL_Flashc_EnableCCMU(); + + /* config flash controller */ + Flash_Ctrl_DelayCycle delay = {1, 0, 3, 0, 0, 0, 1}; + /*delay.cs_deselect = cfg->t_shsl_ns * (cfg->freq / 1000000) / 1000;*/ + delay.data = FC_GetDataDelay(cfg->freq); + FC_Sbus_TransmitDelay(&delay); + + FC_SetFlash(FC_TCTRL_CS_LOW_ENABLE, FC_TCTRL_FBS_MSB, FC_SCLK_Mode0); + FC_Sbus_ResetFIFO(1, 1); + + FC_DEBUG("ccmu : %d", ccmu_on); + FC_REG_ALL(); + + HAL_Flashc_DisableCCMU(); + +#ifdef CONFIG_PM + if (!hal_flashc_suspending) + { + HAL_Memcpy(&pm_sbus_cfg, cfg, sizeof(pm_sbus_cfg)); + pm_register_ops(&flashc_dev); + } +#endif + + return HAL_OK; +} + +/** + * @brief Deinitialize Flash controller SBUS. + * @param None + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Deinit() +{ +#ifdef CONFIG_PM + if (!hal_flashc_suspending) + pm_unregister_ops(&flashc_dev); +#endif + + return HAL_OK; +} + +/** + * @brief Open flash controller SBUS. + * @note At the same time, it will disable XIP and suspend schedule. + * @param None + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Open() +{ + sbusing = 1; + HAL_Flashc_Xip_RawDisable(); + + HAL_Flashc_EnableCCMU(); + HAL_Flashc_PinInit(); + FC_Sbus_ResetFIFO(1, 1); + + return HAL_OK; +} + +/** + * @brief Close flash controller SBUS. + * @param None + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Close() +{ + HAL_Flashc_PinDeinit(); + HAL_Flashc_DisableCCMU(); + + HAL_Flashc_Xip_RawEnable(); + sbusing = 0; + return HAL_OK; +} + +/** + * @brief Flash controller ioctl. + * @note op : arg + * nothing support for now. + * @param op: ioctl command. + * @param arg: ioctl arguement + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Control(Flashc_Commands op, void *arg) +{ + /*TODO: tbc...*/ + + return HAL_INVALID; +} + +/** + * @brief Write flash by flash controller SBUS. + * @note Send a instruction in command + address + dummy + write data. + * @param cmd: Command of instruction. + * @arg cmd->pdata: The data is filled with in this field. + * @arg cmd->len: The data len of this field. + * @arg cmd->line: The number of line transfering this field data. + * @param addr: Address of instruction + * @param dummy: Dummy of instruction + * @param data: Data of instruction + * @param dma: Transfer data by DMA or not. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Write(FC_InstructionField *cmd, FC_InstructionField *addr, FC_InstructionField *dummy, FC_InstructionField *data, bool dma) +{ + HAL_Status ret; + FC_InstructionField zero; + HAL_Memset(&zero, 0, sizeof(zero)); + + /* instruction check */ + if (cmd == NULL) + cmd = &zero; + if (addr == NULL) + addr = &zero; + if (dummy == NULL) + dummy = &zero; + if (data == NULL) + data = &zero; + + FC_Sbus_ResetFIFO(1, 1); + FC_Sbus_CommandConfig(cmd->line, addr->line, dummy->line, data->line, dummy->len); + FC_Sbus_Command(*(cmd->pdata), *((uint32_t *)addr->pdata), 0, 0); + FC_Sbus_WriteSize(data->len); + + if (dma == 1 && data->len != 0 && !xip_on) + ret = HAL_Flashc_DMAWrite(data->pdata, data->len); + else + ret = HAL_Flashc_PollWrite(data->pdata, data->len); + + if (ret != HAL_OK) + FC_ERROR("error occured on cmd: 0x%x, data len: %d", *cmd->pdata, data->len); + + return ret; +} + +/** + * @brief Read flash by flash controller SBUS. + * @note Send a instruction in command + address + dummy + read data. + * @param cmd: Command of instruction. + * @arg cmd->pdata: The data is filled with in this field. + * @arg cmd->len: The data len of this field. + * @arg cmd->line: The number of line transfering this field data. + * @param addr: Address of instruction + * @param dummy: Dummy of instruction + * @param data: Data of instruction + * @param dma: Transfer data by DMA or not. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_Flashc_Read(FC_InstructionField *cmd, FC_InstructionField *addr, FC_InstructionField *dummy, FC_InstructionField *data, bool dma) +{ + HAL_Status ret; + FC_InstructionField zero; + HAL_Memset(&zero, 0, sizeof(zero)); + + /* instruction check */ + if (cmd == NULL) + cmd = &zero; + if (addr == NULL) + addr = &zero; + if (dummy == NULL) + dummy = &zero; + if (data == NULL) + data = &zero; + + FC_Sbus_ResetFIFO(1, 1); + FC_Sbus_CommandConfig(cmd->line, addr->line, dummy->line, data->line, dummy->len); + FC_Sbus_Command(*(cmd->pdata), *((uint32_t *)addr->pdata), 0, 0); + FC_Sbus_ReadSize(data->len); + + if (dma == 1 && data->len != 0 && !xip_on) + ret = HAL_Flashc_DMARead(data->pdata, data->len); + else + ret = HAL_Flashc_PollRead(data->pdata, data->len); + + if (ret != HAL_OK) + FC_ERROR("error occured on cmd: 0x%x, data len: %d", *cmd->pdata, data->len); + + return ret; +} + +HAL_Semaphore dmaSem; + +static void HAL_Flashc_DMARelease(void *arg) +{ + HAL_SemaphoreRelease(&dmaSem); +} + +static HAL_Status HAL_Flashc_DMAWrite(uint8_t *data, uint32_t size) +{ + HAL_Status ret = HAL_OK; + DMA_ChannelInitParam dma_arg; + DMA_Channel dma_ch; + HAL_Memset(&dma_arg, 0, sizeof(dma_arg)); + HAL_Memset(&dma_ch, 0, sizeof(dma_ch)); + HAL_Memset(&dmaSem, 0, sizeof(dmaSem)); + + if (size == 0 || data == NULL) + return HAL_ERROR; + + if ((dma_ch = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + FC_ERROR("DMA request failed"); + ret = HAL_BUSY; + goto failed; + } + + HAL_SemaphoreInit(&dmaSem, 0, 1); + + dma_arg.irqType = DMA_IRQ_TYPE_END; + dma_arg.endCallback = HAL_Flashc_DMARelease; + dma_arg.endArg = NULL; + dma_arg.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + (DMA_Periph)(DMA_PERIPH_FLASHC), + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM); + HAL_DMA_Init(dma_ch, &dma_arg); + HAL_DMA_Start(dma_ch, (uint32_t)data, (uint32_t)&FLASH_CTRL->S_WDATA, size); + + FC_Sbus_StartSend(); + if ((ret = HAL_SemaphoreWait(&dmaSem, 5000)) != HAL_OK) + FC_ERROR("sem wait failed: %d", ret); + + uint32_t i; +// FC_WHILE_TIMEOUT(FC_Sbus_GetStatus(FC_INT_TC) == 0, i); + FC_WHILE_TIMEOUT(FC_Sbus_isSending(), i); + FC_Sbus_ClrStatus(FC_INT_TC); + + HAL_DMA_Stop(dma_ch); + HAL_DMA_DeInit(dma_ch); + HAL_DMA_Release(dma_ch); + + HAL_SemaphoreDeinit(&dmaSem); + + if (FC_DebugCheck(0)) + return HAL_ERROR; + +failed: + return ret; +} + +static HAL_Status HAL_Flashc_PollWrite(uint8_t *data, uint32_t size) +{ + uint32_t wsize = size; + uint32_t i; + + FC_Sbus_StartSend(); + + while (wsize--) { + FC_WHILE_TIMEOUT(FC_Sbus_GetFIFOCnt(FC_SBUS_WRITE) > 100, i); + FC_Sbus_Write(*(data++)); + } + +// FC_WHILE_TIMEOUT(FC_Sbus_GetDebugState() != 0, i); +// FC_WHILE_TIMEOUT(FC_Sbus_GetStatus(FC_INT_TC) == 0, i); + FC_WHILE_TIMEOUT(FC_Sbus_isSending(), i); + FC_Sbus_ClrStatus(FC_INT_TC); + + if (FC_DebugCheck(0)) + return HAL_ERROR; + + return HAL_OK; +} + +static HAL_Status HAL_Flashc_DMARead(uint8_t *data, uint32_t size) +{ + HAL_Status ret = HAL_OK; + DMA_ChannelInitParam dma_arg; + DMA_Channel dma_ch; + HAL_Memset(&dma_arg, 0, sizeof(dma_arg)); + HAL_Memset(&dma_ch, 0, sizeof(dma_ch)); + HAL_Memset(&dmaSem, 0, sizeof(dmaSem)); + + if (size == 0 || data == NULL) + return HAL_ERROR; + + if ((dma_ch = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + FC_ERROR("DMA request failed"); + ret = HAL_BUSY; + goto failed; + } + + HAL_SemaphoreInit(&dmaSem, 0, 1); + + dma_arg.irqType = DMA_IRQ_TYPE_END; + dma_arg.endCallback = HAL_Flashc_DMARelease; + dma_arg.endArg = NULL; + dma_arg.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + (DMA_Periph)(DMA_PERIPH_FLASHC)); + HAL_DMA_Init(dma_ch, &dma_arg); + HAL_DMA_Start(dma_ch, (uint32_t)&FLASH_CTRL->S_RDATA, (uint32_t)data, size); + + FC_Sbus_StartSend(); + if ((ret = HAL_SemaphoreWait(&dmaSem, 5000)) != HAL_OK) + FC_ERROR("sem wait failed: %d", ret); + + uint32_t i; +// FC_WHILE_TIMEOUT(FC_Sbus_GetStatus(FC_INT_TC) == 0, i); + FC_WHILE_TIMEOUT(FC_Sbus_isSending(), i); + FC_Sbus_ClrStatus(FC_INT_TC); + + HAL_DMA_Stop(dma_ch); + HAL_DMA_DeInit(dma_ch); + HAL_DMA_Release(dma_ch); + + HAL_SemaphoreDeinit(&dmaSem); + + if (FC_DebugCheck(0)) + return HAL_ERROR; + +failed: + return ret; +} + +static HAL_Status HAL_Flashc_PollRead(uint8_t *data, uint32_t size) +{ + uint32_t rsize = size; + uint32_t i; + + FC_Sbus_StartSend(); + + while (rsize--) + { + FC_WHILE_TIMEOUT(FC_Sbus_GetFIFOCnt(FC_SBUS_READ) == 0, i); + *(data++) = FC_Sbus_Read(); + } + +// FC_WHILE_TIMEOUT(FC_Sbus_GetDebugState() != 0, i); +// FC_WHILE_TIMEOUT(FC_Sbus_GetStatus(FC_INT_TC) == 0, i); + FC_WHILE_TIMEOUT(FC_Sbus_isSending(), i); + FC_Sbus_ClrStatus(FC_INT_TC); + + if (FC_DebugCheck(0)) + return HAL_ERROR; + + return HAL_OK; +} + + +#ifdef CONFIG_PM +static int flashc_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + /* + suspend condition: + (1) not in sbus opened state + (2) + */ + hal_flashc_suspending = 1; + + if (sbusing) + return -1; + + while((FC_Sbus_GetDebugState() != 0x0c) && (FC_Sbus_GetDebugState() != 0x00)); + + switch (state) { + case PM_MODE_SLEEP: + FC_Ibus_Disable(xip_continue); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_FLASHC); + HAL_CCM_FLASHC_DisableMClock(); + break; + case PM_MODE_STANDBY: + if (xip_on) + { + HAL_Flashc_Xip_Deinit(); + FC_DEBUG("ccmu : %d", ccmu_on); + pm_xip = 1; + } + HAL_Flashc_Deinit(); + FC_DEBUG("ccmu : %d", ccmu_on); + break; + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + + break; + default: + break; + } + + FC_REG_ALL(); + return 0; +} + +static int flashc_resume(struct soc_device *dev, enum suspend_state_t state) +{ + + FC_REG_ALL(); + + switch (state) { + case PM_MODE_SLEEP: + FC_Ibus_Enable(xip_continue); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_FLASHC); + HAL_CCM_FLASHC_EnableMClock(); + break; + case PM_MODE_STANDBY: + HAL_Flashc_Init(&pm_sbus_cfg); + if (pm_xip) + { + pm_xip = 0; + HAL_Flashc_Xip_Init(&pm_ibus_cfg); + HAL_UDelay(300); + } + FC_DEBUG("ccmu: %d, pin: %d", ccmu_on, pin_inited); + break; + + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + + break; + default: + break; + } + + hal_flashc_suspending = 0; + + return 0; +} + +static struct soc_device_driver flashc_drv = { + .name = "flashc", + .suspend_noirq = flashc_suspend, + .resume_noirq = flashc_resume, +}; + +static struct soc_device flashc_dev = { + .name = "flashc", + .driver = &flashc_drv, +}; +#endif + diff --git a/platform/mcu/xr871/src/driver/chip/hal_global.c b/platform/mcu/xr871/src/driver/chip/hal_global.c new file mode 100644 index 0000000000..fddb47bdb7 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_global.c @@ -0,0 +1,46 @@ +/** + * @file hal_global.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal_base.h" + +/** + * @brief Global initialization for HAL module + * @return None + */ +void HAL_GlobalInit(void) +{ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_DEFAULT); + HAL_CCM_BusForceAllPeriphReset(); + HAL_CCM_BusDisableAllPeriphClock(); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_gpio.c b/platform/mcu/xr871/src/driver/chip/hal_gpio.c new file mode 100644 index 0000000000..16bbeaf9b9 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_gpio.c @@ -0,0 +1,423 @@ +/** + * @file hal_gpio.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_gpio.h" +#include "hal_base.h" + +/* + * register bits of GPIO_CTRL_T for each GPIO pin + */ +#define GPIO_CTRL_MODE_BITS 4 +#define GPIO_CTRL_MODE_MASK 0xFU +#define GPIO_CTRL_MODE_MAX GPIOx_Pn_F7_DISABLE + +#define GPIO_CTRL_DATA_BITS 1 + +#define GPIO_CTRL_DRIVING_BITS 2 +#define GPIO_CTRL_DRIVING_MASK 0x3U +#define GPIO_CTRL_DRIVING_MAX GPIO_DRIVING_LEVEL_3 + +#define GPIO_CTRL_PULL_BITS 2 +#define GPIO_CTRL_PULL_MASK 0x3U +#define GPIO_CTRL_PULL_MAX GPIO_PULL_DOWN + +/* + * register bits of GPIO_IRQ_T for each GPIO pin + */ +#define GPIO_IRQ_EVT_BITS 4 +#define GPIO_IRQ_EVT_MASK 0xFU +#define GPIO_IRQ_EVT_MAX GPIO_IRQ_EVT_BOTH_EDGE + +#define GPIO_IRQ_EN_BITS 1 + +#define GPIO_IRQ_STAUTS_BITS 1 + +/* useful macros */ +#define GPIO_PINS_MASK(pinNum) ((1U << pinNum) - 1) + +#define GPIO_REG_BITS 32 +#define GPIO_GET_REG_IDX_SHIFT(idx, shift, pin, bits) \ + do { \ + (shift) = (pin) * (bits); \ + (idx) = (shift) / GPIO_REG_BITS; \ + (shift) = (shift) % GPIO_REG_BITS; \ + } while (0) + +typedef struct { + GPIO_IRQCallback callback; + void *arg; +} GPIO_Private; + +static GPIO_Private gGPIOAPrivate[GPIOA_PIN_NUM]; +static GPIO_Private gGPIOBPrivate[GPIOB_PIN_NUM]; + +static uint8_t gGPIOUsedCnt = 0; + +#define GPIOA_CTRL ((GPIO_CTRL_T *)GPIOA_CTRL_BASE) +#define GPIOB_CTRL ((GPIO_CTRL_T *)GPIOB_CTRL_BASE) + +#define GPIOA_IRQ ((GPIO_IRQ_T *)GPIOA_IRQ_BASE) +#define GPIOB_IRQ ((GPIO_IRQ_T *)GPIOB_IRQ_BASE) + +static GPIO_CTRL_T * const gGPIOPortCtrl[GPIO_PORT_NUM] = { GPIOA_CTRL, GPIOB_CTRL }; +static GPIO_IRQ_T * const gGPIOPortIRQ[GPIO_PORT_NUM] = { GPIOA_IRQ, GPIOB_IRQ }; + + +__STATIC_INLINE GPIO_CTRL_T *GPIO_GetCtrlInstance(GPIO_Port port) +{ + return gGPIOPortCtrl[port]; +} + +__STATIC_INLINE GPIO_IRQ_T *GPIO_GetIRQInstance(GPIO_Port port) +{ + return gGPIOPortIRQ[port]; +} + +/* + * IRQ handling + */ +static void GPIO_IRQHandler(GPIO_IRQ_T *gpiox, uint32_t pinNum, uint32_t pinMask, GPIO_Private *priv) +{ + uint32_t i; + uint32_t irqStatus; + uint32_t isPending; + + irqStatus = gpiox->IRQ_STATUS & gpiox->IRQ_EN & pinMask; /* get pending bits */ + gpiox->IRQ_STATUS = irqStatus; /* clear pending bits */ + + for (i = GPIO_PIN_0; i < pinNum && irqStatus != 0; ++i) { + isPending = irqStatus & HAL_BIT(0); + if (isPending && priv[i].callback) { + priv[i].callback(priv[i].arg); + } + irqStatus >>= 1; + } +} + +void GPIOA_IRQHandler(void) +{ + GPIO_IRQHandler(GPIOA_IRQ, GPIOA_PIN_NUM, GPIO_PINS_MASK(GPIOA_PIN_NUM), gGPIOAPrivate); +} + +void GPIOB_IRQHandler(void) +{ + GPIO_IRQHandler(GPIOB_IRQ, GPIOB_PIN_NUM, GPIO_PINS_MASK(GPIOB_PIN_NUM), gGPIOBPrivate); +} + +static void GPIO_EnableIRQ(GPIO_IRQ_T *gpiox, GPIO_Pin pin) +{ + HAL_SET_BIT(gpiox->IRQ_EN, HAL_BIT(pin)); +} + +static void GPIO_DisableIRQ(GPIO_IRQ_T *gpiox, GPIO_Pin pin) +{ + HAL_CLR_BIT(gpiox->IRQ_EN, HAL_BIT(pin)); +} + +static int GPIO_IsPendingIRQ(GPIO_IRQ_T *gpiox, GPIO_Pin pin) +{ + return HAL_GET_BIT_VAL(gpiox->IRQ_STATUS, pin, 1); +} + +static void GPIO_ClearPendingIRQ(GPIO_IRQ_T *gpiox, GPIO_Pin pin) +{ + HAL_SET_BIT(gpiox->IRQ_STATUS, HAL_BIT(pin)); +} + +void HAL_GPIO_EnableIRQ(GPIO_Port port, GPIO_Pin pin, const GPIO_IrqParam *param) +{ + uint32_t regIdx; + uint32_t bitShift; + GPIO_IRQ_T *gpiox; + GPIO_Private *gpioPriv; + IRQn_Type IRQn; + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + + if (port == GPIO_PORT_A) { + gpioPriv = gGPIOAPrivate; + IRQn = GPIOA_IRQn; + } else if (port == GPIO_PORT_B) { + gpioPriv = gGPIOBPrivate; + IRQn = GPIOB_IRQn; + } else { + HAL_ERR("Invalid port %d for IRQ\n", port); + return; + } + gpiox = GPIO_GetIRQInstance(port); + + /* set callback */ + gpioPriv[pin].callback = param->callback; + gpioPriv[pin].arg = param->arg; + + /* set IRQ trigger mode */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_IRQ_EVT_BITS); + HAL_MODIFY_REG(gpiox->IRQ_MODE[regIdx], + GPIO_IRQ_EVT_MASK << bitShift, + (param->event & GPIO_IRQ_EVT_MASK) << bitShift); + + if (GPIO_IsPendingIRQ(gpiox, pin)) { + GPIO_ClearPendingIRQ(gpiox, pin); + } + GPIO_EnableIRQ(gpiox, pin); + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(IRQn); + + HAL_ExitCriticalSection(flags); +} + +void HAL_GPIO_DisableIRQ(GPIO_Port port, GPIO_Pin pin) +{ + GPIO_IRQ_T *gpiox; + GPIO_Private *gpioPriv; + IRQn_Type IRQn; + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + + if (port == GPIO_PORT_A) { + gpioPriv = gGPIOAPrivate; + IRQn = GPIOA_IRQn; + } else if (port == GPIO_PORT_B) { + gpioPriv = gGPIOBPrivate; + IRQn = GPIOB_IRQn; + } else { + HAL_ERR("Invalid port %d for IRQ\n", port); + return; + } + gpiox = GPIO_GetIRQInstance(port); + + HAL_NVIC_DisableIRQ(IRQn); + GPIO_DisableIRQ(gpiox, pin); + if (GPIO_IsPendingIRQ(gpiox, pin)) { + GPIO_ClearPendingIRQ(gpiox, pin); + } + + gpioPriv[pin].callback = NULL; + gpioPriv[pin].arg = NULL; + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief Initialize the specified GPIO + * @param[in] port GPIO port + * @param[in] pin GPIO pin number + * @param[in] param Pointer to GPIO_InitParam structure + * @return None + */ +void HAL_GPIO_Init(GPIO_Port port, GPIO_Pin pin, const GPIO_InitParam *param) +{ + uint32_t regIdx; + uint32_t bitShift; + GPIO_CTRL_T *gpiox; + unsigned long flags; + +#if 0 + HAL_ASSERT_PARAM(pin <= GPIO_PIN_MAX); + HAL_ASSERT_PARAM(param->mode <= GPIO_CTRL_MODE_MAX); + HAL_ASSERT_PARAM(param->driving <= GPIO_CTRL_DRIVING_MAX); + HAL_ASSERT_PARAM(param->pull <= GPIO_CTRL_PULL_MAX); +#endif + + flags = HAL_EnterCriticalSection(); + + if (gGPIOUsedCnt++ == 0) { + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_GPIO); + } + + gpiox = GPIO_GetCtrlInstance(port); + + /* set working mode (function) */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_MODE_BITS); + HAL_MODIFY_REG(gpiox->MODE[regIdx], + GPIO_CTRL_MODE_MASK << bitShift, + (param->mode & GPIO_CTRL_MODE_MASK) << bitShift); + + /* set driving */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_DRIVING_BITS); + HAL_MODIFY_REG(gpiox->DRIVING[regIdx], + GPIO_CTRL_DRIVING_MASK << bitShift, + (param->driving & GPIO_CTRL_DRIVING_MASK) << bitShift); + + /* set pull */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_PULL_BITS); + HAL_MODIFY_REG(gpiox->PULL[regIdx], + GPIO_CTRL_PULL_MASK << bitShift, + (param->pull & GPIO_CTRL_PULL_MASK) << bitShift); + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief Deinitialize the specified GPIO + * @param[in] port GPIO port + * @param[in] pin GPIO pin number + * @return None + * @note After deinitialization, the GPIO is in its reset state: + * (GPIOx_Pn_F7_DISABLE, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE). + */ +void HAL_GPIO_DeInit(GPIO_Port port, GPIO_Pin pin) +{ + uint32_t regIdx; + uint32_t bitShift; + GPIO_CTRL_T *gpiox; + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + + gpiox = GPIO_GetCtrlInstance(port); + + /* set working mode (function) to disable */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_MODE_BITS); + HAL_MODIFY_REG(gpiox->MODE[regIdx], + GPIO_CTRL_MODE_MASK << bitShift, + (GPIOx_Pn_F7_DISABLE & GPIO_CTRL_MODE_MASK) << bitShift); + + /* set driving to default value (GPIO_DRIVING_LEVEL_1) */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_DRIVING_BITS); + HAL_MODIFY_REG(gpiox->DRIVING[regIdx], + GPIO_CTRL_DRIVING_MASK << bitShift, + (GPIO_DRIVING_LEVEL_1 & GPIO_CTRL_DRIVING_MASK) << bitShift); + + /* set pull to default value (GPIO_PULL_NONE) */ + GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_PULL_BITS); + HAL_MODIFY_REG(gpiox->PULL[regIdx], + GPIO_CTRL_PULL_MASK << bitShift, + (GPIO_PULL_NONE & GPIO_CTRL_PULL_MASK) << bitShift); + + if ((gGPIOUsedCnt > 0) && (--gGPIOUsedCnt == 0)) { + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_GPIO); + } + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief Set the state of the specified GPIO + * @param[in] port GPIO port + * @param[in] pin GPIO pin number + * @param[in] state GPIO pin state + * @return None + */ +void HAL_GPIO_WritePin(GPIO_Port port, GPIO_Pin pin, GPIO_PinState state) +{ + GPIO_CTRL_T *gpiox; + unsigned long flags; + + gpiox = GPIO_GetCtrlInstance(port); + + flags = HAL_EnterCriticalSection(); + + if (state == GPIO_PIN_LOW) + HAL_CLR_BIT(gpiox->DATA, HAL_BIT(pin)); + else + HAL_SET_BIT(gpiox->DATA, HAL_BIT(pin)); + + HAL_ExitCriticalSection(flags); +} + +/** + * @brief Get the state of the specified GPIO + * @param[in] port GPIO port + * @param[in] pin GPIO pin number + * @return GPIO pin state + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_Port port, GPIO_Pin pin) +{ + GPIO_CTRL_T *gpiox; + + gpiox = GPIO_GetCtrlInstance(port); + return (GPIO_PinState)HAL_GET_BIT_VAL(gpiox->DATA, pin, 1); +} + +/** + * @brief Set the state of the specified GPIO port + * @param[in] port GPIO port + * @param[in] portMask GPIO port state, bit mask of all pins + * @return None + */ +void HAL_GPIO_WritePort(GPIO_Port port, uint32_t portMask) +{ + GPIO_CTRL_T *gpiox; + + gpiox = GPIO_GetCtrlInstance(port); + gpiox->DATA = portMask; +} + +/** + * @brief Get the state of the specified GPIO port + * @param[in] port GPIO port + * @return GPIO port state, bit mask of all pins + */ +uint32_t HAL_GPIO_ReadPort(GPIO_Port port) +{ + GPIO_CTRL_T *gpiox; + + gpiox = GPIO_GetCtrlInstance(port); + return gpiox->DATA; +} + +/** + * @brief Configure the GPIOs pinmux by the specified parameters + * @param[in] param Pointer to the array of GPIO_PinMuxParam structure, one + * array element for one GPIO pinmux + * @param[in] count Elements number of the GPIO pinmux parameters array + * @return None + */ +void HAL_GPIO_PinMuxConfig(const GPIO_PinMuxParam *param, uint32_t count) +{ + uint32_t i; + + for (i = 0; i < count; ++i) { + HAL_GPIO_Init(param[i].port, param[i].pin, ¶m[i].config); + } +} + +/** + * @brief Deconfigure the GPIOs pinmux by the specified parameters + * @param[in] param Pointer to the array of GPIO_PinMuxParam structure, one + * array element for one GPIO pinmux, param->config is ignored. + * @param[in] count Elements number of the GPIO pinmux parameters array + * @return None + */ +void HAL_GPIO_PinMuxDeConfig(const GPIO_PinMuxParam *param, uint32_t count) +{ + uint32_t i; + + for (i = 0; i < count; ++i) { + HAL_GPIO_DeInit(param[i].port, param[i].pin); + } +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_i2c.c b/platform/mcu/xr871/src/driver/chip/hal_i2c.c new file mode 100644 index 0000000000..37b36837a0 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_i2c.c @@ -0,0 +1,909 @@ +/** + * @file hal_i2c.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_i2c.h" +#include "hal_base.h" +#include "pm/pm.h" + +#define I2C_MTX_TIMEOUT_MS (5000) +#define I2C_SEM_TIMEOUT_MS (3000) + +/* I2C_Private.ctrl */ +#define I2C_INIT_STATE_BIT HAL_BIT(0) +#define I2C_7BIT_ADDR_BIT HAL_BIT(1) +#define I2C_READ_MODE_BIT HAL_BIT(2) +#define I2C_SCCB_MODE_BIT HAL_BIT(3) +#define I2C_MEM_MODE_BIT HAL_BIT(4) +#define I2C_RESTART_BIT HAL_BIT(5) + +typedef struct { + uint8_t ctrl; + + uint8_t memAddr; + uint16_t devAddr; + uint8_t *buf; + int32_t size; + + HAL_Mutex mtx; + HAL_Semaphore sem; +} I2C_Private; + +static I2C_Private gI2CPrivate[I2C_NUM]; +static I2C_T *gI2CInstance[I2C_NUM] = {I2C0, I2C1}; + +#define I2C_ASSERT_ID(i2cID) HAL_ASSERT_PARAM((i2cID) < I2C_NUM) + +#ifdef CONFIG_PM +static I2C_InitParam hal_i2c_param[I2C_NUM]; +static uint8_t hal_i2c_suspending = 0; + +static int i2c_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + I2C_ID i2cID = (I2C_ID)dev->platform_data; + + hal_i2c_suspending |= (1 << i2cID); + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + HAL_I2C_DeInit(i2cID); + break; + default: + break; + } + + return 0; +} + +static int i2c_resume(struct soc_device *dev, enum suspend_state_t state) +{ + I2C_ID i2cID = (I2C_ID)dev->platform_data; + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_I2C_Init(i2cID, &hal_i2c_param[i2cID]); + break; + default: + break; + } + + hal_i2c_suspending &= ~(1 << i2cID); + + return 0; +} + +static struct soc_device_driver i2c_drv = { + .name = "i2c", + .suspend = i2c_suspend, + .resume = i2c_resume, +}; + +static struct soc_device i2c_dev[] = { + {.name = "i2c0", .driver = &i2c_drv, .platform_data = (void *)I2C0_ID,}, + {.name = "i2c1", .driver = &i2c_drv, .platform_data = (void *)I2C1_ID,}, +}; + +#define I2C_DEV(id) (&i2c_dev[id]) +#else +#define I2C_DEV(id) NULL +#endif + +__STATIC_INLINE I2C_T *I2C_GetI2CInstance(I2C_ID i2cID) +{ + return gI2CInstance[i2cID]; +} + +__STATIC_INLINE I2C_Private *I2C_GetI2CPriv(I2C_ID i2cID) +{ + return &gI2CPrivate[i2cID]; +} + +__STATIC_INLINE void I2C_SetInitStateBit(I2C_Private *priv) +{ + HAL_SET_BIT(priv->ctrl, I2C_INIT_STATE_BIT); +} + +__STATIC_INLINE void I2C_ClrInitStateBit(I2C_Private *priv) +{ + HAL_CLR_BIT(priv->ctrl, I2C_INIT_STATE_BIT); +} + +__STATIC_INLINE uint8_t I2C_IsInitState(I2C_Private *priv) +{ + return !!HAL_GET_BIT(priv->ctrl, I2C_INIT_STATE_BIT); +} + +__STATIC_INLINE void I2C_Set7BitAddrMode(I2C_Private *priv) +{ + HAL_SET_BIT(priv->ctrl, I2C_7BIT_ADDR_BIT); +} + +__STATIC_INLINE void I2C_Set10BitAddrMode(I2C_Private *priv) +{ + HAL_CLR_BIT(priv->ctrl, I2C_7BIT_ADDR_BIT); +} + +__STATIC_INLINE uint8_t I2C_Is7BitAddrMode(I2C_Private *priv) +{ + return !!HAL_GET_BIT(priv->ctrl, I2C_7BIT_ADDR_BIT); +} + +__STATIC_INLINE void I2C_SetReadMode(I2C_Private *priv) +{ + HAL_SET_BIT(priv->ctrl, I2C_READ_MODE_BIT); +} + +__STATIC_INLINE void I2C_SetWriteMode(I2C_Private *priv) +{ + HAL_CLR_BIT(priv->ctrl, I2C_READ_MODE_BIT); +} + +__STATIC_INLINE uint8_t I2C_IsReadMode(I2C_Private *priv) +{ + return !!HAL_GET_BIT(priv->ctrl, I2C_READ_MODE_BIT); +} + +__STATIC_INLINE void I2C_SetSCCBMode(I2C_Private *priv) +{ + HAL_SET_BIT(priv->ctrl, I2C_SCCB_MODE_BIT); +} + +__STATIC_INLINE void I2C_ClrSCCBMode(I2C_Private *priv) +{ + HAL_CLR_BIT(priv->ctrl, I2C_SCCB_MODE_BIT); +} + +__STATIC_INLINE uint8_t I2C_IsSCCBMode(I2C_Private *priv) +{ + return !!HAL_GET_BIT(priv->ctrl, I2C_SCCB_MODE_BIT); +} + +__STATIC_INLINE void I2C_SetMemMode(I2C_Private *priv) +{ + HAL_SET_BIT(priv->ctrl, I2C_MEM_MODE_BIT); +} + +__STATIC_INLINE void I2C_ClrMemMode(I2C_Private *priv) +{ + HAL_CLR_BIT(priv->ctrl, I2C_MEM_MODE_BIT); +} + +__STATIC_INLINE uint8_t I2C_IsMemMode(I2C_Private *priv) +{ + return !!HAL_GET_BIT(priv->ctrl, I2C_MEM_MODE_BIT); +} + +__STATIC_INLINE void I2C_SetRestartBit(I2C_Private *priv) +{ + HAL_SET_BIT(priv->ctrl, I2C_RESTART_BIT); +} + +__STATIC_INLINE void I2C_ClrRestartBit(I2C_Private *priv) +{ + HAL_CLR_BIT(priv->ctrl, I2C_RESTART_BIT); +} + +__STATIC_INLINE uint8_t I2C_IsRestart(I2C_Private *priv) +{ + return !!HAL_GET_BIT(priv->ctrl, I2C_RESTART_BIT); +} + +__STATIC_INLINE uint8_t I2C_Get7BitAddrRd(I2C_Private *priv) +{ + return (uint8_t)((priv->devAddr << 1) | 0x1); +} + +__STATIC_INLINE uint8_t I2C_Get7BitAddrWr(I2C_Private *priv) +{ + return (uint8_t)((priv->devAddr << 1) | 0x0); +} + +__STATIC_INLINE uint8_t I2C_Get10BitAddr1Rd(I2C_Private *priv) +{ + uint8_t tmp = (uint8_t)(priv->devAddr >> 7); + tmp &= ~(0x08U); + tmp |= 0xF1U; + return tmp; +} + +__STATIC_INLINE uint8_t I2C_Get10BitAddr1Wr(I2C_Private *priv) +{ + uint8_t tmp = (uint8_t)(priv->devAddr >> 7); + tmp &= ~(0x09U); + tmp |= 0xF0U; + return tmp; +} + +__STATIC_INLINE uint8_t I2C_Get10BitAddr2(I2C_Private *priv) +{ + return (uint8_t)(HAL_GET_BIT(priv->devAddr, 0xFFU)); +} + +__STATIC_INLINE uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(HAL_GET_BIT(i2c->I2C_DATA, I2C_DATA_MASK)); +} + +__STATIC_INLINE void I2C_PutData(I2C_T *i2c, uint8_t data) +{ + i2c->I2C_DATA = data; +} + +__STATIC_INLINE void I2C_EnableIRQ(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_IRQ_EN_BIT); +} + +__STATIC_INLINE void I2C_DisableIRQ(I2C_T *i2c) +{ + HAL_CLR_BIT(i2c->I2C_CTRL, I2C_WR_CTRL_MASK | I2C_IRQ_EN_BIT); +} + +__STATIC_INLINE void I2C_EnableBus(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_BUS_EN_BIT); +} + +__STATIC_INLINE void I2C_DisableBus(I2C_T *i2c) +{ + HAL_CLR_BIT(i2c->I2C_CTRL, I2C_WR_CTRL_MASK | I2C_BUS_EN_BIT); +} + +__STATIC_INLINE void I2C_SendStart(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_START_BIT); +} + +__STATIC_INLINE uint8_t I2C_GetStartBit(I2C_T *i2c) +{ + return !!HAL_GET_BIT(i2c->I2C_CTRL, I2C_START_BIT); +} + +__STATIC_INLINE void I2C_SendStop(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_STOP_BIT); +} + +__STATIC_INLINE uint8_t I2C_GetStopBit(I2C_T *i2c) +{ + return !!HAL_GET_BIT(i2c->I2C_CTRL, I2C_STOP_BIT); +} + +__STATIC_INLINE void I2C_SendStopStart(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_STOP_BIT | I2C_START_BIT); +} + +__STATIC_INLINE void I2C_ClrIRQFlag(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_IRQ_FLAG_BIT); +} + +__STATIC_INLINE uint8_t I2C_GetIRQFlag(I2C_T *i2c) +{ + return !!HAL_GET_BIT(i2c->I2C_CTRL, I2C_IRQ_FLAG_BIT); +} + +__STATIC_INLINE void I2C_EnableACK(I2C_T *i2c) +{ + HAL_MODIFY_REG(i2c->I2C_CTRL, I2C_WR_CTRL_MASK, I2C_ACK_EN_BIT); +} + +__STATIC_INLINE void I2C_DisableACK(I2C_T *i2c) +{ + HAL_CLR_BIT(i2c->I2C_CTRL, I2C_WR_CTRL_MASK | I2C_ACK_EN_BIT); +} + +__STATIC_INLINE uint32_t I2C_GetIRQStatus(I2C_T *i2c) +{ + return HAL_GET_BIT(i2c->I2C_STATUS, I2C_STATUS_MASK); +} + +__STATIC_INLINE void I2C_SetClockReg(I2C_T *i2c, uint8_t clkM, uint8_t clkN) +{ + HAL_MODIFY_REG(i2c->I2C_CLK_CTRL, I2C_CLK_M_MASK | I2C_CLK_N_MASK, + (clkM << I2C_CLK_M_SHIFT) | (clkN << I2C_CLK_N_SHIFT)); +} + +__STATIC_INLINE void I2C_SetClockFreq(I2C_T *i2c, uint32_t clockFreq) +{ + uint8_t clkM = 0; + uint8_t clkN = 0; + uint8_t pow2N = 1; + + uint32_t APBClkDiv10; + uint32_t div; + uint32_t clockReal; + + APBClkDiv10 = HAL_CCM_BusGetAPBClock() / 10; + div = APBClkDiv10 / clockFreq; + if (div == 0) { + I2C_SetClockReg(i2c, clkM, clkN); + return; + } + + while (clkN <= I2C_CLK_N_MAX) { + clkM = div / pow2N - 1; + while (clkM <= I2C_CLK_M_MAX) { + clockReal = APBClkDiv10 / pow2N / (clkM + 1); + if (clockReal <= clockFreq) { + I2C_SetClockReg(i2c, clkM, clkN); + return; + } else { + clkM++; + } + } + clkN++; + pow2N *= 2; + } +} + +__STATIC_INLINE void I2C_SoftReset(I2C_T *i2c) +{ + HAL_SET_BIT(i2c->I2C_SOFT_RST, I2C_SOFT_RST_BIT); +} + +static void I2C_IRQHandler(I2C_T *i2c, I2C_Private *priv) +{ + uint8_t end = 0; + uint32_t IRQStatus = I2C_GetIRQStatus(i2c); + + HAL_I2C_DBG("IRQ Status: %#x\n", IRQStatus); + + switch (IRQStatus) { + case I2C_START_TRAN: + if (I2C_Is7BitAddrMode(priv)) { + if ((!I2C_IsMemMode(priv)) && (I2C_IsReadMode(priv))) + I2C_PutData(i2c, I2C_Get7BitAddrRd(priv)); + else + I2C_PutData(i2c, I2C_Get7BitAddrWr(priv)); + } else { + if ((!I2C_IsMemMode(priv)) && (I2C_IsReadMode(priv))) + I2C_PutData(i2c, I2C_Get10BitAddr1Rd(priv)); + else + I2C_PutData(i2c, I2C_Get10BitAddr1Wr(priv)); + } + break; + case I2C_RE_START_TRAN: + if (I2C_Is7BitAddrMode(priv)) + I2C_PutData(i2c, I2C_Get7BitAddrRd(priv)); + else + I2C_PutData(i2c, I2C_Get10BitAddr1Rd(priv)); + break; + case I2C_ADDR_WR_TRAN_ACK: + if (I2C_Is7BitAddrMode(priv)) { + if (I2C_IsMemMode(priv)) { + I2C_PutData(i2c, priv->memAddr); + } else { + I2C_PutData(i2c, *priv->buf); + priv->buf++; + priv->size--; + } + } else { + I2C_PutData(i2c, I2C_Get10BitAddr2(priv)); + } + break; + case I2C_ADDR_RD_TRAN_ACK: + if (!I2C_Is7BitAddrMode(priv)) + I2C_PutData(i2c, I2C_Get10BitAddr2(priv)); + if (priv->size == 1) + I2C_DisableACK(i2c); + break; + case I2C_SEC_ADDR_WR_ACK: + if (I2C_IsMemMode(priv)) { + I2C_PutData(i2c, priv->memAddr); + } else { + I2C_PutData(i2c, *priv->buf); + priv->buf++; + priv->size--; + } + break; + case I2C_MASTER_DATA_TRAN_ACK: + if (I2C_IsMemMode(priv) && I2C_IsReadMode(priv)) { + I2C_SendStart(i2c); + I2C_SetRestartBit(priv); + } else { + if (priv->size > 0) { + I2C_PutData(i2c, *priv->buf); + priv->buf++; + priv->size--; + } else { + end = 1; + } + } + break; + case I2C_MASTER_DATA_RECV_ACK: + *priv->buf = I2C_GetData(i2c); + priv->buf++; + priv->size--; + if (priv->size == 1) + I2C_DisableACK(i2c); + break; + case I2C_MASTER_DATA_RECV_NACK: + *priv->buf = I2C_GetData(i2c); + priv->buf++; + priv->size--; + end = 1; + break; + case I2C_ADDR_WR_TRAN_NACK: + HAL_ERR("Invalid IIC address\n"); + end = 1; + break; + case I2C_ADDR_RD_TRAN_NACK: + if (!I2C_IsMemMode(priv)) + HAL_ERR("Invalid IIC address\n"); + else + HAL_ERR("No ACK received after 2nd-address-send\n"); + end = 1; + break; + case I2C_MASTER_DATA_TRAN_NACK: + HAL_ERR("In writing, no ACK received\n"); + end = 1; + break; + default: + end = 1; + break; + } + + if (end) { + I2C_SendStop(i2c); + HAL_SemaphoreRelease(&priv->sem); + } + + I2C_ClrIRQFlag(i2c); + while (I2C_GetIRQFlag(i2c)) + ; + + return; +} + +static void I2C_SCCBIRQHandler(I2C_T *i2c, I2C_Private *priv) +{ + uint8_t end = 0; + uint32_t IRQStatus = I2C_GetIRQStatus(i2c); + + switch (IRQStatus) { + case I2C_START_TRAN: + if (I2C_IsRestart(priv)) + I2C_PutData(i2c, I2C_Get7BitAddrRd(priv)); + else + I2C_PutData(i2c, I2C_Get7BitAddrWr(priv)); + break; + case I2C_ADDR_WR_TRAN_ACK: + case I2C_ADDR_WR_TRAN_NACK: + I2C_PutData(i2c, priv->memAddr); + break; + case I2C_ADDR_RD_TRAN_ACK: + case I2C_ADDR_RD_TRAN_NACK: + I2C_DisableACK(i2c); + break; + case I2C_MASTER_DATA_TRAN_ACK: + case I2C_MASTER_DATA_TRAN_NACK: + if (I2C_IsReadMode(priv)) { + I2C_SendStopStart(i2c); + I2C_SetRestartBit(priv); + } else { + if (priv->size > 0) { + I2C_PutData(i2c, *priv->buf); + priv->buf++; + priv->size--; + } else { + end = 1; + } + } + break; + case I2C_MASTER_DATA_RECV_ACK: + case I2C_MASTER_DATA_RECV_NACK: + *priv->buf = I2C_GetData(i2c); + priv->buf++; + priv->size--; + end = 1; + break; + default: + end = 1; + break; + } + + if (end) { + I2C_SendStop(i2c); + HAL_SemaphoreRelease(&priv->sem); + } + + I2C_ClrIRQFlag(i2c); + while (I2C_GetIRQFlag(i2c)) + ; + + return; +} + +void TWI0_IRQHandler(void) +{ + if (I2C_IsSCCBMode(&gI2CPrivate[I2C0_ID])) + I2C_SCCBIRQHandler(I2C0, &gI2CPrivate[I2C0_ID]); + else + I2C_IRQHandler(I2C0, &gI2CPrivate[I2C0_ID]); +} + +void TWI1_IRQHandler(void) +{ + if (I2C_IsSCCBMode(&gI2CPrivate[I2C1_ID])) + I2C_SCCBIRQHandler(I2C1, &gI2CPrivate[I2C1_ID]); + else + I2C_IRQHandler(I2C1, &gI2CPrivate[I2C1_ID]); +} + +/** + * @brief Initialize the I2C according to the specified parameters + * @param[in] i2cID ID of the specified I2C + * @param[in] initParam Pointer to I2C_InitParam structure + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_I2C_Init(I2C_ID i2cID, const I2C_InitParam *initParam) +{ + I2C_T *i2c; + I2C_Private *priv; + CCM_BusPeriphBit ccmPeriphBit; + IRQn_Type IRQn; + unsigned long flags; + + I2C_ASSERT_ID(i2cID); + + if (initParam->clockFreq == 0) { + HAL_ERR("clock frequency is zero.\n"); + return HAL_ERROR; + } + + flags = HAL_EnterCriticalSection(); + priv = I2C_GetI2CPriv(i2cID); + if (!I2C_IsInitState(priv)) + I2C_SetInitStateBit(priv); + else + priv = NULL; + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("i2c %d already inited\n", i2cID); + return HAL_BUSY; + } +#ifdef CONFIG_PM + if (!(hal_i2c_suspending & (1 << i2cID))) { + pm_register_ops(I2C_DEV(i2cID)); + HAL_Memcpy(&hal_i2c_param[i2cID], initParam, sizeof(I2C_InitParam)); + } +#endif + i2c = I2C_GetI2CInstance(i2cID); + + if (initParam->addrMode == I2C_ADDR_MODE_7BIT) + I2C_Set7BitAddrMode(priv); + else + I2C_Set10BitAddrMode(priv); + + priv->memAddr = 0; + priv->devAddr = 0; + priv->buf = NULL; + priv->size = 0; + HAL_MutexInit(&priv->mtx); + HAL_SemaphoreInitBinary(&priv->sem); + + /* config pinmux */ + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_I2C, i2cID), 0); + + /* enable i2c clock and release reset */ + ccmPeriphBit = (i2cID == I2C0_ID ? CCM_BUS_PERIPH_BIT_I2C0 : + CCM_BUS_PERIPH_BIT_I2C1); + HAL_CCM_BusEnablePeriphClock(ccmPeriphBit); + HAL_CCM_BusReleasePeriphReset(ccmPeriphBit); + + I2C_DisableIRQ(i2c); + I2C_DisableBus(i2c); + I2C_SetClockFreq(i2c, initParam->clockFreq); + I2C_EnableBus(i2c); + + /* enable NVIC IRQ */ + IRQn = (i2cID == I2C0_ID) ? I2C0_IRQn : I2C1_IRQn; + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(IRQn); + + return HAL_OK; +} + +/** + * @brief DeInitialize the specified I2C + * @param[in] i2cID ID of the specified I2C + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_I2C_DeInit(I2C_ID i2cID) +{ + I2C_T *i2c; + I2C_Private *priv; + CCM_BusPeriphBit ccmPeriphBit; + unsigned long flags; + + I2C_ASSERT_ID(i2cID); + +#ifdef CONFIG_PM + if (!(hal_i2c_suspending & (1 << i2cID))) { + pm_unregister_ops(I2C_DEV(i2cID)); + } +#endif + + i2c = I2C_GetI2CInstance(i2cID); + priv = I2C_GetI2CPriv(i2cID); + + HAL_NVIC_DisableIRQ((i2cID == I2C0_ID) ? I2C0_IRQn : I2C1_IRQn); + + I2C_DisableBus(i2c); + + /* disable i2c clock and force reset */ + ccmPeriphBit = (i2cID == I2C0_ID ? CCM_BUS_PERIPH_BIT_I2C0 : + CCM_BUS_PERIPH_BIT_I2C1); + HAL_CCM_BusForcePeriphReset(ccmPeriphBit); + HAL_CCM_BusDisablePeriphClock(ccmPeriphBit); + + /* De-config pinmux */ + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_I2C, i2cID), 0); + + HAL_MutexDeinit(&priv->mtx); + HAL_SemaphoreDeinit(&priv->sem); + + flags = HAL_EnterCriticalSection(); + I2C_ClrInitStateBit(priv); + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + +static int32_t I2C_Master_common(I2C_ID i2cID, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size) +{ + I2C_T *i2c; + I2C_Private *priv; + + I2C_ASSERT_ID(i2cID); + + if (buf == NULL || size <= 0) { + HAL_ERR("buf %p, size %d\n", buf, size); + return -1; + } + + i2c = I2C_GetI2CInstance(i2cID); + priv = I2C_GetI2CPriv(i2cID); + + priv->devAddr = devAddr; + priv->memAddr = memAddr; + priv->buf = buf; + priv->size = size; + + I2C_EnableACK(i2c); + I2C_EnableIRQ(i2c); + I2C_SendStart(i2c); + + if (HAL_SemaphoreWait(&priv->sem, I2C_SEM_TIMEOUT_MS) != HAL_OK) + HAL_WRN("I2C wait semaphore failed, i2c ID %d\n", i2cID); + + while (I2C_GetStopBit(i2c)) + ; + I2C_DisableIRQ(i2c); + I2C_DisableACK(i2c); + + size -= priv->size; + priv->devAddr = 0; + priv->memAddr = 0; + priv->buf = NULL; + priv->size = 0; + + return size; +} + +/** + * @brief Transmit an amount of data in interrupt mode + * @param[in] i2cID ID of the specified I2C + * @param[in] devAddr Device address + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be transmitted + * @return Number of bytes transmitted, -1 on error + */ +int32_t HAL_I2C_Master_Transmit_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t *buf, int32_t size) +{ + I2C_Private *priv = I2C_GetI2CPriv(i2cID); + + if (HAL_MutexLock(&priv->mtx, I2C_MTX_TIMEOUT_MS) != HAL_OK) { + HAL_WRN("I2C wait mutex failed, i2c ID %d\n", i2cID); + return 0; + } + + I2C_SetWriteMode(priv); + I2C_ClrSCCBMode(priv); + I2C_ClrMemMode(priv); + I2C_ClrRestartBit(priv); + + int32_t ret = I2C_Master_common(i2cID, devAddr, 0, buf, size); + + HAL_MutexUnlock(&priv->mtx); + + return ret; +} + +/** + * @brief Receive an amount of data in interrupt mode + * @param[in] i2cID ID of the specified I2C + * @param[in] devAddr Device address + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be received + * @return Number of bytes received, -1 on error + */ +int32_t HAL_I2C_Master_Receive_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t *buf, int32_t size) +{ + I2C_Private *priv = I2C_GetI2CPriv(i2cID); + + if (HAL_MutexLock(&priv->mtx, I2C_MTX_TIMEOUT_MS) != HAL_OK) { + HAL_WRN("I2C wait mutex failed, i2c ID %d\n", i2cID); + return 0; + } + + I2C_SetReadMode(priv); + I2C_ClrSCCBMode(priv); + I2C_ClrMemMode(priv); + I2C_ClrRestartBit(priv); + + int32_t ret = I2C_Master_common(i2cID, devAddr, 0, buf, size); + + HAL_MutexUnlock(&priv->mtx); + + return ret; +} + +/** + * @brief Transmit an amount of data to specified memory or register of the + * slave device in interrupt mode + * @param[in] i2cID ID of the specified I2C + * @param[in] devAddr Device address + * @param[in] memAddr Memory or register address + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be transmitted + * @return Number of bytes transmitted, -1 on error + */ +int32_t HAL_I2C_Master_Transmit_Mem_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size) +{ + I2C_Private *priv = I2C_GetI2CPriv(i2cID); + + if (HAL_MutexLock(&priv->mtx, I2C_MTX_TIMEOUT_MS) != HAL_OK) { + HAL_WRN("I2C wait mutex failed, i2c ID %d\n", i2cID); + return 0; + } + + I2C_SetWriteMode(priv); + I2C_ClrSCCBMode(priv); + I2C_SetMemMode(priv); + I2C_ClrRestartBit(priv); + + int32_t ret = I2C_Master_common(i2cID, devAddr, memAddr, buf, size); + + HAL_MutexUnlock(&priv->mtx); + + return ret; +} + +/** + * @brief Receive an amount of data from specified memory or register of the + * slave device in interrupt mode + * @param[in] i2cID ID of the specified I2C + * @param[in] devAddr Device address + * @param[in] memAddr Memory or register address + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be received + * @return Number of bytes received, -1 on error + */ +int32_t HAL_I2C_Master_Receive_Mem_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t memAddr, uint8_t *buf, int32_t size) +{ + I2C_Private *priv = I2C_GetI2CPriv(i2cID); + + if (HAL_MutexLock(&priv->mtx, I2C_MTX_TIMEOUT_MS) != HAL_OK) { + HAL_WRN("I2C wait mutex failed, i2c ID %d\n", i2cID); + return 0; + } + + I2C_SetReadMode(priv); + I2C_ClrSCCBMode(priv); + I2C_SetMemMode(priv); + I2C_ClrRestartBit(priv); + + int32_t ret = I2C_Master_common(i2cID, devAddr, memAddr, buf, size); + + HAL_MutexUnlock(&priv->mtx); + + return ret; +} + +/** + * @brief Transmit one byte data through SCCB protocol in interrupt mode + * @param[in] i2cID ID of the specified I2C + * @param[in] devAddr Device address + * @param[in] subAddr Sub-address + * @param[in] buf Pointer to the data buffer + * @return Number of bytes transmitted, -1 on error + */ +int32_t HAL_I2C_SCCB_Master_Transmit_IT(I2C_ID i2cID, uint8_t devAddr, uint8_t subAddr, uint8_t *buf) +{ + I2C_Private *priv = I2C_GetI2CPriv(i2cID); + + if (HAL_MutexLock(&priv->mtx, I2C_MTX_TIMEOUT_MS) != HAL_OK) { + HAL_WRN("I2C wait mutex failed, i2c ID %d\n", i2cID); + return 0; + } + + I2C_SetWriteMode(priv); + I2C_SetSCCBMode(priv); + I2C_ClrMemMode(priv); + I2C_ClrRestartBit(priv); + + int32_t ret = I2C_Master_common(i2cID, devAddr, subAddr, buf, 0x01); + + HAL_MutexUnlock(&priv->mtx); + + return ret; +} + +/** + * @brief Receive one byte data through SCCB protocol in interrupt mode + * @param[in] i2cID ID of the specified I2C + * @param[in] devAddr Device address + * @param[in] subAddr Sub-address + * @param[in] buf Pointer to the data buffer + * @return Number of bytes received, -1 on error + */ +int32_t HAL_I2C_SCCB_Master_Receive_IT(I2C_ID i2cID, uint8_t devAddr, uint8_t subAddr, uint8_t *buf) +{ + I2C_Private *priv = I2C_GetI2CPriv(i2cID); + + if (HAL_MutexLock(&priv->mtx, I2C_MTX_TIMEOUT_MS) != HAL_OK) { + HAL_WRN("I2C wait mutex failed, i2c ID %d\n", i2cID); + return 0; + } + + I2C_SetReadMode(priv); + I2C_SetSCCBMode(priv); + I2C_ClrMemMode(priv); + I2C_ClrRestartBit(priv); + + int32_t ret = I2C_Master_common(i2cID, devAddr, subAddr, buf, 0x01); + + HAL_MutexUnlock(&priv->mtx); + + return ret; +} + diff --git a/platform/mcu/xr871/src/driver/chip/hal_i2s.c b/platform/mcu/xr871/src/driver/chip/hal_i2s.c new file mode 100644 index 0000000000..716d80574f --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_i2s.c @@ -0,0 +1,1353 @@ +/** + * @file hal_i2s.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_dma.h" +#include "driver/chip/hal_i2s.h" +#include "hal_base.h" +#include "sys/io.h" +#include "pm/pm.h" + +#define I2D_DBG_ON 0 + +#if (I2D_DBG_ON == 1) +#define I2S_DEBUG(fmt, arg...) HAL_LOG(I2D_DBG_ON, "[I2S] "fmt, ##arg) +#else +#define I2S_DEBUG(fmt, arg...) +#endif +#define I2S_ERROR(fmt, arg...) HAL_LOG(1, "[I2S] "fmt, ##arg) + +typedef struct { + volatile bool isHwInit; + volatile bool txRunning; + volatile bool rxRunning; + + uint8_t *txBuf; + uint8_t *rxBuf; + uint8_t *readPointer; + uint8_t *writePointer; + uint32_t rxLength; + uint32_t txLength; + + DMA_Channel txDMAChan; + DMA_Channel rxDMAChan; + I2S_HWParam *hwParam; + I2S_DataParam pdataParam; + I2S_DataParam cdataParam; + volatile uint32_t txHalfCallCount; + volatile uint32_t rxHalfCallCount; + volatile uint32_t txEndCallCount; + volatile uint32_t rxEndCallCount; + uint8_t *txDmaPointer; + uint8_t *rxDmaPointer; + + HAL_Semaphore txReady; + HAL_Semaphore rxReady; + bool isTxSemaphore; + bool isRxSemaphore; + bool isTxInitiate; + bool isRxInitiate; + + HAL_Mutex devSetLock; + HAL_Mutex devTriggerLock; + + uint32_t audioPllParam; + uint32_t audioPllPatParam; +} I2S_Private; + +typedef struct { + uint32_t hosc; + uint32_t audio; + uint32_t pllParam; + uint32_t pllPatParam; +} HOSC_I2S_Type; + +typedef enum { + I2S_PLL_24M = 0U, + I2S_PLL_22M = 1U, +} I2S_PLLMode; + +typedef struct { + uint8_t clkDiv; + I2S_BCLKDIV bregVal; + I2S_MCLKDIV mregVal; +} CLK_DIVRegval; + +#define AUDIO_PLL_SRC (CCM_DAUDIO_MCLK_SRC_1X) +#define AUDIO_PLL_24 (24576000) +#define AUDIO_PLL_22 (22579200) +#define AUDIO_DEVICE_PLL AUDIO_PLL_22 + +#define I2S_MEMCPY memcpy +#define I2S_MALLOC malloc +#define I2S_FREE free +#define I2S_MEMSET memset + +#define UNDERRUN_THRESHOLD 3 +#define OVERRUN_THRESHOLD 3 + +#ifdef RESERVERD_MEMORY_FOR_I2S_TX +static uint8_t I2STX_BUF[I2S_BUF_LENGTH]; +#endif +#ifdef RESERVERD_MEMORY_FOR_I2S_RX +static uint8_t I2SRX_BUF[I2S_BUF_LENGTH]; +#endif + +void HAL_I2S_Trigger(bool enable,I2S_StreamDir dir); +static I2S_Private gI2sPrivate; +static uint32_t I2S_BUF_LENGTH = 0; + +/* + *default hw configuration + */ +static I2S_HWParam gHwParam = { + 0, /*0:I2S,1:PCM*/ + DAIFMT_CBS_CFS, + DAIFMT_I2S, + DAIFMT_NB_NF, + 32, /*16,32,64,128,256*/ + I2S_SHORT_FRAME, + I2S_TX_MSB_FIRST, + I2S_RX_MSB_FIRST, + 0x40, + 0xF, + {AUDIO_DEVICE_PLL,1}, +}; + +static CLK_DIVRegval DivRegval[] = { + {1, I2S_BCLKDIV_1, I2S_MCLKDIV_1}, + {2, I2S_BCLKDIV_2, I2S_MCLKDIV_2}, + {4, I2S_BCLKDIV_4, I2S_MCLKDIV_4}, + {6, I2S_BCLKDIV_6, I2S_MCLKDIV_6}, + {8, I2S_BCLKDIV_8, I2S_MCLKDIV_8}, + {12, I2S_BCLKDIV_12, I2S_MCLKDIV_12}, + {16, I2S_BCLKDIV_16, I2S_MCLKDIV_16}, + {24, I2S_BCLKDIV_24, I2S_MCLKDIV_24}, + {32, I2S_BCLKDIV_32, I2S_MCLKDIV_32}, + {48, I2S_BCLKDIV_48, I2S_MCLKDIV_48}, + {64, I2S_BCLKDIV_64, I2S_MCLKDIV_64}, + {96, I2S_BCLKDIV_96, I2S_MCLKDIV_96}, + {128, I2S_BCLKDIV_128, I2S_MCLKDIV_128}, + {176, I2S_BCLKDIV_176, I2S_MCLKDIV_176}, + {192, I2S_BCLKDIV_192, I2S_MCLKDIV_192}, + {} +}; + +static const HOSC_I2S_Type i2s_hosc_aud_type[] = { + {HOSC_CLOCK_26M, I2S_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC26M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC26M}, + {HOSC_CLOCK_26M, I2S_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC26M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC26M}, + {HOSC_CLOCK_24M, I2S_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC24M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC24M}, + {HOSC_CLOCK_24M, I2S_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC24M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC24M}, + {HOSC_CLOCK_40M, I2S_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC40M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC40M}, + {HOSC_CLOCK_40M, I2S_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC40M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC40M}, + {HOSC_CLOCK_52M, I2S_PLL_24M, PRCM_AUD_PLL24M_PARAM_HOSC52M, PRCM_AUD_PLL24M_PAT_PARAM_HOSC52M}, + {HOSC_CLOCK_52M, I2S_PLL_22M, PRCM_AUD_PLL22M_PARAM_HOSC52M, PRCM_AUD_PLL22M_PAT_PARAM_HOSC52M}, +}; + +/** + * @internal + * @brief Set i2s clock frequency + * @pll I2S clock identifier + * This parameter can be one of the following values: + * @arg @ref I2S_PLL_22M + * @arg @ref I2S_PLL_24M + * @retval return 0 means success otherwise fail + */ +uint32_t I2S_PLLAUDIO_Update(I2S_PLLMode pll) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + + if (pll != I2S_PLL_24M && pll != I2S_PLL_22M) + return -1; + + uint32_t hoscClock = HAL_PRCM_GetHFClock(); + + int i = 0; + for (i = 0; i < ARRAY_SIZE(i2s_hosc_aud_type); i++) { + if ((i2s_hosc_aud_type[i].hosc == hoscClock) && (i2s_hosc_aud_type[i].audio == pll)) { + i2sPrivate->audioPllParam = i2s_hosc_aud_type[i].pllParam; + i2sPrivate->audioPllPatParam = i2s_hosc_aud_type[i].pllPatParam; + break; + } + } + if (i == ARRAY_SIZE(i2s_hosc_aud_type)) { + I2S_ERROR("Update audio pll failed....\n"); + return -1; + } + return 0; +} + +/** + * @internal + * @brief Enable/disable I2S tx + * @retval None + */ +static void I2S_DisableTx() +{ + HAL_CLR_BIT(I2S->DA_CTL, I2S_TX_EN_BIT); +} + +static void I2S_EnableTx() +{ + HAL_SET_BIT(I2S->DA_CTL, I2S_TX_EN_BIT); +} + +/** + * @internal + * @brief Enable/disable I2S rx + * @retval None + */ +static void I2S_DisableRx() +{ + HAL_CLR_BIT(I2S->DA_CTL, I2S_RX_EN_BIT); +} + +static void I2S_EnableRx() +{ + HAL_SET_BIT(I2S->DA_CTL, I2S_RX_EN_BIT); +} + +/** + * @internal + * @brief set the i2s module clock frequency for a given peripheral clk + * @param isEnable: flag for i2s mclk output + * @param clkSource: Peripheral clock freq + * @param pll: the freq of mclk + * @retval HAL status + */ +static HAL_Status I2S_SET_Mclk(uint32_t isEnable, uint32_t clkSource, uint32_t pll) +{ + if (isEnable == 0) { + HAL_CLR_BIT(I2S->DA_CLKD, I2S_MCLK_OUT_EN_BIT); + return HAL_OK; + } + uint32_t mclkDiv = pll / clkSource; + CLK_DIVRegval *divRegval = DivRegval; + + do { + if (divRegval->clkDiv == mclkDiv) { + HAL_MODIFY_REG(I2S->DA_CLKD, I2S_MCLKDIV_MASK, divRegval->mregVal); + break; + } + divRegval++; + } while (divRegval->mregVal < I2S_MCLKDIV_192); + HAL_SET_BIT(I2S->DA_CLKD, I2S_MCLK_OUT_EN_BIT); + return HAL_OK; +} + +/** + * @internal + * @brief set the Sample Resolution + * @param param: pointer to a I2S_DataParam structure that contains + * data format information + * @retval HAL status + */ +static HAL_Status I2S_SET_SampleResolution(I2S_DataParam *param) +{ + if (!param) + return HAL_INVALID; + I2S_SampleResolution res = param->resolution; + + if (I2S_SR8BIT <= res && res <= I2S_SR32BIT) + HAL_MODIFY_REG(I2S->DA_FMT0, I2S_SR_MASK, res); + else { + I2S_ERROR("Invalid sample resolution (%d) failed\n",res); + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @internal + * @brief set the i2s bclk lrck freq + * @param param: pointer to a I2S_DataParam structure that contains + * data format information + * @param hwParam: pointer to a I2S_HWParam structure that contains + * the configuration for clk/mode/format. + * @retval HAL status + */ +static HAL_Status I2S_SET_ClkDiv(I2S_DataParam *param, I2S_HWParam *hwParam) +{ + int32_t ret = HAL_OK; + if (!param || !hwParam) + return HAL_INVALID; + uint32_t rate = 0; + I2S_SampleRate SR = param->sampleRate; + uint32_t Period = hwParam->lrckPeriod; + uint16_t bclkDiv = 0; + uint32_t audioPll = AUDIO_PLL_24; + + switch (SR) { + case I2S_SR8K:/* 8000Hz */ + rate = 8000; + break; + case I2S_SR12K:/* 12000Hz */ + rate = 12000; + break; + case I2S_SR16K:/* 16000Hz */ + rate = 16000; + break; + case I2S_SR24K:/* 24000Hz */ + rate = 24000; + break; + case I2S_SR32K:/* 32000Hz */ + rate = 32000; + break; + case I2S_SR48K:/* 48000Hz */ + rate = 48000; + break; + case I2S_SR11K: + rate = 11025; + break; + case I2S_SR22K: + rate = 22050; + break; + case I2S_SR44K: + rate = 44100; + break; + default: + I2S_ERROR("Invalid sample rate(%x) failed...\n",rate); + return HAL_INVALID; + } + + I2S_DEBUG("SAMPLE RATE:%d...\n",rate); + if ((rate % 1000) != 0) + audioPll = AUDIO_PLL_22; + + I2S_Private *i2sPrivate = &gI2sPrivate; + + /*set sysclk*/ + if (audioPll == AUDIO_PLL_24) { + I2S_PLLAUDIO_Update(I2S_PLL_24M); + HAL_PRCM_SetAudioPLLParam(i2sPrivate->audioPllParam); + HAL_PRCM_SetAudioPLLPatternParam(i2sPrivate->audioPllPatParam); + } else { + I2S_PLLAUDIO_Update(I2S_PLL_22M); + HAL_PRCM_SetAudioPLLParam(i2sPrivate->audioPllParam); + HAL_PRCM_SetAudioPLLPatternParam(i2sPrivate->audioPllPatParam); + } + + /*config bclk pll div*/ + if (!hwParam->i2sFormat) + bclkDiv = audioPll/(2*Period*rate); + else + bclkDiv = audioPll/(Period*rate); + + CLK_DIVRegval *divRegval = DivRegval; + do { + if (divRegval->clkDiv == bclkDiv) { + HAL_MODIFY_REG(I2S->DA_CLKD, I2S_BCLKDIV_MASK, divRegval->bregVal); + break; + } + divRegval++; + } while (divRegval->bregVal < I2S_BCLKDIV_192); + + return ret; +} + +/** + * @internal + * @brief set the i2s transfer format + * @param param: pointer to a I2S_HWParam structure that contains + * the configuration for clk/mode/format. + * @retval HAL status + */ +static HAL_Status I2S_SET_Format(I2S_HWParam *param) +{ + int32_t ret = HAL_OK; + if (!param) + return HAL_INVALID; + + /* config clk mode*/ + switch (param->clkMode) { + case DAIFMT_CBM_CFM: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_BCLK_OUT_MASK|I2S_LRCK_OUT_MASK|I2S_SDO0_EN_BIT, + I2S_BCLK_INPUT|I2S_LRCK_INPUT|I2S_SDO0_EN_BIT); + + break; + case DAIFMT_CBS_CFS: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_BCLK_OUT_MASK|I2S_LRCK_OUT_MASK|I2S_SDO0_EN_BIT, + I2S_BCLK_OUTPUT|I2S_LRCK_OUTPUT|I2S_SDO0_EN_BIT); + break; + default: + ret = HAL_INVALID; + I2S_ERROR("Invalid DAI format,failed (%d)...\n",param->clkMode); + break; + } + + /* config transfer format */ + switch (param->transferFormat) { + case DAIFMT_I2S: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_MODE_SEL_MASK, I2S_LEFT_MODE); + HAL_MODIFY_REG(I2S->DA_TX0CHSEL, I2S_TXN_OFFSET_MASK, I2S_TX_ONEBCLK_OFFSET); + HAL_MODIFY_REG(I2S->DA_RXCHSEL, I2S_RXN_OFFSET_MASK, I2S_RX_ONEBCLK_OFFSET); + break; + case DAIFMT_RIGHT_J: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_MODE_SEL_MASK, I2S_RIGHT_MODE); + break; + case DAIFMT_LEFT_J: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_MODE_SEL_MASK, I2S_LEFT_MODE); + HAL_MODIFY_REG(I2S->DA_TX0CHSEL, I2S_TXN_OFFSET_MASK, I2S_TX_NO_OFFSET); + HAL_MODIFY_REG(I2S->DA_RXCHSEL, I2S_RXN_OFFSET_MASK, I2S_RX_NO_OFFSET); + break; + case DAIFMT_DSP_A: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_MODE_SEL_MASK, I2S_PCM_MODE); + HAL_MODIFY_REG(I2S->DA_TX0CHSEL, I2S_TXN_OFFSET_MASK, I2S_TX_ONEBCLK_OFFSET); + HAL_MODIFY_REG(I2S->DA_RXCHSEL, I2S_RXN_OFFSET_MASK, I2S_RX_ONEBCLK_OFFSET); + break; + case DAIFMT_DSP_B: + HAL_MODIFY_REG(I2S->DA_CTL, I2S_MODE_SEL_MASK, I2S_PCM_MODE); + HAL_MODIFY_REG(I2S->DA_TX0CHSEL, I2S_TXN_OFFSET_MASK, I2S_TX_NO_OFFSET); + HAL_MODIFY_REG(I2S->DA_RXCHSEL, I2S_RXN_OFFSET_MASK, I2S_RX_NO_OFFSET); + break; + default: + ret = HAL_INVALID; + I2S_ERROR("Invalid transfer format,failed (%d)...\n",param->transferFormat); + break; + } + + /* config signal interval */ + switch (param->signalInterval) { + case DAIFMT_NB_NF: + HAL_CLR_BIT(I2S->DA_FMT0, I2S_LRCK_POLARITY_MASK); + HAL_CLR_BIT(I2S->DA_FMT0, I2S_BCLK_POLARITY_MASK); + break; + case DAIFMT_NB_IF: + HAL_SET_BIT(I2S->DA_FMT0, I2S_LRCK_POLARITY_MASK); + HAL_CLR_BIT(I2S->DA_FMT0, I2S_BCLK_POLARITY_MASK); + break; + case DAIFMT_IB_NF: + HAL_CLR_BIT(I2S->DA_FMT0, I2S_LRCK_POLARITY_MASK); + HAL_SET_BIT(I2S->DA_FMT0, I2S_BCLK_POLARITY_MASK); + break; + case DAIFMT_IB_IF: + HAL_SET_BIT(I2S->DA_FMT0, I2S_LRCK_POLARITY_MASK); + HAL_SET_BIT(I2S->DA_FMT0, I2S_BCLK_POLARITY_MASK); + break; + default: + ret = HAL_INVALID; + I2S_ERROR("Invalid signal Interval,failed (%d)...\n",param->signalInterval); + break; + } + return ret; +} + +/** + * @internal + * @brief set the number channels of i2s transfer + * @param param: pointer to a I2S_DataParam structure that contains + * data format information. + * @retval HAL status + */ +static HAL_Status I2S_SET_Channels(I2S_DataParam *param) +{ + uint8_t channel = 0; + if (!param) + return HAL_INVALID; + + if (param->direction == PLAYBACK) {/*play*/ + if (param->channels < I2S_TX_SLOT_NUM1 || param->channels > I2S_TX_SLOT_NUM8) { + I2S_ERROR("Invalid usr tx channels num,failed (%d)...\n",param->channels); + return HAL_INVALID; + } + HAL_MODIFY_REG(I2S->DA_CHCFG, I2S_TX_SLOT_NUM_MASK, ((param->channels - 1) << I2S_TX_SLOT_NUM_SHIFT)); + HAL_MODIFY_REG(I2S->DA_TX0CHSEL, I2S_TXN_CHANNEL_SEL_MASK, + ((param->channels -1) << I2S_TXN_CHANNEL_SEL_SHIFT)); + HAL_MODIFY_REG(I2S->DA_TX0CHSEL, I2S_TXN_CHANNEL_SLOT_ENABLE_MASK, + I2S_TXN_CHANNEL_SLOTS_ENABLE(param->channels)); + for (channel = 0; channel < param->channels; channel++) { + HAL_MODIFY_REG(I2S->DA_TX0CHMAP, I2S_TXN_CHX_MAP_MASK(channel),I2S_TXN_CHX_MAP(channel)); + } + + } else {/*record*/ + if (param->channels < I2S_RX_SLOT_NUM1 || param->channels > I2S_RX_SLOT_NUM8){ + I2S_ERROR("Invalid usr rx channels num,failed (%d)...\n",param->channels); + return HAL_INVALID; + } + + HAL_MODIFY_REG(I2S->DA_CHCFG, I2S_RX_SLOT_NUM_MASK, ((param->channels - 1) << I2S_RX_SLOT_NUM_SHIFT)); + HAL_MODIFY_REG(I2S->DA_RXCHSEL, I2S_RXN_CHANNEL_SEL_MASK, + ((param->channels - 1) << I2S_RXN_CHANNEL_SEL_SHIFT)); + for (channel = 0; channel < param->channels; channel++) { + HAL_MODIFY_REG(I2S->DA_RXCHMAP, I2S_RXN_CHX_MAP_MASK(channel), I2S_RXN_CHX_MAP(channel)); + } + } + return HAL_OK; +} + +static int I2S_DMA_BUFFER_CHECK_Threshold(uint8_t dir) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + if (dir == 0) { + if (i2sPrivate->txHalfCallCount >= UNDERRUN_THRESHOLD || + i2sPrivate->txEndCallCount >= UNDERRUN_THRESHOLD) { + I2S_ERROR("Tx : underrun and stop dma tx....\n"); + HAL_I2S_Trigger(false,PLAYBACK);/*stop*/ + i2sPrivate->txRunning =false; + i2sPrivate->writePointer = NULL; + i2sPrivate->txHalfCallCount = 0; + i2sPrivate->txEndCallCount = 0; + i2sPrivate->txDmaPointer = NULL; + return -1; + } + } else { + if (i2sPrivate->rxHalfCallCount >= OVERRUN_THRESHOLD || + i2sPrivate->rxEndCallCount >= OVERRUN_THRESHOLD) { + I2S_ERROR("Rx : overrun and stop dma rx....\n"); + HAL_I2S_Trigger(false,RECORD);/*stop*/ + i2sPrivate->rxRunning =false; + i2sPrivate->rxHalfCallCount = 0; + i2sPrivate->rxEndCallCount = 0; + i2sPrivate->readPointer = NULL; + i2sPrivate->rxDmaPointer = NULL; + return -1; + } + } + return 0; +} + +/** + * @internal + * @brief DMA I2S transmit/receive process half complete callback + * @param arg: pointer to a HAL_Semaphore structure that contains + * sem to synchronous data. + * @retval None + */ +static void I2S_DMAHalfCallback(void *arg) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + if (arg == &(i2sPrivate->txReady)) { + i2sPrivate->txHalfCallCount ++; + if (I2S_DMA_BUFFER_CHECK_Threshold(0) != 0) + return; + i2sPrivate->txDmaPointer = i2sPrivate->txBuf + I2S_BUF_LENGTH/2; + if (i2sPrivate->isTxSemaphore) { + i2sPrivate->isTxSemaphore = false; + HAL_SemaphoreRelease((HAL_Semaphore *)arg); + } + + } else { + i2sPrivate->rxHalfCallCount ++; + if (I2S_DMA_BUFFER_CHECK_Threshold(1) != 0) + return; + i2sPrivate->rxDmaPointer = i2sPrivate->rxBuf + I2S_BUF_LENGTH/2; + if (i2sPrivate->isRxSemaphore) { + i2sPrivate->isRxSemaphore = false; + HAL_SemaphoreRelease((HAL_Semaphore *)arg); + } + } +} + +/** + * @internal + * @brief DMA I2S transmit/receive process complete callback + * @param arg: pointer to a HAL_Semaphore structure that contains + * sem to synchronous data. + * @retval None + */ +static void I2S_DMAEndCallback(void *arg) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + if (arg == &(i2sPrivate->txReady)) { + i2sPrivate->txEndCallCount ++; + if (I2S_DMA_BUFFER_CHECK_Threshold(0) != 0) + return; + i2sPrivate->txDmaPointer = i2sPrivate->txBuf; + if (i2sPrivate->isTxSemaphore) { + i2sPrivate->isTxSemaphore = false; + HAL_SemaphoreRelease((HAL_Semaphore *)arg); + } + } else { + i2sPrivate->rxEndCallCount ++; + if (I2S_DMA_BUFFER_CHECK_Threshold(1) != 0) + return; + i2sPrivate->rxDmaPointer = i2sPrivate->rxBuf + I2S_BUF_LENGTH/2; + if (i2sPrivate->isRxSemaphore) { + i2sPrivate->isRxSemaphore = false; + HAL_SemaphoreRelease((HAL_Semaphore *)arg); + } + } +} + +/** + * @internal + * @brief Start the DMA Transfer. + * @param chan: the specified DMA Channel. + * @param srcAddr: The source memory Buffer address + * @param dstAddr: The destination memory Buffer address + * @param datalen: The length of data to be transferred from source to destination + * @retval none + */ +static void I2S_DMAStart(DMA_Channel chan, uint32_t srcAddr, uint32_t dstAddr, uint32_t datalen) +{ + HAL_DMA_Start(chan, srcAddr, dstAddr, datalen); +} + +/** + * @internal + * @brief stop the DMA Transfer. + * @param chan: the specified DMA Channel. + * @retval none + */ +static void I2S_DMAStop(DMA_Channel chan) +{ + HAL_DMA_Stop(chan); +} + +/** + * @internal + * @brief Sets the DMA Transfer parameter. + * @param channel: the specified DMA Channel. + * @param dir: Data transfer direction + * @retval none + */ +static void I2S_DMASet(DMA_Channel channel,I2S_StreamDir dir) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + DMA_ChannelInitParam dmaParam; + HAL_Memset(&dmaParam, 0, sizeof(dmaParam)); + if (dir == PLAYBACK) { + + dmaParam.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_CIRCULAR, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_16BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_DAUDIO, + DMA_DATA_WIDTH_16BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM); + + dmaParam.endArg = &(i2sPrivate->txReady); + dmaParam.halfArg = &(i2sPrivate->txReady); + } else { + + dmaParam.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_CIRCULAR, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_16BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_16BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_DAUDIO); + + dmaParam.endArg = &(i2sPrivate->rxReady); + dmaParam.halfArg = &(i2sPrivate->rxReady); + } + dmaParam.irqType = DMA_IRQ_TYPE_BOTH; + dmaParam.endCallback = I2S_DMAEndCallback; + dmaParam.halfCallback = I2S_DMAHalfCallback; + HAL_DMA_Init(channel, &dmaParam); +} + +/** + * @internal + * @brief Enable or disable the specified i2s tx module. + * @param enable: specifies enable or disable. + * @retval None + */ +static void tx_enable(bool enable) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + /*clear tx tifo*/ + HAL_SET_BIT(I2S->DA_FCTL, I2S_TXFIFO_RESET_BIT); + + if (enable) { + if (i2sPrivate->txDMAChan != DMA_CHANNEL_INVALID) + HAL_SET_BIT(I2S->DA_INT, I2S_TXFIFO_DMA_ITEN_BIT); + } else { + if (i2sPrivate->txDMAChan != DMA_CHANNEL_INVALID) + HAL_CLR_BIT(I2S->DA_INT, I2S_TXFIFO_DMA_ITEN_BIT); + } +} + +/** + * @internal + * @brief Enable or disable the specified i2s rx module. + * @param enable: specifies enable or disable. + * @retval None + */ +static void rx_enable(bool enable) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + /*clear rx tifo*/ + HAL_SET_BIT(I2S->DA_FCTL, I2S_RXFIFO_RESET_BIT); + + if (enable) { + if (i2sPrivate->rxDMAChan != DMA_CHANNEL_INVALID) + HAL_SET_BIT(I2S->DA_INT, I2S_RXFIFO_DMA_ITEN_BIT); + } else { + + if (i2sPrivate->rxDMAChan != DMA_CHANNEL_INVALID) + HAL_CLR_BIT(I2S->DA_INT, I2S_RXFIFO_DMA_ITEN_BIT); + } +} + +/** + * @internal + * @brief Enable or disable the specified i2s module with DMA module. + * @param enable: specifies enable or disable. + * @param dir: the direction of stream. + * @retval None + */ +void HAL_I2S_Trigger(bool enable,I2S_StreamDir dir) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + HAL_MutexLock(&i2sPrivate->devTriggerLock, OS_WAIT_FOREVER); + if (enable) { + if (dir == PLAYBACK) { + /*trigger tx*/ + tx_enable(enable); + + /* start dma*/ + if (i2sPrivate->txDMAChan != DMA_CHANNEL_INVALID) { + I2S_DMAStart(i2sPrivate->txDMAChan, (uint32_t)i2sPrivate->txBuf, + (uint32_t)&(I2S->DA_TXFIFO), i2sPrivate->txLength); + } + i2sPrivate->txRunning = true; + } else { + rx_enable(enable); + if (i2sPrivate->rxDMAChan != DMA_CHANNEL_INVALID) + I2S_DMAStart(i2sPrivate->rxDMAChan, (uint32_t)&(I2S->DA_RXFIFO), + (uint32_t)i2sPrivate->rxBuf, i2sPrivate->rxLength); + i2sPrivate->rxRunning = true; + } + } else { + if (dir == PLAYBACK) { + tx_enable(enable); + if (i2sPrivate->txDMAChan != DMA_CHANNEL_INVALID) + I2S_DMAStop(i2sPrivate->txDMAChan); + i2sPrivate->txRunning = false; + } else { + rx_enable(enable); + if (i2sPrivate->rxDMAChan != DMA_CHANNEL_INVALID) + I2S_DMAStop(i2sPrivate->rxDMAChan); + i2sPrivate->rxRunning = false; + } + } + #if 0 + int i =0 ; + printf("\n"); + for (i = 0; i < 0x68; i = i+4) { + printf("0x%x: 0x%08x",i,(*(uint32_t *)(0x40042c00+i))); + printf("\n"); + } + #endif + HAL_MutexUnlock(&i2sPrivate->devTriggerLock); +} + +/** + * @brief Transmit an amount of data with DMA module + * @param buf: pointer to the Transmit data buffer. + * @param Size: number of data sample to be sent: + * @note if the data size less than half of dmabuf, return HAL_INVALID. when the size + * several times greater than half of dmabuf, only transfer its(half length of + * dmabuf)integer multiple + * @retval length of data transmited + */ +int32_t HAL_I2S_Write_DMA(uint8_t *buf, uint32_t size) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + if (!buf || size <= 0) + return HAL_INVALID; + uint8_t *pdata = buf; + uint8_t *lastWritePointer = NULL; + uint32_t toWrite = 0,writeSize = I2S_BUF_LENGTH/2; + uint8_t err_flag; /* temp solution to avoid outputing debug message when irq disabled */ + + if (size < writeSize) { + // I2S_INFO("Tx : size is too small....\n"); + return HAL_INVALID; + } + while (size > 0) { + if (size < writeSize) + break; + if (i2sPrivate->txRunning == false) { + if (!i2sPrivate->writePointer) + i2sPrivate->writePointer = i2sPrivate->txBuf; + + lastWritePointer = i2sPrivate->writePointer; + + I2S_MEMCPY(lastWritePointer, pdata, writeSize); + pdata += writeSize; + lastWritePointer += writeSize; + toWrite += writeSize; + size -= writeSize; + if (lastWritePointer >= i2sPrivate->txBuf + I2S_BUF_LENGTH) + lastWritePointer = i2sPrivate->txBuf; + i2sPrivate->writePointer = lastWritePointer; + if (i2sPrivate->writePointer == i2sPrivate->txBuf) { + I2S_DEBUG("Tx: play start...\n"); + HAL_I2S_Trigger(true,PLAYBACK);/*play*/ + i2sPrivate->txRunning =true; + } + } else { + err_flag = 0; + /*disable irq*/ + HAL_DisableIRQ(); + + lastWritePointer = i2sPrivate->writePointer; + if (i2sPrivate->txHalfCallCount && i2sPrivate->txEndCallCount) { + err_flag = 1; + i2sPrivate->txHalfCallCount = 0; + i2sPrivate->txEndCallCount = 0; + + if (i2sPrivate->txDmaPointer == i2sPrivate->txBuf) { + lastWritePointer = i2sPrivate->txBuf + I2S_BUF_LENGTH/2; + } else { + lastWritePointer = i2sPrivate->txBuf; + } + } else if (i2sPrivate->txHalfCallCount) { + i2sPrivate->txHalfCallCount --; + } else if (i2sPrivate->txEndCallCount) { + i2sPrivate->txEndCallCount --; + } else { + /**enable irq**/ + i2sPrivate->isTxSemaphore = true; + HAL_EnableIRQ(); + HAL_SemaphoreWait(&(i2sPrivate->txReady), HAL_WAIT_FOREVER); + /**disable irq**/ + HAL_DisableIRQ(); + if (i2sPrivate->txHalfCallCount) + i2sPrivate->txHalfCallCount --; + if (i2sPrivate->txEndCallCount) + i2sPrivate->txEndCallCount --; + } + + I2S_MEMCPY(lastWritePointer, pdata, writeSize); + pdata += writeSize; + lastWritePointer += writeSize; + toWrite += writeSize; + size -= writeSize; + if (lastWritePointer >= i2sPrivate->txBuf + I2S_BUF_LENGTH) + lastWritePointer = i2sPrivate->txBuf; + i2sPrivate->writePointer = lastWritePointer; + + /**enable irq**/ + HAL_EnableIRQ(); + if (err_flag) { + I2S_ERROR("TxCount:(H:%d,F:%d)\n",i2sPrivate->txHalfCallCount, + i2sPrivate->txEndCallCount); + I2S_ERROR("Tx : underrun....\n"); + } + } + } + return toWrite; +} + +/** + * @brief receive an amount of data with DMA module + * @param buf: pointer to the receive data buffer. + * @param Size: number of data sample to be receive: + * @note if the data size less than half of dmabuf, return HAL_INVALID. when the size + * several times greater than half of dmabuf, only transfer its(half length of + * dmabuf)integer multiple + * @retval length of data received + */ +int32_t HAL_I2S_Read_DMA(uint8_t *buf, uint32_t size) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + if (!buf || size <= 0) + return HAL_INVALID; + uint8_t *pdata = buf; + uint8_t *lastReadPointer = NULL; + uint32_t readSize = I2S_BUF_LENGTH/2; + uint32_t toRead = 0; + uint8_t err_flag; /* temp solution to avoid outputing debug message when irq disabled */ + + if ((size / readSize) < 1) { + I2S_ERROR("Rx buf size too small...\n"); + return HAL_INVALID; + } + + while (size > 0) { + + if (size/readSize < 1) + break; + if (i2sPrivate->rxRunning == false) { + + if (!i2sPrivate->readPointer) + i2sPrivate->readPointer = i2sPrivate->rxBuf; + I2S_DEBUG("Rx: record start...\n"); + HAL_I2S_Trigger(true,RECORD); + + } else { + err_flag = 0; + /*disable irq*/ + HAL_DisableIRQ(); + lastReadPointer = i2sPrivate->readPointer; + if (i2sPrivate->rxHalfCallCount && i2sPrivate->rxEndCallCount) { + err_flag = 1; + i2sPrivate->rxHalfCallCount = 0; + i2sPrivate->rxEndCallCount = 0; + + if (i2sPrivate->rxDmaPointer == i2sPrivate->rxBuf) { + lastReadPointer = i2sPrivate->txBuf + I2S_BUF_LENGTH/2; + } else { + lastReadPointer = i2sPrivate->txBuf; + } + } else if (i2sPrivate->rxHalfCallCount) { + i2sPrivate->rxHalfCallCount --; + } else if (i2sPrivate->rxEndCallCount) { + i2sPrivate->rxEndCallCount --; + } else { + /**enable irq**/ + i2sPrivate->isRxSemaphore = true; + HAL_EnableIRQ(); + HAL_SemaphoreWait(&(i2sPrivate->rxReady), HAL_WAIT_FOREVER); + /**disable irq**/ + HAL_DisableIRQ(); + if (i2sPrivate->rxHalfCallCount) + i2sPrivate->rxHalfCallCount --; + if (i2sPrivate->rxEndCallCount) + i2sPrivate->rxEndCallCount --; + } + I2S_MEMCPY(pdata, lastReadPointer, readSize); + pdata += readSize; + lastReadPointer += readSize; + if (lastReadPointer >= i2sPrivate->rxBuf + I2S_BUF_LENGTH) + lastReadPointer = i2sPrivate->rxBuf; + i2sPrivate->readPointer = lastReadPointer; + /**enable irq**/ + HAL_EnableIRQ(); + if (err_flag) { + I2S_ERROR("RxCount:(H:%d,F:%d)\n",i2sPrivate->rxHalfCallCount, + i2sPrivate->rxEndCallCount); + I2S_ERROR("Rx : overrun....\n"); + } + size -= readSize; + toRead += readSize; + } + } + return toRead; +} + +/** + * @brief Open the I2S module according to the specified parameters + * in the I2S_DataParam. + * @param param: pointer to a I2S_DataParam structure that contains + * data format information + * @retval HAL status + */ +HAL_Status HAL_I2S_Open(I2S_DataParam *param) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + + I2S_DataParam *dataParam = param; + + if (param->direction == PLAYBACK) { + if (i2sPrivate->isTxInitiate == true) { + I2S_ERROR("Tx device opened already.open faied...\n"); + return HAL_ERROR; + } + i2sPrivate->isTxInitiate = true; + + I2S_MEMCPY(&(i2sPrivate->pdataParam), param, sizeof(*param)); + } else { + if (i2sPrivate->isRxInitiate == true) { + I2S_ERROR("Rx device opened already.open faied...\n"); + return HAL_ERROR; + } + i2sPrivate->isRxInitiate = true; + + I2S_MEMCPY(&(i2sPrivate->cdataParam), param, sizeof(*param)); + } + I2S_BUF_LENGTH = dataParam->bufSize; + + if (param->direction == PLAYBACK) { + i2sPrivate->txDMAChan = DMA_CHANNEL_INVALID; + i2sPrivate->txLength = I2S_BUF_LENGTH; + i2sPrivate->txHalfCallCount = 0; + i2sPrivate->txEndCallCount = 0; +#ifdef RESERVERD_MEMORY_FOR_I2S_TX + i2sPrivate->txBuf = I2STX_BUF; +#else + i2sPrivate->txBuf = I2S_MALLOC(I2S_BUF_LENGTH); + if(i2sPrivate->txBuf) + I2S_MEMSET(i2sPrivate->txBuf,0,I2S_BUF_LENGTH); + else { + I2S_ERROR("Malloc tx buf(for DMA),faild...\n"); + return HAL_ERROR; + } +#endif + /*request DMA channel*/ + i2sPrivate->txDMAChan = HAL_DMA_Request(); + if (i2sPrivate->txDMAChan == DMA_CHANNEL_INVALID) { + I2S_ERROR("Obtain I2S tx DMA channel,faild...\n"); +#ifndef RESERVERD_MEMORY_FOR_I2S_TX + I2S_FREE(i2sPrivate->txBuf); +#endif + return HAL_ERROR; + } else + I2S_DMASet(i2sPrivate->txDMAChan, PLAYBACK); + HAL_SemaphoreInitBinary(&i2sPrivate->txReady); + } else { + i2sPrivate->rxDMAChan = DMA_CHANNEL_INVALID; + i2sPrivate->rxLength = I2S_BUF_LENGTH; + i2sPrivate->rxHalfCallCount = 0; + i2sPrivate->rxEndCallCount = 0; +#ifdef RESERVERD_MEMORY_FOR_I2S_RX + i2sPrivate->rxBuf = I2SRX_BUF; +#else + i2sPrivate->rxBuf = I2S_MALLOC(I2S_BUF_LENGTH); + if(i2sPrivate->rxBuf) + I2S_MEMSET(i2sPrivate->rxBuf,0,I2S_BUF_LENGTH); + else { + I2S_ERROR("Malloc rx buf(for DMA),faild...\n"); + return HAL_ERROR; + } +#endif + i2sPrivate->rxDMAChan = HAL_DMA_Request(); + if (i2sPrivate->rxDMAChan == DMA_CHANNEL_INVALID) { + I2S_ERROR("Obtain I2S rx DMA channel,faild...\n"); +#ifndef RESERVERD_MEMORY_FOR_I2S_TX + I2S_FREE(i2sPrivate->rxBuf); +#endif + return HAL_ERROR; + } else + I2S_DMASet(i2sPrivate->rxDMAChan, RECORD); + HAL_SemaphoreInitBinary(&i2sPrivate->rxReady); + } + + HAL_MutexLock(&i2sPrivate->devSetLock, OS_WAIT_FOREVER); + /*set bclk*/ + I2S_SET_ClkDiv(dataParam, i2sPrivate->hwParam); + + /*set sample resolution*/ + I2S_SET_SampleResolution(dataParam); + + /*set channel*/ + I2S_SET_Channels(dataParam); + + if (param->direction == PLAYBACK) { + I2S_EnableTx(); + } else { + I2S_EnableRx(); + } + HAL_MutexUnlock(&i2sPrivate->devSetLock); + + return HAL_OK; +} + +/** + * @brief Close the I2S module + * @note The module is closed at the end of transaction to avoid power consumption + * @retval none + */ +HAL_Status HAL_I2S_Close(uint32_t dir) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + + if (dir == PLAYBACK) { + HAL_I2S_Trigger(false,PLAYBACK); + I2S_DisableTx(); + i2sPrivate->txRunning = false; + i2sPrivate->isTxInitiate = false; + if (i2sPrivate->txDMAChan != DMA_CHANNEL_INVALID) { + HAL_DMA_DeInit(i2sPrivate->txDMAChan); + HAL_DMA_Release(i2sPrivate->txDMAChan); + i2sPrivate->txDMAChan = DMA_CHANNEL_INVALID; + + } + I2S_MEMSET(&(i2sPrivate->pdataParam), 0, sizeof(I2S_DataParam)); +#ifndef RESERVERD_MEMORY_FOR_I2S_TX + I2S_FREE(i2sPrivate->txBuf); +#endif + HAL_SemaphoreDeinit(&i2sPrivate->txReady); + i2sPrivate->txBuf = NULL; + i2sPrivate->txLength = 0; + i2sPrivate->writePointer = NULL; + i2sPrivate->txHalfCallCount = 0; + i2sPrivate->txEndCallCount = 0; + } else { + HAL_I2S_Trigger(false,RECORD); + I2S_DisableRx(); + i2sPrivate->isRxInitiate = false; + i2sPrivate->rxRunning = false; + if (i2sPrivate->rxDMAChan != DMA_CHANNEL_INVALID) { + HAL_DMA_DeInit(i2sPrivate->rxDMAChan); + HAL_DMA_Release(i2sPrivate->rxDMAChan); + i2sPrivate->rxDMAChan = DMA_CHANNEL_INVALID; + + } + I2S_MEMSET(&(i2sPrivate->cdataParam), 0, sizeof(I2S_DataParam)); +#ifndef RESERVERD_MEMORY_FOR_I2S_TX + I2S_FREE(i2sPrivate->rxBuf); +#endif + HAL_SemaphoreDeinit(&i2sPrivate->rxReady); + i2sPrivate->rxBuf = NULL; + i2sPrivate->rxLength = 0; + i2sPrivate->readPointer = NULL; + + i2sPrivate->rxHalfCallCount = 0; + i2sPrivate->rxEndCallCount = 0; + } + return HAL_OK; +} + +/** + * @internal + * @brief I2S PINS Init + * @retval HAL status + */ +static inline HAL_Status I2S_PINS_Init() +{ + return HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_I2S, 0), 0); +} + +/** + * @internal + * @brief I2S PINS DeInit + * @retval HAL status + */ +static inline HAL_Status I2S_PINS_Deinit() +{ + return HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_I2S, 0), 0); +} + +/** + * @internal + * @brief I2S hardware Init + * @param param: pointer to a I2S_HWParam structure that contains + * the configuration for clk/mode/format. + * @retval HAL status + */ +static inline HAL_Status I2S_HwInit(I2S_HWParam *param) +{ + if (!param) + return HAL_INVALID; + + /*config device clk source*/ + if (param->codecClk.isDevclk != 0) { + I2S_SET_Mclk(true,param->codecClk.clkSource, AUDIO_DEVICE_PLL); + } + + /* set lrck period /frame mode */ + HAL_MODIFY_REG(I2S->DA_FMT0, I2S_LRCK_PERIOD_MASK|I2S_LRCK_WIDTH_MASK| + I2S_SW_SEC_MASK, + I2S_LRCK_PERIOD(param->lrckPeriod)| + param->frameMode|I2S_SLOT_WIDTH_BIT32); + + /* set first transfer bit */ + HAL_MODIFY_REG(I2S->DA_FMT1, I2S_TX_MLS_MASK|I2S_RX_MLS_MASK| + I2S_PCM_TXMODE_MASK|I2S_PCM_RXMODE_MASK|I2S_SEXT_MASK, + param->txMsbFirst|param->rxMsbFirst| + I2S_TX_LINEAR_PCM|I2S_RX_LINEAR_PCM|I2S_ZERO_SLOT); + /* global enable */ + HAL_SET_BIT(I2S->DA_CTL, I2S_GLOBE_EN_BIT); + + HAL_MODIFY_REG(I2S->DA_FCTL, I2S_RXFIFO_LEVEL_MASK|I2S_TXFIFO_LEVEL_MASK| + I2S_RX_FIFO_MODE_SHIFT|I2S_TX_FIFO_MODE_MASK, + I2S_RXFIFO_TRIGGER_LEVEL(param->rxFifoLevel)| + I2S_TXFIFO_TRIGGER_LEVEL(param->txFifoLevel)| + I2S_RX_FIFO_MODE3|I2S_TX_FIFO_MODE1); + return I2S_SET_Format(param); +} + +/** + * @internal + * @brief I2S hardware DeInit + * @param param: pointer to a I2S_HWParam structure + * @retval HAL status + */ +static inline HAL_Status I2S_HwDeInit(I2S_HWParam *param) +{ + if (!param) + return HAL_INVALID; + /* global disable */ + HAL_CLR_BIT(I2S->DA_CTL, I2S_GLOBE_EN_BIT); + I2S_SET_Mclk(false, 0, 0); + return HAL_OK; +} + +#ifdef CONFIG_PM +static int i2s_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + HAL_MutexLock(&i2sPrivate->devSetLock, OS_WAIT_FOREVER); + I2S_HwDeInit(i2sPrivate->hwParam); + HAL_MutexUnlock(&i2sPrivate->devSetLock); + + I2S_PINS_Deinit(); + HAL_CCM_DAUDIO_DisableMClock(); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_DAUDIO); + HAL_PRCM_DisableAudioPLL(); + HAL_PRCM_DisableAudioPLLPattern(); + break; + default: + break; + } + return 0; +} + +static int i2s_resume(struct soc_device *dev, enum suspend_state_t state) +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + I2S_PINS_Init(); + /*init and enable clk*/ + I2S_PLLAUDIO_Update(I2S_PLL_22M); + HAL_PRCM_SetAudioPLLParam(i2sPrivate->audioPllParam); + HAL_PRCM_SetAudioPLLPatternParam(i2sPrivate->audioPllPatParam); + HAL_PRCM_EnableAudioPLL(); + HAL_PRCM_EnableAudioPLLPattern(); + + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_DAUDIO); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_DAUDIO); + HAL_CCM_DAUDIO_SetMClock(AUDIO_PLL_SRC); + HAL_CCM_DAUDIO_EnableMClock(); + + HAL_MutexLock(&i2sPrivate->devSetLock, OS_WAIT_FOREVER); + I2S_HwInit(i2sPrivate->hwParam); + HAL_MutexUnlock(&i2sPrivate->devSetLock); + break; + default: + break; + } + return 0; +} + +static struct soc_device_driver i2s_drv = { + .name = "I2S", + .suspend = i2s_suspend, + .resume = i2s_resume, +}; + +static struct soc_device i2s_dev = { + .name = "I2S", + .driver = &i2s_drv, +}; + +#define I2S_DEV (&i2s_dev) +#else +#define I2S_DEV NULL +#endif + +/** + * @brief Initializes the I2S module according to the specified parameters + * in the I2S_Param. + * @param param: pointer to a I2S_Param structure that contains + * the configuration information for I2S + * @retval HAL status + */ +HAL_Status HAL_I2S_Init(I2S_Param *param) + +{ + int32_t ret = 0; + if (!param) + return HAL_INVALID; + I2S_Private *i2sPrivate = &gI2sPrivate; + + if (i2sPrivate->isHwInit == true) + return HAL_OK; + I2S_MEMSET(i2sPrivate,0,sizeof(*i2sPrivate)); + i2sPrivate->isHwInit = true; + + if (param->hwParam == NULL) + i2sPrivate->hwParam = &gHwParam; + else + i2sPrivate->hwParam = param->hwParam; + + HAL_MutexInit(&i2sPrivate->devSetLock); + HAL_MutexInit(&i2sPrivate->devTriggerLock); + + I2S_PINS_Init(); + + /*init and enable clk*/ + I2S_PLLAUDIO_Update(I2S_PLL_22M); + HAL_PRCM_SetAudioPLLParam(i2sPrivate->audioPllParam); + HAL_PRCM_EnableAudioPLL(); + HAL_PRCM_SetAudioPLLPatternParam(i2sPrivate->audioPllPatParam); + HAL_PRCM_EnableAudioPLLPattern(); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_DAUDIO); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_DAUDIO); + HAL_CCM_DAUDIO_SetMClock(AUDIO_PLL_SRC); + HAL_CCM_DAUDIO_EnableMClock(); + + HAL_MutexLock(&i2sPrivate->devSetLock, OS_WAIT_FOREVER); + ret = I2S_HwInit(i2sPrivate->hwParam); + +#ifdef CONFIG_PM + pm_register_ops(I2S_DEV); +#endif + HAL_MutexUnlock(&i2sPrivate->devSetLock); + return ret; +} + +#if 0 +void HAL_I2S_REG_DEBUG() +{ + int i = 0; + for (i = 0; i < 0x58; i = i+4) + printf("REG:0X%x,VAL:0X%x\n",i,(*((__IO uint32_t *)(0x40042c00+i)))); +} +#endif + +/** + * @brief DeInitializes the I2S module + * + * @retval none + */ +void HAL_I2S_DeInit() +{ + I2S_Private *i2sPrivate = &gI2sPrivate; + HAL_MutexLock(&i2sPrivate->devSetLock, OS_WAIT_FOREVER); + i2sPrivate->isHwInit = false; + I2S_HwDeInit(i2sPrivate->hwParam); + HAL_MutexUnlock(&i2sPrivate->devSetLock); + + HAL_MutexDeinit(&i2sPrivate->devSetLock); + HAL_MutexDeinit(&i2sPrivate->devTriggerLock); + I2S_PINS_Deinit(); + + HAL_CCM_DAUDIO_DisableMClock(); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_DAUDIO); + HAL_PRCM_DisableAudioPLL(); + HAL_PRCM_DisableAudioPLLPattern(); + + I2S_MEMSET(i2sPrivate,0,sizeof(struct I2S_Private *)); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_irrx.c b/platform/mcu/xr871/src/driver/chip/hal_irrx.c new file mode 100644 index 0000000000..61b627becc --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_irrx.c @@ -0,0 +1,426 @@ +/** + * @file hal_irrx.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "driver/chip/hal_irrx.h" +#include "driver/chip/ir_nec.h" +#include "hal_base.h" +#include "pm/pm.h" + +#define HAL_DBG_IRRX 0 + +#if (HAL_DBG_IRRX == 1) +#define HAL_IRRX_DBG(fmt, arg...) HAL_LOG(HAL_DBG_ON && HAL_DBG_IRRX, "[IRRX] "fmt, ##arg) +#define irrx_hex_dump_bytes(...) print_hex_dump_bytes(__VA_ARGS__) +#define IRRX_INF HAL_IRRX_DBG +#define IRRX_WRN HAL_WRN +#define IRRX_ERR HAL_ERR +#else +#define HAL_IRRX_DBG(fmt, arg...) +#define irrx_hex_dump_bytes(...) +#define IRRX_INF(...) +#define IRRX_WRN(...) +#define IRRX_ERR(...) +#endif + +/* reg 0x00: Bit definition for cir receiver control register */ +#define IRRX_GLOBAL_EN (0x00000001) /* bit0 */ +#define IRRX_RX_EN (0x00000002) /* bit1 */ +#define IRRX_CIR_EN (0x00000030) /* bit4~bit5 */ + +/* reg 0x2c: Bit definition for cir receiver interrupt control */ +#define IRRX_RXFIFO_MASK (0x000000FF) /* bit0~bit7 */ +#define IR_FIFO_SIZE (64) +#define IR_FIFO_TRIGER (32) + +#define IRRX_IT_ROI (0x00000001) /* bit0 receiver fifo overrun interrupt enable */ +#define IRRX_IT_RPEI (0x00000002) /* bit1 receiver packet end interrupt enable */ +#define IRRX_IT_RAI (0x00000010) /* bit4 RX FIFO Available interrupt enable */ +#define IRRX_IT_DRQ (0x00000020) /* bit5 RX FIFO DMA enable */ +#define IRRX_IT_MASK (IRRX_IT_ROI | IRRX_IT_RPEI | IRRX_IT_RAI | IRRX_IT_DRQ) + +#define IRRX_SET_RAL_MASK (0x00003F00) //bit8~bit13 RX FIFO available received byte level +#define IRRX_RAL_INDEX (8) + +#define IRRX_STATUS_STAT (0x00000080) /* bit7 */ +#define IRRX_STATUS_RAC_MASK (0x00003F00) /* bit8~bit14 */ + +/* reg 0x30: Bit definition for cir receiver status */ +#define IRRX_FLAG_ROI (0x00000001) /* Rx FIFO Overflow */ +#define IRRX_FLAG_RPE (0x00000002) /* Rx Packet End */ +#define IRRX_FLAG_RA (0x00000010) /* Rx FIFO Data Available */ +#define IRRX_FLAG_MASK (IRRX_FLAG_ROI | IRRX_FLAG_RPE | IRRX_FLAG_RA) + +/* reg 0x34: Bit definition for cir receiver sample clock select prescaler */ +#define IRRX_SCS_DIV_64 (0x00000000) +#define IRRX_SCS_DIV_128 (0x00000001) +#define IRRX_SCS_DIV_256 (0x00000002) +#define IRRX_SCS_DIV_512 (0x00000003) +#define IRRX_SCS_DIV_NONE (0x01000000) +#define IRRX_SCS_DIV_MASK (0x00010003) /* clear mask */ + +#define IRRX_NTHR_MASK (0x000000FC) /* bit2~bit7 */ +#define IRRX_NTHR_INDEX (2) + +#define IRRX_ITHR_MASK (0x0000FF00) /* bit8~bit15 */ +#define IRRX_ITHR_INDEX (8) + +#define IRRX_ATHR_MASK (0x007F0000) /* bit16~bit22 */ +#define IRRX_ATHR_INDEX (16) + +#define IRRX_ATHC_CLOCKUNIT_1 (0) +#define IRRX_ATHC_CLOCKUNIT_128 (1) +#define IRRX_ATHC_INDEX (23) + +#if defined (IR_CLK_32K_USED) +#define IRRX_32K_SAMPLE_CLK IRRX_SCS_DIV_NONE /* sample_freq = 32768Hz/1=32768Hz (30.5us) */ +#define IRRX_32K_RXFILT_VAL (11) /* NosieTreshold, Filter Threshold = 11*30.5 = ~335.5us < 500us */ +#define IRRX_32K_RXIDLE_VAL (3) /* IdleTreshold, Idle Threshold = (3+1)*128*30.5 = ~16.4ms > 9ms */ +#define IRRX_32K_APB_PERIPH_CLK_SRC CCM_APB_PERIPH_CLK_SRC_LFCLK +#define IRRX_32K_CCM_PERIPH_CLK_DIV_N CCM_PERIPH_CLK_DIV_N_1 +#define IRRX_32K_CCM_PERIPH_CLK_DIV_M CCM_PERIPH_CLK_DIV_M_1 +#else +#define IRRX_26M_SAMPLE_CLK IRRX_SCS_DIV_128 /* 26MHz/8/128=25390.6Hz (39.4us) */ +#define IRRX_26M_RXFILT_VAL (8) /* NosieTreshold, Filter Threshold = 8*39.4 = ~315us < 500us */ +#define IRRX_26M_RXIDLE_VAL (3) /* IdleTreshold, Idle Threshold = (3+1)*128*39.4 = ~20.2ms > 9ms */ +#define IRRX_26M_APB_PERIPH_CLK_SRC CCM_APB_PERIPH_CLK_SRC_HFCLK +#define IRRX_26M_CCM_PERIPH_CLK_DIV_N CCM_PERIPH_CLK_DIV_N_1 +#define IRRX_26M_CCM_PERIPH_CLK_DIV_M CCM_PERIPH_CLK_DIV_M_8 + +#define IRRX_24M_SAMPLE_CLK IRRX_SCS_DIV_128 /* 24MHz/8/128=23437.5Hz (42.7us) */ +#define IRRX_24M_RXFILT_VAL (8) /* NosieTreshold, Filter Threshold = 8*42.7 = ~341us < 500us */ +#define IRRX_24M_RXIDLE_VAL (2) /* IdleTreshold, Idle Threshold = (2+1)*128*42.7 = ~16.4ms > 9ms */ +#define IRRX_24M_APB_PERIPH_CLK_SRC CCM_APB_PERIPH_CLK_SRC_HFCLK +#define IRRX_24M_CCM_PERIPH_CLK_DIV_N CCM_PERIPH_CLK_DIV_N_1 +#define IRRX_24M_CCM_PERIPH_CLK_DIV_M CCM_PERIPH_CLK_DIV_M_8 +#endif + +typedef struct +{ + __IO uint32_t CR; /* 0x00, IRRX Control */ + uint32_t RESERVED0[3]; + __IO uint32_t CFR; /* 0x10, IRRX Configure */ + uint32_t RESERVED1[3]; + __IO uint32_t DR; /* 0x20, IRRX FIFO */ + uint32_t RESERVED2[2]; + __IO uint32_t ICR; /* 0x2C, IRRX Interrupt Control */ + __IO uint32_t SR; /* 0x30, IRRX Status */ + __IO uint32_t CCR; /* 0x34, IRRX Control Configure */ +} IRRX_TypeDef; + +/* IRRX State structures definition */ +typedef enum +{ + IRRX_STATE_RESET = 0x00, /* Peripheral is not yet Initialized */ + IRRX_STATE_READY = 0x02, /* Peripheral Initialized and ready for use */ + IRRX_STATE_BUSY = 0x04, /* An internal process is ongoing */ + IRRX_STATE_ERROR = 0x08 /* Error */ +} IRRX_StateTypeDef; + +#define IRRX_RAW_BUF_SIZE 128 /* 256 */ + +/* IRRX handle Structure definition */ +struct IRRX_HandleDef +{ + IRRX_TypeDef *Instance; /* IRRX registers base address */ + uint32_t rxCnt; /* IRRX Rx Transfer layer Counter */ + uint8_t rxBuff[IRRX_RAW_BUF_SIZE]; /* Pointer to IRRX Rx transfer Buffer */ + IRRX_StateTypeDef State; /* IRRX communication state */ + IRRX_RxCpltCallback rxCpltCallback; +}; + +static HAL_Status IRRX_ReadFIFO_RawData(IRRX_HandleTypeDef *irrx, uint32_t ralcnt) +{ + uint32_t i, tmp; + + if (ralcnt == 0) + return HAL_INVALID; + + for (i = 0; i < ralcnt; i++) { + if (irrx->rxCnt >= IRRX_RAW_BUF_SIZE) + tmp = irrx->Instance->DR; + else + irrx->rxBuff[irrx->rxCnt++] = (uint8_t)(irrx->Instance->DR); + } + + (void)tmp; + + return HAL_OK; +} + +static IRRX_HandleTypeDef hal_irrx; + +static void IRRX_IRQHandler(void) +{ + uint32_t intsta, dcnt; + IRRX_HandleTypeDef *irrx = &hal_irrx; + + intsta = irrx->Instance->SR; + irrx->Instance->SR = intsta & IRRX_FLAG_MASK; + IRRX_INF("%s,%d %x\n", __func__, __LINE__, intsta); + + dcnt = (intsta & IRRX_SET_RAL_MASK) >> IRRX_RAL_INDEX; + IRRX_ReadFIFO_RawData(irrx, dcnt); + + irrx->State = IRRX_STATE_READY; + + if (intsta & IRRX_FLAG_RPE) { /* Packet End */ + uint32_t code; + int32_t code_valid; + + if (irrx->rxCnt >= IRRX_RAW_BUF_SIZE) { + IRRX_INF("Raw Buffer Full!!\n"); + irrx->rxCnt = 0; + return ; + } + + code = IRRX_NECPacket_DeCode(irrx->rxBuff, irrx->rxCnt); + irrx->rxCnt = 0; + code_valid = IRRX_NECCode_Valid(code); + + if (code_valid) { /* report keycode */ + irrx->rxCpltCallback(code & 0xff, (code >> 16) & 0xff); + } /* else retry other protocal */ + } + + if (intsta & IRRX_FLAG_ROI) { /* FIFO Overflow */ + IRRX_INF("Rx FIFO Overflow!!\n"); + irrx->rxCnt = 0; + } +} + +static void IRRX_SetConfig(IRRX_TypeDef *Instance, IRRX_InitTypeDef *param) +{ +#if !defined (IR_CLK_32K_USED) + uint32_t clk = HAL_GetHFClock(); +#endif + Instance->CR |= IRRX_CIR_EN; /* Enable IR Mode */ + +#if defined (IR_CLK_32K_USED) + Instance->CCR = (IRRX_32K_RXFILT_VAL << IRRX_NTHR_INDEX) | \ + (IRRX_32K_RXIDLE_VAL << IRRX_ITHR_INDEX) | \ + (IRRX_32K_ACTIVE_T << IRRX_ATHR_INDEX) | \ + (IRRX_32K_ACTIVE_T_C << IRRX_ATHC_INDEX) | \ + IRRX_32K_SAMPLE_CLK; +#else + if (clk == HOSC_CLOCK_26M) { + Instance->CCR = (IRRX_26M_RXFILT_VAL << IRRX_NTHR_INDEX) | \ + (IRRX_26M_RXIDLE_VAL << IRRX_ITHR_INDEX) | \ + (IRRX_26M_ACTIVE_T << IRRX_ATHR_INDEX) | \ + (IRRX_26M_ACTIVE_T_C << IRRX_ATHC_INDEX) | \ + IRRX_26M_SAMPLE_CLK; + } else if (clk == HOSC_CLOCK_24M) { + Instance->CCR = (IRRX_24M_RXFILT_VAL << IRRX_NTHR_INDEX) | \ + (IRRX_24M_RXIDLE_VAL << IRRX_ITHR_INDEX) | \ + (IRRX_24M_ACTIVE_T << IRRX_ATHR_INDEX) | \ + (IRRX_24M_ACTIVE_T_C << IRRX_ATHC_INDEX) | \ + IRRX_24M_SAMPLE_CLK; + } else { + IRRX_ERR("%s unknow clk type(%d)!\n", __func__, clk); + } +#endif + Instance->ICR &= ~IRRX_SET_RAL_MASK; + Instance->ICR |= (IR_FIFO_TRIGER - 1) << IRRX_RAL_INDEX; + + Instance->CFR = param->PulsePolariyInvert; + Instance->SR = IRRX_FLAG_MASK; + + Instance->ICR |= IRRX_IT_ROI | IRRX_IT_RPEI | IRRX_IT_RAI; + + Instance->CR |= IRRX_GLOBAL_EN | IRRX_RX_EN; /* enable ir module */ +} + +#ifdef CONFIG_PM +static IRRX_InitTypeDef hal_irrx_param; +static IRRX_StateTypeDef hal_irrx_suspending = 0; + +static int irrx_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + hal_irrx_suspending = 1; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + HAL_IRRX_DeInit(dev->platform_data); + IRRX_INF("%s okay\n", __func__); + break; + default: + break; + } + + return 0; +} + +static int irrx_resume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_IRRX_Init(&hal_irrx_param); + IRRX_INF("%s okay\n", __func__); + break; + default: + break; + } + + hal_irrx_suspending = 0; + + return 0; +} + +static struct soc_device_driver irrx_drv = { + .name = "irrx", + .suspend_noirq = irrx_suspend, + .resume_noirq = irrx_resume, +}; + +static struct soc_device irrx_dev = { + .name = "irrx", + .driver = &irrx_drv, +}; + +#define IRRX_DEV (&irrx_dev) +#else +#define IRRX_DEV NULL +#endif + +/** + * @brief Initializes the IRRX peripheral. + * @param param: + * @arg param->[in] The configuration information. + * @retval IRRX handler. + */ +IRRX_HandleTypeDef *HAL_IRRX_Init(IRRX_InitTypeDef *param) +{ +#if !defined (IR_CLK_32K_USED) + uint32_t clk = HAL_GetHFClock(); +#endif + IRRX_HandleTypeDef *irrx = &hal_irrx; + + HAL_ASSERT_PARAM(param->rxCpltCallback); + + irrx->Instance = (IRRX_TypeDef *)IRRX_BASE; + irrx->rxCpltCallback = param->rxCpltCallback; + + if (irrx->State != IRRX_STATE_RESET) { + IRRX_ERR("%s err state:%d\n", __func__, irrx->State); + return NULL; + } + + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_IRRX, 0), 0); + +#if defined (IR_CLK_32K_USED) + HAL_CCM_IRRX_SetMClock(IRRX_32K_APB_PERIPH_CLK_SRC, + IRRX_32K_CCM_PERIPH_CLK_DIV_N, \ + IRRX_32K_CCM_PERIPH_CLK_DIV_M); +#else + if (clk == HOSC_CLOCK_26M) { + HAL_CCM_IRRX_SetMClock(IRRX_26M_APB_PERIPH_CLK_SRC, + IRRX_26M_CCM_PERIPH_CLK_DIV_N, \ + IRRX_26M_CCM_PERIPH_CLK_DIV_M); + } else if (clk == HOSC_CLOCK_24M) { + HAL_CCM_IRRX_SetMClock(IRRX_24M_APB_PERIPH_CLK_SRC, + IRRX_24M_CCM_PERIPH_CLK_DIV_N, \ + IRRX_24M_CCM_PERIPH_CLK_DIV_M); + } else { + IRRX_ERR("%s unknow clk type(%d)!\n", __func__, clk); + } +#endif + HAL_CCM_IRRX_EnableMClock(); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_IRRX); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_IRRX); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_IRRX); + + IRRX_SetConfig(irrx->Instance, param); + irrx->Instance->SR = IRRX_FLAG_MASK; /* Clear All Rx Interrupt Status */ + + irrx->State = IRRX_STATE_READY; + irrx->rxCnt = 0; +#ifdef CONFIG_PM + if (!hal_irrx_suspending) { + memcpy(&hal_irrx_param, param, sizeof(IRRX_InitTypeDef)); + IRRX_DEV->platform_data = irrx; + pm_register_ops(IRRX_DEV); + } +#endif + HAL_NVIC_SetIRQHandler(IRRX_IRQn, IRRX_IRQHandler); + NVIC_EnableIRQ(IRRX_IRQn); + + return irrx; +} + +/** + * @brief DeInitializes the IRRX peripheral. + * @param irrx: + * @arg irrx->[in] IRRX handler. + * @return None. + */ +void HAL_IRRX_DeInit(IRRX_HandleTypeDef *irrx) +{ + HAL_ASSERT_PARAM(irrx); + + if (irrx->State != IRRX_STATE_READY) { + IRRX_ERR("%s err state:%d\n", __func__, irrx->State); + return ; + } + + NVIC_DisableIRQ(IRRX_IRQn); + +#ifdef CONFIG_PM + if (!hal_irrx_suspending) { + pm_unregister_ops(IRRX_DEV); + IRRX_DEV->platform_data = NULL; + } +#endif + + /* Disable the Peripheral */ + irrx->Instance->CR &= ~IRRX_GLOBAL_EN; + + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_IRRX); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_IRRX); + HAL_CCM_IRRX_DisableMClock(); + + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_IRRX, 0), 0); + + irrx->State = IRRX_STATE_RESET; +} + +#undef IRRX_INF +#undef IRRX_WRN +#undef IRRX_ERR diff --git a/platform/mcu/xr871/src/driver/chip/hal_irtx.c b/platform/mcu/xr871/src/driver/chip/hal_irtx.c new file mode 100644 index 0000000000..736214b70b --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_irtx.c @@ -0,0 +1,502 @@ +/** + * @file hal_irtx.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "driver/chip/hal_irtx.h" +#include "driver/chip/ir_nec.h" +#include "hal_base.h" +#include "sys/interrupt.h" +#include "pm/pm.h" + +#define HAL_DBG_IRTX 0 + +#if (HAL_DBG_IRTX == 1) +#define HAL_IRTX_DBG(fmt, arg...) HAL_LOG(HAL_DBG_ON && HAL_DBG_IRTX, "[IRTX] "fmt, ##arg) +#define irtx_hex_dump_bytes(...) print_hex_dump_bytes(__VA_ARGS__) +#define IRTX_INF HAL_IRTX_DBG +#define IRTX_WRN HAL_WRN +#define IRTX_ERR HAL_ERR +#else +#define HAL_IRTX_DBG(fmt, arg...) +#define irtx_hex_dump_bytes(...) +#define IRTX_INF HAL_IRTX_DBG +#define IRTX_WRN(...) +#define IRTX_ERR(...) +#endif + +/* Bit definition for cir Transmit Global register */ +#define IRTX_RESET (1<<1) + +#define IRTX_TXEN (1) + +/* Bit definition for cir Transmit Control register */ +#define IRTX_RCS_DIV_2 (1<<1) +#define IRTX_RCS_DIV_4 (2<<1) +#define IRTX_RCS_DIV_8 (3<<1) +#define IRTX_RCS_DIV_64 (4<<1) +#define IRTX_RCS_DIV_128 (5<<1) +#define IRTX_RCS_DIV_256 (6<<1) +#define IRTX_RCS_DIV_512 (7<<1) +#define IRTX_RCS_DIV_MASK (7<<1) + +#define IRTX_CSS_EN (1<<7) + +/* Bit definition for cir Transmit Interrupt Control register */ +#define IRTX_IT_TAI (1<<1) /* TX FIFO Available Interrupt Enable */ +#define IRTX_IT_TPE (1) /* Transmit Packet End Interrupt Enable for Cyclical Pulse */ +#define IRTX_IT_TUI (1) /* Transmit FIFO under run Interrupt Enable for Non-cyclical Pulse */ + +/* Bit definition for cir Transmit Status register */ +#define IRTX_FLAG_TPE (1) /* Transmitter Packet End Flag for Cyclical Pulse */ +#define IRTX_FLAG_TUR (1) /* Transmitter FIFO Under Run Flag for Non-cyclical Pulse */ +#define IRTX_FLAG_TAI (1<<1) /* TX FIFO Available Interrupt Flag */ + +#define IRTX_STCT (1<<3) /* Status of CIR Transmitter */ + +#define IRTX_CAVE_FREQ (38000) /* actually is 6.5M/IRTX_MC_VALUE=38011.7Hz, T=26.3uS */ +#if (defined IR_CLK_32K_USED) +#define IRTX_32K_APB_PERIPH_CLK_SRC CCM_APB_PERIPH_CLK_SRC_LFCLK +#define IRTX_32K_CCM_PERIPH_CLK_DIV_N CCM_PERIPH_CLK_DIV_N_1 +#define IRTX_32K_CCM_PERIPH_CLK_DIV_M CCM_PERIPH_CLK_DIV_M_1 +#define IRTX_32K_CCM_PERIPH_CLK (32768) +#define IRTX_32K_MC_VALUE (1) /* 1 */ +#define IRTX_32K_SAMPLE IRTX_RCS_DIV_2 /* IRTX_CCM_PERIPH_CLK/2=16.4KHz, Ts=61uS */ +#else +#define IRTX_26M_APB_PERIPH_CLK_SRC CCM_APB_PERIPH_CLK_SRC_HFCLK +#define IRTX_26M_CCM_PERIPH_CLK_DIV_N CCM_PERIPH_CLK_DIV_N_1 +#define IRTX_26M_CCM_PERIPH_CLK_DIV_M CCM_PERIPH_CLK_DIV_M_8 /* 26M/8=3.25M */ +#define IRTX_26M_CCM_PERIPH_CLK (26000000/8) +#define IRTX_26M_MC_VALUE (IRTX_26M_CCM_PERIPH_CLK/IRTX_CAVE_FREQ) /* 3.25MHz/IRTX_CAVE_FREQ=85 */ +#define IRTX_26M_SAMPLE IRTX_RCS_DIV_128 /* IRTX_CCM_PERIPH_CLK/128=25.4KHz, Ts=39.4uS */ + +#define IRTX_24M_APB_PERIPH_CLK_SRC CCM_APB_PERIPH_CLK_SRC_HFCLK +#define IRTX_24M_CCM_PERIPH_CLK_DIV_N CCM_PERIPH_CLK_DIV_N_1 +#define IRTX_24M_CCM_PERIPH_CLK_DIV_M CCM_PERIPH_CLK_DIV_M_4 /* 24M/4=6M */ +#define IRTX_24M_CCM_PERIPH_CLK (24000000/4) +#define IRTX_24M_MC_VALUE (IRTX_24M_CCM_PERIPH_CLK/IRTX_CAVE_FREQ) /* 6MHz/IRTX_CAVE_FREQ=157 */ +#define IRTX_24M_SAMPLE IRTX_RCS_DIV_256 /* IRTX_CCM_PERIPH_CLK/256=23.4KHz, Ts=43.7uS */ +#endif + +#define IR_TX_FIFO_SIZE (128) + +typedef struct +{ + __IO uint32_t TGR; /* 0x00 IRTX Global Register */ + __IO uint32_t TMCR; /* 0x04 IRTX Modulationg Control register */ + __IO uint32_t TCR; /* 0x08 IRTX Control Register */ + __IO uint32_t IDCNT_H; /* 0x0C IRTX Idle Duration threshold Resgister High */ + __IO uint32_t IDCNT_L; /* 0x10 IRTX Idle Duration threshold Resgister Low */ + __IO uint32_t TICNT_H; /* 0x14 IRTX Idle Counter Resgister High */ + __IO uint32_t TICNT_L; /* 0x18 IRTX Idle Counter Resgister Low */ + uint32_t RESERVED0[1]; + __IO uint32_t TER; /* 0x20 IRTX FIFO empty Level Register */ + __IO uint32_t TICR; /* 0x24 IRTX Interrupt Control Register */ + __IO uint32_t TACR; /* 0x28 IRTX FIFO Available Counter Register */ + __IO uint32_t SR; /* 0x2C IRTX Status Register */ + __IO uint32_t TXTR; /* 0x30 IRTX Threshold Register */ + __IO uint32_t DMACR; /* 0x34 IRTX DMA Control Register */ + uint32_t RESERVED1[2]; + uint32_t RESERVED2[4]; /* 0x40 */ + uint32_t RESERVED3[4]; /* 0x50 */ + uint32_t RESERVED4[4]; /* 0x60 */ + uint32_t RESERVED5[4]; /* 0x70 */ + __IO uint32_t DR; /* 0x80 IRTX Trainsmit FIFO Data Register */ +} IRTX_TypeDef; + +/* IRTX State structures definition */ +typedef enum +{ + IRTX_STATE_RESET = 0x00, /* Peripheral is not initialized */ + IRTX_STATE_READY = 0x01, /* Peripheral Initialized and ready for use */ + IRTX_STATE_BUSY = 0x02, /* An internal process is ongoing */ + IRTX_STATE_ERROR = 0x04 /* Error */ +} IRTX_StateTypeDef; + +#define IRTX_BUFFER_SIZE 256 + +/* IRTX handle Structure definition */ +struct IRTX_HandleDef +{ + IRTX_TypeDef *Instance; /* IRTX registers base address */ + IRTX_TTS_Type SendModeType; /* signal or cyclical mode */ + uint32_t CyclicalCnt; /* count of cyclical mode */ + uint32_t CyclicalTxCnt; /* sended count of cyclical mode */ + uint16_t TxNum; /* Used when send data more than 128 bytes */ + uint8_t txBuff[IRTX_BUFFER_SIZE]; /* Pointer to IRRX Rx transfer Buffer */ + uint16_t txCnt; /* IRRX Rx Transfer layer Counter */ + IRTX_StateTypeDef State; /* IRTX communication state */ + IRTX_Proto_Code Protos[IRTX_PROTO_NUM]; +}; + +static IRTX_HandleTypeDef hal_irtx; + +static void HAL_IRTX_CycMode_Stop(IRTX_HandleTypeDef *irtx) +{ + if (irtx->SendModeType == IRTX_TTS_CYCLICAL) { + irtx->Instance->TCR &= ~IRTX_CSS_EN; + irtx->Instance->TGR |= IRTX_RESET; + while (irtx->Instance->TGR & IRTX_RESET) + ; + + irtx->State = IRTX_STATE_READY; + } +} + +static void IRTX_IRQHandler(void) +{ + uint32_t intsta; + IRTX_HandleTypeDef *irtx = &hal_irtx; + + intsta = irtx->Instance->SR; + irtx->Instance->SR = intsta; + //IRTX_INF("%s,%d %x\n", __func__, __LINE__, intsta); + + if (irtx->SendModeType == IRTX_TTS_CYCLICAL) { + irtx->Instance->TICNT_L = 0; + irtx->Instance->TICNT_H = 0; + if (++irtx->CyclicalTxCnt >= irtx->CyclicalCnt) { + HAL_IRTX_CycMode_Stop(irtx); + } + return ; + } + + if (intsta & IRTX_FLAG_TPE) { + irtx->Instance->TCR &= ~IRTX_CSS_EN; + irtx->Instance->TICR &= ~IRTX_FLAG_TPE; + irtx->State = IRTX_STATE_READY; + } + if (intsta & IRTX_FLAG_TAI) { + while (irtx->TxNum < irtx->txCnt) { + if (irtx->Instance->TACR == 0) { + IRTX_WRN("%s,%d\n", __func__, __LINE__); + return ; + } + irtx->Instance->DR = irtx->txBuff[irtx->TxNum++]; + } + if (irtx->TxNum >= irtx->txCnt) + irtx->Instance->TICR &= ~IRTX_FLAG_TAI; + } +} + +static void IRTX_SetConfig(IRTX_TypeDef *Instance, IRTX_InitTypeDef *Init) +{ +#if !defined (IR_CLK_32K_USED) + uint32_t clk = HAL_GetHFClock(); +#endif + + HAL_ASSERT_PARAM(((Init->ModulateDutyLevel) == IRTX_DRMC_TIME_1) || \ + ((Init->ModulateDutyLevel) == IRTX_DRMC_TIME_2) || \ + ((Init->ModulateDutyLevel) == IRTX_DRMC_TIME_3)); + HAL_ASSERT_PARAM(((Init->SendModeType) == IRTX_TTS_NONE) || \ + ((Init->SendModeType) == IRTX_TTS_CYCLICAL)); + HAL_ASSERT_PARAM(((Init->PulsePolarity) == IRTX_TPPI_NONE) || \ + ((Init->PulsePolarity) == IRTX_TPPI_INVERT)); + +#if defined (IR_CLK_32K_USED) + Instance->TMCR = IRTX_32K_MC_VALUE; + + Instance->TCR &= ~IRTX_RCS_DIV_MASK; + Instance->TCR |= IRTX_32K_SAMPLE; +#else + if (clk == HOSC_CLOCK_26M) { + Instance->TMCR = IRTX_26M_MC_VALUE; + + Instance->TCR &= ~IRTX_RCS_DIV_MASK; + Instance->TCR |= IRTX_26M_SAMPLE; + } else if (clk == HOSC_CLOCK_24M) { + Instance->TMCR = IRTX_24M_MC_VALUE; + + Instance->TCR &= ~IRTX_RCS_DIV_MASK; + Instance->TCR |= IRTX_24M_SAMPLE; + } +#endif + + Instance->TGR &= ~IRTX_DRMC_TIME_MASK; + Instance->TGR |= Init->ModulateDutyLevel; + + Instance->TCR &= ~IRTX_TTS_MASK; + Instance->TCR |= Init->SendModeType; + + Instance->TGR &= ~IRTX_TPPI_MASK; + Instance->TGR |= Init->PulsePolarity; + + Instance->IDCNT_H = (Init->IdleDurationCnt >> 8) & 0x0F; + Instance->IDCNT_L = Init->IdleDurationCnt & 0xff; + + Instance->TGR |= Init->InternalModulation; + + Instance->TER &= ~0x000000FF; + Instance->TER |= IR_TX_FIFO_SIZE; + + Instance->SR = IRTX_FLAG_TAI | IRTX_FLAG_TPE; + + Instance->TXTR = IR_TX_FIFO_SIZE; + + Instance->TGR |= IRTX_TXEN; +} + +#define MIN(x , y) (((x) < (y)) ? (x) : (y)) + +/** + * @brief Send a code by IRTX peripheral. + * @param irtx: + * @arg irtx-> IRTX handler. + * @param protos_sel: + * @arg protos_sel->[in] The protocal used. + * @param ir_tx_code: + * @arg ir_tx_code->[in] The add and key(add|~addr|key|~key) will send. + * @retval None. + */ +void HAL_IRTX_Transmit(IRTX_HandleTypeDef *irtx, uint32_t protos_sel, uint32_t ir_tx_code) +{ + uint32_t i = 0; + unsigned long flags; + + IRTX_INF("%s %x\n", __func__, ir_tx_code); + if (irtx->State != IRTX_STATE_READY) { + IRTX_WRN("wait ir tx ready!\n"); + return ; + } + irtx->State = IRTX_STATE_BUSY; + irtx->CyclicalTxCnt = 0; + + HAL_ASSERT_PARAM(irtx->Protos[protos_sel]); + irtx->txCnt = irtx->Protos[protos_sel](irtx->txBuff, ir_tx_code); + + irtx->Instance->TICR &= ~(IRTX_IT_TAI | IRTX_IT_TPE); + irtx->Instance->SR = IRTX_FLAG_TAI | IRTX_FLAG_TPE; + + if (irtx->SendModeType == IRTX_TTS_CYCLICAL) { + if (irtx->txCnt > IR_TX_FIFO_SIZE) { + IRTX_ERR("send too much bytes in cyclical mode!\n"); + return ; + } + flags = arch_irq_save(); + for (i = 0; i < irtx->txCnt; i++) { + while (irtx->Instance->TACR == 0) { + IRTX_INF("%s: fifo full\n", __func__); + } + irtx->Instance->DR = irtx->txBuff[i]; + } + arch_irq_restore(flags); + + irtx->Instance->TICR |= IRTX_IT_TPE; + irtx->Instance->TCR |= IRTX_CSS_EN; + } else { + uint32_t tmp_tthreshold, tmp_ethreshold; + + if (irtx->txCnt > IR_TX_FIFO_SIZE) { + tmp_tthreshold = IR_TX_FIFO_SIZE - 4; + tmp_ethreshold = IR_TX_FIFO_SIZE >> 1; + } else { + tmp_tthreshold = irtx->txCnt - 1; + tmp_ethreshold = irtx->txCnt >> 1; + } + irtx->Instance->TXTR = tmp_tthreshold; + irtx->Instance->TER &= ~0x000000FF; + irtx->Instance->TER |= tmp_ethreshold; + irtx->TxNum = 0; + flags = arch_irq_save(); + while (irtx->TxNum < MIN(IR_TX_FIFO_SIZE, irtx->txCnt)) { + while (irtx->Instance->TACR == 0) { + IRTX_INF("%s fifo full\n", __func__); + } + i = 0; + irtx->Instance->DR = irtx->txBuff[irtx->TxNum++]; + } + arch_irq_restore(flags); + if (irtx->TxNum < irtx->txCnt) + irtx->Instance->TICR |= IRTX_IT_TAI; + irtx->Instance->TICR |= IRTX_IT_TPE; /* non-cycle transmit threshold */ + } +} + +#ifdef CONFIG_PM +static IRTX_InitTypeDef hal_irtx_param; +static IRTX_StateTypeDef hal_irtx_suspending = 0; + +static int irtx_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + hal_irtx_suspending = 1; + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_IRTX_DeInit(dev->platform_data); + IRTX_INF("%s okay\n", __func__); + break; + default: + break; + } + + return 0; +} + +static int irtx_resume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_IRTX_Init(&hal_irtx_param); + IRTX_INF("%s okay\n", __func__); + break; + default: + break; + } + + hal_irtx_suspending = 0; + + return 0; +} + +static struct soc_device_driver irtx_drv = { + .name = "irtx", + .suspend_noirq = irtx_suspend, + .resume_noirq = irtx_resume, +}; + +static struct soc_device irtx_dev = { + .name = "irtx", + .driver = &irtx_drv, +}; + +#define IRTX_DEV (&irtx_dev) +#else +#define IRTX_DEV NULL +#endif + +/** + * @brief Initializes the IRTX peripheral. + * @param param: + * @arg param->[in] The configuration information. + * @retval IRTX handler. + */ +IRTX_HandleTypeDef *HAL_IRTX_Init(IRTX_InitTypeDef *param) +{ +#if !defined (IR_CLK_32K_USED) + uint32_t clk = HAL_GetHFClock(); +#endif + IRTX_HandleTypeDef *irtx = &hal_irtx; + + irtx->SendModeType = param->SendModeType; + if (irtx->SendModeType == IRTX_TTS_CYCLICAL) { + HAL_ASSERT_PARAM(param->CyclicalCnt > 0); + irtx->CyclicalCnt = param->CyclicalCnt; + } + + irtx->Instance = (IRTX_TypeDef *)IRTX_BASE; + if (irtx->State == IRTX_STATE_RESET) { + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_IRTX, 0), 0); + } +#if defined (IR_CLK_32K_USED) + HAL_CCM_IRTX_SetMClock(IRTX_32K_APB_PERIPH_CLK_SRC, + IRTX_32K_CCM_PERIPH_CLK_DIV_N, \ + IRTX_32K_CCM_PERIPH_CLK_DIV_M); +#else + if (clk == HOSC_CLOCK_26M) { + HAL_CCM_IRTX_SetMClock(IRTX_26M_APB_PERIPH_CLK_SRC, + IRTX_26M_CCM_PERIPH_CLK_DIV_N, \ + IRTX_26M_CCM_PERIPH_CLK_DIV_M); + } else if (clk == HOSC_CLOCK_24M) { + HAL_CCM_IRTX_SetMClock(IRTX_24M_APB_PERIPH_CLK_SRC, + IRTX_24M_CCM_PERIPH_CLK_DIV_N, \ + IRTX_24M_CCM_PERIPH_CLK_DIV_M); + } else { + IRTX_ERR("%s unknow clk type(%d)!\n", __func__, clk); + return NULL; + } +#endif + + HAL_CCM_IRTX_EnableMClock(); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_IRTX); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_IRTX); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_IRTX); + + IRTX_SetConfig(irtx->Instance, param); + + IRTX_PROTOS_FUN_INIT(irtx); +#ifdef CONFIG_PM + if (!hal_irtx_suspending) { + memcpy(&hal_irtx_param, param, sizeof(IRTX_InitTypeDef)); + IRTX_DEV->platform_data = irtx; + pm_register_ops(IRTX_DEV); + } +#endif + + HAL_NVIC_SetIRQHandler(IRTX_IRQn, IRTX_IRQHandler); + NVIC_EnableIRQ(IRTX_IRQn); + + irtx->State = IRTX_STATE_READY; + + return irtx; +} + +/** + * @brief DeInitializes the IRTX peripheral. + * @param irtx: + * @arg irtx->IRTX handler. + * @retval None. + */ +void HAL_IRTX_DeInit(IRTX_HandleTypeDef *irtx) +{ + if (irtx->State == IRTX_STATE_BUSY) { + IRTX_ERR("try deinit when not busy\n"); + return ; + } + + if (irtx->State != IRTX_STATE_READY) + return ; + + irtx->Instance->TGR &= ~IRTX_TXEN; + + NVIC_DisableIRQ(IRTX_IRQn); + +#ifdef CONFIG_PM + if (!hal_irtx_suspending) { + pm_unregister_ops(IRTX_DEV); + IRTX_DEV->platform_data = NULL; + } +#endif + + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_IRTX); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_IRTX); + HAL_CCM_IRTX_DisableMClock(); + + /* DeInit the low level hardware */ + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_IRTX, 0), 0); + + irtx->State = IRTX_STATE_RESET; +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_mbox.c b/platform/mcu/xr871/src/driver/chip/hal_mbox.c new file mode 100644 index 0000000000..bb4b225261 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_mbox.c @@ -0,0 +1,394 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_mbox.h" +#include "hal_base.h" + +/* useful macros */ +#define MBOX_REG_BITS 32 + +#define MBOX_IRQ_ALL_BITS ((1 << (MBOX_QUEUE_NUM << 1)) - 1) + +#define MBOX_GET_IRQ_BIT_POS(queue, dir) \ + ((queue << 1) + (dir == MBOX_DIR_TX ? 1 : 0)) + + +#define N_CCM_BUS_PERIPH_BIT_MSGBOX HAL_BIT(2) +#define N_CCM_BUS_PERIPH_CLK_CTRL_REG (*((__IO uint32_t *)(0xA0041024U))) +#define N_CCM_BUS_PERIPH_RST_CTRL_REG (*((__IO uint32_t *)(0xA0041028U))) + +void HAL_MBOX_Init(MBOX_T *mbox) +{ + if (mbox == MBOX_A) { + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_MSGBOX); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_MSGBOX); + } else { + HAL_SET_BIT(N_CCM_BUS_PERIPH_CLK_CTRL_REG, N_CCM_BUS_PERIPH_BIT_MSGBOX); + HAL_SET_BIT(N_CCM_BUS_PERIPH_RST_CTRL_REG, N_CCM_BUS_PERIPH_BIT_MSGBOX); + } +} + +void HAL_MBOX_DeInit(MBOX_T *mbox) +{ + if (mbox == MBOX_A) { + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_MSGBOX); + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_MSGBOX); + } else { + HAL_CLR_BIT(N_CCM_BUS_PERIPH_RST_CTRL_REG, N_CCM_BUS_PERIPH_BIT_MSGBOX); + HAL_CLR_BIT(N_CCM_BUS_PERIPH_CLK_CTRL_REG, N_CCM_BUS_PERIPH_BIT_MSGBOX); + } +} + +#if HAL_MBOX_PM_PATCH + +#ifdef __CONFIG_ARCH_APP_CORE + +#include "driver/chip/hal_dma.h" + +void HAL_MBOX_QueueInit(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t regIdx; + uint32_t rxBit, txBit; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + /* NB: MUST set the users of queue's TX/RX at the same time */ + + rxBit = (queue << 3); + txBit = rxBit + 4; + + regIdx = rxBit / MBOX_REG_BITS; + rxBit = rxBit % MBOX_REG_BITS; + txBit = txBit % MBOX_REG_BITS; + + /* TODO: may need spinlock to lock this operation */ + if (user == MBOX_USER0) { + HAL_MODIFY_REG(mbox->CTRL[regIdx], + HAL_BIT(rxBit) | HAL_BIT(txBit), + dir == MBOX_DIR_TX ? HAL_BIT(rxBit) : HAL_BIT(txBit)); + } else { + HAL_MODIFY_REG(mbox->CTRL[regIdx], + HAL_BIT(rxBit) | HAL_BIT(txBit), + dir == MBOX_DIR_TX ? HAL_BIT(txBit) : HAL_BIT(rxBit)); + } +} + +static void MBOX_WriteRegister_DMA(volatile uint32_t *reg, uint32_t val) +{ + DMA_ChannelInitParam dmaParam; + DMA_Channel dmaChan; + static volatile uint32_t data; + + dmaChan = HAL_DMA_Request(); + if (dmaChan == DMA_CHANNEL_INVALID) { + HAL_ERR("no free dma channel\n"); + return; + } + + data = val; + HAL_Memset(&dmaParam, 0, sizeof(dmaParam)); + dmaParam.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_1, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_32BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_32BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + DMA_PERIPH_SRAM); + dmaParam.irqType = DMA_IRQ_TYPE_END; + dmaParam.endCallback = NULL; + dmaParam.endArg = NULL; + HAL_DMA_Init(dmaChan, &dmaParam); + HAL_DMA_Start(dmaChan, (uint32_t)&data, (uint32_t)reg, 1); + while (HAL_DMA_GetByteCount(dmaChan) != 0) { } + HAL_DMA_Stop(dmaChan); + HAL_DMA_DeInit(dmaChan); + HAL_DMA_Release(dmaChan); +} + +void HAL_MBOX_QueueEnableIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t bit; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = MBOX_GET_IRQ_BIT_POS(queue, dir); + + if (user == MBOX_USER0) { + HAL_SET_BIT(mbox->IRQ0_EN, HAL_BIT(bit)); + } else { + uint32_t irq_en = mbox->IRQ1_EN; + HAL_SET_BIT(irq_en, HAL_BIT(bit)); + MBOX_WriteRegister_DMA(&mbox->IRQ1_EN, irq_en); + } +} + +void HAL_MBOX_QueueDisableIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t bit; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = MBOX_GET_IRQ_BIT_POS(queue, dir); + + if (user == MBOX_USER0) { + HAL_CLR_BIT(mbox->IRQ0_EN, HAL_BIT(bit)); + } else { + uint32_t irq_en = mbox->IRQ1_EN; + HAL_CLR_BIT(irq_en, HAL_BIT(bit)); + MBOX_WriteRegister_DMA(&mbox->IRQ1_EN, irq_en); + } +} + +#endif /* __CONFIG_ARCH_APP_CORE */ + +void HAL_MBOX_EnableIRQ(MBOX_T *mbox) +{ + IRQn_Type IRQn; + + IRQn = (mbox == MBOX_A) ? MBOX_A_IRQn : MBOX_N_IRQn; + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(IRQn); +} + +void HAL_MBOX_DisableIRQ(MBOX_T *mbox) +{ + IRQn_Type IRQn; + + IRQn = (mbox == MBOX_A) ? MBOX_A_IRQn : MBOX_N_IRQn; + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_DisableIRQ(IRQn); +} + +#else /* HAL_MBOX_PM_PATCH */ + +void HAL_MBOX_QueueInit(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t regIdx; + uint32_t bit; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = (queue << 3) + (dir == MBOX_DIR_TX ? 4 : 0); + regIdx = bit / MBOX_REG_BITS; + bit = bit % MBOX_REG_BITS; + + /* TODO: may need spinlock to lock this operation */ + if (user == MBOX_USER0) { + HAL_CLR_BIT(mbox->CTRL[regIdx], HAL_BIT(bit)); + } else { + HAL_SET_BIT(mbox->CTRL[regIdx], HAL_BIT(bit)); + } +} + +void HAL_MBOX_QueueEnableIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t bit; + IRQn_Type IRQn; + uint32_t irqEnBits; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = MBOX_GET_IRQ_BIT_POS(queue, dir); + + if (user == MBOX_USER0) { + irqEnBits = mbox->IRQ0_EN; + HAL_SET_BIT(mbox->IRQ0_EN, HAL_BIT(bit)); + } else { + irqEnBits = mbox->IRQ1_EN; + HAL_SET_BIT(mbox->IRQ1_EN, HAL_BIT(bit)); + } + + if (irqEnBits == 0) { + IRQn = (mbox == MBOX_A) ? MBOX_A_IRQn : MBOX_N_IRQn; + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(IRQn); + } +} + +void HAL_MBOX_QueueDisableIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t bit; + IRQn_Type IRQn; + uint32_t irqEnBits; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = MBOX_GET_IRQ_BIT_POS(queue, dir); + + if (user == MBOX_USER0) { + HAL_CLR_BIT(mbox->IRQ0_EN, HAL_BIT(bit)); + irqEnBits = mbox->IRQ0_EN; + } else { + HAL_CLR_BIT(mbox->IRQ1_EN, HAL_BIT(bit)); + irqEnBits = mbox->IRQ1_EN; + } + + if (irqEnBits == 0) { + IRQn = (mbox == MBOX_A) ? MBOX_A_IRQn : MBOX_N_IRQn; + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_DisableIRQ(IRQn); + } +} + +#endif /* HAL_MBOX_PM_PATCH */ + +void HAL_MBOX_QueueDeInit(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + /* Nothing to do */ +} + +int HAL_MBOX_QueueIsPendingIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t bit; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = MBOX_GET_IRQ_BIT_POS(queue, dir); + + if (user == MBOX_USER0) { + return HAL_GET_BIT(mbox->IRQ0_STATUS, HAL_BIT(bit)); + } else { + return HAL_GET_BIT(mbox->IRQ1_STATUS, HAL_BIT(bit)); + } +} + +void HAL_MBOX_QueueClrPendingIRQ(MBOX_T *mbox, MBOX_User user, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t bit; + + HAL_ASSERT_PARAM(user < MBOX_USER_NUM); + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + HAL_ASSERT_PARAM(dir < MBOX_DIR_NUM); + + bit = MBOX_GET_IRQ_BIT_POS(queue, dir); + + if (user == MBOX_USER0) { + HAL_SET_BIT(mbox->IRQ0_STATUS, HAL_BIT(bit)); + } else { + HAL_SET_BIT(mbox->IRQ1_STATUS, HAL_BIT(bit)); + } +} + +int HAL_MBOX_QueueIsFull(MBOX_T *mbox, MBOX_Queue queue) +{ + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + + return HAL_GET_BIT(mbox->FIFO_STATUS[queue], MBOX_QUEUE_FULL_BIT); +} + +uint32_t HAL_MBOX_QueueGetMsgNum(MBOX_T *mbox, MBOX_Queue queue) +{ + HAL_ASSERT_PARAM(queue < MBOX_QUEUE_NUM); + + return HAL_GET_BIT_VAL(mbox->MSG_STATUS[queue], + MBOX_QUEUE_MSG_NUM_SHIFT, + MBOX_QUEUE_MSG_NUM_VMASK); +} + +/* NB: befor put @msg to @queue, make sure @queue is not full */ +void HAL_MBOX_QueuePutMsg(MBOX_T *mbox, MBOX_Queue queue, uint32_t msg) +{ + mbox->MSG[queue] = msg; +} + +/* NB: befor get @msg from @queue, make sure @queue has message */ +uint32_t HAL_MBOX_QueueGetMsg(MBOX_T *mbox, MBOX_Queue queue) +{ + return mbox->MSG[queue]; +} + +__weak void MBOX_IRQCallback(MBOX_T *mbox, MBOX_Queue queue, MBOX_Direction dir) +{ +} + +static void MBOX_IRQHandler(MBOX_T *mbox, MBOX_User user) +{ + uint32_t i; + uint32_t irqPending, irqPendingBackup; + uint32_t isRxPending, isTxPending; + + if (user == MBOX_USER0) { + irqPending = mbox->IRQ0_STATUS & mbox->IRQ0_EN & MBOX_IRQ_ALL_BITS; /* get pending bits */ + HAL_MBOX_DBG("mbox %p, user %d, STATUS 0x%x, EN 0x%x, irqPending 0x%x\n", + mbox, user, mbox->IRQ0_STATUS, mbox->IRQ0_EN, irqPending); + } else { + irqPending = mbox->IRQ1_STATUS & mbox->IRQ1_EN & MBOX_IRQ_ALL_BITS; /* get pending bits */ + HAL_MBOX_DBG("mbox %p, user %d, STATUS 0x%x, EN 0x%x, irqPending 0x%x\n", + mbox, user, mbox->IRQ1_STATUS, mbox->IRQ1_EN, irqPending); + } + irqPendingBackup = irqPending; + + for (i = MBOX_QUEUE_0; i < MBOX_QUEUE_NUM && irqPending != 0; ++i) { + isRxPending = (irqPending & HAL_BIT(0)); + if (isRxPending) { + MBOX_IRQCallback(mbox, i, MBOX_DIR_RX); + } + + isTxPending = (irqPending & HAL_BIT(1)); + if (isTxPending) { + MBOX_IRQCallback(mbox, i, MBOX_DIR_TX); + } + + irqPending >>= 2; + } + + if (user == MBOX_USER0) { + mbox->IRQ0_STATUS = irqPendingBackup; /* clear pending bits */ + } else { + mbox->IRQ1_STATUS = irqPendingBackup; /* clear pending bits */ + } +} + +void MBOX_A_IRQHandler(void) +{ + MBOX_IRQHandler(MBOX_A, MBOX_USER0); +} + +void MBOX_N_IRQHandler(void) +{ + MBOX_IRQHandler(MBOX_N, MBOX_USER1); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_nvic.c b/platform/mcu/xr871/src/driver/chip/hal_nvic.c new file mode 100644 index 0000000000..42dc4b1048 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_nvic.c @@ -0,0 +1,321 @@ +/** + * @file hal_nvic.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal_base.h" +#include "pm/pm.h" +#include "sys/param.h" +#include "sys/xr_debug.h" + +/** + * @brief Set the handler for the specified interrupt + * @param[in] IRQn interrupt number + * @param[in] handler Handler of the specified interrupt + * @return None + */ +void HAL_NVIC_SetIRQHandler(IRQn_Type IRQn, NVIC_IRQHandler handler) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + + vectors[IRQn + NVIC_PERIPH_IRQ_OFFSET] = (uint32_t)handler; +} + +/** + * @brief Get the handler of the specified interrupt + * @param[in] IRQn interrupt number + * @return IRQ Handler of the specified interrupt + */ +NVIC_IRQHandler HAL_NVIC_GetIRQHandler(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + + return (NVIC_IRQHandler)(vectors[IRQn + NVIC_PERIPH_IRQ_OFFSET]); +} + +/** + * @brief Set priority grouping of the NVIC interrupt controller + * @param [in] priorityGroup Priority grouping field + * @return None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t priorityGroup) +{ + NVIC_SetPriorityGrouping(priorityGroup); +} + +/** + * @brief Get Priority Grouping of the NVIC interrupt controller + * @return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Set the interrupt priority of the specified interrupt + * @param[in] IRQn Interrupt number + * @param[in] priority Interrupt priority of the specified interrupt + * @return None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + NVIC_SetPriority(IRQn, priority); +} + +/** + * @brief Get the interrupt priority of the specified interrupt + * @param[in] IRQn Interrupt number + * @return Interrupt priority of the specified interrupt + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Enable external (device-specific) interrupt + * @param[in] IRQn External interrupt number. Value cannot be negative. + * @return None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable external (device-specific) interrupt + * @param[in] IRQn External interrupt number. Value cannot be negative. + * @return None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Set the pending bit of the specified external (device-specific) + * interrupt + * @param[in] IRQn External interrupt number. Value cannot be negative. + * @return None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get the pending status of the specified external (device-specific) + * interrupt + * @param[in] IRQn External interrupt number. Value cannot be negative. + * @return 0 Interrupt status is not pending + * @return 1 Interrupt status is pending + */ +int HAL_NVIC_IsPendingIRQ(IRQn_Type IRQn) +{ + return (int)(NVIC_GetPendingIRQ(IRQn)); +} + +/** + * @brief Clear the pending bit of the specified external (device-specific) + * interrupt + * @param[in] IRQn External interrupt number. Value cannot be negative. + * @return None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC_ClearPendingIRQ(IRQn); +} + +#ifdef CONFIG_PM +struct nvic_regs { + uint32_t vector_table; /* Vector Table Offset */ + uint32_t int_ctrl_state; /* Interrupt Control and State */ + uint32_t app_int; /* Application Interrupt Reset control */ + uint32_t sys_ctrl; /* System control */ + uint32_t config_ctrl; /* Configuration control */ + uint32_t sys_pri[3]; /* System Handler Priority */ + uint32_t sys_hcrs; /* System Handler control and state register */ + uint32_t systick_ctrl; /* SysTick Control Status */ + uint32_t systick_reload; /* SysTick Reload */ + uint32_t int_en[DIV_ROUND_UP(NVIC_VECTOR_TABLE_SIZE, 32)]; /* Interrupt set enable */ + uint8_t int_priority[NVIC_PERIPH_IRQ_NUM * 4]; /* Interrupt priority */ +#ifdef __CONFIG_CPU_CM4F + uint32_t cpacr; /* Coprocessor Access Control Register */ + uint32_t fpccr; /* Floating-Point Context Control Register */ + uint32_t fpcar; /* Floating-Point Context Address Register */ +#endif +}; + +static struct nvic_regs nvic_reg_store; + +static int nvic_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + uint32_t i = 0; + volatile uint32_t *reg_en_addr; + volatile uint8_t *reg_ip_addr; + struct nvic_regs *nvic_back = &nvic_reg_store; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + /* Save the NVIC control registers */ + nvic_back->vector_table = SCB->VTOR; + nvic_back->int_ctrl_state = SCB->ICSR; + nvic_back->app_int = SCB->AIRCR; + nvic_back->sys_ctrl = SCB->SCR; + nvic_back->config_ctrl = SCB->CCR; + reg_en_addr = (volatile uint32_t *)SCB->SHP; + for (i = 0; i < 3; i++) { + nvic_back->sys_pri[i] = reg_en_addr[i]; + } + nvic_back->sys_hcrs = SCB->SHCSR; + + /* Systick registers */ + nvic_back->systick_ctrl = SysTick->CTRL; + nvic_back->systick_reload = SysTick->LOAD; + + /* Save the interrupt enable registers */ + reg_en_addr = NVIC->ISER; + for (i = 0; i < DIV_ROUND_UP(NVIC_VECTOR_TABLE_SIZE, 32); i++) { + nvic_back->int_en[i] = reg_en_addr[i]; + //NVIC->ICER[i] = 0xffffffff; /* disable all ints */ + } + + /* Save the interrupt priority registers */ + reg_ip_addr = NVIC->IP; + for (i = 0; i < sizeof(nvic_back->int_priority); i++) { + nvic_back->int_priority[i] = reg_ip_addr[i]; + } +#ifdef __CONFIG_CPU_CM4F + nvic_back->cpacr = SCB->CPACR; + nvic_back->fpccr = FPU->FPCCR; + nvic_back->fpcar = FPU->FPCAR; +#endif + HAL_DBG("%s okay\n", __func__); + break; + default: + break; + } + + return 0; +} + +static int nvic_resume(struct soc_device *dev, enum suspend_state_t state) +{ + uint32_t i = 0; + volatile uint32_t *reg_en_addr; + volatile uint8_t *reg_ip_addr; + struct nvic_regs *nvic_back = &nvic_reg_store; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + /* Restore the NVIC control registers */ + SCB->VTOR = nvic_back->vector_table; + SCB->AIRCR = (nvic_back->app_int & 0x0ffff) | (0x5FA << SCB_AIRCR_VECTKEY_Pos); + SCB->SCR = nvic_back->sys_ctrl; + SCB->CCR = nvic_back->config_ctrl; + reg_en_addr = (volatile uint32_t *)SCB->SHP; + for (i = 0; i < 3; i++) { + reg_en_addr[i] = nvic_back->sys_pri[i]; + } + SCB->SHCSR = nvic_back->sys_hcrs; + + /* Systick registers */ + SysTick->CTRL = nvic_back->systick_ctrl; + SysTick->LOAD = nvic_back->systick_reload; + + /* Restore the interrupt priority registers */ + reg_ip_addr = NVIC->IP; + for (i = 0; i < sizeof(nvic_back->int_priority); i++) { + reg_ip_addr[i] = nvic_back->int_priority[i]; + } + + /* Restore the interrupt enable registers */ + reg_en_addr = NVIC->ISER; + for (i = 0; i < DIV_ROUND_UP(NVIC_VECTOR_TABLE_SIZE, 32); i++) { + reg_en_addr[i] = nvic_back->int_en[i]; + } +#ifdef __CONFIG_CPU_CM4F + SCB->CPACR = nvic_back->cpacr; + FPU->FPCCR = nvic_back->fpccr; + FPU->FPCAR = nvic_back->fpcar; +#endif + __asm(" dsb \n"); + __asm(" isb \n"); + HAL_DBG("%s okay\n", __func__); + break; + default: + break; + } + + return 0; +} + +void nvic_print_regs(void) +{ + //hex_dump_bytes(&nvic_reg_store, sizeof(nvic_reg_store)); +} + +static struct soc_device_driver nvic_drv = { + .name = "nvic", + .suspend_noirq = nvic_suspend, + .resume_noirq = nvic_resume, +}; + +static struct soc_device nvic_dev = { + .name = "nvic", + .driver = &nvic_drv, +}; + +#define NVIC_DEV (&nvic_dev) +#endif + +/** + * @brief Initialize the NVIC module + * @return None + */ +void HAL_NVIC_Init(void) +{ + /* Enable some system fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk; + +#ifdef CONFIG_PM + pm_register_ops(NVIC_DEV); +#endif +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_os.h b/platform/mcu/xr871/src/driver/chip/hal_os.h new file mode 100644 index 0000000000..f8e5498767 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_os.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_HAL_OS_H_ +#define _DRIVER_CHIP_HAL_OS_H_ + +#include "kernel/os/os.h" +#include "sys/interrupt.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* IRQ disable/enable */ +__STATIC_INLINE void HAL_DisableIRQ(void) +{ + arch_irq_disable(); +} + +__STATIC_INLINE void HAL_EnableIRQ(void) +{ + arch_irq_enable(); +} + +/* Critical Sections */ +__STATIC_INLINE unsigned long HAL_EnterCriticalSection(void) +{ + return arch_irq_save(); // temp implementation +} + +__STATIC_INLINE void HAL_ExitCriticalSection(unsigned long flags) +{ + arch_irq_restore(flags); // temp implementation +} + +/* Semaphore */ +typedef OS_Semaphore_t HAL_Semaphore; + +__STATIC_INLINE HAL_Status HAL_SemaphoreInit(HAL_Semaphore *sem, uint32_t initCount, uint32_t maxCount) +{ + return OS_SemaphoreCreate(sem, initCount, maxCount) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_SemaphoreInitBinary(HAL_Semaphore *sem) +{ + return OS_SemaphoreCreateBinary(sem) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_SemaphoreDeinit(HAL_Semaphore *sem) +{ + return OS_SemaphoreDelete(sem) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_SemaphoreWait(HAL_Semaphore *sem, uint32_t msec) +{ + return OS_SemaphoreWait(sem, msec) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_SemaphoreRelease(HAL_Semaphore *sem) +{ + return OS_SemaphoreRelease(sem) == OS_OK ? HAL_OK : HAL_ERROR; +} + +/* Mutex */ +typedef OS_Mutex_t HAL_Mutex; + +__STATIC_INLINE HAL_Status HAL_MutexInit(HAL_Mutex *mtx) +{ + return OS_MutexCreate(mtx) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_MutexDeinit(HAL_Mutex *mtx) +{ + return OS_MutexDelete(mtx) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_MutexLock(HAL_Mutex *mtx, uint32_t msec) +{ + return OS_MutexLock(mtx, msec) == OS_OK ? HAL_OK : HAL_ERROR; +} + +__STATIC_INLINE HAL_Status HAL_MutexUnlock(HAL_Mutex *mtx) +{ + return OS_MutexUnlock(mtx) == OS_OK ? HAL_OK : HAL_ERROR; +} + +/* time */ +__STATIC_INLINE uint32_t HAL_Ticks(void) +{ + return OS_GetTicks(); +} + +__STATIC_INLINE void HAL_MSleep(uint32_t msec) +{ + OS_MSleep(msec); +} + +#define HAL_SecsToTicks(sec) OS_SecsToTicks(sec) +#define HAL_MSecsToTicks(msec) OS_MSecsToTicks(msec) +#define HAL_TicksToMSecs(t) OS_TicksToMSecs(t) +#define HAL_TicksToSecs(t) OS_TicksToSecs(t) + +#define HAL_TimeAfter(a, b) OS_TimeAfter(a, b) +#define HAL_TimeBefore(a, b) OS_TimeAfter(b, a) +#define HAL_TimeAfterEqual(a, b) OS_TimeAfterEqual(a, b) +#define HAL_TimeBeforeEqual(a, b) OS_TimeAfterEqual(b, a) + +/* memory */ +#define HAL_Malloc(l) malloc(l) +#define HAL_Free(p) free(p) +#define HAL_Memcpy(d, s, l) memcpy(d, s, l) +#define HAL_Memset(d, c, l) memset(d, c, l) +#define HAL_Memcmp(a, b, l) memcmp(a, b, l) +#define HAL_Memmove(d, s, n) memmove(d, s, n) + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_HAL_OS_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/hal_prcm.c b/platform/mcu/xr871/src/driver/chip/hal_prcm.c new file mode 100644 index 0000000000..3febe995ad --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_prcm.c @@ -0,0 +1,665 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_prcm.h" +#include "hal_base.h" + +/* + * Power + * - DCDC + * - Power switch + * - LDO + */ +void HAL_PRCM_SetDCDCVoltage(PRCM_DCDCVolt volt) +{ + HAL_MODIFY_REG(PRCM->SYS_DCDC_CTRL, PRCM_DCDC_VOLT_MASK, volt); +} + +uint32_t HAL_PRCM_GetSysPowerEnableFlags(void) +{ + return HAL_GET_BIT(PRCM->SYS_LDO_SW_CTRL, + PRCM_SYS1_PWR1_EN_BIT | + PRCM_SYS1_PWR2_EN_BIT | + PRCM_SYS2_PWR3_EN_BIT | + PRCM_SYS3_PWR4_EN_BIT | + PRCM_SYS3_PWR5_EN_BIT | + PRCM_SYS1_SRAM_PWR1_EN_BIT | + PRCM_SYS2_SRAM_PWR2_EN_BIT | + PRCM_SYS3_SRAM_PWR3_EN_BIT); +} + +void HAL_PRCM_EnableSys2Power(void) +{ + HAL_SET_BIT(PRCM->SYS_LDO_SW_CTRL, + PRCM_SYS2_PWR3_EN_BIT | PRCM_SYS2_SRAM_PWR2_EN_BIT); +} + +void HAL_PRCM_DisableSys2Power(void) +{ + HAL_CLR_BIT(PRCM->SYS_LDO_SW_CTRL, + PRCM_SYS2_PWR3_EN_BIT | PRCM_SYS2_SRAM_PWR2_EN_BIT); +} + +void HAL_PRCM_SetLDO1Voltage(PRCM_LDO1Volt volt) +{ + HAL_MODIFY_REG(PRCM->SYS_LDO_SW_CTRL, PRCM_LDO1_VOLT_MASK, volt); +} + +uint32_t HAL_PRCM_GetLDOEnableFlags(void) +{ + return HAL_GET_BIT(PRCM->SYS_LDO_SW_CTRL, + PRCM_LDO1_EN_BIT | + PRCM_PLL_LDO_EN_BIT | + PRCM_SRAM_LDO_EN_BIT); +} + +/* + * Clock + */ +void HAL_PRCM_SetLFCLKSource(PRCM_LFCLKSrc src) +{ + /* always enable inter 32K */ + uint32_t clr_mask = PRCM_LFCLK_SRC_MASK | PRCM_LFCLK_EXT32K_EN_BIT; + uint32_t set_mask = src | PRCM_LFCLK_INTER32K_EN_BIT; + if (src == PRCM_LFCLK_SRC_EXT32K) { + set_mask |= PRCM_LFCLK_EXT32K_EN_BIT; + } + HAL_MODIFY_REG(PRCM->SYS_LFCLK_CTRL, clr_mask, set_mask); +} + +void HAL_PRCM_SetHOSCType(PRCM_HOSCType type) +{ + HAL_MODIFY_REG(PRCM->SYS_HOSC_CTRL, PRCM_HOSC_TYPE_MASK, type); +} + +uint32_t HAL_PRCM_GetHOSCType(void) +{ + return HAL_GET_BIT(PRCM->SYS_HOSC_CTRL, PRCM_HOSC_TYPE_MASK); +} + +uint32_t HAL_PRCM_GetHFClock(void) +{ + static const uint32_t PRCM_HOSCClock[] = + { HOSC_CLOCK_26M, HOSC_CLOCK_40M, HOSC_CLOCK_24M, HOSC_CLOCK_52M }; + + uint32_t val; + + val = HAL_GET_BIT_VAL(PRCM->SYS_HOSC_CTRL, + PRCM_HOSC_TYPE_SHIFT, + PRCM_HOSC_TYPE_VMASK); + return PRCM_HOSCClock[val]; +} + +uint32_t HAL_PRCM_GetInter32KFreq(void) +{ + return (10 * HAL_GET_BIT_VAL(PRCM->SYS_RCOSC_CALIB_CTRL, + PRCM_RCOSC_CALIB_FREQ_SHIFT, + PRCM_RCOSC_CALIB_FREQ_VMASK)); +} + +uint32_t HAL_PRCM_EnableInter32KCalib(void) +{ + return HAL_SET_BIT(PRCM->SYS_RCOSC_CALIB_CTRL, PRCM_RCOSC_CALIB_EN_BIT); +} + +uint32_t HAL_PRCM_DisableInter32KCalib(void) +{ + return HAL_CLR_BIT(PRCM->SYS_RCOSC_CALIB_CTRL, PRCM_RCOSC_CALIB_EN_BIT); +} + +#if 0 +void HAL_PRCM_SetSysPLLParam(PRCM_SysPLLParam param) +{ + HAL_MODIFY_REG(PRCM->SYS_PLL_CTRL, PRCM_SYS_PLL_PARAM_MASK, param); +} + +void HAL_PRCM_EnableSysPLL(void) +{ + HAL_SET_BIT(PRCM->SYS_PLL_CTRL, PRCM_SYS_PLL_EN_BIT); +} +#else +void HAL_PRCM_SetSysPLL(PRCM_SysPLLParam param) +{ + PRCM->SYS_PLL_CTRL = PRCM_SYS_PLL_EN_BIT | param; /* NB: enable system PLL */ +} +#endif + +void HAL_PRCM_DisableSysPLL(void) +{ + HAL_CLR_BIT(PRCM->SYS_PLL_CTRL, PRCM_SYS_PLL_EN_BIT); +} + +void HAL_PRCM_SetCPUAClk(PRCM_CPUClkSrc src, PRCM_SysClkFactor factor) +{ + switch (src) { + case PRCM_CPU_CLK_SRC_HFCLK: + HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_CPU_CLK_SRC_MASK, PRCM_CPU_CLK_SRC_HFCLK); + break; + case PRCM_CPU_CLK_SRC_LFCLK: + HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_CPU_CLK_SRC_MASK, PRCM_CPU_CLK_SRC_LFCLK); + break; + case PRCM_CPU_CLK_SRC_SYSCLK: + default: +#if 1 + HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_FACTOR_MASK, factor); + HAL_SET_BIT(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_EN_BIT); + HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_CPU_CLK_SRC_MASK, PRCM_CPU_CLK_SRC_SYSCLK); +#else + PRCM->SYS_CLK1_CTRL = PRCM_SYS_CLK_EN_BIT | factor | PRCM_CPU_CLK_SRC_SYSCLK; +#endif + break; + } +} + +void HAL_PRCM_DisCLK1(PRCM_SysClkFactor factor) +{ + HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_FACTOR_MASK, factor); + HAL_CLR_BIT(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_EN_BIT); +} + +uint32_t HAL_PRCM_GetCPUAClk(void) +{ + uint32_t reg = PRCM->SYS_CLK1_CTRL; + uint32_t freq, div; + + switch (reg & PRCM_CPU_CLK_SRC_MASK) { + case PRCM_CPU_CLK_SRC_HFCLK: + freq = HAL_GetHFClock(); + break; + case PRCM_CPU_CLK_SRC_LFCLK: + freq = HAL_GetLFClock(); + break; + case PRCM_CPU_CLK_SRC_SYSCLK: + default: + div = HAL_GET_BIT_VAL(reg, + PRCM_SYS_CLK_FACTOR_SHIFT, + PRCM_SYS_CLK_FACTOR_VMASK) + 1; + freq = SYS_PLL_CLOCK / div; + break; + } + return freq; +} + +void HAL_PRCM_SetAudioPLLParam(PRCM_AudPLLParam param) +{ + PRCM->AUD_PLL_CTRL = param; /* NB: it will disable system PLL */ +} + +void HAL_PRCM_EnableAudioPLL(void) +{ + HAL_SET_BIT(PRCM->AUD_PLL_CTRL, PRCM_AUD_PLL_EN_BIT); +} + +void HAL_PRCM_DisableAudioPLL(void) +{ + HAL_CLR_BIT(PRCM->AUD_PLL_CTRL, PRCM_AUD_PLL_EN_BIT); +} + +void HAL_PRCM_SetDevClock(PRCM_DevClkFactor factor) +{ + PRCM->DEV_CLK_CTRL = factor; +} + +uint32_t HAL_PRCM_GetDevClock(void) +{ + uint32_t div = HAL_GET_BIT_VAL(PRCM->DEV_CLK_CTRL, + PRCM_DEV_CLK_FACTOR_SHIFT, + PRCM_DEV_CLK_FACTOR_VMASK) + 1; + return (SYS_PLL_CLOCK / div); +} + +void HAL_PRCM_SetAudioPLLPatternParam(PRCM_AudPLLPatParam param) +{ + PRCM->AUD_PLL_PAT_CTRL = param; /* NB: it will disable system PLL */ +} + +void HAL_PRCM_EnableAudioPLLPattern(void) +{ + HAL_SET_BIT(PRCM->AUD_PLL_PAT_CTRL, PRCM_AUD_DIG_DELT_PAT_EN_BIT); +} + +void HAL_PRCM_DisableAudioPLLPattern(void) +{ + HAL_CLR_BIT(PRCM->AUD_PLL_PAT_CTRL, PRCM_AUD_DIG_DELT_PAT_EN_BIT); +} + +int HAL_PRCM_IsCPUAResetRelease(void) +{ + return HAL_GET_BIT(PRCM->SYS1_CTRL, PRCM_CPUA_RESET_BIT); +} + +int HAL_PRCM_IsSys1ResetRelease(void) +{ + return HAL_GET_BIT(PRCM->SYS1_CTRL, PRCM_SYS1_RESET_BIT); +} + +void HAL_PRCM_AllowCPUNDeepSleep(void) +{ + HAL_CLR_BIT(PRCM->SYS1_STATUS, PRCM_CPUN_DEEPSLEEP_LOCK_BIT); +} + +void HAL_PRCM_DisallowCPUNDeepSleep(void) +{ + HAL_SET_BIT(PRCM->SYS1_STATUS, PRCM_CPUN_DEEPSLEEP_LOCK_BIT); +} + +int HAL_PRCM_IsCPUNDeepSleepAllowed(void) +{ + return !HAL_GET_BIT(PRCM->SYS1_STATUS, PRCM_CPUN_DEEPSLEEP_LOCK_BIT); +} + +int HAL_PRCM_IsCPUASleep(void) +{ + return HAL_GET_BIT(PRCM->SYS1_STATUS, PRCM_CPUA_SLEEP_STATUS_BIT); +} + +int HAL_PRCM_IsCPUADeepSleep(void) +{ + return HAL_GET_BIT(PRCM->SYS1_STATUS, PRCM_CPUA_DEEPSLEEP_STATUS_BIT); +} + +int HAL_PRCM_IsSys1Alive(void) +{ + return HAL_GET_BIT(PRCM->SYS1_STATUS, PRCM_SYS1_ALIVE_BIT); +} + +void HAL_PRCM_DisableSys2(void) +{ + HAL_CLR_BIT(PRCM->SYS2_CTRL, PRCM_SYS2_ISOLATION_EN_BIT | + PRCM_CPUN_RESET_BIT | + PRCM_SYS2_RESET_BIT); +} + +void HAL_PRCM_EnableSys2Isolation(void) +{ + HAL_CLR_BIT(PRCM->SYS2_CTRL, PRCM_SYS2_ISOLATION_EN_BIT); +} + +void HAL_PRCM_DisableSys2Isolation(void) +{ + HAL_SET_BIT(PRCM->SYS2_CTRL, PRCM_SYS2_ISOLATION_EN_BIT); +} + +void HAL_PRCM_ForceCPUNReset(void) +{ + HAL_CLR_BIT(PRCM->SYS2_CTRL, PRCM_CPUN_RESET_BIT); +} + +void HAL_PRCM_ReleaseCPUNReset(void) +{ + HAL_SET_BIT(PRCM->SYS2_CTRL, PRCM_CPUN_RESET_BIT); +} + +int HAL_PRCM_IsCPUNReleased(void) +{ + return HAL_GET_BIT(PRCM->SYS2_CTRL, PRCM_CPUN_RESET_BIT); +} + +void HAL_PRCM_ForceSys2Reset(void) +{ + HAL_CLR_BIT(PRCM->SYS2_CTRL, PRCM_SYS2_RESET_BIT); +} + +void HAL_PRCM_ReleaseSys2Reset(void) +{ + HAL_SET_BIT(PRCM->SYS2_CTRL, PRCM_SYS2_RESET_BIT); +} + +int HAL_PRCM_IsCPUADeepSleepAllowed(void) +{ + return !HAL_GET_BIT(PRCM->SYS2_STATUS, PRCM_CPUA_DEEPSLEEP_LOCK_BIT); +} + +int HAL_PRCM_IsCPUNSleep(void) +{ + return HAL_GET_BIT(PRCM->SYS2_STATUS, PRCM_CPUN_SLEEP_STATUS_BIT); +} + +int HAL_PRCM_IsCPUNDeepSleep(void) +{ + return HAL_GET_BIT(PRCM->SYS2_STATUS, PRCM_CPUN_DEEPSLEEP_STATUS_BIT); +} + +int HAL_PRCM_IsSys2Alive(void) +{ + return HAL_GET_BIT(PRCM->SYS2_STATUS, PRCM_SYS2_ALIVE_BIT); +} + +int HAL_PRCM_IsSys3Alive(void) +{ + return HAL_GET_BIT(PRCM->SYS3_STATUS, PRCM_SYS3_ALIVE_BIT); +} + +void HAL_PRCM_SetSys1WakeupPowerFlags(uint32_t flags) +{ + PRCM->SYS1_WAKEUP_CTRL = flags & PRCM_SYS_WS_PWR_FLAGS_MASK; +} + +uint32_t HAL_PRCM_GetSys2WakeupPowerFlags(void) +{ + return (PRCM->SYS2_WAKEUP_CTRL & PRCM_SYS_WS_PWR_FLAGS_MASK); +} + +uint32_t HAL_PRCM_GetSys1SleepPowerFlags(void) +{ + return (PRCM->SYS1_SLEEP_CTRL & PRCM_SYS_WS_PWR_FLAGS_MASK); +} + +void HAL_PRCM_SetSys1SleepPowerFlags(uint32_t flags) +{ + PRCM->SYS1_SLEEP_CTRL = flags & PRCM_SYS_WS_PWR_FLAGS_MASK; +} + +uint32_t HAL_PRCM_GetSys2SleepPowerFlags(void) +{ + return (PRCM->SYS2_SLEEP_CTRL & PRCM_SYS_WS_PWR_FLAGS_MASK); +} + +void HAL_PRCM_SetSRAMVoltage(PRCM_SRAMVolt workVolt, PRCM_SRAMVolt retenVolt) +{ + PRCM->SRAM_VOLT_CTRL = + ((workVolt << PRCM_SRAM_WORK_VOLT_SHIFT) & PRCM_SRAM_WORK_VOLT_MASK) | + ((retenVolt << PRCM_SRAM_RETEN_VOLT_SHIFT) & PRCM_SRAM_RETEN_VOLT_MASK); +} + +void HAL_PRCM_SetBANDGAPSTABLE_TIME(uint32_t time) +{ + PRCM->BANDGAP_STABLE_REF_TIME = (time & PRCM_BANDGAP_STABLE_REF_TIME_MASK); +} + +uint32_t HAL_PRCM_GetBANDGAPSTABLE_TIME(void) +{ + return (PRCM->BANDGAP_STABLE_REF_TIME & PRCM_BANDGAP_STABLE_REF_TIME_MASK); +} + +void HAL_PRCM_SetDCDCSTABLE_TIME(uint32_t time) +{ + PRCM->DCDC_STABLE_REF_TIME = (time & PRCM_DCDC_STABLE_REF_TIME_MASK); +} + +uint32_t HAL_PRCM_GetDCDCSTABLE_TIME(void) +{ + return (PRCM->DCDC_STABLE_REF_TIME & PRCM_DCDC_STABLE_REF_TIME_MASK); +} + +void HAL_PRCM_SetCPUABootFlag(PRCM_CPUABootFlag flag) +{ + PRCM->CPUA_BOOT_FLAG = PRCM_CPUA_BOOT_FLAG_WR_LOCK | flag; +} + +uint32_t HAL_PRCM_GetCPUABootFlag(void) +{ + return HAL_GET_BIT(PRCM->CPUA_BOOT_FLAG, PRCM_CPUA_BOOT_FLAG_MASK); +} + +void HAL_PRCM_SetCPUABootAddr(uint32_t addr) +{ + PRCM->CPUA_BOOT_ADDR = addr; +} + +uint32_t HAL_PRCM_GetCPUABootAddr(void) +{ + return PRCM->CPUA_BOOT_ADDR; +} + +void HAL_PRCM_SetCPUABootArg(uint32_t arg) +{ + PRCM->CPUA_BOOT_ARG = arg; +} + +uint32_t HAL_PRCM_GetCPUABootArg(void) +{ + return PRCM->CPUA_BOOT_ARG; +} + +void HAL_PRCM_SetCPUAPrivateData(uint32_t data) +{ + PRCM->CPUA_PRIV_REG = data; +} + +uint32_t HAL_PRCM_GetCPUAPrivateData(void) +{ + return PRCM->CPUA_PRIV_REG; +} + +uint32_t HAL_PRCM_GetWakeupTimerEnable(void) +{ + return (PRCM->CPUA_WAKE_TIMER_CNT & PRCM_CPUx_WAKE_TIMER_EN_BIT); +} + +void HAL_PRCM_WakeupTimerEnable(void) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_TIMER_CNT, PRCM_CPUx_WAKE_TIMER_EN_BIT); +} + +void HAL_PRCM_WakeupTimerDisable(void) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_TIMER_CNT, PRCM_CPUx_WAKE_TIMER_EN_BIT); +} + +uint32_t HAL_PRCM_WakeupTimerGetCurrentValue(void) +{ + return (PRCM->CPUA_WAKE_TIMER_CNT & PRCM_CPUx_WAKE_TIMER_CUR_VAL_MASK); +} + +uint32_t HAL_PRCM_GetWakeupTimerPending(void) +{ + return (PRCM->CPUA_WAKE_TIMER_CMP & PRCM_CPUx_WAKE_TIMER_PENDING_BIT); +} + +void HAL_PRCM_ClearWakeupTimerPending(void) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_TIMER_CMP, PRCM_CPUx_WAKE_TIMER_PENDING_BIT); +} + +void HAL_PRCM_WakeupTimerSetCompareValue(uint32_t val) +{ + PRCM->CPUA_WAKE_TIMER_CMP = val & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK; +} + +uint32_t HAL_PRCM_WakeupTimerGetCompareValue(void) +{ + return (PRCM->CPUA_WAKE_TIMER_CMP & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK); +} + +#if 0 +uint32_t HAL_PRCM_GetCPUNWakeupTimerCurrentValue(void) +{ + return (PRCM->CPUN_WAKE_TIMER_CNT & PRCM_CPUx_WAKE_TIMER_CUR_VAL_MASK); +} + +void HAL_PRCM_SetCPUNWakeupTimerCompareValue(uint32_t val) +{ + PRCM->CPUN_WAKE_TIMER_CMP = val & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK); +} + +uint32_t HAL_PRCM_GetCPUNWakeupTimerCompareValue(void) +{ + return (PRCM->CPUN_WAKE_TIMER_CMP & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK); +} +#endif + +void HAL_PRCM_WakeupIOEnable(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_EN, ioMask); +} + +void HAL_PRCM_WakeupIODisable(uint32_t ioMask) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_EN, ioMask); +} + +void HAL_PRCM_WakeupIOSetRisingEvent(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_MODE, ioMask); +} + +void HAL_PRCM_WakeupIOSetFallingEvent(uint32_t ioMask) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_MODE, ioMask); +} + +uint32_t HAL_PRCM_WakeupIOGetEventStatus(void) +{ + return HAL_GET_BIT(PRCM->CPUA_WAKE_IO_STATUS, PRCM_WAKE_IO_MASK); +} + +int HAL_PRCM_WakeupIOIsEventDetected(uint32_t ioMask) +{ + return HAL_GET_BIT(PRCM->CPUA_WAKE_IO_STATUS, ioMask); +} + +void HAL_PRCM_WakeupIOClearEventDetected(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_STATUS, ioMask); +} + +void HAL_PRCM_WakeupIOEnableCfgHold(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_HOLD, ioMask); +} + +void HAL_PRCM_WakeupIODisableCfgHold(uint32_t ioMask) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_HOLD, ioMask); +} + +void HAL_PRCM_WakeupIOEnableGlobal(void) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_GLOBAL_EN, PRCM_WAKE_IO_GLOBAL_EN_BIT); +} + +void HAL_PRCM_WakeupIODisableGlobal(void) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_GLOBAL_EN, PRCM_WAKE_IO_GLOBAL_EN_BIT); +} + +void HAL_PRCM_Start(void) +{ + HAL_CLR_BIT(PRCM->CPUA_PRCM_REG, PRCM_CPUA_PRCM_REG_BIT); +} + +#if 0 +void HAL_PRCM_EnableCPUAWakeupTimer(void) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_TIMER_CNT, PRCM_CPUx_WAKE_TIMER_EN_BIT); +} + +void HAL_PRCM_DisableCPUAWakeupTimer(void) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_TIMER_CNT, PRCM_CPUx_WAKE_TIMER_EN_BIT); +} + +uint32_t HAL_PRCM_GetCPUAWakeupTimerCurrentValue(void) +{ + return (PRCM->CPUA_WAKE_TIMER_CNT & PRCM_CPUx_WAKE_TIMER_CUR_VAL_MASK); +} + +void HAL_PRCM_SetCPUAWakeupTimerCompareValue(uint32_t val) +{ + PRCM->CPUA_WAKE_TIMER_CMP = val & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK; +} + +uint32_t HAL_PRCM_GetCPUAWakeupTimerCompareValue(void) +{ + return (PRCM->CPUA_WAKE_TIMER_CMP & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK); +} + +#if 0 +uint32_t HAL_PRCM_GetCPUNWakeupTimerCurrentValue(void) +{ + return (PRCM->CPUN_WAKE_TIMER_CNT & PRCM_CPUx_WAKE_TIMER_CUR_VAL_MASK); +} + +void HAL_PRCM_SetCPUNWakeupTimerCompareValue(uint32_t val) +{ + PRCM->CPUN_WAKE_TIMER_CMP = val & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK); +} + +uint32_t HAL_PRCM_GetCPUNWakeupTimerCompareValue(void) +{ + return (PRCM->CPUN_WAKE_TIMER_CMP & PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK); +} +#endif + +void HAL_PRCM_EnableWakeupIO(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_EN, ioMask); +} + +void HAL_PRCM_DisableWakeupIO(uint32_t ioMask) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_EN, ioMask); +} + +void HAL_PRCM_SetWakeupIORisingEvent(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_MODE, ioMask); +} + +void HAL_PRCM_SetWakeupIOFallingEvent(uint32_t ioMask) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_MODE, ioMask); +} + +uint32_t HAL_PRCM_GetWakeupIOEventStatus(void) +{ + return HAL_GET_BIT(PRCM->CPUA_WAKE_IO_STATUS, PRCM_WAKE_IO_MASK); +} + +int HAL_PRCM_IsWakeupIOEventDetected(uint32_t ioMask) +{ + return HAL_GET_BIT(PRCM->CPUA_WAKE_IO_STATUS, ioMask); +} + +void HAL_PRCM_ClearWakeupIOEventDetected(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_STATUS, ioMask); +} + +void HAL_PRCM_EnableWakeupIOCfgHold(uint32_t ioMask) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_HOLD, ioMask); +} + +void HAL_PRCM_DisableWakeupIOCfgHold(uint32_t ioMask) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_HOLD, ioMask); +} + +void HAL_PRCM_EnableWakeupIOGlobal(void) +{ + HAL_SET_BIT(PRCM->CPUA_WAKE_IO_GLOBAL_EN, PRCM_WAKE_IO_GLOBAL_EN_BIT); +} + +void HAL_PRCM_DisableWakeupIOGlobal(void) +{ + HAL_CLR_BIT(PRCM->CPUA_WAKE_IO_GLOBAL_EN, PRCM_WAKE_IO_GLOBAL_EN_BIT); +} +#endif diff --git a/platform/mcu/xr871/src/driver/chip/hal_pwm.c b/platform/mcu/xr871/src/driver/chip/hal_pwm.c new file mode 100644 index 0000000000..e6863ab773 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_pwm.c @@ -0,0 +1,955 @@ +/** + * @file hal_pwm.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "kernel/os/os.h" +#include "hal_base.h" +#include "driver/chip/hal_pwm.h" + +#define DBG_PWM 0 +#define PWM_DBG(fmt, arg...) \ + HAL_LOG(HAL_DBG_ON && DBG_PWM, "[HAL PWM] "fmt, ##arg) + + +#define MAXCNTRVAL 65535 +#define RISECH(ch) (HAL_BIT(ch) * HAL_BIT(ch)) +#define FALLCH(ch) (HAL_BIT(ch) * HAL_BIT(ch) * 2) +#define PWM_IRQ_ALL_BITS ((1 << (PWM_CH_NUM << 1)) - 1) + +static uint32_t Cap_priv = 0; +static uint8_t IoInitCount = 0; +static PWM_IrqParam PWM_IrqPrivate[8]; + +/** + * @internal + * @brief eanble pwm module. + * @note This function is used to enable the pwm module source clock. + * @param none. + * @retval none. + */ +static void PWM_ModuleEnable() +{ + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_PWM); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_PWM); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_PWM); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_PWM); +} + +/** + * @internal + * @brief disable pwm module. + * @note This function is used to disable the pwm module source clock. + * @param none. + * @retval none. + */ +static void PWM_ModuleDisable() +{ + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_PWM); +} + +static void PWM_EnableModuleIRQ() +{ + HAL_NVIC_SetPriority(PWM_ECT_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(PWM_ECT_IRQn); +} + +static void PWM_DisableModuleIRQ() +{ + HAL_NVIC_DisableIRQ(PWM_ECT_IRQn); +} + +static PWM_GROUP_ID PWM_ChToGroup(PWM_CH_ID ch_id) +{ + if (ch_id >= PWM_CH_NUM) + return PWM_GROUP_NULL; + + return ch_id / 2; +} + +static PWM_CH_ID PWM_GroupToCh0(PWM_GROUP_ID group_id) +{ + if (group_id >= PWM_GROUP_NUM) + return PWM_GROUP_NULL; + + return group_id * 2; +} + +static PWM_CH_ID PWM_GroupToCh1(PWM_GROUP_ID group_id) +{ + if (group_id >= PWM_GROUP_NUM) + return PWM_GROUP_NULL; + + return group_id * 2 + 1; +} + +static uint32_t PWM_ReadGroupClkFreq(PWM_GROUP_ID group_id) +{ + if (group_id >= PWM_GROUP_NUM) + return 0; + + uint32_t src_clk_freq = 0; + __IO uint32_t *reg = &PWM->PCCR[group_id]; + uint32_t clk = *reg & PWM_SRC_CLK_SELECT; + uint32_t div = *reg & PWM_SRC_CLK_DIV_V; + + if (clk == 0) { + src_clk_freq = HAL_GetHFClock(); + PWM_DBG("%s, %d HRCLK\n", __func__, __LINE__); + } else { + src_clk_freq = HAL_GetAPBClock(); + PWM_DBG("%s, %d APBCLK\n", __func__, __LINE__); + } + + src_clk_freq /= (1 << div); + + return src_clk_freq; +} + + +static int PWM_ChClkDiv(PWM_CH_ID ch_id, PWM_ChInitParam *param) +{ + if (ch_id >= PWM_CH_NUM) + return 0; + + int ch_clk_freq = 1; + uint32_t minFreq = 0; + uint8_t ch_div = 0; + uint32_t temp1 = 0, temp2 = 0; + __IO uint32_t *reg = NULL; + uint32_t src_clk_freq = PWM_ReadGroupClkFreq(PWM_ChToGroup(ch_id)); + + PWM_DBG("SRC_CLK freq = %d\n", src_clk_freq); + + if ((src_clk_freq % MAXCNTRVAL) > 0) + temp1 = 1; + if (((src_clk_freq + temp1) % 256) > 0) + temp2 = 1; + + minFreq = (src_clk_freq / MAXCNTRVAL + temp1)/ 256 + temp2; + + if (param->hz > src_clk_freq || param->hz < minFreq) + ch_clk_freq = 0; + + if (param->hz > (src_clk_freq / MAXCNTRVAL + temp1)) + ch_div = 0; + else { + ch_div = (src_clk_freq / MAXCNTRVAL + temp1) % param->hz; + if (ch_div) + ch_div = (src_clk_freq / MAXCNTRVAL + temp1) / param->hz; + else + ch_div = (src_clk_freq / MAXCNTRVAL + temp1) / param->hz - 1; + } + + + PWM_DBG("ch div = %d\n", ch_div); + + reg = &PWM->CH_REG[ch_id].PCR; + + if (ch_div > 255) + return 0; + + uint32_t temp = *reg; + temp &= ~PWM_PCR_PRESCAL; + temp |= ch_div; + *reg = temp; //Source clock Frequency Division + + if (ch_clk_freq != 0) + ch_clk_freq = src_clk_freq / (ch_div + 1); + + return ch_clk_freq; +} + + +static void PWM_ChSetPolarity(PWM_CH_ID ch_id, PWM_ChInitParam *param) +{ + if (ch_id >= PWM_CH_NUM) + return; + + __IO uint32_t *reg = NULL; + + reg = &PWM->CH_REG[ch_id].PCR; + + if (param->polarity == PWM_LOWLEVE) + HAL_CLR_BIT(*reg, PWM_PCR_ACT_STA); + else if (param->polarity == PWM_HIGHLEVE) + HAL_SET_BIT(*reg, PWM_PCR_ACT_STA); +} + +static void PWM_ChSetMode(PWM_CH_ID ch_id, PWM_ChInitParam *param) +{ + if (ch_id >= PWM_CH_NUM) + return; + + __IO uint32_t *reg = NULL; + reg = &PWM->CH_REG[ch_id].PCR; + + if (param->mode == PWM_PLUSE_MODE) + HAL_SET_BIT(*reg, PWM_PCR_MODE); + else if (param->mode == PWM_CYCLE_MODE) + HAL_CLR_BIT(*reg, PWM_PCR_MODE); +} + +static int PWM_OutPeriodRady(PWM_CH_ID ch_id) +{ + if (ch_id >= PWM_CH_NUM) + return -1; + __IO uint32_t *reg = NULL; + reg = &PWM->CH_REG[ch_id].PCR; + + return HAL_GET_BIT(*reg, PWM_PCR_PERIODRDY); + +} + +static void PWM_OutSetCycle(PWM_CH_ID ch_id, uint16_t value) +{ + + if (ch_id >= PWM_CH_NUM) + return; + + __IO uint32_t *reg = &PWM->CH_REG[ch_id].PPR;; + + uint32_t temp = *reg; + temp &= ~PWM_PPR_ENTIER_CYCLE; + temp |= (value << 16); + *reg = temp; +} + +static int PWM_OutModeInit(PWM_CH_ID ch_id, PWM_ChInitParam *param) +{ + int ch_cycle_value = 0; + + ch_cycle_value = PWM_ChClkDiv(ch_id, param); + + PWM_DBG("ch freq = %d\n", ch_cycle_value); + + if (ch_cycle_value == 0) + return -1; + + if (param->hz > (ch_cycle_value / 2)) + return -1; + + ch_cycle_value /= param->hz; + + PWM_DBG("ch_cycle_value = %d\n", ch_cycle_value); + + PWM_ChSetPolarity(ch_id, param); + PWM_ChSetMode(ch_id, param); + + while (PWM_OutPeriodRady(ch_id) == 1) + OS_MSleep(10); + + PWM_OutSetCycle(ch_id, ch_cycle_value - 1); + + return ch_cycle_value; +} + +static int PWM_InputInit(PWM_CH_ID ch_id, PWM_ChInitParam *param) +{ + int clk_freq = PWM_ChClkDiv(ch_id, param); + + if (clk_freq == 0) { + HAL_ERR("Hz out of range\n"); + return -1; + } + + PWM_ChSetPolarity(ch_id, param); + PWM_ChSetMode(ch_id, param); + + return 0; +} + +static int PWM_EnableClock(PWM_CH_ID ch_id, uint8_t en) +{ + PWM_GROUP_ID group = PWM_ChToGroup(ch_id); + + __IO uint32_t *reg = NULL; + + if (group >= PWM_GROUP_NUM) + return -1; + + reg = &PWM->PCCR[group]; + + if (en == 1) + HAL_SET_BIT(*reg, PWM_CH_CLK_GATING); + else + HAL_CLR_BIT(*reg, PWM_CH_CLK_GATING); + + return 0; +} + +static void PWM_Init(PWM_CH_ID ch_id) +{ + int is_init = IoInitCount & (1 << ch_id); + + if (!is_init) { + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_PWM, ch_id), 0); + IoInitCount |= 1 << ch_id; + } +} + +static void PWM_DeInit(PWM_CH_ID ch_id) +{ + + + int is_init = IoInitCount & (1 << ch_id); + PWM_CH_ID brother; + + if (ch_id % 2) + brother = ch_id - 1; + else + brother = ch_id + 1; + + int brother_is_init = IoInitCount & (1 << brother); + + if(is_init) { + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_PWM, ch_id), 0); + + if (!brother_is_init) + PWM_EnableClock(ch_id, 0); + + IoInitCount &= ~(1 << ch_id); + + if (IoInitCount == 0) { + PWM_DBG("pwm module disable\n"); + PWM_ModuleDisable(); + } + } +} + +__STATIC_INLINE void PWM_EnableOutputIRQ(PWM_CH_ID ch_id, uint8_t en) +{ + if (en) + HAL_SET_BIT(PWM->PIER, HAL_BIT(ch_id)); + else + HAL_CLR_BIT(PWM->PIER, HAL_BIT(ch_id)); +} + +__STATIC_INLINE void PWM_EnableInuptRiseEdgeIRQ(PWM_CH_ID ch_id, uint8_t en) +{ + if (en) + HAL_SET_BIT(PWM->CIER, RISECH(ch_id)); + else + HAL_CLR_BIT(PWM->CIER, RISECH(ch_id)); +} + +__STATIC_INLINE void PWM_EnableInuputFallEdgeIRQ(PWM_CH_ID ch_id, uint8_t en) +{ + if (en) + HAL_SET_BIT(PWM->CIER, FALLCH(ch_id)); + else + HAL_CLR_BIT(PWM->CIER, FALLCH(ch_id)); +} + +__STATIC_INLINE void PWM_EnableInputBothEdgeIRQ(PWM_CH_ID ch_id, uint8_t en) +{ + if (en) + HAL_SET_BIT(PWM->CIER, (RISECH(ch_id) | FALLCH(ch_id))); + else + HAL_CLR_BIT(PWM->CIER, (RISECH(ch_id) | FALLCH(ch_id))); +} + +static uint32_t PWM_CycleValue(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg; + + reg = &PWM->CH_REG[ch_id].PPR; + + return (*reg & PWM_PPR_ENTIER_CYCLE) >> 16; +} + +static int PWM_CycleIsReady(PWM_CH_ID ch_id) +{ + __IO uint32_t* reg; + + reg = &PWM->CH_REG[ch_id].PCR; + + return HAL_GET_BIT(*reg, PWM_PCR_PERIODRDY); +} + +static void PWM_SetActCycle(PWM_CH_ID ch_id, uint16_t cycle) +{ + __IO uint32_t *reg; + reg = &PWM->CH_REG[ch_id].PPR; + + uint32_t p = *reg; + p &= ~PWM_PPR_ACT_CYCLE; + p |= cycle; + *reg = p; +} + +static void PWM_EnableDeadZone(PWM_GROUP_ID group_id, uint8_t en) +{ + __IO uint32_t *reg = NULL; + + reg = &PWM->PDZCR[group_id]; + + if (en) + HAL_SET_BIT(*reg, PWM_CH_DZ_EN); + else + HAL_CLR_BIT(*reg, PWM_CH_DZ_EN); +} + +static int PWM_FallEdgeLock(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg = &PWM->CH_REG[ch_id].CCR;; + + return *reg & PWM_CCR_CFLF; +} + +static void PWM_ClearFallEdgeLock(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg = &PWM->CH_REG[ch_id].CCR; + + *reg |= PWM_CCR_CFLF; +} + +static int PWM_RiseEdgeLock(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg = &PWM->CH_REG[ch_id].CCR; + + return *reg & PWM_CCR_CRLF; +} + +static void PWM_ClearRiseEdgeLock(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg = &PWM->CH_REG[ch_id].CCR; + if(reg == NULL) + return; + *reg |= PWM_CCR_CRLF; +} + +static uint16_t PWM_CRLRValue(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg = &PWM->CH_REG[ch_id].CRLR; + + return ((uint16_t)(*reg & PWM_CRLR)); +} + +static uint16_t PWM_CFLRValue(PWM_CH_ID ch_id) +{ + __IO uint32_t *reg = &PWM->CH_REG[ch_id].CFLR; + + return ((uint16_t)(*reg & PWM_CFLR)); +} + +static void PWM_OutIRQHandle() +{ + uint32_t i; + uint32_t status; + uint32_t is_irq; + PWM_IrqParam *irq; + + status = PWM->PISR & PWM->PIER & PWM_IRQ_ALL_BITS; /* get pending bits */ + PWM->PISR = status; /* clear IRQ bits */ + irq = PWM_IrqPrivate; + + for (i = PWM_GROUP0_CH0; i < PWM_CH_NUM && status != 0; i++) { + is_irq = status & HAL_BIT(0); + if (is_irq && irq[i].callback) { + PWM_IrqEvent event = PWM_IRQ_OUTPUT; + irq[i].callback(irq[i].arg, event); + } + status >>= 1; + } +} + +static void PWM_InputIRQHandle() +{ + uint32_t i; + uint32_t status; + uint32_t rise_edge; + uint32_t fall_edge; + PWM_IrqParam *irq; + status = PWM->CISR & PWM->CIER & PWM_IRQ_ALL_BITS; /* get pending bits */ + PWM->CISR = status; /* clear IRQ bits */ + irq = PWM_IrqPrivate; + + for (i = PWM_GROUP0_CH0; i < PWM_CH_NUM && status != 0; i++) { + rise_edge = status & HAL_BIT(0); + if (rise_edge && irq[i].callback) { + PWM_IrqEvent event = PWM_IRQ_RISEEDGE; + irq[i].callback(irq[i].arg, event); + } + fall_edge = status & HAL_BIT(1); + if (fall_edge && irq[i].callback) { + PWM_IrqEvent event = PWM_IRQ_FALLEDGE; + irq[i].callback(irq[i].arg, event); + } + status >>= 2; + } +} + +void PWM_ECT_IRQHandler() +{ + if (PWM->CIER > 0) + PWM_InputIRQHandle(); + + if (PWM->PIER > 0) + PWM_OutIRQHandle(); +} + +/** + * @brief Configure the pwm group source clock. + * @note This function is used to configure the group source clock , + * each group contains two channels. + * For example : The group_0's clock is effect channel0 and channel 1. + * @param group_id: The pwm group id. + * @param param: + * @arg param->clk:The source clk of this group. + * @arg param->div:The division for source clk. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_PWM_GroupClkCfg(PWM_GROUP_ID group_id, PWM_ClkParam *param) +{ + if (group_id >= PWM_GROUP_NUM) + return HAL_ERROR; + + if (IoInitCount == 0) { + PWM_ModuleEnable(); + } + + __IO uint32_t *reg = &PWM->PCCR[group_id]; + + if (param->clk == PWM_CLK_HOSC) { + *reg &= ~PWM_SRC_CLK_SELECT; + } else if (param->clk == PWM_CLK_APB1){ + HAL_SET_BIT(*reg, PWM_SRC_CLK_SELECT); + HAL_CLR_BIT(*reg, HAL_BIT(8)); + } else + return HAL_ERROR; + + if (param->div > PWM_SRC_CLK_DIV_256 || param->div < 0) + return HAL_ERROR; + + uint32_t temp = *reg; + temp &= ~PWM_SRC_CLK_DIV_V; + temp |= param->div; + *reg = temp; + + return HAL_OK; +} + +/** + * @brief Init the pwm channel. + * @note This function is used to configure the channel pin(IO mode), output frequency , + * polarity and rum mode. + * @param ch_id: The pwm channel id. + * @param param: + * @arg param->mode:The channels run mode. + * @arg param->polarity:The channels polarity. + * @arg param->hz:The channels output frequency. + * @retval max_duty_ratio: The channel max duty cycle value. if the mode is + * capture, the return value is 0. error return -1; + */ +int HAL_PWM_ChInit(PWM_CH_ID ch_id, PWM_ChInitParam *param) +{ + int duty_ratio = -1; + if (ch_id >= PWM_CH_NUM) + return -1; + + PWM_Init(ch_id); + + switch(param->mode) { + case PWM_CYCLE_MODE: + case PWM_PLUSE_MODE: + duty_ratio = PWM_OutModeInit(ch_id, param); + break; + case PWM_CAPTURE_MODE: + duty_ratio = PWM_InputInit(ch_id, param); + break; + default: + return -1; + } + + return duty_ratio; +} + +/** + * @brief Deinit the pwm channel. + * @note This function is used to deinit the channel pin, reduce power consumption. + * @param ch_id: The pwm channel id. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_ChDeinit(PWM_CH_ID ch_id) +{ + if (ch_id >= PWM_CH_NUM) + return HAL_ERROR; + + PWM_DeInit(ch_id); + + return HAL_OK; +} + +/** + * @brief Init the complementary mode. + * @note This function is used to configure the groups pin(IO mode), output frequency , + * polarity. + * This mode is two channel output complementart waveform, the channel run in + * cycle mode. + * @param group_id: The pwm group id. + * @param param: + * @arg param->polarity:The channels polarity. + * @arg param->hz:The channels output frequency. + * @retval HAL_Status: The channel max duty cycle value. + */ +int HAL_PWM_ComplementaryInit(PWM_GROUP_ID group_id, PWM_CompInitParam *param) +{ + if (group_id >= PWM_GROUP_NUM) + return -1; + + int cycle_value = -1; + PWM_CH_ID ch_low = group_id * 2; + PWM_CH_ID ch_high = ch_low + 1; + PWM_ChInitParam ch_param; + + PWM_Init(ch_low); + PWM_Init(ch_high); + + ch_param.hz = param->hz; + ch_param.polarity = param->polarity; + ch_param.mode = PWM_CYCLE_MODE; + + cycle_value = PWM_OutModeInit(ch_low, &ch_param); + if (cycle_value == -1) + return -1; + + if (ch_param.polarity == PWM_LOWLEVE) + ch_param.polarity = PWM_HIGHLEVE; + else if (ch_param.polarity == PWM_HIGHLEVE) + ch_param.polarity = PWM_LOWLEVE; + else + return -1; + + PWM_OutModeInit(ch_high, &ch_param); + + return cycle_value; +} + +/** + * @brief Deinit the pwm complementary. + * @note This function is used to deinit the groupl pin, reduce power consumption. + * @param group_id: The pwm group id. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_ComplementaryDeInit(PWM_GROUP_ID group_id) +{ + if (group_id >= PWM_GROUP_NUM) + return HAL_ERROR; + + PWM_CH_ID ch_low = group_id * 2; + PWM_CH_ID ch_high = ch_low + 1; + + PWM_DeInit(ch_low); + PWM_DeInit(ch_high); + + return HAL_OK; +} + + +/** + * @brief Enable the pwm channel. + * @param ch_id: The pwm channel id. + * @param mode: The pwm channel run mode. + * @param en: set 1 enable , 0 disable. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_EnableCh(PWM_CH_ID ch_id, PWM_Mode mode, uint8_t en) +{ + if (ch_id >= PWM_CH_NUM) + return HAL_ERROR; + + PWM_EnableClock(ch_id, en); + + if (en) { + if (mode == PWM_CAPTURE_MODE) { + HAL_CLR_BIT(PWM->PER, HAL_BIT(ch_id)); + HAL_SET_BIT(PWM->CER, HAL_BIT(ch_id)); + } else { + HAL_CLR_BIT(PWM->CER, HAL_BIT(ch_id)); + HAL_SET_BIT(PWM->PER, HAL_BIT(ch_id)); + } + } else { + HAL_CLR_BIT(PWM->CER, HAL_BIT(ch_id)); + HAL_CLR_BIT(PWM->PER, HAL_BIT(ch_id)); + } + + return HAL_OK; + +} + + +/** + * @brief Output one pluse.Use this function you need already enable the channel. + * @param ch_id: The pwm channel id. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_OutputPluse(PWM_CH_ID ch_id) +{ + __IO uint32_t* reg = NULL; + reg = &PWM->CH_REG[ch_id].PCR; + + if ((*reg & PWM_PCR_PLUSE_START) > 0) + return HAL_BUSY; + + HAL_SET_BIT(*reg, PWM_PCR_PLUSE_START); + + return HAL_OK; +} + +/** + * @brief Enable the complementary. + * @param group_id: The pwm group id. + * @param en: set 1 enable , 0 disable. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_EnableComplementary(PWM_GROUP_ID group_id, uint8_t en) +{ + if (group_id >= PWM_GROUP_NUM) + return HAL_ERROR; + + PWM_CH_ID ch_id_0 = PWM_GroupToCh0(group_id); + PWM_CH_ID ch_id_1 = PWM_GroupToCh1(group_id); + PWM_EnableClock(ch_id_0, en); + PWM_EnableClock(ch_id_1, en); + if (en) { + HAL_CLR_BIT(PWM->CER, HAL_BIT(ch_id_0) | HAL_BIT(ch_id_1)); + HAL_SET_BIT(PWM->PER, HAL_BIT(ch_id_0) | HAL_BIT(ch_id_1)); + } else + HAL_CLR_BIT(PWM->PER, HAL_BIT(ch_id_0) | HAL_BIT(ch_id_1)); + + return HAL_OK; +} + +/** + * @brief Enable the pwm channel's interrupt. + * @param ch_id: The pwm channel id. + * @param param: + * @arg param->event:The interrupt event. + * @arg param->callback:The interrupt callback. + * @arg param->arg: The param for callback. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_EnableIRQ(PWM_CH_ID ch_id, const PWM_IrqParam *param) +{ + + if (PWM->CIER == 0 && PWM->PIER == 0) + PWM_EnableModuleIRQ(); + + switch (param->event) { + case PWM_IRQ_OUTPUT: + PWM_EnableOutputIRQ(ch_id, 1); + break; + case PWM_IRQ_RISEEDGE: + PWM_EnableInuptRiseEdgeIRQ(ch_id, 1); + break; + case PWM_IRQ_FALLEDGE: + PWM_EnableInuputFallEdgeIRQ(ch_id, 1); + break; + case PWM_IRQ_BOTHEDGE: + PWM_EnableInputBothEdgeIRQ(ch_id, 1); + break; + case PWM_IRQ_NULL: + break; + default: + HAL_WRN("PWM invalid IRQ event, event: %d\n", param->event); + return HAL_ERROR; + } + + PWM_IrqPrivate[ch_id] = *param; + + return HAL_OK; +} + + +/** + * @brief Disable the pwm channel's interrupt. + * @param ch_id: The pwm channel id. + * @retval HAL_Status: The status of driver. + */ +void HAL_PWM_DisableIRQ(PWM_CH_ID ch_id) +{ + PWM_EnableOutputIRQ(ch_id, 0); + PWM_EnableInputBothEdgeIRQ(ch_id, 0); + + if (PWM->CIER == 0 && PWM->PIER == 0) + PWM_DisableModuleIRQ(); +} + + +/** + * @brief Set channel's duty ratio. + * @param ch_id: The pwm channel id. + * @param value: The duty ratio value. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_ChSetDutyRatio(PWM_CH_ID ch_id, uint16_t value) +{ + + if (ch_id >= PWM_CH_NUM) { + HAL_ERR("Invalid ch_id\n"); + return HAL_ERROR; + } + + if (value > PWM_CycleValue(ch_id)) { + HAL_ERR("value is out of range , should <= %d\n",PWM_CycleValue(ch_id)); + return HAL_ERROR; + } + + while (PWM_CycleIsReady(ch_id) == 1) + OS_MSleep(10); + + PWM_SetActCycle(ch_id, value); + + return HAL_OK; +} + +/** + * @brief Set Complementary duty ratio. + * @param group_id: The pwm group id. + * @param value: The duty ratio value. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_ComplementarySetDutyRatio(PWM_GROUP_ID group_id, uint16_t value) +{ + PWM_CH_ID ch_0, ch_1; + + ch_0 = PWM_GroupToCh0(group_id); + ch_1 = PWM_GroupToCh1(group_id); + + if (HAL_PWM_ChSetDutyRatio(ch_0, value) != HAL_OK) + return HAL_ERROR; + if (HAL_PWM_ChSetDutyRatio(ch_1, value) != HAL_OK) + return HAL_ERROR; + + return HAL_OK; +} + +/** + * @brief Set dead zone for complementary mode. + * @param group_id: The pwm group id. + * @param value: The dead zone value. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_SetDeadZoneTime(PWM_GROUP_ID group_id, uint8_t dead_zone_value) +{ + __IO uint32_t *reg = NULL; + + if (group_id >= PWM_GROUP_NUM) { + HAL_ERR("Invalid group id\n"); + return HAL_ERROR; + } + + reg = &PWM->PDZCR[group_id]; + uint32_t p = *reg; + + p &= ~PWM_CH_DZ_INV; + p |= (dead_zone_value << 8); + *reg = p; + + return HAL_OK; +} + +/** + * @brief Enable the dead zone. + * @param group_id: The pwm group id. + * @param en: set 1 enable, 0 disable. + * @retval HAL_Status: The status of driver. + */ +HAL_Status HAL_PWM_EnableDeadZone(PWM_GROUP_ID group_id, uint8_t en) +{ + if (group_id >= PWM_GROUP_NUM) { + HAL_ERR("Invalid group id\n"); + return HAL_ERROR; + } + if (en) + PWM_EnableDeadZone(group_id, 1); + else + PWM_EnableDeadZone(group_id, 0); + + return HAL_OK; +} + +/** + * @brief The pwm channel capture result. + * @param mode: + * @arg PWM_CAP_PLUSE: used for capture pluse. Run in the mode, + * only the highLevlTime is valid. + * @arg PWM_CAP_CYCLE: used for cycle signal. capture the signal's period, + * high level time and low level time. + * @param ch_id: The pwm channel id. + * @retval PWM_CapResult: The result of capture. + */ +PWM_CapResult HAL_PWM_CaptureResult(PWM_CaptureMode mode, PWM_CH_ID ch_id) +{ + PWM_CapResult result = {0, 0, 0}; + uint16_t fall_time = 0, rise_time = 0; + uint32_t temp = 0; + + switch (mode) { + case PWM_CAP_PLUSE: + if (PWM_FallEdgeLock(ch_id) && PWM_RiseEdgeLock(ch_id)) { + PWM_ClearFallEdgeLock(ch_id); + PWM_ClearRiseEdgeLock(ch_id); + fall_time = PWM_CRLRValue(ch_id); + rise_time = PWM_CFLRValue(ch_id); + + result.highLevelTime = rise_time ; + result.lowLevelTime = 0 ; + result.periodTime = 0; + } + break; + case PWM_CAP_CYCLE: + if (PWM_RiseEdgeLock(ch_id)) { + temp = Cap_priv & (1 << ch_id); + if (temp) { + PWM_ClearFallEdgeLock(ch_id); + PWM_ClearRiseEdgeLock(ch_id); + fall_time = PWM_CRLRValue(ch_id); + rise_time = PWM_CFLRValue(ch_id); + + result.highLevelTime = rise_time ; + result.lowLevelTime = fall_time ; + result.periodTime = rise_time + fall_time; + Cap_priv &= ~(1 << ch_id); + } else { + PWM_ClearRiseEdgeLock(ch_id); + Cap_priv |= (1 << ch_id); + } + } + break; + default : + break; + } + + return result; +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_rtc.c b/platform/mcu/xr871/src/driver/chip/hal_rtc.c new file mode 100644 index 0000000000..948b200a7c --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_rtc.c @@ -0,0 +1,385 @@ +/** + * @file hal_rtc.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_rtc.h" +#include "hal_base.h" + +typedef struct { + RTC_AlarmIRQCallback callback; + void *arg; +} RTC_AlarmPrivate; + +static RTC_AlarmPrivate gRtcSecAlarmPriv; +static RTC_AlarmPrivate gRtcWDayAlarmPriv; + +__STATIC_INLINE int RTC_WDayAlarmIsHHMMSSReadable(void) +{ + return !HAL_GET_BIT(RTC->CTRL, RTC_WDAY_ALARM_HHMMSS_ACCESS_BIT); +} + +static int RTC_IsDDHHMMSSReadable(void) +{ + return !HAL_GET_BIT(RTC->CTRL, RTC_DDHHMMSS_ACCESS_BIT); +} + +static int RTC_IsYYMMDDReadable(void) +{ + return !HAL_GET_BIT(RTC->CTRL, RTC_YYMMDD_ACCESS_BIT); +} + +static void RTC_SecAlarmSetAlarmTime(uint32_t sec) +{ + RTC->SEC_ALARM_LOAD_VAL = sec; +} + +__STATIC_INLINE uint32_t RTC_SecAlarmGetCurrentTime(void) +{ + return RTC->SEC_ALARM_CUR_VAL; +} + +static void RTC_SecAlarmEnableIRQ(void) +{ + HAL_SET_BIT(RTC->SEC_ALARM_IRQ_EN, RTC_SEC_ALARM_IRQ_EN_BIT); +} + +static void RTC_SecAlarmDisableIRQ(void) +{ + HAL_CLR_BIT(RTC->SEC_ALARM_IRQ_EN, RTC_SEC_ALARM_IRQ_EN_BIT); +} + +static int RTC_SecAlarmIsPendingIRQ(void) +{ + return HAL_GET_BIT(RTC->SEC_ALARM_IRQ_STATUS, RTC_SEC_ALARM_IRQ_PENDING_BIT); +} + +static void RTC_SecAlarmClearPendingIRQ(void) +{ + HAL_SET_BIT(RTC->SEC_ALARM_IRQ_STATUS, RTC_SEC_ALARM_IRQ_PENDING_BIT); +} + +static void RTC_SecAlarmStart(void) +{ + HAL_SET_BIT(RTC->SEC_ALARM_EN, RTC_SEC_ALARM_EN_BIT); +} + +static void RTC_SecAlarmStop(void) +{ + HAL_CLR_BIT(RTC->SEC_ALARM_EN, RTC_SEC_ALARM_EN_BIT); +} + +static void RTC_WDayAlarmSetAlarmTime(uint8_t hour, uint8_t minute, uint8_t second) +{ + HAL_ASSERT_PARAM(hour >= RTC_HOUR_MIN && hour <= RTC_HOUR_MAX); + HAL_ASSERT_PARAM(minute >= RTC_MINUTE_MIN && minute <= RTC_MINUTE_MAX); + HAL_ASSERT_PARAM(second >= RTC_SECOND_MIN && second <= RTC_SECOND_MAX); + + RTC->WDAY_ALARM_HHMMSS = + (((uint32_t)hour & RTC_WDAY_ALARM_HOUR_VMASK) << RTC_WDAY_ALARM_HOUR_SHIFT) | + (((uint32_t)minute & RTC_WDAY_ALARM_MINUTE_VMASK) << RTC_WDAY_ALARM_MINUTE_SHIFT) | + (((uint32_t)second & RTC_WDAY_ALARM_SECOND_VMASK) << RTC_WDAY_ALARM_SECOND_SHIFT); +} + +static uint32_t RTC_WDayAlarmSetAlarmDay(uint8_t wdayMask) +{ + return RTC->WDAY_ALARM_WDAY_EN = wdayMask & RTC_WDAY_ALARM_EN_MASK; +} + +static void RTC_WDayAlarmEnableIRQ(void) +{ + HAL_SET_BIT(RTC->WDAY_ALARM_IRQ_EN, RTC_WDAY_ALARM_IRQ_EN_BIT); +} + +static void RTC_WDayAlarmDisableIRQ(void) +{ + HAL_CLR_BIT(RTC->WDAY_ALARM_IRQ_EN, RTC_WDAY_ALARM_IRQ_EN_BIT); +} + +static int RTC_WDayAlarmIsPendingIRQ(void) +{ + return HAL_GET_BIT(RTC->WDAY_ALARM_IRQ_STATUS, RTC_WDAY_ALARM_IRQ_PENDING_BIT); +} + +static void RTC_WDayAlarmClearPendingIRQ(void) +{ + HAL_SET_BIT(RTC->WDAY_ALARM_IRQ_STATUS, RTC_WDAY_ALARM_IRQ_PENDING_BIT); +} + +void RTC_SecAlarm_IRQHandler() +{ + RTC_SecAlarmStop(); + if (RTC_SecAlarmIsPendingIRQ()) { + RTC_SecAlarmClearPendingIRQ(); + if (gRtcSecAlarmPriv.callback) { + gRtcSecAlarmPriv.callback(gRtcSecAlarmPriv.arg); + } + } +} + +void RTC_WDayAlarm_IRQHandler() +{ + if (RTC_WDayAlarmIsPendingIRQ()) { + RTC_WDayAlarmClearPendingIRQ(); + if (gRtcWDayAlarmPriv.callback) { + gRtcWDayAlarmPriv.callback(gRtcWDayAlarmPriv.arg); + } + } +} + +/** + * @brief Set the RTC date, including leaf year flag, year, month and month day + * @param[in] isLeapYear Leap year flag set to the RTC. + * @arg !0 The year is a leap year + * @arg 0 The year is not a leap year + * @param[in] year Year set to the RTC, [0, 255] + * @param[in] month Month set to the RTC, [1, 12] + * @param[in] mday Month day set to the RTC, [1, 31] + * @return None + * + * @note The leap year flag is always set by the caller, but never changed after + * setting. So the leap year bit of the RTC maybe wrong. + * @note The value of year is not a real year, but year's offset relative to + * the base year defined by the caller. + * @note The correction of the combination of all the parameters is guaranteed + * by the caller. + */ +void HAL_RTC_SetYYMMDD(uint8_t isLeapYear, uint8_t year, uint8_t month, uint8_t mday) +{ + HAL_ASSERT_PARAM(year <= RTC_YEAR_MAX); + HAL_ASSERT_PARAM(month >= RTC_MONTH_MIN && month <= RTC_MONTH_MAX); + HAL_ASSERT_PARAM(mday >= RTC_MDAY_MIN && month <= RTC_MDAY_MAX); + + RTC->YYMMDD = (isLeapYear ? RTC_LEAP_YEAR_BIT : 0) | + (((uint32_t)year & RTC_YEAR_VMASK) << RTC_YEAR_SHIFT) | + (((uint32_t)month & RTC_MONTH_VMASK) << RTC_MONTH_SHIFT) | + (((uint32_t)mday & RTC_MDAY_VMASK) << RTC_MDAY_SHIFT); +} + +/** + * @brief Set the RTC weekday and time including hour, minute and second + * @param[in] wday Weekday set to the RTC + * @param[in] hour Hour set to the RTC, [0, 23] + * @param[in] minute Minute set to the RTC, [0, 59] + * @param[in] second Second set to the RTC, [0, 59] + * @return None + * + * @note The correction of the weekday is guaranteed by the caller. + */ +void HAL_RTC_SetDDHHMMSS(RTC_WeekDay wday, uint8_t hour, uint8_t minute, uint8_t second) +{ + HAL_ASSERT_PARAM(hour >= RTC_HOUR_MIN && hour <= RTC_HOUR_MAX); + HAL_ASSERT_PARAM(minute >= RTC_MINUTE_MIN && minute <= RTC_MINUTE_MAX); + HAL_ASSERT_PARAM(second >= RTC_SECOND_MIN && second <= RTC_SECOND_MAX); + + RTC->DDHHMMSS = (((uint32_t)wday & RTC_WDAY_VMASK) << RTC_WDAY_SHIFT) | + (((uint32_t)hour & RTC_HOUR_VMASK) << RTC_HOUR_SHIFT) | + (((uint32_t)minute & RTC_MINUTE_VMASK) << RTC_MINUTE_SHIFT) | + (((uint32_t)second & RTC_SECOND_VMASK) << RTC_SECOND_SHIFT); +} + +/** + * @brief Get the RTC date, including leaf year flag, year, month and month day + * @param[out] isLeapYear The RTC's leap year flag. Don't use it because it + * maybe wrong. + * - 1 means the year is a leap year + * - 0 means the year is not a leap year + * @param[out] year The RTC's Year + * @param[out] month The RTC's Month + * @param[out] mday The RTC's Month day + * @return None + * + * @note Don't trust the RTC leap year flag, because it's never changed by the + * RTC hardware, and maybe wrong. + * @note The RTC's year is not a real year, but year offset relative to the + * base year defined by the caller. + */ +void HAL_RTC_GetYYMMDD(uint8_t *isLeapYear, uint8_t *year, uint8_t *month, uint8_t *mday) +{ + uint32_t yymmdd; + + while (!RTC_IsYYMMDDReadable()) { + HAL_MSleep(1); + } + + yymmdd = RTC->YYMMDD; + *isLeapYear = HAL_GET_BIT(yymmdd, RTC_LEAP_YEAR_BIT) ? 1 : 0; + *year = HAL_GET_BIT_VAL(yymmdd, RTC_YEAR_SHIFT, RTC_YEAR_VMASK); + *month = HAL_GET_BIT_VAL(yymmdd, RTC_MONTH_SHIFT, RTC_MONTH_VMASK); + *mday = HAL_GET_BIT_VAL(yymmdd, RTC_MDAY_SHIFT, RTC_MDAY_VMASK); +} + +/** + * @brief Get the RTC weekday and time including hour, minute and second + * @param[out] wday The RTC's Weekday + * @param[out] hour The RTC's hour + * @param[out] minute The RTC's minute + * @param[out] second The RTC's second + * @return None + */ +void HAL_RTC_GetDDHHMMSS(RTC_WeekDay *wday, uint8_t *hour, uint8_t *minute, uint8_t *second) +{ + uint32_t ddhhmmss; + + while (!RTC_IsDDHHMMSSReadable()) { + HAL_MSleep(1); + } + + ddhhmmss = RTC->DDHHMMSS; + *wday = (RTC_WeekDay)HAL_GET_BIT_VAL(ddhhmmss, RTC_WDAY_SHIFT, RTC_WDAY_VMASK); + *hour = HAL_GET_BIT_VAL(ddhhmmss, RTC_HOUR_SHIFT, RTC_HOUR_VMASK); + *minute = HAL_GET_BIT_VAL(ddhhmmss, RTC_MINUTE_SHIFT, RTC_MINUTE_VMASK); + *second = HAL_GET_BIT_VAL(ddhhmmss, RTC_SECOND_SHIFT, RTC_SECOND_VMASK); +} + +/** + * @brief Start the RTC second alarm once + * + * After starting, the RTC second alarm counts down from param->alarmSeconds + * to zero, and trigger interrupt when it reach zero. After alarming, the + * alarm stops automatically. + * + * @param[in] param Pointer to RTC_SecAlarmStartParam structure + * @return None + * + */ +void HAL_RTC_StartSecAlarm(const RTC_SecAlarmStartParam *param) +{ + /* reset the current value and wait it done */ + RTC_SecAlarmStop(); + while (RTC_SecAlarmGetCurrentTime() != 0) { + HAL_MSleep(10); + } + + RTC_SecAlarmSetAlarmTime(param->alarmSeconds); + gRtcSecAlarmPriv.callback = param->callback; + gRtcSecAlarmPriv.arg = param->arg; + if (RTC_SecAlarmIsPendingIRQ()) { + RTC_SecAlarmClearPendingIRQ(); + } + RTC_SecAlarmEnableIRQ(); + HAL_NVIC_SetPriority(RTC_SEC_ALARM_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(RTC_SEC_ALARM_IRQn); + RTC_SecAlarmStart(); +} + +/** + * @brief Stop the RTC second alarm + * @return None + */ +void HAL_RTC_StopSecAlarm(void) +{ + RTC_SecAlarmStop(); + HAL_NVIC_DisableIRQ(RTC_SEC_ALARM_IRQn); + RTC_SecAlarmDisableIRQ(); + if (RTC_SecAlarmIsPendingIRQ()) { + RTC_SecAlarmClearPendingIRQ(); + } + gRtcSecAlarmPriv.callback = NULL; + gRtcSecAlarmPriv.arg = NULL; +} + +/** + * @brief Start the RTC weekday alarm + * + * After starting, the RTC weekday alarm will trigger interrupt when it reach + * the configured weekday time. After alarming, the alarm continues to running. + * + * @param[in] param Pointer to RTC_WDayAlarmStartParam structure + * @return None + */ +void HAL_RTC_StartWDayAlarm(const RTC_WDayAlarmStartParam *param) +{ + RTC_WDayAlarmSetAlarmDay(0); + RTC_WDayAlarmSetAlarmTime(param->alarmHour, param->alarmMinute, param->alarmSecond); + + gRtcWDayAlarmPriv.callback = param->callback; + gRtcWDayAlarmPriv.arg = param->arg; + if (RTC_WDayAlarmIsPendingIRQ()) { + RTC_WDayAlarmClearPendingIRQ(); + } + RTC_WDayAlarmEnableIRQ(); + HAL_NVIC_SetPriority(RTC_WDAY_ALARM_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(RTC_WDAY_ALARM_IRQn); + RTC_WDayAlarmSetAlarmDay(param->alarmWDayMask); +} + +/** + * @brief Stop the RTC weekday alarm + * @return None + */ +void HAL_RTC_StopWDayAlarm(void) +{ + RTC_WDayAlarmSetAlarmDay(0); + HAL_NVIC_DisableIRQ(RTC_WDAY_ALARM_IRQn); + RTC_WDayAlarmDisableIRQ(); + if (RTC_WDayAlarmIsPendingIRQ()) { + RTC_WDayAlarmClearPendingIRQ(); + } + gRtcWDayAlarmPriv.callback = NULL; + gRtcWDayAlarmPriv.arg = NULL; +} + +/** + * @brief Get the time value (in microsecond) of the RTC's Free running counter + * + * Free running counter is a 48-bit counter which is driven by LFCLK and starts + * to count as soon as the system reset is released and the LFCLK is ready. + * + * The time unit of the counter is: + * (10^6 / LFCLK) = (10^6 / 32768) = (15625 / 512) us + * + * @return The time value (in microsecond) of the RTC's Free running counter. + * Its accuracy is about 32 us. + */ +uint64_t HAL_RTC_GetFreeRunTime(void) +{ +#define RTC_FREE_RUN_CNT_TO_US(cnt) (((cnt) * 15625) >> 9) + + uint64_t cnt; + uint32_t cntLow1, cntLow2, cntHigh; + + cntLow1 = RTC->FREERUN_CNT_L; + cntHigh = RTC->FREERUN_CNT_H; + cntLow2 = RTC->FREERUN_CNT_L; + if (cntLow2 < cntLow1) { + /* counter's low 32-bit overflow, get high 16-bit again */ + cntHigh = RTC->FREERUN_CNT_H; + cnt = ((uint64_t)cntHigh << 32) | cntLow2; + } else { + cnt = ((uint64_t)cntHigh << 32) | cntLow1; + } + + return RTC_FREE_RUN_CNT_TO_US(cnt); + +#undef RTC_FREE_RUN_CNT_TO_US +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_spi.c b/platform/mcu/xr871/src/driver/chip/hal_spi.c new file mode 100644 index 0000000000..a0e2041ead --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_spi.c @@ -0,0 +1,1356 @@ +/** + * @file hal_spi.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "hal_base.h" +#include "driver/chip/hal_spi.h" +#include "pm/pm.h" + +/*************************************** Debug *****************************************/ +#define SPI_MODULE (DBG_ON | XR_LEVEL_ALERT) +#define SPI_TRANSFER_DEBUG +//#define SPI_REG_DEBUG + +#define SPI_ASSERT(condition) XR_ASSERT(condition, SPI_MODULE, #condition " failed\n") + +#define SPI_DEBUG(msg, arg...) XR_DEBUG(SPI_MODULE, NOEXPAND, "[SPI Debug] " msg, ##arg) + +#define SPI_ALERT(msg, arg...) XR_ALERT(SPI_MODULE, NOEXPAND, "[SPI Alert] " msg, ##arg) + +#define SPI_ENTRY() XR_ENTRY(SPI_MODULE, "[SPI Entry]") +#define SPI_EXIT(val) XR_RET(SPI_MODULE, "[SPI Exit]", val) + +#ifdef SPI_REG_DEBUG +#define SPI_REG_ALL(spi, msg) { \ + SPI_DEBUG(msg "\n"); \ + SPI_REG(spi->VER); \ + SPI_REG(spi->CTRL); \ + SPI_REG(spi->TCTRL); \ + SPI_REG(spi->IER); \ + SPI_REG(spi->STA); \ + SPI_REG(spi->FCTL); \ + SPI_REG(spi->FST); \ + SPI_REG(spi->WAIT); \ + SPI_REG(spi->CCTR); \ + SPI_REG(spi->BC); \ + SPI_REG(spi->TC); \ + SPI_REG(spi->BCC); \ + SPI_REG(spi->NDMA_MODE_CTRL); \ + } + +#define SPI_REG(reg) SPI_DEBUG("register " #reg ": 0x%x.\n", reg); + +#else +#define SPI_REG_ALL(spi, msg) + +#define SPI_REG(reg) + +#endif + +#ifdef SPI_TRANSFER_DEBUG +#define SPI_DEBUG_TRANSFER_DATA(pdata, size, dir) { \ + uint32_t temp_size = size; \ + uint8_t *temp_pdata = pdata; \ + XR_DEBUG(SPI_MODULE, NOEXPAND, "[SPI Debug Transfer] " dir " size = %d: ", size); \ + while (temp_size--) \ + XR_DEBUG(SPI_MODULE, NOEXPAND, "0x%x ", *(temp_pdata++)); \ + XR_DEBUG(SPI_MODULE, NOEXPAND, "\n"); \ + } +#else +#define SPI_DEBUG_TRANSFER_DATA(pdata, size) +#endif + + +#define __SPI_STATIC_INLINE__ __STATIC_INLINE + +/* + * @brief Hardware Layer Interface + */ +__SPI_STATIC_INLINE__ +uint32_t SPI_GetVersion(SPI_T *spi) +{ + return spi->VER; +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_Reset(SPI_T *spi) +{ + HAL_SET_BIT(spi->CTRL, SPI_CTRL_RST_MASK); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetMode(SPI_T *spi, SPI_CTRL_Mode mode) +{ + HAL_MODIFY_REG(spi->CTRL, SPI_CTRL_MODE_MASK, mode); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_Enable(SPI_T *spi) +{ + HAL_SET_BIT(spi->CTRL, SPI_CTRL_EN_MASK); +} + +__SPI_STATIC_INLINE__ +void SPI_Disable(SPI_T *spi) +{ + HAL_CLR_BIT(spi->CTRL, SPI_CTRL_EN_MASK); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_StartTransmit(SPI_T *spi) +{ + HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_XCH_MASK); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetFirstTransmitBit(SPI_T *spi, SPI_TCTRL_Fbs bit) +{ + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_FBS_MASK, bit); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_EnableRapidsMode(SPI_T *spi, bool delay_sample) +{ + HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK); + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SDC_MASK, delay_sample << SPI_TCTRL_SDC_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_DisableRapidsMode(SPI_T *spi) +{ + HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetDuplex(SPI_T *spi, SPI_TCTRL_DHB_Duplex duplex) +{ + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_DHB_MASK, duplex); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetCsLevel(SPI_T *spi, bool level) +{ + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_LEVEL_MASK, level << SPI_TCTRL_SS_LEVEL_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_ManualChipSelect(SPI_T *spi, SPI_TCTRL_SS_Sel cs) +{ + HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK); + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_AutoChipSelect(SPI_T *spi, SPI_TCTRL_SS_Sel cs, bool cs_remain) +{ + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs); + HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK); + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_CTL_MASK, (!cs_remain) << SPI_TCTRL_SS_CTL_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetCsIdle(SPI_T *spi, bool idle) +{ + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SPOL_MASK, (!!idle) << SPI_TCTRL_SPOL_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetSclkMode(SPI_T *spi, SPI_SCLK_Mode mode) +{ + HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_CPOL_MASK | SPI_TCTRL_CPHA_MASK, mode); +} + +typedef enum { + SPI_INT_CS_DESELECT = SPI_IER_SS_INT_EN_MASK, + SPI_INT_TRANSFER_COMPLETE = SPI_IER_TC_INT_EN_MASK, + SPI_INT_TXFIFO_UNDER_RUN = SPI_IER_TF_UDR_INT_EN_MASK, + SPI_INT_TXFIFO_OVERFLOW = SPI_IER_TF_OVF_INT_EN_MASK, + SPI_INT_RXFIFO_UNDER_RUN = SPI_IER_RF_UDR_INT_EN_MASK, + SPI_INT_RXFIFO_OVERFLOW = SPI_IER_RF_OVF_INT_EN_MASK, + SPI_INT_TXFIFO_FULL = SPI_IER_TF_FUL_INT_EN_MASK, + SPI_INT_TXFIFO_EMPTY = SPI_IER_TX_EMP_INT_EN_MASK, + SPI_INT_TXFIFO_READY = SPI_IER_TX_ERQ_INT_EN_MASK, + SPI_INT_RXFIFO_FULL = SPI_IER_RF_FUL_INT_EN_MASK, + SPI_INT_RXFIFO_EMPTY = SPI_IER_RX_EMP_INT_EN_MASK, + SPI_INT_RXFIFO_READY = SPI_IER_RF_RDY_INT_EN_MASK +} SPI_Int_Type; + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_EnableInt(SPI_T *spi, SPI_Int_Type type) +{ + HAL_SET_BIT(spi->IER, type); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_DisableInt(SPI_T *spi, SPI_Int_Type type) +{ + HAL_CLR_BIT(spi->IER, type); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +bool SPI_IntState(SPI_T *spi, SPI_Int_Type type) +{ + return !!HAL_GET_BIT(spi->STA, type); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +bool SPI_ClearInt(SPI_T *spi, SPI_Int_Type type) +{ + HAL_SET_BIT(spi->STA, type); + return HAL_GET_BIT(spi->STA, type); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_DebugReadTx(SPI_T *spi, uint32_t *data) +{ + // tbc... +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_DebugWriteRx(SPI_T *spi, uint32_t *data) +{ + // tbc... +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_ResetTxFifo(SPI_T *spi) +{ + HAL_SET_BIT(spi->FCTL, SPI_FCTL_TF_RST_MASK); + while(HAL_GET_BIT(spi->FCTL, SPI_FCTL_TF_RST_MASK) != 0); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_ResetRxFifo(SPI_T *spi) +{ + HAL_SET_BIT(spi->FCTL, SPI_FCTL_RF_RST_MASK); + while(HAL_GET_BIT(spi->FCTL, SPI_FCTL_RF_RST_MASK) != 0); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_DMA(SPI_T *spi, bool txEn, bool rxEn) +{ + HAL_MODIFY_REG(spi->FCTL, + SPI_FCTL_TF_DRQ_EN_MASK | SPI_FCTL_RF_DRQ_EN_MASK, + ((!!txEn) << SPI_FCTL_TF_DRQ_EN_SHIFT) | ((!!rxEn) << SPI_FCTL_RF_DRQ_EN_SHIFT)); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetTxFifoThreshold(SPI_T *spi, uint8_t threshold) +{ + HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_TX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_TX_TRIG_LEVEL_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetRxFifoThreshold(SPI_T *spi, uint8_t threshold) +{ + HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_RX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_RX_TRIG_LEVEL_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +uint8_t SPI_GetTxFifoCounter(SPI_T *spi) +{ + return (uint8_t)((spi->FST & SPI_FST_TF_CNT_MASK) >> SPI_FST_TF_CNT_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +uint8_t SPI_GetRxFifoCounter(SPI_T *spi) +{ + return (uint8_t)((spi->FST & SPI_FST_RF_CNT_MASK) >> SPI_FST_RF_CNT_SHIFT); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_EnableDualMode(SPI_T *spi) +{ + HAL_SET_BIT(spi->BCC, SPI_BCC_DRM_MASK); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_DisableDualMode(SPI_T *spi) +{ + HAL_CLR_BIT(spi->BCC, SPI_BCC_DRM_MASK); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetInterval(SPI_T *spi, uint16_t nSCLK) +{ + HAL_MODIFY_REG(spi->WAIT, SPI_WAIT_WCC_MASK, nSCLK << SPI_WAIT_WCC_SHIFT); +} + +/* + * @brief + */ +static void SPI_SetClkDiv(SPI_T *spi, uint16_t div) +{ + uint8_t n = 0; + if (div < 1) { + SPI_DEBUG("spi div < 1\n"); + return; + } + + if (div > 2 * (0xFF + 1)) { + HAL_CLR_BIT(spi->CCTR, SPI_CCTR_DRS_MASK); + do { + div = (div == 1) ? 0 : ((div + 1) / 2); + n++; + } while (div); + + SPI_DEBUG("SPI CLK Div into 2^%d\n", n); + HAL_MODIFY_REG(spi->CCTR, SPI_CCTR_CDR1_MASK, (n & 0x0F) << SPI_CCTR_CDR1_SHIFT); + } else { + HAL_SET_BIT(spi->CCTR, SPI_CCTR_DRS_MASK); + n = ((div + 1)/ 2) - 1; + HAL_MODIFY_REG(spi->CCTR, SPI_CCTR_CDR2_MASK, (n & 0xFF) << SPI_CCTR_CDR2_SHIFT); + } +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_SetDataSize(SPI_T *spi, uint32_t data_size, uint32_t dummy_size) +{ + HAL_MODIFY_REG(spi->BC, SPI_BC_MBC_MASK, data_size + dummy_size); + HAL_MODIFY_REG(spi->TC, SPI_TC_MWTC_MASK, data_size); + HAL_MODIFY_REG(spi->BCC, SPI_BCC_STC_MASK, data_size); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_Write(SPI_T *spi, uint8_t *data) +{ + HAL_REG_8BIT(&spi->TXD) = *data; +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +void SPI_Read(SPI_T *spi, uint8_t *data) +{ + *data = HAL_REG_8BIT(&spi->RXD); +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +uint8_t *SPI_TxAddress(SPI_T *spi) +{ + return (uint8_t *)&spi->TXD; +} + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +uint8_t *SPI_RxAddress(SPI_T *spi) +{ + return (uint8_t *)&spi->RXD; +} + + +/************************ private **************************************/ + +typedef struct { + uint8_t *ptr; /* Pointer to SPI transfer Buffer */ + uint32_t size; /* SPI transfer size */ + uint32_t count; /* SPI Transfer Counter */ +} SPI_TransferBuffer; + +#define SPI_TRANSFERBUFFER_DEFAULT \ + { \ + .ptr = NULL, \ + .size = 0, \ + .count = 0\ + } + + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + SPI_STATUS_RESET = 0x00, /*!< SPI not yet initialized or disabled */ + SPI_STATUS_READY = 0x01, /*!< SPI initialized and ready for use */ + SPI_STATUS_BUSY = 0x02, /*!< SPI is occupied */ + SPI_STATUS_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + SPI_STATUS_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + SPI_STATUS_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + SPI_STATUS_ERROR = 0x03 /*!< SPI error state */ +} SPI_Status; + +typedef struct { + SPI_Status status; + HAL_Mutex lock; +} SPI_StateMachine; + +typedef struct { + SPI_T *spi; + SPI_Config config; + SPI_StateMachine sm; + bool dmaSupport; + DMA_Channel tx_dmaChannel; + DMA_Channel rx_dmaChannel; + SPI_TransferBuffer tx; // can be optimized + SPI_TransferBuffer rx; // can be optimized + uint32_t mclk; + HAL_Semaphore block; + SPI_IO_Mode ioMode; + bool cs_idle; + SPI_CS cs_using; +} SPI_Handler; + + + +static SPI_Handler spi_handler[SPI_NUM] = { + { + .spi = (SPI_T *)SPI0_BASE, + .tx_dmaChannel = DMA_CHANNEL_INVALID, + .rx_dmaChannel = DMA_CHANNEL_INVALID, + .dmaSupport = 0, + .mclk = 0, + .rx = {0}, //SPI_TRANSFERBUFFER_DEFAULT, + .tx = {0}, //SPI_TRANSFERBUFFER_DEFAULT, + .sm = {0}, + .config = SPI_CONFIG_DEFAULT, + .block = {0}, + .ioMode = SPI_IO_MODE_NORMAL, + .cs_idle = 1, + .cs_using = SPI_TCTRL_SS_SEL_SS0 + }, + { + .spi = (SPI_T *)SPI1_BASE, + .tx_dmaChannel = DMA_CHANNEL_INVALID, + .rx_dmaChannel = DMA_CHANNEL_INVALID, + .dmaSupport = 0, + .mclk = 0, + .rx = {0}, //SPI_TRANSFERBUFFER_DEFAULT, + .tx = {0}, //SPI_TRANSFERBUFFER_DEFAULT, + .sm = {0}, + .config = SPI_CONFIG_DEFAULT, + .block = {0}, + .ioMode = SPI_IO_MODE_NORMAL, + .cs_idle = 1, + .cs_using = SPI_TCTRL_SS_SEL_SS0 + } +}; + +/* + * @brief + */ +__SPI_STATIC_INLINE__ +SPI_Handler *HAL_SPI_GetInstance(SPI_Port port) +{ + return &spi_handler[port]; +} + + +/* + * @brief + */ +static void HAL_SPI_EnableCCMU(SPI_Port port) +{ + if (port == SPI0) { + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_SPI0); + HAL_CCM_SPI0_EnableMClock(); + } else if (port == SPI1) { + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_SPI1); + HAL_CCM_SPI1_EnableMClock(); + } +} + + +/* + * @brief + */ +static void HAL_SPI_DisableCCMU(SPI_Port port) +{ + if (port == SPI0) { + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_SPI0); + HAL_CCM_SPI0_DisableMClock(); + } else if (port == SPI1) { + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_SPI1); + HAL_CCM_SPI1_DisableMClock(); + } +} + +static inline void HAL_SPI_ResetCCMU(SPI_Port port) +{ + CCM_BusPeriphBit ccm_spi = CCM_BUS_PERIPH_BIT_SPI0 + port; /* spi_port translate to ccm_bit */ + HAL_CCM_BusForcePeriphReset(ccm_spi); + HAL_CCM_BusReleasePeriphReset(ccm_spi); +} + + +/* + * @brief + */ +static bool HAL_SPI_ConfigCCMU(SPI_Port port, uint32_t clk) +{ + CCM_AHBPeriphClkSrc src; + uint32_t mclk; + uint32_t div; + + if (clk > HAL_GetHFClock()) + { + mclk = HAL_PRCM_GetDevClock(); + src = CCM_AHB_PERIPH_CLK_SRC_DEVCLK; + SPI_DEBUG("CCMU src = CCM_AHB_PERIPH_CLK_SRC_DEVCLK.\n"); + } + else + { + mclk = HAL_GetHFClock(); + src = CCM_AHB_PERIPH_CLK_SRC_HFCLK; + SPI_DEBUG("CCMU src = CCM_AHB_PERIPH_CLK_SRC_HFCLK.\n"); + } + + div = (mclk + clk - 1) / clk; + div = div==0 ? 1 : div; + + SPI_DEBUG("CCMU div = %d\n", div); + if (div > (16 * 8)) + return 0; + + if (port == SPI0) + { + if (div > 64) + HAL_CCM_SPI0_SetMClock(src, CCM_PERIPH_CLK_DIV_N_8, (CCM_PeriphClkDivM)((div >> 3) - 1)); + else if (div > 32) + HAL_CCM_SPI0_SetMClock(src, CCM_PERIPH_CLK_DIV_N_4, (CCM_PeriphClkDivM)((div >> 2) - 1)); + else if (div > 16) + HAL_CCM_SPI0_SetMClock(src, CCM_PERIPH_CLK_DIV_N_2, (CCM_PeriphClkDivM)((div >> 1) - 1)); + else + HAL_CCM_SPI0_SetMClock(src, CCM_PERIPH_CLK_DIV_N_1, (CCM_PeriphClkDivM)((div >> 0) - 1)); + } + else if (port == SPI1) + { + if (div > 64) + HAL_CCM_SPI1_SetMClock(src, CCM_PERIPH_CLK_DIV_N_8, (CCM_PeriphClkDivM)((div >> 3) - 1)); + else if (div > 32) + HAL_CCM_SPI1_SetMClock(src, CCM_PERIPH_CLK_DIV_N_4, (CCM_PeriphClkDivM)((div >> 2) - 1)); + else if (div > 16) + HAL_CCM_SPI1_SetMClock(src, CCM_PERIPH_CLK_DIV_N_2, (CCM_PeriphClkDivM)((div >> 1) - 1)); + else + HAL_CCM_SPI1_SetMClock(src, CCM_PERIPH_CLK_DIV_N_1, (CCM_PeriphClkDivM)((div >> 0) - 1)); + } + + return 1; +} + + +/* + * @brief + */ +static void HAL_SPI_TxDMAIntFunc(void *arg) +{ + SPI_Handler *hdl = (SPI_Handler *)arg; + +// SPI_DEBUG("tx DMA Interrupt for SPI.\n"); + + if (hdl->sm.status != SPI_STATUS_BUSY_TX_RX) { + SPI_DMA(hdl->spi, 0, 0); + HAL_SemaphoreRelease(&hdl->block); + } +} + +static void HAL_SPI_RxDMAIntFunc(void *arg) +{ + SPI_Handler *hdl = (SPI_Handler *)arg; + +// SPI_DEBUG("rx DMA Interrupt for SPI.\n"); + SPI_DMA(hdl->spi, 0, 0); + HAL_SemaphoreRelease(&hdl->block); +} + +int pm_resume[SPI_NUM] = {0}; +#ifdef CONFIG_PM +static int spi_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance((SPI_Port)dev->platform_data); + if (hdl->sm.status != SPI_STATUS_READY) + return -1; + return 0; +} + +static int spi_resume(struct soc_device *dev, enum suspend_state_t state) +{ + SPI_Port port = (SPI_Port)dev->platform_data; + SPI_Handler *hdl = HAL_SPI_GetInstance((SPI_Port)dev->platform_data); + SPI_T *spi = hdl->spi; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + pm_resume[port] = 1; + // CCMU config + HAL_SPI_DisableCCMU(port); + HAL_SPI_ResetCCMU(port); + HAL_SPI_ConfigCCMU(port, hdl->mclk); + HAL_SPI_EnableCCMU(port); + + SPI_Disable(spi); + SPI_Reset(spi); + SPI_ResetRxFifo(spi); + SPI_ResetTxFifo(spi); + + HAL_SPI_DisableCCMU(port); + break; + default: + break; + } + + return 0; +} + +static struct soc_device_driver spi_drv = { + .name = "spi", + .suspend_noirq = spi_suspend, + .resume_noirq = spi_resume, +}; + +static struct soc_device spi_dev[SPI_NUM] = { + {.name = "spi0", .driver = &spi_drv, .platform_data = (void *)SPI0,}, + {.name = "spi1", .driver = &spi_drv, .platform_data = (void *)SPI1,}, +}; + +#define SPI_DEV(id) (&spi_dev[id]) + +#endif + + +/************************ public **************************************/ + +/** + * @brief Initialize SPI driver. + * @note Each SPI port can master sevral devices, HAL_SPI_Init initialize the + * SPI port for its own devices. Mclk configed here must be the max freq + * of all devices under this SPI port. + * @param port: spi port + * @param gconfig: + * @arg gconfig->mclk: SPI controller frequency. It must be the the max + * freq of all devices under this SPI port. + * @arg gconfig->cs_level: chip selected level of SPI devices enabled, + * cs level should be same amound all devices. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Init(SPI_Port port, const SPI_Global_Config *gconfig) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + SPI_T *spi = hdl->spi; + HAL_Status ret = HAL_OK; + + SPI_ENTRY(); + SPI_ASSERT(port > SPI_NUM); + + if (hdl->sm.status != SPI_STATUS_RESET) { + ret = HAL_ERROR; + SPI_ALERT("Changing State incorrectly in %s\n", __func__); + goto out; + } + + if ((ret = HAL_MutexInit(&hdl->sm.lock)) != HAL_OK) { + SPI_ALERT("Mutex init failed\n"); + goto out; + } + + if ((ret = HAL_SemaphoreInit(&hdl->block, 0, 1)) != HAL_OK) { + HAL_MutexDeinit(&hdl->sm.lock); + SPI_ALERT("Semaphore init failed\n"); + goto out; + } + + HAL_Memset(&hdl->tx, 1, sizeof(SPI_TransferBuffer)); + HAL_Memset(&hdl->rx, 1, sizeof(SPI_TransferBuffer)); +// hdl->mclk = SPI_SOURCE_CLK; + hdl->mclk = gconfig->mclk * 1; /* a larger mclk could be divided easier by + multi-device-frequency, 2 is not necessary */ + + hdl->cs_idle = !gconfig->cs_level; + SPI_SetCsIdle(spi, hdl->cs_idle); + + // CCMU config + HAL_SPI_DisableCCMU(port); + HAL_SPI_ResetCCMU(port); + if (HAL_SPI_ConfigCCMU(port, hdl->mclk) != 1) { + SPI_ALERT("mclk by CCMU divided too low, config failed.\n"); + ret = HAL_ERROR; + goto out; + } + HAL_SPI_EnableCCMU(port); + + SPI_Disable(spi); + SPI_Reset(spi); + SPI_ResetRxFifo(spi); + SPI_ResetTxFifo(spi); + + // default SPI Register Config + SPI_SetDuplex(spi, SPI_TCTRL_DHB_HALF_DUPLEX); + SPI_SetMode(spi, hdl->config.mode); + SPI_SetFirstTransmitBit(spi, hdl->config.firstBit); + SPI_SetSclkMode(spi, hdl->config.sclkMode); + SPI_SetClkDiv(spi, (hdl->mclk + hdl->config.sclk - 1) / hdl->config.sclk); + + hdl->sm.status = SPI_STATUS_READY; + + SPI_REG_ALL(hdl->spi, "inited"); + HAL_SPI_DisableCCMU(port); + +#ifdef CONFIG_PM + pm_register_ops(SPI_DEV(port)); +#endif + +out: + SPI_EXIT(ret); + return ret; +} + +/** + * @brief Deinitialize SPI driver. + * @param port: spi port + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Deinit(SPI_Port port) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + HAL_Status ret = HAL_OK; + + SPI_ENTRY(); + + if (hdl->sm.status != SPI_STATUS_READY) { + ret = HAL_ERROR; + SPI_ALERT("Changing State incorrectly in %s\n", __func__); + goto out; + } + +#ifdef CONFIG_PM + pm_unregister_ops(SPI_DEV(port)); +#endif + + HAL_MutexDeinit(&hdl->sm.lock); + HAL_SemaphoreDeinit(&hdl->block); + SPI_Disable(hdl->spi); + HAL_SPI_DisableCCMU(port); + hdl->sm.status = SPI_STATUS_RESET; + +out: + SPI_EXIT(ret); + return ret; +} + +/** + * @brief Open a SPI device before using this spi device. + * @note Other SPI devices will block when open a spi device, please make sure + * this device will be close eventually. + * @param port: spi port + * @param cs: spi cs pin. SPI_TCTRL_SS_SEL_SS0~3 are pin cs0~cs3. + * @param config: + * @arg config->mode: spi in master mode or slave mode. slave is not + * supported for now. + * @arg config->opMode: use dma to move data or CPU to move data. + * @arg config->firstBit: data on line is MSB or LSB. + * @arg config->sclk: spi device working frequency. + * @arg config->sclkMode: SPI sclk mode. + * @param msec: timeout in millisecond + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Open(SPI_Port port, SPI_CS cs, SPI_Config *config, uint32_t msec) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + SPI_T *spi = hdl->spi; + HAL_Status ret = HAL_OK; + unsigned long flags; + + SPI_ENTRY(); + flags = HAL_EnterCriticalSection(); + + if ((ret = HAL_MutexLock(&hdl->sm.lock, msec)) != HAL_OK) + goto out; + if (hdl->sm.status != SPI_STATUS_READY) { + ret = HAL_ERROR; + SPI_ALERT("Changing State incorrectly in %s, state: %d -> busy\n", __func__, hdl->sm.status); + goto failed; + } + hdl->sm.status = SPI_STATUS_BUSY; + + hdl->cs_using = cs; + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_SPI, port), cs); + + HAL_SPI_EnableCCMU(port); + + // DMA config + if (config->opMode == SPI_OPERATION_MODE_DMA) { + DMA_ChannelInitParam tx_param; + DMA_ChannelInitParam rx_param; + HAL_Memset(&tx_param, 0, sizeof(tx_param)); + HAL_Memset(&rx_param, 0, sizeof(rx_param)); + + if ((hdl->tx_dmaChannel = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + SPI_ALERT("DMA request failed \n"); + goto init_failed; + } + if ((hdl->rx_dmaChannel = HAL_DMA_Request()) == DMA_CHANNEL_INVALID) { + SPI_ALERT("DMA request failed \n"); + HAL_DMA_Release(hdl->tx_dmaChannel); + goto init_failed; + } + + tx_param.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + (DMA_Periph)(DMA_PERIPH_SPI0 + port), + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM); + tx_param.irqType = DMA_IRQ_TYPE_END; + tx_param.endCallback = HAL_SPI_TxDMAIntFunc; + tx_param.endArg = hdl; + + rx_param.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + (DMA_Periph)(DMA_PERIPH_SPI0 + port)); + rx_param.irqType = DMA_IRQ_TYPE_END; + rx_param.endCallback = HAL_SPI_RxDMAIntFunc; + rx_param.endArg = hdl; + + HAL_DMA_Init(hdl->rx_dmaChannel, &rx_param); + HAL_DMA_Init(hdl->tx_dmaChannel, &tx_param); + } + + SPI_Disable(spi); + + if (HAL_Memcmp(config, &hdl->config, sizeof(*config)) || pm_resume[port]) { // ________________maybe unuseful_______________ // + HAL_Memcpy(&hdl->config, config, sizeof(*config)); + SPI_SetMode(spi, config->mode); + SPI_SetFirstTransmitBit(spi, config->firstBit); + SPI_SetSclkMode(spi, config->sclkMode); + SPI_SetClkDiv(spi, (hdl->mclk + config->sclk - 1) / config->sclk); + SPI_SetDuplex(spi, SPI_TCTRL_DHB_HALF_DUPLEX); + pm_resume[port] = 0; + } + +/* if (config->csMode == SPI_CS_MODE_AUTO) + SPI_AutoChipSelect(spi, cs, 1, hdl->cs_idle); + else { + SPI_ManualChipSelect(spi, cs, hdl->cs_idle); + SPI_SetCsLevel(spi, hdl->cs_idle); + }*/ + SPI_ManualChipSelect(spi, cs); + SPI_SetDataSize(spi, 0, 0); + SPI_Enable(spi); + SPI_REG_ALL(spi, "opened"); + + HAL_ExitCriticalSection(flags); + SPI_EXIT(ret); + return HAL_OK; + +init_failed: + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_SPI, port), cs); +failed: + HAL_MutexUnlock(&hdl->sm.lock); +out: + HAL_ExitCriticalSection(flags); + SPI_EXIT(ret); + return ret; +} + +/** + * @brief Close a SPI device to release SPI port. + * @param port: spi port + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Close(SPI_Port port) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + HAL_Status ret = HAL_OK; + unsigned long flags; + + SPI_ENTRY(); + flags = HAL_EnterCriticalSection(); + + + if (hdl->sm.status != SPI_STATUS_BUSY) { + ret = HAL_ERROR; + SPI_ALERT("Changing State incorrectly in %s, state: %d -> ready\n", __func__, hdl->sm.status); + goto out; + } + hdl->sm.status = SPI_STATUS_READY; + + if (hdl->config.opMode == SPI_OPERATION_MODE_DMA) { + HAL_DMA_Stop(hdl->tx_dmaChannel); + HAL_DMA_Stop(hdl->rx_dmaChannel); + HAL_DMA_DeInit(hdl->tx_dmaChannel); + HAL_DMA_DeInit(hdl->rx_dmaChannel); + HAL_DMA_Release(hdl->tx_dmaChannel); + HAL_DMA_Release(hdl->rx_dmaChannel); + } + + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_SPI, port), hdl->cs_using); + SPI_Disable(hdl->spi); + HAL_SPI_DisableCCMU(port); + HAL_SPI_Config(port, SPI_ATTRIBUTION_IO_MODE, SPI_IO_MODE_NORMAL); + HAL_MutexUnlock(&hdl->sm.lock); +out: + HAL_ExitCriticalSection(flags); + SPI_EXIT(ret); + return ret; + +} + +/** + * @brief Enable SPI device or not by chip select pin + * @note Example: device is select by low voltage level, HAL_SPI_CS(spi_port, 1) + * output cs pin to low voltage level. + * @param port: spi port. + * @param select: select/enable device or not. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_CS(SPI_Port port, bool select) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + SPI_ENTRY(); + + SPI_SetCsLevel(hdl->spi, select ^ hdl->cs_idle); + + SPI_EXIT(HAL_OK); + return HAL_OK; +} + +/** + * @brief Config SPI attribution, such as dual rx mode. + * @note This is a ioctl. + * attr : arg + * SPI_ATTRIBUTION_IO_MODE : SPI_IO_MODE_NORMAL + * : SPI_IO_MODE_DUAL_RX + * other is not support for now. + * @param port: spi port + * @param attr: + * @arg SPI_ATTRIBUTION_IO_MODE: config SPI to a IO mode, for example: + * flash has a dual output fast read mode may use this. And the + * arg can be SPI_IO_MODE_NORMAL or SPI_IO_MODE_DUAL_RX, others + * are not support for now. + * @param arg: an arguement according attribution. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Config(SPI_Port port, SPI_Attribution attr, uint32_t arg) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + HAL_Status ret = HAL_OK; + SPI_ENTRY(); + + if (attr == SPI_ATTRIBUTION_IO_MODE) { + if (arg == SPI_IO_MODE_NORMAL) + hdl->ioMode = SPI_IO_MODE_NORMAL; + else if (arg == SPI_IO_MODE_DUAL_RX) + hdl->ioMode = SPI_IO_MODE_DUAL_RX; + else { + ret = HAL_ERROR; + goto out; + } + } + +out: + SPI_EXIT(ret); + return ret; +} + +/** + * @brief Receive data from SPI device. + * @param port: spi port + * @param data: the buf to store received data, created by user. + * @param size: the data size needed to receive. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Receive(SPI_Port port, uint8_t *data, uint32_t size) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + SPI_TransferBuffer *rx = &hdl->rx; + SPI_T *spi = hdl->spi; + HAL_Status ret = HAL_OK; + unsigned long flags; + + SPI_ENTRY(); + flags = HAL_EnterCriticalSection(); + + if (hdl->sm.status != SPI_STATUS_BUSY) { + ret = HAL_INVALID; + SPI_ALERT("Changing State incorrectly in %s, state: %d -> rx\n", __func__, hdl->sm.status); + HAL_ExitCriticalSection(flags); + goto out; + } + hdl->sm.status = SPI_STATUS_BUSY_RX; + HAL_ExitCriticalSection(flags); + + if (hdl->ioMode == SPI_IO_MODE_DUAL_RX) + SPI_EnableDualMode(spi); + + // check spi enable? + + rx->ptr = data; + rx->count = size; + rx->size = size; + SPI_SetDataSize(spi, 0, rx->size); + + SPI_SetDuplex(hdl->spi, SPI_TCTRL_DHB_HALF_DUPLEX); + SPI_ResetRxFifo(spi); + + SPI_REG_ALL(spi, "prepare to receive"); + + if (hdl->config.opMode == SPI_OPERATION_MODE_DMA) + { + HAL_DMA_Start(hdl->rx_dmaChannel, (uint32_t)SPI_RxAddress(hdl->spi), (uint32_t)rx->ptr, rx->count); + + SPI_DMA(spi, 0, 1); + SPI_StartTransmit(spi); + + SPI_REG_ALL(spi, "spi receive dma start"); + HAL_SemaphoreWait(&hdl->block, SPI_MAX_WAIT_MS); //--------------------return error + HAL_DMA_Stop(hdl->rx_dmaChannel); + while (SPI_IntState(hdl->spi, SPI_INT_TRANSFER_COMPLETE) == 0); + SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); + } + else if (hdl->config.opMode == SPI_OPERATION_MODE_POLL) + { + SPI_StartTransmit(spi); + SPI_REG_ALL(spi, "receive start"); + + while (rx->count > 0) + { + uint32_t len; + SPI_REG_ALL(spi, "receiving"); + +/* while (SPI_IntState(spi, SPI_INT_RXFIFO_EMPTY) != 0); + rx->count--; + SPI_Read(spi, rx->ptr); + rx->ptr++;*/ + len = SPI_GetRxFifoCounter(spi); + while (len--) { + rx->count--; + SPI_Read(spi, rx->ptr); + rx->ptr++; + } + } + + while (SPI_IntState(hdl->spi, SPI_INT_TRANSFER_COMPLETE) == 0); + SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); + } + + if (hdl->ioMode == SPI_IO_MODE_DUAL_RX) + SPI_DisableDualMode(spi); + + SPI_REG_ALL(spi, "receive completed"); + SPI_DEBUG_TRANSFER_DATA(data, size, "Rx"); + +out: + hdl->sm.status = SPI_STATUS_BUSY; + SPI_EXIT(ret); + return ret; +} + + +/** + * @brief Transmit data to SPI device. + * @param port: spi port + * @param data: the data transmitted to SPI device. + * @param size: the data size needed to transmit. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_Transmit(SPI_Port port, uint8_t *data, uint32_t size) /* timeout is not that timeout */ +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + SPI_TransferBuffer *tx = &hdl->tx; + SPI_T *spi = hdl->spi; + HAL_Status ret = HAL_OK; + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + if (hdl->sm.status != SPI_STATUS_BUSY) { + ret = HAL_INVALID; + SPI_ALERT("Changing State incorrectly in %s, state: %d -> tx\n", __func__, hdl->sm.status); + HAL_ExitCriticalSection(flags); + goto out; + } + hdl->sm.status = SPI_STATUS_BUSY_TX; + HAL_ExitCriticalSection(flags); + + // check spi enable? + + SPI_ResetTxFifo(spi); + SPI_SetDuplex(hdl->spi, SPI_TCTRL_DHB_HALF_DUPLEX); + + tx->ptr = data; + tx->count = size; + tx->size = size; + SPI_SetDataSize(spi, tx->size, 0); + + SPI_REG_ALL(spi, "prepare transmit"); + + if (hdl->config.opMode == SPI_OPERATION_MODE_DMA) + { + HAL_DMA_Start(hdl->tx_dmaChannel, (uint32_t)tx->ptr, (uint32_t)SPI_TxAddress(hdl->spi), tx->count); + + SPI_DMA(spi, 1, 0); + SPI_StartTransmit(spi); + + HAL_SemaphoreWait(&hdl->block, SPI_MAX_WAIT_MS); + SPI_REG_ALL(spi, "writing by DMA finish"); + while (SPI_IntState(hdl->spi, SPI_INT_TRANSFER_COMPLETE) == 0); + SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); + HAL_DMA_Stop(hdl->tx_dmaChannel); + //ret = HAL_DMA_GetByteCount(hdl->tx_dmaChannel); + } + else if (hdl->config.opMode == SPI_OPERATION_MODE_POLL) + { + SPI_StartTransmit(spi); + SPI_REG_ALL(spi, "transmit start, TCTRL 31 bit should be 1"); + while (tx->count > 0) + { +// while (SPI_IntState(spi, SPI_INT_TXFIFO_FULL) != 0); + while (SPI_GetTxFifoCounter(spi) == SPI_FIFO_SIZE); + tx->count--; + SPI_Write(spi, tx->ptr); + tx->ptr++; + + SPI_REG_ALL(spi, "writing"); + } + + while (SPI_IntState(hdl->spi, SPI_INT_TRANSFER_COMPLETE) == 0); + SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); + } + + SPI_REG_ALL(spi, "transmit completed"); + SPI_DEBUG_TRANSFER_DATA(data, size, "Tx"); + +out: + hdl->sm.status = SPI_STATUS_BUSY; + SPI_EXIT(ret); + return ret; +} + +/** + * @brief Transmit and Receive data from SPI device in the same time. + * @note Transmit data by MOSI pin, and the exactly same time, receive the + * data by MISO pin. + * @param port: spi port + * @param tx_data: the data transmitted to SPI device. + * @param rx_data: the buf to store received data, created by user. + * @param size: the data size needed to transmit and receive. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPI_TransmitReceive(SPI_Port port, uint8_t *tx_data, uint8_t *rx_data, uint32_t size) +{ + SPI_Handler *hdl = HAL_SPI_GetInstance(port); + SPI_TransferBuffer *tx = &hdl->tx; + SPI_TransferBuffer *rx = &hdl->rx; + SPI_T *spi = hdl->spi; + HAL_Status ret = HAL_OK; + unsigned long flags; + + flags = HAL_EnterCriticalSection(); + if (hdl->sm.status != SPI_STATUS_BUSY) { + ret = HAL_INVALID; + SPI_ALERT("Changing State incorrectly in %s, state: %d -> rx\n", __func__, hdl->sm.status); + HAL_ExitCriticalSection(flags); + goto out; + } + hdl->sm.status = SPI_STATUS_BUSY_TX_RX; + HAL_ExitCriticalSection(flags); + + // check spi enable? + + tx->ptr = tx_data; + tx->count = size; + tx->size = size; + rx->ptr = rx_data; + rx->count = size; + rx->size = size; + SPI_SetDataSize(spi, size, 0); + + SPI_SetDuplex(hdl->spi, SPI_TCTRL_DHB_FULL_DUPLEX); + SPI_ResetTxFifo(spi); + SPI_ResetRxFifo(spi); + + if (hdl->config.opMode == SPI_OPERATION_MODE_DMA) + { + HAL_DMA_Start(hdl->tx_dmaChannel, (uint32_t)tx->ptr, (uint32_t)SPI_TxAddress(hdl->spi), tx->count); + HAL_DMA_Start(hdl->rx_dmaChannel, (uint32_t)SPI_RxAddress(hdl->spi), (uint32_t)rx->ptr, rx->count); + + SPI_DMA(spi, 1, 1); + SPI_StartTransmit(spi); + + HAL_SemaphoreWait(&hdl->block, SPI_MAX_WAIT_MS); + HAL_DMA_Stop(hdl->tx_dmaChannel); + HAL_DMA_Stop(hdl->rx_dmaChannel); + while (SPI_IntState(hdl->spi, SPI_INT_TRANSFER_COMPLETE) == 0); + SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); + } + else if (hdl->config.opMode == SPI_OPERATION_MODE_POLL) + { + SPI_StartTransmit(spi); + while ((tx->count > 0) || (rx->count > 0)) + { + while ((SPI_IntState(spi, SPI_INT_RXFIFO_FULL) == 0) && (tx->count > 0)) { + tx->count--; + SPI_Write(spi, tx->ptr); + tx->ptr++; + } + while (SPI_GetRxFifoCounter(spi) > 0) { + rx->count--; + SPI_Read(spi, rx->ptr); + rx->ptr++; + } + } + + if ((tx->count != 0) || (rx->count != 0)) { + SPI_ALERT("spi_tx_rx error with tx count = %d, rx count = %d.\n", tx->count, rx->count); + ret = HAL_ERROR; + goto out; + } + + while (SPI_IntState(hdl->spi, SPI_INT_TRANSFER_COMPLETE) == 0); + SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE); + + } + + SPI_DEBUG_TRANSFER_DATA(rx_data, size, "Rx"); + SPI_DEBUG_TRANSFER_DATA(tx_data, size, "Tx"); + +out: + hdl->sm.status = SPI_STATUS_BUSY; + return ret; +} + + diff --git a/platform/mcu/xr871/src/driver/chip/hal_spinlock.c b/platform/mcu/xr871/src/driver/chip/hal_spinlock.c new file mode 100644 index 0000000000..0fcfbfe14e --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_spinlock.c @@ -0,0 +1,217 @@ +/** + * @file hal_spinlock.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "hal_base.h" +#include "driver/chip/hal_spinlock.h" +#include "kernel/os/os.h" + +#define DBG_SPIN 0 +#define SPIN_DBG(fmt, arg...) \ + HAL_LOG(HAL_DBG_ON && DBG_SPIN, "[HAL SPIN] "fmt, ##arg) + +static uint32_t SPIN_Num() +{ + __IO uint32_t *reg = SPINLOCK_SYSTATUS_REG; + + uint32_t num = HAL_GET_BIT(*reg, SPINLOCK_NUM); + num = num >> 28; + + if (num > 1) + num = (num - 1) * 2; + + return num * 32; +} + +static uint32_t SPIN_Status() +{ + __IO uint32_t *reg = SPINLOCK_STATUS_REG; + return *reg; +} + +static uint32_t SPIN_ReadLock(int lock) +{ + __IO uint32_t *reg = SPINLOCKN_LOCK_REG(lock); + return HAL_GET_BIT(*reg, SPINLOCK_TAKEN); +} + +static void SPIN_ClearLock(int lock) +{ + __IO uint32_t *reg = SPINLOCKN_LOCK_REG(lock); + HAL_CLR_BIT(*reg, SPINLOCK_TAKEN); +} + +static int SPIN_AllocationLock() +{ + int i = 0; + uint32_t spin_sta = SPIN_Status(); + SPIN_DBG("%s %d, spin_sta %d\n", __func__, __LINE__, spin_sta); + uint32_t spin_num = SPIN_Num(); + SPIN_DBG("%s %d, SPIN_Num %u\n", __func__, __LINE__, spin_num); + + while (i < spin_num) { + if (! (spin_sta & HAL_BIT(i))) + return i; + i++; + } + + return -1; +} + +static int SPIN_LockCheck(SPIN_Lock_t *lock) +{ + int ret = 0; + + if (!lock) + ret = -1; + + if (lock->lock > SPIN_Num()) + ret = -1; + + return ret; +} + +static int SPIN_UnLockCheck(SPIN_Lock_t *lock) +{ + int ret = 0; + + if (!lock) + ret = -1; + + if (lock->lock > SPIN_Num()) + ret = -1; + + if (!(SPIN_Status()& HAL_BIT(lock->lock))) //it is unlock + ret = -1; + + return ret; +} + + +/** + * @brief Init the spinlock module. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPIN_Init() +{ + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_SPINLOCK); + HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_SPINLOCK); + HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_SPINLOCK); + HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_SPINLOCK); + + return HAL_OK; +} + +/** + * @brief Deinit the spinlock module. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPIN_Deinit() +{ + HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_SPINLOCK); + + return HAL_OK; +} + +/** + * @brief Request a spinlock. + * @note Allocation a spinlock resources. + * @param lock: used to save the spinlock number; + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPIN_RequestLock(SPIN_Lock_t *lock) +{ + if (!lock) { + SPIN_DBG("%s %d invalid param\n", __func__, __LINE__); + return HAL_ERROR; + } + + int spin_lock = SPIN_AllocationLock(); + lock->lock = spin_lock; + + if (spin_lock == -1) + return HAL_ERROR; + + return HAL_OK; +} + +/** + * @brief Taken lock. + * @note If the lock alreadytaken, it will be block until lock is released. + * Else the lock will be taken. + * @param lock: The spinlock. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPIN_Lock(SPIN_Lock_t *lock) +{ + if (SPIN_LockCheck(lock) != 0) + return HAL_INVALID; + + while (SPIN_ReadLock(lock->lock)); + + return HAL_OK; +} + +/** + * @brief Try to taken lock. + * @note If the lock lock alreadytaken, it will be return busy. + * Else the lcok will be taken. + * @param lock: The spinlock. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPIN_TryLock(SPIN_Lock_t *lock) +{ + if (SPIN_LockCheck(lock) != 0) + return HAL_INVALID; + + if (SPIN_ReadLock(lock->lock)) + return HAL_BUSY; + + return HAL_OK; +} + +/** + * @brief Unlock. + * @param lock: The spinlock. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_SPIN_Unlock(SPIN_Lock_t *lock) +{ + if (SPIN_UnLockCheck(lock) != 0) + return HAL_INVALID; + + SPIN_ClearLock(lock->lock); + + return HAL_OK; +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_timer.c b/platform/mcu/xr871/src/driver/chip/hal_timer.c new file mode 100644 index 0000000000..32ddf04d3a --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_timer.c @@ -0,0 +1,243 @@ +/** + * @file hal_timer.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_timer.h" +#include "hal_base.h" + +typedef enum { + TIMER_STATE_INVALID = 0, + TIMER_STATE_READY = 1, + TIMER_STATE_RUNNING = 2 +} TIMER_State; + +typedef struct { + TIMER_State state; + TIMER_IRQCallback callback; + void *arg; +} TIMER_Private; + +static TIMER_Private gTimerPrivate[TIMER_NUM]; + +#define TIMER_ASSERT_ID(timerID) HAL_ASSERT_PARAM((timerID) < TIMER_NUM) + +static void TIMER_EnableIRQ(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + HAL_SET_BIT(TIMER->IRQ_EN, HAL_BIT(timerID)); +} + +static void TIMER_DisableIRQ(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + HAL_CLR_BIT(TIMER->IRQ_EN, HAL_BIT(timerID)); +} + +static int TIMER_IsPendingIRQ(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + return HAL_GET_BIT_VAL(TIMER->IRQ_STATUS, timerID, 1); +} + +static void TIMER_ClearPendingIRQ(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + HAL_SET_BIT(TIMER->IRQ_STATUS, HAL_BIT(timerID)); +} + +static void TIMER_IRQHandler(TIMER_ID timerID) +{ + if (TIMER_IsPendingIRQ(timerID)) { + TIMER_ClearPendingIRQ(timerID); + if (gTimerPrivate[timerID].callback) { + gTimerPrivate[timerID].callback(gTimerPrivate[timerID].arg); + } + } +} + +void TIMER0_IRQHandler(void) +{ + TIMER_IRQHandler(TIMER0_ID); +} + +void TIMER1_IRQHandler(void) +{ + TIMER_IRQHandler(TIMER1_ID); +} + +/** + * @brief Initialize the timer according to the specified parameters + * @param[in] timerID ID of the specified timer + * @param[in] param Pointer to TIMER_InitParam structure + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_TIMER_Init(TIMER_ID timerID, const TIMER_InitParam *param) +{ + TIMER_Private *timerPriv; + IRQn_Type IRQn; + unsigned long flags; + + TIMER_ASSERT_ID(timerID); + + if (param->period == 0) { + return HAL_INVALID; + } + + flags = HAL_EnterCriticalSection(); + + timerPriv = &gTimerPrivate[timerID]; + if (timerPriv->state == TIMER_STATE_INVALID) + timerPriv->state = TIMER_STATE_READY; + else + timerPriv = NULL; + + HAL_ExitCriticalSection(flags); + + if (timerPriv == NULL) { + HAL_WRN("timer %d already inited\n", timerID); + return HAL_BUSY; + } + + /* enable clock */ + + /* release reset */ + + /* init parameters */ +#if 1 + /* NB: Clear other bits other than param->cfg, it seems no side effect */ + TIMER->TIMERx[timerID].CTRL = param->cfg; +#else + HAL_MODIFY_REG(TIMER->TIMERx[timerID].CTRL, + TIMER_MODE_MASK | TIMER_CLK_SRC_MASK | TIMER_CLK_PRESCALER_MASK, + param->cfg); +#endif + TIMER->TIMERx[timerID].LOAD_VAL = param->period; + + if (param->isEnableIRQ) { + IRQn = (timerID == TIMER0_ID) ? TIMER0_IRQn : TIMER1_IRQn; +#if 0 + NVIC_IRQHandler IRQHandler = (timerID == TIMER0_ID ? TIMER0_IRQHandler : TIMER1_IRQHandler); + HAL_NVIC_SetIRQHandler(IRQn, IRQHandler); +#endif + timerPriv->callback = param->callback; + timerPriv->arg = param->arg; + if (TIMER_IsPendingIRQ(timerID)) { + TIMER_ClearPendingIRQ(timerID); + } + TIMER_EnableIRQ(timerID); + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(IRQn); + } + + return HAL_OK; +} + +/** + * @brief DeInitialize the specified timer + * @param[in] timerID ID of the specified timer + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_TIMER_DeInit(TIMER_ID timerID) +{ + TIMER_Private *timerPriv; + unsigned long flags; + + TIMER_ASSERT_ID(timerID); + + timerPriv = &gTimerPrivate[timerID]; + + /* stop timer */ + HAL_TIMER_Stop(timerID); + + /* disable IRQ */ + HAL_NVIC_DisableIRQ(timerID == TIMER0_ID ? TIMER0_IRQn : TIMER1_IRQn); + TIMER_DisableIRQ(timerID); + if (TIMER_IsPendingIRQ(timerID)) { + TIMER_ClearPendingIRQ(timerID); + } + timerPriv->callback = NULL; + timerPriv->arg = NULL; + + /* force reset */ + + /* disable clock */ + + flags = HAL_EnterCriticalSection(); + timerPriv->state = TIMER_STATE_INVALID; + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + +/** + * @brief Reload the timer's current value and start to count down + * @param[in] timerID ID of the specified timer + * @return None + */ +void HAL_TIMER_Start(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + HAL_SET_BIT(TIMER->TIMERx[timerID].CTRL, TIMER_RELOAD_BIT | TIMER_START_BIT); +} + +/** + * @brief Stop the timer's counting, the current value of timer is kept + * @param[in] timerID ID of the specified timer + * @return None + */ +void HAL_TIMER_Stop(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + HAL_CLR_BIT(TIMER->TIMERx[timerID].CTRL, TIMER_START_BIT); +} + +/** + * @brief Continue the timer's counting + * + * The timer's current value is not changed, and start to count down + * + * @param[in] timerID ID of the specified timer + * @return None + */ +void HAL_TIMER_Continue(TIMER_ID timerID) +{ + TIMER_ASSERT_ID(timerID); + + HAL_SET_BIT(TIMER->TIMERx[timerID].CTRL, TIMER_START_BIT); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_uart.c b/platform/mcu/xr871/src/driver/chip/hal_uart.c new file mode 100644 index 0000000000..48a3d21433 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_uart.c @@ -0,0 +1,1226 @@ +/** + * @file hal_uart.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_dma.h" +#include "driver/chip/hal_uart.h" +#include "hal_base.h" +#include "pm/pm.h" + +#define UART_TRANSMIT_BY_IRQ_HANDLER 1 + +typedef enum { + UART_STATE_INVALID = 0, + UART_STATE_READY = 1, +} UART_State; + +typedef struct { + UART_State state; + + HAL_Semaphore txSem; + HAL_Semaphore rxSem; + +#if UART_TRANSMIT_BY_IRQ_HANDLER + uint8_t *txBuf; + int32_t txBufSize; +#endif /* UART_TRANSMIT_BY_IRQ_HANDLER */ + + uint8_t *rxBuf; + int32_t rxBufSize; + + UART_RxReadyCallback rxReadyCallback; + void *arg; + + DMA_Channel txDMAChan; + DMA_Channel rxDMAChan; +} UART_Private; + +static UART_Private gUartPrivate[UART_NUM]; +static UART_T * const gUartInstance[UART_NUM] = { UART0, UART1 }; + +__STATIC_INLINE IRQn_Type UART_GetIRQnType(UART_ID uartID) +{ + return (uartID == UART0_ID ? UART0_IRQn: UART1_IRQn); +} + +#ifdef CONFIG_PM + +//#define CONFIG_UART_PM_DEBUG + +#ifdef CONFIG_UART_PM_DEBUG +#define PM_UART_PRINT_BUF_LEN 512 +static volatile uint32_t pm_print_index; +static char pm_print_buf[PM_UART_PRINT_BUF_LEN]; +#endif + +static int8_t g_uart_suspending = 0; +static int8_t g_uart_irq_enable = 0; +static UART_InitParam g_uart_param[UART_NUM]; +static UART_RxReadyCallback g_uart_cb[UART_NUM]; +static void *g_uart_arg[UART_NUM]; + +static int uart_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + UART_ID uartID = (UART_ID)dev->platform_data; + + g_uart_suspending |= (1 << uartID); + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + if (g_uart_irq_enable & (1 << uartID)) + HAL_UART_DisableRxCallback(uartID); + while (!HAL_UART_IsTxEmpty(HAL_UART_GetInstance(uartID))) + ; + for (volatile int i = 0; i < 1000; i++) /* wait tx done */ + i = i; + HAL_DBG("%s id:%d okay\n", __func__, uartID); + HAL_UART_DeInit(uartID); + break; + default: + break; + } + return 0; +} + +static int uart_resume(struct soc_device *dev, enum suspend_state_t state) +{ + UART_ID uartID = (UART_ID)dev->platform_data; + + switch (state) { + case PM_MODE_SLEEP: + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + HAL_UART_Init(uartID, &g_uart_param[uartID]); + if (g_uart_irq_enable & (1 << uartID)) + HAL_UART_EnableRxCallback(uartID, g_uart_cb[uartID], + g_uart_arg[uartID]); + HAL_DBG("%s id:%d okay\n", __func__, uartID); + break; + default: + break; + } + + g_uart_suspending &= ~(1 << uartID); + +#ifdef CONFIG_UART_PM_DEBUG + if (pm_print_index) { + HAL_DBG("%s", pm_print_buf); + pm_print_index = 0; + } +#endif + return 0; +} + +static struct soc_device_driver uart_drv = { + .name = "uart", + .suspend_noirq = uart_suspend, + .resume_noirq = uart_resume, +}; + +static struct soc_device uart_dev[UART_NUM] = { + {.name = "uart0", .driver = &uart_drv, .platform_data = (void *)UART0_ID,}, + {.name = "uart1", .driver = &uart_drv, .platform_data = (void *)UART1_ID,}, +}; + +#define UART_DEV(id) (&uart_dev[id]) + +#endif /* CONFIG_PM */ + +#define UART_ASSERT_ID(uartID) HAL_ASSERT_PARAM((uartID) < UART_NUM) + +__STATIC_INLINE CCM_BusPeriphBit UART_GetCCMPeriphBit(UART_ID uartID) +{ + return (uartID == UART0_ID ? CCM_BUS_PERIPH_BIT_UART0 : + CCM_BUS_PERIPH_BIT_UART1); +} + +__STATIC_INLINE UART_Private *UART_GetUartPriv(UART_ID uartID) +{ + return &gUartPrivate[uartID]; +} + +static void UART_EnableIRQ(UART_T *uart, uint32_t mask) +{ + HAL_SET_BIT(uart->DLH_IER.IRQ_EN, mask); +} + +static void UART_DisableIRQ(UART_T *uart, uint32_t mask) +{ + HAL_CLR_BIT(uart->DLH_IER.IRQ_EN, mask); +} + +__STATIC_INLINE void UART_DisableAllIRQ(UART_T *uart) +{ + uart->DLH_IER.IRQ_EN = 0U; +} + +__STATIC_INLINE void UART_EnableTxReadyIRQ(UART_T *uart) +{ + UART_EnableIRQ(uart, UART_TX_FIFO_TRIG_MODE_EN_BIT | UART_TX_READY_IRQ_EN_BIT); +} + +__STATIC_INLINE void UART_DisableTxReadyIRQ(UART_T *uart) +{ + UART_DisableIRQ(uart, UART_TX_FIFO_TRIG_MODE_EN_BIT | UART_TX_READY_IRQ_EN_BIT); +} + +__STATIC_INLINE void UART_EnableRxReadyIRQ(UART_T *uart) +{ + UART_EnableIRQ(uart, UART_RX_READY_IRQ_EN_BIT); +} + +__STATIC_INLINE void UART_DisableRxReadyIRQ(UART_T *uart) +{ + UART_DisableIRQ(uart, UART_RX_READY_IRQ_EN_BIT); +} + +__STATIC_INLINE void UART_EnableFIFO(UART_T *uart) +{ + HAL_SET_BIT(uart->IIR_FCR.FIFO_CTRL, UART_FIFO_EN_BIT); +} + +__STATIC_INLINE void UART_DisableFIFO(UART_T *uart) +{ + HAL_CLR_BIT(uart->IIR_FCR.FIFO_CTRL, UART_FIFO_EN_BIT); +} + +__STATIC_INLINE void UART_ResetTxFIFO(UART_T *uart) +{ + HAL_SET_BIT(uart->IIR_FCR.FIFO_CTRL, UART_TX_FIFO_RESET_BIT); +} + +__STATIC_INLINE void UART_ResetRxFIFO(UART_T *uart) +{ + HAL_SET_BIT(uart->IIR_FCR.FIFO_CTRL, UART_RX_FIFO_RESET_BIT); +} + +/* baudRate = apb_freq / (16 * div) */ +__STATIC_INLINE uint32_t UART_CalcClkDiv(uint32_t baudRate) +{ + uint32_t div; + + div = baudRate << 4; + div = (HAL_GetAPBClock() + (div >> 1)) / div; + if (div == 0) + div = 1; + return div; +} + +__STATIC_INLINE void UART_SetClkDiv(UART_T *uart, uint16_t div) +{ + HAL_SET_BIT(uart->LINE_CTRL, UART_DIV_ACCESS_BIT); + + uart->RBR_THR_DLL.DIV_LOW = div & UART_DIV_LOW_MASK; + uart->DLH_IER.DIV_HIGH = (div >> 8) & UART_DIV_HIGH_MASK; + + HAL_CLR_BIT(uart->LINE_CTRL, UART_DIV_ACCESS_BIT); +} + +__STATIC_INLINE int UART_IsBusy(UART_T *uart) +{ + return HAL_GET_BIT(uart->STATUS, UART_BUSY_BIT); +} + +__STATIC_INLINE void UART_EnableTx(UART_T *uart) +{ + HAL_CLR_BIT(uart->HALT, UART_HALT_TX_EN_BIT); +} + +__STATIC_INLINE void UART_DisableTx(UART_T *uart) +{ + HAL_SET_BIT(uart->HALT, UART_HALT_TX_EN_BIT); +} + +/** + * @brief Get UART hardware instance by the specified UART ID + * @param[in] uartID ID of the specified UART + * @return UART hardware instance + */ +UART_T *HAL_UART_GetInstance(UART_ID uartID) +{ + return gUartInstance[uartID]; +} + +/** + * @brief Check whether the specified UART can transmit data or not + * @param[in] uart UART hardware instance + * @return 1 The UART can transmit data + * @return 0 The UART cannot transmit data + */ +int HAL_UART_IsTxReady(UART_T *uart) +{ +// return HAL_GET_BIT(uart->LINE_STATUS, UART_TX_HOLD_EMPTY_BIT); + return HAL_GET_BIT(uart->STATUS, UART_TX_FIFO_NOT_FULL_BIT); +} + +/** + * @brief Check whether the transmit FIFO of the specified UART is empty or not + * @param[in] uart UART hardware instance + * @return 1 The UART transmit FIFO is empty + * @return 0 The UART transmit FIFO is not empty + */ +int HAL_UART_IsTxEmpty(UART_T *uart) +{ + return HAL_GET_BIT(uart->STATUS, UART_TX_FIFO_EMPTY_BIT); +} + +/** + * @brief Check whether the specified UART has receive data or not + * @param[in] uart UART hardware instance + * @return 1 The UART has receive data + * @return 0 The UART has no receive data + */ +int HAL_UART_IsRxReady(UART_T *uart) +{ +#ifdef CONFIG_PM + UART_ID uartID = (uart == gUartInstance[UART0_ID]) ? UART0_ID : UART1_ID; + + if (g_uart_suspending & (1 << uartID)) + return 0; +#endif + + return HAL_GET_BIT(uart->LINE_STATUS, UART_RX_READY_BIT); +// return HAL_GET_BIT(uart->STATUS, UART_RX_FIFO_NOT_EMPTY_BIT); +} + +/** + * @brief Get one byte received data of the specified UART + * @param[in] uart UART hardware instance + * @return One byte received data + * + * @note Before calling this function, make sure the specified UART has + * receive data by calling HAL_UART_IsRxReady() + */ +uint8_t HAL_UART_GetRxData(UART_T *uart) +{ + return (uint8_t)(uart->RBR_THR_DLL.RX_BUF); +} + +uint8_t HAL_UART_GetRxFIFOLevel(UART_T *uart) +{ + return (uint8_t)(uart->RX_FIFO_LEVEL); +} + +/** + * @brief Transmit one byte data for the specified UART + * @param[in] uart UART hardware instance + * @param[in] data one byte data + * @return None + * + * @note Before calling this function, make sure the specified UART can + * transmit data by calling HAL_UART_IsTxReady() + */ +void HAL_UART_PutTxData(UART_T *uart, uint8_t data) +{ + uart->RBR_THR_DLL.TX_HOLD = data; +} + +__STATIC_INLINE uint32_t UART_GetInterruptID(UART_T *uart) +{ + return HAL_GET_BIT(uart->IIR_FCR.IRQ_ID, UART_IID_MASK); +} + +__STATIC_INLINE uint32_t UART_GetLineStatus(UART_T *uart) +{ + return HAL_GET_BIT(uart->LINE_STATUS, UART_LINE_STATUS_MASK); +} + +__STATIC_INLINE uint32_t UART_GetModemStatus(UART_T *uart) +{ + return HAL_GET_BIT(uart->MODEM_STATUS, UART_MODEM_STATUS_MASK); +} + +__STATIC_INLINE uint32_t UART_GetUartStatus(UART_T *uart) +{ + return HAL_GET_BIT(uart->STATUS, UART_STATUS_MASK); +} + +static void UART_IRQHandler(UART_T *uart, UART_Private *priv) +{ + uint32_t iid = UART_GetInterruptID(uart); + + switch (iid) { + case UART_IID_MODEM_STATUS: + UART_GetModemStatus(uart); + break; + case UART_IID_TX_READY: +#if UART_TRANSMIT_BY_IRQ_HANDLER + if (priv->txBuf) { + while (priv->txBufSize > 0) { + if (HAL_UART_IsTxReady(uart)) { + HAL_UART_PutTxData(uart, *priv->txBuf); + ++priv->txBuf; + --priv->txBufSize; + } else { + break; + } + } + if (priv->txBufSize == 0) { + UART_DisableTxReadyIRQ(uart); + HAL_SemaphoreRelease(&priv->txSem); /* end transmitting */ + } + } +#else /* UART_TRANSMIT_BY_IRQ_HANDLER */ + UART_DisableTxReadyIRQ(uart); + HAL_SemaphoreRelease(&priv->txSem); +#endif /* UART_TRANSMIT_BY_IRQ_HANDLER */ + break; + case UART_IID_RX_READY: + case UART_IID_CHAR_TIMEOUT: + if (priv->rxReadyCallback) { + priv->rxReadyCallback(priv->arg); + } else if (priv->rxBuf) { + while (priv->rxBufSize > 0) { + if (HAL_UART_IsRxReady(uart)) { + *priv->rxBuf = HAL_UART_GetRxData(uart); + ++priv->rxBuf; + --priv->rxBufSize; + } else { + break; + } + } + if (priv->rxBufSize == 0 || iid == UART_IID_CHAR_TIMEOUT) { + UART_DisableRxReadyIRQ(uart); + HAL_SemaphoreRelease(&priv->rxSem); /* end receiving */ + } + } else { + HAL_WRN("no one receive data, but uart irq is enable\n"); + /* discard received data */ + while (HAL_UART_IsRxReady(uart)) { + HAL_UART_GetRxData(uart); + } + } + break; + case UART_IID_LINE_STATUS: + UART_GetLineStatus(uart); + break; + case UART_IID_BUSY_DETECT: + UART_GetUartStatus(uart); + break; + case UART_IID_RS485: + default: + break; + } +} + +void UART0_IRQHandler(void) +{ + UART_IRQHandler(UART0, &gUartPrivate[UART0_ID]); +} + +void UART1_IRQHandler(void) +{ + UART_IRQHandler(UART1, &gUartPrivate[UART1_ID]); +} + +void N_UART_IRQHandler(void) +{ + HAL_NVIC_DisableIRQ(N_UART_IRQn); + HAL_NVIC_ClearPendingIRQ(N_UART_IRQn); +} + +/** + * @brief Initialize the UART according to the specified parameters + * @param[in] uartID ID of the specified UART + * @param[in] param Pointer to UART_InitParam structure + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_UART_Init(UART_ID uartID, const UART_InitParam *param) +{ + UART_T *uart; + UART_Private *priv; + CCM_BusPeriphBit ccmPeriphBit; + IRQn_Type IRQn; + uint32_t tmp; + unsigned long flags; + + UART_ASSERT_ID(uartID); + + flags = HAL_EnterCriticalSection(); + + priv = UART_GetUartPriv(uartID); + if (priv->state == UART_STATE_INVALID) + priv->state = UART_STATE_READY; + else + priv = NULL; + + HAL_ExitCriticalSection(flags); + + if (priv == NULL) { + HAL_WRN("uart %d already inited\n", uartID); + return HAL_BUSY; + } + + uart = HAL_UART_GetInstance(uartID); + + HAL_SemaphoreInitBinary(&priv->txSem); + HAL_SemaphoreInitBinary(&priv->rxSem); +#if UART_TRANSMIT_BY_IRQ_HANDLER + priv->txBuf = NULL; + priv->txBufSize = 0; +#endif + priv->rxBuf = NULL; + priv->rxBufSize = 0; + priv->rxReadyCallback = NULL; + priv->arg = NULL; + priv->txDMAChan = DMA_CHANNEL_INVALID; + priv->rxDMAChan = DMA_CHANNEL_INVALID; + + /* config pinmux */ + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_UART, uartID), 0); + + /* enable uart clock and release reset */ + ccmPeriphBit = UART_GetCCMPeriphBit(uartID); + HAL_CCM_BusEnablePeriphClock(ccmPeriphBit); + HAL_CCM_BusReleasePeriphReset(ccmPeriphBit); + + UART_DisableAllIRQ(uart); /* disable all IRQ */ + + UART_DisableTx(uart); + + /* wait uart become not busy if necessary */ + while (UART_IsBusy(uart)) { + ; + } + + /* set baud rate, parity, stop bits, data bits */ + tmp = UART_CalcClkDiv(param->baudRate); + UART_SetClkDiv(uart, (uint16_t)tmp); + + HAL_MODIFY_REG(uart->LINE_CTRL, + UART_PARITY_MASK | UART_STOP_BITS_MASK | + UART_DATA_BITS_MASK | UART_BREAK_CTRL_BIT, + param->parity | param->stopBits | param->dataBits); + + /* set uart->MODEM_CTRL */ + if (uartID != UART0_ID && param->isAutoHwFlowCtrl) { + tmp = UART_WORK_MODE_UART | UART_AUTO_FLOW_CTRL_EN_BIT | UART_RTS_ASSERT_BIT; + } else { + tmp = UART_WORK_MODE_UART; + } + HAL_MODIFY_REG(uart->MODEM_CTRL, + UART_WORK_MODE_MASK | UART_LOOP_BACK_EN_BIT | + UART_AUTO_FLOW_CTRL_EN_BIT | UART_RTS_ASSERT_BIT, + tmp); + + /* set FIFO level, DMA mode, reset FIFO, enable FIFO */ + uart->IIR_FCR.FIFO_CTRL = UART_RX_FIFO_TRIG_LEVEL_HALF_FULL | + UART_TX_FIFO_TRIG_LEVEL_EMPTY | + UART_DMA_MODE_1 | + UART_TX_FIFO_RESET_BIT | + UART_RX_FIFO_RESET_BIT | + UART_FIFO_EN_BIT; + UART_EnableTx(uart); + + /* enable NVIC IRQ */ + IRQn = UART_GetIRQnType(uartID); + HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(IRQn); + +#ifdef CONFIG_PM + if (!(g_uart_suspending & (1 << uartID))) { + memcpy(&g_uart_param[uartID], param, sizeof(UART_InitParam)); + pm_register_ops(UART_DEV(uartID)); + } +#endif + + return HAL_OK; +} + +/** + * @brief DeInitialize the specified UART + * @param[in] uartID ID of the specified UART + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_UART_DeInit(UART_ID uartID) +{ + UART_T *uart; + UART_Private *priv; + CCM_BusPeriphBit ccmPeriphBit; + unsigned long flags; + + UART_ASSERT_ID(uartID); + + priv = UART_GetUartPriv(uartID); + if (priv->state == UART_STATE_INVALID) { + return HAL_OK; + } + uart = HAL_UART_GetInstance(uartID); + +#ifdef CONFIG_PM + if (!(g_uart_suspending & (1 << uartID))) { + pm_unregister_ops(UART_DEV(uartID)); + } +#endif + + HAL_UART_DisableTxDMA(uartID); + HAL_UART_DisableRxDMA(uartID); + + if (priv->rxReadyCallback != NULL) { + HAL_WRN("RX callback should be disabled first\n"); + } + HAL_NVIC_DisableIRQ(UART_GetIRQnType(uartID)); + UART_DisableAllIRQ(uart); + UART_DisableTx(uart); + UART_DisableFIFO(uart); + + /* disable uart clock and force reset */ + ccmPeriphBit = UART_GetCCMPeriphBit(uartID); + HAL_CCM_BusForcePeriphReset(ccmPeriphBit); + HAL_CCM_BusDisablePeriphClock(ccmPeriphBit); + + /* De-config pinmux */ + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_UART, uartID), 0); + + HAL_SemaphoreDeinit(&priv->txSem); + HAL_SemaphoreDeinit(&priv->rxSem); + + flags = HAL_EnterCriticalSection(); + priv->state = UART_STATE_INVALID; + HAL_ExitCriticalSection(flags); + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in interrupt mode + * @param[in] uartID ID of the specified UART + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be transmitted + * @return Number of bytes transmitted, -1 on error + * + * @note This function is not thread safe. If using the UART transmit series + * functions in multi-thread, make sure they are executed exclusively. + */ +int32_t HAL_UART_Transmit_IT(UART_ID uartID, uint8_t *buf, int32_t size) +{ + UART_T *uart; + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + if (buf == NULL || size <= 0) { + return -1; + } + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + +#if UART_TRANSMIT_BY_IRQ_HANDLER + priv->txBuf = buf; + priv->txBufSize = size; + + UART_EnableTxReadyIRQ(uart); + HAL_SemaphoreWait(&priv->txSem, HAL_WAIT_FOREVER); + UART_DisableTxReadyIRQ(uart); + priv->txBuf = NULL; + size -= priv->txBufSize; + priv->txBufSize = 0; +#else /* UART_TRANSMIT_BY_IRQ_HANDLER */ + uint8_t *ptr = buf; + int32_t left = size; + while (left > 0) { + if (HAL_UART_IsTxReady(uart)) { + HAL_UART_PutTxData(uart, *ptr); + ++ptr; + --left; + } else { + UART_EnableTxReadyIRQ(uart); + HAL_SemaphoreWait(&priv->txSem, HAL_WAIT_FOREVER); + } + } + UART_DisableTxReadyIRQ(uart); /* just in case */ +// size -= left; +#endif /* UART_TRANSMIT_BY_IRQ_HANDLER */ + + /* TODO: add protection */ + + return size; +} + +/** + * @brief Receive an amount of data in interrupt mode + * @param[in] uartID ID of the specified UART + * @param[out] buf Pointer to the data buffer + * @param[in] size The maximum number of bytes to be received. + * The actual received bytes can be less than this. + * @param[in] msec Timeout value in millisecond to receive data. + * HAL_WAIT_FOREVER for no timeout. + * @return Number of bytes received, -1 on error + * + * @note This function is not thread safe. If using the UART receive series + * functions in multi-thread, make sure they are executed exclusively. + */ +int32_t HAL_UART_Receive_IT(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec) +{ + UART_T *uart; + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + if (buf == NULL || size <= 0) { + return -1; + } + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + if (priv->rxReadyCallback != NULL) { + HAL_WRN("rx callback is enabled\n"); + return -1; + } + + priv->rxBuf = buf; + priv->rxBufSize = size; + + UART_EnableRxReadyIRQ(uart); + HAL_SemaphoreWait(&priv->rxSem, msec); + UART_DisableRxReadyIRQ(uart); + + priv->rxBuf = NULL; + size -= priv->rxBufSize; + priv->rxBufSize = 0; + + /* TODO: add protection */ + + return size; +} + +/** + * @brief Enable receive ready callback function for the specified UART + * @param[in] uartID ID of the specified UART + * @param[in] cb The UART receive ready callback function + * @param[in] arg Argument of the UART receive ready callback function + * @retval HAL_Status, HAL_OK on success + * + * @note To handle receive data externally, use this function to enable the + * receive ready callback function, then receive and process the data in + * the callback function. + * @note If the receive ready callback function is enabled, all other receive + * series functions cannot be used to receive data. + * @note This function is not thread safe. If using the UART receive series + * functions in multi-thread, make sure they are executed exclusively. + */ +HAL_Status HAL_UART_EnableRxCallback(UART_ID uartID, UART_RxReadyCallback cb, void *arg) +{ + UART_T *uart; + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + priv->rxReadyCallback = cb; + priv->arg = arg; + + UART_EnableRxReadyIRQ(uart); + + /* TODO: add protection */ + +#ifdef CONFIG_PM + if (!(g_uart_suspending & (1 << uartID))) { + g_uart_cb[uartID] = cb; + g_uart_arg[uartID] = arg; + g_uart_irq_enable |= (1 << uartID); + } +#endif + + return HAL_OK; +} + +/** + * @brief Disable receive ready callback function for the specified UART + * @param[in] uartID ID of the specified UART + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_UART_DisableRxCallback(UART_ID uartID) +{ + UART_T *uart; + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + UART_DisableRxReadyIRQ(uart); + + priv->rxReadyCallback = NULL; + priv->arg = NULL; + + /* TODO: add protection */ + +#ifdef CONFIG_PM + if (!(g_uart_suspending & (1 << uartID))) { + g_uart_cb[uartID] = NULL; + g_uart_arg[uartID] = NULL; + g_uart_irq_enable &= ~(1 << uartID); + } +#endif + + return HAL_OK; +} + +/** + * @internal + * @brief UART DMA transfer complete callback fucntion to release waiting + * semaphore + * @param[in] arg Pointer to waiting semaphore for DMA transfer + * @return None + */ +static void UART_DMAEndCallback(void *arg) +{ + HAL_SemaphoreRelease((HAL_Semaphore *)arg); +} + +/** + * @brief Enable UART transmitting data in DMA mode + * @param[in] uartID ID of the specified UART + * @retval HAL_Status, HAL_OK on success, HAL_ERROR on no valid DMA channel + * + * @note To transmit data in DMA mode, a DMA channel for the specified + * UART to transmit data MUST be configured first by this function. + */ +HAL_Status HAL_UART_EnableTxDMA(UART_ID uartID) +{ + UART_T *uart; + UART_Private *priv; + DMA_ChannelInitParam dmaParam; + + UART_ASSERT_ID(uartID); + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + if (priv->txDMAChan != DMA_CHANNEL_INVALID) { + return HAL_OK; + } + + priv->txDMAChan = HAL_DMA_Request(); + if (priv->txDMAChan == DMA_CHANNEL_INVALID) { + return HAL_ERROR; + } + + HAL_Memset(&dmaParam, 0, sizeof(dmaParam)); + dmaParam.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + uartID == UART0_ID ? + DMA_PERIPH_UART0 : + DMA_PERIPH_UART1, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM); + dmaParam.irqType = DMA_IRQ_TYPE_END; + dmaParam.endCallback = UART_DMAEndCallback; + dmaParam.endArg = &priv->txSem; + + HAL_DMA_Init(priv->txDMAChan, &dmaParam); + + /* set DMA mode of UART */ +// HAL_MODIFY_REG(uart->IIR_FCR.FIFO_CTRL, UART_DMA_MODE_MASK, UART_DMA_MODE_1); + HAL_SET_BIT(uart->HALT, UART_DMA_PTE_TX_BIT); + + return HAL_OK; +} + +/** + * @brief Enable UART receiving data in DMA mode + * @param[in] uartID ID of the specified UART + * @retval HAL_Status, HAL_OK on success, HAL_ERROR on no valid DMA channel + * + * @note To reveive data in DMA mode, a DMA channel for the specified + * UART to receive data MUST be configured first by this function. + */ +HAL_Status HAL_UART_EnableRxDMA(UART_ID uartID) +{ + UART_T *uart; + UART_Private *priv; + DMA_ChannelInitParam dmaParam; + + UART_ASSERT_ID(uartID); + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + if (priv->rxDMAChan != DMA_CHANNEL_INVALID) { + return HAL_OK; + } + + priv->rxDMAChan = HAL_DMA_Request(); + if (priv->rxDMAChan == DMA_CHANNEL_INVALID) { + return HAL_ERROR; + } + + HAL_Memset(&dmaParam, 0, sizeof(dmaParam)); + dmaParam.cfg = HAL_DMA_MakeChannelInitCfg(DMA_WORK_MODE_SINGLE, + DMA_WAIT_CYCLE_2, + DMA_BYTE_CNT_MODE_REMAIN, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_INC, + DMA_PERIPH_SRAM, + DMA_DATA_WIDTH_8BIT, + DMA_BURST_LEN_1, + DMA_ADDR_MODE_FIXED, + uartID == UART0_ID ? + DMA_PERIPH_UART0 : + DMA_PERIPH_UART1); + dmaParam.irqType = DMA_IRQ_TYPE_END; + dmaParam.endCallback = UART_DMAEndCallback; + dmaParam.endArg = &priv->rxSem; + + HAL_DMA_Init(priv->rxDMAChan, &dmaParam); + + /* set DMA mode of UART */ +// HAL_MODIFY_REG(uart->IIR_FCR.FIFO_CTRL, UART_DMA_MODE_MASK, UART_DMA_MODE_1); + HAL_SET_BIT(uart->HALT, UART_DMA_PTE_RX_BIT); + + return HAL_OK; +} + +/** + * @brief Disable UART transmitting data in DMA mode + * @param[in] uartID ID of the specified UART + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_UART_DisableTxDMA(UART_ID uartID) +{ + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + /* TODO: add protection */ + + priv = UART_GetUartPriv(uartID); + + if (priv->txDMAChan != DMA_CHANNEL_INVALID) { + HAL_DMA_Stop(priv->txDMAChan); + HAL_DMA_DeInit(priv->txDMAChan); + HAL_DMA_Release(priv->txDMAChan); + priv->txDMAChan = DMA_CHANNEL_INVALID; + } + + return HAL_OK; +} + +/** + * @brief Disable UART receiving data in DMA mode + * @param[in] uartID ID of the specified UART + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_UART_DisableRxDMA(UART_ID uartID) +{ + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + /* TODO: add protection */ + + priv = UART_GetUartPriv(uartID); + + if (priv->rxDMAChan != DMA_CHANNEL_INVALID) { + HAL_DMA_Stop(priv->rxDMAChan); + HAL_DMA_DeInit(priv->rxDMAChan); + HAL_DMA_Release(priv->rxDMAChan); + priv->rxDMAChan = DMA_CHANNEL_INVALID; + } + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in DMA mode + * + * Steps to transmit data in DMA mode: + * - use HAL_UART_EnableTxDMA() to enable UART transmit DMA mode + * - use HAL_UART_Transmit_DMA() to transmit data, it can be called + * repeatedly after HAL_UART_EnableTxDMA() + * - use HAL_UART_DisableTxDMA() to disable UART transmit DMA mode if needed + * + * @param[in] uartID ID of the specified UART + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be transmitted + * @return Number of bytes transmitted, -1 on error + * + * @note This function is not thread safe. If using the UART transmit series + * functions in multi-thread, make sure they are executed exclusively. + * @note To transmit data in DMA mode, HAL_UART_EnableTxDMA() MUST be executed + * before calling this function. + */ +int32_t HAL_UART_Transmit_DMA(UART_ID uartID, uint8_t *buf, int32_t size) +{ + UART_T *uart; + UART_Private *priv; + int32_t left; + + UART_ASSERT_ID(uartID); + + if (buf == NULL || size <= 0) { + return -1; + } + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + if (priv->txDMAChan == DMA_CHANNEL_INVALID) { + HAL_WRN("tx dma is disabled\n"); + return -1; + } + + HAL_DMA_Start(priv->txDMAChan, (uint32_t)buf, (uint32_t)&uart->RBR_THR_DLL.TX_HOLD, size); + HAL_SemaphoreWait(&priv->txSem, HAL_WAIT_FOREVER); + HAL_DMA_Stop(priv->txDMAChan); + left = HAL_DMA_GetByteCount(priv->txDMAChan); + + /* TODO: add protection */ + + return (size - left); +} + +/** + * @brief Receive an amount of data in DMA mode + * + * Steps to receive data in DMA mode: + * - use HAL_UART_EnableRxDMA() to enable UART receive DMA mode + * - use HAL_UART_Receive_DMA() to receive data, it can be called + * repeatedly after HAL_UART_EnableRxDMA() + * - use HAL_UART_DisableRxDMA() to disable UART receive DMA mode if needed + * + * @param[in] uartID ID of the specified UART + * @param[out] buf Pointer to the data buffer + * @param[in] size The maximum number of bytes to be received. + * The actual received bytes can be less than this. + * @param[in] msec Timeout value in millisecond to receive data. + * HAL_WAIT_FOREVER for no timeout. + * @return Number of bytes received, -1 on error + * + * @note This function is not thread safe. If using the UART receive series + * functions in multi-thread, make sure they are executed exclusively. + * @note To receive data in DMA mode, HAL_UART_EnableRxDMA() MUST be executed + * before calling this function. + */ +int32_t HAL_UART_Receive_DMA(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec) +{ + UART_T *uart; + UART_Private *priv; + int32_t left; + + UART_ASSERT_ID(uartID); + + if (buf == NULL || size <= 0) { + return -1; + } + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + priv = UART_GetUartPriv(uartID); + + if (priv->rxReadyCallback != NULL) { + HAL_WRN("rx callback is enabled\n"); + return -1; + } + + if (priv->rxDMAChan == DMA_CHANNEL_INVALID) { + HAL_WRN("rx dma is disabled\n"); + return -1; + } + + HAL_DMA_Start(priv->rxDMAChan, (uint32_t)&uart->RBR_THR_DLL.RX_BUF, (uint32_t)buf, size); + HAL_SemaphoreWait(&priv->rxSem, msec); + HAL_DMA_Stop(priv->rxDMAChan); + left = HAL_DMA_GetByteCount(priv->rxDMAChan); + + /* TODO: add protection */ + + return (size - left); +} + +/** + * @brief Transmit an amount of data in polling mode + * @param[in] uartID ID of the specified UART + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be transmitted + * @return Number of bytes transmitted, -1 on error + * + * @note This function is not thread safe. If using the UART transmit series + * functions in multi-thread, make sure they are executed exclusively. + */ +int32_t HAL_UART_Transmit_Poll(UART_ID uartID, uint8_t *buf, int32_t size) +{ + UART_T *uart; + uint8_t *ptr; + int32_t left; + + UART_ASSERT_ID(uartID); + + if (buf == NULL || size <= 0) { + return -1; + } + +#ifdef CONFIG_PM + if (g_uart_suspending & (1 << uartID)) { +#ifdef CONFIG_UART_PM_DEBUG + if (pm_print_index + size < (PM_UART_PRINT_BUF_LEN - 1)) { + memcpy(pm_print_buf + pm_print_index, buf, size); + pm_print_index += size; + } +#endif + return size; + } +#endif + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + ptr = buf; + left = size; + while (left > 0) { + while (!HAL_UART_IsTxReady(uart)) { + ; /* wait FIFO become not full */ + } + + HAL_UART_PutTxData(uart, *ptr); + ++ptr; + --left; + } + + /* TODO: add protection */ + + return size; +} + +/** + * @brief Receive an amount of data in polling mode + * @param[in] uartID ID of the specified UART + * @param[out] buf Pointer to the data buffer + * @param[in] size The maximum number of bytes to be received. + * The actual received bytes can be less than this. + * @param[in] msec Timeout value in millisecond to receive data. + * HAL_WAIT_FOREVER for no timeout. + * @return Number of bytes received, -1 on error + * + * @note This function is not thread safe. If using the UART receive series + * functions in multi-thread, make sure they are executed exclusively. + */ +int32_t HAL_UART_Receive_Poll(UART_ID uartID, uint8_t *buf, int32_t size, uint32_t msec) +{ + UART_T *uart; + uint8_t *ptr; + int32_t left; + uint32_t endTick; + UART_Private *priv; + + UART_ASSERT_ID(uartID); + + if (buf == NULL || size <= 0) { + return -1; + } + + priv = UART_GetUartPriv(uartID); + if (priv->rxReadyCallback != NULL) { + HAL_WRN("rx callback is enabled\n"); + return -1; + } + + /* TODO: add protection */ + + uart = HAL_UART_GetInstance(uartID); + ptr = buf; + left = size; + + if (msec != HAL_WAIT_FOREVER) { + endTick = HAL_Ticks() + HAL_MSecsToTicks(msec); + } + while (left > 0) { + if (HAL_UART_IsRxReady(uart)) { + *ptr = HAL_UART_GetRxData(uart); + ++ptr; + --left; + } else if (msec != HAL_WAIT_FOREVER) { + if (HAL_TimeAfter(HAL_Ticks(), endTick)) { + break; + } + } + } + + /* TODO: add protection */ + + return (size - left); +} + +/** + * @brief Start or stop to transmit break characters + * @param[in] uartID ID of the specified UART + * @param[in] isSet + * @arg !0 Start to transmit break characters + * @arg 0 Stop to transmit break characters + * @return None + */ +void HAL_UART_SetBreakCmd(UART_ID uartID, int8_t isSet) +{ + UART_T *uart; + + UART_ASSERT_ID(uartID); + + uart = HAL_UART_GetInstance(uartID); + + if (isSet) { + HAL_SET_BIT(uart->LINE_CTRL, UART_BREAK_CTRL_BIT); + } else { + HAL_CLR_BIT(uart->LINE_CTRL, UART_BREAK_CTRL_BIT); + } +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_util.c b/platform/mcu/xr871/src/driver/chip/hal_util.c new file mode 100644 index 0000000000..37c8434adc --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_util.c @@ -0,0 +1,62 @@ +/** + * @file hal_util.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "driver/chip/hal_rtc.h" + +/** + * @brief Provide accurate delay (in microsecond), and its accuracy is about + * 32 microseconds. + * @param[in] us Time (in microsecond) to delay + * @return None + * + * @note Avoid using this function to delay for a long time (longer than 10ms), + * because its execution will occupy a lot of CPU resource. + */ +void HAL_UDelay(uint32_t us) +{ +#if defined(__CONFIG_CHIP_XR871) + uint64_t expire; + + expire = us + HAL_RTC_GetFreeRunTime(); + while (expire > HAL_RTC_GetFreeRunTime()) + ; +#else /* __CONFIG_CHIP_XR871 */ + unsigned int cpu_clk, i; + + cpu_clk = HAL_PRCM_GetCPUAClk() / 2000; + for (i = 0; i < cpu_clk; i++) + i = i; +#endif /* __CONFIG_CHIP_XR871 */ +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_wakeup.c b/platform/mcu/xr871/src/driver/chip/hal_wakeup.c new file mode 100644 index 0000000000..fd4ab8eb57 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_wakeup.c @@ -0,0 +1,364 @@ +/** + * @file hal_wakeup.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sys/io.h" +#include "driver/chip/hal_wakeup.h" +#include "hal_base.h" + +#define HAL_DBG_WAKEUP 1 + +#if (HAL_DBG_WAKEUP == 1) +#define WK_INF(fmt, arg...) HAL_LOG(HAL_DBG_ON && 0, "[WK] "fmt, ##arg) +#define WK_WAR(fmt, arg...) HAL_LOG(HAL_DBG_ON && HAL_DBG_WAKEUP, "[WK] "fmt, ##arg) +#define WK_ERR(fmt, arg...) HAL_LOG(HAL_DBG_ON && HAL_DBG_WAKEUP, "[WK] "fmt, ##arg) +#else +#define WK_INF(fmt, arg...) +#define WK_WAR(fmt, arg...) +#define WK_ERR(fmt, arg...) +#endif + +#define WAKEUP_IRQn A_WAKEUP_IRQn +#define WAKEUP_GetTimerPending() HAL_PRCM_GetWakeupTimerPending() +#define WAKEUP_ClearTimerPending() HAL_PRCM_ClearWakeupTimerPending() +#define WAKEUP_GetTimerEnable() HAL_PRCM_GetWakeupTimerEnable() + +static uint32_t wakeup_event; + +#ifdef __CONFIG_ARCH_APP_CORE +static void Wakeup_ClrIO() +{ + HAL_PRCM_WakeupIODisableCfgHold((1< counter to wakeup system based on 32k counter. from + * WAKEUP_TIMER_MIN_TIME*32(WAKEUP_TIMER_MIN_TIME mS) to 134217727(4194.303S). + * retval 0 if success or other if failed. + */ +int32_t HAL_Wakeup_SetTimer(uint32_t count_32k) +{ +#ifdef WAKEUP_TIMER_CHECK_TIME + uint32_t current_count; + unsigned long flags; +#endif + + if ((count_32k < (32*WAKEUP_TIMER_MIN_TIME)) || (count_32k & PRCM_CPUx_WAKE_TIMER_EN_BIT)) + return -1; + +#ifdef WAKEUP_TIMER_CHECK_TIME + flags = arch_irq_save(); + current_count = HAL_PRCM_WakeupTimerGetCurrentValue(); + if (wakeup_time_back > current_count) + wakeup_time_back -= current_count; + else + WK_WAR("WAR:%s,%d\n", __func__, __LINE__); + + if (wakeup_time_back <= count_32k) { + arch_irq_restore(flags); + WK_WAR("ignor time set, bk:%d cu:%d\n", wakeup_time_back, count_32k); + return -1; + } + + wakeup_time_back = count_32k; + arch_irq_restore(flags); +#endif + Wakeup_DisTimer(); + HAL_PRCM_WakeupTimerSetCompareValue(count_32k); + HAL_PRCM_WakeupTimerEnable(); + + return 0; +} + +#ifdef __CONFIG_ARCH_APP_CORE +static uint32_t wakeup_io_en; +static uint32_t wakeup_io_mode; + +/** + * @brief Set wakeup IO enable and mode. + * @note This won't change IO config immediately, the enabled IO will be setted + * to input and wakeup mode before system enter lowpower mode. And the IO + * will be disabled after wakeup. So reinit IO if you want this IO used + * as other function. The IO will used as wakeup IO until be cleaned. + * @param pn: + * @arg pn-> 0~9. + * @param mode: + * @arg mode-> 0:negative edge, 1:positive edge. + * retval None. + */ +void HAL_Wakeup_SetIO(uint32_t pn, uint32_t mode) +{ + if (pn >= WAKEUP_IO_MAX || mode > 1) { + WK_ERR("%s,%d err\n", __func__, __LINE__); + return; + } + + /* mode */ + if (mode) + wakeup_io_mode |= BIT(pn); + else + wakeup_io_mode &= ~BIT(pn); + + /* enable */ + wakeup_io_en |= BIT(pn); +} + +/** + * @brief Clear wakeup IO enable. + * @param pn: + * @arg pn-> 0~9. + * retval None. + */ +void HAL_Wakeup_ClrIO(uint32_t pn) +{ + wakeup_io_en &= ~BIT(pn); +} + +static GPIO_Pin WakeIo_To_Gpio(uint32_t wkup_io) +{ + switch (wkup_io) { + case 0: return WAKEUP_IO0; + case 1: return WAKEUP_IO1; + case 2: return WAKEUP_IO2; + case 3: return WAKEUP_IO3; + case 4: return WAKEUP_IO4; + case 5: return WAKEUP_IO5; + case 6: return WAKEUP_IO6; + case 7: return WAKEUP_IO7; + case 8: return WAKEUP_IO8; + case 9: return WAKEUP_IO9; + } + + WK_ERR("%s,%d err!\n", __func__, __LINE__); + + return 0; +} + +/** + * @brief Set IO hold. + * @note Set all IO hold before poweroff to prevent IO output low level voltage. + * @param hold_io: + * @arg hold_io-> IO hold mask. + * retval 0 if success or other if failed. + */ +int32_t HAL_Wakeup_SetIOHold(uint32_t hold_io) +{ + /* clear */ + HAL_PRCM_WakeupIOClearEventDetected(HAL_PRCM_WakeupIOGetEventStatus()); + /* set hold */ + HAL_PRCM_WakeupIOEnableCfgHold(hold_io); + + return 0; +} +#endif + +/** + * @brief Config and enable wakeup io. + * retval 0 if success or other if failed. + */ +int32_t HAL_Wakeup_SetSrc(void) +{ +#ifdef __CONFIG_ARCH_APP_CORE + uint32_t i, wkio_input; +#endif + + /* check wakeup time */ + if (WAKEUP_GetTimerEnable() && + (HAL_PRCM_WakeupTimerGetCompareValue() <= (32*WAKEUP_TIMER_MIN_TIME))) { + WK_ERR("wakeup timer err:%x\n", HAL_PRCM_WakeupTimerGetCurrentValue()); + return -1; + } + +#ifdef __CONFIG_ARCH_APP_CORE + /* enable wakeup gpio if configed wakeup io */ + if (wakeup_io_en) { + wkio_input = wakeup_io_en; + for (i = 0; (i < WAKEUP_IO_MAX) && wkio_input; wkio_input >>= 1, i++) { + if (wkio_input & 0x01) { + GPIO_InitParam param; + + param.mode = GPIOx_Pn_F0_INPUT; + param.driving = GPIO_DRIVING_LEVEL_1; + param.pull = GPIO_PULL_UP; + WK_INF("init io:%d\n", WakeIo_To_Gpio(i)); + HAL_GPIO_Init(GPIO_PORT_A, WakeIo_To_Gpio(i), ¶m); /* set input */ + } + } + /* clear */ + HAL_PRCM_WakeupIOClearEventDetected(HAL_PRCM_WakeupIOGetEventStatus()); + /* mode */ + HAL_PRCM_WakeupIOSetRisingEvent(wakeup_io_mode); + /* enable */ + HAL_PRCM_WakeupIOEnable(wakeup_io_en); + /* enable global wakeup io */ + HAL_PRCM_WakeupIOEnableGlobal(); + /* set hold if this io enable */ + HAL_PRCM_WakeupIOEnableCfgHold(wakeup_io_en); + } +#endif + + NVIC_EnableIRQ(WAKEUP_IRQn); /* enable when sleep */ + + return 0; +} + +/** @brief Disable wakeup io. */ +void HAL_Wakeup_ClrSrc(void) +{ +#ifdef __CONFIG_ARCH_APP_CORE + uint32_t i, wkio_input; +#endif +#ifdef WAKEUP_TIMER_CHECK_TIME + unsigned long flags; +#endif + +#ifdef __CONFIG_ARCH_APP_CORE + /* wakeup io event */ + wakeup_event = HAL_PRCM_WakeupIOGetEventStatus(); +#else + wakeup_event = 0; +#endif + + /* wakeup timer event */ + if (WAKEUP_GetTimerPending()) { + WAKEUP_ClearTimerPending(); + while (WAKEUP_GetTimerPending()) + ; + wakeup_event |= PM_WAKEUP_SRC_WKTIMER; +#ifdef WAKEUP_TIMER_CHECK_TIME + flags = arch_irq_save(); + wakeup_time_back = 0xffffffff; + arch_irq_restore(flags); +#endif + } + + /* no events is net cpu sev */ + if (!wakeup_event) + wakeup_event = PM_WAKEUP_SRC_WKSEV; + +#ifdef __CONFIG_ARCH_APP_CORE + if (wakeup_io_en) { + wkio_input = wakeup_io_en; + for (i = 0; (i < WAKEUP_IO_MAX) && wkio_input; wkio_input >>= 1, i++) { + if (wkio_input & 0x01) { + HAL_GPIO_DeInit(GPIO_PORT_A, WakeIo_To_Gpio(i)); + WK_INF("deinit io:%d\n", i); + } + } + } +#endif + + NVIC_EnableIRQ(WAKEUP_IRQn); +} + + +/** + * @brief Get last wakeup event. + * retval Events defined in PM_WAKEUP_SRC_XX. + */ +uint32_t HAL_Wakeup_GetEvent(void) +{ + return wakeup_event; +} + +/** @brief Init wakeup IO and Timer as disable mode. */ +void HAL_Wakeup_Init(void) +{ + Wakeup_ClrTimer(); + Wakeup_DisTimer(); +#ifdef __CONFIG_ARCH_APP_CORE + Wakeup_ClrIO(); +#endif + + HAL_NVIC_SetIRQHandler(WAKEUP_IRQn, Wakeup_Source_Handler); + NVIC_ClearPendingIRQ(WAKEUP_IRQn); + NVIC_EnableIRQ(WAKEUP_IRQn); +} + +/** @brief Deinit wakeup IO and Timer. */ +void HAL_Wakeup_DeInit(void) +{ + NVIC_DisableIRQ(WAKEUP_IRQn); + +#ifdef __CONFIG_ARCH_APP_CORE + Wakeup_ClrIO(); +#endif + Wakeup_DisTimer(); +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_wdg.c b/platform/mcu/xr871/src/driver/chip/hal_wdg.c new file mode 100644 index 0000000000..fcbcb46fcd --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_wdg.c @@ -0,0 +1,257 @@ +/** + * @file hal_wdg.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "pm/pm.h" + +#include "driver/chip/hal_wdg.h" +#include "hal_base.h" + +/* Note: Has no 32000HZ clock source, use WDG_CLK_32768HZ by default */ +#define WDG_CLK_SRC_SHIFT 8 +#define WDG_CLK_SRC_MASK (0x1U << WDG_CLK_SRC_SHIFT) +typedef enum { + WDG_CLK_32000HZ = (0U << WDG_CLK_SRC_SHIFT), + WDG_CLK_32768HZ = (1U << WDG_CLK_SRC_SHIFT) +} WDG_ClkSrc; + +#define WDG_RELOAD_VAL ((0xA57 << 1) | 1) + +typedef struct { + WDG_IRQCallback callback; + void *arg; +} WDG_Private; + +static WDG_Private gWdgPrivate; + +static void WDG_EnableIRQ(void) +{ + HAL_SET_BIT(WDG->IRQ_EN, WDG_IRQ_EN_BIT); +} + +static void WDG_DisableIRQ(void) +{ + HAL_CLR_BIT(WDG->IRQ_EN, WDG_IRQ_EN_BIT); +} + +static int WDG_IsPendingIRQ(void) +{ + return HAL_GET_BIT(WDG->IRQ_STATUS, WDG_IRQ_PENDING_BIT); +} + +static void WDG_ClearPendingIRQ(void) +{ + HAL_SET_BIT(WDG->IRQ_STATUS, WDG_IRQ_PENDING_BIT); +} + +void WDG_IRQHandler(void) +{ + if (WDG_IsPendingIRQ()) { + WDG_ClearPendingIRQ(); + if (gWdgPrivate.callback) { + gWdgPrivate.callback(gWdgPrivate.arg); + } + } +} + +#ifdef CONFIG_PM +static WDG_InitParam hal_wdg_param; +static uint32_t hal_wdg_suspending = 0; +static uint32_t hal_wdg_runing = 0; + +static int wdg_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + hal_wdg_suspending = 1; + + HAL_WDG_DeInit(); + //HAL_DBG("%s okay\n", __func__); + + return 0; +} + +static int wdg_resume(struct soc_device *dev, enum suspend_state_t state) +{ + HAL_WDG_Init(&hal_wdg_param); + //HAL_DBG("%s okay\n", __func__); + + if (hal_wdg_runing) + HAL_WDG_Start(); + else + HAL_WDG_Stop(); + + hal_wdg_suspending = 0; + + return 0; +} + +static struct soc_device_driver wdg_drv = { + .name = "wdg", + .suspend = wdg_suspend, + .resume = wdg_resume, +}; + +static struct soc_device wdg_dev = { + .name = "wdg", + .driver = &wdg_drv, +}; + +#define WDG_DEV (&wdg_dev) +#endif + +/** + * @brief Initialize the watchdog according to the specified parameters + * @param[in] param Pointer to WDG_InitParam structure + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_WDG_Init(const WDG_InitParam *param) +{ + /* enable clock */ + + /* release reset */ + + /* init parameters */ + WDG->MODE = param->timeout; /* NB: it will clear WDG_IRQ_EN_BIT (stop WDG) */ + WDG->CFG = param->event | WDG_CLK_32768HZ; + + if (param->event == WDG_EVT_RESET) { + WDG->RESET_CTRL = ((param->resetCycle << WDG_RESET_CYCLE_SHIFT) & + WDG_RESET_CYCLE_MASK); + } else if (param->event == WDG_EVT_INTERRUPT) { + gWdgPrivate.callback = param->callback; + gWdgPrivate.arg = param->arg; + if (WDG_IsPendingIRQ()) { + WDG_ClearPendingIRQ(); + } + WDG_EnableIRQ(); + HAL_NVIC_SetPriority(WDG_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + HAL_NVIC_EnableIRQ(WDG_IRQn); + } else { + HAL_ERR("Invalid event type 0x%x\n", param->event); + return HAL_ERROR; + } + +#ifdef CONFIG_PM + if (!hal_wdg_suspending) { + memcpy(&hal_wdg_param, param, sizeof(WDG_InitParam)); + pm_register_ops(WDG_DEV); + } +#endif + + return HAL_OK; +} + +/** + * @brief DeInitialize the watchdog + * @retval HAL_Status, HAL_OK on success + */ +HAL_Status HAL_WDG_DeInit(void) +{ + HAL_WDG_Stop(); + +#ifdef CONFIG_PM + if (!hal_wdg_suspending) { + pm_unregister_ops(WDG_DEV); + } +#endif + + /* disable IRQ */ + HAL_NVIC_DisableIRQ(WDG_IRQn); + WDG_DisableIRQ(); + if (WDG_IsPendingIRQ()) { + WDG_ClearPendingIRQ(); + } + + gWdgPrivate.callback = NULL; + gWdgPrivate.arg = NULL; + + /* force reset */ + + /* disable clock */ + + return HAL_OK; +} + +/** + * @brief Feed the watchdog + * @note When watchdog running, reset system or IRQ event will be triggered if + * no feeding executed in the interval configured by HAL_WDG_Init(). + * @return None + */ +void HAL_WDG_Feed(void) +{ + WDG->CTRL = WDG_RELOAD_VAL; +} + +/** + * @brief Start the watchdog + * @return None + */ +void HAL_WDG_Start(void) +{ + HAL_WDG_Feed(); +#ifdef CONFIG_PM + if (!hal_wdg_suspending) + hal_wdg_runing = 1; +#endif + HAL_SET_BIT(WDG->MODE, WDG_EN_BIT); +} + +/** + * @brief Stop the watchdog + * @return None + */ +void HAL_WDG_Stop(void) +{ + HAL_CLR_BIT(WDG->MODE, WDG_EN_BIT); +#ifdef CONFIG_PM + if (!hal_wdg_suspending) + hal_wdg_runing = 0; +#endif +} + +/** + * @brief Reboot system using the watchdog + * @return None + */ +void HAL_WDG_Reboot(void) +{ + HAL_DisableIRQ(); + HAL_PRCM_DisableSys2(); + HAL_PRCM_DisableSys2Power(); + WDG->MODE = WDG_TIMEOUT_500MS; /* NB: it will clear WDG_IRQ_EN_BIT (stop WDG) */ + WDG->CFG = WDG_EVT_RESET | WDG_CLK_32768HZ; + WDG->RESET_CTRL = ((WDG_DEFAULT_RESET_CYCLE << WDG_RESET_CYCLE_SHIFT) & + WDG_RESET_CYCLE_MASK); + HAL_WDG_Start(); + while (1) ; +} diff --git a/platform/mcu/xr871/src/driver/chip/hal_xip.c b/platform/mcu/xr871/src/driver/chip/hal_xip.c new file mode 100644 index 0000000000..1266740aff --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/hal_xip.c @@ -0,0 +1,245 @@ +/** + * @file hal_xip.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "hal_base.h" +#include "driver/chip/hal_flashctrl.h" +#include "driver/chip/hal_flash.h" +#include "driver/chip/hal_xip.h" +#include "hal_os.h" +#include "sys/param.h" + +#include "pm/pm.h" + + +#define XIP_DEBUG(msg, arg...) XR_DEBUG((DBG_OFF | XR_LEVEL_ERROR), NOEXPAND, "[XIP iface debug] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) +#define XIP_ERROR(msg, arg...) XR_ERROR((DBG_ON | XR_LEVEL_ALL), NOEXPAND, "[XIP iface error] <%s : %d> " msg "\n", __func__, __LINE__, ##arg) + +FlashChipBase *getFlashChip(FlashDev *dev); +FlashReadMode getFlashMode(FlashDev *dev); +FlashDev *getFlashDev(uint32_t flash); +void insToFcIns(InstructionField *ins, FC_InstructionField *fcins); +static int setCmd(XipDriverBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data); +static int setContinue(XipDriverBase *base, uint32_t continueMode, void *arg); +static int setDelay(XipDriverBase *base, Flashc_Delay *delay); +static int setAddr(XipDriverBase *base, uint32_t addr); +/*void HAL_Flashc_Xip_RawEnable(); +void HAL_Flashc_Xip_Enable(); +void HAL_Flashc_Xip_RawDisable(); +void HAL_Flashc_Xip_Disable();*/ + +static XipDriverBase xipDrv = {0}; +#ifdef CONFIG_PM +static struct soc_device Xip_dev; +#endif + + +/** + * @brief Initializes XIP module. + * @note XIP is a module that cpu can run the code in flash but not ram. + * @param flash: flash number, this flash must have been initialized, and must + * be connected to the flash controller pin. + * @param xaddr: XIP code start address. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Xip_Init(uint32_t flash, uint32_t xaddr) +{ + HAL_Status ret = HAL_OK; + FlashDev *dev; + FlashChipBase *chip; + FlashBoardCfg *cfg; + int devNum = HAL_MKDEV(HAL_DEV_MAJOR_FLASH, flash); + + HAL_BoardIoctl(HAL_BIR_GET_CFG, devNum, (uint32_t)&cfg); + if (cfg->type != FLASH_DRV_FLASHC) + return HAL_INVALID; + + dev = getFlashDev(flash); + if (dev == NULL) + return HAL_INVALID; + + xipDrv.flash = flash; + xipDrv.dev = dev; + xipDrv.setAddr = setAddr; + xipDrv.setCmd = setCmd; + xipDrv.setContinue = setContinue; + xipDrv.setDelay = setDelay; + HAL_Memset(&xipDrv.mCfg, 0, sizeof(xipDrv.mCfg)); + + chip = getFlashChip(dev); + + chip->mXip = &xipDrv; + + chip->enableXIP(chip); + chip->xipDriverCfg(chip, getFlashMode(dev)); + xipDrv.mCfg.freq = cfg->flashc.clk; + xipDrv.mCfg.addr = xaddr; + + HAL_Flashc_Xip_Init(&xipDrv.mCfg); + +#ifdef CONFIG_PM + pm_register_ops(&Xip_dev); +#endif + + return ret; +} + +/** + * @brief Deinitializes XIP module. + * @retval HAL_Status: The status of driver + */ +HAL_Status HAL_Xip_Deinit(void) +{ + HAL_Status ret = HAL_OK; + FlashChipBase *chip = getFlashChip(xipDrv.dev); + +#ifdef CONFIG_PM + pm_unregister_ops(&Xip_dev); +#endif + + HAL_Flashc_Xip_Deinit(); + chip->disableXIP(chip); + + return ret; +} +/* +static HAL_Status HAL_XIP_Enable() +{ + +} + +static HAL_Status HAL_XIP_Disable() +{ + +}*/ + +static int setCmd(struct XipDriverBase *base, InstructionField *cmd, InstructionField *addr, InstructionField *dummy, InstructionField *data) +{ + FC_InstructionField tmp; + XIP_Instruction *ins = &base->mCfg.ins; + + insToFcIns(cmd, &tmp); + ins->cmd = *tmp.pdata; + ins->cmd_line = tmp.line; + + insToFcIns(addr, &tmp); + ins->addr_line = tmp.line; + + insToFcIns(dummy, &tmp); + ins->dummy_line = tmp.line; + ins->dum_btyes = tmp.len; + + insToFcIns(data, &tmp); + ins->data_line = tmp.line; + + return 0; +} + +static int setContinue(struct XipDriverBase *base, uint32_t continueMode, void *arg) +{ + base->mCfg.cont_mode = continueMode; + + return 0; +} + +static int setDelay(struct XipDriverBase *base, Flashc_Delay *delay) +{ + /*TODO: how and where should be the delay calculation*/ + + return 0; +} + +static int setAddr(struct XipDriverBase *base, uint32_t addr) +{ + base->mCfg.addr = addr; + + return 0; +} + + +#ifdef CONFIG_PM +//#define FLASH_POWERDOWN (PM_MODE_POWEROFF) + +static int PM_XipSuspend(struct soc_device *dev, enum suspend_state_t state) +{ + FlashChipBase *chip = getFlashChip(xipDrv.dev); + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + chip->disableXIP(chip); + break; + default: + break; + } + + return 0; +} + +static int PM_XipResume(struct soc_device *dev, enum suspend_state_t state) +{ + FlashChipBase *chip = getFlashChip(xipDrv.dev); + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + chip->enableXIP(chip); + break; + default: + break; + } + + return 0; +} + +static struct soc_device_driver Xip_drv = { + .name = "Xip", + .suspend = PM_XipSuspend, + .resume = PM_XipResume, +}; + +static struct soc_device Xip_dev = { + .name = "Xip", + .driver = &Xip_drv, +}; + +#endif + diff --git a/platform/mcu/xr871/src/driver/chip/ir_nec.c b/platform/mcu/xr871/src/driver/chip/ir_nec.c new file mode 100644 index 0000000000..f376b06dbb --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/ir_nec.c @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sys/xr_debug.h" +#include "driver/chip/ir_nec.h" +#include "hal_base.h" + +#define HAL_DBG_IRNEC 0 + +#if (HAL_DBG_IRNEC == 1) +#define IRNEC_DBG(fmt, arg...) HAL_LOG(HAL_DBG_ON && HAL_DBG_IRNEC, "[IRNEC] "fmt, ##arg) +#define irnec_hex_dump_bytes(...) print_hex_dump_bytes(__VA_ARGS__) +#define IRNEC_INF IRNEC_DBG +#define IRNEC_WRN HAL_WRN +#define IRNEC_ERR HAL_ERR +#else +#define irnec_hex_dump_bytes(...) +#define IRNEC_INF(...) +#define IRNEC_WRN(...) +#define IRNEC_ERR(...) +#endif + +/** + * @brief DePacket code by NEC protocal. + * @param buf: + * @arg buf->[in]Raw code buffer. + * @param dcnt: + * @arg dcnt->[in] Num of Raw code. + * @retval DePacket code if success or 0xffffffff if depacket failed. + */ +uint32_t IRRX_NECPacket_DeCode(uint8_t *buf, uint32_t dcnt) +{ + uint32_t len; + uint8_t val = 0, last; + uint32_t code = 0; + int32_t bitCnt = 0; + uint32_t i = 0; + uint32_t active_delay = 0; + uint32_t irrx_l1_min = 0, irrx_l0_min = 0, irrx_pmax = 0, irrx_dmid = 0, irrx_dmax = 0; +#if !defined (IR_CLK_32K_USED) + uint32_t clk = HAL_GetHFClock(); +#endif + + irnec_hex_dump_bytes(buf, dcnt); + + IRNEC_INF("dcnt = %d\n", dcnt); + + /* Find Lead '1' */ +#if defined (IR_CLK_32K_USED) + active_delay = (IRRX_32K_ACTIVE_T + 1) * (IRRX_32K_ACTIVE_T_C ? 128 : 1); + irrx_l1_min = IRRX_32K_L1_MIN; + irrx_l0_min = IRRX_32K_L0_MIN; + irrx_pmax = IRRX_32K_PMAX; + irrx_dmid = IRRX_32K_DMID; + irrx_dmax = IRRX_32K_DMAX; +#else + if (clk == HOSC_CLOCK_26M) { + active_delay = (IRRX_26M_ACTIVE_T + 1) * (IRRX_26M_ACTIVE_T_C ? 128 : 1); + irrx_l1_min = IRRX_26M_L1_MIN; + irrx_l0_min = IRRX_26M_L0_MIN; + irrx_pmax = IRRX_26M_PMAX; + irrx_dmid = IRRX_26M_DMID; + irrx_dmax = IRRX_26M_DMAX; + } else if (clk == HOSC_CLOCK_24M) { + active_delay = (IRRX_24M_ACTIVE_T + 1) * (IRRX_24M_ACTIVE_T_C ? 128 : 1); + irrx_l1_min = IRRX_24M_L1_MIN; + irrx_l0_min = IRRX_24M_L0_MIN; + irrx_pmax = IRRX_24M_PMAX; + irrx_dmid = IRRX_24M_DMID; + irrx_dmax = IRRX_24M_DMAX; + } +#endif + //IRNEC_INF("active_delay = %d\n", active_delay); + len = 0; + len += (active_delay >> 1); + for (i = 0; i < dcnt; i++) { + val = buf[i]; + if (val & 0x80) { + len += val & 0x7f; + } else { + if (len > irrx_l1_min) + break; + len = 0; + } + } + + //IRNEC_INF("'1' len = %d\n", len); + + if ((val & 0x80) || (len <= irrx_l1_min)){ + IRNEC_INF("start 1 error code %d\n", len); + goto error_code; + } + + /* Find Lead '0' */ + len = 0; + for (; i < dcnt; i++) { + val = buf[i]; + if (val & 0x80) { + if (len > irrx_l0_min) + break; + len = 0; + } else { + len += val & 0x7f; + } + } + + //IRNEC_INF("'0' len = %d\n", len); + + if ((!(val & 0x80)) || (len <= irrx_l0_min)){ + IRNEC_INF("start 0 error code %d\n", len); + goto error_code; + } + + /* go decoding */ + code = 0; /* 0 for Repeat Code */ + bitCnt = 0; + last = 1; + len = 0; + for (; i < dcnt; i++) { + val = buf[i]; + if (last) { + if (val & 0x80) { + len += val & 0x7f; + } else { + if (len > irrx_pmax) { /* Error Pulse */ + IRNEC_INF("len:%d > IRRX_PMAX @%d\n", len, i); + goto error_code; + } + last = 0; + len = val & 0x7f; + } + } else { + if (val & 0x80) { + if (len > irrx_dmax){ /* Error Distant */ + IRNEC_INF("len:%d > IRRX_DMAX @%d\n", len, i); + goto error_code; + } else { + if (len > irrx_dmid) { + /* data '1'*/ + code |= 1 << bitCnt; + } + bitCnt++; + if (bitCnt == 32) + break; /* decode over */ + } + last = 1; + len = val & 0x7f; + } else { + len += val & 0x7f; + } + } + } + return code; + +error_code: + irnec_hex_dump_bytes(buf, dcnt); + + return (uint32_t)-1; +} + +int32_t IRRX_NECCode_Valid(uint32_t code) +{ + uint32_t tmp1, tmp2; + +#ifdef IRRX_CHECK_ADDR_CODE + /* Check Address Value */ + if ((code & 0xffff) != (IRRX_ADDR_CODE & 0xffff)) + return 0; /* Address Error */ + + tmp1 = code & 0x00ff0000; + tmp2 = (code & 0xff000000) >> 8; + + return ((tmp1 ^ tmp2) == 0x00ff0000); /* Check User Code */ +#else + /* Do Not Check Address Value */ + tmp1 = code & 0x00ff00ff; + tmp2 = (code & 0xff00ff00) >> 8; + + return (((tmp1 ^ tmp2) & 0x00ff0000) == 0x00ff0000); +#endif +} + +/** + * @brief Packet code by NEC protocal. + * @param txBuff: + * @arg txBuff->[out] Raw code will put in. + * @param ir_tx_code: + * @arg ir_tx_code->[in] The code will be Packeted. + * @retval Raw code num. + */ +uint32_t IRTX_NECPacket_Code(uint8_t *txBuff, uint32_t ir_tx_code) +{ + uint32_t i, j; + uint32_t txCnt = 0; + uint8_t tx_code[4]; +#if !defined (IR_CLK_32K_USED) + uint32_t clk = HAL_GetHFClock(); +#endif + uint32_t irtx_560us_num = 0, irtx_1680us_num = 0; + + tx_code[0] = (uint8_t)(ir_tx_code >> 24); + tx_code[1] = (uint8_t)(ir_tx_code >> 16); + tx_code[2] = (uint8_t)(ir_tx_code >> 8); + tx_code[3] = (uint8_t)(ir_tx_code & 0xff); + + /* go encoding */ +#if defined (IR_CLK_32K_USED) + txBuff[txCnt++] = 0x80|IRTX_32K_9MS_NUM1; /* S1:9ms */ + txBuff[txCnt++] = 0x80|IRTX_32K_9MS_NUM2; + txBuff[txCnt++] = IRTX_32K_4P5MS_NUM1; /* S0:4.5ms */ + irtx_560us_num = IRTX_32K_560US_NUM; + irtx_1680us_num = IRTX_32K_1680US_NUM; +#else + if (clk == HOSC_CLOCK_26M) { + txBuff[txCnt++] = 0x80|IRTX_26M_9MS_NUM1; /* S1:9ms */ + txBuff[txCnt++] = 0x80|IRTX_26M_9MS_NUM2; + txBuff[txCnt++] = IRTX_26M_4P5MS_NUM1; /* S0:4.5ms */ + irtx_560us_num = IRTX_26M_560US_NUM; + irtx_1680us_num = IRTX_26M_1680US_NUM; + } else if (clk == HOSC_CLOCK_24M) { + txBuff[txCnt++] = 0x80|IRTX_24M_9MS_NUM1; /* S1:9ms */ + txBuff[txCnt++] = 0x80|IRTX_24M_9MS_NUM2; + txBuff[txCnt++] = IRTX_24M_4P5MS_NUM1; /* S0:4.5ms */ + irtx_560us_num = IRTX_24M_560US_NUM; + irtx_1680us_num = IRTX_24M_1680US_NUM; + } +#endif + + for (j = 0; j < 4; j++) { + for (i = 0; i < 8; i++ ) { + if (tx_code[j] & 0x01) { + /* L1:560uS, 1680uS */ + txBuff[txCnt++] = 0x80|irtx_560us_num; + txBuff[txCnt++] = irtx_1680us_num; + } else { + /* L0:560uS, 560uS */ + txBuff[txCnt++] = 0x80|irtx_560us_num; + txBuff[txCnt++] = irtx_560us_num; + } + tx_code[j] = tx_code[j] >> 1; + } + } + txBuff[txCnt++] = 0x80|irtx_560us_num; + txBuff[txCnt++] = irtx_560us_num; /* add for set gpio to 0 */ + txBuff[txCnt++] = 0x7f; + txBuff[txCnt++] = 0x7f; + txBuff[txCnt++] = 0x7f; + txBuff[txCnt++] = 0x7f; + + IRNEC_INF("%s: tx_dcnt = %d\n", __func__, txCnt); + irnec_hex_dump_bytes(txBuff, txCnt); + + return txCnt; +} + +#undef IRNEC_INF +#undef IRNEC_WRN +#undef IRNEC_ERR diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/_sd.h b/platform/mcu/xr871/src/driver/chip/sdmmc/_sd.h new file mode 100644 index 0000000000..68af307f0e --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/_sd.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_SDMMC_SD_H_ +#define _DRIVER_CHIP_SDMMC_SD_H_ + +#include "core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern int32_t mmc_wait_for_app_cmd(struct mmc_host *host, struct mmc_card *card, struct mmc_command *cmd); +extern int32_t mmc_app_cmd(struct mmc_host *host, struct mmc_card *card); +extern int32_t mmc_send_relative_addr(struct mmc_host *host, uint32_t *rca); +extern int32_t mmc_send_if_cond(struct mmc_host *host, uint32_t ocr); +extern int32_t mmc_app_sd_status(struct mmc_card *card, uint8_t *ssr); +extern uint32_t mmc_sd_get_max_clock(struct mmc_card *card); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_SDMMC_SD_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/core.c b/platform/mcu/xr871/src/driver/chip/sdmmc/core.c new file mode 100644 index 0000000000..78d01bde82 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/core.c @@ -0,0 +1,970 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../hal_base.h" + +#include "driver/chip/sdmmc/hal_sdhost.h" +#include "driver/chip/sdmmc/sdmmc.h" +#ifdef CONFIG_USE_SDIO +#include "driver/chip/sdmmc/sdio.h" +#endif +#include "sdhost.h" +#include "core.h" +#ifdef CONFIG_USE_SDIO +#include "_sdio.h" +#endif +#ifdef CONFIG_USE_SD +#include "_sd.h" +#endif +#ifdef CONFIG_USE_MMC +#include "_mmc.h" +#endif + +/** + * mmc_wait_for_req - start a request and wait for completion + * @host: MMC host to start command + * @mrq: MMC request to start + * + * Start a new MMC custom command request for a host, and wait + * for the command to complete. Does not attempt to parse the + * response. + */ +int32_t mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq) +{ + mrq->cmd->data = mrq->data; + return HAL_SDC_Request(host, mrq); +} + +/** + * mmc_wait_for_cmd - start a command and wait for completion + * @host: MMC host to start command + * @cmd: MMC command to start + * @retries: maximum number of retries + * + * Start a new MMC command for a host, and wait for the command + * to complete. Return any error that occurred while the command + * was executing. Do not attempt to parse the response. + */ +int32_t mmc_wait_for_cmd(struct mmc_host *host, struct mmc_command *cmd) +{ + struct mmc_request mrq = {0}; + + memset(cmd->resp, 0, sizeof(cmd->resp)); + + mrq.cmd = cmd; + + return mmc_wait_for_req(host, &mrq); +} + +/** + * mmc_align_data_size - pads a transfer size to a more optimal value + * @card: the MMC card associated with the data transfer + * @sz: original transfer size + * + * Pads the original data size with a number of extra bytes in + * order to avoid controller bugs and/or performance hits + * (e.g. some controllers revert to PIO for certain sizes). + * + * Returns the improved size, which might be unmodified. + * + * Note that this function is only relevant when issuing a + * single scatter gather entry. + */ +int32_t mmc_align_data_size(struct mmc_card *card, uint32_t sz) +{ + /* + * FIXME: We don't have a system for the controller to tell + * the core about its problems yet, so for now we just 32-bit + * align the size. + */ + sz = ((sz + 3) / 4) * 4; + + return sz; +} + +static inline void mmc_host_clk_hold(struct mmc_host *host) +{ + HAL_SDC_Clk_PWR_Opt(host, 1, 0); +} + +static inline void mmc_host_clk_release(struct mmc_host *host) +{ + HAL_SDC_Clk_PWR_Opt(host, 0, 0); +} + +/* + * Apply power to the MMC stack. This is a two-stage process. + * First, we enable power to the card without the clock running. + * We then wait a bit for the power to stabilise. Finally, + * enable the bus drivers and clock to the card. + * + * We must _NOT_ enable the clock prior to power stablising. + * + * If a host does all the power sequencing itself, ignore the + * initial MMC_POWER_UP stage. + */ +static void mmc_power_up(struct mmc_host *host) +{ + //int bit; + + mmc_host_clk_hold(host); + + /* If ocr is set, we use it */ + //if (host->ocr) + // bit = ffs(host->ocr) - 1; + //else + // bit = fls(host->ocr_avail) - 1; + + HAL_SDC_PowerOn(host); + + /* + * This delay must be at least 74 clock sizes, or 1 ms, or the + * time required to reach a stable voltage. + */ + mmc_mdelay(10); + + mmc_host_clk_release(host); +} + +static void mmc_power_off(struct mmc_host *host) +{ + mmc_host_clk_hold(host); + + /* + * For eMMC 4.5 device send AWAKE command before + * POWER_OFF_NOTIFY command, because in sleep state + * eMMC 4.5 devices respond to only RESET and AWAKE cmd + */ + //if (host->card && mmc_card_is_sleep(host->card)) { + // mmc_poweroff_notify(host); + //} + + /* + * Reset ocr mask to be the highest possible voltage supported for + * this mmc host. This value will be used at next power up. + */ + //host->ocr = 1 << (fls(host->ocr_avail) - 1); + + HAL_SDC_PowerOff(host); + /* + * Some configurations, such as the 802.11 SDIO card in the OLPC + * XO-1.5, require a short delay after poweroff before the card + * can be successfully turned on again. + */ + mmc_mdelay(1); + + mmc_host_clk_release(host); +} + +static int32_t mmc_go_idle(struct mmc_host *host) +{ + int32_t err; + struct mmc_command cmd = {0}; + + cmd.opcode = MMC_GO_IDLE_STATE; + cmd.arg = 0; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; + + err = mmc_wait_for_cmd(host, &cmd); + + mmc_mdelay(1); + + return err; +} + +int32_t mmc_send_status(struct mmc_card *card, uint32_t *status) +{ + int32_t err; + struct mmc_command cmd = {0}; + + cmd.opcode = MMC_SEND_STATUS; + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC; + + err = mmc_wait_for_cmd(card->host, &cmd); + if (err) + return err; + + /* NOTE: callers are required to understand the difference + * between "native" and SPI format status words! + */ + if (status) + *status = cmd.resp[0]; + + return 0; +} + +#if ((defined CONFIG_USE_SD) || (defined CONFIG_USE_MMC)) +int32_t mmc_sd_switch(struct mmc_card *card, uint8_t mode, uint8_t group, + uint16_t value, uint8_t *resp) +{ + struct mmc_request mrq; + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct scatterlist sg; + + /* NOTE: caller guarantees resp is heap-allocated */ + + mode = !!mode; + value &= 0xF; + + mrq.cmd = &cmd; + mrq.data = &data; + + cmd.opcode = SD_SWITCH; + cmd.arg = mode << 31 | 0x00FFFFFF; + cmd.arg &= ~(0xF << (group * 4)); + cmd.arg |= value << (group * 4); + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; + + data.blksz = 64; + data.blocks = 1; + data.flags = MMC_DATA_READ; + data.sg = &sg; + data.sg_len = 1; + + sg.len = 64; + sg.buffer = resp; + + if (mmc_wait_for_req(card->host, &mrq)) { + return -1; + } + + return 0; +} + +static int32_t mmc_switch(struct mmc_card *card, uint8_t set, uint8_t index, uint8_t value) +{ + struct mmc_command cmd = {0}; + int32_t ret; + uint32_t status = 0; + + cmd.opcode = MMC_SWITCH; + cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | (index << 16) | (value << 8) | set; + cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; + + if (mmc_wait_for_cmd(card->host, &cmd)) { + return -1; + } + + /* Must check status to be sure of no errors */ + do { + ret = mmc_send_status(card, &status); + if (ret) + return ret; + } while (R1_CURRENT_STATE(status) == R1_STATE_PRG); + + if (status & 0xFDFFA000) + SD_LOGW("unexpected status %x after switch", status); + if (status & R1_SWITCH_ERROR) + return -1; + + return 0; +} + +int32_t mmc_switch_part(struct mmc_card *card, uint32_t part_num) +{ + return mmc_switch(card, MMC_EXT_CSD_CMD_SET_NORMAL, MMC_EXT_CSD_PART_CONF, + (card->extcsd.part_config & ~MMC_SWITCH_PART_ACCESS_MASK) + | (part_num & MMC_SWITCH_PART_ACCESS_MASK)); +} + +int32_t mmc_switch_boot_part(struct mmc_card *card, uint32_t boot_ack, uint32_t boot_part) +{ + return mmc_switch(card, MMC_EXT_CSD_CMD_SET_NORMAL, MMC_EXT_CSD_PART_CONF, + (card->extcsd.part_config & (~MMC_SWITCH_PART_BOOT_PART_MASK) & (~MMC_SWITCH_PART_BOOT_ACK_MASK)) + | ((boot_part << 3) & MMC_SWITCH_PART_BOOT_PART_MASK) | (boot_ack << 6)); +} + +int32_t mmc_switch_boot_bus_cond(struct mmc_card *card, uint32_t boot_mode, uint32_t rst_bus_cond, uint32_t bus_width) +{ + return mmc_switch(card, MMC_EXT_CSD_CMD_SET_NORMAL, MMC_EXT_CSD_BOOT_BUS_COND, + (card->extcsd.boot_bus_cond & + (~MMC_SWITCH_BOOT_MODE_MASK) & + (~MMC_SWITCH_BOOT_RST_BUS_COND_MASK) & + (~MMC_SWITCH_BOOT_BUS_WIDTH_MASK)) + | ((boot_mode << 3) & MMC_SWITCH_BOOT_MODE_MASK) + | ((rst_bus_cond << 2) & MMC_SWITCH_BOOT_RST_BUS_COND_MASK) + | ((bus_width) & MMC_SWITCH_BOOT_BUS_WIDTH_MASK) ); +} + +int32_t mmc_app_cmd(struct mmc_host *host, struct mmc_card *card) +{ + int32_t err; + struct mmc_command cmd = {0}; + + SD_BUG_ON(!host); + SD_BUG_ON(card && (card->host != host)); + + cmd.opcode = MMC_APP_CMD; + + if (card) { + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; + } else { + cmd.arg = 0; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_BCR; + } + + err = mmc_wait_for_cmd(host, &cmd); + if (err) + return err; + + /* Check that card supported application commands */ + if (!(cmd.resp[0] & R1_APP_CMD)) + return -1; + + return 0; +} + +/** + * mmc_wait_for_app_cmd - start an application command and wait for + * completion + * @host: MMC host to start command + * @card: Card to send MMC_APP_CMD to + * @cmd: MMC command to start + * + * Sends a MMC_APP_CMD, checks the card response, sends the command + * in the parameter and waits for it to complete. Return any error + * that occurred while the command was executing. Do not attempt to + * parse the response. + */ +int32_t mmc_wait_for_app_cmd(struct mmc_host *host, struct mmc_card *card, + struct mmc_command *cmd) +{ + struct mmc_request mrq = {NULL}; + + int32_t i, err; + + SD_BUG_ON(!cmd); + + err = -1; + + /* + * We have to resend MMC_APP_CMD for each attempt so + * we cannot use the retries field in mmc_command. + */ + for (i = 0; i <= MMC_CMD_RETRIES; i++) { + err = mmc_app_cmd(host, card); + if (err) { + continue; + } + + memset(&mrq, 0, sizeof(struct mmc_request)); + + memset(cmd->resp, 0, sizeof(cmd->resp)); + + mrq.cmd = cmd; + cmd->data = NULL; + + err = mmc_wait_for_req(host, &mrq); + if (!err) + break; + } + + return err; +} + +int32_t mmc_app_set_bus_width(struct mmc_card *card, uint32_t width) +{ + struct mmc_command cmd = {0}; + + cmd.opcode = SET_BUS_WIDTH; + cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; + + switch (width) { + case MMC_BUS_WIDTH_1: + cmd.arg = SD_BUS_WIDTH_1; + break; + case MMC_BUS_WIDTH_4: + cmd.arg = SD_BUS_WIDTH_4; + break; + default: + cmd.arg = SD_BUS_WIDTH_1; + } + + if (mmc_wait_for_app_cmd(card->host, card, &cmd)) { + return -1; + } + card->bus_width = width; + + return 0; +} + +int32_t mmc_switch_to_high_speed(struct mmc_card *card) +{ + int32_t err; + +#ifdef CONFIG_USE_MMC + if (card->csd.mmc_spec_ver < MMC_CSD_SPEC_VER_4) { + SD_LOGD("MMC card doesn't support to switch to high speed mode !!\n"); + return -1; + } +#endif + + err = mmc_switch(card, MMC_EXT_CSD_CMD_SET_NORMAL, MMC_EXT_CSD_HS_TIMING, 1); + if (err) { + SD_LOGD("MMC card failed to switch to high speed mode !!\n"); + return err; + } + + SD_LOGD("MMC card is switched to high speed!!\n"); + + return 0; +} + +int32_t smc_model_set_blkcnt(struct mmc_host *host, uint32_t blkcnt) +{ + struct mmc_command cmd = {0}; + + cmd.opcode = MMC_SET_BLOCK_COUNT; + cmd.arg = blkcnt & 0xffff; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; + + if (mmc_wait_for_cmd(host, &cmd)) { + return -1; + } + + host->blkcnt = blkcnt; + + return 0; +} + +int32_t __sdmmc_block_rw(struct mmc_card *card, uint32_t blk_num, uint32_t blk_cnt, + uint32_t sg_len, struct scatterlist *sg, int write) +{ + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct mmc_request mrq; + uint32_t status = 0; + + SD_LOGD("%s %s blk_num:%d, blk_cnt:%d, sg_len:%d sg->len:%d\n", __func__, + write?"wirte":"read", blk_num, blk_cnt, sg_len, sg->len); + + if (blk_cnt > 1) { + cmd.opcode = write ? MMC_WRITE_MULTIPLE_BLOCK : MMC_READ_MULTIPLE_BLOCK; + } else { + cmd.opcode = write ? MMC_WRITE_SINGLE_BLOCK : MMC_READ_SINGLE_BLOCK; + } + cmd.arg = blk_num; + if (!mmc_card_blockaddr(card)) + cmd.arg <<= 9; + cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.stop = (blk_cnt == 1) ? 0 : 1; + + data.blksz = 512; + data.flags = write ? MMC_DATA_WRITE : MMC_DATA_READ; + + data.sg = sg; + data.sg_len = sg_len; + + mrq.cmd = &cmd; + mrq.data = &data; + + SD_LOGD("starting CMD%d arg 0x%08x flags %x\n", cmd.opcode, cmd.arg, cmd.flags); + SD_LOGD(" blksz %d blocks %d flags %x\n", data.blksz, data.blocks, data.flags); + if (mmc_wait_for_req(card->host, &mrq)) { + SD_LOGE("%s,%d %s sector:%x BSZ:%d Err!!\n", __func__, __LINE__, + write?"W":"R", blk_num, blk_cnt); + + return -1; + } + if (write) { + do { + if (HAL_SDC_Is_Busy(card->host)) + continue; + mmc_send_status(card, &status); + mmc_mdelay(1); + } while (!(status & 0x100)); + } + return 0; +} + +int32_t sdmmc_stream_write(struct mmc_card *card, uint32_t blk_num, uint32_t blk_size, uint32_t sg_len, struct scatterlist *sg) +{ + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct mmc_request mrq; + uint32_t status = 0; + + cmd.opcode = MMC_WRITE_SINGLE_BLOCK; + cmd.arg = blk_num; + if (!mmc_card_blockaddr(card)) + cmd.arg <<= 9; + cmd.stop = 0; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 |MMC_CMD_ADTC; + cmd.data = &data; + data.flags |= MMC_DATA_WRITE | MMC_DATA_STREAM; + + data.blksz = blk_size; + data.sg_len = sg_len; + data.sg = sg; + mrq.cmd = &cmd; + mrq.data = &data; + if (mmc_wait_for_req(card->host, &mrq)) { + return -1; + } + + /* check busy */ + do { + if (HAL_SDC_Is_Busy(card->host)) + continue; + mmc_send_status(card, &status); + } while (!(status & 0x100)); + return 0; +} +#endif + +void mmc_add_card(struct mmc_card *card) +{ + uint8_t spec_ver = 0; + uint32_t speed_hz = 0; +#if SD_DEBUG + const char *speed_mode = ""; + const char *type; +#endif + + switch (card->type) { +#ifdef CONFIG_USE_MMC + case MMC_TYPE_MMC: + type = "MMC"; + if (card->csd.mmc_spec_ver == 4) + spec_ver = 0x40; + else + spec_ver = 0x31; + speed_hz = mmc_mmc_get_max_clock(card); + break; +#endif +#ifdef CONFIG_USE_SD + case MMC_TYPE_SD: + type = "SD"; + if (mmc_card_blockaddr(card)) { + if (mmc_card_ext_capacity(card)) + type = "SDXC"; + else + type = "SDHC"; + } + if (card->scr.sda_vsn == 0) + spec_ver = 0x10; + else if (card->scr.sda_vsn == 1) + spec_ver = 0x11; + else if (card->scr.sda_vsn == 2 && card->scr.sda_spec3) + spec_ver = 0x30; + else + spec_ver = 0x20; + if (card->scr.sda_vsn == 2 && card->scr.sda_spec3 && card->scr.sda_spec4) + spec_ver = 0x40; + if (card->scr.sda_vsn == 2 && card->scr.sda_spec3 && card->scr.sda_spec5) + spec_ver = 0x50; + speed_hz = mmc_sd_get_max_clock(card); + break; +#endif +#ifdef CONFIG_USE_SDIO + case MMC_TYPE_SDIO: + type = "SDIO"; + spec_ver = 0x10; + speed_hz = mmc_sdio_get_max_clock(card); + break; +#endif +#ifdef CONFIG_USE_SD_COMBO + case MMC_TYPE_SD_COMBO: + type = "SD-combo"; + if (mmc_card_blockaddr(card)) + type = "SDHC-combo"; + break; +#endif + default: + type = "?"; + break; + } + + if (card->sd_bus_speed == HIGH_SPEED_BUS_SPEED) + speed_mode = "HS: 50 MHz"; + else + speed_mode = "DS: 25 MHz"; + + SD_LOGN("\n============= card information ==============\n"); + SD_LOGN("Card Type : %s\n", type); + SD_LOGN("Card Spec Ver : %x.%x\n", spec_ver>>4, spec_ver&0xf); + SD_LOGN("Card RCA : 0x%04x \n", card->rca); + SD_LOGN("Card OCR : 0x%x\n", card->ocr.ocr); + SD_LOGN(" vol_window : 0x%08x\n", card->ocr.vol_window); + SD_LOGN(" to_1v8_acpt : %x\n", card->ocr.to_1v8_acpt); + SD_LOGN(" high_capac : %x\n", card->ocr.high_capacity); + SD_LOGN("Card CSD :\n"); + SD_LOGN(" speed : %d KHz\n", speed_hz/1000); +#if ((defined CONFIG_USE_SD) || (defined CONFIG_USE_MMC)) + SD_LOGN(" cmd class : 0x%x\n", card->csd.cmdclass); + SD_LOGN(" capacity : %dMB\n", card->csd.capacity/1024); + SD_LOGN("Card CUR_STA :\n"); + SD_LOGN(" speed_mode : %s\n", speed_mode); + SD_LOGN(" bus_width : %d\n", card->bus_width); + SD_LOGN(" speed_class : %d\n", card->speed_class); +#else + (void)speed_mode; +#endif + SD_LOGN("=============================================\n"); + (void)spec_ver; + + mmc_card_set_present(card); +} + +#if ((defined CONFIG_USE_SD) || (defined CONFIG_USE_MMC)) +int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen) +{ + struct mmc_command cmd = {0}; + + if (mmc_card_blockaddr(card) || mmc_card_ddr_mode(card)) + return 0; + + cmd.opcode = MMC_SET_BLOCKLEN; + cmd.arg = blocklen; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; + return mmc_wait_for_cmd(card->host, &cmd); +} + +/** + * @brief read SD card. + * @param card: + * @arg card->card handler. + * @param buf: + * @arg buf->for store readed data. + * @param sblk: + * @arg sblk->start block num. + * @param nblk: + * @arg nblk->number of blocks. + * @retval 0 if success or other if failed. + */ +int32_t mmc_block_read(struct mmc_card *card, uint8_t *buf, uint64_t sblk, uint32_t nblk) +{ + int32_t err; + struct scatterlist sg = {0}; + + SD_BUG_ON(!card->host); + + if (nblk > SDXC_MAX_TRANS_LEN/512) { + SD_LOGW("%s only support len < %d\n", __func__, SDXC_MAX_TRANS_LEN/512); + return -1; + } + + mmc_claim_host(card->host); + + err = mmc_set_blocklen(card, 512); + if (err) + goto out; + + sg.len = 512 * nblk; + sg.buffer = buf; + //if ((unsigned int)buf & 0x03) { + // SD_LOGW("%s buf not align 4!!!\n", __func__); + // return -1; + //} + + err = __sdmmc_block_rw(card, sblk, nblk, 1, &sg, 0); + +out: + mmc_release_host(card->host); + return err; +} + +/** + * @brief write SD card. + * @param card: + * @arg card->card handler. + * @param buf: + * @arg buf->data will be write. + * @param sblk: + * @arg sblk->start block num. + * @param nblk: + * @arg nblk->number of blocks. + * @retval 0 if success or other if failed. + */ +int32_t mmc_block_write(struct mmc_card *card, const uint8_t *buf, uint64_t sblk, uint32_t nblk) +{ + int32_t err; + struct scatterlist sg = {0}; + + SD_BUG_ON(!card->host); + + if (nblk > SDXC_MAX_TRANS_LEN/512) { + SD_LOGW("%s only support len < %d\n", __func__, SDXC_MAX_TRANS_LEN/512); + return -1; + } + + mmc_claim_host(card->host); + + err = mmc_set_blocklen(card, 512); + if (err) + goto out; + + sg.len = 512 * nblk; + sg.buffer = (uint8_t *)buf; + //if ((unsigned int)buf & 0x03) { + // SD_LOGW("%s buf not align 4!!!\n", __func__); + // return -1; + //} + + err = __sdmmc_block_rw(card, sblk, nblk, 1, &sg, 1); + +out: + mmc_release_host(card->host); + return err; +} +#endif + +int32_t mmc_send_relative_addr(struct mmc_host *host, uint32_t *rca) +{ + struct mmc_command cmd = {0}; + + cmd.opcode = SD_SEND_RELATIVE_ADDR; + cmd.arg = 0; + cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; + + do { + if (mmc_wait_for_cmd(host, &cmd)) { + return -1; + } + *rca = cmd.resp[0] >> 16; + } while (!*rca); + + return 0; +} + +int32_t mmc_send_if_cond(struct mmc_host *host, uint32_t ocr) +{ + struct mmc_command cmd = {0}; + int32_t err; + static const uint8_t test_pattern = 0xAA; + uint8_t result_pattern; + + /* + * To support SD 2.0 cards, we must always invoke SD_SEND_IF_COND + * before SD_APP_OP_COND. This command will harmlessly fail for + * SD 1.0 cards. + */ + cmd.opcode = SD_SEND_IF_COND; + cmd.arg = ((ocr & 0xFF8000) != 0) << 8 | test_pattern; + cmd.flags = MMC_RSP_SPI_R7 | MMC_RSP_R7 | MMC_CMD_BCR; + + err = mmc_wait_for_cmd(host, &cmd); + if (err) + return err; + + result_pattern = cmd.resp[0] & 0xFF; + + if (result_pattern != test_pattern) + return -1; + + return 0; +} + +int32_t mmc_select_card(struct mmc_card *card, uint32_t select) +{ + struct mmc_command cmd = {0}; + + cmd.opcode = MMC_SELECT_CARD; + if (select) { + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; + } else { + cmd.arg = 0; + cmd.flags = MMC_RSP_NONE | MMC_CMD_AC; + } + + if (mmc_wait_for_cmd(card->host, &cmd)) { + return -1; + } + + return 0; +} + +int32_t mmc_all_send_cid(struct mmc_host *host, uint32_t *cid) +{ + int32_t err; + struct mmc_command cmd = {0}; + + SD_BUG_ON(!host); + SD_BUG_ON(!cid); + + cmd.opcode = MMC_ALL_SEND_CID; + cmd.arg = 0; + cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; + + err = mmc_wait_for_cmd(host, &cmd); + if (err) + return err; + + memcpy(cid, cmd.resp, sizeof(uint32_t) * 4); + + return 0; +} + +#ifdef CONFIG_SD_PM +/* + * Assign a mmc bus handler to a host. Only one bus handler may control a + * host at any given time. + */ +void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops) +{ + unsigned long flags; + + SD_BUG_ON(!host); + SD_BUG_ON(!ops); + + flags = arch_irq_save(); + + SD_BUG_ON(host->bus_ops); + + host->bus_ops = ops; + + arch_irq_restore(flags); +} + +/* + * Remove the current bus handler from a host. + */ +void mmc_detach_bus(struct mmc_host *host) +{ + unsigned long flags; + + SD_BUG_ON(!host); + + SD_WARN_ON(!host->bus_ops); + + flags = arch_irq_save(); + + host->bus_ops = NULL; + + arch_irq_restore(flags); +} + +#endif + +/** + * @brief scan or rescan SD card. + * @param card: + * @arg card->card handler. + * @param sdc_id: + * @arg sdc_id->SDC ID which card on. + * @retval 0 if success or other if failed. + */ +int32_t mmc_rescan(struct mmc_card *card, uint32_t sdc_id) +{ + int32_t err = -1; + struct mmc_host *host = _mci_host; + + if (!host) { + SD_LOGE("%s init sdc host first!!\n", __func__); + return -1; + } + + card->host = host; + + mmc_claim_host(host); + + mmc_power_up(host); + + /* set identification clock 400KHz */ + HAL_SDC_Update_Clk(card->host, 400000); + + /* Initialization should be done at 3.3 V I/O voltage. */ + //mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330, 0); + + /* + * sdio_reset sends CMD52 to reset card. Since we do not know + * if the card is being re-initialized, just send it. CMD52 + * should be ignored by SD/eMMC cards. + */ +#ifdef CONFIG_USE_SDIO + sdio_reset(host); +#endif + mmc_go_idle(host); + + /* cmd8 for SD2.0 */ + if (mmc_send_if_cond(host, host->ocr_avail)) { + SD_LOGN("sd1.0 or mmc\n"); + } + + /* Order's important: probe SDIO, then SD, then MMC */ +#ifdef CONFIG_USE_SDIO + SD_LOGN("***** Try sdio *****\n"); + if (!mmc_attach_sdio(card, host)){ + SD_LOGN("***** sdio init ok *****\n"); + err = 0; + goto out; + } +#endif +#ifdef CONFIG_USE_SD + SD_LOGN("***** Try sd *****\n"); + if (!mmc_attach_sd(card, host)){ + SD_LOGN("***** sd init ok *****\n"); + err = 0; + goto out; + } +#endif +#ifdef CONFIG_USE_MMC + SD_LOGN("***** Try mmc *****\n"); + if (!mmc_attach_mmc(card, host)){ + SD_LOGN("***** mmc init ok *****\n"); + err = 0; + goto out; + } +#endif + + SD_LOGD("Undown Card Detected!!\n"); + + mmc_power_off(host); + +out: + mmc_release_host(host); + return err; +} + +/** + * @brief deinit SD card. + * @param card: + * @arg card->card handler. + * @retval 0 if success or other if failed. + */ +int32_t mmc_card_deinit(struct mmc_card *card) +{ + SD_BUG_ON(!card->host); + +#ifdef CONFIG_USE_SDIO + mmc_deattach_sdio(card, card->host); +#endif +#ifdef CONFIG_USE_SD + mmc_deattach_sd(card, card->host); +#endif + + mmc_power_off(card->host); + memset(card, 0, sizeof(struct mmc_card)); + + return 0; +} diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/core.h b/platform/mcu/xr871/src/driver/chip/sdmmc/core.h new file mode 100644 index 0000000000..73f2c6b900 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/core.h @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_SDMMC_CORE_H_ +#define _DRIVER_CHIP_SDMMC_CORE_H_ + +#include "../hal_base.h" + +#include "driver/chip/sdmmc/card.h" + +#ifdef CONFIG_USE_SDIO +#include "driver/chip/sdmmc/sdio.h" +#endif +#include "driver/chip/sdmmc/sdmmc.h" + +#include "sdhost.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SD_DEBUG 1 + +#if SD_DEBUG +#define SD_DEBUG_DETAIL 0 +#define SD_LOGD(format, args...) HAL_LOG(0, format, ##args) +#define SD_LOGN(format, args...) HAL_LOG(SD_DEBUG_DETAIL, format, ##args) +#define SD_LOGW(format, args...) HAL_LOG(SD_DEBUG, format, ##args) +#define SD_LOGE(format, args...) HAL_LOG(SD_DEBUG, format, ##args) +#define SD_LOGA(format, args...) HAL_LOG(SD_DEBUG, format, ##args) +#if SD_DEBUG_DETAIL +extern void print_hex_dump_bytes(const void *addr, unsigned int len); +#define sd_hex_dump_bytes(a, l) print_hex_dump_bytes(a, l) +#else +#define sd_hex_dump_bytes(a, l) +#endif +#else +#define SD_LOGD(x...) +#define SD_LOGN(x...) +#define SD_LOGW(x...) +#define SD_LOGE(x...) +#define SD_LOGA(x...) +#define sd_hex_dump_bytes(a, l) +#endif +#define SD_BUG_ON(v) do {if(v) {printf("BUG at %s:%d!\n", __func__, __LINE__); while (1);}} while (0) +#define SD_WARN_ON(v) do {if(v) {printf("WARN at %s:%d!\n", __func__, __LINE__);}} while (0) + +#define MMC_CMD_RETRIES 3 + +struct mmc_data { + uint32_t blksz; /* data block size */ + uint32_t blocks; /* number of blocks */ + uint32_t flags; + +#define MMC_DATA_WRITE (1 << 8) +#define MMC_DATA_READ (1 << 9) +#define MMC_DATA_STREAM (1 << 10) + + uint32_t bytes_xfered; + uint32_t sg_len; /* size of scatter list */ + struct scatterlist *sg; /* I/O scatter list */ +}; + +struct mmc_command { + uint32_t opcode; + uint32_t arg; + uint32_t resp[4]; + uint32_t flags; /* expected response type */ + /* data transfer */ + volatile uint32_t stop :1, + boot :1, + vol_switch :1; + +#define MMC_RSP_MASK (0x1f << 0) +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ +#define MMC_CMD_AC (0 << 5) /* addressed comamnd without data transfer */ +#define MMC_CMD_ADTC (1 << 5) /* addressed command with data transfer */ +#define MMC_CMD_BC (2 << 5) /* broadcast command without response */ +#define MMC_CMD_BCR (3 << 5) /* broadcast command with response */ + +#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ +#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ +#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ +#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ + +/* These are the native response types, and correspond to valid bit + * patterns of the above flags. One additional valid pattern + * is all zeros, which means we don't expect a response. + */ +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + +#define mmc_resp_type(cmd) ((cmd)->flags & MMC_RSP_MASK) + +/* + * These are the SPI response types for MMC, SD, and SDIO cards. + * Commands return R1, with maybe more info. Zero is an error type; + * callers must always provide the appropriate MMC_RSP_SPI_Rx flags. + */ +#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1) +#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY) +#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) +#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) +#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) +#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) +#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) + +/* These are the command types. */ +#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK) + + struct mmc_data *data; /* data segment associated with cmd */ +}; + +struct mmc_request { + struct mmc_command *cmd; + struct mmc_data *data; +}; + +#define UNSTUFF_BITS(resp,start,size) \ + ({ \ + const int32_t __size = size; \ + const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int32_t __off = 3 - ((start) / 32); \ + const int32_t __shft = (start) & 31; \ + uint32_t __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off-1] << ((32 - __shft) % 32); \ + __res & __mask; \ + }) + +void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops); +void mmc_detach_bus(struct mmc_host *host); + +extern int32_t mmc_align_data_size(struct mmc_card *card, uint32_t sz); +extern int32_t mmc_sd_switch(struct mmc_card *card, uint8_t mode, uint8_t group, + uint16_t value, uint8_t *resp); +extern void mmc_enumerate_card_info(struct mmc_card *card); +extern int32_t mmc_switch_to_high_speed(struct mmc_card *card); +extern int32_t mmc_sd_switch_hs(struct mmc_card *card); +extern int32_t mmc_app_set_bus_width(struct mmc_card *card, uint32_t width); +extern int32_t mmc_wait_for_cmd(struct mmc_host *host, struct mmc_command *cmd); +extern int32_t mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq); +extern int32_t mmc_attach_sd(struct mmc_card *card, struct mmc_host *host); +extern void mmc_deattach_sd(struct mmc_card *card, struct mmc_host *host); +extern int32_t mmc_select_card(struct mmc_card *card, uint32_t select); +extern int32_t mmc_all_send_cid(struct mmc_host *host, uint32_t *cid); +extern int32_t mmc_send_relative_addr(struct mmc_host *host, uint32_t *rca); +extern void mmc_add_card(struct mmc_card *card); + +/** + * @brief Exclusively claim a host. + * @note Claim a host for a set of operations. + * @param host: + * @host->mmc host to claim. + * @retval None. + */ +static inline void mmc_claim_host(struct mmc_host *host) +{ + HAL_SDC_Claim_Host(host); +} + +/** + * @brief Release a host. + * @note Release a MMC host, allowing others to claim the host for their operations. + * @param host: + * @host->mmc host to release. + * @retval None. + */ +static inline void mmc_release_host(struct mmc_host *host) +{ + HAL_SDC_Release_Host(host); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_SDMMC_CORE_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/hal_sdhost.c b/platform/mcu/xr871/src/driver/chip/sdmmc/hal_sdhost.c new file mode 100644 index 0000000000..fe5e25f6d2 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/hal_sdhost.c @@ -0,0 +1,1462 @@ +/** + * @file hal_sdhost.c + * @author XRADIO IOT WLAN Team + */ + +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../hal_base.h" + +#include "sys/io.h" +#include "driver/chip/hal_gpio.h" + +#include "driver/chip/sdmmc/hal_sdhost.h" +#ifdef CONFIG_USE_SDIO +#include "driver/chip/sdmmc/sdio.h" +#endif +#include "driver/chip/sdmmc/sdmmc.h" +#include "sdhost.h" +#include "core.h" + +#include "pm/pm.h" + +#if ((defined CONFIG_USE_SD) || (defined CONFIG_USE_MMC)) +#define SDC_DMA_TIMEOUT 2000 /* not much data to write on this platform */ +#else +#define SDC_DMA_TIMEOUT 300 +#endif +#define SDC_THREAD_TIMEOUT (SDC_DMA_TIMEOUT + 50) + +#define SDC_SemCreate(l, n) HAL_SemaphoreInit(l, n, OS_SEMAPHORE_MAX_COUNT) +#define SDC_SemDel(l) HAL_SemaphoreDeinit(l) +#define SDC_SemPend(l, t) HAL_SemaphoreWait(l, t) +#define SDC_SemPost(l) HAL_SemaphoreRelease(l) + +#define SDC_MutexCreate(m) OS_MutexCreate(m); +#define SDC_MutexDelete(m) OS_MutexDelete(m); +#define SDC_MutexLock(m, t) OS_MutexLock(m, t) +#define SDC_MutexUnlock(m) OS_MutexUnlock(m); + +#define SDC_InitTimer(t, cb, arg, pms) OS_TimerCreate(t, OS_TIMER_ONCE, cb, arg, pms) +#define SDC_DelTimer(t) OS_TimerDelete(t) +#define SDC_ModTimer(t, ms) do {if (!ms) SDC_BUG_ON(1); \ + OS_TimerChangePeriod(t, ms);} while (0) + +#define SDC_REQUEST_IRQ(n, hdl) HAL_NVIC_SetIRQHandler(n, hdl) +#define SDC_SetPriority(n, l) HAL_NVIC_SetPriority(n, l) +#define SDC_ENABLE_IRQ(n) HAL_NVIC_EnableIRQ(n) +#define SDC_DISABLE_IRQ(n) HAL_NVIC_DisableIRQ(n) +#define SDC_CLEAR_IRQPINGD(n) HAL_NVIC_ClearPendingIRQ(n) +#define SDC_IRQHandler NVIC_IRQHandler + +//#define NUSE_STANDARD_INTERFACE 1 +#ifdef NUSE_STANDARD_INTERFACE +#define SDC_CCM_BASE (0x40040400) +#define SDC_CCM_SDC0_SCLK_CTRL (SDC_CCM_BASE + 0x028) +#else +#define SDC_CCM_BusForceReset() HAL_CCM_BusForcePeriphReset(CCM_BUS_PERIPH_BIT_SDC0) +#define SDC_CCM_BusReleaseRest() HAL_CCM_BusReleasePeriphReset(CCM_BUS_PERIPH_BIT_SDC0) +#define SDC_CCM_BusEnableClock() HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_SDC0) +#define SDC_CCM_BusDisableClock() HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_SDC0) +#define SDC_CCM_EnableMClock() HAL_CCM_SDC_EnableMClock() +#endif + +#define MEMS_VA2PA(x) (x) + +struct mmc_host *_mci_host; + +static int32_t __mci_exit_host(struct mmc_host *host) +{ + uint32_t rval; + +#ifdef CONFIG_SDC_SUPPORT_1V8 + host->voltage = SDC_WOLTAGE_OFF; +#endif + + rval = readl(SDXC_REG_GCTRL) | SDXC_HWReset; + writel(rval, SDXC_REG_GCTRL); + + return 0; +} + +static __inline void __mci_sel_access_mode(uint32_t access_mode) +{ + writel((readl(SDXC_REG_GCTRL) & (~SDXC_ACCESS_BY_AHB)) | access_mode, SDXC_REG_GCTRL); +} + +static int32_t __mci_reset(void) +{ + uint32_t value; + int32_t time = 0x0ffff; + + value = readl(SDXC_REG_GCTRL)|SDXC_HWReset; + writel(value, SDXC_REG_GCTRL); + while (time-- && (readl(SDXC_REG_GCTRL) & SDXC_SoftReset)) + ; + if (time <= 0) { + SDC_LOGE("SDC reset time out\n"); + return -1; + } + SDC_LOGD("%s,%d SDC reset finish \n", __func__, __LINE__); + + return 0; +} + +static int32_t __mci_program_clk(void) +{ + uint32_t value; + int32_t time = 0xf000; + int32_t ret = 0; + + /* disable command done interrupt */ + writel(readl(SDXC_REG_IMASK) & (~SDXC_CmdDone), SDXC_REG_IMASK); + + value = SDXC_Start | SDXC_UPCLKOnly | SDXC_WaitPreOver; + writel(value, SDXC_REG_CMDR); + + do { + value = readl(SDXC_REG_CMDR); + } while (time-- && (value & SDXC_Start)); + + if ((time <= 0) || (value & SDXC_Start)) { + SDC_LOGE("%s,%d SDC change clock time out\n", __func__, __LINE__); + ret = -1; + } + + /* clear command done flag */ + value = readl(SDXC_REG_RINTR); + writel(value, SDXC_REG_RINTR); + + /* enable command done interrupt */ + writel(readl(SDXC_REG_IMASK) | SDXC_CmdDone, SDXC_REG_IMASK); + + return ret; +} + +static void __mci_trans_by_ahb(struct mmc_host *host, struct mmc_data *data) +{ + uint32_t i, j; + uint32_t *buf_temp; /* Cortex-M3/4 can access data with unaligned address */ + volatile uint32_t time; + + for (i = 0; i < data->sg_len; i++) { + buf_temp = data->sg[i].buffer; + if (data->flags & MMC_DATA_READ) { + for (j = 0; j < (data->sg[i].len >> 2); j++) { /* sg[i].len should be multiply of 4 */ + time = 0xfffff00; + while ((readl(SDXC_REG_STAS) & SDXC_FIFOEmpty) && time--) + ; + buf_temp[j] = readl(SDXC_REG_FIFO); + } + } else if (data->flags & MMC_DATA_WRITE) { + for (j = 0; j < (data->sg[i].len >> 2); j++) { /* sg[i].len should be multiply of 4 */ + time = 0xfffff00; + while ((readl(SDXC_REG_STAS) & SDXC_FIFOFull) && time--) + ; + if (time <= 5) + SDC_BUG_ON(1); + writel(buf_temp[j], SDXC_REG_FIFO); + } + } else { + SDC_LOGW("illigle data request\n"); + SDC_BUG_ON(1); + } + } +} + +static smc_idma_des _mci_idma_des[SDXC_MAX_DES_NUM] __attribute__ ((aligned (8))); + +static smc_idma_des *__mci_alloc_idma_des(struct mmc_data *data) +{ + smc_idma_des *pdes = _mci_idma_des; + uint32_t des_idx = 0; + uint32_t buff_frag_num = 0; + uint32_t remain; + uint32_t i, j; + uint32_t config; + + /* init IDMA Descriptor, two mode: 1-fixed skip length, 2-chain mode */ + for (i = 0; i < data->sg_len; i++) { + buff_frag_num = data->sg[i].len >> SDXC_DES_NUM_SHIFT; /* num = len/8192 = len>>13 */ + remain = data->sg[i].len & (SDXC_DES_BUFFER_MAX_LEN - 1); + if (remain) { + buff_frag_num++; + } else { + remain = SDXC_DES_BUFFER_MAX_LEN; + } + + for (j = 0; j < buff_frag_num; j++, des_idx++) { + HAL_Memset((void *)&pdes[des_idx], 0, sizeof(smc_idma_des)); + config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_DIC; + if (buff_frag_num > 1 && j != buff_frag_num - 1) { + pdes[des_idx].data_buf1_sz = SDXC_DES_BUFFER_MAX_LEN; + } else { + pdes[des_idx].data_buf1_sz = remain; + } + + pdes[des_idx].buf_addr_ptr1 = (uint32_t)MEMS_VA2PA(data->sg[i].buffer) + j * SDXC_DES_BUFFER_MAX_LEN; + if (i == 0 && j == 0) { + config |= SDXC_IDMAC_DES0_FD; + } + + if ((i == data->sg_len - 1) && (j == buff_frag_num - 1)) { + config &= ~SDXC_IDMAC_DES0_DIC; + config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER; + pdes[des_idx].buf_addr_ptr2 = 0; + } else { + pdes[des_idx].buf_addr_ptr2 = (uint32_t)MEMS_VA2PA(&pdes[des_idx + 1]); + } + pdes[des_idx].config = config; + SDC_LOGD("sg %d, frag %d, remain %d, des[%d](%p): [0]:%x, [1]:%x, [2]:%x, [3]:%x\n", + i, j, remain, des_idx, &pdes[des_idx], + ((uint32_t *)&pdes[des_idx])[0], ((uint32_t *)&pdes[des_idx])[1], + ((uint32_t *)&pdes[des_idx])[2], ((uint32_t *)&pdes[des_idx])[3]); + } + } + + return pdes; +} + +static smc_idma_des *__mci_prepare_dma(struct mmc_host *host, struct mmc_data *data) +{ + uint32_t temp; + smc_idma_des *pdes = NULL; + + /* creat descriptor list, two mode: 1-fixed skip length, 2-chain mode */ + pdes = __mci_alloc_idma_des(data); + if (NULL == pdes) { + SDC_LOGW("alloc IDMA descriptor failed\n"); + return NULL; + } + + temp = readl(SDXC_REG_GCTRL); + temp |= SDXC_DMAEnb; + writel(temp, SDXC_REG_GCTRL); + temp |= SDXC_DMAReset; + writel(temp, SDXC_REG_GCTRL); + writel(SDXC_IDMACSoftRST, SDXC_REG_DMAC); /* reset IDMAC */ + temp = SDXC_IDMACFixBurst | SDXC_IDMACIDMAOn; + writel(temp, SDXC_REG_DMAC); + /* enable IDMA interrupt, here not use */ + temp = readl(SDXC_REG_IDIE); + temp &= ~(SDXC_IDMACReceiveInt | SDXC_IDMACTransmitInt); + if (data->flags & MMC_DATA_WRITE) { + temp |= SDXC_IDMACTransmitInt; + } else { + temp |= SDXC_IDMACReceiveInt; + } + writel(temp, SDXC_REG_IDIE); + + /* write descriptor address to register */ + writel((uint32_t)MEMS_VA2PA(pdes), SDXC_REG_DLBA); + /* write water level */ + writel((BURST_SIZE << 28) | (SMC_RX_WLEVEL << 16) | SMC_TX_WLEVEL, SDXC_REG_FTRGL); + + return pdes; +} + +static void __mci_free_idma_des(smc_idma_des *pdes) +{ + pdes->config &= ~SDXC_IDMAC_DES0_OWN; +} + +int32_t __mci_wait_access_done(void) +{ + int32_t own_set = 0; + int32_t timeout = 0x0f0000; + + while (!(readl(SDXC_REG_GCTRL) & SDXC_MemAccessDone) && timeout--) + ; + if (!(readl(SDXC_REG_GCTRL) & SDXC_MemAccessDone)) { + SDC_LOGW("wait memory access done timeout !!\n"); + } + + return own_set; +} + +static int32_t __mci_request_done(struct mmc_host *host) +{ + struct mmc_request *mrq = host->mrq; + unsigned long iflags; + uint32_t temp; + int32_t ret = 0; + + iflags = arch_irq_save(); + if (host->wait != SDC_WAIT_FINALIZE) { + arch_irq_restore(iflags); + SDC_LOGW("%s nothing finalize, wt %x\n", __func__, host->wait); + return -1; + } + host->wait = SDC_WAIT_NONE; + host->trans_done = 0; + host->dma_done = 0; + arch_irq_restore(iflags); + + if (host->int_sum & SDXC_IntErrBit) { + SDC_LOGE("SDC err, cmd %d, %s%s%s%s%s%s%s%s%s%s\n", + (host->smc_cmd & SDXC_CMD_OPCODE), + host->int_sum & SDXC_RespErr ? " RE" : "", + host->int_sum & SDXC_RespCRCErr ? " RCE" : "", + host->int_sum & SDXC_DataCRCErr ? " DCE" : "", + host->int_sum & SDXC_RespTimeout ? " RTO" : "", + host->int_sum & SDXC_DataTimeout ? " DTO" : "", + host->int_sum & SDXC_DataStarve ? " DS" : "", + host->int_sum & SDXC_FIFORunErr ? " FRE" : "", + host->int_sum & SDXC_HardWLocked ? " HL" : "", + host->int_sum & SDXC_StartBitErr ? " SBE" : "", + host->int_sum & SDXC_EndBitErr ? " EBE" : ""); + ret = -1; + goto out; + } + + if (mrq->cmd->flags & MMC_RSP_136) { + mrq->cmd->resp[0] = readl(SDXC_REG_RESP3); + mrq->cmd->resp[1] = readl(SDXC_REG_RESP2); + mrq->cmd->resp[2] = readl(SDXC_REG_RESP1); + mrq->cmd->resp[3] = readl(SDXC_REG_RESP0); + } else + mrq->cmd->resp[0] = readl(SDXC_REG_RESP0); + +out: + if (mrq->data) { + if (host->dma_hdle) { + __mci_wait_access_done(); + writel(0x337, SDXC_REG_IDST); /* clear interrupt flags */ + writel(0, SDXC_REG_IDIE); /* disable idma interrupt */ + writel(0, SDXC_REG_DMAC); /* idma off */ + temp = readl(SDXC_REG_GCTRL); + writel(temp | SDXC_DMAReset, SDXC_REG_GCTRL); + temp &= ~SDXC_DMAEnb; + writel(temp, SDXC_REG_GCTRL); /* disable IDMA */ + temp |= SDXC_FIFOReset; + writel(temp, SDXC_REG_GCTRL); + __mci_free_idma_des((void *)host->dma_hdle); + host->dma_hdle = NULL; + } + writel(readl(SDXC_REG_GCTRL) | SDXC_FIFOReset, SDXC_REG_GCTRL); + } + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_DETECT_BY_D3){ + writel(SDXC_CardInsert|SDXC_CardRemove, SDXC_REG_IMASK); + } else +#endif + { + writel(0, SDXC_REG_IMASK); + } + if (host->int_sum & (SDXC_RespErr | SDXC_HardWLocked | SDXC_RespTimeout)) { + SDC_LOGE("sdc %d abnormal status: %s\n", __LINE__, + host->int_sum & SDXC_HardWLocked ? "HardWLocked" : "RespErr"); + } + + writel(0xffff, SDXC_REG_RINTR); + + SDC_LOGD("SDC done, resp %x %x %x %x\n", mrq->cmd->resp[0], + mrq->cmd->resp[1], mrq->cmd->resp[2], mrq->cmd->resp[3]); + + if (mrq->data && (host->int_sum & SDXC_IntErrBit)) { + SDC_LOGW("found data error, need to send stop command !!\n"); + __mci_reset(); + __mci_program_clk(); + } + + return ret; +} + +#ifdef CONFIG_SDIO_IRQ_SUPPORT +static void __mci_enable_sdio_irq(struct mmc_host *host, int enable) +{ + uint32_t imask; + + imask = readl(SDXC_REG_IMASK); + if (enable) + imask |= SDXC_SDIOInt; + else + imask &= ~SDXC_SDIOInt; + writel(imask, SDXC_REG_IMASK); +} + +static inline void __mci_signal_sdio_irq(struct mmc_host *host) +{ + SDC_BUG_ON(!host->card || !host->card->irq_handler); + + __mmc_enable_sdio_irq(host, 0); + host->card->irq_handler(host->card); + __mmc_enable_sdio_irq(host, 1); +} +#endif + +static void __mci_clk_prepare_enable(void) +{ + SDC_CCM_BusEnableClock(); /* clock enable */ + SDC_CCM_BusReleaseRest(); /* reset and gating */ + SDC_CCM_EnableMClock(); +} + +static void __mci_clk_disable_unprepare(void) +{ + SDC_CCM_BusDisableClock(); +} + +static void __mci_hold_io(struct mmc_host* host) +{ +#ifdef __CONFIG_ARCH_APP_CORE + /* disable gpio to avoid power leakage */ + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_SDC, host->sdc_id), SDCGPIO_BAS); +#endif +} + +static void __mci_restore_io(struct mmc_host* host) +{ +#ifdef __CONFIG_ARCH_APP_CORE + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_SDC, host->sdc_id), SDCGPIO_BAS); +#endif +} + +static void __mci_irq_handler(void) +{ + struct mmc_host *host = _mci_host; + uint32_t sdio_int = 0; + uint32_t raw_int; + uint32_t msk_int; + uint32_t idma_inte; + uint32_t idma_int; + + if (!host->present) { + SDC_CCM_BusEnableClock(); + } + + idma_int = readl(SDXC_REG_IDST); + idma_inte = readl(SDXC_REG_IDIE); + raw_int = readl(SDXC_REG_RINTR); + msk_int = readl(SDXC_REG_MISTA); + + if (!msk_int && !idma_int) { + SDC_LOGE("sdc nop irq: ri:%08x mi:%08x ie:%08x idi:%08x\n", + raw_int, msk_int, idma_inte, idma_int); + return ; + } + + host->int_sum = raw_int; + SDC_LOGD("smc %d ri:%02x(%02x), mi:%x, ie:%x, idi:%x\n", __LINE__, + (int)raw_int, (int)host->int_sum, + (int)msk_int, (int)idma_inte, (int)idma_int); + + (void)idma_inte; + +#ifdef CONFIG_SDIO_IRQ_SUPPORT + if (msk_int & SDXC_SDIOInt) { + sdio_int = 1; + SDC_LOGE("%s,%d unsupport sdio int now!\n", __func__, __LINE__); + writel(SDXC_SDIOInt, SDXC_REG_RINTR); + goto sdio_out; + } +#endif + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_DETECT_BY_D3) { + if (msk_int & SDXC_CardInsert) { + SDC_LOGN("Card Insert !!\n"); + host->present = 1; + SDC_ModTimer(&host->cd_timer, 10); + } else if (msk_int & SDXC_CardRemove) { + SDC_LOGN("Card Remove !!\n"); + host->present = 0; + SDC_ModTimer(&host->cd_timer, 10); + } + } +#endif + + if (host->wait == SDC_WAIT_NONE && !sdio_int) { + SDC_LOGE("%s nothing to complete, ri:%08x, mi:%08x\n", + __func__, raw_int, msk_int); + goto irq_out; + } + + if ((raw_int & SDXC_IntErrBit) || (idma_int & SDXC_IDMA_ERR)) { + host->int_err = raw_int & SDXC_IntErrBit; + host->wait = SDC_WAIT_FINALIZE; + SDC_LOGE("%s,%d raw_int:%x err!\n", __func__, __LINE__, raw_int); + goto irq_out; + } + if (raw_int & SDXC_HardWLocked) { + SDC_LOGE("command hardware lock\n"); + } + + if (idma_int & (SDXC_IDMACTransmitInt|SDXC_IDMACReceiveInt)) { + host->dma_done = 1; + writel(idma_int, SDXC_REG_IDST); + } + if (msk_int & (SDXC_AutoCMDDone|SDXC_DataOver|SDXC_CmdDone|SDXC_VolChgDone)) + host->trans_done = 1; + if ((host->trans_done && \ + (host->wait == SDC_WAIT_AUTOCMD_DONE || host->wait == SDC_WAIT_DATA_OVER + || host->wait == SDC_WAIT_CMD_DONE || host->wait == SDC_WAIT_SWITCH1V8)) + || (host->trans_done && host->dma_done && (host->wait & SDC_WAIT_IDMA_DONE))) { + host->wait = SDC_WAIT_FINALIZE; + } + +irq_out: + writel(msk_int & (~SDXC_SDIOInt), SDXC_REG_RINTR); + + if (host->wait == SDC_WAIT_FINALIZE) { +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_DETECT_BY_D3){ + writel(SDXC_CardInsert|SDXC_CardRemove, SDXC_REG_IMASK); + } else +#endif + { + writel(0, SDXC_REG_IMASK); + } + SDC_SemPost(&host->lock); + SDC_LOGD("SDC irq post, trans:%d, dma:%d\n", (int)host->trans_done, (int)host->dma_done); + } + +#ifdef CONFIG_SDIO_IRQ_SUPPORT +sdio_out: + if (sdio_int) + __mci_signal_sdio_irq(host); +#endif +} + +/* clock config: + * SYS_CRYSTAL: 26M + * 400K, SCLK-26M, 26M/(2^3)/(7+1)/2 = 361K + * SYS_CRYSTAL: 24M + * 400K, SCLK-24M, 24M/(2^2)/(7+1)/2 = 375K + * + * 25M, SCLK-192M, 192M/(2^0)/(3+1)/2 = 24M + * 50M, SCLK-192M, 192M/(2^0)/(1+1)/2 = 48M + * 64M, SCLK-192M, 192M/(2^0)/(1+1)/2 = 48M + */ +#define DEFINE_SYS_CRYSTAL HAL_GetHFClock() +#define DEFINE_SYS_DEVCLK HAL_GetDevClock() + +static int32_t __mci_update_clock(uint32_t cclk) +{ + uint32_t sclk; + uint32_t div; + uint32_t rval; + uint32_t src = 0; + uint32_t m, n; + + if (cclk > DEFINE_SYS_CRYSTAL/2) { +#ifdef NUSE_STANDARD_INTERFACE + src = 1; +#else + src = CCM_AHB_PERIPH_CLK_SRC_DEVCLK; +#endif + sclk = DEFINE_SYS_DEVCLK; + } else { +#ifdef NUSE_STANDARD_INTERFACE + src = 0; +#else + src = CCM_AHB_PERIPH_CLK_SRC_HFCLK; +#endif + sclk = DEFINE_SYS_CRYSTAL; + } + cclk = cclk * 2; /* 2x MODE clock configure */ + div = (2 * sclk + cclk) / (2 * cclk); + div = div == 0 ? 1 : div; + if (div > 128) { + n = 3; + m = 16; + SDC_LOGE("source clk is too high!\n"); + } else if (div > 64) { + n = 3; + m = div >> 3; + } else if (div > 32) { + n = 2; + m = div >> 2; + } else if (div > 16) { + n = 1; + m = div >> 1; + } else { + n = 0; + m = div; + } + m = m - 1; +#ifdef NUSE_STANDARD_INTERFACE + rval = (1U << 31) | (src << 24) | (n << 16) | (m); + if (src) { + rval |= (2U << 20) | (1 << 8); + SDC_LOGN("%s,%d check spec. bit20, 8!!\n", __func__, __LINE__); + } + writel(rval, SDC_CCM_SDC0_SCLK_CTRL); + SDC_LOGN("SDC clock=%d kHz,src:%x, n:%d, m:%d\n", + (src?DEFINE_SYS_DEVCLK:DEFINE_SYS_CRYSTAL)/(1<clk = clk; + + return 0; +} + +static int32_t __mci_update_clk(struct mmc_host *host) +{ + uint32_t rval; + int32_t timeout = 0xf000; + int32_t ret = 0; + + rval = SDXC_Start|SDXC_UPCLKOnly|SDXC_WaitPreOver; +#ifdef CONFIG_SDC_SUPPORT_1V8 + if (host->voltage_switching) + rval |= SDXC_VolSwitch; +#endif + writel(rval, SDXC_REG_CMDR); + + do { + rval = readl(SDXC_REG_CMDR); + } while (timeout-- && (rval & SDXC_Start)); + + if (rval & SDXC_Start) { + SDC_LOGE("sdc update clock timeout, fatal error!!!\n"); + ret = -1; + } + + if (!ret) + SDC_LOGD("sdc update clock ok\n"); + + return ret; +} + +int32_t HAL_SDC_Clk_PWR_Opt(struct mmc_host *host, uint32_t oclk_en, uint32_t pwr_save) +{ + uint32_t rval; + + if (!host->power_on) + return 0; + + rval = readl(SDXC_REG_CLKCR); + + rval &= ~(SDXC_CardClkOn | SDXC_LowPowerOn); + if (oclk_en) + rval |= SDXC_CardClkOn; + if (pwr_save) + rval |= SDXC_LowPowerOn; + writel(rval, SDXC_REG_CLKCR); + + __mci_update_clk(host); + + return 0; +} + +static void __mci_debounce_onoff(uint32_t onoff) +{ + uint32_t rval = readl(SDXC_REG_GCTRL); + + rval &= ~SDXC_DebounceEnb; + if (onoff) + rval |= SDXC_DebounceEnb; + writel(rval, SDXC_REG_GCTRL); +} + +uint32_t HAL_SDC_Is_Busy(struct mmc_host *host) +{ + return readl(SDXC_REG_STAS) & SDXC_CardBusy; +} + +void HAL_SDC_Set_BusWidth(struct mmc_host *host, uint32_t width) +{ + SDC_BUG_ON(!host); + + switch (width) { + case MMC_BUS_WIDTH_1: + writel(SDXC_WIDTH1, SDXC_REG_WIDTH); + break; + case MMC_BUS_WIDTH_4: + writel(SDXC_WIDTH4, SDXC_REG_WIDTH); + break; +#ifdef CONFIG_USE_MMC + case MMC_BUS_WIDTH_8: + writel(SDXC_WIDTH8, SDXC_REG_WIDTH); + break; +#endif + default: + SDC_BUG_ON(1); + } + + host->buswidth = width; +} + +static void __mci_send_cmd(struct mmc_host *host, struct mmc_command *cmd) +{ + uint32_t imask = SDXC_IntErrBit; + uint32_t cmd_val = SDXC_Start | (cmd->opcode & 0x3f); + unsigned long iflags; + uint32_t wait = SDC_WAIT_CMD_DONE; + struct mmc_data *data = cmd->data; + + if (cmd->opcode == MMC_GO_IDLE_STATE) { + cmd_val |= SDXC_SendInitSeq; + imask |= SDXC_CmdDone; + } + +#ifdef CONFIG_SDC_SUPPORT_1V8 + if (cmd->opcode == SD_SWITCH_VOLTAGE) { + cmd_val |= SDXC_VolSwitch; + imask |= SDXC_VolChgDone; + host->voltage_switching = 1; + wait = SDC_WAIT_SWITCH1V8; + /* switch controller to high power mode */ + HAL_SDC_Clk_PWR_Opt(host, 1, 0); + } +#endif + + if (cmd->flags & MMC_RSP_PRESENT) { /* with response */ + cmd_val |= SDXC_RspExp; + if (cmd->flags & MMC_RSP_136) /* long response */ + cmd_val |= SDXC_LongRsp; + if (cmd->flags & MMC_RSP_CRC) + cmd_val |= SDXC_CheckRspCRC; + + if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { /* with data */ + SDC_BUG_ON(!data); + cmd_val |= SDXC_DataExp | SDXC_WaitPreOver; + wait = SDC_WAIT_DATA_OVER; + if (data->flags & MMC_DATA_STREAM) { /* sequence mode */ + imask |= SDXC_AutoCMDDone; + cmd_val |= SDXC_Seqmod | SDXC_SendAutoStop; + wait = SDC_WAIT_AUTOCMD_DONE; + } + if (cmd->stop) { + imask |= SDXC_AutoCMDDone; + cmd_val |= SDXC_SendAutoStop; + wait = SDC_WAIT_AUTOCMD_DONE; + } else + imask |= SDXC_DataOver; + + if (data->flags & MMC_DATA_WRITE) { + cmd_val |= SDXC_Write; + } else if (host->dma_hdle) { + wait |= SDC_WAIT_IDMA_DONE; + } + SDC_LOGD("blk_size:%d, sg len:%d\n", data->blksz, data->sg->len); + } else + imask |= SDXC_CmdDone; + } else + imask |= SDXC_CmdDone; + + SDC_LOGD("smc cmd:%d(%x), arg:%x ie:%x wt:%x len:%d\n", + (cmd_val & SDXC_CMD_OPCODE), cmd_val, cmd->arg, imask, wait, + cmd->data ? cmd->data->blksz * cmd->data->blocks : 0); + + iflags = arch_irq_save(); + host->smc_cmd = cmd_val; + host->wait = wait; + + writel(imask, SDXC_REG_IMASK); + + if (cmd_val & SDXC_SendAutoStop) + writel(0, SDXC_REG_A12A); + else + writel(0xffff, SDXC_REG_A12A); + + writel(cmd->arg, SDXC_REG_CARG); + writel(cmd_val, SDXC_REG_CMDR); + + arch_irq_restore(iflags); + + if (data && NULL == host->dma_hdle) { + __mci_trans_by_ahb(host, data); + } +} + +int32_t HAL_SDC_Request(struct mmc_host *host, struct mmc_request *mrq) +{ + int32_t ret = 0; + struct mmc_command *cmd = mrq->cmd; + struct mmc_data *data = mrq->data; +#ifdef CONFIG_SDC_DMA_USED + uint32_t sdc_use_dma = 1; +#else + uint32_t sdc_use_dma = 0; +#endif + + if (!host->present) { + SDC_LOGW("sdc no medium present\n"); + return -1; + } + +#ifdef CONFIG_SD_PM + if (host->suspend) { + SDC_LOGE("sdc has suspended!\n"); + return -1; + } +#endif + + OS_MutexLock(&host->thread_lock, SDC_THREAD_TIMEOUT); + + /* disable debounce */ + __mci_debounce_onoff(0); + + host->mrq = mrq; + + if (data) { + uint32_t i; + uint32_t byte_cnt = 0; + struct scatterlist *sg = data->sg; + uint32_t sg_len = data->sg_len; + + for (i = 0; i < sg_len; i++) { + byte_cnt += sg[i].len; +#ifdef CONFIG_SDC_DMA_USED + if (((uint32_t)sg[i].buffer & 0x03)) { + sdc_use_dma = 0; + break; + } +#endif + } +#ifdef CONFIG_SDC_DMA_USED + if (byte_cnt <= SDC_MAX_CPU_TRANS_LEN) { + sdc_use_dma = 0; + } +#endif + + writel(data->blksz, SDXC_REG_BLKSZ); + writel(byte_cnt, SDXC_REG_BCNTR); + + if (sdc_use_dma && byte_cnt > SDC_MAX_CPU_TRANS_LEN) { /* transfer by idma */ + __mci_sel_access_mode(SDXC_ACCESS_BY_DMA); + host->dma_hdle = __mci_prepare_dma(host, data); + if (NULL == host->dma_hdle) { + SDC_LOGW("SDC prepare DMA failed\n"); + __mci_sel_access_mode(SDXC_ACCESS_BY_AHB); + } + } else { + /* switch data bus to ahb */ + __mci_sel_access_mode(SDXC_ACCESS_BY_AHB); + } + } + + __mci_send_cmd(host, cmd); + + ret = SDC_SemPend(&host->lock, SDC_DMA_TIMEOUT); + if (ret != HAL_OK){ + SDC_LOGE("sdc cmd:%d, wait command done timeout !!\n", + (host->smc_cmd & SDXC_CMD_OPCODE)); + goto out; + } + + ret = __mci_request_done(host); + if (ret) { + SDC_LOGE("int err %x\n", host->int_err); + goto out; + } + +out: + /* enable debounce */ + __mci_debounce_onoff(1); + + SDC_MutexUnlock(&host->thread_lock); + + return ret; +} + +#ifdef CONFIG_SDC_EXCLUSIVE_HOST +/** + * HAL_SDC_Claim_Host - exclusively claim a host + * @host: mmc host to claim + * + * Claim a host for a set of operations. + */ +int32_t HAL_SDC_Claim_Host(struct mmc_host *host) +{ + return (SDC_SemPend(&host->exclusive_lock, OS_WAIT_FOREVER) == HAL_OK ? 0 : -1); +} + +/** + * HAL_SDC_Release_Host - release a host + * @host: mmc host to release + * + * Release a MMC host, allowing others to claim the host + * for their operations. + */ +void HAL_SDC_Release_Host(struct mmc_host *host) +{ + SDC_SemPost(&host->exclusive_lock); +} +#endif + +#ifdef CONFIG_SDC_READONLY_USED +int32_t HAL_SDC_Get_ReadOnly(struct mmc_host *host) +{ + uint32_t wp_val; + GPIO_PinMuxParam *ro_gpio = &host->ro_gpio; + + wp_val = = (GPIO_PIN_HIGH == HAL_GPIO_ReadPin(ro_gpio->port, ro_gpio->pin)) ? 1 : 0; + SDC_LOGN("sdc fetch card wp pin status: %d \n", wp_val); + + if (!wp_val) { + host->read_only = 0; + return 0; + } else { + SDC_LOGN("Card is write-protected\n"); + host->read_only = 1; + return 1; + } + + return 0; +} +#endif + +#ifdef CONFIG_DETECT_CARD +static void __mci_cd_timer(void *arg) +{ + struct mmc_host *host = (struct mmc_host *)arg; + uint32_t gpio_val = 0; + uint32_t present; + + gpio_val = (GPIO_PIN_HIGH == HAL_GPIO_ReadPin(host->cd_port, host->cd_pin)) ? 1 : 0; + + if (gpio_val) { + present = 0; + } else if (!gpio_val) + present = 1; + + SDC_LOGD("cd %d, host present %d, cur present %d\n", gpio_val, host->present, present); + + if (host->present ^ present) { + SDC_LOGD("sdc detect change, present %d\n", present); + host->present = present; + host->param.cd_cb(present); + } + + return ; +} + +static void __mci_dat3_det(void *arg) +{ + struct mmc_host *host = (struct mmc_host *)arg; + + SDC_LOGD("***dat3 det***\n"); + + host->param.cd_cb(host->present); +} + +static void __mci_cd_irq(void *arg) +{ + struct mmc_host *host = (struct mmc_host *)arg; + + SDC_LOGD("***in cd***\n"); + + SDC_ModTimer(&host->cd_timer, 10); + + return ; +} +#endif + +int32_t HAL_SDC_PowerOn(struct mmc_host *host) +{ + uint32_t rval; + + SDC_BUG_ON(!host); + + SDC_LOGD("MMC Driver init host\n"); + + __mci_restore_io(host); + __mci_clk_prepare_enable(); + + /* delay 1ms ? */ + __mci_update_clock(400000); + host->clk = 400000; + + /* reset controller */ + rval = readl(SDXC_REG_GCTRL)|SDXC_HWReset|SDXC_INTEnb|SDXC_AccessDoneDirect; + writel(rval, SDXC_REG_GCTRL); + + writel(0xffffffff, SDXC_REG_RINTR); + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_DETECT_BY_D3){ + writel(SDXC_CardInsert|SDXC_CardRemove, SDXC_REG_IMASK); + } else +#endif + { + writel(0, SDXC_REG_IMASK); + } + +#define SDMC_DATA_TIMEOUT 0x0ffffffU +#define SDMC_RESP_TIMEOUT 0xffU + /* Set Data & Response Timeout Value */ + writel((SDMC_DATA_TIMEOUT<<8)|SDMC_RESP_TIMEOUT, SDXC_REG_TMOUT); +#undef SDMC_RESP_TIMEOUT +#undef SDMC_DATA_TIMEOUT + + HAL_SDC_Set_BusWidth(host, MMC_BUS_WIDTH_1); + +#ifdef SDC_DEBUG + writel(0xdeb, SDXC_REG_DBGC); + writel(0xceaa0000, SDXC_REG_FUNS); +#endif + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_DETECT_BY_D3){ + rval |= SDXC_DebounceEnb; + } + writel(rval, SDXC_REG_GCTRL); +#endif + + SDC_ENABLE_IRQ(SDC_IRQn); + + host->power_on = 1; + + return 0; +} + +int32_t HAL_SDC_PowerOff(struct mmc_host *host) +{ + SDC_BUG_ON(!host); + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode != CARD_DETECT_BY_D3) +#endif + { + uint32_t rval; + + SDC_DISABLE_IRQ(SDC_IRQn); + + rval = readl(SDXC_REG_GCTRL) | SDXC_HWReset; + writel(rval, SDXC_REG_GCTRL); + rval = readl(SDXC_REG_MISTA); + writel(rval & (~SDXC_SDIOInt), SDXC_REG_RINTR); + + SDC_CLEAR_IRQPINGD(SDC_IRQn); + + __mci_clk_disable_unprepare(); + + __mci_hold_io(host); + host->power_on = 0; + } + + return 0; +} + +static struct mmc_host _mci_host_rel; + +#ifdef CONFIG_SD_PM + +struct __mci_ctrl_regs { + uint32_t gctrl; + uint32_t clkc; + uint32_t timeout; + uint32_t buswid; + uint32_t waterlvl; + uint32_t funcsel; + uint32_t idmacc; +}; + +static struct __mci_ctrl_regs _mci_pm_bak_regs; +#ifdef __CONFIG_ARCH_APP_CORE +static SDC_InitTypeDef g_sdc_param; +#endif + +static void __mci_regs_save(struct mmc_host *host) +{ + struct __mci_ctrl_regs* bak_regs = &_mci_pm_bak_regs; + + bak_regs->gctrl = readl(SDXC_REG_GCTRL); + bak_regs->clkc = readl(SDXC_REG_CLKCR); + bak_regs->timeout = readl(SDXC_REG_TMOUT); + bak_regs->buswid = readl(SDXC_REG_WIDTH); + bak_regs->waterlvl = readl(SDXC_REG_FTRGL); + bak_regs->funcsel = readl(SDXC_REG_FUNS); + bak_regs->idmacc = readl(SDXC_REG_DMAC); +} + +static void __mci_regs_restore(struct mmc_host *host) +{ + struct __mci_ctrl_regs* bak_regs = &_mci_pm_bak_regs; + + writel(bak_regs->gctrl, SDXC_REG_GCTRL); + writel(bak_regs->clkc, SDXC_REG_CLKCR); + writel(bak_regs->timeout, SDXC_REG_TMOUT); + writel(bak_regs->buswid, SDXC_REG_WIDTH); + writel(bak_regs->waterlvl, SDXC_REG_FTRGL); + writel(bak_regs->funcsel, SDXC_REG_FUNS); +#ifdef SDC_DEBUG + writel(0xdeb, SDXC_REG_DBGC); + writel(0xceaa0000, SDXC_REG_FUNS); +#endif + writel(bak_regs->idmacc, SDXC_REG_DMAC); +} + +static int __mci_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + int ret = 0; + struct mmc_host *host = _mci_host; + +#ifdef CONFIG_DETECT_CARD + if (cancel_delayed_work(&host->detect)) + wake_unlock(&host->detect_wake_lock); +#endif + if (host->bus_ops && host->bus_ops->suspend) + ret = host->bus_ops->suspend(host); + + host->suspend = 1; + __mci_regs_save(host); + + /* gate clock for lower power */ + HAL_CCM_SDC_DisableMClock(); + SDC_CCM_BusForceReset(); + __mci_clk_disable_unprepare(); + +#ifdef CONFIG_DETECT_CARD + if (host->cd_mode == CARD_DETECT_BY_D3) { + __mci_exit_host(host); + + HAL_CCM_SDC_DisableMClock(); + SDC_CCM_BusForceReset(); + __mci_hold_io(host); + + SDC_LOGD("sdc card_power_off ok\n"); + + //__mci_set_vddio(host, SDC_WOLTAGE_OFF); + //usleep_range(1000, 1500); + host->power_on = 0; + + } +#endif + + SDC_LOGD("%s okay\n", __func__); + + return ret; +} + +static int __mci_resume(struct soc_device *dev, enum suspend_state_t state) +{ + int ret = 0; + struct mmc_host *host = _mci_host; + uint32_t clk = host->clk; + + __mci_restore_io(host); + + SDC_CCM_BusForceReset(); + __mci_clk_disable_unprepare(); + mmc_udelay(35); + + /* enable clock for resotre */ + __mci_clk_prepare_enable(); + mmc_udelay(50); + __mci_update_clock(clk); + mmc_udelay(100); + + __mci_regs_restore(host); +#ifdef CONFIG_DETECT_CARD +#else + writel(SDXC_CardInsert, SDXC_REG_RINTR); +#endif + __mci_update_clk(host); + + /* register IRQ */ + SDC_REQUEST_IRQ(SDC_IRQn, (SDC_IRQHandler)&__mci_irq_handler); + SDC_SetPriority(SDC_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + SDC_ENABLE_IRQ(SDC_IRQn); + mmc_udelay(100); + +#ifdef CONFIG_DETECT_CARD + if (host->cd_mode == CARD_DETECT_BY_GPIO_IRQ) + __mci_cd_timer(host); + + if (host->cd_mode == CARD_DETECT_BY_D3) { + uint32_t rval = 0; + + //__mci_set_vddio(host, host->regulator_voltage); + //usleep_range(1000, 1500); + host->power_on = 1; + + __mci_restore_io(host); + __mci_clk_prepare_enable(); + + mmc_mdelay(1); + rval = readl(SDXC_REG_RINTR); + SDC_LOGD(">> REG_RINTR=0x%x\n", rval); + } +#endif + + host->suspend = 0; + + if (host->bus_ops && host->bus_ops->resume) + ret = host->bus_ops->resume(host); + + SDC_LOGD("sdc resume okay\n"); + + return ret; +} + +static struct soc_device_driver sdc_drv = { + .name = "sdc", + .suspend = __mci_suspend, + .resume = __mci_resume, +}; + +static struct soc_device sdc_dev = { + .name = "sdc", + .driver = &sdc_drv, + .platform_data = (void *)&_mci_host_rel, +}; + +#define SDC_DEV (&sdc_dev) + +#else /* CONFIG_SD_PM */ + +#define SDC_DEV NULL + +#endif /* CONFIG_SD_PM */ + +/** + * @brief Initializes the SDC peripheral. + * @param sdc_id: + * @arg sdc_id->SDC ID. + * @param param: + * @arg param->[in] The configuration information. + * @retval SDC handler. + */ +#ifdef __CONFIG_ARCH_APP_CORE +struct mmc_host *HAL_SDC_Init(uint32_t sdc_id, SDC_InitTypeDef *param) +#else +/** + * @brief Initializes the SDC peripheral. + * @param sdc_id: + * @arg sdc_id->SDC ID. + * @retval SDC handler. + */ +struct mmc_host *HAL_SDC_Init(uint32_t sdc_id) +#endif +{ + struct mmc_host *host; +#ifdef __CONFIG_ARCH_APP_CORE + const HAL_SDCGPIOCfg *sd_gpio_cfg; +#endif + + host = &_mci_host_rel; + _mci_host = host; + + if (host->State != SDC_STATE_RESET) { + SDC_LOGW("%s reinit sdc!\n", __func__); + return NULL; + } + + host->sdc_id = sdc_id; +#ifdef __CONFIG_ARCH_APP_CORE + memcpy(&host->param, param, sizeof(SDC_InitTypeDef)); +#endif + + host->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY | + MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50; +#ifdef CONFIG_SD_PM + host->pm_caps = MMC_PM_KEEP_POWER|MMC_PM_WAKE_SDIO_IRQ; +#endif + +#ifdef __CONFIG_ARCH_APP_CORE + HAL_BoardIoctl(HAL_BIR_GET_CFG, HAL_MKDEV(HAL_DEV_MAJOR_SDC, host->sdc_id), + (uint32_t)&sd_gpio_cfg); + if (sd_gpio_cfg->data_bits == 8) + host->caps |= MMC_CAP_8_BIT_DATA; + else if (sd_gpio_cfg->data_bits == 4) + host->caps |= MMC_CAP_4_BIT_DATA; +#else + host->caps |= MMC_CAP_4_BIT_DATA; +#endif + + __mci_restore_io(host); + + /* register IRQ */ + SDC_REQUEST_IRQ(SDC_IRQn, (SDC_IRQHandler)&__mci_irq_handler); + SDC_SetPriority(SDC_IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_ALWAYS_PRESENT) { + host->present = 1; + } else if (host->param.cd_mode == CARD_DETECT_BY_GPIO_IRQ) { + SDC_BUG_ON(!param->cd_cb); + SDC_BUG_ON(!sd_gpio_cfg->has_detect_gpio); + GPIO_IrqParam Irq_param; + + host->cd_port = sd_gpio_cfg->detect_port; + host->cd_pin = sd_gpio_cfg->detect_pin; + HAL_BoardIoctl(HAL_BIR_PINMUX_INIT, HAL_MKDEV(HAL_DEV_MAJOR_SDC, host->sdc_id), SDCGPIO_DET); + + SDC_InitTimer(&host->cd_timer, &__mci_cd_timer, host, 300); + + //HAL_GPIO_SetDebounce(&Irq_param, (2U << 4) | 1); /* set debounce clock */ + Irq_param.event = GPIO_IRQ_EVT_BOTH_EDGE; + Irq_param.callback = &__mci_cd_irq; + Irq_param.arg = host; + HAL_GPIO_EnableIRQ(host->cd_port, host->cd_pin, &Irq_param); + host->present = !((GPIO_PIN_HIGH == + HAL_GPIO_ReadPin(host->cd_port, host->cd_pin)) ? 1 : 0); + } else if (host->param.cd_mode == CARD_DETECT_BY_D3) { + uint32_t rval; + SDC_BUG_ON(!param->cd_cb); + + __mci_clk_prepare_enable(); + mmc_mdelay(1); + host->present = 1; + rval = readl(SDXC_REG_RINTR); + SDC_LOGD("sdc +> REG_RINTR=0x%x\n", rval); + if ((rval & SDXC_CardRemove)) { + SDC_LOGD("sdc data[3] detect Card Remove\n"); + host->present = 0; + } + SDC_InitTimer(&host->cd_timer, &__mci_dat3_det, host, 300); + } +#else + host->present = 1; +#endif + + host->max_blk_count = 8192; + host->max_blk_size = 4096; + host->max_req_size = host->max_blk_size * host->max_blk_count; + host->max_seg_size = host->max_req_size; + host->max_segs = 128; + host->ocr_avail = MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 + | MMC_VDD_32_33 | MMC_VDD_33_34; + + SDC_LOGD("SDC Host Capability:0x%x Ocr avail:0x%x\n", host->caps, host->ocr_avail); + + /* init semaphore */ + SDC_SemCreate(&host->lock, 0); + SDC_MutexCreate(&host->thread_lock); +#ifdef CONFIG_SDC_EXCLUSIVE_HOST + SDC_SemCreate(&host->exclusive_lock, 1); +#endif + +#ifdef CONFIG_DETECT_CARD + if (host->param.cd_mode == CARD_DETECT_BY_D3 && host->present == 0) { + SDC_LOGD("sdc power init.\n"); + HAL_SDC_PowerOn(host); + } else if (host->present == 0) { + /* if card is not present and the card detect mode is not CARD_DETECT_BY_D3, + * we shutdown io voltage to save power. */ + SDC_LOGD("sdc no card detected, shutdown io voltage.\n"); + __mci_hold_io(host); + //__mci_set_vddio(host, SDC_VOLTAGE_OFF); + } +#endif + +#ifdef CONFIG_SD_PM +#ifdef __CONFIG_ARCH_APP_CORE + memcpy(&g_sdc_param, param, sizeof(SDC_InitTypeDef)); +#endif + pm_register_ops(SDC_DEV); +#endif + + host->State = SDC_STATE_READY; + SDC_LOGD("sdc init ok.\n"); + + return host; +} + +/** + * @brief DeInitializes the SDC peripheral. + * @param sdc_id: + * @arg sdc_id-> SDC ID. + * @retval None. + */ +int32_t HAL_SDC_Deinit(uint32_t sdc_id) +{ + struct mmc_host *host = _mci_host; +#ifdef CONFIG_DETECT_CARD + host->param.cd_mode = 0; +#endif + SDC_BUG_ON(!host); + +#ifdef CONFIG_SD_PM + pm_unregister_ops(SDC_DEV); +#endif + + __mci_exit_host(host); + HAL_CCM_SDC_DisableMClock(); + SDC_CCM_BusForceReset(); + +#ifdef CONFIG_DETECT_CARD + HAL_BoardIoctl(HAL_BIR_PINMUX_DEINIT, HAL_MKDEV(HAL_DEV_MAJOR_SDC, host->sdc_id), SDCGPIO_DET); +#endif + +#ifdef CONFIG_SDC_EXCLUSIVE_HOST + SDC_SemDel(&host->exclusive_lock); +#endif + SDC_MutexDelete(&host->thread_lock); + SDC_SemDel(&host->lock); + +#ifdef CONFIG_DETECT_CARD + if ((host->param.cd_mode == CARD_DETECT_BY_GPIO_IRQ)|| + (host->param.cd_mode == CARD_DETECT_BY_D3)) { + SDC_DelTimer(&host->cd_timer); + } +#endif + + memset((void *)_mci_host, 0, sizeof(struct mmc_host)); /* SDC_STATE_RESET */ + _mci_host = NULL; + SDC_LOGD("sdc deinit ok.\n"); + + return 0; +} diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/sd.c b/platform/mcu/xr871/src/driver/chip/sdmmc/sd.c new file mode 100644 index 0000000000..f747b5e000 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/sd.c @@ -0,0 +1,773 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../hal_base.h" + +#include "sys/endian.h" + +#include "driver/chip/sdmmc/hal_sdhost.h" +#include "driver/chip/sdmmc/sdmmc.h" +#include "sdhost.h" +#include "core.h" +#ifdef CONFIG_USE_MMC +#include "_mmc.h" +#endif +#include "_sd.h" + +#ifdef CONFIG_USE_SD +static const unsigned int tran_exp[] = { + 10000, 100000, 1000000, 10000000, + 0, 0, 0, 0 +}; + +static const unsigned char tran_mant[] = { + 0, 10, 12, 13, 15, 20, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80, +}; +/* +static const unsigned int tacc_exp[] = { + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, +}; + +static const unsigned int tacc_mant[] = { + 0, 10, 12, 13, 15, 20, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80, +}; +*/ + +static int32_t mmc_send_app_op_cond(struct mmc_host *host, uint32_t ocr, uint32_t *rocr) +{ + struct mmc_command cmd = {0}; + int32_t i, err; + + SD_BUG_ON(!host); + + cmd.opcode = SD_APP_OP_COND; + cmd.arg = ocr; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R3 | MMC_CMD_BCR; + + for (i = 100; i; i--) { + err = mmc_wait_for_app_cmd(host, NULL, &cmd); + if (err) + break; + + /* otherwise wait until reset completes */ + if (cmd.resp[0] & MMC_CARD_BUSY) + break; + + cmd.arg = 0x41000000 | (cmd.resp[0] & 0xFF8000); + + err = -1; + + mmc_mdelay(10); + } + + if (rocr) + *rocr = cmd.resp[0]; + + return err; +} + +int32_t mmc_app_sd_status(struct mmc_card *card, uint8_t *ssr) +{ + struct mmc_request mrq; + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct scatterlist sg; + + SD_BUG_ON(!ssr); + + if (mmc_app_cmd(card->host, card)) { + return -1; + } + + mrq.cmd = &cmd; + mrq.data = &data; + + cmd.opcode = SD_APP_SD_STATUS; + cmd.arg = 0; + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_ADTC; + + data.blksz = 64; + data.blocks = 1; + data.flags = MMC_DATA_READ; + data.sg = &sg; + data.sg_len = 1; + + sg.len = 64; + sg.buffer = ssr; + + if (mmc_wait_for_req(card->host, &mrq)) { + return -1; + } + + SD_LOGN("card raw SD status:\n"); + sd_hex_dump_bytes((void *)ssr, 64); + + return 0; +} + +int32_t mmc_app_send_scr(struct mmc_card *card, uint32_t *raw_scr) +{ + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct mmc_request mrq; + struct scatterlist sg; + + if (mmc_app_cmd(card->host, card)) { + return -1; + } + + mrq.cmd = &cmd; + mrq.data = &data; + + cmd.opcode = SD_APP_SEND_SCR; + cmd.arg = 0; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; + + + data.blksz = 8; + data.blocks = 1; + data.flags = MMC_DATA_READ; + data.sg = &sg; + data.sg_len = 1; + + sg.len = 8; + sg.buffer = (void *)raw_scr; + + /* get scr, 8 bytes */ + if (mmc_wait_for_req(card->host, &mrq)) { + return -1; + } + + raw_scr[0] = be32_to_cpu(raw_scr[0]); + raw_scr[1] = be32_to_cpu(raw_scr[1]); + + return 0; +} + +/* + * Given the decoded CSD structure, decode the raw CID to our CID structure. + */ +void mmc_decode_cid(struct mmc_card *card, uint32_t *resp) +{ + memset(&card->cid, 0, sizeof(struct mmc_cid)); + + /* + * SD doesn't currently have a version field so we will + * have to assume we can parse this. + */ + card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); + card->cid.oemid = UNSTUFF_BITS(resp, 104, 8); + card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8); + card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8); + card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8); + card->cid.prod_name[3] = UNSTUFF_BITS(resp, 72, 8); + card->cid.prod_name[4] = UNSTUFF_BITS(resp, 64, 8); + card->cid.hwrev = UNSTUFF_BITS(resp, 60, 4); + card->cid.fwrev = UNSTUFF_BITS(resp, 56, 4); + card->cid.serial = UNSTUFF_BITS(resp, 24, 32); + card->cid.year = UNSTUFF_BITS(resp, 12, 8); + card->cid.month = UNSTUFF_BITS(resp, 8, 4); + + card->cid.year += 2000; /* SD cards year offset */ +} + +int32_t mmc_send_cid(struct mmc_card *card) +{ + struct mmc_command cmd = {0}; + uint32_t cid[4] = {0}; + + cmd.opcode = MMC_SEND_CID; + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_R2 | MMC_CMD_AC; + + if (mmc_wait_for_cmd(card->host, &cmd)) { + return -1; + } + + memcpy((void *)cid, (void *)cmd.resp, 16); + SD_LOGN("card raw cid:\n"); + sd_hex_dump_bytes((void *)cid, 16); + + mmc_decode_cid(card, cid); + + return 0; +} + +static int32_t mmc_decode_csd(struct mmc_card *card, uint32_t *csd) +{ + int32_t e, m, csd_struct; + uint32_t *resp = csd; + + csd_struct = UNSTUFF_BITS(resp, 126, 2); + card->csd.csd_ver = csd_struct; + + switch (csd_struct) { + case 0: + //m = UNSTUFF_BITS(resp, 115, 4); + //e = UNSTUFF_BITS(resp, 112, 3); + //csd->tacc_ns = (tacc_exp[e] * tacc_mant[m] + 9) / 10; + //csd->tacc_clks = UNSTUFF_BITS(resp, 104, 8) * 100; + + m = UNSTUFF_BITS(resp, 99, 4); + e = UNSTUFF_BITS(resp, 96, 3); + card->csd.max_dtr = tran_exp[e] * tran_mant[m]; + card->csd.cmdclass = UNSTUFF_BITS(resp, 84, 12); + + e = UNSTUFF_BITS(resp, 47, 3); + m = UNSTUFF_BITS(resp, 62, 12); + card->csd.c_size_mult = e; + card->csd.c_size = m; + card->csd.capacity = (1 + m) << (e + 2); + + //csd->read_blkbits = UNSTUFF_BITS(resp, 80, 4); + card->csd.read_blk_len = UNSTUFF_BITS(resp, 80, 4); + //csd->read_partial = UNSTUFF_BITS(resp, 79, 1); + //csd->write_misalign = UNSTUFF_BITS(resp, 78, 1); + //csd->read_misalign = UNSTUFF_BITS(resp, 77, 1); + //csd->r2w_factor = UNSTUFF_BITS(resp, 26, 3); + //csd->write_blkbits = UNSTUFF_BITS(resp, 22, 4); + //csd->write_partial = UNSTUFF_BITS(resp, 21, 1); + + //if (UNSTUFF_BITS(resp, 46, 1)) { + // csd->erase_size = 1; + //} else if (csd->write_blkbits >= 9) { + // csd->erase_size = UNSTUFF_BITS(resp, 39, 7) + 1; + // csd->erase_size <<= csd->write_blkbits - 9; + //} + break; + case 1: + /* + * This is a block-addressed SDHC or SDXC card. Most + * interesting fields are unused and have fixed + * values. To avoid getting tripped by buggy cards, + * we assume those fixed values ourselves. + */ + mmc_card_set_blockaddr(card); + + //csd->tacc_ns = 0; /* Unused */ + //csd->tacc_clks = 0; /* Unused */ + + m = UNSTUFF_BITS(resp, 99, 4); + e = UNSTUFF_BITS(resp, 96, 3); + card->csd.cmdclass = UNSTUFF_BITS(resp, 84, 12); + card->csd.read_blk_len = UNSTUFF_BITS(resp, 80, 4); + card->csd.max_dtr = tran_exp[e] * tran_mant[m]; + + m = UNSTUFF_BITS(resp, 48, 22); + card->csd.c_size = m; + card->csd.capacity = (1 + m) << 9; + /* SDXC cards have a minimum C_SIZE of 0x00FFFF */ + if (card->csd.c_size >= 0xFFFF) + mmc_card_set_ext_capacity(card); + + card->csd.c_size_mult = 0; + + //csd->read_blkbits = 9; + //csd->read_partial = 0; + //csd->write_misalign = 0; + //csd->read_misalign = 0; + //csd->r2w_factor = 4; /* Unused */ + //csd->write_blkbits = 9; + //csd->write_partial = 0; + //csd->erase_size = 1; + break; + default: + SD_LOGE("%s: unrecognised CSD structure version %d\n", + __func__, csd_struct); + return -1; + } + + //card->erase_size = csd->erase_size; + SD_LOGD("%s %d c_z:%d ca:%d %d\n", __func__, csd_struct, card->csd.c_size, + card->csd.capacity, card->csd.c_size_mult); + + return 0; +} + +/* + * Given a 64-bit response, decode to our card SCR structure. + */ +static int32_t mmc_decode_scr(struct mmc_card *card, uint32_t *raw_scr) +{ + struct sd_scr *scr = &card->scr; + uint32_t scr_struct; + uint32_t resp[4]; + + resp[3] = raw_scr[1]; + resp[2] = raw_scr[0]; + + scr_struct = UNSTUFF_BITS(resp, 60, 4); + if (scr_struct != 0) { + SD_LOGW("sdc unrecognised SCR structure version %d\n", scr_struct); + return -1; + } + + scr->sda_vsn = UNSTUFF_BITS(resp, 56, 4); + scr->security_sup = UNSTUFF_BITS(resp, 52, 3); + scr->bus_widths = UNSTUFF_BITS(resp, 48, 4); + + if (scr->sda_vsn == SCR_SPEC_VER_2) + /* Check if Physical Layer Spec v3.0 is supported */ + scr->sda_spec3 = UNSTUFF_BITS(resp, 47, 1); + + //if (UNSTUFF_BITS(resp, 55, 1)) + // card->erased_byte = 0xFF; + //else + // card->erased_byte = 0x0; + + if (scr->sda_spec3) { + scr->cmds = UNSTUFF_BITS(resp, 32, 2); + scr->sda_spec4 = UNSTUFF_BITS(resp, 42, 1); + scr->sda_spec5 = UNSTUFF_BITS(resp, 38, 4); + } + + return 0; +} + +/* + * Fetch and process SD Status register. + */ +static int32_t mmc_read_ssr(struct mmc_card *card) +{ + int32_t err, i; + uint32_t ssr[64/4]; + + if (!(card->csd.cmdclass & CCC_APP_SPEC)) { + SD_LOGW("%s: card lacks mandatory SD Status function.\n", __func__); + return 0; + } + + err = mmc_app_sd_status(card, (uint8_t *)ssr); + if (err) { + SD_LOGW("%s: problem reading SD Status register.\n", __func__); + err = 0; + goto out; + } + + for (i = 0; i < 16; i++) + ssr[i] = be32_to_cpu(ssr[i]); + + card->speed_class = UNSTUFF_BITS(ssr, 440 - 384, 8) * 2; + if (card->speed_class == 8) + card->speed_class = 10; +out: + return err; +} + +/* + * Fetches and decodes switch information + */ +static int32_t mmc_read_switch(struct mmc_card *card) +{ + int32_t err; + uint32_t status[64/sizeof(uint32_t)] = {0}; + uint8_t *p_sta = (uint8_t *)status; + + if (card->scr.sda_vsn < SCR_SPEC_VER_1) { + SD_LOGW("Card ver. does not support to read switch info!\n"); + return -1; + } + if (!(card->csd.cmdclass & CCC_SWITCH)) { + SD_LOGW("Card cmdclass does not support to read switch info!\n"); + return -1; + } + + /* Find out the supported Bus Speed Modes. */ + err = mmc_sd_switch(card, SD_SWITCH_CHECK, SD_SWITCH_GRP_ACCESS_MODE, + SD_SWITCH_ACCESS_HS, p_sta); + if (err) { + SD_LOGW("%s: problem reading Bus Speed modes.\n", __func__); + goto out; + } + + if (p_sta[13] & SD_MODE_HIGH_SPEED) + card->sw_caps.hs_max_dtr = HIGH_SPEED_MAX_DTR; + + if (card->scr.sda_spec3) { + card->sw_caps.sd3_bus_mode = p_sta[13]; + + /* Find out Driver Strengths supported by the card */ + err = mmc_sd_switch(card, SD_SWITCH_CHECK, SD_SWITCH_GRP_DRV_STRENGTH, + SD_SWITCH_ACCESS_HS, p_sta); + if (err) { + SD_LOGW("%s: problem reading Driver Strength.\n", __func__); + goto out; + } + + card->sw_caps.sd3_drv_type = p_sta[9]; + + /* Find out Current Limits supported by the card */ + err = mmc_sd_switch(card, SD_SWITCH_CHECK, SD_SWITCH_GRP_CUR_LIMIT, + SD_SWITCH_ACCESS_HS, p_sta); + if (err) { + SD_LOGW("%s: problem reading Current Limit.\n", __func__); + goto out; + } + + card->sw_caps.sd3_curr_limit = p_sta[7]; + } + +out: + return err; +} + +/* + * Test if the card supports high-speed mode and, if so, switch to it. + */ +int32_t mmc_sd_switch_hs(struct mmc_card *card) +{ + int32_t err; + uint32_t status[64/sizeof(uint32_t)] = {0}; + uint8_t *p_sta = (uint8_t *)status; + + if (card->scr.sda_vsn < SCR_SPEC_VER_1) { + SD_LOGW("Card ver. does not support to switch to high speed!\n"); + return -1; + } + + if (!(card->csd.cmdclass & CCC_SWITCH)) { + SD_LOGW("Card cmdclass not support to switch to high speed!\n"); + return -1; + } + + if (!(card->host->caps & MMC_CAP_SD_HIGHSPEED)) + return -1; + + /* Check function */ + err = mmc_sd_switch(card, SD_SWITCH_CHECK, SD_SWITCH_GRP_ACCESS_MODE, + SD_SWITCH_ACCESS_HS, p_sta); + if (err) + return err; + + if ((p_sta[16] & 0x0F) != 1) { + SD_LOGW("%s: Problem switching card into high-speed mode!\n", __func__); + err = -1; + } else { + err = 0; + } + + return err; +} + +static int32_t mmc_send_cxd_native(struct mmc_host *host, uint32_t arg, uint32_t *cxd, int32_t opcode) +{ + int32_t err; + struct mmc_command cmd = {0}; + + SD_BUG_ON(!host); + SD_BUG_ON(!cxd); + + cmd.opcode = opcode; + cmd.arg = arg; + cmd.flags = MMC_RSP_R2 | MMC_CMD_AC; + + err = mmc_wait_for_cmd(host, &cmd); + if (err) + return err; + + memcpy(cxd, cmd.resp, sizeof(uint32_t) * 4); + + return 0; +} + +int32_t mmc_send_csd(struct mmc_card *card, uint32_t *csd) +{ + return mmc_send_cxd_native(card->host, card->rca << 16, + csd, MMC_SEND_CSD); +} + +int32_t mmc_sd_get_csd(struct mmc_card *card) +{ + int32_t err; + uint32_t csd[4] = {0}; + + /* Fetch CSD from card. */ + err = mmc_send_csd(card, csd); + if (err) + return err; + + SD_LOGN("card raw csd:\n"); + sd_hex_dump_bytes((void *)csd, 16); + + err = mmc_decode_csd(card, csd); + if (err) + return err; + + return 0; +} + +int32_t mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card) +{ + int32_t err; + int32_t retries; + uint32_t raw_scr[2] = {0}; + + /* Fetch SCR from card. */ + err = mmc_app_send_scr(card, raw_scr); + if (err) + return err; + + SD_LOGN("card raw scr:\n"); + sd_hex_dump_bytes((void *)raw_scr, 8); + + err = mmc_decode_scr(card, raw_scr); + if (err) + return err; + + /* Fetch and process SD Status register. */ + err = mmc_read_ssr(card); + if (err) + return err; + + /* Fetch switch information from card. */ + for (retries = 1; retries <= 3; retries++) { + err = mmc_read_switch(card); + if (!err) { + if (retries > 1) { + SD_LOGW("%s: recovered\n", __func__); + } + break; + } else { + SD_LOGW("%s: read switch failed (attempt %d)\n", + __func__, retries); + } + } + + if (err) + return err; + + return 0; +} + +uint32_t mmc_sd_get_max_clock(struct mmc_card *card) +{ + uint32_t max_dtr = (uint32_t)-1; + + if (mmc_card_highspeed(card)) { + if (max_dtr > card->sw_caps.hs_max_dtr) + max_dtr = card->sw_caps.hs_max_dtr; + } else if (max_dtr > card->csd.max_dtr) { + max_dtr = card->csd.max_dtr; + } + + return max_dtr; +} + +/* + * Handle the detection and initialisation of a card. + * + * In the case of a resume, "oldcard" will contain the card + * we're trying to reinitialise. + */ +static int32_t mmc_sd_init_card(struct mmc_card *card, struct mmc_host *host) +{ + int32_t err = 0; + + /* + * I/O voltage should be 3.3 V here for the initialization needed. + */ + + /* cmd2, send cid, check if card support 3.3V */ + err = mmc_all_send_cid(host, card->cidno); + if (err) { + SD_LOGW("Cards all send CID number failed !!\n"); + return -1; + } else + SD_LOGN("Card CID number:%x\n", card->cidno[0]); + + card->type = MMC_TYPE_SD; + + /* cmd3, For native busses: get card RCA and quit open drain mode. */ + err = mmc_send_relative_addr(card->host, &card->rca); + if (err) { + SD_LOGW("Card public new RCA failed !!\n"); + return -1; + } else + SD_LOGD("Card public new RCA:%x\n", card->rca); + + /* cmd10, get CID register */ + if (mmc_send_cid(card)) { + SD_LOGW("Card send CID reg failed !!\n"); + return -1; + } + + /* cmd9, get CSD register */ + if (mmc_sd_get_csd(card)) { + SD_LOGW("Card send CSD reg failed !!\n"); + return -1; + } + + /* cmd7, Select card to standby state, as all following commands rely on that. */ + if (mmc_select_card(card, 1)) { + SD_LOGW("mmc_select_card failed !!\n"); + return -1; + } + + err = mmc_sd_setup_card(host, card); + if (err) + goto free_card; + + /* Initialization sequence for UHS-I cards */ + { + uint32_t clk; + uint32_t retries = 3; + + while (retries) { + err = mmc_sd_switch_hs(card); + if (err < 0) { + SD_LOGE("%s: Re-switch hs, err %d (retries = %d)\n", + __func__, err, retries); + mmc_mdelay(5); + retries--; + continue; + } + break; + } + + if (err) { + SD_LOGW("switch to high speed error, use DS: 25 MHz\n"); + clk = 25000000; + HAL_SDC_Update_Clk(card->host, clk); + err = 0; + } else { + mmc_card_set_highspeed(card); + card->sd_bus_speed = HIGH_SPEED_BUS_SPEED; + + clk = mmc_sd_get_max_clock(card); + HAL_SDC_Update_Clk(card->host, clk); + SD_LOGN("card is switched to high speed mode, clk:%d KHz\n", clk/1000); + } + + /* Switch to wider bus (if supported). */ + if ((host->caps & MMC_CAP_4_BIT_DATA) && + (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) { + err = mmc_app_set_bus_width(card, MMC_BUS_WIDTH_4); + if (err) { + SD_LOGW("Set bus width error, use default 1 bit !!\n"); + return -1; + } + + /* config SDMMC controller bus width */ + HAL_SDC_Set_BusWidth(card->host, MMC_BUS_WIDTH_4); + SD_LOGN("Set bus width type: %d\n", MMC_BUS_WIDTH_4); + } + } + + mmc_add_card(card); + card->host->card = card; + + return 0; + +free_card: + card->host->card = NULL; + return err; +} + +#ifdef CONFIG_SD_PM +static uint32_t mmc_sd_suspending; + +static int32_t mmc_sd_suspend(struct mmc_host *host) +{ + mmc_sd_suspending = 1; + mmc_card_deinit(host->card); + SD_LOGD("%s ok\n", __func__); + + return 0; +} + +static int32_t mmc_sd_resume(struct mmc_host *host) +{ + mmc_rescan(host->card, host->sdc_id); + mmc_sd_suspending = 0; + SD_LOGD("%s ok\n", __func__); + + return 0; +} + +static const struct mmc_bus_ops sd_bus_ops = { + .suspend = mmc_sd_suspend, + .resume = mmc_sd_resume, +}; +#endif + +/* + * Starting point for SD card init. + */ +int32_t mmc_attach_sd(struct mmc_card *card, struct mmc_host *host) +{ + int32_t err = 0; + uint32_t ocr; + + SD_BUG_ON(!host); + + /* send cmd41/55 to check operation condition */ + err = mmc_send_app_op_cond(host, 0, &ocr); + if (err) { + return err; + } + SD_LOGN("card ocr: %08x\n", ocr); + + /* + * Sanity check the voltages that the card claims to + * support. + */ + if (ocr & 0x7F) { + SD_LOGW("%s: card claims to support voltages below the defined range." + " These will be ignored.\n", __func__); + ocr &= ~0x7F; + } + + card->ocr.ocr = 0x7fffffff & ocr; /* set card not in busy state */ + + err = mmc_sd_init_card(card, host); + +#ifdef CONFIG_SD_PM + if (!mmc_sd_suspending) { + mmc_attach_bus(host, &sd_bus_ops); + } +#endif + + return err; +} + +void mmc_deattach_sd(struct mmc_card *card, struct mmc_host *host) +{ + mmc_select_card(host->card, 0); + host->card->state &= ~MMC_STATE_HIGHSPEED; + +#ifdef CONFIG_SD_PM + if (!mmc_sd_suspending) { + mmc_detach_bus(host); + } +#endif +} + +#endif /* CONFIG_USE_SD */ diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/sdhost.h b/platform/mcu/xr871/src/driver/chip/sdmmc/sdhost.h new file mode 100644 index 0000000000..b7b0987571 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/sdhost.h @@ -0,0 +1,553 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRIVER_CHIP_SDMMC_SDHOST_H_ +#define _DRIVER_CHIP_SDMMC_SDHOST_H_ + +#include "../hal_debug.h" + +#include "driver/chip/hal_util.h" +#include "driver/chip/sdmmc/card.h" +#include "driver/chip/sdmmc/hal_sdhost.h" +#ifdef CONFIG_USE_SDIO +#include "driver/chip/sdmmc/sdio.h" +#endif +#include "driver/chip/sdmmc/sdmmc.h" +#include "pm/pm.h" + +#define CONFIG_SDC_OS_USED + +#ifdef SD_SUPPORT_VERSION3 +#define CONFIG_SDC_SUPPORT_1V8 /* board not support */ +#endif +#ifndef __CONFIG_ARCH_DUAL_CORE +//#define CONFIG_SDC_DMA_USED +#endif +#ifdef SD_SUPPORT_WRITEPROTECT +#define CONFIG_SDC_READONLY_USED /* check readonly */ +#endif + +#define SDC_DEBUG 1 + +#ifdef CONFIG_SDC_OS_USED +#include "./../hal_os.h" +#include "kernel/os/os_semaphore.h" +#include "kernel/os/os_mutex.h" +#ifdef __CONFIG_ARCH_APP_CORE +#include "kernel/os/os_timer.h" +#endif + +#define SDC_Semaphore OS_Semaphore_t +#define SDC_Mutex OS_Mutex_t +#ifdef __CONFIG_ARCH_APP_CORE +#define SDC_Timer OS_Timer_t +#endif +#endif + +#if SDC_DEBUG +#define SDC_LOGD(format, args...) HAL_LOG(0, format, ##args) +#define SDC_LOGN(format, args...) HAL_LOG(SDC_DEBUG, format, ##args) +#define SDC_LOGW(format, args...) HAL_LOG(SDC_DEBUG, format, ##args) +#define SDC_LOGE(format, args...) HAL_LOG(SDC_DEBUG, format, ##args) +#define SDC_LOGA(format, args...) HAL_LOG(SDC_DEBUG, format, ##args) +#else +#define SDC_LOGD(x...) +#define SDC_LOGN(x...) +#define SDC_LOGW(x...) +#define SDC_LOGE(x...) +#define SDC_LOGA(x...) +#endif +#define SDC_BUG_ON(v) do {if(v) {printf("BUG at %s:%d!\n", __func__, __LINE__); while (1);}} while (0) +#define SDC_WARN_ON(v) do {if(v) {printf("WARN at %s:%d!\n", __func__, __LINE__);}} while (0) + +#define mmc_mdelay(ms) OS_MSleep(ms) +#define mmc_udelay(us) HAL_UDelay(us) + +#ifdef CONFIG_PM +#define CONFIG_SD_PM +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if ((defined SDIO_EXCLUSIVE_HOST) || (defined SD_EXCLUSIVE_HOST) || (defined MMC_EXCLUSIVE_HOST)) +#define CONFIG_SDC_EXCLUSIVE_HOST +#endif + +struct scatterlist { + void *buffer; + uint32_t len; +}; + +/* IDMC structure */ +typedef struct { + uint32_t config; + +#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ +#define SDXC_IDMAC_DES0_LD BIT(2) /* 1-this data buffer is the last buffer */ +#define SDXC_IDMAC_DES0_FD BIT(3) /* 1-data buffer is the first buffer, 0-data buffer contained in the next descriptor is the first data buffer */ +#define SDXC_IDMAC_DES0_CH BIT(4) /* 1-the 2nd address in the descriptor is the next descriptor address */ +#define SDXC_IDMAC_DES0_ER BIT(5) /* 1-last descriptor flag when using dual data buffer in descriptor */ +#define SDXC_IDMAC_DES0_CES BIT(30) /* transfer error flag */ +#define SDXC_IDMAC_DES0_OWN BIT(31) /* des owner:1-idma owns it, 0-host owns it */ + + uint32_t data_buf1_sz :16, + data_buf2_sz :16; + + uint32_t buf_addr_ptr1; + uint32_t buf_addr_ptr2; +} smc_idma_des; + +typedef enum +{ + SDC_STATE_RESET = 0x00, /* Peripheral is not yet Initialized */ + SDC_STATE_READY = 0x02, /* Peripheral Initialized and ready for use */ + SDC_STATE_BUSY = 0x04, /* An internal process is ongoing */ + SDC_STATE_ERROR = 0x08 /* Error */ +} SDC_StateTypeDef; + +struct mmc_bus_ops { + int (*suspend)(struct mmc_host *); + int (*resume)(struct mmc_host *); +}; + +struct mmc_host { + uint32_t sdc_id; + struct mmc_card *card; +#ifdef CONFIG_SDC_SUPPORT_1V8 + uint32_t voltage; +#define SDC_WOLTAGE_3V3 (0) +#define SDC_WOLTAGE_1V8 (1) +#define SDC_WOLTAGE_1V2 (2) +#define SDC_WOLTAGE_OFF (3) +#define SDC_WOLTAGE_ON (4) + uint32_t voltage_switching; +#endif + volatile uint32_t present; + uint32_t power_on; + uint32_t suspend; + uint32_t int_err; /* for Interrupt Controller */ + + uint32_t int_use; /* Control */ + uint32_t int_sum; /* interrupt summary */ + uint32_t trans_done; + uint32_t dma_done; + uint32_t buswidth; /* current card bus width */ + uint32_t blkcnt; + + smc_idma_des *dma_hdle; + + /* host specific block data */ + uint32_t max_seg_size; /* see blk_queue_max_segment_size */ + uint32_t max_segs; /* see blk_queue_max_segments */ + uint32_t max_req_size; /* maximum number of bytes in one req */ + uint32_t max_blk_size; /* maximum size of one mmc block */ + uint32_t max_blk_count; /* maximum number of blocks in one req */ + uint32_t ocr_avail; + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + + uint32_t caps; /* Host capabilities */ + +#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ +#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ +#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ +#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ +#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ +#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ + +#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ +#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ +#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ + /* DDR mode at 1.8V */ +#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ + /* DDR mode at 1.2V */ +#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ +#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ +#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ +#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ +#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ +#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ +#define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */ +#define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */ +#define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */ +#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ +#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ +#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ +#define MMC_CAP_MAX_CURRENT_200 (1 << 26) /* Host max current limit is 200mA */ +#define MMC_CAP_MAX_CURRENT_400 (1 << 27) /* Host max current limit is 400mA */ +#define MMC_CAP_MAX_CURRENT_600 (1 << 28) /* Host max current limit is 600mA */ +#define MMC_CAP_MAX_CURRENT_800 (1 << 29) /* Host max current limit is 800mA */ +#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ +#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ + + uint32_t caps2; /* More host capabilities */ + +#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ +#define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */ +#define MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */ +#define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */ +#define MMC_CAP2_NO_SLEEP_CMD (1 << 4) /* Don't allow sleep command */ +#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ +#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ +#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR) +#define MMC_CAP2_BROKEN_VOLTAGE (1 << 7) /* Use the broken voltage */ +#define MMC_CAP2_DETECT_ON_ERR (1 << 8) /* On I/O err check card removal */ +#define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ + +#ifdef CONFIG_SDC_OS_USED + SDC_Semaphore lock; + SDC_Mutex thread_lock; +#ifdef CONFIG_DETECT_CARD + SDC_Timer cd_timer; +#endif +#ifdef CONFIG_SDC_EXCLUSIVE_HOST + SDC_Semaphore exclusive_lock; /* lock for claim and bus ops */ +#endif +#endif + + //uint8_t bus_width; /* data bus width */ + uint32_t clk; + +#define MMC_BUS_WIDTH_1 0 +#define MMC_BUS_WIDTH_4 2 +#define MMC_BUS_WIDTH_8 3 + + struct mmc_request *mrq; + +#define SDC_WAIT_NONE BIT(0) +#define SDC_WAIT_CMD_DONE BIT(1) +#define SDC_WAIT_DATA_OVER BIT(2) +#define SDC_WAIT_AUTOCMD_DONE BIT(3) +#define SDC_WAIT_IDMA_DONE BIT(4) +#define SDC_WAIT_IDMA_ERR BIT(5) +#define SDC_WAIT_ERROR BIT(6) +#define SDC_WAIT_RXDATA_OVER (SDC_WAIT_DATA_OVER|SDC_WAIT_IDMA_DONE) +#define SDC_WAIT_RXAUTOCMD_DONE (SDC_WAIT_AUTOCMD_DONE|SDC_WAIT_IDMA_DONE) +#define SDC_WAIT_SWITCH1V8 BIT(7) +#define SDC_WAIT_FINALIZE BIT(8) + volatile uint32_t smc_cmd; + + uint32_t wait; +#ifdef CONFIG_SDIO_IRQ_SUPPORT + uint32_t sdio_int; +#endif +#ifdef CONFIG_SD_PM + const struct mmc_bus_ops *bus_ops; /* current bus driver */ + uint32_t pm_flags; /* requested pm features */ + uint32_t pm_caps; /* supported pm features */ +#endif +#ifdef __CONFIG_ARCH_APP_CORE + SDC_InitTypeDef param; + GPIO_Port cd_port; + GPIO_Pin cd_pin; +#endif +#ifdef CONFIG_SDC_READONLY_USED + uint32_t read_only; + GPIO_PinMuxParam ro_gpio; +#endif + SDC_StateTypeDef State; +}; + +#define SDC_MAX_CPU_TRANS_LEN 64 + +//#define SMC_LOW_POWER_MODE 0 /* 1--Close Clock when Idle, 0--Clock always on */ +/* IDMA control */ +#define IDMAC_DES_MODE 0 /* 0-chain mode, 1-fix skip length */ + +#define SMC_RX_WLEVEL 7 +#define SMC_TX_WLEVEL 8 +#define BURST_SIZE 2 + +#define IDMA_MAX_TBKNUM_ONETIME 16 + +/* registers define */ +#ifdef __CONFIG_ARCH_APP_CORE +#define SMC0_BASE (0x40002000) +#else +#define SMC0_BASE (0xA0001000) +#endif + +#define SDXC_REG_GCTRL (SMC0_BASE + 0x00) /* SMC Global Control Register */ +#define SDXC_REG_CLKCR (SMC0_BASE + 0x04) /* SMC Clock Control Register */ +#define SDXC_REG_TMOUT (SMC0_BASE + 0x08) /* SMC Time Out Register */ +#define SDXC_REG_WIDTH (SMC0_BASE + 0x0C) /* SMC Bus Width Register */ +#define SDXC_REG_BLKSZ (SMC0_BASE + 0x10) /* SMC Block Size Register */ +#define SDXC_REG_BCNTR (SMC0_BASE + 0x14) /* SMC Byte Count Register */ +#define SDXC_REG_CMDR (SMC0_BASE + 0x18) /* SMC Command Register */ +#define SDXC_REG_CARG (SMC0_BASE + 0x1C) /* SMC Argument Register */ +#define SDXC_REG_RESP0 (SMC0_BASE + 0x20) /* SMC Response Register 0 */ +#define SDXC_REG_RESP1 (SMC0_BASE + 0x24) /* SMC Response Register 1 */ +#define SDXC_REG_RESP2 (SMC0_BASE + 0x28) /* SMC Response Register 2 */ +#define SDXC_REG_RESP3 (SMC0_BASE + 0x2C) /* SMC Response Register 3 */ +#define SDXC_REG_IMASK (SMC0_BASE + 0x30) /* SMC Interrupt Mask Register */ +#define SDXC_REG_MISTA (SMC0_BASE + 0x34) /* SMC Masked Interrupt Status Register */ +#define SDXC_REG_RINTR (SMC0_BASE + 0x38) /* SMC Raw Interrupt Status Register */ +#define SDXC_REG_STAS (SMC0_BASE + 0x3C) /* SMC Status Register */ +#define SDXC_REG_FTRGL (SMC0_BASE + 0x40) /* SMC FIFO Threshold Watermark Register */ +#define SDXC_REG_FUNS (SMC0_BASE + 0x44) /* SMC Function Select Register */ +#define SDXC_REG_CBCR (SMC0_BASE + 0x48) /* SMC CIU Byte Count Register */ +#define SDXC_REG_BBCR (SMC0_BASE + 0x4C) /* SMC BIU Byte Count Register */ +#define SDXC_REG_DBGC (SMC0_BASE + 0x50) /* SMC Debug Enable Register */ +#define SDXC_REG_A12A (SMC0_BASE + 0x58) /* SMC auto command 12 argument */ +#define SDXC_REG_NTSR (SMC0_BASE + 0x5C) /* SMC NewTiming Set Register(RX TX) */ +#define SDXC_REG_SDEG (SMC0_BASE + 0x60) /* SMC NewTiming Set debg */ +#define SDXC_REG_HWST (SMC0_BASE + 0x78) /* SMC SMC hardware reset register */ +#define SDXC_REG_DMAC (SMC0_BASE + 0x80) /* SMC IDMAC Control Register */ +#define SDXC_REG_DLBA (SMC0_BASE + 0x84) /* SMC IDMAC Descriptor List Base Address Register */ +#define SDXC_REG_IDST (SMC0_BASE + 0x88) /* SMC IDMAC Status Register */ +#define SDXC_REG_IDIE (SMC0_BASE + 0x8C) /* SMC IDMAC Interrupt Enable Register */ +#define SDXC_REG_CHDA (SMC0_BASE + 0x90) /* SMC Current Host Descriptor Address Register */ +#define SDXC_REG_CBDA (SMC0_BASE + 0x94) /* SMC Current Buffer Descriptor Address Register */ +#define SDXC_REG_THLDC (SMC0_BASE + 0x100) /* SMC Threshold Control Register */ +#define SDXC_REG_DSBD (SMC0_BASE + 0x10C) +#define SDXC_REG_RESP_CRC (SMC0_BASE + 0x110) +#define SDXC_REG_DAT7_CRC (SMC0_BASE + 0x114) +#define SDXC_REG_DAT6_CRC (SMC0_BASE + 0x118) +#define SDXC_REG_DAT5_CRC (SMC0_BASE + 0x11C) +#define SDXC_REG_DAT4_CRC (SMC0_BASE + 0x120) +#define SDXC_REG_DAT3_CRC (SMC0_BASE + 0x124) +#define SDXC_REG_DAT2_CRC (SMC0_BASE + 0x128) +#define SDXC_REG_DAT1_CRC (SMC0_BASE + 0x12C) +#define SDXC_REG_DAT0_CRC (SMC0_BASE + 0x130) +#define SDXC_REG_CRC_STA (SMC0_BASE + 0x134) +#define SDXC_REG_FIFO (SMC0_BASE + 0x200) /* SMC FIFO Access Address */ + +#define SDXC_REG_FCTL (SMC0_BASE + 0x64) /* SMC FIFO Access Address */ +#define SDXC_REG_FCTL_OS (0x64) /* SMC FIFO Access Address */ + +/* global control register */ +#define SDXC_SoftReset BIT(0 ) +#define SDXC_FIFOReset BIT(1 ) +#define SDXC_DMAReset BIT(2 ) +#define SDXC_HWReset (SDXC_SoftReset|SDXC_FIFOReset|SDXC_DMAReset) +#define SDXC_INTEnb BIT(4 ) +#define SDXC_DMAEnb BIT(5 ) +#define SDXC_DebounceEnb BIT(8 ) +#define SDXC_DDR_MODE BIT(10) +#define SDXC_MemAccessDone BIT(29) +#define SDXC_AccessDoneDirect BIT(30) +#define SDXC_ACCESS_BY_AHB BIT(31) +#define SDXC_ACCESS_BY_DMA (0x0U << 31) + +/* Clock control */ +#define SDXC_CardClkOn (0x1U << 16) +#define SDXC_LowPowerOn (0x1U << 17) + +/* bus width */ +#define SDXC_WIDTH1 (0) +#define SDXC_WIDTH4 (1) +#define SDXC_WIDTH8 (2) + +/* Struct for SMC Commands */ +#define SDXC_CMD_OPCODE (0x3F ) /* 0x00000040 */ +#define SDXC_RspExp BIT(6 ) /* 0x00000080 */ +#define SDXC_LongRsp BIT(7 ) /* 0x00000100 */ +#define SDXC_CheckRspCRC BIT(8 ) /* 0x00000200 */ +#define SDXC_DataExp BIT(9 ) /* 0x00000000 */ +#define SDXC_Read (0x0U<<10 ) /* 0x00000400 */ +#define SDXC_Write BIT(10) /* 0x00000000 */ +#define SDXC_Blockmod (0x0U<<11 ) /* 0x00000800 */ +#define SDXC_Seqmod BIT(11) /* 0x00001000 */ +#define SDXC_SendAutoStop BIT(12) /* 0x00002000 */ +#define SDXC_WaitPreOver BIT(13) /* 0x00004000 */ +#define SDXC_StopAbortCMD BIT(14) /* 0x00008000 */ +#define SDXC_SendInitSeq BIT(15) /* 0x00200000 */ +#define SDXC_UPCLKOnly BIT(21) /* 0x00400000 */ +#define SDXC_RdCEATADev BIT(22) /* 0x00800000 */ +#define SDXC_CCSExp BIT(23) /* 0x01000000 */ +#define SDXC_EnbBoot BIT(24) /* 0x02000000 */ +#define SDXC_AltBootOpt BIT(25) /* 0x00000000 */ +#define SDXC_MandBootOpt (0x0U<<25) /* 0x04000000 */ +#define SDXC_BootACKExp BIT(26) /* 0x08000000 */ +#define SDXC_DisableBoot BIT(27) /* 0x10000000 */ +#define SDXC_VolSwitch BIT(28) /* 0x80000000 */ +#define SDXC_Start BIT(31) + +/* Struct for Intrrrupt Information */ +#define SDXC_RespErr BIT(1) /* 0x00000002 */ +#define SDXC_CmdDone BIT(2) /* 0x00000004 */ +#define SDXC_DataOver BIT(3) /* 0x00000008 */ +#define SDXC_TxDataReq BIT(4) /* 0x00000010 */ +#define SDXC_RxDataReq BIT(5) /* 0x00000020 */ +#define SDXC_RespCRCErr BIT(6) /* 0x00000040 */ +#define SDXC_DataCRCErr BIT(7) /* 0x00000080 */ +#define SDXC_RespTimeout BIT(8) /* 0x00000100 */ +#define SDXC_ACKRcv BIT(8) /* 0x00000100 */ +#define SDXC_DataTimeout BIT(9) /* 0x00000200 */ +#define SDXC_BootStart BIT(9) /* 0x00000200 */ +#define SDXC_DataStarve BIT(10) /* 0x00000400 */ +#define SDXC_VolChgDone BIT(10) /* 0x00000400 */ +#define SDXC_FIFORunErr BIT(11) /* 0x00000800 */ +#define SDXC_HardWLocked BIT(12) /* 0x00001000 */ +#define SDXC_StartBitErr BIT(13) /* 0x00002000 */ +#define SDXC_AutoCMDDone BIT(14) /* 0x00004000 */ +#define SDXC_EndBitErr BIT(15) /* 0x00008000 */ +#define SDXC_SDIOInt BIT(16) /* 0x00010000 */ +#define SDXC_CardInsert BIT(30) /* 0x40000000 */ +#define SDXC_CardRemove BIT(31) /* 0x80000000 */ +#define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr | SDXC_RespTimeout | SDXC_DataTimeout | \ + SDXC_FIFORunErr | SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr) /* 0xbbc2 */ +/* status */ +#define SDXC_RXWLFlag BIT(0) +#define SDXC_TXWLFlag BIT(1) +#define SDXC_FIFOEmpty BIT(2) +#define SDXC_FIFOFull BIT(3) +#define SDXC_CardPresent BIT(8) +#define SDXC_CardDataBusy BIT(9) +#define SDXC_DataFSMBusy BIT(10) +#define SDXC_DMAReq BIT(31) + +/* Function select */ +#define SDXC_CEATAOn (0xceaaU << 16) +#define SDXC_SendIrqRsp BIT(0) +#define SDXC_SDIORdWait BIT(1) +#define SDXC_AbtRdData BIT(2) +#define SDXC_SendCCSD BIT(8) +#define SDXC_SendAutoStopCCSD BIT(9) +#define SDXC_CEATADevIntEnb BIT(10) +/* status bit */ +#define SDXC_CardBusy BIT(9) +/* IDMA controller bus mod bit field */ +#define SDXC_IDMACSoftRST BIT(0) +#define SDXC_IDMACFixBurst BIT(1) +#define SDXC_IDMACIDMAOn BIT(7) +#define SDXC_IDMACRefetchDES BIT(31) + +/* IDMA status bit field */ +#define SDXC_IDMACTransmitInt BIT(0) +#define SDXC_IDMACReceiveInt BIT(1) +#define SDXC_IDMACFatalBusErr BIT(2) +#define SDXC_IDMACDesInvalid BIT(4) +#define SDXC_IDMACCardErrSum BIT(5) +#define SDXC_IDMACNormalIntSum BIT(8) +#define SDXC_IDMACAbnormalIntSum BIT(9) +#define SDXC_IDMACHostAbtInTx BIT(10) +#define SDXC_IDMACHostAbtInRx BIT(10) +#define SDXC_IDMACIdle (0x0U << 13) +#define SDXC_IDMACSuspend (0x1U << 13) +#define SDXC_IDMACDESCRd (0x2U << 13) +#define SDXC_IDMACDESCCheck (0x3U << 13) +#define SDXC_IDMACRdReqWait (0x4U << 13) +#define SDXC_IDMACWrReqWait (0x5U << 13) +#define SDXC_IDMACRd (0x6U << 13) +#define SDXC_IDMACWr (0x7U << 13) +#define SDXC_IDMACDESCClose (0x8U << 13) + +#define SDXC_IDMA_OVER (SDXC_IDMACTransmitInt|SDXC_IDMACReceiveInt|SDXC_IDMACNormalIntSum) +#define SDXC_IDMA_ERR (SDXC_IDMACFatalBusErr|SDXC_IDMACDesInvalid|SDXC_IDMACCardErrSum|SDXC_IDMACAbnormalIntSum) + +/* + * the max length of buffer which IDMA description supported is 8192, + * transport data by several IDMA descriptions if data lenght more than 8192, + * and the max number IDMA description support is 1024. + * which meas the mas length transport data is 1024 * 8192 = 8MB in a signal transfer. + */ +#ifdef __CONFIG_ARCH_APP_CORE +#define SDXC_MAX_TRANS_LEN (1 << 18) /* max len is 256K */ +#else +#define SDXC_MAX_TRANS_LEN (1 << 14) /* max len is 16K */ +#endif +#define SDXC_DES_NUM_SHIFT (13) +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) /* 8192 == 1<<13; */ +#define SDXC_MAX_DES_NUM (SDXC_MAX_TRANS_LEN >> SDXC_DES_NUM_SHIFT) /* 2 is the least */ +#define SDXC_DES_MODE (0) /* 0-chain mode, 1-fix length skip */ + +extern struct mmc_host *_mci_host; + +/* + * These flags are used to describe power management features that + * some cards (typically SDIO cards) might wish to benefit from when + * the host system is being suspended. There are several layers of + * abstractions involved, from the host controller driver, to the MMC core + * code, to the SDIO core code, to finally get to the actual SDIO function + * driver. This file is therefore used for common definitions shared across + * all those layers. + */ + +#define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ +#define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ +#define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */ + +#ifdef CONFIG_SD_PM +static inline int mmc_card_keep_power(struct mmc_host *host) +{ + return host->pm_flags & MMC_PM_KEEP_POWER; +} + +static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) +{ + return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; +} +#endif + +#ifdef CONFIG_SDC_READONLY_USED +extern int32_t HAL_SDC_Get_ReadOnly(struct mmc_host *host); +#endif +extern void HAL_SDC_Set_BusWidth(struct mmc_host *host, uint32_t width); +extern int32_t HAL_SDC_Update_Clk(struct mmc_host *host, uint32_t clk); +extern uint32_t HAL_SDC_Is_Busy(struct mmc_host *host); +extern int32_t HAL_SDC_Clk_PWR_Opt(struct mmc_host *host, uint32_t oclk_en, uint32_t pwr_save); +#ifdef CONFIG_SDC_EXCLUSIVE_HOST +extern int32_t HAL_SDC_Claim_Host(struct mmc_host *host); +extern void HAL_SDC_Release_Host(struct mmc_host *host); +#else +static inline int32_t HAL_SDC_Claim_Host(struct mmc_host *host) { return 0; } +static inline void HAL_SDC_Release_Host(struct mmc_host *host) { ; } +#endif +extern int32_t HAL_SDC_PowerOn(struct mmc_host *host); +extern int32_t HAL_SDC_PowerOff(struct mmc_host *host); + +extern int32_t HAL_SDC_Request(struct mmc_host *host, struct mmc_request *mrq); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_CHIP_SDMMC_SDHOST_H_ */ diff --git a/platform/mcu/xr871/src/driver/chip/sdmmc/test.c b/platform/mcu/xr871/src/driver/chip/sdmmc/test.c new file mode 100644 index 0000000000..0d7139c272 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/sdmmc/test.c @@ -0,0 +1,261 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "sys/io.h" +#include "sys/xr_debug.h" + +#include "kernel/os/os_time.h" +#include "kernel/os/os_semaphore.h" + +#include "driver/chip/hal_def.h" +#include "driver/chip/hal_ccm.h" +#include "driver/chip/sdmmc/hal_sdhost.h" +#include "driver/chip/sdmmc/sdmmc.h" + +#define TEST_SD +#define TEST_SD_WRITE + +#ifdef TEST_SD + +#define SIZE_1K (1024) +#define SIZE_1M (SIZE_1K*SIZE_1K) + +#define READ_WRITE_SINGLE_SIZE (16*SIZE_1K) +#define READ_WRITE_TOTAL_SIZE (8*SIZE_1M) + +static uint8_t wbuf[READ_WRITE_SINGLE_SIZE]; +static uint8_t rbuf[READ_WRITE_SINGLE_SIZE]; + +static struct mmc_card card; + +void print_hex_dump_words(const void *addr, unsigned int len); + +#ifdef CONFIG_DETECT_CARD +static OS_Semaphore_t card_present_sem; + +void card_detect(uint32_t present) +{ + if (present) { + printf("%s insert\n", __func__); + OS_MSleep(500); /* wait voltage stable */ + + if (mmc_rescan(&card, 0)) { + printf("Initial card failed!!\n"); + return ; + } else + printf("Initial card success\n"); + OS_SemaphoreRelease(&card_present_sem); + } else { + printf("%s removed\n", __func__); + } +} +#endif + +int32_t mmc_test_init(void) +{ + SDC_InitTypeDef sdc_param; +#ifdef CONFIG_DETECT_CARD + uint32_t card_exist = 1; + + OS_SemaphoreCreate(&card_present_sem, 0, OS_SEMAPHORE_MAX_COUNT); + + XR_ASSERT((cd_mode != CARD_ALWAYS_PRESENT) && (cd_mode != CARD_DETECT_BY_GPIO_IRQ) && \ + (cd_mode != CARD_DETECT_BY_D3), 1, " cd_mode config err!\n"); + + sdc_param.cd_mode = cd_mode; + sdc_param.cd_cb = &card_detect; +#endif + HAL_SDC_Init(0, &sdc_param); + + return 0; +} + +int32_t mmc_test_exit(void) +{ + if (!card.host) + return 0; + + mmc_card_deinit(&card); + HAL_SDC_Deinit(0); + + return 0; +} + +struct mmc_card *mmc_scan_init(void) +{ + if (!mmc_rescan(&card, 0)) + return &card; + else + return NULL; +} + +int32_t mmc_test(uint32_t cd_mode) +{ + int32_t err; + uint32_t i, cnt = 0; + + mmc_test_init(); /* reinit is ok */ + + memset((void *)wbuf, 0x55, 128); + memset((void *)&wbuf[128], 0xaa, 128); + + for (i = 0; i < 256; i ++) + wbuf[256 + i] = i; + + memcpy((void *)&wbuf[512], (void *)wbuf, 512); + + /* scan card for detect card is exist? */ + if (mmc_rescan(&card, 0)) { + printf("Initial card failed!!\n"); +#ifdef CONFIG_DETECT_CARD + card_exist = 0; +#else + goto out; +#endif + } else { + printf("Initial card success\n"); + } + + while (cnt++ < 100) { + uint32_t throuth_mb, throuth_kb; + OS_Time_t tick_use; +#ifdef CONFIG_DETECT_CARD + if (!card_exist || (cd_mode != CARD_ALWAYS_PRESENT)) + OS_SemaphoreWait(&card_present_sem, OS_WAIT_FOREVER); +#endif + + printf("%s,%d test count:%d\n", __func__, __LINE__, cnt); + +#ifdef TEST_SD_WRITE + tick_use = OS_GetTicks(); + err = mmc_block_write(&card, wbuf, 0, 1); + tick_use = OS_GetTicks() - tick_use; + if (err) { + goto err_out; + } else + printf("%s 1 block write ok, 512B use:%d ms\n", __func__, + (uint32_t)OS_TicksToMSecs(tick_use)); +#endif + memset((void *)rbuf, 0, 512); + tick_use = OS_GetTicks(); + err = mmc_block_read(&card, rbuf, 0, 1); + tick_use = OS_GetTicks() - tick_use; + if (err) { + goto err_out; + } else { + printf("%s 1 block read ok, 512B use:%d ms\n", __func__, + (uint32_t)OS_TicksToMSecs(tick_use)); +#ifndef TEST_SD_WRITE + print_hex_dump_words(rbuf, 512); +#endif + } +#ifdef TEST_SD_WRITE + if (memcmp((void *)wbuf, (void *)rbuf, 512)) { + goto err_out; + } else + printf("%s,%d mmc 1 block rw ok\n", __func__, __LINE__); + + tick_use = OS_GetTicks(); + for (i = 0; i < READ_WRITE_TOTAL_SIZE/READ_WRITE_SINGLE_SIZE; i++) { + err = mmc_block_write(&card, wbuf, 3 + i * (READ_WRITE_SINGLE_SIZE/512), + READ_WRITE_SINGLE_SIZE/512); + if (err) + break; + if (i % 50 == 0) + printf("%s, wirite cnt:%d\n", __func__, i); + } + tick_use = OS_GetTicks() - tick_use; + if (err) { + printf("%s,%d mmc mult blocks write err!\n", __func__, __LINE__); + goto err_out; + } else { + throuth_kb = READ_WRITE_TOTAL_SIZE/SIZE_1K*1000/(uint32_t)OS_TicksToMSecs(tick_use); + throuth_mb = throuth_kb/1000; + printf("%s mult blocks write ok, %d MB use:%d ms, throughput:%d.%d MB/S\n", + __func__, READ_WRITE_TOTAL_SIZE/SIZE_1M, (uint32_t)OS_TicksToMSecs(tick_use), + throuth_mb, throuth_kb - throuth_mb); + } +#endif + + tick_use = OS_GetTicks(); + for (i = 0; i < READ_WRITE_TOTAL_SIZE/READ_WRITE_SINGLE_SIZE; i++) { + err = mmc_block_read(&card, rbuf, 3 + i * (READ_WRITE_SINGLE_SIZE/512), + READ_WRITE_SINGLE_SIZE/512); + if (err) + break; + } + tick_use = OS_GetTicks() - tick_use; + if (err) { + printf("%s,%d mmc mult blocks read err!\n", __func__, __LINE__); + goto err_out; + } else { + throuth_kb = READ_WRITE_TOTAL_SIZE/SIZE_1K*1000/(uint32_t)OS_TicksToMSecs(tick_use); + throuth_mb = throuth_kb/1000; + printf("%s mult blocks read ok, %d MB use:%d ms, throughput:%d.%d MB/S\n", + __func__, READ_WRITE_TOTAL_SIZE/SIZE_1M, (uint32_t)OS_TicksToMSecs(tick_use), + throuth_mb, throuth_kb - throuth_mb); + } + + memset((void *)rbuf, 0, READ_WRITE_SINGLE_SIZE); + err = mmc_block_read(&card, rbuf, 3, READ_WRITE_SINGLE_SIZE/512); + if (err) { + goto err_out; + } else + printf("%s %d blocks read ok\n", __func__, READ_WRITE_SINGLE_SIZE/512); + +#ifdef TEST_SD_WRITE + if (memcmp((void *)wbuf, (void *)rbuf, 1024)) { /* check 1024B */ + printf("%s %d mmc blocks rw failed\n", __func__, READ_WRITE_SINGLE_SIZE/512); + goto err_out; + } else + printf("%s %d mmc blocks rw ok\n", __func__, READ_WRITE_SINGLE_SIZE/512); +#endif + + OS_MSleep(1000); + } + + mmc_test_exit(); + + return 0; + +err_out: +#ifdef TEST_SD_WRITE + printf("%s,%d mmc block rw failed\n", __func__, __LINE__); + printf("rbuf:\n"); + print_hex_dump_words(rbuf, SIZE_1K); + printf("wbuf:\n"); + print_hex_dump_words(wbuf, 512); +#endif +out: + return -1; +} +#endif /* TEST_SD */ diff --git a/platform/mcu/xr871/src/driver/chip/system_chip.c b/platform/mcu/xr871/src/driver/chip/system_chip.c new file mode 100644 index 0000000000..82045e9bd7 --- /dev/null +++ b/platform/mcu/xr871/src/driver/chip/system_chip.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "hal_base.h" +#include "driver/chip/system_chip.h" +#include "pm/pm.h" + +uint32_t SystemCoreClock; +extern const unsigned char __RAM_BASE[]; /* SRAM start address */ + +/** + * @brief Initialize the chip system, including power, FPU setting, vector + * table location, clock, etc. + * @return None + */ +void SystemInit(void) +{ +#ifdef __CONFIG_CHIP_XR871 + HAL_PRCM_SetDCDCVoltage(PRCM_DCDC_VOLT_1V51); + HAL_PRCM_SetSRAMVoltage(PRCM_SRAM_VOLT_1V10, PRCM_SRAM_VOLT_0V70); +#if 0 + /* overwite efuse values */ + HAL_MODIFY_REG(PRCM->DCDC_PARAM_CTRL, + PRCM_DCDC_BANDGAP_TRIM_MASK, + 1U << PRCM_DCDC_BANDGAP_TRIM_SHIFT); + HAL_MODIFY_REG(PRCM->DIG_LDO_PARAM, + PRCM_DIG_LDO_BANDGAP_TRIM_MASK, + 2U << PRCM_DIG_LDO_BANDGAP_TRIM_SHIFT); +#endif +#endif + + SCB->VTOR = (uint32_t)__RAM_BASE; /* Vector Table Relocation in Internal SRAM. */ + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + /* FPU settings, set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); +#endif + + /* set clock */ + HAL_BoardIoctl(HAL_BIR_CHIP_CLOCK_INIT, 0, 0); + + SystemCoreClock = HAL_GetCPUClock(); + pm_init(); + HAL_NVIC_Init(); + HAL_CCM_Init(); +} + +/** + * @brief DeInitialize the chip system by disabling and cleaning the system IRQ + * @param flag Rest system clock if bit SYSTEM_DEINIT_FLAG_RESET_CLK is set in + * the flag + * @return None + */ +void SystemDeInit(uint32_t flag) +{ + /* disable irq0~63 */ + NVIC->ICER[0] = NVIC->ISER[0]; + NVIC->ICER[1] = NVIC->ISER[1]; + + /* clear irq pending0~63 */ + NVIC->ICPR[0] = NVIC->ISPR[0]; + NVIC->ICPR[1] = NVIC->ISPR[1]; + + /* disable systick irq */ + SysTick->CTRL = 0; + + /* clear pendsv irq */ + SCB->ICSR = (SCB->ICSR & SCB_ICSR_PENDSVSET_Msk) >> (SCB_ICSR_PENDSVSET_Pos - SCB_ICSR_PENDSVCLR_Pos); + + /* clear systick irq */ + SCB->ICSR = (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> (SCB_ICSR_PENDSTSET_Pos - SCB_ICSR_PENDSTCLR_Pos); + + if (flag & SYSTEM_DEINIT_FLAG_RESET_CLK) { + /* reset clock for restart */ + HAL_PRCM_SetCPUAClk(PRCM_CPU_CLK_SRC_HFCLK, PRCM_SYS_CLK_FACTOR_80M); + HAL_PRCM_DisCLK1(PRCM_SYS_CLK_FACTOR_80M); + HAL_CCM_BusSetClock(CCM_AHB2_CLK_DIV_1, CCM_APB_CLK_SRC_HFCLK, CCM_APB_CLK_DIV_2); + HAL_PRCM_DisableSysPLL(); + } +} + +/** + * @brief Update system core (cpu) clock + * @return None + */ +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = HAL_GetCPUClock(); +} diff --git a/platform/mcu/xr871/src/efpg/efpg.c b/platform/mcu/xr871/src/efpg/efpg.c new file mode 100644 index 0000000000..9452144d63 --- /dev/null +++ b/platform/mcu/xr871/src/efpg/efpg.c @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "efpg_i.h" +#include "efpg_debug.h" +#include "efpg/efpg.h" +#include "driver/chip/hal_uart.h" +#include "driver/chip/hal_efuse.h" + +static void efpg_task(void *arg) +{ + uint8_t *buf; + int32_t recv_len; + efpg_priv_t *efpg = arg; + efpg_state_t state = EFPG_STATE_NUM; + + if (efpg->start_cb) + efpg->start_cb(); + +efpg_reset: + efpg->is_cmd = 1; + efpg->ext_cmd = EFPG_NORMAL_CMD; + efpg->expt_len = EFPG_CMD_FRAME_LEN; + efpg->recv_len = 0; + efpg->op = EFPG_OP_NUM; + efpg->field = EFPG_FIELD_NUM; + efpg->start_bit_addr = 0; + efpg->bit_length = 0; + + while (1) { +efpg_continue: + if (efpg->is_cmd) + if (efpg->ext_cmd == EFPG_EXT_CMD) + buf = efpg->ext_cmd_frame; + else + buf = efpg->cmd_frame; + else + buf = efpg->data_frame; + recv_len = 0; + while (recv_len == 0) { + recv_len = HAL_UART_Receive_IT(efpg->uart_id, buf, efpg->expt_len, EFPG_RECV_TIMEOUT_MS); + } + + if (recv_len == -1) { + EFPG_ERR("UART receive failed\n"); + goto efpg_stop; + } + + if ((uint16_t)recv_len != efpg->expt_len) { + EFPG_WARN("%s(), %d, recv len %d, expt len %d\n", + __func__, __LINE__, recv_len, efpg->expt_len); + goto efpg_reset; + } + + efpg->recv_len = (uint16_t)recv_len; + + if (efpg->is_cmd) + state = efpg_cmd_frame_process(efpg); + else + state = efpg_data_frame_process(efpg); + + switch (state) { + case EFPG_STATE_CONTINUE: + goto efpg_continue; + case EFPG_STATE_RESET: + goto efpg_reset; + case EFPG_STATE_STOP: + goto efpg_stop; + default: + EFPG_ERR("invalid state %d\n", state); + goto efpg_stop; + } + } + +efpg_stop: + if (efpg->stop_cb) + efpg->stop_cb(); + + if (efpg) + efpg_free(efpg); + + OS_ThreadDelete(NULL); +} + +/** + * @brief Start communicating with the OEM programming tool + * @param[in] key Pointer to the key + * @param[in] key_len The length of the key + * @param[in] uart_id ID of the specified UART used to communication + * @param[in] start_cb Function called when start communication + * @param[in] stop_cb Function called when stop communication + * @return 0 on success, -1 on failure + * + * @note Just for OEM programming tool to entry eFuse programming mode. + */ +int efpg_start(uint8_t *key, uint8_t key_len, UART_ID uart_id, efpg_cb_t start_cb, efpg_cb_t stop_cb) +{ + efpg_priv_t *efpg; + OS_Thread_t thread; + + if ((key == NULL) || (key_len == 0) || (key_len > EFPG_KEY_LEN_MAX) || (uart_id == UART_NUM)) { + EFPG_ERR("key %p, key len %d, uart id %d\n", key, key_len, uart_id); + return -1; + } + + efpg = efpg_malloc(sizeof(efpg_priv_t)); + if (efpg == NULL) { + EFPG_ERR("malloc failed\n"); + return -1; + } + + efpg->uart_id = uart_id; + efpg->start_cb = start_cb; + efpg->stop_cb = stop_cb; + + efpg_memcpy(efpg->key, key, key_len); + efpg->key_len = key_len; + + OS_ThreadSetInvalid(&thread); + if (OS_ThreadCreate(&thread, + "efpg task", + efpg_task, + efpg, + OS_THREAD_PRIO_CONSOLE, + EFPG_THREAD_STACK_SIZE) != OS_OK) { + EFPG_ERR("create efpg task failed\n"); + return -1; + } + + return 0; +} + +/** + * @brief Read data of the specified field in eFuse + * @param[in] field The filed in eFuse + * @param[in] data Pointer to the data buffer + * @return 0 on success, -1 on failure + * + * @note The rest bit(s) in data will be cleared to be 0. + */ +int efpg_read(efpg_field_t field, uint8_t *data) +{ + if (data == NULL) { + EFPG_ERR("data %p\n", data); + return -1; + } + + uint16_t ack = efpg_read_field(field, data, 0, 0); + if (ack != EFPG_ACK_OK) { + EFPG_WARN("%s(), %d, ack %d\n", __func__, __LINE__, ack); + return -1; + } + + return 0; +} + +/** + * @brief Read data from user area (OEM reserved field) on EFUSE + * @param[in] start The first bit to be read in user area (OEM reserved field) + * @param[in] num Number of bits to be read + * @param[in] data Pointer to the data buffer + * @return 0 on success, -1 on failure + * + * @note The rest bit(s) in data will be cleared to be 0. + */ +int efpg_read_ua(uint32_t start, uint32_t num, uint8_t *data) +{ + if (efpg_read_field(EFPG_FIELD_UA, data, start, num) != EFPG_ACK_OK) { + return -1; + } + return 0; +} + diff --git a/platform/mcu/xr871/src/efpg/efpg.mk b/platform/mcu/xr871/src/efpg/efpg.mk new file mode 100644 index 0000000000..c405c6bdb1 --- /dev/null +++ b/platform/mcu/xr871/src/efpg/efpg.mk @@ -0,0 +1,6 @@ +NAME := efpg + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := efpg_efuse.c \ + efpg.c + diff --git a/platform/mcu/xr871/src/efpg/efpg_debug.h b/platform/mcu/xr871/src/efpg/efpg_debug.h new file mode 100644 index 0000000000..9bf939a0c9 --- /dev/null +++ b/platform/mcu/xr871/src/efpg/efpg_debug.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EFPG_DEBUG_H_ +#define _EFPG_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFPG_DBG_ON 0 +#define EFPG_WARN_ON 0 +#define EFPG_ERR_ON 1 +#define EFPG_ABORT_ON 0 + +#define EFPG_SYSLOG printf +#define EFPG_ABORT() sys_abort() + +#define EFPG_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + EFPG_SYSLOG(fmt, ##arg); \ + } while (0) + +#define EFPG_DBG(fmt, arg...) EFPG_LOG(EFPG_DBG_ON, "[efpg] "fmt, ##arg) +#define EFPG_WARN(fmt, arg...) EFPG_LOG(EFPG_WARN_ON, "[efpg WARN] "fmt, ##arg) +#define EFPG_ERR(fmt, arg...) \ + do { \ + EFPG_LOG(EFPG_ERR_ON, "[efpg ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (EFPG_ABORT_ON) \ + EFPG_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _EFPG_DEBUG_H_ */ \ No newline at end of file diff --git a/platform/mcu/xr871/src/efpg/efpg_efuse.c b/platform/mcu/xr871/src/efpg/efpg_efuse.c new file mode 100644 index 0000000000..394695f4be --- /dev/null +++ b/platform/mcu/xr871/src/efpg/efpg_efuse.c @@ -0,0 +1,532 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "efpg_i.h" +#include "efpg_debug.h" +#include "driver/chip/hal_efuse.h" + +static int efpg_boot_hash_cmp(const uint8_t *data, const uint8_t *buf, uint8_t *err_cnt, + uint8_t *err_1st_no, uint8_t *err_2nd_no) +{ + uint8_t byte_cnt; + uint8_t bit_cnt; + + if (efpg_memcmp(data, buf, EFPG_BOOT_BUF_LEN) == 0) + return 0; + + *err_cnt = 0; + for (byte_cnt = 0; byte_cnt < EFPG_BOOT_BUF_LEN; byte_cnt++) { + if (data[byte_cnt] == buf[byte_cnt]) + continue; + + for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) { + if ((data[byte_cnt] & (0x1 << bit_cnt)) == (buf[byte_cnt] & (0x1 << bit_cnt))) + continue; + + if (*err_cnt == 0) { + *err_1st_no = (byte_cnt << 3) + bit_cnt; + *err_cnt = 1; + } else if (*err_cnt == 1) { + *err_2nd_no = (byte_cnt << 3) + bit_cnt; + *err_cnt = 2; + } else { + return -1; + } + } + } + + return 0; +} + +static uint16_t efpg_read_hosc(uint8_t *data) +{ + if (HAL_EFUSE_Read(EFPG_HOSC_TYPE_START, EFPG_HOSC_TYPE_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + + return EFPG_ACK_OK; +} + +static uint16_t efpg_read_boot(uint8_t *data) +{ + uint8_t tmp = 0; + uint8_t byte_cnt; + uint8_t bit_cnt; + + /* flag */ + if (HAL_EFUSE_Read(EFPG_BOOT_FLAG_START, EFPG_BOOT_FLAG_NUM, &tmp) != HAL_OK) + return EFPG_ACK_RW_ERR; + + if (tmp == 0) { + EFPG_WARN("%s(), %d, boot flag 0\n", __func__, __LINE__); + return EFPG_ACK_NODATA_ERR; + } + + /* hash */ + if (HAL_EFUSE_Read(EFPG_BOOT_HASH_START, EFPG_BOOT_HASH_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + + /* correct bit error */ + if (HAL_EFUSE_Read(EFPG_BOOT_1ST_EN_START, EFPG_BOOT_1ST_EN_NUM, &tmp) != HAL_OK) + return EFPG_ACK_RW_ERR; + + if (tmp != 0) { + if (HAL_EFUSE_Read(EFPG_BOOT_1ST_NO_START, EFPG_BOOT_1ST_NO_NUM, &tmp) != HAL_OK) + return EFPG_ACK_RW_ERR; + byte_cnt = tmp >> 3; + bit_cnt = tmp & 0x07; + data[byte_cnt] ^= (0x1 << bit_cnt); + + if (HAL_EFUSE_Read(EFPG_BOOT_2ND_EN_START, EFPG_BOOT_2ND_EN_NUM, &tmp) != HAL_OK) + return EFPG_ACK_RW_ERR; + + if (tmp != 0) { + if (HAL_EFUSE_Read(EFPG_BOOT_2ND_NO_START, EFPG_BOOT_2ND_NO_NUM, &tmp) != HAL_OK) + return EFPG_ACK_RW_ERR; + byte_cnt = tmp >> 3; + bit_cnt = tmp & 0x07; + data[byte_cnt] ^= (0x1 << bit_cnt); + } + } + + return EFPG_ACK_OK; +} + +static uint16_t efpg_read_dcxo(uint8_t *data) +{ + uint8_t idx = 1; + uint8_t flag = 0; + uint32_t start_bit; + + /* flag */ + if (HAL_EFUSE_Read(EFPG_DCXO_FLAG_START, EFPG_DCXO_FLAG_NUM, &flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + if (flag == 0) { + EFPG_WARN("%s(), %d, dcxo flag 0\n", __func__, __LINE__); + return EFPG_ACK_NODATA_ERR; + } + + while ((flag & 0x3) == 0) { + flag = flag >> 2; + idx++; + } + + /* DCXO TRIM */ + start_bit = EFPG_DCXO_TRIM_START + (idx - 1) * EFPG_DCXO_TRIM_NUM; + if (HAL_EFUSE_Read(start_bit, EFPG_DCXO_TRIM_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + + return EFPG_ACK_OK; +} + +static uint16_t efpg_read_pout(uint8_t *data) +{ + uint8_t idx = 1; + uint8_t flag = 0; + uint32_t start_bit; + + /* flag */ + if (HAL_EFUSE_Read(EFPG_POUT_FLAG_START, EFPG_POUT_FLAG_NUM, &flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + if (flag == 0) { + EFPG_WARN("%s(), %d, pout flag 0\n", __func__, __LINE__); + return EFPG_ACK_NODATA_ERR; + } + + while ((flag & 0x3) == 0) { + flag = flag >> 2; + idx++; + } + + /* POUT CAL */ + start_bit = EFPG_POUT_CAL_START + (idx - 1) * EFPG_POUT_CAL_NUM; + if (HAL_EFUSE_Read(start_bit, EFPG_POUT_CAL_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + + return EFPG_ACK_OK; +} + +static uint16_t efpg_read_mac(uint8_t *data) +{ + uint8_t idx = 1; + uint32_t flag = 0; + uint32_t start_bit; + + /* flag */ + if (HAL_EFUSE_Read(EFPG_MAC_FLAG_START, EFPG_MAC_FLAG_NUM, (uint8_t *)&flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + if (flag == 0) { + EFPG_WARN("%s(), %d, mac flag 0\n", __func__, __LINE__); + return EFPG_ACK_NODATA_ERR; + } + + while ((flag & 0x3) == 0) { + flag = flag >> 2; + idx++; + } + + /* MAC */ + start_bit = EFPG_MAC_ADDR_START + (idx - 1) * EFPG_MAC_ADDR_NUM; + if (HAL_EFUSE_Read(start_bit, EFPG_MAC_ADDR_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + + return EFPG_ACK_OK; +} + +static uint16_t efpg_read_chipid(uint8_t *data) +{ + uint8_t flag = 0; + + /* flag */ + if (HAL_EFUSE_Read(EFPG_CHIPID_FLAG_START, EFPG_CHIPID_FLAG_NUM, &flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + /* chipid */ + if (flag == 0) { + if (HAL_EFUSE_Read(EFPG_CHIPID_1ST_START, EFPG_CHIPID_1ST_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + } else { + if (HAL_EFUSE_Read(EFPG_CHIPID_2ND_START, EFPG_CHIPID_2ND_NUM, data) != HAL_OK) + return EFPG_ACK_RW_ERR; + } + + return EFPG_ACK_OK; +} + +static uint16_t efpg_read_user_area(uint16_t start, uint16_t num, uint8_t *data) +{ + if ((start >= EFPG_USER_AREA_NUM) + || (num == 0) + || (num > EFPG_USER_AREA_NUM) + || (start + num > EFPG_USER_AREA_NUM)) { + EFPG_ERR("start %d, num %d\n", start, num); + return EFPG_ACK_RW_ERR; + } + + if (HAL_EFUSE_Read(start + EFPG_USER_AREA_START, num, data) != HAL_OK) { + EFPG_ERR("eFuse read failed\n"); + return EFPG_ACK_RW_ERR; + } + + return EFPG_ACK_OK; +} + +static uint16_t efpg_write_hosc(uint8_t *data) +{ + uint8_t buf[EFPG_HOSC_BUF_LEN] = {0}; + + if ((HAL_EFUSE_Write(EFPG_HOSC_TYPE_START, EFPG_HOSC_TYPE_NUM, data) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_HOSC_TYPE_START, EFPG_HOSC_TYPE_NUM, buf) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (efpg_memcmp(data, buf, EFPG_HOSC_BUF_LEN)) { + EFPG_WARN("%s(), %d, hosc: write %#04x, read %#04x\n", + __func__, __LINE__, data[0], buf[0]); + return EFPG_ACK_DI_ERR; + } + + return EFPG_ACK_OK; +} + +static uint16_t efpg_write_boot(uint8_t *data) +{ + uint8_t tmp; + uint8_t err_cnt = 0; + uint8_t err_1st_no = 0; + uint8_t err_2nd_no = 0; + uint8_t buf[EFPG_BOOT_BUF_LEN] = {0}; + + /* flag */ + tmp = 0x03; + if ((HAL_EFUSE_Write(EFPG_BOOT_FLAG_START, EFPG_BOOT_FLAG_NUM, &tmp) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_BOOT_FLAG_START, EFPG_BOOT_FLAG_NUM, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (tmp == 0) { + EFPG_WARN("%s(), %d, boot flag 0\n", __func__, __LINE__); + return EFPG_ACK_DI_ERR; + } + + /* hash */ + if ((HAL_EFUSE_Write(EFPG_BOOT_HASH_START, EFPG_BOOT_HASH_NUM, data) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_BOOT_HASH_START, EFPG_BOOT_HASH_NUM, buf) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (efpg_boot_hash_cmp(data, buf, &err_cnt, &err_1st_no, &err_2nd_no) < 0) { + EFPG_WARN("%s(), %d, boot hash: compare failed\n", __func__, __LINE__); + return EFPG_ACK_DI_ERR; + } + + /* error bit */ + if (err_cnt > 0) { + /* bit en */ + tmp = 0x01; + if ((HAL_EFUSE_Write(EFPG_BOOT_1ST_EN_START, EFPG_BOOT_1ST_EN_NUM, &tmp) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_BOOT_1ST_EN_START, EFPG_BOOT_1ST_EN_NUM, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (tmp != 0x01) { + EFPG_WARN("%s(), %d, boot 1st en %d\n", __func__, __LINE__, tmp); + return EFPG_ACK_DI_ERR; + } + + /* bit no */ + if ((HAL_EFUSE_Write(EFPG_BOOT_1ST_NO_START, EFPG_BOOT_1ST_NO_NUM, &err_1st_no) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_BOOT_1ST_NO_START, EFPG_BOOT_1ST_NO_NUM, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (err_1st_no != tmp) { + EFPG_WARN("%s(), %d, boot 1st no: write %d, read %d\n", + __func__, __LINE__, err_1st_no, tmp); + return EFPG_ACK_DI_ERR; + } + + if (err_cnt == 2) { + /* bit en */ + tmp = 0x01; + if ((HAL_EFUSE_Write(EFPG_BOOT_2ND_EN_START, EFPG_BOOT_2ND_EN_NUM, &tmp) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_BOOT_2ND_EN_START, EFPG_BOOT_2ND_EN_NUM, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (tmp != 0x01) { + EFPG_WARN("%s(), %d, boot 2nd en %d\n", __func__, __LINE__, tmp); + return EFPG_ACK_DI_ERR; + } + + /* bit no */ + if ((HAL_EFUSE_Write(EFPG_BOOT_2ND_NO_START, EFPG_BOOT_2ND_NO_NUM, &err_2nd_no) != HAL_OK) + || (HAL_EFUSE_Read(EFPG_BOOT_2ND_NO_START, EFPG_BOOT_2ND_NO_NUM, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (err_2nd_no != tmp) { + EFPG_WARN("%s(), %d, boot 2nd no: write %d, read %d\n", + __func__, __LINE__, err_2nd_no, tmp); + return EFPG_ACK_DI_ERR; + } + } + } + + return EFPG_ACK_OK; +} + +static uint16_t efpg_write_dcxo(uint8_t *data) +{ + uint8_t tmp; + uint8_t idx = 0; + uint8_t flag = 0; + uint8_t buf[EFPG_DCXO_BUF_LEN] = {0}; + uint32_t start_bit; + + if (HAL_EFUSE_Read(EFPG_DCXO_FLAG_START, EFPG_DCXO_FLAG_NUM, &flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + while (((flag & 0x3) == 0) && (idx < EFPG_DCXO_IDX_MAX)) { + flag = flag >> 2; + idx++; + } + + while (idx > 0) { + tmp = 0x3; + start_bit = EFPG_DCXO_FLAG_START + (idx - 1) * 2; + if ((HAL_EFUSE_Write(start_bit, 2, &tmp) != HAL_OK) + || (HAL_EFUSE_Read(start_bit, 2, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (tmp == 0) { + idx--; + continue; + } + + start_bit = EFPG_DCXO_TRIM_START + (idx - 1) * EFPG_DCXO_TRIM_NUM; + if ((HAL_EFUSE_Write(start_bit, EFPG_DCXO_TRIM_NUM, data) != HAL_OK) + || (HAL_EFUSE_Read(start_bit, EFPG_DCXO_TRIM_NUM, buf) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (efpg_memcmp(data, buf, EFPG_DCXO_BUF_LEN)) { + idx--; + continue; + } + + return EFPG_ACK_OK; + } + + return EFPG_ACK_DI_ERR; +} + +static uint16_t efpg_write_pout(uint8_t *data) +{ + uint8_t tmp; + uint8_t idx = 0; + uint8_t flag = 0; + uint8_t buf[EFPG_POUT_BUF_LEN] = {0}; + uint32_t start_bit; + + if (HAL_EFUSE_Read(EFPG_POUT_FLAG_START, EFPG_POUT_FLAG_NUM, &flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + while (((flag & 0x3) == 0) && (idx < EFPG_POUT_IDX_MAX)) { + flag = flag >> 2; + idx++; + } + + while (idx > 0) { + tmp = 0x3; + start_bit = EFPG_POUT_FLAG_START + (idx - 1) * 2; + if ((HAL_EFUSE_Write(start_bit, 2, &tmp) != HAL_OK) + || (HAL_EFUSE_Read(start_bit, 2, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (tmp == 0) { + idx--; + continue; + } + + start_bit = EFPG_POUT_CAL_START + (idx - 1) * EFPG_POUT_CAL_NUM; + if ((HAL_EFUSE_Write(start_bit, EFPG_POUT_CAL_NUM, data) != HAL_OK) + || (HAL_EFUSE_Read(start_bit, EFPG_POUT_CAL_NUM, buf) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (efpg_memcmp(data, buf, EFPG_POUT_BUF_LEN)) { + idx--; + continue; + } + + return EFPG_ACK_OK; + } + + return EFPG_ACK_DI_ERR; +} + +static uint16_t efpg_write_mac(uint8_t *data) +{ + uint8_t tmp; + uint8_t idx = 0; + uint32_t flag = 0; + uint8_t buf[EFPG_MAC_BUF_LEN] = {0}; + uint32_t start_bit; + + if (HAL_EFUSE_Read(EFPG_MAC_FLAG_START, EFPG_MAC_FLAG_NUM, (uint8_t *)&flag) != HAL_OK) + return EFPG_ACK_RW_ERR; + + while (((flag & 0x3) == 0) && (idx < EFPG_MAC_IDX_MAX)) { + flag = flag >> 2; + idx++; + } + + while (idx > 0) { + tmp = 0x3; + start_bit = EFPG_MAC_FLAG_START + (idx - 1) * 2; + if ((HAL_EFUSE_Write(start_bit, 2, &tmp) != HAL_OK) + || (HAL_EFUSE_Read(start_bit, 2, &tmp) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (tmp == 0) { + idx--; + continue; + } + + start_bit = EFPG_MAC_ADDR_START + (idx - 1) * EFPG_MAC_ADDR_NUM; + if ((HAL_EFUSE_Write(start_bit, EFPG_MAC_ADDR_NUM, data) != HAL_OK) + || (HAL_EFUSE_Read(start_bit, EFPG_MAC_ADDR_NUM, buf) != HAL_OK)) + return EFPG_ACK_RW_ERR; + + if (efpg_memcmp(data, buf, EFPG_MAC_BUF_LEN)) { + idx--; + continue; + } + + return EFPG_ACK_OK; + } + + return EFPG_ACK_DI_ERR; +} + +static uint16_t efpg_write_user_area(uint16_t start, uint16_t num, uint8_t *data) +{ + if ((start >= EFPG_USER_AREA_NUM) + || (num == 0) + || (num > EFPG_USER_AREA_NUM) + || (start + num > EFPG_USER_AREA_NUM)) { + EFPG_ERR("start %d, num %d\n", start, num); + return EFPG_ACK_RW_ERR; + } + + if (HAL_EFUSE_Write(start + EFPG_USER_AREA_START, num, data) != HAL_OK) { + EFPG_ERR("eFuse write failed\n"); + return EFPG_ACK_RW_ERR; + } + + return EFPG_ACK_OK; +} + +uint16_t efpg_read_field(efpg_field_t field, uint8_t *data, uint16_t start_bit_addr, uint16_t bit_len) +{ + switch (field) { + case EFPG_FIELD_HOSC: + return efpg_read_hosc(data); + case EFPG_FIELD_BOOT: + return efpg_read_boot(data); + case EFPG_FIELD_DCXO: + return efpg_read_dcxo(data); + case EFPG_FIELD_POUT: + return efpg_read_pout(data); + case EFPG_FIELD_MAC: + return efpg_read_mac(data); + case EFPG_FIELD_CHIPID: + return efpg_read_chipid(data); + case EFPG_FIELD_UA: + return efpg_read_user_area(start_bit_addr, bit_len, data); + default: + EFPG_WARN("%s(), %d, read field %d\n", __func__, __LINE__, field); + return EFPG_ACK_RW_ERR; + } +} + +uint16_t efpg_write_field(efpg_field_t field, uint8_t *data, uint16_t start_bit_addr, uint16_t bit_len) +{ + switch (field) { + case EFPG_FIELD_HOSC: + return efpg_write_hosc(data); + case EFPG_FIELD_BOOT: + return efpg_write_boot(data); + case EFPG_FIELD_DCXO: + return efpg_write_dcxo(data); + case EFPG_FIELD_POUT: + return efpg_write_pout(data); + case EFPG_FIELD_MAC: + return efpg_write_mac(data); + case EFPG_FIELD_UA: + return efpg_write_user_area(start_bit_addr, bit_len, data); + default: + EFPG_WARN("%s(), %d, write field %d\n", __func__, __LINE__, field); + return EFPG_ACK_RW_ERR; + } +} diff --git a/platform/mcu/xr871/src/efpg/efpg_frame.c b/platform/mcu/xr871/src/efpg/efpg_frame.c new file mode 100644 index 0000000000..51a0c42bb3 --- /dev/null +++ b/platform/mcu/xr871/src/efpg/efpg_frame.c @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "efpg_i.h" +#include "efpg_debug.h" +#include "driver/chip/hal_uart.h" +#include "driver/chip/hal_crypto.h" + +static uint8_t efpg_checksum8(uint8_t *data, uint32_t len) +{ + uint8_t cs = 0; + + while (len > 0) { + cs += *data++; + len--; + } + + return cs; +} + +static int efpg_check_msg_dgst(efpg_priv_t *efpg) +{ + CE_SHA256_Handler hdl; + uint8_t msg_dgst_cal[EFPG_MSG_DGST_LEN]; + uint8_t *msg_dgst = efpg->data_frame + efpg->recv_len - EFPG_MSG_DGST_LEN; + + if ((HAL_SHA256_Init(&hdl, CE_CTL_IVMODE_SHA_MD5_FIPS180, NULL) != HAL_OK) + || (HAL_SHA256_Append(&hdl, efpg->cmd_frame, EFPG_CMD_FRAME_LEN) != HAL_OK) + || (HAL_SHA256_Append(&hdl, efpg->data_frame, efpg->recv_len - EFPG_MSG_DGST_LEN) != HAL_OK) + || (HAL_SHA256_Append(&hdl, efpg->key, efpg->key_len) != HAL_OK) + || (HAL_SHA256_Finish(&hdl, (uint32_t *)msg_dgst_cal) != HAL_OK)) { + EFPG_ERR("failed to calculate msg dgst\n"); + return -1; + } + + if (efpg_memcmp(msg_dgst, msg_dgst_cal, EFPG_MSG_DGST_LEN)) { + EFPG_WARN("%s(), %d, check msg dgst failed\n", __func__, __LINE__); + return -1; + } + + return 0; +} + +static int efpg_send_ack(efpg_priv_t *efpg, uint16_t status) +{ + uint8_t cs; + int32_t send_len; + + uint8_t *ack_frame = efpg_malloc(EFPG_ACK_FRAME_LEN); + if (ack_frame == NULL) { + EFPG_ERR("malloc failed\n"); + return -1; + } + + efpg_memset(ack_frame, 0, EFPG_ACK_FRAME_LEN); + efpg_memcpy(ack_frame, &status, 2); + cs = 0xFF - efpg_checksum8(ack_frame, EFPG_ACK_FRAME_LEN); + efpg_memcpy(ack_frame + 3, &cs, sizeof(cs)); + + send_len = HAL_UART_Transmit_Poll(efpg->uart_id, ack_frame, EFPG_ACK_FRAME_LEN); + efpg_free(ack_frame); + + if (send_len != EFPG_ACK_FRAME_LEN) { + EFPG_WARN("%s(), %d, send len %d\n", __func__, __LINE__, send_len); + return -1; + } else { + return 0; + } +} + +static int efpg_parse_cmd(efpg_priv_t *efpg) +{ + uint16_t op_code; + uint16_t type; + uint16_t len; + uint8_t *p; + uint8_t extCmd; + + if (efpg->ext_cmd == EFPG_EXT_CMD) + p = efpg->ext_cmd_frame; + else + p = efpg->cmd_frame; + + op_code = *((uint16_t *)p); + p += 2; + type = *((uint16_t *)p); + p += 2; + len = *((uint16_t *)p); + + switch (op_code) { + case EFPG_OP_CODE_READ: + efpg->op = EFPG_OP_READ; + break; + case EFPG_OP_CODE_WRITE: + efpg->op = EFPG_OP_WRITE; + break; + case EFPG_OP_CODE_EXIT: + efpg->op = EFPG_OP_EXIT; + return 0; + default: + EFPG_WARN("%s(), %d, op_code %#06x\n", __func__, __LINE__, op_code); + return -1; + } + + switch (type) { + case EFPG_TYPE_HOSC: + efpg->field = EFPG_FIELD_HOSC; + efpg->expt_len = EFPG_HOSC_FRAME_LEN; + break; + case EFPG_TYPE_BOOT: + efpg->field = EFPG_FIELD_BOOT; + efpg->expt_len = EFPG_BOOT_FRAME_LEN; + break; + case EFPG_TYPE_DCXO: + efpg->field = EFPG_FIELD_DCXO; + efpg->expt_len = EFPG_DCXO_FRAME_LEN; + break; + case EFPG_TYPE_POUT: + efpg->field = EFPG_FIELD_POUT; + efpg->expt_len = EFPG_POUT_FRAME_LEN; + break; + case EFPG_TYPE_MAC: + efpg->field = EFPG_FIELD_MAC; + efpg->expt_len = EFPG_MAC_FRAME_LEN; + break; + case EFPG_TYPE_USER_AREA: + if (efpg->ext_cmd == EFPG_NORMAL_CMD) { + p += 2; + extCmd = *p; + if (extCmd != EFPG_EXT_CMD) { + EFPG_WARN("%s(), %d, extCmd %d, expt extCmd 0\n", + __func__, __LINE__, extCmd); + return -1; + } + efpg->ext_cmd = EFPG_EXT_CMD; + efpg->field = EFPG_FIELD_UA; + efpg->expt_len = EFPG_UAER_AREA_EXT_LEN; + } + else { + p += 2; + efpg->protocol_version = *((uint16_t *)p); + p += 2; + efpg->start_bit_addr= *((uint16_t *)p); + p += 2; + efpg->bit_length = *((uint16_t *)p); + efpg->ext_cmd = EFPG_NORMAL_CMD; + efpg->field = EFPG_FIELD_UA; + efpg->expt_len = efpg->bit_length / 8 + EFPG_MSG_DGST_LEN; + if (efpg->bit_length % 8) + efpg->expt_len ++; + len = efpg->expt_len; + } + break; + default: + EFPG_WARN("%s(), %d, type %#06x\n", __func__, __LINE__, type); + return -1; + } + + if (len != efpg->expt_len) { + EFPG_WARN("%s(), %d, len %d, expt len %d\n", + __func__, __LINE__, len, efpg->expt_len); + return -1; + } + + return 0; +} + +static efpg_state_t efpg_ext_cmd_process(efpg_priv_t *efpg) +{ + efpg->is_cmd = 1; + efpg->recv_len = 0; + + if (efpg_send_ack(efpg, EFPG_ACK_OK) < 0) { + EFPG_WARN("%s(), %d, send ack failed\n", __func__, __LINE__); + return EFPG_STATE_RESET; + } + + return EFPG_STATE_CONTINUE; +} + +static efpg_state_t efpg_read_process(efpg_priv_t *efpg) +{ + uint16_t status; + uint8_t *data; + uint8_t *msg_dgst; + int32_t send_len; + CE_SHA256_Handler hdl; + + uint8_t *frame = efpg_malloc(efpg->expt_len); + if (frame == NULL) { + EFPG_ERR("malloc failed\n"); + return EFPG_STATE_RESET; + } + + efpg_memset(frame, 0, efpg->expt_len); + data = frame; + msg_dgst = frame + efpg->expt_len - EFPG_MSG_DGST_LEN; + + status = efpg_read_field(efpg->field, data, efpg->start_bit_addr, efpg->bit_length); + if ((HAL_SHA256_Init(&hdl, CE_CTL_IVMODE_SHA_MD5_FIPS180, NULL) != HAL_OK) + || (HAL_SHA256_Append(&hdl, efpg->cmd_frame, EFPG_CMD_FRAME_LEN) != HAL_OK) + || (HAL_SHA256_Append(&hdl, data, efpg->expt_len - EFPG_MSG_DGST_LEN) != HAL_OK) + || (HAL_SHA256_Append(&hdl, efpg->key, efpg->key_len) != HAL_OK) + || (HAL_SHA256_Finish(&hdl, (uint32_t *)msg_dgst) != HAL_OK)) { + EFPG_WARN("%s(), %d, SHA256 failed\n", __func__, __LINE__); + status = EFPG_ACK_RW_ERR; + } + + if (status != EFPG_ACK_OK) { + EFPG_WARN("%s(), %d, status %d\n", __func__, __LINE__, status); + efpg_free(frame); + efpg_send_ack(efpg, status); + return EFPG_STATE_RESET; + } + + if (efpg_send_ack(efpg, EFPG_ACK_OK) < 0) { + EFPG_WARN("%s(), %d, send ack failed\n", __func__, __LINE__); + efpg_free(frame); + return EFPG_STATE_RESET; + } + + send_len = HAL_UART_Transmit_Poll(efpg->uart_id, frame, efpg->expt_len); + if (send_len != efpg->expt_len) + EFPG_WARN("%s(), %d, send len %d, expt %d\n", + __func__, __LINE__, send_len, efpg->expt_len); + + efpg_free(frame); + return EFPG_STATE_RESET; +} + +static efpg_state_t efpg_write_process(efpg_priv_t *efpg) +{ + efpg->is_cmd = 0; + efpg->recv_len = 0; + + if (efpg_send_ack(efpg, EFPG_ACK_OK) < 0) { + EFPG_WARN("%s(), %d, send ack failed\n", __func__, __LINE__); + return EFPG_STATE_RESET; + } + + return EFPG_STATE_CONTINUE; +} + +static efpg_state_t efpg_stop_process(efpg_priv_t *efpg) +{ + if (efpg_send_ack(efpg, EFPG_ACK_OK) < 0) { + EFPG_WARN("%s(), %d, send ack failed\n", __func__, __LINE__); + return EFPG_STATE_RESET; + } else { + return EFPG_STATE_STOP; + } +} + +efpg_state_t efpg_cmd_frame_process(efpg_priv_t *efpg) +{ + uint8_t * pFrame; + if (efpg->ext_cmd == EFPG_EXT_CMD) + pFrame = efpg->ext_cmd_frame; + else + pFrame = efpg->cmd_frame; + + /* checksum */ + if (efpg_checksum8(pFrame, efpg->recv_len) != 0xFF) { + EFPG_WARN("%s(), %d, checksum failed\n", __func__, __LINE__); + efpg_send_ack(efpg, EFPG_ACK_CS_ERR); + return EFPG_STATE_RESET; + } + + /* parse frame */ + if (efpg_parse_cmd(efpg) < 0) { + EFPG_WARN("%s(), %d, parse cmd failed\n", __func__, __LINE__); + efpg_send_ack(efpg, EFPG_ACK_PARSE_ERR); + return EFPG_STATE_RESET; + } + + /* check ext cmd */ + if (efpg->ext_cmd == EFPG_EXT_CMD) { + return efpg_ext_cmd_process(efpg); + } + + switch (efpg->op) { + case EFPG_OP_READ: + return efpg_read_process(efpg); + case EFPG_OP_WRITE: + return efpg_write_process(efpg); + case EFPG_OP_EXIT: + return efpg_stop_process(efpg); + default: + EFPG_ERR("invalid op %d\n", efpg->op); + return EFPG_STATE_STOP; + } +} + +efpg_state_t efpg_data_frame_process(efpg_priv_t *efpg) +{ + uint16_t status; + uint8_t *data; + + /* message digest */ + if (efpg_check_msg_dgst(efpg) < 0) { + EFPG_WARN("%s(), %d, check msg dgst failed\n", __func__, __LINE__); + efpg_send_ack(efpg, EFPG_ACK_MD_ERR); + return EFPG_STATE_RESET; + } + + /* write data */ + data = efpg->data_frame; + status = efpg_write_field(efpg->field, data, efpg->start_bit_addr, efpg->bit_length); + EFPG_DBG("%s(), %d, write field status %d\n", __func__, __LINE__, status); + + efpg_send_ack(efpg, status); + return EFPG_STATE_RESET; +} + diff --git a/platform/mcu/xr871/src/efpg/efpg_i.h b/platform/mcu/xr871/src/efpg/efpg_i.h new file mode 100644 index 0000000000..ab2518e4b5 --- /dev/null +++ b/platform/mcu/xr871/src/efpg/efpg_i.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EFPG_I_H_ +#define _EFPG_I_H_ + +#include +#include +#include "efpg/efpg.h" +#include "kernel/os/os.h" +#include "driver/chip/hal_uart.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFPG_KEY_LEN_MAX (64) +#define EFPG_RECV_TIMEOUT_MS (3000) +#define EFPG_THREAD_STACK_SIZE (3 * 1024) + +#define EFPG_CMD_FRAME_LEN (8) +#define EFPG_ACK_FRAME_LEN (4) +#define EFPG_MSG_DGST_LEN (32) +#define EFPG_DATA_FRAME_LEN_MAX ((76) + EFPG_MSG_DGST_LEN) +#define EFPG_HOSC_FRAME_LEN ((1) + EFPG_MSG_DGST_LEN) +#define EFPG_BOOT_FRAME_LEN ((32) + EFPG_MSG_DGST_LEN) +#define EFPG_DCXO_FRAME_LEN ((1) + EFPG_MSG_DGST_LEN) +#define EFPG_POUT_FRAME_LEN ((3) + EFPG_MSG_DGST_LEN) +#define EFPG_MAC_FRAME_LEN ((6) + EFPG_MSG_DGST_LEN) +#define EFPG_UA_FRAME_LEN ((76) + EFPG_MSG_DGST_LEN) + +#define EFPG_ACK_OK (200) +#define EFPG_ACK_CS_ERR (400) +#define EFPG_ACK_MD_ERR (401) +#define EFPG_ACK_PARSE_ERR (402) +#define EFPG_ACK_RW_ERR (403) +#define EFPG_ACK_DI_ERR (404) +#define EFPG_ACK_NODATA_ERR (405) + +#define EFPG_OP_CODE_READ (0x0FF0) +#define EFPG_OP_CODE_WRITE (0xF00F) +#define EFPG_OP_CODE_EXIT (0xFFFF) + +#define EFPG_TYPE_HOSC (0xFF00) +#define EFPG_TYPE_BOOT (0xFE01) +#define EFPG_TYPE_DCXO (0xFD02) +#define EFPG_TYPE_POUT (0xFC03) +#define EFPG_TYPE_MAC (0xFB04) +#define EFPG_TYPE_USER_AREA (0xFA05) + +#define EFPG_NORMAL_CMD (0) +#define EFPG_EXT_CMD (1) + +#define EFPG_UAER_AREA_EXT_LEN (8 + (2 + 2) + 1) + +#define EFPG_HOSC_TYPE_START (328) +#define EFPG_HOSC_TYPE_NUM (4) +#define EFPG_BOOT_FLAG_START (332) +#define EFPG_BOOT_FLAG_NUM (2) +#define EFPG_BOOT_1ST_EN_START (334) +#define EFPG_BOOT_1ST_EN_NUM (1) +#define EFPG_BOOT_1ST_NO_START (335) +#define EFPG_BOOT_1ST_NO_NUM (8) +#define EFPG_BOOT_2ND_EN_START (343) +#define EFPG_BOOT_2ND_EN_NUM (1) +#define EFPG_BOOT_2ND_NO_START (344) +#define EFPG_BOOT_2ND_NO_NUM (8) +#define EFPG_BOOT_HASH_START (352) +#define EFPG_BOOT_HASH_NUM (256) +#define EFPG_DCXO_FLAG_START (898) +#define EFPG_DCXO_FLAG_NUM (6) +#define EFPG_DCXO_TRIM_START (904) +#define EFPG_DCXO_TRIM_NUM (8) +#define EFPG_POUT_FLAG_START (928) +#define EFPG_POUT_FLAG_NUM (6) +#define EFPG_POUT_CAL_START (934) +#define EFPG_POUT_CAL_NUM (21) +#define EFPG_MAC_FLAG_START (997) +#define EFPG_MAC_FLAG_NUM (18) +#define EFPG_MAC_ADDR_START (1015) +#define EFPG_MAC_ADDR_NUM (48) +#define EFPG_CHIPID_FLAG_START (608) +#define EFPG_CHIPID_FLAG_NUM (2) +#define EFPG_CHIPID_1ST_START (200) +#define EFPG_CHIPID_1ST_NUM (128) +#define EFPG_CHIPID_2ND_START (610) +#define EFPG_CHIPID_2ND_NUM (128) +#define EFPG_USER_AREA_START (1447) +#define EFPG_USER_AREA_NUM (601) + +#define EFPG_HOSC_BUF_LEN (1) +#define EFPG_BOOT_BUF_LEN (32) +#define EFPG_DCXO_BUF_LEN (1) +#define EFPG_POUT_BUF_LEN (3) +#define EFPG_MAC_BUF_LEN (6) + +#define EFPG_DCXO_IDX_MAX (3) +#define EFPG_POUT_IDX_MAX (3) +#define EFPG_MAC_IDX_MAX (9) + +#define efpg_malloc(l) malloc(l) +#define efpg_free(p) free(p) +#define efpg_memcpy(d, s, n) memcpy(d, s, n) +#define efpg_memset(s, c, n) memset(s, c, n) +#define efpg_memcmp(s1, s2, n) memcmp(s1, s2, n) + +typedef enum efpg_op { + EFPG_OP_READ = 0, + EFPG_OP_WRITE = 1, + EFPG_OP_EXIT = 2, + EFPG_OP_NUM = 3, +} efpg_op_t; + +typedef enum efpg_state { + EFPG_STATE_CONTINUE = 0, + EFPG_STATE_RESET = 1, + EFPG_STATE_STOP = 2, + EFPG_STATE_NUM = 3, +} efpg_state_t; + +typedef struct efpg_priv { + UART_ID uart_id; + efpg_cb_t start_cb; + efpg_cb_t stop_cb; + + uint8_t key[EFPG_KEY_LEN_MAX]; + uint8_t key_len; + + uint8_t is_cmd; + uint8_t ext_cmd; + uint8_t cmd_frame[EFPG_CMD_FRAME_LEN]; + uint8_t data_frame[EFPG_DATA_FRAME_LEN_MAX]; + uint8_t ext_cmd_frame[EFPG_UAER_AREA_EXT_LEN]; + uint16_t expt_len; + uint16_t recv_len; + + uint16_t protocol_version; + uint16_t start_bit_addr; + uint16_t bit_length; + + efpg_op_t op; + efpg_field_t field; +} efpg_priv_t; + +efpg_state_t efpg_cmd_frame_process(efpg_priv_t *efpg); +efpg_state_t efpg_data_frame_process(efpg_priv_t *efpg); + +uint16_t efpg_read_field(efpg_field_t field, uint8_t *data, uint16_t start_bit_addr, uint16_t bit_len); +uint16_t efpg_write_field(efpg_field_t field, uint8_t *data, uint16_t start_bit_addr, uint16_t bit_len); + +#ifdef __cplusplus +} +#endif + +#endif /* _EFPG_I_H_ */ \ No newline at end of file diff --git a/platform/mcu/xr871/src/image/fdcm.c b/platform/mcu/xr871/src/image/fdcm.c new file mode 100644 index 0000000000..25cb28be80 --- /dev/null +++ b/platform/mcu/xr871/src/image/fdcm.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "flash.h" +#include "sys/fdcm.h" +#include "image_debug.h" + +#define fdcm_malloc(l) malloc(l) +#define fdcm_free(p) free(p) +#define fdcm_memcpy(d, s, n) memcpy(d, s, n) +#define fdcm_memset(s, c, n) memset(s, c, n) + +#define FDCM_ID_CODE (0xA55A5AA5) +#define FDCM_INDEX_MAX (1 << 10) +#define FDCM_BYTE_BITS (8) + +typedef struct fdcm_header { + uint32_t id_code; + uint16_t bitmap_size; + uint16_t data_size; +} fdcm_header_t; + +#define FDCM_HEADER_SIZE sizeof(fdcm_header_t) + +static uint32_t fdcm_bit_count(uint8_t *bitmap, uint16_t size) +{ + uint32_t byte_cnt = 0; + uint32_t bit_cnt = 0; + uint8_t val; + + while (byte_cnt < size) { + if (*bitmap == 0) { + bit_cnt += FDCM_BYTE_BITS; + } + else { + val = ~(*bitmap); + while (val) { + val = val >> 1; + bit_cnt++; + } + break; + } + bitmap++; + byte_cnt++; + } + + return bit_cnt; +} + +/** + * @brief Erase the area and then write a data chunk to the area + * @param[in] hdl Pointer to the FDCM handle + * @param[in] data Pointer to the data + * @param[in] data_size Size of the data + * @return Number of bytes written + */ +static uint32_t fdcm_rewrite(fdcm_handle_t *hdl, void *data, uint16_t data_size) +{ + uint8_t bitmap_byte = 0xFE; + fdcm_header_t header; + + if (flash_erase(hdl->flash, hdl->addr, hdl->size) != hdl->size) { + FDCM_ERR("flash %d, addr %#010x, size %#010x\n", hdl->flash, hdl->addr, hdl->size); + return 0; + } + + header.id_code = FDCM_ID_CODE; + header.bitmap_size = (hdl->size - FDCM_HEADER_SIZE - 1) / (data_size * FDCM_BYTE_BITS + 1) + 1; + if (header.bitmap_size > FDCM_INDEX_MAX) + header.bitmap_size = FDCM_INDEX_MAX; + header.data_size = data_size; + + FDCM_DBG("%s(), %d, flash %d, addr %#010x, size %#010x, bitmap size %d, data size %d\n", + __func__, __LINE__, hdl->flash, hdl->addr, hdl->size, header.bitmap_size, header.data_size); + + if (flash_write(hdl->flash, hdl->addr, &header, FDCM_HEADER_SIZE) + && flash_write(hdl->flash, hdl->addr + FDCM_HEADER_SIZE, &bitmap_byte, 1) + && flash_write(hdl->flash, hdl->addr + FDCM_HEADER_SIZE + header.bitmap_size, data, data_size)) { + return data_size; + } else { + FDCM_ERR("flash %d, addr %#010x, size %#010x\n", hdl->flash, hdl->addr, hdl->size); + return 0; + } +} + +/** + * @brief Open an area in a flash to be managed by FDCM module + * @param[in] flash Flash device number + * @param[in] addr Start address of the area + * @param[in] size Size of the area + * @retval Pointer to the FDCM handle, NULL on failure + * + * @note The area must be aligned to the flash erase block + */ +fdcm_handle_t *fdcm_open(uint32_t flash, uint32_t addr, uint32_t size) +{ + fdcm_handle_t *hdl; + + if (flash_erase_check(flash, addr, size) != 0) { + FDCM_ERR("flash %d, addr %#010x, size %#010x\n", flash, addr, size); + return NULL; + } + + hdl = (fdcm_handle_t *)fdcm_malloc(sizeof(fdcm_handle_t)); + if (hdl == NULL) { + FDCM_ERR("hdl %p\n", hdl); + return NULL; + } + + hdl->flash = flash; + hdl->addr = addr; + hdl->size = size; + + FDCM_DBG("%s(), %d, flash %d, addr %#010x, size %#010x\n", + __func__, __LINE__, flash, addr, size); + + return hdl; +} + +/** + * @brief Read a data chunk from the specified area + * @param[in] hdl Pointer to the FDCM handle + * @param[in] data Pointer to the data + * @param[in] data_size Size of the data + * @return Number of bytes read + */ +uint32_t fdcm_read(fdcm_handle_t *hdl, void *data, uint16_t data_size) +{ + fdcm_header_t header; + uint8_t *bitmap; + uint32_t bit_cnt; + uint32_t addr; + + if ((hdl == NULL) || (data == NULL)) { + FDCM_ERR("hdl %p, data %p\n", hdl, data); + return 0; + } + + flash_read(hdl->flash, hdl->addr, &header, FDCM_HEADER_SIZE); + + FDCM_DBG("%s(), %d, id code %#010x, bitmap size %#06x, data size %#06x\n", + __func__, __LINE__, header.id_code, header.bitmap_size, header.data_size); + + if ((header.id_code != FDCM_ID_CODE) + || (header.data_size != data_size) + || (header.bitmap_size == 0) + || (header.bitmap_size + FDCM_HEADER_SIZE >= hdl->size)) { + FDCM_WARN("id code %#010x, bitmap size %#06x, data size %#06x\n", + header.id_code, header.bitmap_size, header.data_size); + return 0; + } + + bitmap = (uint8_t *)fdcm_malloc(header.bitmap_size); + if (bitmap == NULL) { + FDCM_ERR("bitmap %p\n", bitmap); + return 0; + } + + flash_read(hdl->flash, hdl->addr + FDCM_HEADER_SIZE, bitmap, header.bitmap_size); + bit_cnt = fdcm_bit_count(bitmap, header.bitmap_size); + fdcm_free(bitmap); + + addr = hdl->addr + FDCM_HEADER_SIZE + header.bitmap_size + data_size * (bit_cnt - 1); + return flash_read(hdl->flash, addr, data, data_size); +} + +/** + * @brief Write a data chunk to the specified area + * @param[in] hdl Pointer to the FDCM handle + * @param[in] data Pointer to the data + * @param[in] data_size Size of the data + * @return Number of bytes written + */ +uint32_t fdcm_write(fdcm_handle_t *hdl, void *data, uint16_t data_size) +{ + fdcm_header_t header; + uint8_t *bitmap; + uint32_t bit_cnt; + uint32_t addr; + + if ((hdl == NULL) || (data == NULL)) { + FDCM_ERR("hdl %p, data %p\n", hdl, data); + return 0; + } + + flash_read(hdl->flash, hdl->addr, &header, FDCM_HEADER_SIZE); + + FDCM_DBG("%s(), %d, id code %#010x, bitmap size %#06x, data size %#06x\n", + __func__, __LINE__, header.id_code, header.bitmap_size, header.data_size); + + if ((header.id_code != FDCM_ID_CODE) + || (header.data_size != data_size) + || (header.bitmap_size == 0) + || (header.bitmap_size + FDCM_HEADER_SIZE >= hdl->size)) { + return fdcm_rewrite(hdl, data, data_size); + } + + bitmap = (uint8_t *)fdcm_malloc(header.bitmap_size); + if (bitmap == NULL) { + FDCM_ERR("bitmap %p\n", bitmap); + return 0; + } + + flash_read(hdl->flash, hdl->addr + FDCM_HEADER_SIZE, bitmap, header.bitmap_size); + bit_cnt = fdcm_bit_count(bitmap, header.bitmap_size); + if ((bit_cnt == FDCM_BYTE_BITS * header.bitmap_size) + || (FDCM_HEADER_SIZE + header.bitmap_size + data_size * (bit_cnt + 1) > hdl->size)) { + fdcm_free(bitmap); + return fdcm_rewrite(hdl, data, data_size); + } + + addr = hdl->addr + FDCM_HEADER_SIZE + bit_cnt / FDCM_BYTE_BITS; + bitmap[bit_cnt / FDCM_BYTE_BITS] &= ~(0x1 << (bit_cnt % FDCM_BYTE_BITS)); + flash_write(hdl->flash, addr, bitmap + bit_cnt / FDCM_BYTE_BITS, 1); + fdcm_free(bitmap); + + addr = hdl->addr + FDCM_HEADER_SIZE + header.bitmap_size + data_size * bit_cnt; + return flash_write(hdl->flash, addr, data, data_size); +} + +/** + * @brief Close the area managed by FDCM module + * @param[in] hdl Pointer to the FDCM handle + * @return None + */ +void fdcm_close(fdcm_handle_t *hdl) +{ + if (hdl != NULL) { + fdcm_free(hdl); + hdl = NULL; + } +} + diff --git a/platform/mcu/xr871/src/image/flash.c b/platform/mcu/xr871/src/image/flash.c new file mode 100644 index 0000000000..501b1629d5 --- /dev/null +++ b/platform/mcu/xr871/src/image/flash.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "flash.h" +#include "image_debug.h" + +#include "driver/chip/hal_flash.h" + +/** + * @brief Read an amount of data from flash + * @param[in] flash Flash device number + * @param[in] src_addr The source address of reading + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be read + * @return Number of bytes read + */ +uint32_t flash_read(uint32_t flash, uint32_t src_addr, void *buf, uint32_t size) +{ + if (HAL_Flash_Open(flash, FLASH_OPEN_TIMEOUT) != HAL_OK) { + FLASH_ERR("flash %d\n", flash); + return 0; + } + + if (HAL_Flash_Read(flash, src_addr, buf, size) != HAL_OK) { + FLASH_ERR("flash %d, src addr %#010x, buf %p, size %#010x\n", + flash, src_addr, buf, size); + HAL_Flash_Close(flash); + return 0; + } + + HAL_Flash_Close(flash); + return size; +} + +/** + * @brief Write an amount of data to flash + * @param[in] flash Flash device number + * @param[in] dst_addr The destination address of writing + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be written + * @return Number of bytes written + */ +uint32_t flash_write(uint32_t flash, uint32_t dst_addr, void *buf, uint32_t size) +{ + if (HAL_Flash_Open(flash, FLASH_OPEN_TIMEOUT) != HAL_OK) { + FLASH_ERR("flash %d\n", flash); + return 0; + } + + if (HAL_Flash_Write(flash, dst_addr, buf, size) != HAL_OK) { + FLASH_ERR("flash %d, dst addr %#010x, buf %p, size %#010x\n", + flash, dst_addr, buf, size); + HAL_Flash_Close(flash); + return 0; + } + + HAL_Flash_Close(flash); + return size; +} + +/** + * @brief Check whether the specified area is aligned to the flash erase block + * @param[in] flash Flash device number + * @param[in] addr Start address of the specified area + * @param[in] size Size of the specified area + * @return 0 on aligned, -1 on misaligned + */ +int32_t flash_erase_check(uint32_t flash, uint32_t addr, uint32_t size) +{ + uint32_t start; + + if ((size >= (64 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_64KB, addr, &start) == HAL_OK) + && (addr == start) + && ((size & 0xFFFF) == 0)) { + } else if ((size >= (32 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_32KB, addr, &start) == HAL_OK) + && (addr == start) + && ((size & 0x7FFF) == 0)) { + } else if ((size >= (4 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_4KB, addr, &start) == HAL_OK) + && (addr == start) + && ((size & 0xFFF) == 0)) { + } else { + FLASH_WARN("%s(), %d, flash %d, addr %#010x, size %#010x\n", + __func__, __LINE__, flash, addr, size); + return -1; + } + + return 0; +} + +/** + * @brief Erase a specified area in flash + * @param[in] flash Flash device number + * @param[in] addr Start address of the specified area + * @param[in] size Size of the specified area + * @return Number of bytes erased + */ +uint32_t flash_erase(uint32_t flash, uint32_t addr, uint32_t size) +{ + uint32_t start; + uint32_t multiples; + FlashEraseMode erase_size; + HAL_Status status; + + if ((size >= (64 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_64KB, addr, &start) == HAL_OK)) { + multiples = size / (64 << 10); + erase_size = FLASH_ERASE_64KB; + } else if ((size >= (32 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_32KB, addr, &start) == HAL_OK)) { + multiples = size / (32 << 10); + erase_size = FLASH_ERASE_32KB; + } else if ((size >= (4 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_4KB, addr, &start) == HAL_OK)) { + multiples = size / (4 << 10); + erase_size = FLASH_ERASE_4KB; + } else { + FLASH_ERR("flash %d, addr %#010x, size %#010x\n", flash, addr, size); + return 0; + } + + if (HAL_Flash_Open(flash, FLASH_OPEN_TIMEOUT) != HAL_OK) { + FLASH_ERR("flash %d\n", flash); + return 0; + } + + status = HAL_Flash_Erase(flash, erase_size, addr, multiples); + if (status != HAL_OK) { + FLASH_ERR("flash %d, erase size %#010x, addr %#010x, mul %d\n", + flash, erase_size, addr, multiples); + HAL_Flash_Close(flash); + return 0; + } + + HAL_Flash_Close(flash); + return size; +} + diff --git a/platform/mcu/xr871/src/image/flash.h b/platform/mcu/xr871/src/image/flash.h new file mode 100644 index 0000000000..bb801aa314 --- /dev/null +++ b/platform/mcu/xr871/src/image/flash.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IMAGE_FLASH_H_ +#define _IMAGE_FLASH_H_ + +#include "types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define FLASH_OPEN_TIMEOUT (5000) + +uint32_t flash_read(uint32_t flash, uint32_t src_addr, void *buf, uint32_t size); +uint32_t flash_write(uint32_t flash, uint32_t dst_addr, void *buf, uint32_t size); + +int32_t flash_erase_check(uint32_t flash, uint32_t addr, uint32_t size); +uint32_t flash_erase(uint32_t flash, uint32_t addr, uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* _IMAGE_FLASH_H_ */ diff --git a/platform/mcu/xr871/src/image/image.c b/platform/mcu/xr871/src/image/image.c new file mode 100644 index 0000000000..e3d2867edb --- /dev/null +++ b/platform/mcu/xr871/src/image/image.c @@ -0,0 +1,568 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "flash.h" +#include "sys/image.h" +#include "image_debug.h" + +#define image_malloc(l) malloc(l) +#define image_free(p) free(p) +#define image_memcpy(d, s, n) memcpy(d, s, n) +#define image_memset(s, c, n) memset(s, c, n) + +#define IMAGE_CHECK_SIZE (1024) +#define IMAGE_EXPAND_SIZE (5) + +typedef struct { + uint32_t id; + uint32_t addr; +} sec_addr_t; + +typedef struct { + uint8_t sec_num[IMAGE_SEQ_NUM]; + sec_addr_t *sec_addr[IMAGE_SEQ_NUM]; + uint32_t flash[IMAGE_SEQ_NUM]; + uint32_t addr[IMAGE_SEQ_NUM]; + uint32_t image_size; + uint32_t boot_size; + image_seq_t seq; +} image_priv_t; + +image_priv_t image_priv; + +static void image_clear_sec_addr(void) +{ + image_seq_t seq; + + for (seq = IMAGE_SEQ_1ST; seq < IMAGE_SEQ_NUM; seq++) { + image_priv.sec_num[seq] = 0; + if (image_priv.sec_addr[seq]) { + image_free(image_priv.sec_addr[seq]); + image_priv.sec_addr[seq] = NULL; + } + } +} + +/** + * @brief Initialize the image module + * @param[in] flash Flash device number + * @param[in] addr Start address of the image region + * @param[in] size Size of the image region + * @return None + */ +void image_init(uint32_t flash, uint32_t addr, uint32_t size) +{ + section_header_t sh; + + IMAGE_DBG("%s(), %d, flash %d, addr %#010x, size %#010x\n", + __func__, __LINE__, flash, addr, size); + + if (flash_read(flash, addr, &sh, IMAGE_HEADER_SIZE) != IMAGE_HEADER_SIZE) { + IMAGE_ERR("read flash failed\n"); + return; + } + + image_clear_sec_addr(); + image_priv.flash[IMAGE_SEQ_1ST] = flash; + image_priv.addr[IMAGE_SEQ_1ST] = addr; + if (sh.priv[0] == IMAGE_INVALID_FLASH) + image_priv.flash[IMAGE_SEQ_2ND] = flash; + else + image_priv.flash[IMAGE_SEQ_2ND] = sh.priv[0]; + image_priv.addr[IMAGE_SEQ_2ND] = sh.priv[1]; + image_priv.image_size = size; + image_priv.boot_size = sh.next_addr; + image_priv.seq = IMAGE_SEQ_NUM; + + IMAGE_DBG("%s(), %d, flash_1st %d, addr_1st %#010x, flash_2nd %d, " + "addr_2nd %#010x, image_size %#010x, boot_size %#010x, seq %d\n", + __func__, __LINE__, + image_priv.flash[IMAGE_SEQ_1ST], image_priv.addr[IMAGE_SEQ_1ST], + image_priv.flash[IMAGE_SEQ_2ND], image_priv.addr[IMAGE_SEQ_2ND], + image_priv.image_size, image_priv.boot_size, image_priv.seq); +} + +/** + * @brief DeInitialize the image module + * @return None + */ +void image_deinit(void) +{ + image_clear_sec_addr(); + image_priv.flash[IMAGE_SEQ_1ST] = 0; + image_priv.addr[IMAGE_SEQ_1ST] = IMAGE_INVALID_ADDR; + image_priv.flash[IMAGE_SEQ_2ND] = 0; + image_priv.addr[IMAGE_SEQ_2ND] = IMAGE_INVALID_ADDR; + image_priv.image_size = 0; + image_priv.boot_size = 0; + image_priv.seq = IMAGE_SEQ_NUM; +} + +/** + * @brief Get OTA parameter + * @param[in] param Pointer to the OTA parameter + * @return None + */ +void image_get_ota_param(image_ota_param_t *param) +{ + if (param == NULL) { + IMAGE_ERR("param %p\n", param); + return; + } + + param->flash[IMAGE_SEQ_1ST] = image_priv.flash[IMAGE_SEQ_1ST]; + param->addr[IMAGE_SEQ_1ST] = image_priv.addr[IMAGE_SEQ_1ST]; + param->flash[IMAGE_SEQ_2ND] = image_priv.flash[IMAGE_SEQ_2ND]; + param->addr[IMAGE_SEQ_2ND] = image_priv.addr[IMAGE_SEQ_2ND]; + param->image_size = image_priv.image_size; + param->boot_size = image_priv.boot_size; + + IMAGE_DBG("%s(), %d, flash_1st %d, addr_1st %#010x, flash_2nd %d, " + "addr_2nd %#010x, image_size %#010x, boot_size %#010x\n", + __func__, __LINE__, + param->flash[IMAGE_SEQ_1ST], param->addr[IMAGE_SEQ_1ST], + param->flash[IMAGE_SEQ_2ND], param->addr[IMAGE_SEQ_2ND], + param->image_size, param->boot_size); +} + +/** + * @brief Set running image sequence + * @param[in] seq Image sequence + * @return None + */ +void image_set_running_seq(image_seq_t seq) +{ + IMAGE_DBG("%s(), %d, seq %d\n", __func__, __LINE__, seq); + + image_priv.seq = seq; +} + +/** + * @brief Get running image sequence + * @param[in] seq Pointer to image sequence + * @return None + */ +void image_get_running_seq(image_seq_t *seq) +{ + if (seq == NULL) { + IMAGE_ERR("seq %p\n", seq); + return; + } + + IMAGE_DBG("%s(), %d, seq %d\n", __func__, __LINE__, image_priv.seq); + + *seq = image_priv.seq; +} + +static sec_addr_t *image_expand_addr(image_seq_t seq) +{ + sec_addr_t *sec_addr; + + if (image_priv.sec_num[seq] == 0) + return image_malloc(IMAGE_EXPAND_SIZE * sizeof(sec_addr_t)); + + sec_addr = image_malloc((image_priv.sec_num[seq] + IMAGE_EXPAND_SIZE) * sizeof(sec_addr_t)); + if (sec_addr) { + image_memcpy(sec_addr, image_priv.sec_addr[seq], image_priv.sec_num[seq] * sizeof(sec_addr_t)); + image_free(image_priv.sec_addr[seq]); + } + + return sec_addr; +} + +static uint32_t image_get_addr(image_seq_t seq, uint32_t id) +{ + uint8_t index; + uint32_t addr; + uint32_t next_addr; + sec_addr_t *sec_addr; + + if (seq >= IMAGE_SEQ_NUM) { + IMAGE_ERR("seq %d\n", seq); + return IMAGE_INVALID_ADDR; + } + + for (index = 0; index < image_priv.sec_num[seq]; index++) { + if (id == image_priv.sec_addr[seq][index].id) + return image_priv.sec_addr[seq][index].addr; + } + + if (image_priv.sec_num[seq] == 0) { + addr = image_priv.addr[IMAGE_SEQ_1ST]; + } else { + addr = image_priv.sec_addr[seq][image_priv.sec_num[seq] - 1].addr; + flash_read(image_priv.flash[seq], addr + offsetof(section_header_t, next_addr), &next_addr, sizeof(next_addr)); + addr = image_priv.addr[seq] + next_addr; + } + + while (next_addr != IMAGE_INVALID_ADDR) { + if ((image_priv.sec_num[seq] % IMAGE_EXPAND_SIZE) == 0) { + sec_addr = image_expand_addr(seq); + if (sec_addr == NULL) { + IMAGE_ERR("sec_addr %p, seq %d, num %d\n", sec_addr, seq, image_priv.sec_num[seq]); + return IMAGE_INVALID_ADDR; + } else { + image_priv.sec_addr[seq] = sec_addr; + } + } + + image_priv.sec_addr[seq][image_priv.sec_num[seq]].addr = addr; + flash_read(image_priv.flash[seq], addr + offsetof(section_header_t, id), + &(image_priv.sec_addr[seq][image_priv.sec_num[seq]].id), sizeof(id)); + image_priv.sec_num[seq]++; + + if (id == image_priv.sec_addr[seq][image_priv.sec_num[seq] - 1].id) { + return image_priv.sec_addr[seq][image_priv.sec_num[seq] - 1].addr; + } + flash_read(image_priv.flash[seq], addr + offsetof(section_header_t, next_addr), + &next_addr, sizeof(next_addr)); + addr = image_priv.addr[seq] + next_addr; + } + + IMAGE_ERR("seq %d, id %#010x\n", seq, id); + return IMAGE_INVALID_ADDR; +} + +/** + * @brief Get address of the specified section in running image + * @param[in] id ID of the specified section + * @return section address + */ +uint32_t image_get_section_addr(uint32_t id) +{ + IMAGE_DBG("%s(), %d, id %#010x\n", __func__, __LINE__, id); + + return image_get_addr(image_priv.seq, id); +} + +/** + * @brief Read an amount of image data from flash + * @param[in] id Section ID of the image data + * @param[in] seg Section segment of the image data + * @param[in] offset Offset into the segment from where to read data + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be read + * @return Number of bytes read + */ +uint32_t image_read(uint32_t id, image_seg_t seg, uint32_t offset, void *buf, uint32_t size) +{ + uint32_t addr; + uint32_t body_len; + + IMAGE_DBG("%s(), %d, id %#010x, seg %d, offset %d, buf %p, size %d\n", + __func__, __LINE__, id, seg, offset, buf, size); + + if (buf == NULL) { + IMAGE_ERR("buf %p\n", buf); + return 0; + } + + addr = image_get_addr(image_priv.seq, id); + if (addr == IMAGE_INVALID_ADDR) { + IMAGE_ERR("seq %d, id %#010x, addr %#010x\n", image_priv.seq, id, addr); + return 0; + } + + switch (seg) { + case IMAGE_SEG_HEADER: + break; + case IMAGE_SEG_BODY: + addr += IMAGE_HEADER_SIZE; + break; + case IMAGE_SEG_TAILER: + flash_read(image_priv.flash[image_priv.seq], addr + offsetof(section_header_t, body_len), + &body_len, sizeof(body_len)); + addr += IMAGE_HEADER_SIZE + body_len; + break; + default : + IMAGE_ERR("seg %d\n", seg); + return 0; + } + + addr += offset; + + return flash_read(image_priv.flash[image_priv.seq], addr, buf, size); + +} + +/** + * @brief Write an amount of image data to flash + * @param[in] id Section ID of the image data + * @param[in] seg Section segment of the image data + * @param[in] offset Offset into the segment from where to write data + * @param[in] buf Pointer to the data buffer + * @param[in] size Number of bytes to be written + * @return Number of bytes written + */ +uint32_t image_write(uint32_t id, image_seg_t seg, uint32_t offset, void *buf, uint32_t size) +{ + uint32_t addr; + uint32_t body_len; + + IMAGE_DBG("%s(), %d, id %#010x, seg %d, offset %d, buf %p, size %d\n", + __func__, __LINE__, id, seg, offset, buf, size); + + if (buf == NULL) { + IMAGE_ERR("buf %p\n", buf); + return 0; + } + + addr = image_get_addr(image_priv.seq, id); + if (addr == IMAGE_INVALID_ADDR) { + IMAGE_ERR("seq %d, id %#010x, addr %#010x\n", image_priv.seq, id, addr); + return 0; + } + + switch (seg) { + case IMAGE_SEG_HEADER: + image_clear_sec_addr(); + break; + case IMAGE_SEG_BODY: + addr += IMAGE_HEADER_SIZE; + break; + case IMAGE_SEG_TAILER: + flash_read(image_priv.flash[image_priv.seq], addr + offsetof(section_header_t, body_len), + &body_len, sizeof(body_len)); + addr += IMAGE_HEADER_SIZE + body_len; + break; + default : + IMAGE_ERR("seg %d\n", seg); + return 0; + } + + addr += offset; + + return flash_write(image_priv.flash[image_priv.seq], addr, buf, size); +} + +static uint16_t image_checksum16(uint8_t *data, uint32_t len) +{ + uint16_t cs = 0; + uint16_t *p = (uint16_t *)data; + + while (len > 1) { + cs += *p++; + len -= 2; + } + if (len) { + cs += *(uint8_t *)p; + } + + return cs; +} + +/** + * @brief Get 16-bit checksum of the data buffer + * @param[in] buf Pointer to the data buffer + * @param[in] len length of the data buffer + * @return 16-bit checksum + */ +uint16_t image_get_checksum(void *buf, uint32_t len) +{ + if (buf == NULL) { + IMAGE_ERR("buf %p\n", buf); + return 0; + } + + return image_checksum16(buf, len); +} + +/** + * @brief Check vadility of the section header + * @param[in] sh Pointer to the section header + * @retval image_val_t, IMAGE_VALID on valid, IMAGE_INVALID on invalid + */ +image_val_t image_check_header(section_header_t *sh) +{ + if (sh == NULL) { + IMAGE_ERR("sh %p\n", sh); + return IMAGE_INVALID; + } + + if ((sh->magic_number != IMAGE_MAGIC_NUMBER) + || (0xFFFF != image_get_checksum(sh, IMAGE_HEADER_SIZE))) { + IMAGE_WARN("%s(), %d, magic number %#010x, checksum %#06x\n", __func__, __LINE__, + sh->magic_number, image_get_checksum(sh, IMAGE_HEADER_SIZE)); + return IMAGE_INVALID; + } + + return IMAGE_VALID; +} + +/** + * @brief Check vadility of the section data(body and tailer) + * @param[in] sh Pointer to the section header + * @param[in] body Pointer to the section body + * @param[in] body_len Length of the section body + * @param[in] tailer Pointer to the section tailer + * @param[in] tailer_len Length of the section tailer + * @retval image_val_t, IMAGE_VALID on valid, IMAGE_INVALID on invalid + */ +image_val_t image_check_data(section_header_t *sh, void *body, uint32_t body_len, + void *tailer, uint32_t tailer_len) +{ + uint8_t joint[2]; + uint16_t data_checksum; + + if ((sh == NULL) || (body == NULL) || (body_len == 0) + || ((tailer == NULL) && (tailer_len != 0))) { + IMAGE_ERR("sh %p, body %p, body len %d, tailer %p, tailer len %d\n", + sh, body, body_len, tailer, tailer_len); + return IMAGE_INVALID; + } + + if (tailer_len == 0) { + data_checksum = sh->data_chksum + + image_checksum16(body, body_len); + } else if ((body_len & 0x1) == 0) { + data_checksum = sh->data_chksum + + image_checksum16(body, body_len) + + image_checksum16(tailer, tailer_len); + } else { + image_memcpy(joint, ((uint8_t *)body) + body_len - 1, 1); + image_memcpy(joint + 1, tailer, 1); + data_checksum = sh->data_chksum + + image_checksum16(body, body_len - 1) + + image_checksum16(joint, 2) + + image_checksum16(((uint8_t *)tailer) + 1, tailer_len - 1); + } + + if (data_checksum != 0xFFFF) { + IMAGE_WARN("%s(), %d, checksum %#06x\n", __func__, __LINE__, data_checksum); + return IMAGE_INVALID; + } + + return IMAGE_VALID; +} + +static image_val_t _image_check_section(uint32_t flash, uint32_t addr) +{ + uint16_t data_chksum; + uint32_t data_size; + uint8_t *buf_check; + section_header_t *sh; + + sh = (section_header_t *)image_malloc(IMAGE_HEADER_SIZE); + if (sh == NULL) { + IMAGE_ERR("sh %p\n", sh); + return IMAGE_INVALID; + } + + flash_read(flash, addr, sh, IMAGE_HEADER_SIZE); + if (image_check_header(sh) == IMAGE_INVALID) { + IMAGE_ERR("flash %d, addr %#010x\n", flash, addr); + image_free(sh); + return IMAGE_INVALID; + } + + data_chksum = sh->data_chksum; + data_size = sh->data_size; + image_free(sh); + + buf_check = (uint8_t *)image_malloc(IMAGE_CHECK_SIZE); + if (buf_check == NULL) { + IMAGE_ERR("buf_check %p\n", buf_check); + return IMAGE_INVALID; + } + + addr += IMAGE_HEADER_SIZE; + while (data_size > 0) { + if (data_size >= IMAGE_CHECK_SIZE) { + flash_read(flash, addr, buf_check, IMAGE_CHECK_SIZE); + data_chksum += image_checksum16(buf_check, IMAGE_CHECK_SIZE); + addr += IMAGE_CHECK_SIZE; + data_size -= IMAGE_CHECK_SIZE; + } else { + flash_read(flash, addr, buf_check, data_size); + data_chksum += image_checksum16(buf_check, data_size); + addr += data_size; + data_size -= data_size; + } + } + image_free(buf_check); + + if (data_chksum != 0xFFFF) { + IMAGE_WARN("%s(), %d, data checksum %#06x\n", __func__, __LINE__, data_chksum); + return IMAGE_INVALID; + } + + return IMAGE_VALID; +} + +/** + * @brief Check vadility of the specified section in specified image + * @param[in] seq Sequence of the specified image + * @param[in] id Section ID of the specified section + * @retval image_val_t, IMAGE_VALID on valid, IMAGE_INVALID on invalid + */ +image_val_t image_check_section(image_seq_t seq, uint32_t id) +{ + uint32_t addr; + + addr = image_get_addr(seq, id); + if (addr == IMAGE_INVALID_ADDR) { + IMAGE_ERR("seq %d, id %#010x, addr %#010x\n", seq, id, addr); + return IMAGE_INVALID; + } + + IMAGE_DBG("%s(), %d, seq %d, flash %d, id %#010x, addr %#010x\n", + __func__, __LINE__, seq, image_priv.flash[seq], id, addr); + + return _image_check_section(image_priv.flash[seq], addr); +} + +/** + * @brief Check vadility of all the sections in specified image + * @param[in] seq Sequence of the specified image + * @retval image_val_t, IMAGE_VALID on valid, IMAGE_INVALID on invalid + */ +image_val_t image_check_sections(image_seq_t seq) +{ + uint32_t addr; + uint32_t next_addr = image_priv.boot_size; + + IMAGE_DBG("%s(), %d, seq %d, next addr %#010x\n", __func__, __LINE__, seq, next_addr); + + while (next_addr != IMAGE_INVALID_ADDR) { + addr = image_priv.addr[seq] + next_addr; + if (_image_check_section(image_priv.flash[seq], addr) == IMAGE_INVALID) { + IMAGE_WARN("%s(), %d, seq %d, flash %d, addr %#010x\n", + __func__, __LINE__, seq, image_priv.flash[seq], addr); + return IMAGE_INVALID; + } + flash_read(image_priv.flash[seq], addr + offsetof(section_header_t, next_addr), + &next_addr, sizeof(next_addr)); + } + + return IMAGE_VALID; +} + diff --git a/platform/mcu/xr871/src/image/image.mk b/platform/mcu/xr871/src/image/image.mk new file mode 100644 index 0000000000..3878ba6359 --- /dev/null +++ b/platform/mcu/xr871/src/image/image.mk @@ -0,0 +1,6 @@ +NAME := image + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := fdcm.c \ + flash.c \ + image.c \ No newline at end of file diff --git a/platform/mcu/xr871/src/image/image_debug.h b/platform/mcu/xr871/src/image/image_debug.h new file mode 100644 index 0000000000..2d979fd56d --- /dev/null +++ b/platform/mcu/xr871/src/image/image_debug.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _IMAGE_DEBUG_H_ +#define _IMAGE_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IMAGE_DBG_ON 0 +#define IMAGE_WARN_ON 0 +#define IMAGE_ERR_ON 1 +#define IMAGE_ABORT_ON 0 + +#define FDCM_DBG_ON 0 +#define FDCM_WARN_ON 0 +#define FDCM_ERR_ON 1 +#define FDCM_ABORT_ON 0 + +#define FLASH_DBG_ON 0 +#define FLASH_WARN_ON 0 +#define FLASH_ERR_ON 1 +#define FLASH_ABORT_ON 0 + +#define IMAGE_SYSLOG printf +#define IMAGE_ABORT() sys_abort() + +#define IMAGE_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + IMAGE_SYSLOG(fmt, ##arg); \ + } while (0) + +#define IMAGE_DBG(fmt, arg...) IMAGE_LOG(IMAGE_DBG_ON, "[image] "fmt, ##arg) +#define IMAGE_WARN(fmt, arg...) IMAGE_LOG(IMAGE_WARN_ON, "[image WARN] "fmt, ##arg) +#define IMAGE_ERR(fmt, arg...) \ + do { \ + IMAGE_LOG(IMAGE_ERR_ON, "[image ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (IMAGE_ABORT_ON) \ + IMAGE_ABORT(); \ + } while (0) + +#define FDCM_SYSLOG printf +#define FDCM_ABORT() sys_abort() + +#define FDCM_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + FDCM_SYSLOG(fmt, ##arg); \ + } while (0) + +#define FDCM_DBG(fmt, arg...) FDCM_LOG(FDCM_DBG_ON, "[FDCM] "fmt, ##arg) +#define FDCM_WARN(fmt, arg...) FDCM_LOG(FDCM_WARN_ON, "[FDCM WARN] "fmt, ##arg) +#define FDCM_ERR(fmt, arg...) \ + do { \ + FDCM_LOG(FDCM_ERR_ON, "[FDCM ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (FDCM_ABORT_ON) \ + FDCM_ABORT(); \ + } while (0) + +#define FLASH_SYSLOG printf +#define FLASH_ABORT() sys_abort() + +#define FLASH_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + FLASH_SYSLOG(fmt, ##arg); \ + } while (0) + +#define FLASH_DBG(fmt, arg...) FLASH_LOG(FLASH_DBG_ON, "[flash] "fmt, ##arg) +#define FLASH_WARN(fmt, arg...) FLASH_LOG(FLASH_WARN_ON, "[flash WARN] "fmt, ##arg) +#define FLASH_ERR(fmt, arg...) \ + do { \ + FLASH_LOG(FLASH_ERR_ON, "[flash ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (FLASH_ABORT_ON) \ + FLASH_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _IMAGE_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/net/lwip/checksum.c b/platform/mcu/xr871/src/net/lwip/checksum.c new file mode 100644 index 0000000000..73ce526438 --- /dev/null +++ b/platform/mcu/xr871/src/net/lwip/checksum.c @@ -0,0 +1,126 @@ +/* Copyright (C) 2013 - Adam Green (https://github.com/adamgreen) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +#if defined(__GNUC__) && defined(__thumb2__) + + +/* This is a hand written Thumb-2 assembly language version of the + algorithm 3 version of lwip_standard_chksum in lwIP's inet_chksum.c. It + performs the checksumming 32-bits at a time and even unrolls the loop to + perform two of these 32-bit adds per loop iteration. + + Returns: + 16-bit 1's complement summation (not inversed). + + NOTE: This function does return a uint16_t from the assembly language code + but is marked as void so that GCC doesn't issue warning because it + doesn't know about this low level return. +*/ +__attribute__((naked)) void /*uint16_t*/ thumb2_checksum(const void* pData, int length) +{ + __asm ( + ".syntax unified\n" + ".thumb\n" + + // Push non-volatile registers we use on stack. Push link register too to + // keep stack 8-byte aligned and allow single pop to restore and return. + " push {r4, lr}\n" + // Initialize sum, r2, to 0. + " movs r2, #0\n" + // Remember whether pData was at odd address in r3. This is used later to + // know if it needs to swap the result since the summation will be done at + // an offset of 1, rather than 0. + " ands r3, r0, #1\n" + // Need to 2-byte align? If not skip ahead. + " beq 1$\n" + // We can return if there are no bytes to sum. + " cbz r1, 9$\n" + + // 2-byte align. + // Place the first data byte in odd summation location since it needs to be + // swapped later. It's ok to overwrite r2 here as it only had a value of 0 + // up until now. Advance r0 pointer and decrement r1 length as we go. + " ldrb r2, [r0], #1\n" + " lsls r2, r2, #8\n" + " subs r1, r1, #1\n" + + // Need to 4-byte align? If not skip ahead. + "1$:\n" + " ands r4, r0, #3\n" + " beq 2$\n" + // Have more than 1 byte left to align? If not skip ahead to take care of + // trailing byte. + " cmp r1, #2\n" + " blt 7$\n" + + // 4-byte align. + " ldrh r4, [r0], #2\n" + " adds r2, r2, r4\n" + " subs r1, r1, #2\n" + + // Main summing loop which sums up data 2 words at a time. + // Make sure that we have more than 7 bytes left to sum. + "2$:\n" + " cmp r1, #8\n" + " blt 3$\n" + // Sum next two words. Applying previous upper 16-bit carry to + // lower 16-bits. + " ldr r4, [r0], #4\n" + " adds r2, r4\n" + " adc r2, r2, #0\n" + " ldr r4, [r0], #4\n" + " adds r2, r4\n" + " adc r2, r2, #0\n" + " subs r1, r1, #8\n" + " b 2$\n" + + // Sum up any remaining half-words. + "3$:\n" + // Make sure that we have more than 1 byte left to sum. + " cmp r1, #2\n" + " blt 7$\n" + // Sum up next half word, continue to apply carry. + " ldrh r4, [r0], #2\n" + " adds r2, r4\n" + " adc r2, r2, #0\n" + " subs r1, r1, #2\n" + " b 3$\n" + + // Handle trailing byte, if it exists + "7$:\n" + " cbz r1, 8$\n" + " ldrb r4, [r0]\n" + " adds r2, r4\n" + " adc r2, r2, #0\n" + + // Fold 32-bit checksum into 16-bit checksum. + "8$:\n" + " ubfx r4, r2, #16, #16\n" + " ubfx r2, r2, #0, #16\n" + " adds r2, r4\n" + " ubfx r4, r2, #16, #16\n" + " ubfx r2, r2, #0, #16\n" + " adds r2, r4\n" + + // Swap bytes if started at odd address + " cbz r3, 9$\n" + " rev16 r2, r2\n" + + // Return final sum. + "9$: mov r0, r2\n" + " pop {r4, pc}\n" + ); +} + +#endif diff --git a/platform/mcu/xr871/src/net/lwip/lwip.mk b/platform/mcu/xr871/src/net/lwip/lwip.mk new file mode 100644 index 0000000000..ee51eb8060 --- /dev/null +++ b/platform/mcu/xr871/src/net/lwip/lwip.mk @@ -0,0 +1,5 @@ +NAME := lwip + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := memcpy.c \ + checksum.c diff --git a/platform/mcu/xr871/src/net/lwip/memcpy.c b/platform/mcu/xr871/src/net/lwip/memcpy.c new file mode 100644 index 0000000000..dc71888048 --- /dev/null +++ b/platform/mcu/xr871/src/net/lwip/memcpy.c @@ -0,0 +1,59 @@ +/* Copyright (C) 2013 - Adam Green (https://github.com/adamgreen) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +#if defined(__GNUC__) && defined(__thumb2__) + +#include // for size_t + + +/* This is a hand written Thumb-2 assembly language version of the + standard C memcpy() function that can be used by the lwIP networking + stack to improve its performance. It copies 4 bytes at a time and + unrolls the loop to perform 4 of these copies per loop iteration. +*/ +__attribute__((naked)) void thumb2_memcpy(void* pDest, const void* pSource, size_t length) +{ + __asm ( + ".syntax unified\n" + ".thumb\n" + + // Copy 16 bytes at a time first. + " lsrs r3, r2, #4\n" + " beq.n 2$\n" + "1$: ldr r12, [r1], #4\n" + " str r12, [r0], #4\n" + " ldr r12, [r1], #4\n" + " str r12, [r0], #4\n" + " ldr r12, [r1], #4\n" + " str r12, [r0], #4\n" + " ldr r12, [r1], #4\n" + " str r12, [r0], #4\n" + " subs r3, #1\n" + " bne 1$\n" + + // Copy byte by byte for what is left. + "2$:\n" + " ands r3, r2, #0xf\n" + " beq.n 4$\n" + "3$: ldrb r12, [r1], #1\n" + " strb r12, [r0], #1\n" + " subs r3, #1\n" + " bne 3$\n" + + // Return to caller. + "4$: bx lr\n" + ); +} + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/AUTHORS b/platform/mcu/xr871/src/net/udhcp/AUTHORS new file mode 100644 index 0000000000..89a6de41df --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/AUTHORS @@ -0,0 +1,13 @@ +udhcp server/client package +----------------------- + +Russ Dill +Matthew Ramsay +Chris Trew + +Other Credits: +-------------- +Moreton Bay (http://www.moretonbay.com/) +Lineo (http://opensource.lineo.com) + + diff --git a/platform/mcu/xr871/src/net/udhcp/COPYING b/platform/mcu/xr871/src/net/udhcp/COPYING new file mode 100644 index 0000000000..a43ea2126f --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 675 Mass Ave, Cambridge, MA 02139, USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/platform/mcu/xr871/src/net/udhcp/ChangeLog b/platform/mcu/xr871/src/net/udhcp/ChangeLog new file mode 100644 index 0000000000..34cfe16f9e --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/ChangeLog @@ -0,0 +1,249 @@ +0.9.8 (021031) ++ split up README files (me) ++ use /dev/urandom to seed xid's (instead of time(0)) (me) ++ fixed renew behavior (me) ++ udhcp now fits nicely into busybox + (Glenn McGrath as well as myself) ++ updated client manpage (me) ++ both client and server now use sockets for signal handling, + hopefully, this will be the last needed change in signal + handling, I'm fairly certain all the possible races are now + closed. (me) ++ The server now restarts the auto_time timer when it receives + a SIGUSR1 (write out config file). (me) ++ Improve signal handling (David Poole) ++ Fix to config file parsing (Matt Kraai) ++ Fix load lease logic (me) ++ Fix clear_lease logic (me) ++ -h is now an alias for -H (udhcp bug #1253) ++ Shorter timeout on not receiving offers (me) ++ Improved signal behavior by client (me) ++ Would never assign end address (Keith Smith ) ++ Was improperly reporting yiaddr as siaddr (ben-udhcp@bdlow.net) + udhcp bug#1256 ++ Fixed reading of client id (David Poole ) ++ change sys_errlist[] to strerror() as it aparently doesn't exist + (andersee ) ++ fixed get_raw_packet so it returns -2 on non fatal errors + (Ted Lemon ) ++ Improved (hopefully) NAKing behavior (me) ++ Added -b option (Jouni Malinen) ++ Compute checksums correctly on big endian hosts + (Jouni Malinen ) + +0.9.7 (020526) ++ Use add_lease in read_leases, sanitizes leases more, and clears out exprired + ones if there is no more room (me) ++ Moved udhcpd.leases to /var/lib/misc/udhcpd.leases (Debian bug #147747) ++ Change (obsolete) AF_INET in arping.c to PF_PACKET (Debian bug #127049) ++ Added script hook for DHCPNAK (nak), as well as providing the message option + (me) ++ Generate the paramaters request list by seeing what options in options.c are + ored with OPTION_REQ in options.c ++ Fix dhcp renew forgetfullness on client (bug #1230) ++ Fix dhcp release bug on client (bug #1231) ++ Set option request list for DHCP renew (bug #1233) ++ Set BOOTREQUEST/REPLY properly ++ Change client-identifier field to popularly expected behavior (me) ++ Only reopen port on errors (me) ++ Change fork/close/setsid structures to daemon() (me) ++ Allow user to specify udhcpd config file at run time (Steven, me) ++ Write pidfile after changing it (Steven CTR Carr ) ++ Added env var docs to udhcpc man page (Matt) ++ Standardized lowercase udhcp in documentation (me) ++ Accept packets without a UDP checksum (me) ++ Accept packets with extra garbage (me) ++ Better error handling in files.c (me) ++ Combined read_interface function to reduce COMBINED_BINARY size (me) ++ Drop calc_length(), some servers choke on smaller packets (me) ++ Try to clean some fat out (me) + +0.9.6 (011001) ++ Added bootp paramaters to server (me) ++ Added bootp paramaters to client (me) ++ Added vendor id to client (me) ++ Better pidfile handling in client and server (me) ++ Added man pages (Matt Kraai ) + +0.9.5 (010914) ++ Fixed $HOME and $PATH env passing (me) ++ Fixed client to only listen for raw packets on correct interface (me) ++ added --quit,-q option to quit after a lease is obtained (me) ++ Fixed 100% CPU utilization by client when interface is down (me) + +0.9.4 (010827) ++ Force broadcast to broken clients that request unicast (ie, MSFT 98) ++ Make install rules (Adam J. Richter ) ++ One scripts, instead of many (Adam) ++ Removed script paramater info files (env vars only) (Adam) ++ Controlling of forking behavior in client (Adam) ++ General script.c/dhcpc.c cleanups (Adam) + +0.9.3 (010820) ++ Increased debugging verbosity (me) ++ Cut trailing whitespace when reading config file (me) ++ added hostname option to client (me) ++ fixed a strncpy bug in script.c (me) ++ fixed a leaky socket in dhcpc.c (me) ++ fixed a leaky socket in dhcpd.c (me) + +0.9.2 (010810) ++ Added raw sockets to client (me) ++ alignment fixes (Mark Huang) ++ compiler warning fixes (Mark Huang) ++ client now sends parameter list (Mark Huang/me) ++ added ipttl option ++ Does now not request broadcast packets + +0.9.1 (010806) ++ Added udhcpc client ++ reorganized functions/files ++ listening socket now only binds to one interface + +0.9.0 (010720) Major rewrite, current changes, goals: ++ should not segfault on bogus packets. ++ Options can be read from sname and file fields. ++ supports all DHCP messages (release, decline, inform). ++ IP block is now specified by a range of IP's. ++ Leases file now contains lease time (relative, or absolute). ++ Just about any DHCP option is now supported. ++ DNS entries are no longer read from resolv.conf ++ Lease file can be written periodically when the process receives a SIGUSR1 ++ arpping should be supported on all arches. ++ support for DHCP relays. ++ DHCP messages can be unicast if the client requests it. ++ many, many, many other things. + +0.8.29 (000323) ++ stable(?) release + + +0.8.28 (000323) ++ removed alarm as it was causing server to go down ++ removed debugging ++ break down dhcpd.c into manageable files + + +0.8.27 (000221) ++ OFFER also sends gateway/subnet (for picky dhcp clients) ++ multiple DNS now handled from resolv.conf if available ++ multiple WINS (from dhcpd.conf) + +0.8.25 (000120) ++ now compiles *and* runs on a generic linux system + tested with a windows 98 client and the sample config + files in the samples directory. + +0.8.24 (000117) ++ makeiplist tool has basic functionality in place ++ new sample config files ++ route add -host 255.255.255.255 dev eth0 added for generic linux + +0.8.23 (000117) ++ NETtel specific fix for ignoring dhcp requests on 2nd interface + +0.8.22 (000113) ++ minor changes to compile under a generic linux system ++ minor config file location changes for a generic linux system ++ makeiplist fixes.. still incomplete.. but etting closer + +0.8.21 (000113) ++ now sends the correct server ip instead of hardcoded value ++ minor debugging fixes for critical messages + +0.8.20 (000106) ++ cut out dhcp server checking.. this was causing dialout ppp + sessions with idle time set to never time out. ++ also removed the 10 second pause before launching.. as this + was originally to stop it replying to a dhcp client + on a NETtel which was really a bad way to do it in the + first place :-) + +0.8.19 (000104) ++ fixes for route add -host on a machine that needs to run both + a DHCP client and server (dual eth box) + +0.8.18 (991220) + ++ Race conditions fixed by disabling alarm whilst the server is busy ++ Fixed continous clearing of the offered array so that it is only cleared + when it is dirty - (could change the position of when dirty is set) + +0.8.17 (991212) + +- has problems clearing out the offered array + +0.8.16 (991203) ++ Non blocking error is changes to informational as it is not really + an error + +0.8.15 (991129) ++ Servs the dns field 3 times (Nettel only) so that windows servers + dont time out whilst nettel is booting + +0.8.14 (991126) ++ added owner check for the offered array so clean out time may be + increased ++ added new func to print out chadder/MAC + +0.8.13 (991125) ++ added win95 support (w95 changed xid halfway through conversation) ++ had to change the offered array to use hardware addresses instead of xid ++ fixed re offered bug ++ added more debugging + +0.8.12 (991111) ++ debugging was real bad.. cleaned up a bit.. needs overhaul + + +0.8.11 (991110) ++ fixed up offeredAddr array to actually be used now!! offeredAddr is + used to see if another simultaneous connecting client was offered + an address that we are about to offer another client (multiple + client bug) ++ removed re_offered variable as it breaks multiple client support ++ added lease time to ACK -- doesn't work if in OFFER ++ decreased internal array clear delay to 60 seconds ++ minor findAddr bug (returning -1 instead of 0) ++ if clients xid already in offeredAddr offer the same addr and don't add a + new addr to offered (caused by a client issuing multiple DISCOVERs) + +0.8.10 (991105) ++ \n bug in arpping ++ minor debugging changes (removed printfs etc) ++ started browseiplist (not finished) + +0.8.9 (19991105) ++ fixed options array size bug (options were cut off) + +0.8.8 (19991105) ++ ignores requests from dhcpcd on the same machine + +0.8.7 (19991104) ++ don't die if we can't bind to search for existing DHCP server ++ slightly more verbose syslogging + +0.8.6 (19991103) ++ added makeiplist (not finished -- core dumps) ++ minor debug changes + +0.8.5 (19991029) ++ exits if another DHCP server is already on the network ++ added Linux Makefile + +0.8.4 (19991026) ++ minor bug fix in findaddr preventing an addr being found + +0.8.3 (19991025) ++ fixed up debugging ++ minor hwaddr issues + +0.8.2 (19991022) ++ free leases (new arpping code from dhcpcd) ++ fixed bug where crashes if no leases/iplist file ++ syslogging and debugging switch ++ serve DNS from resolv.conf ++ fixed bug where new lease added if same mac offered ++ now checks the ip is free b4 offering ++ now supports wins server + diff --git a/platform/mcu/xr871/src/net/udhcp/Makefile b/platform/mcu/xr871/src/net/udhcp/Makefile new file mode 100644 index 0000000000..41ab910f5c --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/Makefile @@ -0,0 +1,39 @@ +# +# Rules for building library +# + +# ---------------------------------------------------------------------------- +# common rules +# ---------------------------------------------------------------------------- +ROOT_PATH := ../../.. + +include $(ROOT_PATH)/gcc.mk + +# ---------------------------------------------------------------------------- +# library and objects +# ---------------------------------------------------------------------------- +LIBS := libudhcp.a + +OBJS := usr_dhcpd.o \ + arpping.o \ + files.o \ + leases.o \ + serverpacket.o \ + options.o \ + socket.o \ + packet.o \ + dhcp_time.o + +# extra flags +VER := 0.9.8 +CC_FLAGS += -DVERSION='"$(VER)"' -DXR_DHCPD +CC_FLAGS += -DDHCPD_TIMEALT \ + -DDHCPD_LWIP \ + -DDHCPD_HEAP_REPLACE_STACK \ + -DDHCPD_USRCFG \ + -DDHCPD_FREERTOS \ + -DDHCPD_ICMPPING \ + -DDHCPD_LOW_LEVEL + +# library make rules +include $(LIB_MAKE_RULES) diff --git a/platform/mcu/xr871/src/net/udhcp/README b/platform/mcu/xr871/src/net/udhcp/README new file mode 100644 index 0000000000..5f4bb78a84 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/README @@ -0,0 +1,50 @@ +udhcp server/client package readme +------------------------- + +The udhcp server/client package is primarily geared towards embedded +systems. It does however, strive to be fully functional, and RFC +compliant. + + +compile time options +------------------- + +The Makefile contains three of the compile time options: + + DEBUG: If DEBUG is defined, udhcpd will output extra debugging + output, compile with -g, and not fork to the background when run. + SYSLOG: If SYSLOG is defined, udhcpd will log all its messages + syslog, otherwise, it will attempt to log them to stdout. + + COMBINED_BINARY: If COMBINED_BINARY is define, one binary, udhcpd, + is created. If called as udhcpd, the dhcp server will be started. + If called as udhcpc, the dhcp client will be started. + +dhcpd.h contains the other two compile time options: + + LEASE_TIME: The default lease time if not specified in the config + file. + + DHCPD_CONFIG_FILE: The defualt config file to use. + +options.c contains a set of dhcp options for the client: + + name[10]: The name of the option as it will appear in scripts + + flags: The type of option, as well as if it will be requested + by the client (OPTION_REQ) + + code: The DHCP code for this option + + +busybox drop-in +-------------- +udhcp is now a drop-in component for busybox (http://busybox.net). +To update busybox to the latest revision, simply do a: + +cp *.[ch] README AUTHORS COPYING ChangeLog TODO \ + /networking/udhcp + +The only two files udhcp does not provide are config.in and +Makefile.in, so these may need to be updated from time to time. + diff --git a/platform/mcu/xr871/src/net/udhcp/README.dumpleases b/platform/mcu/xr871/src/net/udhcp/README.dumpleases new file mode 100644 index 0000000000..6367710c4f --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/README.dumpleases @@ -0,0 +1,17 @@ +udhcp lease dump (dumpleases) +---------------------------- + +dumpleases displays the leases written out by the udhcpd server. Lease +times are stored in the file by time remaining in lease (for systems +without clock that works when there is no power), or by the absolute +time that it expires in seconds from epoch. dumpleases accepts the +following command line options: + +-a, --absolute Interpret lease times as expiration time. +-r, --remaining Interpret lease times as remaining time. +-f, --file=FILE Read lease information from FILE. +-h, --help Display help. + +Note that if udhcpd has not written a leases file recently, the output +of may not be up to date. + diff --git a/platform/mcu/xr871/src/net/udhcp/README.udhcpc b/platform/mcu/xr871/src/net/udhcp/README.udhcpc new file mode 100644 index 0000000000..3591605e3c --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/README.udhcpc @@ -0,0 +1,139 @@ +udhcp client (udhcpc) +-------------------- + +The udhcp client negotiates a lease with the DHCP server and notifies +a set of scripts when a leases is obtained or lost. + + +command line options +------------------- + +The command line options for the udhcp client are: + +-c, --clientid=CLIENTID Client identifier +-H, --hostname=HOSTNAME Client hostname +-h, Alias for -H +-f, --foreground Do not fork after getting lease +-b, --background Fork to background if lease cannot be + immediately negotiated. +-i, --interface=INTERFACE Interface to use (default: eth0) +-n, --now Exit with failure if lease cannot be + immediately negotiated. +-p, --pidfile=file Store process ID of daemon in file +-q, --quit Quit after obtaining lease +-r, --request=IP IP address to request (default: none) +-s, --script=file Run file at dhcp events (default: + /usr/share/udhcpc/default.script) +-v, --version Display version + + +If the requested IP address cannot be obtained, the client accepts the +address that the server offers. + + +udhcp client scripts +------------------- + +When an event occurs, udhcpc calls the action script. The script by +default is /usr/share/udhcpc/default.script but this can be changed via +the command line arguments. The three possible arguments to the script +are: + + deconfig: This argument is used when udhcpc starts, and + when a leases is lost. The script should put the interface in an + up, but deconfigured state, ie: ifconfig $interface 0.0.0.0. + + bound: This argument is used when udhcpc moves from an + unbound, to a bound state. All of the paramaters are set in + enviromental variables, The script should configure the interface, + and set any other relavent parameters (default gateway, dns server, + etc). + + renew: This argument is used when a DHCP lease is renewed. All of + the paramaters are set in enviromental variables. This argument is + used when the interface is already configured, so the IP address, + will not change, however, the other DHCP paramaters, such as the + default gateway, subnet mask, and dns server may change. + + nak: This argument is used with udhcpc receives a NAK message. + The script with the deconfig argument will be called directly + afterwards, so no changes to the network interface are neccessary. + This hook is provided for purely informational purposes (the + message option may contain a reason for the NAK). + +The paramaters for enviromental variables are as follows: + + $HOME - The set $HOME env or "/" + $PATH - the set $PATH env or "/bin:/usr/bin:/sbin:/usr/sbin" + $1 - What action the script should perform + interface - The interface this was obtained on + ip - The obtained IP + siaddr - The bootp next server option + sname - The bootp server name option + boot_file - The bootp boot file option + subnet - The assigend subnet mask + timezone - Offset in seconds from UTC + router - A list of routers + timesvr - A list of time servers + namesvr - A list of IEN 116 name servers + dns - A list of DNS server + logsvr - A list of MIT-LCS UDP log servers + cookiesvr - A list of RFC 865 cookie servers + lprsvr - A list of LPR servers + hostname - The assigned hostname + bootsize - The length in 512 octect blocks of the bootfile + domain - The domain name of the network + swapsvr - The IP address of the client's swap server + rootpath - The path name of the client's root disk + ipttl - The TTL to use for this network + mtu - The MTU to use for this network + broadcast - The broadcast address for this network + ntpsrv - A list of NTP servers + wins - A list of WINS servers + lease - The lease time, in seconds + dhcptype - DHCP message type (safely ignored) + serverid - The IP of the server + message - Reason for a DHCPNAK + tftp - The TFTP server name + bootfile - The bootfile name + +additional options are easily added in options.c. + + +note on udhcpc's random seed +--------------------------- + +udhcpc will seed its random number generator (used for generating xid's) +by reading /dev/urandom. If you have a lot of embedded systems on the same +network, with no entropy, you can either seed /dev/urandom by a method of +your own, or doing the following on startup: + +ifconfig eth0 > /dev/urandom + +in order to seed /dev/urandom with some data (mac address) unique to your +system. If reading /dev/urandom fails, udhcpc will fall back to its old +behavior of seeding with time(0). + + +signals accepted by udhcpc +------------------------- + +udhcpc also responds to SIGUSR1 and SIGUSR2. SIGUSR1 will force a renew state, +and SIGUSR2 will force a release of the current lease, and cause udhcpc to +go into an inactive state (until it is killed, or receives a SIGUSR1). You do +not need to sleep between sending signals, as signals received are processed +sequencially in the order they are received. + + +compile time options +------------------- + +options.c contains a set of dhcp options for the client: + + name[10]: The name of the option as it will appear in scripts + + flags: The type of option, as well as if it will be requested + by the client (OPTION_REQ) + + code: The DHCP code for this option + diff --git a/platform/mcu/xr871/src/net/udhcp/README.udhcpd b/platform/mcu/xr871/src/net/udhcp/README.udhcpd new file mode 100644 index 0000000000..bc6137de37 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/README.udhcpd @@ -0,0 +1,59 @@ +udhcp server (udhcpd) +-------------------- + +The only command line argument to udhcpd is an optional specifed +config file. If no config file is specified, udhcpd uses the default +config file, /etc/udhcpd.conf. Ex: + +udhcpd /etc/udhcpd.eth1.conf + +The udhcp server employs a number of simple config files: + +udhcpd.leases +------------ + +The udhcpd.leases behavior is designed for an embedded system. The +file is written either every auto_time seconds, or when a SIGUSR1 +is received (the auto_time timer restarts if a SIGUSR1 is received). +If you send a SIGTERM to udhcpd directly after a SIGUSR1, udhcpd will +finish writing the leases file and wait for the aftermentioned script +to be executed and finish before quiting, so you do not need to sleep +between sending signals. When the file is written, a script can be +optionally called to commit the file to flash. Lease times are stored +in the file by time remaining in lease (for systems without clock +that works when there is no power), or by the absolute time that it +expires in seconds from epoch. In the remaining format, expired leases +are stored as zero. The file is of the format: + +16 byte MAC +4 byte ip address +u32 expire time +16 byte MAC +4 byte ip address +u32 expire time +. +etc. + +example: hexdump udhcpd.leases + +0000000 1000 c95a 27d9 0000 0000 0000 0000 0000 +0000010 a8c0 150a 0d00 2d29 5000 23fc 8566 0000 +0000020 0000 0000 0000 0000 a8c0 140a 0d00 4e29 +0000030 + + +udhcpd.conf +---------- + +The format is fairly simple, there is a sample file with all the +available options and comments describing them in samples/udhcpd.conf + +compile time options +------------------- + +dhcpd.h contains the other two compile time options: + + LEASE_TIME: The default lease time if not specified in the config + file. + + DHCPD_CONFIG_FILE: The defualt config file to use. diff --git a/platform/mcu/xr871/src/net/udhcp/TODO b/platform/mcu/xr871/src/net/udhcp/TODO new file mode 100644 index 0000000000..f88694a866 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/TODO @@ -0,0 +1,14 @@ +TODO +---- ++ Integrade README.*'s with manpages ++ using time(0) breaks if the system clock changes, find a portable solution ++ make failure of reading functions revert to previous value, not the default ++ sanity code for option[OPT_LEN] ++ fix aliasing (ie: eth0:0) ++ better standard linux distro support ++ make sure packet generation works on a wide varitey of arches ++ Interoperability testing ++ Hooks within the DHCP server ++ Additional bootp support in client/server ++ Make serverid option in server configurable ++ Possibly add failure message to DHCP NAK diff --git a/platform/mcu/xr871/src/net/udhcp/arpping.c b/platform/mcu/xr871/src/net/udhcp/arpping.c new file mode 100644 index 0000000000..2fad26c9ba --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/arpping.c @@ -0,0 +1,200 @@ +/* + * arpping.c + * + * Mostly stolen from: dhcpcd - DHCP client daemon + * by Yoichi Hariguchi + */ +#ifdef DHCPD_LWIP +#include +#include +#include +#else +#include +#include +#include +#include +#include +#endif + +#ifndef DHCPD_TIMEALT +#include +#else +#include "dhcp_time.h" +#endif + +#include +#include +#include +//#include + +#include "dhcpd.h" +#include "debug.h" +#include "arpping.h" + +/* args: yiaddr - what IP to ping + * ip - our ip + * mac - our arp address + * interface - interface to use + * retn: 1 addr free + * 0 addr used + * -1 error + */ + +#ifdef DHCPD_LWIP +#define ETH_P_ARP ETHTYPE_ARP +#define ARPHRD_ETHER 1 +#define ETH_P_IP ETHTYPE_IP + +#define ARPOP_REQUEST ARP_REQUEST +#endif + +/* FIXME: match response against chaddr */ +int arpping(u_int32_t yiaddr, u_int32_t ip, unsigned char *mac, char *interface) +{ + int timeout = 2; + int optval = 1; + int s; /* socket */ + int rv = 1; /* return value */ + //struct sockaddr addr; /* for interface name */ +#ifdef DHCPD_ICMPPING + char icmp_buf[50]; + struct icmp_echo_hdr *icmp_hdr = (struct icmp_echo_hdr *)icmp_buf; +#else + struct arpMsg arp; +#endif + fd_set fdset; + struct timeval tm; + time_t prevTime; +#ifdef DHCPD_ICMPPING + struct sockaddr_in sl; +#else + struct sockaddr_ll sl; +#endif +#ifdef DHCPD_ICMPPING + if ((s = socket(AF_INET, SOCK_RAW, IPPROTO_ICMP)) == -1) { +#else + if ((s = socket (AF_PACKET, SOCK_RAW, htons(ETH_P_ARP))) == -1) { +#endif + DHCPD_LOG(LOG_ERR, "arp:Could not open raw socket"); + return -1; + } + + if (setsockopt(s, SOL_SOCKET, SO_BROADCAST, &optval, sizeof(optval)) == -1) { + DHCPD_LOG(LOG_ERR, "arp:Could not setsocketopt on raw socket"); +#ifdef DHCPD_LWIP + closesocket(s); +#else + close(s); +#endif + return -1; + } + DHCPD_LOG(LOG_INFO, "arp : check ip %s\n", inet_ntoa(yiaddr)); + /* send arp request */ +#ifdef DHCPD_ICMPPING + memset(icmp_buf, 0, sizeof(icmp_buf)); +#else + memset(&arp, 0, sizeof(arp)); +#endif +#ifndef DHCPD_ICMPPING +#ifdef DHCPD_LWIP + memcpy(arp.ethhdr.dest.addr, MAC_BCAST_ADDR, 6); /* MAC DA */ + memcpy(arp.ethhdr.src.addr, mac, 6); /* MAC SA */ + arp.ethhdr.type = htons(ETH_P_ARP); /* protocol type (Ethernet) */ +#else + memcpy(arp.ethhdr.h_dest, MAC_BCAST_ADDR, 6); /* MAC DA */ + memcpy(arp.ethhdr.h_source, mac, 6); /* MAC SA */ + arp.ethhdr.h_proto = htons(ETH_P_ARP); /* protocol type (Ethernet) */ +#endif +#endif +#ifdef DHCPD_ICMPPING + ICMPH_TYPE_SET(icmp_hdr, ICMP_ECHO); + ICMPH_CODE_SET(icmp_hdr, 0); + icmp_hdr->chksum = 0; + icmp_hdr->id = 0; + icmp_hdr->seqno = 0; + icmp_hdr->chksum = inet_chksum(icmp_hdr, sizeof(struct icmp_echo_hdr)); +#else + arp.htype = htons(ARPHRD_ETHER); /* hardware type */ + arp.ptype = htons(ETH_P_IP); /* protocol type (ARP message) */ + arp.hlen = 6; /* hardware address length */ + arp.plen = 4; /* protocol address length */ + arp.operation = htons(ARPOP_REQUEST); /* ARP op code */ +#endif +#ifndef DHCPD_ICMPPING +#ifndef DHCPD_LWIP + *((u_int *) arp.sInaddr) = ip; /* source IP address */ +#else + memcpy(arp.sInaddr,(char *)&ip, 4); +#endif + memcpy(arp.sHaddr, mac, 6); /* source hardware address */ +#ifndef DHCPD_LWIP + *((u_int *) arp.tInaddr) = yiaddr; /* target IP address */ +#else + memcpy(arp.tInaddr,(char *)&yiaddr, 4); +#endif +#endif + //memset(&addr, 0, sizeof(addr)); + //strcpy(addr.sa_data, interface); + //if (sendto(s, &arp, sizeof(arp), 0, &addr, sizeof(addr)) < 0) + memset(&sl, 0, sizeof(sl)); +#ifdef DHCPD_ICMPPING + sl.sin_len = sizeof(sl); + sl.sin_family = AF_INET; + sl.sin_addr.s_addr = yiaddr; +#else + sl.sll_family = AF_PACKET; + //sl.sll_addr = MAC_SOURCE; + //sl.sll_halen = ETH_ALEN; + sl.sll_ifindex = 0x2; +#endif +#ifdef DHCPD_ICMPPING + if (sendto(s, icmp_buf, sizeof(icmp_buf), 0, (struct sockaddr*)&sl, sizeof(sl)) < 0) +#else + if (sendto(s, &arp, sizeof(arp), 0, (struct sockaddr*)&sl, sizeof(sl)) < 0) +#endif + rv = 0; + + /* wait arp reply, and check it */ + tm.tv_usec = 0; + time(&prevTime); + + while (timeout > 0) { + FD_ZERO(&fdset); + FD_SET(s, &fdset); + tm.tv_sec = timeout; + if (select(s + 1, &fdset, (fd_set *) NULL, (fd_set *) NULL, &tm) < 0) { + DEBUG(LOG_ERR, "Error on ARPING request: %s", strerror(errno)); + if (errno != EINTR) rv = 0; + } else if (FD_ISSET(s, &fdset)) { +#ifdef DHCPD_ICMPPING + if (recv(s, icmp_buf, sizeof(icmp_buf), 0) < 0 ) rv = 0; + struct ip_hdr *iphdr = (struct ip_hdr *)icmp_buf; + icmp_hdr = (struct icmp_echo_hdr *)(icmp_buf + IPH_HL(iphdr) * 4); +#else + if (recv(s, &arp, sizeof(arp), 0) < 0 ) rv = 0; + u_int *tsInaddr = (u_int *)arp.sInaddr; +#endif +#ifdef DHCPD_ICMPPING + if (iphdr->src.addr == yiaddr && icmp_hdr->type == ICMP_ER) { +#else + if (arp.operation == htons(ARP_REPLY) && + bcmp(arp.tHaddr, mac, 6) == 0 && + *(/*(u_int *) arp.sInaddr*/tsInaddr) == yiaddr) { +#endif + DEBUG(LOG_INFO, "Valid arp reply receved for this address"); + rv = 0; + break; + } + } + timeout -= time(NULL) - prevTime; + time(&prevTime); + + } +#ifdef DHCPD_LWIP + closesocket(s); +#else + close(s); +#endif + DEBUG(LOG_INFO, "%salid arp replies for this address", rv ? "No v" : "V"); + return rv; +} diff --git a/platform/mcu/xr871/src/net/udhcp/arpping.h b/platform/mcu/xr871/src/net/udhcp/arpping.h new file mode 100644 index 0000000000..5c5a6ec351 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/arpping.h @@ -0,0 +1,41 @@ +/* + * arpping .h + */ + +#ifndef ARPPING_H +#define ARPPING_H + +#ifdef DHCPD_LWIP +#include "netif/etharp.h" +#else +#include +#include +#include +#include +#endif + +#ifdef DHCPD_USRCFG +#include "dhcpd_cfg.h" +#endif +struct arpMsg { +#ifdef DHCPD_LWIP + struct eth_hdr ethhdr; /* Ethernet header */ +#else + struct ethhdr ethhdr; /* Ethernet header */ +#endif + u_short htype; /* hardware type (must be ARPHRD_ETHER) */ + u_short ptype; /* protocol type (must be ETH_P_IP) */ + u_char hlen; /* hardware address length (must be 6) */ + u_char plen; /* protocol address length (must be 4) */ + u_short operation; /* ARP opcode */ + u_char sHaddr[6]; /* sender's hardware address */ + u_char sInaddr[4]; /* sender's IP address */ + u_char tHaddr[6]; /* target's hardware address */ + u_char tInaddr[4]; /* target's IP address */ + u_char pad[18]; /* pad for min. Ethernet payload (60 bytes) */ +}; + +/* function prototypes */ +int arpping(u_int32_t yiaddr, u_int32_t ip, unsigned char *arp, char *interface); + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/clientpacket.c b/platform/mcu/xr871/src/net/udhcp/clientpacket.c new file mode 100644 index 0000000000..6c32f922ea --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/clientpacket.c @@ -0,0 +1,253 @@ +/* clientpacket.c + * + * Packet generation and dispatching functions for the DHCP client. + * + * Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#if __GLIBC__ >=2 && __GLIBC_MINOR >= 1 +#include +#include +#elif __LINUX +#include +#include +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "dhcpd.h" +#include "packet.h" +#include "options.h" +#include "dhcpc.h" +#include "debug.h" + + +/* Create a random xid */ +unsigned long random_xid(void) +{ + static int initialized; + if (!initialized) { + int fd; + unsigned long seed; + + fd = open("/dev/urandom", 0); + if (fd < 0 || read(fd, &seed, sizeof(seed)) < 0) { + LOG(LOG_WARNING, "Could not load seed from /dev/urandom: %s", + strerror(errno)); + seed = time(0); + } + if (fd >= 0) close(fd); + srand(seed); + initialized++; + } + return rand(); +} + + +/* initialize a packet with the proper defaults */ +static void init_packet(struct dhcpMessage *packet, char type) +{ + struct vendor { + char vendor, length; + char str[sizeof("udhcp "VERSION)]; + } vendor_id = { DHCP_VENDOR, sizeof("udhcp "VERSION) - 1, "udhcp "VERSION}; + + init_header(packet, type); + memcpy(packet->chaddr, client_config.arp, 6); + add_option_string(packet->options, client_config.clientid); + if (client_config.hostname) add_option_string(packet->options, client_config.hostname); + add_option_string(packet->options, (unsigned char *) &vendor_id); +} + + +/* Add a paramater request list for stubborn DHCP servers. Pull the data + * from the struct in options.c. Don't do bounds checking here because it + * goes towards the head of the packet. */ +static void add_requests(struct dhcpMessage *packet) +{ + int end = end_option(packet->options); + int i, len = 0; + + packet->options[end + OPT_CODE] = DHCP_PARAM_REQ; + for (i = 0; options[i].code; i++) + if (options[i].flags & OPTION_REQ) + packet->options[end + OPT_DATA + len++] = options[i].code; + packet->options[end + OPT_LEN] = len; + packet->options[end + OPT_DATA + len] = DHCP_END; + +} + + +/* Broadcast a DHCP discover packet to the network, with an optionally requested IP */ +int send_discover(unsigned long xid, unsigned long requested) +{ + struct dhcpMessage packet; + + init_packet(&packet, DHCPDISCOVER); + packet.xid = xid; + if (requested) + add_simple_option(packet.options, DHCP_REQUESTED_IP, requested); + + add_requests(&packet); + LOG(LOG_DEBUG, "Sending discover..."); + return raw_packet(&packet, INADDR_ANY, CLIENT_PORT, INADDR_BROADCAST, + SERVER_PORT, MAC_BCAST_ADDR, client_config.ifindex); +} + + +/* Broadcasts a DHCP request message */ +int send_selecting(unsigned long xid, unsigned long server, unsigned long requested) +{ + struct dhcpMessage packet; + struct in_addr addr; + + init_packet(&packet, DHCPREQUEST); + packet.xid = xid; + + add_simple_option(packet.options, DHCP_REQUESTED_IP, requested); + add_simple_option(packet.options, DHCP_SERVER_ID, server); + + add_requests(&packet); + addr.s_addr = requested; + LOG(LOG_DEBUG, "Sending select for %s...", inet_ntoa(addr)); + return raw_packet(&packet, INADDR_ANY, CLIENT_PORT, INADDR_BROADCAST, + SERVER_PORT, MAC_BCAST_ADDR, client_config.ifindex); +} + + +/* Unicasts or broadcasts a DHCP renew message */ +int send_renew(unsigned long xid, unsigned long server, unsigned long ciaddr) +{ + struct dhcpMessage packet; + int ret = 0; + + init_packet(&packet, DHCPREQUEST); + packet.xid = xid; + packet.ciaddr = ciaddr; + + add_requests(&packet); + LOG(LOG_DEBUG, "Sending renew..."); + if (server) + ret = kernel_packet(&packet, ciaddr, CLIENT_PORT, server, SERVER_PORT); + else ret = raw_packet(&packet, INADDR_ANY, CLIENT_PORT, INADDR_BROADCAST, + SERVER_PORT, MAC_BCAST_ADDR, client_config.ifindex); + return ret; +} + + +/* Unicasts a DHCP release message */ +int send_release(unsigned long server, unsigned long ciaddr) +{ + struct dhcpMessage packet; + + init_packet(&packet, DHCPRELEASE); + packet.xid = random_xid(); + packet.ciaddr = ciaddr; + + add_simple_option(packet.options, DHCP_REQUESTED_IP, ciaddr); + add_simple_option(packet.options, DHCP_SERVER_ID, server); + + LOG(LOG_DEBUG, "Sending release..."); + return kernel_packet(&packet, ciaddr, CLIENT_PORT, server, SERVER_PORT); +} + + +/* return -1 on errors that are fatal for the socket, -2 for those that aren't */ +int get_raw_packet(struct dhcpMessage *payload, int fd) +{ + int bytes; + struct udp_dhcp_packet packet; + u_int32_t source, dest; + u_int16_t check; + + memset(&packet, 0, sizeof(struct udp_dhcp_packet)); + bytes = read(fd, &packet, sizeof(struct udp_dhcp_packet)); + if (bytes < 0) { + DEBUG(LOG_INFO, "couldn't read on raw listening socket -- ignoring"); + usleep(500000); /* possible down interface, looping condition */ + return -1; + } + + if (bytes < (int) (sizeof(struct iphdr) + sizeof(struct udphdr))) { + DEBUG(LOG_INFO, "message too short, ignoring"); + return -2; + } + + if (bytes < ntohs(packet.ip.tot_len)) { + DEBUG(LOG_INFO, "Truncated packet"); + return -2; + } + + /* ignore any extra garbage bytes */ + bytes = ntohs(packet.ip.tot_len); + + /* Make sure its the right packet for us, and that it passes sanity checks */ + if (packet.ip.protocol != IPPROTO_UDP || packet.ip.version != IPVERSION || + packet.ip.ihl != sizeof(packet.ip) >> 2 || packet.udp.dest != htons(CLIENT_PORT) || + bytes > (int) sizeof(struct udp_dhcp_packet) || + ntohs(packet.udp.len) != (short) (bytes - sizeof(packet.ip))) { + DEBUG(LOG_INFO, "unrelated/bogus packet"); + return -2; + } + + /* check IP checksum */ + check = packet.ip.check; + packet.ip.check = 0; + if (check != checksum(&(packet.ip), sizeof(packet.ip))) { + DEBUG(LOG_INFO, "bad IP header checksum, ignoring"); + return -1; + } + + /* verify the UDP checksum by replacing the header with a psuedo header */ + source = packet.ip.saddr; + dest = packet.ip.daddr; + check = packet.udp.check; + packet.udp.check = 0; + memset(&packet.ip, 0, sizeof(packet.ip)); + + packet.ip.protocol = IPPROTO_UDP; + packet.ip.saddr = source; + packet.ip.daddr = dest; + packet.ip.tot_len = packet.udp.len; /* cheat on the psuedo-header */ + if (check && check != checksum(&packet, bytes)) { + DEBUG(LOG_ERR, "packet with bad UDP checksum received, ignoring"); + return -2; + } + + memcpy(payload, &(packet.data), bytes - (sizeof(packet.ip) + sizeof(packet.udp))); + + if (ntohl(payload->cookie) != DHCP_MAGIC) { + LOG(LOG_ERR, "received bogus message (bad magic) -- ignoring"); + return -2; + } + DEBUG(LOG_INFO, "oooooh!!! got some!"); + return bytes - (sizeof(packet.ip) + sizeof(packet.udp)); + +} + diff --git a/platform/mcu/xr871/src/net/udhcp/clientpacket.h b/platform/mcu/xr871/src/net/udhcp/clientpacket.h new file mode 100644 index 0000000000..2a6facbc84 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/clientpacket.h @@ -0,0 +1,12 @@ +#ifndef _CLIENTPACKET_H +#define _CLIENTPACKET_H + +unsigned long random_xid(void); +int send_discover(unsigned long xid, unsigned long requested); +int send_selecting(unsigned long xid, unsigned long server, unsigned long requested); +int send_renew(unsigned long xid, unsigned long server, unsigned long ciaddr); +int send_renew(unsigned long xid, unsigned long server, unsigned long ciaddr); +int send_release(unsigned long server, unsigned long ciaddr); +int get_raw_packet(struct dhcpMessage *payload, int fd); + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/debug.h b/platform/mcu/xr871/src/net/udhcp/debug.h new file mode 100644 index 0000000000..2650c772e3 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/debug.h @@ -0,0 +1,48 @@ +#ifndef _DEBUG_H +#define _DEBUG_H + +#include "libbb_udhcp.h" + +#include +#ifdef SYSLOG +#include +#endif + +//#define DEBUG +#define DHCPD_LOGD + +#ifdef SYSLOG +# define LOG(level, str, args...) do { printf(str, ## args); \ + printf("\n"); \ + syslog(level, str, ## args); } while(0) +# define OPEN_LOG(name) openlog(name, 0, 0) +#define CLOSE_LOG() closelog() +#else +# define LOG_EMERG "EMERGENCY!" +# define LOG_ALERT "ALERT!" +# define LOG_CRIT "critical!" +# define LOG_WARNING "warning" +# define LOG_ERR "error" +# define LOG_INFO "info" +# define LOG_DEBUG "debug" +#ifdef DHCPD_LOGD +# define DHCPD_LOG(level, str, args...) do { printf("%s, ", level); \ + printf(str, ## args); \ + printf("\n"); } while(0) +#else +# define DHCPD_LOG(level, str, args...) do {; } while(0) +#endif +# define OPEN_LOG(name) do {;} while(0) +#define CLOSE_LOG() do {;} while(0) +#endif + + +#ifdef DEBUG +# undef DEBUG +# define DEBUG(level, str, args...) DHCPD_LOG(level, str, ## args) +# define DEBUGGING +#else +# define DEBUG(level, str, args...) do {;} while(0) +#endif + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/dhcp_time.c b/platform/mcu/xr871/src/net/udhcp/dhcp_time.c new file mode 100644 index 0000000000..a6ec7483d1 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcp_time.c @@ -0,0 +1,13 @@ +#ifdef DHCPD_TIMEALT +#include "kernel/os/os_time.h" +#include "dhcp_time.h" + +time_t dhcp_time(time_t *timer) +{ + if (!timer) + return (time_t)OS_GetTime(); + *timer = (time_t)OS_GetTime(); + return *timer; +} + +#endif \ No newline at end of file diff --git a/platform/mcu/xr871/src/net/udhcp/dhcp_time.h b/platform/mcu/xr871/src/net/udhcp/dhcp_time.h new file mode 100644 index 0000000000..155a5cceb3 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcp_time.h @@ -0,0 +1,12 @@ +#ifndef DHCP_TMER_H_H +#define DHCP_TMER_H_H + +#ifdef DHCPD_TIMEALT +#include +time_t dhcp_time(time_t *timer); + +#define time dhcp_time + +#endif + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/dhcpc.c b/platform/mcu/xr871/src/net/udhcp/dhcpc.c new file mode 100644 index 0000000000..7b13f988e1 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcpc.c @@ -0,0 +1,560 @@ +/* dhcpc.c + * + * udhcp DHCP client + * + * Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dhcpd.h" +#include "dhcpc.h" +#include "options.h" +#include "clientpacket.h" +#include "packet.h" +#include "script.h" +#include "socket.h" +#include "debug.h" +#include "pidfile.h" + +static int state; +static unsigned long requested_ip; /* = 0 */ +static unsigned long server_addr; +static unsigned long timeout; +static int packet_num; /* = 0 */ +static int fd; +static int signal_pipe[2]; + +#define LISTEN_NONE 0 +#define LISTEN_KERNEL 1 +#define LISTEN_RAW 2 +static int listen_mode; + +#define DEFAULT_SCRIPT "/usr/share/udhcpc/default.script" + +struct client_config_t client_config = { + /* Default options. */ + abort_if_no_lease: 0, + foreground: 0, + quit_after_lease: 0, + background_if_no_lease: 0, + interface: "eth0", + pidfile: NULL, + script: DEFAULT_SCRIPT, + clientid: NULL, + hostname: NULL, + ifindex: 0, + arp: "\0\0\0\0\0\0", /* appease gcc-3.0 */ +}; + +#ifndef BB_VER +static void show_usage(void) +{ + printf( +"Usage: udhcpc [OPTIONS]\n\n" +" -c, --clientid=CLIENTID Client identifier\n" +" -H, --hostname=HOSTNAME Client hostname\n" +" -h Alias for -H\n" +" -f, --foreground Do not fork after getting lease\n" +" -b, --background Fork to background if lease cannot be\n" +" immediately negotiated.\n" +" -i, --interface=INTERFACE Interface to use (default: eth0)\n" +" -n, --now Exit with failure if lease cannot be\n" +" immediately negotiated.\n" +" -p, --pidfile=file Store process ID of daemon in file\n" +" -q, --quit Quit after obtaining lease\n" +" -r, --request=IP IP address to request (default: none)\n" +" -s, --script=file Run file at dhcp events (default:\n" +" " DEFAULT_SCRIPT ")\n" +" -v, --version Display version\n" + ); + exit(0); +} +#endif + + +/* just a little helper */ +static void change_mode(int new_mode) +{ + DEBUG(LOG_INFO, "entering %s listen mode", + new_mode ? (new_mode == 1 ? "kernel" : "raw") : "none"); + close(fd); + fd = -1; + listen_mode = new_mode; +} + + +/* perform a renew */ +static void perform_renew(void) +{ + LOG(LOG_INFO, "Performing a DHCP renew"); + switch (state) { + case BOUND: + change_mode(LISTEN_KERNEL); + case RENEWING: + case REBINDING: + state = RENEW_REQUESTED; + break; + case RENEW_REQUESTED: /* impatient are we? fine, square 1 */ + run_script(NULL, "deconfig"); + case REQUESTING: + case RELEASED: + change_mode(LISTEN_RAW); + state = INIT_SELECTING; + break; + case INIT_SELECTING: + } + + /* start things over */ + packet_num = 0; + + /* Kill any timeouts because the user wants this to hurry along */ + timeout = 0; +} + + +/* perform a release */ +static void perform_release(void) +{ + char buffer[16]; + struct in_addr temp_addr; + + /* send release packet */ + if (state == BOUND || state == RENEWING || state == REBINDING) { + temp_addr.s_addr = server_addr; + sprintf(buffer, "%s", inet_ntoa(temp_addr)); + temp_addr.s_addr = requested_ip; + LOG(LOG_INFO, "Unicasting a release of %s to %s", + inet_ntoa(temp_addr), buffer); + send_release(server_addr, requested_ip); /* unicast */ + run_script(NULL, "deconfig"); + } + LOG(LOG_INFO, "Entering released state"); + + change_mode(LISTEN_NONE); + state = RELEASED; + timeout = 0x7fffffff; +} + + +/* Exit and cleanup */ +static void exit_client(int retval) +{ + pidfile_delete(client_config.pidfile); + CLOSE_LOG(); + exit(retval); +} + + +/* Signal handler */ +static void signal_handler(int sig) +{ + if (send(signal_pipe[1], &sig, sizeof(sig), MSG_DONTWAIT) < 0) { + LOG(LOG_ERR, "Could not send signal: %s", + strerror(errno)); + } +} + + +static void background(void) +{ + int pid_fd; + + pid_fd = pidfile_acquire(client_config.pidfile); /* hold lock during fork. */ + while (pid_fd >= 0 && pid_fd < 3) pid_fd = dup(pid_fd); /* don't let daemon close it */ + if (daemon(0, 0) == -1) { + perror("fork"); + exit_client(1); + } + client_config.foreground = 1; /* Do not fork again. */ + pidfile_write_release(pid_fd); +} + + +#ifdef COMBINED_BINARY +int udhcpc_main(int argc, char *argv[]) +#else +int main(int argc, char *argv[]) +#endif +{ + unsigned char *temp, *message; + unsigned long t1 = 0, t2 = 0, xid = 0; + unsigned long start = 0, lease; + fd_set rfds; + int retval; + struct timeval tv; + int c, len; + struct dhcpMessage packet; + struct in_addr temp_addr; + int pid_fd; + time_t now; + int max_fd; + int sig; + + static struct option arg_options[] = { + {"clientid", required_argument, 0, 'c'}, + {"foreground", no_argument, 0, 'f'}, + {"background", no_argument, 0, 'b'}, + {"hostname", required_argument, 0, 'H'}, + {"hostname", required_argument, 0, 'h'}, + {"interface", required_argument, 0, 'i'}, + {"now", no_argument, 0, 'n'}, + {"pidfile", required_argument, 0, 'p'}, + {"quit", no_argument, 0, 'q'}, + {"request", required_argument, 0, 'r'}, + {"script", required_argument, 0, 's'}, + {"version", no_argument, 0, 'v'}, + {"help", no_argument, 0, '?'}, + {0, 0, 0, 0} + }; + + /* get options */ + while (1) { + int option_index = 0; + c = getopt_long(argc, argv, "c:fbH:h:i:np:qr:s:v", arg_options, &option_index); + if (c == -1) break; + + switch (c) { + case 'c': + len = strlen(optarg) > 255 ? 255 : strlen(optarg); + if (client_config.clientid) free(client_config.clientid); + client_config.clientid = xmalloc(len + 2); + client_config.clientid[OPT_CODE] = DHCP_CLIENT_ID; + client_config.clientid[OPT_LEN] = len; + client_config.clientid[OPT_DATA] = '\0'; + strncpy(client_config.clientid + OPT_DATA, optarg, len); + break; + case 'f': + client_config.foreground = 1; + break; + case 'b': + client_config.background_if_no_lease = 1; + break; + case 'h': + case 'H': + len = strlen(optarg) > 255 ? 255 : strlen(optarg); + if (client_config.hostname) free(client_config.hostname); + client_config.hostname = xmalloc(len + 2); + client_config.hostname[OPT_CODE] = DHCP_HOST_NAME; + client_config.hostname[OPT_LEN] = len; + strncpy(client_config.hostname + 2, optarg, len); + break; + case 'i': + client_config.interface = optarg; + break; + case 'n': + client_config.abort_if_no_lease = 1; + break; + case 'p': + client_config.pidfile = optarg; + break; + case 'q': + client_config.quit_after_lease = 1; + break; + case 'r': + requested_ip = inet_addr(optarg); + break; + case 's': + client_config.script = optarg; + break; + case 'v': + printf("udhcpcd, version %s\n\n", VERSION); + exit_client(0); + break; + default: + show_usage(); + } + } + + OPEN_LOG("udhcpc"); + LOG(LOG_INFO, "udhcp client (v%s) started", VERSION); + + pid_fd = pidfile_acquire(client_config.pidfile); + pidfile_write_release(pid_fd); + + if (read_interface(client_config.interface, &client_config.ifindex, + NULL, client_config.arp) < 0) + exit_client(1); + + if (!client_config.clientid) { + client_config.clientid = xmalloc(6 + 3); + client_config.clientid[OPT_CODE] = DHCP_CLIENT_ID; + client_config.clientid[OPT_LEN] = 7; + client_config.clientid[OPT_DATA] = 1; + memcpy(client_config.clientid + 3, client_config.arp, 6); + } + + /* setup signal handlers */ + socketpair(AF_UNIX, SOCK_STREAM, 0, signal_pipe); + signal(SIGUSR1, signal_handler); + signal(SIGUSR2, signal_handler); + signal(SIGTERM, signal_handler); + + state = INIT_SELECTING; + run_script(NULL, "deconfig"); + change_mode(LISTEN_RAW); + + for (;;) { + + tv.tv_sec = timeout - time(0); + tv.tv_usec = 0; + FD_ZERO(&rfds); + + if (listen_mode != LISTEN_NONE && fd < 0) { + if (listen_mode == LISTEN_KERNEL) + fd = listen_socket(INADDR_ANY, CLIENT_PORT, client_config.interface); + else + fd = raw_socket(client_config.ifindex); + if (fd < 0) { + LOG(LOG_ERR, "FATAL: couldn't listen on socket, %s", strerror(errno)); + exit_client(0); + } + } + if (fd >= 0) FD_SET(fd, &rfds); + FD_SET(signal_pipe[0], &rfds); + + if (tv.tv_sec > 0) { + DEBUG(LOG_INFO, "Waiting on select...\n"); + max_fd = signal_pipe[0] > fd ? signal_pipe[0] : fd; + retval = select(max_fd + 1, &rfds, NULL, NULL, &tv); + } else retval = 0; /* If we already timed out, fall through */ + + now = time(0); + if (retval == 0) { + /* timeout dropped to zero */ + switch (state) { + case INIT_SELECTING: + if (packet_num < 3) { + if (packet_num == 0) + xid = random_xid(); + + /* send discover packet */ + send_discover(xid, requested_ip); /* broadcast */ + + timeout = now + ((packet_num == 2) ? 4 : 2); + packet_num++; + } else { + if (client_config.background_if_no_lease) { + LOG(LOG_INFO, "No lease, forking to background."); + background(); + } else if (client_config.abort_if_no_lease) { + LOG(LOG_INFO, "No lease, failing."); + exit_client(1); + } + /* wait to try again */ + packet_num = 0; + timeout = now + 60; + } + break; + case RENEW_REQUESTED: + case REQUESTING: + if (packet_num < 3) { + /* send request packet */ + if (state == RENEW_REQUESTED) + send_renew(xid, server_addr, requested_ip); /* unicast */ + else send_selecting(xid, server_addr, requested_ip); /* broadcast */ + + timeout = now + ((packet_num == 2) ? 10 : 2); + packet_num++; + } else { + /* timed out, go back to init state */ + if (state == RENEW_REQUESTED) run_script(NULL, "deconfig"); + state = INIT_SELECTING; + timeout = now; + packet_num = 0; + change_mode(LISTEN_RAW); + } + break; + case BOUND: + /* Lease is starting to run out, time to enter renewing state */ + state = RENEWING; + change_mode(LISTEN_KERNEL); + DEBUG(LOG_INFO, "Entering renew state"); + /* fall right through */ + case RENEWING: + /* Either set a new T1, or enter REBINDING state */ + if ((t2 - t1) <= (lease / 14400 + 1)) { + /* timed out, enter rebinding state */ + state = REBINDING; + timeout = now + (t2 - t1); + DEBUG(LOG_INFO, "Entering rebinding state"); + } else { + /* send a request packet */ + send_renew(xid, server_addr, requested_ip); /* unicast */ + + t1 = (t2 - t1) / 2 + t1; + timeout = t1 + start; + } + break; + case REBINDING: + /* Either set a new T2, or enter INIT state */ + if ((lease - t2) <= (lease / 14400 + 1)) { + /* timed out, enter init state */ + state = INIT_SELECTING; + LOG(LOG_INFO, "Lease lost, entering init state"); + run_script(NULL, "deconfig"); + timeout = now; + packet_num = 0; + change_mode(LISTEN_RAW); + } else { + /* send a request packet */ + send_renew(xid, 0, requested_ip); /* broadcast */ + + t2 = (lease - t2) / 2 + t2; + timeout = t2 + start; + } + break; + case RELEASED: + /* yah, I know, *you* say it would never happen */ + timeout = 0x7fffffff; + break; + } + } else if (retval > 0 && listen_mode != LISTEN_NONE && FD_ISSET(fd, &rfds)) { + /* a packet is ready, read it */ + + if (listen_mode == LISTEN_KERNEL) + len = get_packet(&packet, fd); + else len = get_raw_packet(&packet, fd); + + if (len == -1 && errno != EINTR) { + DEBUG(LOG_INFO, "error on read, %s, reopening socket", strerror(errno)); + change_mode(listen_mode); /* just close and reopen */ + } + if (len < 0) continue; + + if (packet.xid != xid) { + DEBUG(LOG_INFO, "Ignoring XID %lx (our xid is %lx)", + (unsigned long) packet.xid, xid); + continue; + } + + if ((message = get_option(&packet, DHCP_MESSAGE_TYPE)) == NULL) { + DEBUG(LOG_ERR, "couldnt get option from packet -- ignoring"); + continue; + } + + switch (state) { + case INIT_SELECTING: + /* Must be a DHCPOFFER to one of our xid's */ + if (*message == DHCPOFFER) { + if ((temp = get_option(&packet, DHCP_SERVER_ID))) { + memcpy(&server_addr, temp, 4); + xid = packet.xid; + requested_ip = packet.yiaddr; + + /* enter requesting state */ + state = REQUESTING; + timeout = now; + packet_num = 0; + } else { + DEBUG(LOG_ERR, "No server ID in message"); + } + } + break; + case RENEW_REQUESTED: + case REQUESTING: + case RENEWING: + case REBINDING: + if (*message == DHCPACK) { + if (!(temp = get_option(&packet, DHCP_LEASE_TIME))) { + LOG(LOG_ERR, "No lease time with ACK, using 1 hour lease"); + lease = 60 * 60; + } else { + memcpy(&lease, temp, 4); + lease = ntohl(lease); + } + + /* enter bound state */ + t1 = lease / 2; + + /* little fixed point for n * .875 */ + t2 = (lease * 0x7) >> 3; + temp_addr.s_addr = packet.yiaddr; + LOG(LOG_INFO, "Lease of %s obtained, lease time %ld", + inet_ntoa(temp_addr), lease); + start = now; + timeout = t1 + start; + requested_ip = packet.yiaddr; + run_script(&packet, + ((state == RENEWING || state == REBINDING) ? "renew" : "bound")); + + state = BOUND; + change_mode(LISTEN_NONE); + if (client_config.quit_after_lease) + exit_client(0); + if (!client_config.foreground) + background(); + + } else if (*message == DHCPNAK) { + /* return to init state */ + LOG(LOG_INFO, "Received DHCP NAK"); + run_script(&packet, "nak"); + if (state != REQUESTING) + run_script(NULL, "deconfig"); + state = INIT_SELECTING; + timeout = now; + requested_ip = 0; + packet_num = 0; + change_mode(LISTEN_RAW); + sleep(3); /* avoid excessive network traffic */ + } + break; + /* case BOUND, RELEASED: - ignore all packets */ + } + } else if (retval > 0 && FD_ISSET(signal_pipe[0], &rfds)) { + if (read(signal_pipe[0], &sig, sizeof(signal)) < 0) { + DEBUG(LOG_ERR, "Could not read signal: %s", + strerror(errno)); + continue; /* probably just EINTR */ + } + switch (sig) { + case SIGUSR1: + perform_renew(); + break; + case SIGUSR2: + perform_release(); + break; + case SIGTERM: + LOG(LOG_INFO, "Received SIGTERM"); + exit_client(0); + } + } else if (retval == -1 && errno == EINTR) { + /* a signal was caught */ + } else { + /* An error occured */ + DEBUG(LOG_ERR, "Error on select"); + } + + } + return 0; +} + diff --git a/platform/mcu/xr871/src/net/udhcp/dhcpc.h b/platform/mcu/xr871/src/net/udhcp/dhcpc.h new file mode 100644 index 0000000000..52157f5c81 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcpc.h @@ -0,0 +1,34 @@ +/* dhcpc.h */ +#ifndef _DHCPC_H +#define _DHCPC_H + +#include "libbb_udhcp.h" + +#define INIT_SELECTING 0 +#define REQUESTING 1 +#define BOUND 2 +#define RENEWING 3 +#define REBINDING 4 +#define INIT_REBOOT 5 +#define RENEW_REQUESTED 6 +#define RELEASED 7 + + +struct client_config_t { + char foreground; /* Do not fork */ + char quit_after_lease; /* Quit after obtaining lease */ + char abort_if_no_lease; /* Abort if no lease */ + char background_if_no_lease; /* Fork to background if no lease */ + char *interface; /* The name of the interface to use */ + char *pidfile; /* Optionally store the process ID */ + char *script; /* User script to run at dhcp events */ + unsigned char *clientid; /* Optional client id to use */ + unsigned char *hostname; /* Optional hostname to use */ + int ifindex; /* Index number of the interface to use */ + unsigned char arp[6]; /* Our arp address */ +}; + +extern struct client_config_t client_config; + + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/dhcpd.c b/platform/mcu/xr871/src/net/udhcp/dhcpd.c new file mode 100644 index 0000000000..a6968faede --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcpd.c @@ -0,0 +1,289 @@ +/* dhcpd.c + * + * udhcp Server + * Copyright (C) 1999 Matthew Ramsay + * Chris Trew + * + * Rewrite by Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "debug.h" +#include "dhcpd.h" +#include "arpping.h" +#include "socket.h" +#include "options.h" +#include "files.h" +#include "leases.h" +#include "packet.h" +#include "serverpacket.h" +#include "pidfile.h" + + +/* globals */ +struct dhcpOfferedAddr *leases; +struct server_config_t server_config; +static int signal_pipe[2]; + +/* Exit and cleanup */ +static void exit_server(int retval) +{ + pidfile_delete(server_config.pidfile); + CLOSE_LOG(); + exit(retval); +} + + +/* Signal handler */ +static void signal_handler(int sig) +{ + if (send(signal_pipe[1], &sig, sizeof(sig), MSG_DONTWAIT) < 0) { + LOG(LOG_ERR, "Could not send signal: %s", + strerror(errno)); + } +} + + +#ifdef COMBINED_BINARY +int udhcpd_main(int argc, char *argv[]) +#else +int main(int argc, char *argv[]) +#endif +{ + fd_set rfds; + struct timeval tv; + int server_socket = -1; + int bytes, retval; + struct dhcpMessage packet; + unsigned char *state; + unsigned char *server_id, *requested; + u_int32_t server_id_align, requested_align; + unsigned long timeout_end; + struct option_set *option; + struct dhcpOfferedAddr *lease; + int pid_fd; + int max_sock; + int sig; + + OPEN_LOG("udhcpd"); + LOG(LOG_INFO, "udhcp server (v%s) started", VERSION); + + memset(&server_config, 0, sizeof(struct server_config_t)); + + if (argc < 2) + read_config(DHCPD_CONF_FILE); + else read_config(argv[1]); + + pid_fd = pidfile_acquire(server_config.pidfile); + pidfile_write_release(pid_fd); + + if ((option = find_option(server_config.options, DHCP_LEASE_TIME))) { + memcpy(&server_config.lease, option->data + 2, 4); + server_config.lease = ntohl(server_config.lease); + } + else server_config.lease = LEASE_TIME; + + leases = malloc(sizeof(struct dhcpOfferedAddr) * server_config.max_leases); + memset(leases, 0, sizeof(struct dhcpOfferedAddr) * server_config.max_leases); + read_leases(server_config.lease_file); + + if (read_interface(server_config.interface, &server_config.ifindex, + &server_config.server, server_config.arp) < 0) + exit_server(1); + +#ifndef DEBUGGING + pid_fd = pidfile_acquire(server_config.pidfile); /* hold lock during fork. */ + if (daemon(0, 0) == -1) { + perror("fork"); + exit_server(1); + } + pidfile_write_release(pid_fd); +#endif + + + socketpair(AF_UNIX, SOCK_STREAM, 0, signal_pipe); + signal(SIGUSR1, signal_handler); + signal(SIGTERM, signal_handler); + + timeout_end = time(0) + server_config.auto_time; + while(1) { /* loop until universe collapses */ + + if (server_socket < 0) + if ((server_socket = listen_socket(INADDR_ANY, SERVER_PORT, server_config.interface)) < 0) { + LOG(LOG_ERR, "FATAL: couldn't create server socket, %s", strerror(errno)); + exit_server(0); + } + + FD_ZERO(&rfds); + FD_SET(server_socket, &rfds); + FD_SET(signal_pipe[0], &rfds); + if (server_config.auto_time) { + tv.tv_sec = timeout_end - time(0); + tv.tv_usec = 0; + } + if (!server_config.auto_time || tv.tv_sec > 0) { + max_sock = server_socket > signal_pipe[0] ? server_socket : signal_pipe[0]; + retval = select(max_sock + 1, &rfds, NULL, NULL, + server_config.auto_time ? &tv : NULL); + } else retval = 0; /* If we already timed out, fall through */ + + if (retval == 0) { + write_leases(); + timeout_end = time(0) + server_config.auto_time; + continue; + } else if (retval < 0 && errno != EINTR) { + DEBUG(LOG_INFO, "error on select"); + continue; + } + + if (FD_ISSET(signal_pipe[0], &rfds)) { + if (read(signal_pipe[0], &sig, sizeof(sig)) < 0) + continue; /* probably just EINTR */ + switch (sig) { + case SIGUSR1: + LOG(LOG_INFO, "Received a SIGUSR1"); + write_leases(); + /* why not just reset the timeout, eh */ + timeout_end = time(0) + server_config.auto_time; + continue; + case SIGTERM: + LOG(LOG_INFO, "Received a SIGTERM"); + exit_server(0); + } + } + + if ((bytes = get_packet(&packet, server_socket)) < 0) { /* this waits for a packet - idle */ + if (bytes == -1 && errno != EINTR) { + DEBUG(LOG_INFO, "error on read, %s, reopening socket", strerror(errno)); + close(server_socket); + server_socket = -1; + } + continue; + } + + if ((state = get_option(&packet, DHCP_MESSAGE_TYPE)) == NULL) { + DEBUG(LOG_ERR, "couldn't get option from packet, ignoring"); + continue; + } + + /* ADDME: look for a static lease */ + lease = find_lease_by_chaddr(packet.chaddr); + switch (state[0]) { + case DHCPDISCOVER: + DEBUG(LOG_INFO,"received DISCOVER"); + + if (sendOffer(&packet) < 0) { + LOG(LOG_ERR, "send OFFER failed"); + } + break; + case DHCPREQUEST: + DEBUG(LOG_INFO, "received REQUEST"); + + requested = get_option(&packet, DHCP_REQUESTED_IP); + server_id = get_option(&packet, DHCP_SERVER_ID); + + if (requested) memcpy(&requested_align, requested, 4); + if (server_id) memcpy(&server_id_align, server_id, 4); + + if (lease) { /*ADDME: or static lease */ + if (server_id) { + /* SELECTING State */ + DEBUG(LOG_INFO, "server_id = %08x", ntohl(server_id_align)); + if (server_id_align == server_config.server && requested && + requested_align == lease->yiaddr) { + sendACK(&packet, lease->yiaddr); + } + } else { + if (requested) { + /* INIT-REBOOT State */ + if (lease->yiaddr == requested_align) + sendACK(&packet, lease->yiaddr); + else sendNAK(&packet); + } else { + /* RENEWING or REBINDING State */ + if (lease->yiaddr == packet.ciaddr) + sendACK(&packet, lease->yiaddr); + else { + /* don't know what to do!!!! */ + sendNAK(&packet); + } + } + } + + /* what to do if we have no record of the client */ + } else if (server_id) { + /* SELECTING State */ + + } else if (requested) { + /* INIT-REBOOT State */ + if ((lease = find_lease_by_yiaddr(requested_align))) { + if (lease_expired(lease)) { + /* probably best if we drop this lease */ + memset(lease->chaddr, 0, 16); + /* make some contention for this address */ + } else sendNAK(&packet); + } else if (requested_align < server_config.start || + requested_align > server_config.end) { + sendNAK(&packet); + } /* else remain silent */ + + } else { + /* RENEWING or REBINDING State */ + } + break; + case DHCPDECLINE: + DEBUG(LOG_INFO,"received DECLINE"); + if (lease) { + memset(lease->chaddr, 0, 16); + lease->expires = time(0) + server_config.decline_time; + printf("%s,line:%d,lease->expires:%lu\n",__func__,__LINE__,lease->expires); + } + break; + case DHCPRELEASE: + DEBUG(LOG_INFO,"received RELEASE"); + if (lease) lease->expires = time(0); + printf("%s,line:%d,lease->expires:%lu\n",__func__,__LINE__,lease->expires); + break; + case DHCPINFORM: + DEBUG(LOG_INFO,"received INFORM"); + send_inform(&packet); + break; + default: + LOG(LOG_WARNING, "unsupported DHCP message (%02x) -- ignoring", state[0]); + } + } + + return 0; +} + diff --git a/platform/mcu/xr871/src/net/udhcp/dhcpd.h b/platform/mcu/xr871/src/net/udhcp/dhcpd.h new file mode 100644 index 0000000000..18f876d3c3 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcpd.h @@ -0,0 +1,139 @@ +/* dhcpd.h */ +#ifndef _DHCPD_H +#define _DHCPD_H + +#ifndef DHCPD_LWIP +#include +#include +#include "libbb_udhcp.h" +#endif +#ifdef DHCPD_FREERTOS +#include "kernel/os/os_thread.h" +#endif +#include + +#include "leases.h" + + +/************************************/ +/* Defaults _you_ may want to tweak */ +/************************************/ + +/* the period of time the client is allowed to use that address */ +#define LEASE_TIME (60*60*24*10) /* 10 days of seconds */ + +#ifdef DHCPD_FS +/* where to find the DHCP server configuration file */ +#define DHCPD_CONF_FILE "/etc/udhcpd.conf" +#endif +/*****************************************************************/ +/* Do not modify below here unless you know what you are doing!! */ +/*****************************************************************/ + +/* DHCP protocol -- see RFC 2131 */ +#define SERVER_PORT 67 +#define CLIENT_PORT 68 + +#define DHCP_MAGIC 0x63825363 + +/* DHCP option codes (partial list) */ +#define DHCP_PADDING 0x00 +#define DHCP_SUBNET 0x01 +#define DHCP_TIME_OFFSET 0x02 +#define DHCP_ROUTER 0x03 +#define DHCP_TIME_SERVER 0x04 +#define DHCP_NAME_SERVER 0x05 +#define DHCP_DNS_SERVER 0x06 +#define DHCP_LOG_SERVER 0x07 +#define DHCP_COOKIE_SERVER 0x08 +#define DHCP_LPR_SERVER 0x09 +#define DHCP_HOST_NAME 0x0c +#define DHCP_BOOT_SIZE 0x0d +#define DHCP_DOMAIN_NAME 0x0f +#define DHCP_SWAP_SERVER 0x10 +#define DHCP_ROOT_PATH 0x11 +#define DHCP_IP_TTL 0x17 +#define DHCP_MTU 0x1a +#define DHCP_BROADCAST 0x1c +#define DHCP_NTP_SERVER 0x2a +#define DHCP_WINS_SERVER 0x2c +#define DHCP_REQUESTED_IP 0x32 +#define DHCP_LEASE_TIME 0x33 +#define DHCP_OPTION_OVER 0x34 +#define DHCP_MESSAGE_TYPE 0x35 +#define DHCP_SERVER_ID 0x36 +#define DHCP_PARAM_REQ 0x37 +#define DHCP_MESSAGE 0x38 +#define DHCP_MAX_SIZE 0x39 +#define DHCP_T1 0x3a +#define DHCP_T2 0x3b +#define DHCP_VENDOR 0x3c +#define DHCP_CLIENT_ID 0x3d + +#define DHCP_END 0xFF + + +#define BOOTREQUEST 1 +#define BOOTREPLY 2 + +#define ETH_10MB 1 +#define ETH_10MB_LEN 6 + +#define DHCPDISCOVER 1 +#define DHCPOFFER 2 +#define DHCPREQUEST 3 +#define DHCPDECLINE 4 +#define DHCPACK 5 +#define DHCPNAK 6 +#define DHCPRELEASE 7 +#define DHCPINFORM 8 + +#define BROADCAST_FLAG 0x8000 + +#define OPTION_FIELD 0 +#define FILE_FIELD 1 +#define SNAME_FIELD 2 + +/* miscellaneous defines */ +#define MAC_BCAST_ADDR (unsigned char *) "\xff\xff\xff\xff\xff\xff" +#define OPT_CODE 0 +#define OPT_LEN 1 +#define OPT_DATA 2 + +struct option_set { + unsigned char *data; + struct option_set *next; +}; + +struct server_config_t { + u_int32_t server; /* Our IP, in network order */ + u_int32_t start; /* Start address of leases, network order */ + u_int32_t end; /* End of leases, network order */ + struct option_set *options; /* List of DHCP options loaded from the config file */ + char *interface; /* The name of the interface to use */ + int ifindex; /* Index number of the interface to use */ + unsigned char arp[6]; /* Our arp address */ + unsigned long lease; /* lease time in seconds (host order) */ + unsigned long max_leases; /* maximum number of leases (including reserved address) */ + char remaining; /* should the lease file be interpreted as lease time remaining, or + * as the time the lease expires */ + unsigned long auto_time; /* how long should udhcpd wait before writing a config file. + * if this is zero, it will only write one on SIGUSR1 */ + unsigned long decline_time; /* how long an address is reserved if a client returns a + * decline message */ + unsigned long conflict_time; /* how long an arp conflict offender is leased for */ + unsigned long offer_time; /* how long an offered address is reserved */ + unsigned long min_lease; /* minimum lease a client can request*/ + char *lease_file; + char *pidfile; + char *notify_file; /* What to run whenever leases are written */ + u_int32_t siaddr; /* next server bootp option */ + char *sname; /* bootp server name */ + char *boot_file; /* bootp boot file option */ +}; + +extern struct server_config_t server_config; +extern struct dhcpOfferedAddr *leases; + + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/dhcpd_cfg.h b/platform/mcu/xr871/src/net/udhcp/dhcpd_cfg.h new file mode 100644 index 0000000000..a01703d95d --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dhcpd_cfg.h @@ -0,0 +1,27 @@ +#ifndef DHCPD_CFG_H_H +#define DHCPD_CFG_H_H + +#define DHCPD_ADDR_START "192.168.51.100" +#define DHCPD_ADDR_END "192.168.51.104" +#define DHCPD_INTERFACE "en1" +#define DHCPD_OPTION "" +#define DHCPD_OPT "" +#define DHCPD_REMAIN "yes" +#define DHCPD_MAX_LEASES "5" +#define DHCPD_AUTO_TIME "7200" +#define DHCPD_DECLINE_TIME "3600" +#define DHCPD_CONFLICT_TIME "3600" +#define DHCPD_OFFER_TIME "60" +#define DHCPD_MIN_LEASE "60" +#define DHCPD_SIADDR "0.0.0.0" +#define DHCPD_SNAME "IOT" + +#define u_int8_t uint8_t +#define u_int16_t uint16_t +#define u_int32_t uint32_t + +#define u_int uint32_t +#define u_char uint8_t +#define u_short uint16_t + +#endif /* DHCPD_CFG_H_H */ diff --git a/platform/mcu/xr871/src/net/udhcp/dns.h b/platform/mcu/xr871/src/net/udhcp/dns.h new file mode 100644 index 0000000000..a8cd5079ba --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dns.h @@ -0,0 +1,82 @@ +/*** + * dns-server.c + * Provided by: Paul Krzyzanowski + * Group: Aditya Geria, Monisha Jain, Jeevana Lagisetty + * Header file for dns-server.c + * Provides the header structs for a DNS query exchange + **/ + +#ifndef __DHCPD_DNS_H__ +#define __DHCPD_DNS_H__ + +#include +#include +#include "lwip/sockets.h" +#include +#include + +/* + DNS structures +*/ + +/* dns header - see rfc1035 */ +/* this is the main header of a DNS message */ +/* it is followed by zero or more questions, answers, authorities, and additional sections */ +/* the last four count fields tell you how many of each to expect */ + +typedef struct { + unsigned short id; + unsigned char rd:1; + unsigned char tc:1; + unsigned char aa:1; + unsigned char opcode:4; + unsigned char qr:1; + unsigned char rcode:4; + unsigned char cd:1; + unsigned char ad:1; + unsigned char z:1; + unsigned char ra:1; + unsigned short qd_count; + unsigned short an_count; + unsigned short ns_count; + unsigned short ar_count; +} dns_header; + +/* dns question section format. This is prepended with a name */ +/* check the specs for the format of a name. Instead of components */ +/* separated by dots, each component is prefixed with a byte containing */ +/* the length of that component */ + +typedef struct { + unsigned short qtype; + unsigned short qclass; +} dns_question; + +/* DNS resource record format */ +/* The answer, authority, and additional sections all share this format. */ +/* It is prepended with a name and suffixed with additional data */ + +typedef struct __attribute__ ((__packed__)) { + unsigned short type; + unsigned short class; + unsigned int ttl; + unsigned short data_len; + //unsigned int rdata; +} dns_rrhdr; + +#define DNS_BUF_SIZE 256 + +//#define DNS_SERVER_DBG + +#ifdef DNS_SERVER_DBG +#define DNS_DBG printf +#define DNS_ERR(x...) do {printf("[DNS ERR]"); printf(x); } while (0) +#else +#define DNS_DBG(x...) NULL +#define DNS_ERR(x...) NULL +#endif /* DEBUG */ + +int dns_listen_socket(void); +int dns_server(int fd, char *recvbuf, int buflen); + +#endif \ No newline at end of file diff --git a/platform/mcu/xr871/src/net/udhcp/dns_server.c b/platform/mcu/xr871/src/net/udhcp/dns_server.c new file mode 100644 index 0000000000..28b5f0f5fa --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dns_server.c @@ -0,0 +1,120 @@ +/*** + * dns-server.c + * Authors: Aditya Geria, Monisha Jain, Jeevana Lagisetty + * Version 1.0.4 (April 1, 2016) + * Fixed debug information, cleaned up messages shown + * Host a simple DNS server which will resolve hosts from a given + * hosts.txt file, and provide an IP address. + **/ + +#include "dns.h" +#include "lwip/netdb.h" +#include +#include + +int process_request (int fd, void* recvbuf, int recvlen, struct sockaddr *to) +{ + int ret; + dns_header* header = (dns_header*) recvbuf; + socklen_t addrlen = sizeof(*to); + + if(header->qr == 0) { + DNS_DBG("Correct query field - identified question\n"); + DNS_DBG("Query count: %d\n", htons(header->qd_count)); + + //char* query = (char*)recvbuf + sizeof(dns_header); //gets the query name + //DNS_DBG("Query length: %d\n", strlen(query)); + + header->qr = 1; + header->aa = 0; + header->tc = 0; + header->ra = 1; + header->rcode = 5; //refuse; + //header->qd_count = htons(1); + //header->an_count = 0; + //header->ns_count = 0; + //header->ar_count = 0; + + //no need to add answer record, or query + if((ret = sendto(fd, recvbuf, recvlen, 0, to, addrlen)) < 0) { + DNS_ERR("Failed to send, line %d\n", __LINE__); + return -1; + } + return ret; + }else { + return -1; + } +} + +/** + * @Method dump + * @param buf - thing to view/dump + * @param len - length of buf + * Shows contents of (buf) in bitwise manner + */ +void dump (char* buf, int len) { + int i = 0; + + for(i=0; i < len; ++i) + DNS_DBG("%02x ", buf[i]); // dump hex values + DNS_DBG("\n"); + + for(i=0; i < len; ++i) { + if((u8_t)buf[i] >= 0x20 && (u8_t)buf[i] <= 0x7f) + DNS_DBG("'%c' ", buf[i]); // dump a character if it’s printable + else + DNS_DBG("0x%02x ", buf[i]); // else dump a hex value + } + DNS_DBG("\n"); + return; +} + +int dns_listen_socket(void) { + struct sockaddr_in myaddr; // our address + int fd = -1; // our socket + int port = 53; + int n = 1; + + DNS_DBG("Opening listen socket on port %d for dns server\n", port); + /* create a UDP socket */ + if ((fd = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) { + DNS_ERR("cannot create socket\n"); + return -1; + } + + if(setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *) &n, sizeof(n)) < 0) { + closesocket(fd); + return -1; + } + + /* bind the socket to any valid IP address and a specific port */ + memset((char *)&myaddr, 0, sizeof(myaddr)); + myaddr.sin_family = AF_INET; + myaddr.sin_addr.s_addr = htonl(INADDR_ANY); + myaddr.sin_port = htons(port); + + if (bind(fd, (struct sockaddr *)&myaddr, sizeof(myaddr)) < 0) { + closesocket(fd); + return -1; + } + return fd; +} + +int dns_server(int fd, char *recvbuf, int buflen) +{ + struct sockaddr_in remaddr; // remote address + socklen_t addrlen = sizeof(remaddr); // length of addresses + int ret; //bytes received + + ret = recvfrom(fd, recvbuf, buflen, 0, (struct sockaddr *)&remaddr, &addrlen); + if (ret < 0 || ret < sizeof(dns_header)) { + DNS_ERR("dns packet recv err\n"); + return -1; + } + DNS_DBG("dns server received %d bytes\n", ret); + //dump(recvbuf, ret); //debugging dump + ret = process_request(fd, recvbuf, ret, (struct sockaddr *)&remaddr); + return ret; +} + + diff --git a/platform/mcu/xr871/src/net/udhcp/dumpleases.1 b/platform/mcu/xr871/src/net/udhcp/dumpleases.1 new file mode 100644 index 0000000000..04a04da155 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dumpleases.1 @@ -0,0 +1,30 @@ +.TH DUMPLEASES 1 2001-09-27 GNU/Linux "GNU/Linux Administrator's Manual" +.SH NAME +dumpleases \- display leases granted by udhcp server +.SH SYNOPSIS +.B dumpleases +.RI [ OPTION ]... +.SH DESCRIPTION +Display the DHCP leases granted by +.BR udhcpd (8). +.SH OPTIONS +.TP +.BR \-a ,\ \-\-absolute +Interpret lease times as expiration time. +.TP +.BI \-f\ FILE,\ \-\-file= FILE +Read lease information from +.IR FILE . +.TP +.BR \-h ,\ \-\-help +Display help. +.TP +.BR \-r ,\ \-\-remaining +Interpret lease times as remaining time. +.SH FILES +.TP +.I /var/lib/misc/udhcpd.leases +Lease information file. +.SH SEE ALSO +.BR udhcpd (8), +.BR udhcpd.conf (5). diff --git a/platform/mcu/xr871/src/net/udhcp/dumpleases.c b/platform/mcu/xr871/src/net/udhcp/dumpleases.c new file mode 100644 index 0000000000..78d4322c91 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/dumpleases.c @@ -0,0 +1,112 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "libbb_udhcp.h" + +#define REMAINING 0 +#define ABSOLUTE 1 + +struct lease_t { + unsigned char chaddr[16]; + u_int32_t yiaddr; + u_int32_t expires; +}; + +#ifdef BB_VER +int dumpleases_main(int argc, char *argv[]) +#else +int main(int argc, char *argv[]) +#endif +{ + FILE *fp; + int i, c, mode = REMAINING; + long expires; + char file[255] = "/var/lib/misc/udhcpd.leases"; + struct lease_t lease; + struct in_addr addr; + + static struct option options[] = { + {"absolute", 0, 0, 'a'}, + {"remaining", 0, 0, 'r'}, + {"file", 1, 0, 'f'}, + {"help", 0, 0, 'h'}, + {0, 0, 0, 0} + }; + + while (1) { + int option_index = 0; + c = getopt_long(argc, argv, "arf:h", options, &option_index); + if (c == -1) break; + + switch (c) { + case 'a': mode = ABSOLUTE; break; + case 'r': mode = REMAINING; break; + case 'f': + strncpy(file, optarg, 255); + file[254] = '\0'; + break; + case 'h': + printf("Usage: dumpleases -f -[r|a]\n\n"); + printf(" -f, --file=FILENAME Leases file to load\n"); + printf(" -r, --remaining Interepret lease times as time remaing\n"); + printf(" -a, --absolute Interepret lease times as expire time\n"); + break; + } + } + + if (!(fp = fopen(file, "r"))) { + perror("could not open input file"); + return 0; + } + + printf("Mac Address IP-Address Expires %s\n", mode == REMAINING ? "in" : "at"); + /* "00:00:00:00:00:00 255.255.255.255 Wed Jun 30 21:49:08 1993" */ + while (fread(&lease, sizeof(lease), 1, fp)) { + + for (i = 0; i < 6; i++) { + printf("%02x", lease.chaddr[i]); + if (i != 5) printf(":"); + } + addr.s_addr = lease.yiaddr; + printf(" %-15s", inet_ntoa(addr)); + expires = ntohl(lease.expires); + printf(" "); + if (mode == REMAINING) { + if (!expires) printf("expired\n"); + else { + if (expires > 60*60*24) { + printf("%ld days, ", expires / (60*60*24)); + expires %= 60*60*24; + } + if (expires > 60*60) { + printf("%ld hours, ", expires / (60*60)); + expires %= 60*60; + } + if (expires > 60) { + printf("%ld minutes, ", expires / 60); + expires %= 60; + } + printf("%ld seconds\n", expires); + } + } else printf("%s", ctime(&expires)); + } + fclose(fp); + + return 0; +} diff --git a/platform/mcu/xr871/src/net/udhcp/files.c b/platform/mcu/xr871/src/net/udhcp/files.c new file mode 100644 index 0000000000..a609741d7f --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/files.c @@ -0,0 +1,322 @@ +/* + * files.c -- DHCP server file manipulation * + * Rewrite by Russ Dill July 2001 + */ + +#include +#include +#include +#include + +#ifdef DHCPD_LWIP +#include "lwip/netdb.h" +#include "lwip/sockets.h" +#else +#include +#include +#include +#endif + +#ifndef DHCPD_TIMEALT +#include +#endif + +#include "debug.h" +#include "dhcpd.h" +#include "files.h" +#include "options.h" +#include "leases.h" + +/* on these functions, make sure you datatype matches */ +static int read_ip(char *line, void *arg) +{ + struct in_addr *addr = arg; + struct hostent *host; + + int retval = 1; + if (!inet_aton(line, addr)) { + if ((host = gethostbyname(line))) { + addr->s_addr = *((unsigned long *) host->h_addr_list[0]); + } + else retval = 0; + + } + return retval; +} + +static int read_str(char *line, void *arg) +{ + char **dest = arg; + + if (*dest) free(*dest); + *dest = strdup(line); + + return 1; +} + +static int read_u32(char *line, void *arg) +{ + u_int32_t *dest = arg; + char *endptr; + *dest = strtoul(line, &endptr, 0); + return endptr[0] == '\0'; +} + +static int read_yn(char *line, void *arg) +{ + char *dest = arg; + int retval = 1; + + if (!strcasecmp("yes", line)) + *dest = 1; + else if (!strcasecmp("no", line)) + *dest = 0; + else retval = 0; + + return retval; +} + +/* read a dhcp option and add it to opt_list */ +static int read_opt(char *line, void *arg) +{ + struct option_set **opt_list = arg; + char *opt, *val, *endptr; + struct dhcp_option *option = NULL; + int retval = 0, length = 0; + char buffer[255]; + u_int16_t result_u16; + u_int32_t result_u32; + int i; + + if (!(opt = strtok(line, " \t="))) return 0; + + for (i = 0; options[i].code; i++) + if (!strcmp(options[i].name, opt)) + option = &(options[i]); + + if (!option) return 0; + + do { + val = strtok(NULL, ", \t"); + if (val) { + length = option_lengths[option->flags & TYPE_MASK]; + retval = 0; + switch (option->flags & TYPE_MASK) { + case OPTION_IP: + retval = read_ip(val, buffer); + break; + case OPTION_IP_PAIR: + retval = read_ip(val, buffer); + if (!(val = strtok(NULL, ", \t/-"))) retval = 0; + if (retval) retval = read_ip(val, buffer + 4); + break; + case OPTION_STRING: + length = strlen(val); + if (length > 0) { + if (length > 254) length = 254; + memcpy(buffer, val, length); + retval = 1; + } + break; + case OPTION_BOOLEAN: + retval = read_yn(val, buffer); + break; + case OPTION_U8: + buffer[0] = strtoul(val, &endptr, 0); + retval = (endptr[0] == '\0'); + break; + case OPTION_U16: + result_u16 = htons(strtoul(val, &endptr, 0)); + memcpy(buffer, &result_u16, 2); + retval = (endptr[0] == '\0'); + break; + case OPTION_S16: + result_u16 = htons(strtol(val, &endptr, 0)); + memcpy(buffer, &result_u16, 2); + retval = (endptr[0] == '\0'); + break; + case OPTION_U32: + result_u32 = htonl(strtoul(val, &endptr, 0)); + memcpy(buffer, &result_u32, 4); + retval = (endptr[0] == '\0'); + break; + case OPTION_S32: + result_u32 = htonl(strtol(val, &endptr, 0)); + memcpy(buffer, &result_u32, 4); + retval = (endptr[0] == '\0'); + break; + default: + break; + } + if (retval) + attach_option(opt_list, option, buffer, length); + }; + } while (val && retval && option->flags & OPTION_LIST); + return retval; +} + +#ifndef DHCPD_USRCFG + +static struct config_keyword keywords[] = { + /* keyword[14] handler variable address default[20] */ + {"start", read_ip, &(server_config.start), "192.168.0.20"}, + {"end", read_ip, &(server_config.end), "192.168.0.254"}, + {"interface", read_str, &(server_config.interface), "eth0"}, + {"option", read_opt, &(server_config.options), ""}, + {"opt", read_opt, &(server_config.options), ""}, + {"max_leases", read_u32, &(server_config.max_leases), "254"}, + {"remaining", read_yn, &(server_config.remaining), "yes"}, + {"auto_time", read_u32, &(server_config.auto_time), "7200"}, + {"decline_time",read_u32, &(server_config.decline_time),"3600"}, + {"conflict_time",read_u32,&(server_config.conflict_time),"3600"}, + {"offer_time", read_u32, &(server_config.offer_time), "60"}, + {"min_lease", read_u32, &(server_config.min_lease), "60"}, + {"lease_file", read_str, &(server_config.lease_file), "/var/lib/misc/udhcpd.leases"}, + {"pidfile", read_str, &(server_config.pidfile), "/var/run/udhcpd.pid"}, + {"notify_file", read_str, &(server_config.notify_file), ""}, + {"siaddr", read_ip, &(server_config.siaddr), "0.0.0.0"}, + {"sname", read_str, &(server_config.sname), ""}, + {"boot_file", read_str, &(server_config.boot_file), ""}, + /*ADDME: static lease */ + {"", NULL, NULL, ""} +}; +#else + +#include "dhcpd_cfg.h" + +static struct config_keyword keywords[] = { + /* keyword[14] handler variable address default[20] */ + {"start", read_ip, &(server_config.start), DHCPD_ADDR_START}, /* default start addr*/ + {"end", read_ip, &(server_config.end), DHCPD_ADDR_END}, /* default end addr*/ + {"interface", read_str, &(server_config.interface), DHCPD_INTERFACE}, + {"option", read_opt, &(server_config.options), DHCPD_OPTION}, + {"opt", read_opt, &(server_config.options), DHCPD_OPT}, + {"max_leases", read_u32, &(server_config.max_leases), DHCPD_MAX_LEASES}, + {"remaining", read_yn, &(server_config.remaining), DHCPD_REMAIN}, + {"auto_time", read_u32, &(server_config.auto_time), DHCPD_AUTO_TIME}, + {"decline_time",read_u32, &(server_config.decline_time),DHCPD_DECLINE_TIME}, + {"conflict_time",read_u32,&(server_config.conflict_time),DHCPD_CONFLICT_TIME}, + {"offer_time", read_u32, &(server_config.offer_time), DHCPD_OFFER_TIME}, + {"min_lease", read_u32, &(server_config.min_lease), DHCPD_MIN_LEASE}, + {"siaddr", read_ip, &(server_config.siaddr), DHCPD_SIADDR}, + {"sname", read_str, &(server_config.sname), DHCPD_SNAME}, + {"", NULL, NULL, ""} +}; + +int init_config() +{ + u_int32_t i = 0; + for (i = 0; strlen(keywords[i].keyword); i++) + if (strlen(keywords[i].def)) + keywords[i].handler(keywords[i].def, keywords[i].var); + return 0; +} +#endif + +#ifdef DHCPD_FS +int read_config(char *file) +{ + FILE *in; + char buffer[80], orig[80], *token, *line; + int i; + + for (i = 0; strlen(keywords[i].keyword); i++) + if (strlen(keywords[i].def)) + keywords[i].handler(keywords[i].def, keywords[i].var); + + if (!(in = fopen(file, "r"))) { + DHCPD_LOG(LOG_ERR, "unable to open config file: %s", file); + return 0; + } + + while (fgets(buffer, 80, in)) { + if (strchr(buffer, '\n')) *(strchr(buffer, '\n')) = '\0'; + strncpy(orig, buffer, 80); + if (strchr(buffer, '#')) *(strchr(buffer, '#')) = '\0'; + token = buffer + strspn(buffer, " \t"); + if (*token == '\0') continue; + line = token + strcspn(token, " \t="); + if (*line == '\0') continue; + *line = '\0'; + line++; + + /* eat leading whitespace */ + line = line + strspn(line, " \t="); + /* eat trailing whitespace */ + for (i = strlen(line); i > 0 && isspace(line[i - 1]); i--); + line[i] = '\0'; + + for (i = 0; strlen(keywords[i].keyword); i++) + if (!strcasecmp(token, keywords[i].keyword)) + if (!keywords[i].handler(line, keywords[i].var)) { + DHCPD_LOG(LOG_ERR, "unable to parse '%s'", orig); + /* reset back to the default value */ + keywords[i].handler(keywords[i].def, keywords[i].var); + } + } + fclose(in); + return 1; +} + +void write_leases(void) +{ + FILE *fp; + unsigned int i; + char buf[255]; + time_t curr = time(0); + unsigned long lease_time; + + if (!(fp = fopen(server_config.lease_file, "w"))) { + DHCPD_LOG(LOG_ERR, "Unable to open %s for writing", server_config.lease_file); + return; + } + + for (i = 0; i < server_config.max_leases; i++) { + if (leases[i].yiaddr != 0) { + if (server_config.remaining) { + if (lease_expired(&(leases[i]))) + lease_time = 0; + else lease_time = leases[i].expires - curr; + } else lease_time = leases[i].expires; + lease_time = htonl(lease_time); + fwrite(leases[i].chaddr, 16, 1, fp); + fwrite(&(leases[i].yiaddr), 4, 1, fp); + fwrite(&lease_time, 4, 1, fp); + } + } + fclose(fp); + + if (server_config.notify_file) { + sprintf(buf, "%s %s", server_config.notify_file, server_config.lease_file); + system(buf); + } +} + +void read_leases(char *file) +{ + FILE *fp; + unsigned int i = 0; + struct dhcpOfferedAddr lease; + + if (!(fp = fopen(file, "r"))) { + DHCPD_LOG(LOG_ERR, "Unable to open %s for reading", file); + return; + } + + while (i < server_config.max_leases && (fread(&lease, sizeof lease, 1, fp) == 1)) { + /* ADDME: is it a static lease */ + if (lease.yiaddr >= server_config.start && lease.yiaddr <= server_config.end) { + lease.expires = ntohl(lease.expires); + if (!server_config.remaining) lease.expires -= time(0); + if (!(add_lease(lease.chaddr, lease.yiaddr, lease.expires))) { + DHCPD_LOG(LOG_WARNING, "Too many leases while loading %s\n", file); + break; + } + i++; + } + } + DEBUG(LOG_INFO, "Read %d leases", i); + fclose(fp); +} + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/files.h b/platform/mcu/xr871/src/net/udhcp/files.h new file mode 100644 index 0000000000..695b7c73b5 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/files.h @@ -0,0 +1,19 @@ +/* files.h */ +#ifndef _FILES_H +#define _FILES_H + +struct config_keyword { + char keyword[14]; + int (*handler)(char *line, void *var); + void *var; + char def[30]; +}; + +#ifdef DHCPD_FS +int read_config(char *file); +void write_leases(void); +void read_leases(char *file); +#else +int init_config(); +#endif +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/frontend.c b/platform/mcu/xr871/src/net/udhcp/frontend.c new file mode 100644 index 0000000000..de57795084 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/frontend.c @@ -0,0 +1,16 @@ +#include + +extern int udhcpd_main(int argc, char *argv[]); +extern int udhcpc_main(int argc, char *argv[]); + +int main(int argc, char *argv[]) +{ + int ret = 0; + char *base = strrchr(argv[0], '/'); + + if (strstr(base ? (base + 1) : argv[0], "dhcpd")) + ret = udhcpd_main(argc, argv); + else ret = udhcpc_main(argc, argv); + + return ret; +} diff --git a/platform/mcu/xr871/src/net/udhcp/leases.c b/platform/mcu/xr871/src/net/udhcp/leases.c new file mode 100644 index 0000000000..0550bd691b --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/leases.c @@ -0,0 +1,161 @@ +/* + * leases.c -- tools to manage DHCP leases + * Russ Dill July 2001 + */ +#include + +#ifdef DHCPD_LWIP +#include +#else +#include +#include +#include +#endif + +#ifdef DHCPD_TIMEALT +#include "dhcp_time.h" +#else +#include +#endif + +#include "debug.h" +#include "dhcpd.h" +#include "files.h" +#include "options.h" +#include "leases.h" +#include "arpping.h" + +unsigned char blank_chaddr[] = {[0 ... 15] = 0}; + +/* clear every lease out that chaddr OR yiaddr matches and is nonzero */ +void clear_lease(u_int8_t *chaddr, u_int32_t yiaddr) +{ + unsigned int i, j; + + for (j = 0; j < 16 && !chaddr[j]; j++); + + for (i = 0; i < server_config.max_leases; i++) + if ((j != 16 && !memcmp(leases[i].chaddr, chaddr, 16)) || + (yiaddr && leases[i].yiaddr == yiaddr)) { + memset(&(leases[i]), 0, sizeof(struct dhcpOfferedAddr)); + } +} + + +/* add a lease into the table, clearing out any old ones */ +struct dhcpOfferedAddr *add_lease(u_int8_t *chaddr, u_int32_t yiaddr, unsigned long lease) +{ + struct dhcpOfferedAddr *oldest; + + /* clean out any old ones */ + clear_lease(chaddr, yiaddr); + + oldest = oldest_expired_lease(); + + if (oldest) { + memcpy(oldest->chaddr, chaddr, 16); + oldest->yiaddr = yiaddr; + oldest->expires = time(0) + lease; + } + + return oldest; +} + + +/* true if a lease has expired */ +int lease_expired(struct dhcpOfferedAddr *lease) +{ + return (lease->expires < (unsigned long) time(0)); +} + + +/* Find the oldest expired lease, NULL if there are no expired leases */ +struct dhcpOfferedAddr *oldest_expired_lease(void) +{ + struct dhcpOfferedAddr *oldest = NULL; + unsigned long oldest_lease = time(0); + unsigned int i; + + + for (i = 0; i < server_config.max_leases; i++) + if (oldest_lease > leases[i].expires) { + oldest_lease = leases[i].expires; + oldest = &(leases[i]); + } + return oldest; + +} + + +/* Find the first lease that matches chaddr, NULL if no match */ +struct dhcpOfferedAddr *find_lease_by_chaddr(u_int8_t *chaddr) +{ + unsigned int i; + + for (i = 0; i < server_config.max_leases; i++) + if (!memcmp(leases[i].chaddr, chaddr, 16)) return &(leases[i]); + + return NULL; +} + + +/* Find the first lease that matches yiaddr, NULL is no match */ +struct dhcpOfferedAddr *find_lease_by_yiaddr(u_int32_t yiaddr) +{ + unsigned int i; + + for (i = 0; i < server_config.max_leases; i++) + if (leases[i].yiaddr == yiaddr) return &(leases[i]); + + return NULL; +} + + +/* find an assignable address, it check_expired is true, we check all the expired leases as well. + * Maybe this should try expired leases by age... */ +u_int32_t find_address(int check_expired) +{ + u_int32_t addr, ret; + struct dhcpOfferedAddr *lease = NULL; + + addr = ntohl(server_config.start); /* addr is in host order here */ + for (;addr <= ntohl(server_config.end); addr++) { + + /* ie, 192.168.55.0 */ + if (!(addr & 0xFF)) continue; + + /* ie, 192.168.55.255 */ + if ((addr & 0xFF) == 0xFF) continue; + + /* lease is not taken */ + ret = htonl(addr); + if ((!(lease = find_lease_by_yiaddr(ret)) || + + /* or it expired and we are checking for expired leases */ + (check_expired && lease_expired(lease))) && + + /* and it isn't on the network */ + !check_ip(ret)) { + return ret; + break; + } + } + return 0; +} + + +/* check is an IP is taken, if it is, add it to the lease table */ +int check_ip(u_int32_t addr) +{ + struct in_addr temp; + memset(&temp, 0, sizeof(temp)); + DHCPD_LOG(LOG_INFO, "check ip"); + if (arpping(addr, server_config.server, server_config.arp, server_config.interface) == 0) { + temp.s_addr = addr; + DHCPD_LOG(LOG_INFO, "%s belongs to someone, reserving it for %ld seconds", + inet_ntoa(temp), server_config.conflict_time); + add_lease(blank_chaddr, addr, server_config.conflict_time); + return 1; + } else return 0; +} + diff --git a/platform/mcu/xr871/src/net/udhcp/leases.h b/platform/mcu/xr871/src/net/udhcp/leases.h new file mode 100644 index 0000000000..4c8f4ee187 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/leases.h @@ -0,0 +1,27 @@ +/* leases.h */ +#ifndef _LEASES_H +#define _LEASES_H + +#ifdef DHCPD_USRCFG +#include "dhcpd_cfg.h" +#endif + +struct dhcpOfferedAddr { + u_int8_t chaddr[16]; + u_int32_t yiaddr; /* network order */ + u_int32_t expires; /* host order */ +}; + +extern unsigned char blank_chaddr[]; + +void clear_lease(u_int8_t *chaddr, u_int32_t yiaddr); +struct dhcpOfferedAddr *add_lease(u_int8_t *chaddr, u_int32_t yiaddr, unsigned long lease); +int lease_expired(struct dhcpOfferedAddr *lease); +struct dhcpOfferedAddr *oldest_expired_lease(void); +struct dhcpOfferedAddr *find_lease_by_chaddr(u_int8_t *chaddr); +struct dhcpOfferedAddr *find_lease_by_yiaddr(u_int32_t yiaddr); +u_int32_t find_address(int check_expired); +int check_ip(u_int32_t addr); + + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/libbb_udhcp.h b/platform/mcu/xr871/src/net/udhcp/libbb_udhcp.h new file mode 100644 index 0000000000..d3f72c65b1 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/libbb_udhcp.h @@ -0,0 +1,29 @@ +/* libbb_udhcp.h - busybox compatability wrapper */ + +#ifndef _LIBBB_UDHCP_H +#define _LIBBB_UDHCP_H + +#ifdef BB_VER +#include "libbb.h" + +#ifdef CONFIG_FEATURE_UDHCP_SYSLOG +#define SYSLOG +#endif + +#ifdef CONFIG_FEATURE_UDHCP_DEBUG +#define DEBUG +#endif + +#define COMBINED_BINARY +#define VERSION "0.9.8-pre" + +#else /* ! BB_VER */ + +#define TRUE 1 +#define FALSE 0 + +#define xmalloc malloc + +#endif /* BB_VER */ + +#endif /* _LIBBB_UDHCP_H */ diff --git a/platform/mcu/xr871/src/net/udhcp/log b/platform/mcu/xr871/src/net/udhcp/log new file mode 100644 index 0000000000..86a4f652d9 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/log @@ -0,0 +1,9 @@ +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o xradio_dhcpd.o xradio_dhcpd.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o arpping.o arpping.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o files.o files.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o leases.o leases.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o serverpacket.o serverpacket.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o options.o options.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o socket.o socket.c +../../../../../tools/toolchain/bin/arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -gdwarf-2 -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer -MMD -MP -DNDEBUG -Os -Werror -DBB_VER -Wno-address -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_XR1705_F103RB -DTARGET_AW -DTARGET_AW1705 -DTARGET_AW1705F103RB -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 -D__FPU_PRESENT=0 -DMBED_BUILD_TIMESTAMP=1437480207.16 -D__MBED__=1 -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__XRADIO_HEADERS__ -D__XRADIO_REDEFINE_GCC_INT32_TYPE__ -D__XRADIO_DUAL_CORE__ -D__XRADIO_APP_CORE__ -D__XRADIO_SIMULATE_HW_MBOX__ -D__XRADIO_WLAN_CMD_TEST__ -std=gnu99 -I../../../../inc -I../../../../inc/rtos -I../../../../inc/net -I../../../../inc/net/lwip -I../../../../inc/net/lwip/ipv4 -o packet.o packet.c +../../../../../tools/toolchain/bin/arm-none-eabi-ar -crs libudhcpd.a xradio_dhcpd.o arpping.o files.o leases.o serverpacket.o options.o socket.o packet.o diff --git a/platform/mcu/xr871/src/net/udhcp/options.c b/platform/mcu/xr871/src/net/udhcp/options.c new file mode 100644 index 0000000000..2c4128f55f --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/options.c @@ -0,0 +1,230 @@ +/* + * options.c -- DHCP server option packet tools + * Rewrite by Russ Dill July 2001 + */ + +#include +#include +#include + +#include "debug.h" +#include "dhcpd.h" +#include "files.h" +#include "options.h" +#include "leases.h" + + +/* supported options are easily added here */ +struct dhcp_option options[] = { + /* name[10] flags code */ + {"subnet", OPTION_IP | OPTION_REQ, 0x01}, + {"timezone", OPTION_S32, 0x02}, + {"router", OPTION_IP | OPTION_LIST | OPTION_REQ, 0x03}, + {"timesvr", OPTION_IP | OPTION_LIST, 0x04}, + {"namesvr", OPTION_IP | OPTION_LIST, 0x05}, + {"dns", OPTION_IP | OPTION_LIST | OPTION_REQ, 0x06}, + {"logsvr", OPTION_IP | OPTION_LIST, 0x07}, + {"cookiesvr", OPTION_IP | OPTION_LIST, 0x08}, + {"lprsvr", OPTION_IP | OPTION_LIST, 0x09}, + {"hostname", OPTION_STRING | OPTION_REQ, 0x0c}, + {"bootsize", OPTION_U16, 0x0d}, + {"domain", OPTION_STRING | OPTION_REQ, 0x0f}, + {"swapsvr", OPTION_IP, 0x10}, + {"rootpath", OPTION_STRING, 0x11}, + {"ipttl", OPTION_U8, 0x17}, + {"mtu", OPTION_U16, 0x1a}, + {"broadcast", OPTION_IP | OPTION_REQ, 0x1c}, + {"ntpsrv", OPTION_IP | OPTION_LIST, 0x2a}, + {"wins", OPTION_IP | OPTION_LIST, 0x2c}, + {"requestip", OPTION_IP, 0x32}, + {"lease", OPTION_U32, 0x33}, + {"dhcptype", OPTION_U8, 0x35}, + {"serverid", OPTION_IP, 0x36}, + {"message", OPTION_STRING, 0x38}, + {"tftp", OPTION_STRING, 0x42}, + {"bootfile", OPTION_STRING, 0x43}, + {"", 0x00, 0x00} +}; + +/* Lengths of the different option types */ +int option_lengths[] = { + [OPTION_IP] = 4, + [OPTION_IP_PAIR] = 8, + [OPTION_BOOLEAN] = 1, + [OPTION_STRING] = 1, + [OPTION_U8] = 1, + [OPTION_U16] = 2, + [OPTION_S16] = 2, + [OPTION_U32] = 4, + [OPTION_S32] = 4 +}; + + +/* get an option with bounds checking (warning, not aligned). */ +unsigned char *get_option(struct dhcpMessage *packet, int code) +{ + int i, length; + unsigned char *optionptr; + int over = 0, done = 0, curr = OPTION_FIELD; + + optionptr = packet->options; + i = 0; + length = 308; + while (!done) { + if (i >= length) { + DHCPD_LOG(LOG_WARNING, "bogus packet, option fields too long."); + return NULL; + } + if (optionptr[i + OPT_CODE] == code) { + if (i + 1 + optionptr[i + OPT_LEN] >= length) { + DHCPD_LOG(LOG_WARNING, "bogus packet, option fields too long."); + return NULL; + } + return optionptr + i + 2; + } + switch (optionptr[i + OPT_CODE]) { + case DHCP_PADDING: + i++; + break; + case DHCP_OPTION_OVER: + if (i + 1 + optionptr[i + OPT_LEN] >= length) { + DHCPD_LOG(LOG_WARNING, "bogus packet, option fields too long."); + return NULL; + } + over = optionptr[i + 3]; + i += optionptr[OPT_LEN] + 2; + break; + case DHCP_END: + if (curr == OPTION_FIELD && over & FILE_FIELD) { + optionptr = packet->file; + i = 0; + length = 128; + curr = FILE_FIELD; + } else if (curr == FILE_FIELD && over & SNAME_FIELD) { + optionptr = packet->sname; + i = 0; + length = 64; + curr = SNAME_FIELD; + } else done = 1; + break; + default: + i += optionptr[OPT_LEN + i] + 2; + } + } + return NULL; +} + + +/* return the position of the 'end' option (no bounds checking) */ +int end_option(unsigned char *optionptr) +{ + int i = 0; + + while (optionptr[i] != DHCP_END) { + if (optionptr[i] == DHCP_PADDING) i++; + else i += optionptr[i + OPT_LEN] + 2; + } + return i; +} + + +/* add an option string to the options (an option string contains an option code, + * length, then data) */ +int add_option_string(unsigned char *optionptr, unsigned char *string) +{ + int end = end_option(optionptr); + + /* end position + string length + option code/length + end option */ + if (end + string[OPT_LEN] + 2 + 1 >= 308) { + DHCPD_LOG(LOG_ERR, "Option 0x%02x did not fit into the packet!", string[OPT_CODE]); + return 0; + } + DEBUG(LOG_INFO, "adding option 0x%02x", string[OPT_CODE]); + memcpy(optionptr + end, string, string[OPT_LEN] + 2); + optionptr[end + string[OPT_LEN] + 2] = DHCP_END; + return string[OPT_LEN] + 2; +} + + +/* add a one to four byte option to a packet */ +int add_simple_option(unsigned char *optionptr, unsigned char code, u_int32_t data) +{ + char length = 0; + int i; + unsigned char option[2 + 4]; + unsigned char *u8; + u_int16_t *u16; + u_int32_t *u32; + u_int32_t aligned; + u8 = (unsigned char *) &aligned; + u16 = (u_int16_t *) &aligned; + u32 = &aligned; + + for (i = 0; options[i].code; i++) + if (options[i].code == code) { + length = option_lengths[options[i].flags & TYPE_MASK]; + } + + if (!length) { + DEBUG(LOG_ERR, "Could not add option 0x%02x", code); + return 0; + } + + option[OPT_CODE] = code; + option[OPT_LEN] = length; + + switch (length) { + case 1: *u8 = data; break; + case 2: *u16 = data; break; + case 4: *u32 = data; break; + } + memcpy(option + 2, &aligned, length); + return add_option_string(optionptr, option); +} + + +/* find option 'code' in opt_list */ +struct option_set *find_option(struct option_set *opt_list, char code) +{ + while (opt_list && opt_list->data[OPT_CODE] < code) + opt_list = opt_list->next; + + if (opt_list && opt_list->data[OPT_CODE] == code) return opt_list; + else return NULL; +} + + +/* add an option to the opt_list */ +void attach_option(struct option_set **opt_list, struct dhcp_option *option, char *buffer, int length) +{ + struct option_set *existing, *new, **curr; + + /* add it to an existing option */ + if ((existing = find_option(*opt_list, option->code))) { + DEBUG(LOG_INFO, "Attaching option %s to existing member of list", option->name); + if (option->flags & OPTION_LIST) { + if (existing->data[OPT_LEN] + length <= 255) { + existing->data = realloc(existing->data, + existing->data[OPT_LEN] + length + 2); + memcpy(existing->data + existing->data[OPT_LEN] + 2, buffer, length); + existing->data[OPT_LEN] += length; + } /* else, ignore the data, we could put this in a second option in the future */ + } /* else, ignore the new data */ + } else { + DEBUG(LOG_INFO, "Attaching option %s to list", option->name); + + /* make a new option */ + new = malloc(sizeof(struct option_set)); + new->data = malloc(length + 2); + new->data[OPT_CODE] = option->code; + new->data[OPT_LEN] = length; + memcpy(new->data + 2, buffer, length); + + curr = opt_list; + while (*curr && (*curr)->data[OPT_CODE] < option->code) + curr = &(*curr)->next; + + new->next = *curr; + *curr = new; + } +} diff --git a/platform/mcu/xr871/src/net/udhcp/options.h b/platform/mcu/xr871/src/net/udhcp/options.h new file mode 100644 index 0000000000..1fded2ef4d --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/options.h @@ -0,0 +1,40 @@ +/* options.h */ +#ifndef _OPTIONS_H +#define _OPTIONS_H + +#include "packet.h" + +#define TYPE_MASK 0x0F + +enum { + OPTION_IP=1, + OPTION_IP_PAIR, + OPTION_STRING, + OPTION_BOOLEAN, + OPTION_U8, + OPTION_U16, + OPTION_S16, + OPTION_U32, + OPTION_S32 +}; + +#define OPTION_REQ 0x10 /* have the client request this option */ +#define OPTION_LIST 0x20 /* There can be a list of 1 or more of these */ + +struct dhcp_option { + char name[10]; + char flags; + unsigned char code; +}; + +extern struct dhcp_option options[]; +extern int option_lengths[]; + +unsigned char *get_option(struct dhcpMessage *packet, int code); +int end_option(unsigned char *optionptr); +int add_option_string(unsigned char *optionptr, unsigned char *string); +int add_simple_option(unsigned char *optionptr, unsigned char code, u_int32_t data); +struct option_set *find_option(struct option_set *opt_list, char code); +void attach_option(struct option_set **opt_list, struct dhcp_option *option, char *buffer, int length); + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/packet.c b/platform/mcu/xr871/src/net/udhcp/packet.c new file mode 100644 index 0000000000..fd44e0d98d --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/packet.c @@ -0,0 +1,357 @@ +#include +#include + +#ifndef DHCPD_LWIP +#include +#include +#include +#endif +#include + + +#if __GLIBC__ >=2 && __GLIBC_MINOR >= 1 +#include +#include +#elif __LINUX +#include +#include +#include +#endif + +#ifdef DHCPD_LWIP +#include "netif/etharp.h" +#include "lwip/sockets.h" +#include "lwip/inet_chksum.h" +#include "lwip/ip_addr.h" +#include "lwipopts.h" +#include "stdlib.h" +#endif + +#include "packet.h" +#include "debug.h" +#include "dhcpd.h" +#include "options.h" + + +void init_header(struct dhcpMessage *packet, char type) +{ + memset(packet, 0, sizeof(struct dhcpMessage)); + switch (type) { + case DHCPDISCOVER: + case DHCPREQUEST: + case DHCPRELEASE: + case DHCPINFORM: + packet->op = BOOTREQUEST; + break; + case DHCPOFFER: + case DHCPACK: + case DHCPNAK: + packet->op = BOOTREPLY; + } + packet->htype = ETH_10MB; + packet->hlen = ETH_10MB_LEN; + packet->cookie = htonl(DHCP_MAGIC); + packet->options[0] = DHCP_END; + add_simple_option(packet->options, DHCP_MESSAGE_TYPE, type); +} + + +/* read a packet from socket fd, return -1 on read error, -2 on packet error */ +int get_packet(struct dhcpMessage *packet, int fd) +{ + int bytes; + int i; + const char broken_vendors[][8] = { + "MSFT 98", + "" + }; + char unsigned *vendor; + + memset(packet, 0, sizeof(struct dhcpMessage)); +#ifndef DHCPD_LWIP + bytes = read(fd, packet, sizeof(struct dhcpMessage)); +#else + struct sockaddr_in from; + int from_len = sizeof(from); + bytes = recvfrom(fd, packet, sizeof(struct dhcpMessage), 0, (struct sockaddr*)&from, (socklen_t *)&from_len); +#endif + if (bytes < 0) { + DEBUG(LOG_INFO, "couldn't read on listening socket, ignoring"); + return -1; + } + if (ntohl(packet->cookie) != DHCP_MAGIC) { + if ((strncmp((char *)packet,"", strlen("")) == 0) && + (from.sin_addr.s_addr == htonl(INADDR_LOOPBACK))) { + DHCPD_LOG(LOG_ALERT, "received stop server message"); + return -3; + } + DHCPD_LOG(LOG_ERR, "received bogus message, ignoring"); + return -2; + } + DEBUG(LOG_INFO, "Received a packet"); + + if (packet->op == BOOTREQUEST && (vendor = get_option(packet, DHCP_VENDOR))) { + for (i = 0; broken_vendors[i][0]; i++) { + if (vendor[OPT_LEN - 2] == (unsigned char) strlen(broken_vendors[i]) && + !strncmp((char *)vendor, broken_vendors[i], vendor[OPT_LEN - 2])) { + DEBUG(LOG_INFO, "broken client (%s), forcing broadcast", + broken_vendors[i]); + packet->flags |= htons(BROADCAST_FLAG); + } + } + } + + + return bytes; +} + + +u_int16_t checksum(void *addr, int count) +{ + /* Compute Internet Checksum for "count" bytes + * beginning at location "addr". + */ + register int32_t sum = 0; + u_int16_t *source = (u_int16_t *) addr; + + while (count > 1) { + /* This is the inner loop */ + sum += *source++; + count -= 2; + } + + /* Add left-over byte, if any */ + if (count > 0) { + /* Make sure that the left-over byte is added correctly both + * with little and big endian hosts */ + u_int16_t tmp = 0; + *(unsigned char *) (&tmp) = * (unsigned char *) source; + sum += tmp; + } + /* Fold 32-bit sum to 16 bits */ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + + return ~sum; +} +#define ETH_P_IP ETHTYPE_IP + +int _low_level_dhcp_send(struct dhcpMessage *payload, u_int32_t source_ip, int source_port, + u_int32_t dest_ip, int dest_port, unsigned char *dest_arp, int ifindex) +{ + struct netif *netif = netif_find(server_config.interface); + struct pbuf *p; + struct eth_hdr *ethhdr; + struct ip_hdr *iphdr; + struct udp_hdr *udphdr; + + p = pbuf_alloc(PBUF_LINK, + SIZEOF_ETH_HDR + sizeof(struct ip_hdr) + + sizeof(struct udp_hdr) + sizeof(struct dhcpMessage), + PBUF_RAM); + if (p == NULL) { + DHCPD_LOG(LOG_ERR, "Calloc failed...%s %d", __FUNCTION__, __LINE__); + return -1; + } + + ethhdr = (struct eth_hdr *)p->payload; + iphdr = (struct ip_hdr *)((char *)ethhdr + SIZEOF_ETH_HDR); + udphdr = (struct udp_hdr *)((char *)iphdr + sizeof(struct ip_hdr)); + + ETHADDR32_COPY(ðhdr->dest, dest_arp); + ETHADDR16_COPY(ðhdr->src, server_config.arp); + ethhdr->type = PP_HTONS(ETHTYPE_IP); + + iphdr->src.addr = source_ip; + iphdr->dest.addr = dest_ip; + + IPH_VHL_SET(iphdr, 4, IP_HLEN / 4); + IPH_TOS_SET(iphdr, 0x00); + IPH_LEN_SET(iphdr, htons(IP_HLEN + sizeof(struct udp_hdr) + sizeof(struct dhcpMessage))); + IPH_ID_SET(iphdr, htons(2)); + IPH_OFFSET_SET(iphdr, 0); + IPH_TTL_SET(iphdr, 255); + IPH_PROTO_SET(iphdr, IP_PROTO_UDP); + IPH_CHKSUM_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + + udphdr->src = htons(source_port); + udphdr->dest = htons(dest_port); + udphdr->len = htons(sizeof(struct udp_hdr) + sizeof(struct dhcpMessage)); + udphdr->chksum = 0; + + memcpy((char *)udphdr + sizeof(struct udp_hdr), + payload, sizeof(struct dhcpMessage)); + + netif->linkoutput(netif, p); + pbuf_free(p); + + return 0; +} + + +/* Constuct a ip/udp header for a packet, and specify the source and dest hardware address */ +int raw_packet(struct dhcpMessage *payload, u_int32_t source_ip, int source_port, + u_int32_t dest_ip, int dest_port, unsigned char *dest_arp, int ifindex) +{ +#ifndef DHCPD_LOW_LEVEL + int fd; + int result; + struct sockaddr_ll dest; +#ifdef DHCPD_HEAP_REPLACE_STACK + uint32_t interval; + struct udp_dhcp_packet *packet; + packet = malloc(sizeof(*packet)); + if (!packet) + DHCPD_LOG(LOG_ERR, "Calloc failed...%d",__LINE__); +#else + struct udp_dhcp_packet packet; +#endif + + if ((fd = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_IP))) < 0) { + DEBUG(LOG_ERR, "socket call failed: %s", strerror(errno)); + return -1; + } + + memset(&dest, 0, sizeof(dest)); +#ifndef DHCPD_HEAP_REPLACE_STACK + memset(&packet, 0, sizeof(packet)); +#else + memset(packet, 0, sizeof(*packet)); +#endif + + dest.sll_family = AF_PACKET; + dest.sll_protocol = htons(ETH_P_IP); + dest.sll_ifindex = ifindex; + dest.sll_halen = 6; + memcpy(dest.sll_addr, dest_arp, 6); + if (bind(fd, (struct sockaddr *)&dest, sizeof(struct sockaddr_ll)) < 0) { + DEBUG(LOG_ERR, "bind call failed: %s", strerror(errno)); +#ifndef DHCPD_LWIP + close(fd); +#else + closesocket(fd); +#ifdef DHCPD_HEAP_REPLACE_STACK + if (packet) { + free(packet); + packet = NULL; + } +#endif +#endif + return -1; + } +#ifdef DHCPD_LWIP + packet->ip._proto = IPPROTO_UDP; + interval = source_ip; + memcpy(&(packet->ip.src), &interval, 4); + + interval = dest_ip; + memcpy(&(packet->ip.dest), &interval, 4); +#else + packet.ip.protocol = IPPROTO_UDP; + packet.ip.saddr = source_ip; + packet.ip.daddr = dest_ip; +#endif +#ifdef DHCPD_LWIP + packet->udp.src = htons(source_port); + packet->udp.dest = htons(dest_port); + packet->udp.len = htons(sizeof(packet->udp) + sizeof(struct dhcpMessage)); /* cheat on the psuedo-header */ +#else + packet.udp.source = htons(source_port); + packet.udp.dest = htons(dest_port); + packet.udp.len = htons(sizeof(packet.udp) + sizeof(struct dhcpMessage)); /* cheat on the psuedo-header */ +#endif + +#ifdef DHCPD_LWIP + packet->ip._len = packet->udp.len; + memcpy(&(packet->data), payload, sizeof(struct dhcpMessage)); + packet->udp.chksum = checksum(packet, sizeof(struct udp_dhcp_packet)); +#else + packet.ip.tot_len = packet.udp.len; + memcpy(&(packet.data), payload, sizeof(struct dhcpMessage)); + packet.udp.check = checksum(&packet, sizeof(struct udp_dhcp_packet)); +#endif + + +#ifdef DHCPD_LWIP + packet->ip._len = htons(sizeof(struct udp_dhcp_packet)); + #define IPVERSION 4 + packet->ip._v_hl = (IPVERSION << 4) |(sizeof(packet->ip) >> 2); + //packet.ip._v_hl = sizeof(packet.ip) >> 2; + //IPH_V(packet.ip) = IPVERSION; + ///**********/packet.ip.version = IPVERSION; + packet->ip._ttl = IP_DEFAULT_TTL; + packet->ip._chksum = checksum(&(packet->ip), sizeof(packet->ip)); +#else + packet.ip.tot_len = htons(sizeof(struct udp_dhcp_packet)); + packet.ip.ihl = sizeof(packet.ip) >> 2; + packet.ip.version = IPVERSION; + packet.ip.ttl = IPDEFTTL; + packet.ip.check = checksum(&(packet.ip), sizeof(packet.ip)); +#endif +#ifdef DHCPD_HEAP_REPLACE_STACK + result = sendto(fd, packet, sizeof(struct udp_dhcp_packet), 0, (struct sockaddr *) &dest, sizeof(dest)); +#else + result = sendto(fd, &packet, sizeof(struct udp_dhcp_packet), 0, (struct sockaddr *) &dest, sizeof(dest)); +#endif + if (result <= 0) { + DEBUG(LOG_ERR, "write on socket failed: %s", strerror(errno)); + } +#ifdef DHCPD_HEAP_REPLACE_STACK + if (packet) + free(packet); +#endif +#ifdef DHCPD_LWIP + closesocket(fd); +#else + close(fd); +#endif + return result; +#else + + return _low_level_dhcp_send(payload, source_ip, source_port, + dest_ip, dest_port, dest_arp, ifindex); + +#endif +} + + +/* Let the kernel do all the work for packet generation */ +int kernel_packet(struct dhcpMessage *payload, u_int32_t source_ip, int source_port, + u_int32_t dest_ip, int dest_port) +{ + int n = 1; + int fd, result; + struct sockaddr_in client; + + if ((fd = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) + return -1; + + if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *) &n, sizeof(n)) == -1) + return -1; + + memset(&client, 0, sizeof(client)); + client.sin_family = AF_INET; + client.sin_port = htons(source_port); + client.sin_addr.s_addr = source_ip; + + if (bind(fd, (struct sockaddr *)&client, sizeof(struct sockaddr)) == -1) + return -1; + + memset(&client, 0, sizeof(client)); + client.sin_family = AF_INET; + client.sin_port = htons(dest_port); + client.sin_addr.s_addr = dest_ip; + + if (connect(fd, (struct sockaddr *)&client, sizeof(struct sockaddr)) == -1) + return -1; + + result = write(fd, payload, sizeof(struct dhcpMessage)); +#ifdef DHCPD_LWIP + closesocket(fd); +#else + close(fd); +#endif + return result; +} + diff --git a/platform/mcu/xr871/src/net/udhcp/packet.h b/platform/mcu/xr871/src/net/udhcp/packet.h new file mode 100644 index 0000000000..b6739ccaaa --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/packet.h @@ -0,0 +1,54 @@ +#ifndef _PACKET_H +#define _PACKET_H + +#ifdef DHCPD_LWIP +#include +#include +#else +#include +#include +#endif +#ifdef DHCPD_USRCFG +#include "dhcpd_cfg.h" +#endif + +struct dhcpMessage { + u_int8_t op; + u_int8_t htype; + u_int8_t hlen; + u_int8_t hops; + u_int32_t xid; + u_int16_t secs; + u_int16_t flags; + u_int32_t ciaddr; + u_int32_t yiaddr; + u_int32_t siaddr; + u_int32_t giaddr; + u_int8_t chaddr[16]; + u_int8_t sname[64]; + u_int8_t file[128]; + u_int32_t cookie; + u_int8_t options[308]; /* 312 - cookie */ +}; + +struct udp_dhcp_packet { +#ifdef DHCPD_LWIP + struct ip_hdr ip; + struct udp_hdr udp; +#else + struct iphdr ip; + struct udphdr udp; +#endif + struct dhcpMessage data; +}; + +void init_header(struct dhcpMessage *packet, char type); +int get_packet(struct dhcpMessage *packet, int fd); +u_int16_t checksum(void *addr, int count); +int raw_packet(struct dhcpMessage *payload, u_int32_t source_ip, int source_port, + u_int32_t dest_ip, int dest_port, unsigned char *dest_arp, int ifindex); +int kernel_packet(struct dhcpMessage *payload, u_int32_t source_ip, int source_port, + u_int32_t dest_ip, int dest_port); + + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/pidfile.c b/platform/mcu/xr871/src/net/udhcp/pidfile.c new file mode 100644 index 0000000000..837fcaeb17 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/pidfile.c @@ -0,0 +1,69 @@ +/* pidfile.c + * + * Functions to assist in the writing and removing of pidfiles. + * + * Russ Dill Soptember 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "debug.h" + +int pidfile_acquire(char *pidfile) +{ + int pid_fd; + if (pidfile == NULL) return -1; + + pid_fd = open(pidfile, O_CREAT | O_WRONLY, 0644); + if (pid_fd < 0) { + DHCPD_LOG(LOG_ERR, "Unable to open pidfile %s: %s\n", + pidfile, strerror(errno)); + } else { + lockf(pid_fd, F_LOCK, 0); + } + + return pid_fd; +} + + +void pidfile_write_release(int pid_fd) +{ + FILE *out; + + if (pid_fd < 0) return; + + if ((out = fdopen(pid_fd, "w")) != NULL) { + fprintf(out, "%d\n", getpid()); + fclose(out); + } + lockf(pid_fd, F_UNLCK, 0); + close(pid_fd); +} + + +void pidfile_delete(char *pidfile) +{ + if (pidfile) unlink(pidfile); +} + + diff --git a/platform/mcu/xr871/src/net/udhcp/pidfile.h b/platform/mcu/xr871/src/net/udhcp/pidfile.h new file mode 100644 index 0000000000..0e2b148a93 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/pidfile.h @@ -0,0 +1,26 @@ +/* pidfile.h + * + * Functions to assist in the writing and removing of pidfiles. + * + * Russ Dill Soptember 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +int pidfile_acquire(char *pidfile); +void pidfile_write_release(int pid_fd); +void pidfile_delete(char *pidfile); + diff --git a/platform/mcu/xr871/src/net/udhcp/samples/README b/platform/mcu/xr871/src/net/udhcp/samples/README new file mode 100644 index 0000000000..51721ea3cd --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/README @@ -0,0 +1,11 @@ +The files in this dir are: + + udhcpd.conf: A sample udhpcd configuration file. + + sample.script + sample.nak + sample.deconfig + sample.bound + sample.renew : sample scripts for the udhcpc client. + + simple.script : a simple sample script for the client. diff --git a/platform/mcu/xr871/src/net/udhcp/samples/sample.bound b/platform/mcu/xr871/src/net/udhcp/samples/sample.bound new file mode 100644 index 0000000000..200352672d --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/sample.bound @@ -0,0 +1,30 @@ +#!/bin/sh +# Sample udhcpc renew script + +RESOLV_CONF="/etc/udhcpc/resolv.conf" + +[ -n "$broadcast" ] && BROADCAST="broadcast $broadcast" +[ -n "$subnet" ] && NETMASK="netmask $subnet" + +/sbin/ifconfig $interface $ip $BROADCAST $NETMASK + +if [ -n "$router" ] +then + echo "deleting routers" + while /sbin/route del default gw 0.0.0.0 dev $interface + do : + done + + for i in $router + do + /sbin/route add default gw $i dev $interface + done +fi + +echo -n > $RESOLV_CONF +[ -n "$domain" ] && echo domain $domain >> $RESOLV_CONF +for i in $dns +do + echo adding dns $i + echo nameserver $i >> $RESOLV_CONF +done \ No newline at end of file diff --git a/platform/mcu/xr871/src/net/udhcp/samples/sample.deconfig b/platform/mcu/xr871/src/net/udhcp/samples/sample.deconfig new file mode 100644 index 0000000000..b221bcf12b --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/sample.deconfig @@ -0,0 +1,4 @@ +#!/bin/sh +# Sample udhcpc deconfig script + +/sbin/ifconfig $interface 0.0.0.0 diff --git a/platform/mcu/xr871/src/net/udhcp/samples/sample.nak b/platform/mcu/xr871/src/net/udhcp/samples/sample.nak new file mode 100644 index 0000000000..f4d08e6691 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/sample.nak @@ -0,0 +1,4 @@ +#!/bin/sh +# Sample udhcpc nak script + +echo Received a NAK: $message diff --git a/platform/mcu/xr871/src/net/udhcp/samples/sample.renew b/platform/mcu/xr871/src/net/udhcp/samples/sample.renew new file mode 100644 index 0000000000..c953e97588 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/sample.renew @@ -0,0 +1,30 @@ +#!/bin/sh +# Sample udhcpc bound script + +RESOLV_CONF="/etc/udhcpc/resolv.conf" + +[ -n "$broadcast" ] && BROADCAST="broadcast $broadcast" +[ -n "$subnet" ] && NETMASK="netmask $subnet" + +/sbin/ifconfig $interface $ip $BROADCAST $NETMASK + +if [ -n "$router" ] +then + echo "deleting routers" + while /sbin/route del default gw 0.0.0.0 dev $interface + do : + done + + for i in $router + do + /sbin/route add default gw $i dev $interface + done +fi + +echo -n > $RESOLV_CONF +[ -n "$domain" ] && echo domain $domain >> $RESOLV_CONF +for i in $dns +do + echo adding dns $i + echo nameserver $i >> $RESOLV_CONF +done \ No newline at end of file diff --git a/platform/mcu/xr871/src/net/udhcp/samples/sample.script b/platform/mcu/xr871/src/net/udhcp/samples/sample.script new file mode 100644 index 0000000000..9b717ac3c5 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/sample.script @@ -0,0 +1,7 @@ +#!/bin/sh +# Currently, we only dispatch according to command. However, a more +# elaborate system might dispatch by command and interface or do some +# common initialization first, especially if more dhcp event notifications +# are added. + +exec /usr/share/udhcpc/sample.$1 diff --git a/platform/mcu/xr871/src/net/udhcp/samples/simple.script b/platform/mcu/xr871/src/net/udhcp/samples/simple.script new file mode 100644 index 0000000000..a52a7f8122 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/simple.script @@ -0,0 +1,39 @@ +#!/bin/sh + +# udhcpc script edited by Tim Riker + +[ -z "$1" ] && echo "Error: should be called from udhcpc" && exit 1 + +RESOLV_CONF="/etc/resolv.conf" +[ -n "$broadcast" ] && BROADCAST="broadcast $broadcast" +[ -n "$subnet" ] && NETMASK="netmask $subnet" + +case "$1" in + deconfig) + /sbin/ifconfig $interface 0.0.0.0 + ;; + + renew|bound) + /sbin/ifconfig $interface $ip $BROADCAST $NETMASK + + if [ -n "$router" ] ; then + echo "deleting routers" + while route del default gw 0.0.0.0 dev $interface ; do + : + done + + for i in $router ; do + route add default gw $i dev $interface + done + fi + + echo -n > $RESOLV_CONF + [ -n "$domain" ] && echo search $domain >> $RESOLV_CONF + for i in $dns ; do + echo adding dns $i + echo nameserver $i >> $RESOLV_CONF + done + ;; +esac + +exit 0 diff --git a/platform/mcu/xr871/src/net/udhcp/samples/udhcpd.conf b/platform/mcu/xr871/src/net/udhcp/samples/udhcpd.conf new file mode 100644 index 0000000000..36cb58c3f8 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/samples/udhcpd.conf @@ -0,0 +1,116 @@ +# Sample udhcpd configuration file (/etc/udhcpd.conf) + +# The start and end of the IP lease block + +start 192.168.0.20 #default: 192.168.0.20 +end 192.168.0.254 #default: 192.168.0.254 + + +# The interface that udhcpd will use + +interface eth0 #default: eth0 + + +# The maximim number of leases (includes addressesd reserved +# by OFFER's, DECLINE's, and ARP conficts + +#max_leases 254 #default: 254 + + +# If remaining is true (default), udhcpd will store the time +# remaining for each lease in the udhcpd leases file. This is +# for embedded systems that cannot keep time between reboots. +# If you set remaining to no, the absolute time that the lease +# expires at will be stored in the dhcpd.leases file. + +#remaining yes #default: yes + + +# The time period at which udhcpd will write out a dhcpd.leases +# file. If this is 0, udhcpd will never automatically write a +# lease file. (specified in seconds) + +#auto_time 7200 #default: 7200 (2 hours) + + +# The amount of time that an IP will be reserved (leased) for if a +# DHCP decline message is received (seconds). + +#decline_time 3600 #default: 3600 (1 hour) + + +# The amount of time that an IP will be reserved (leased) for if an +# ARP conflct occurs. (seconds + +#conflict_time 3600 #default: 3600 (1 hour) + + +# How long an offered address is reserved (leased) in seconds + +#offer_time 60 #default: 60 (1 minute) + +# If a lease to be given is below this value, the full lease time is +# instead used (seconds). + +#min_lease 60 #defult: 60 + + +# The location of the leases file + +#lease_file /var/lib/misc/udhcpd.leases #defualt: /var/lib/misc/udhcpd.leases + +# The location of the pid file +#pidfile /var/run/udhcpd.pid #default: /var/run/udhcpd.pid + +# Everytime udhcpd writes a leases file, the below script will be called. +# Useful for writing the lease file to flash every few hours. + +#notify_file #default: (no script) + +#notify_file dumpleases # <--- usefull for debugging + +# The following are bootp specific options, setable by udhcpd. + +#siaddr 192.168.0.22 #default: 0.0.0.0 + +#sname zorak #default: (none) + +#boot_file /var/nfs_root #default: (none) + +# The remainer of options are DHCP options and can be specifed with the +# keyword 'opt' or 'option'. If an option can take multiple items, such +# as the dns option, they can be listed on the same line, or multiple +# lines. The only option with a default is 'lease'. + +#Examles +opt dns 192.168.10.2 192.168.10.10 +option subnet 255.255.255.0 +opt router 192.168.10.2 +opt wins 192.168.10.10 +option dns 129.219.13.81 # appened to above DNS servers for a total of 3 +option domain local +option lease 864000 # 10 days of seconds + + +# Currently supported options, for more info, see options.c +#subnet +#timezone +#router +#timesvr +#namesvr +#dns +#logsvr +#cookiesvr +#lprsvr +#bootsize +#domain +#swapsvr +#rootpath +#ipttl +#mtu +#broadcast +#wins +#lease +#ntpsrv +#tftp +#bootfile \ No newline at end of file diff --git a/platform/mcu/xr871/src/net/udhcp/script.c b/platform/mcu/xr871/src/net/udhcp/script.c new file mode 100644 index 0000000000..c2889a06ea --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/script.c @@ -0,0 +1,228 @@ +/* script.c + * + * Functions to call the DHCP client notification scripts + * + * Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "options.h" +#include "dhcpd.h" +#include "dhcpc.h" +#include "packet.h" +#include "options.h" +#include "debug.h" + +/* get a rough idea of how long an option will be (rounding up...) */ +static int max_option_length[] = { + [OPTION_IP] = sizeof("255.255.255.255 "), + [OPTION_IP_PAIR] = sizeof("255.255.255.255 ") * 2, + [OPTION_STRING] = 1, + [OPTION_BOOLEAN] = sizeof("yes "), + [OPTION_U8] = sizeof("255 "), + [OPTION_U16] = sizeof("65535 "), + [OPTION_S16] = sizeof("-32768 "), + [OPTION_U32] = sizeof("4294967295 "), + [OPTION_S32] = sizeof("-2147483684 "), +}; + + +static int upper_length(int length, struct dhcp_option *option) +{ + return max_option_length[option->flags & TYPE_MASK] * + (length / option_lengths[option->flags & TYPE_MASK]); +} + + +static int sprintip(char *dest, char *pre, unsigned char *ip) { + return sprintf(dest, "%s%d.%d.%d.%d ", pre, ip[0], ip[1], ip[2], ip[3]); +} + + +/* Fill dest with the text of option 'option'. */ +static void fill_options(char *dest, unsigned char *option, struct dhcp_option *type_p) +{ + int type, optlen; + u_int16_t val_u16; + int16_t val_s16; + u_int32_t val_u32; + int32_t val_s32; + int len = option[OPT_LEN - 2]; + + dest += sprintf(dest, "%s=", type_p->name); + + type = type_p->flags & TYPE_MASK; + optlen = option_lengths[type]; + for(;;) { + switch (type) { + case OPTION_IP_PAIR: + dest += sprintip(dest, "", option); + *(dest++) = '/'; + option += 4; + optlen = 4; + case OPTION_IP: /* Works regardless of host byte order. */ + dest += sprintip(dest, "", option); + break; + case OPTION_BOOLEAN: + dest += sprintf(dest, *option ? "yes " : "no "); + break; + case OPTION_U8: + dest += sprintf(dest, "%u ", *option); + break; + case OPTION_U16: + memcpy(&val_u16, option, 2); + dest += sprintf(dest, "%u ", ntohs(val_u16)); + break; + case OPTION_S16: + memcpy(&val_s16, option, 2); + dest += sprintf(dest, "%d ", ntohs(val_s16)); + break; + case OPTION_U32: + memcpy(&val_u32, option, 4); + dest += sprintf(dest, "%lu ", (unsigned long) ntohl(val_u32)); + break; + case OPTION_S32: + memcpy(&val_s32, option, 4); + dest += sprintf(dest, "%ld ", (long) ntohl(val_s32)); + break; + case OPTION_STRING: + memcpy(dest, option, len); + dest[len] = '\0'; + return; /* Short circuit this case */ + } + option += optlen; + len -= optlen; + if (len <= 0) break; + } +} + + +static char *find_env(const char *prefix, char *defaultstr) +{ + extern char **environ; + char **ptr; + const int len = strlen(prefix); + + for (ptr = environ; *ptr != NULL; ptr++) { + if (strncmp(prefix, *ptr, len) == 0) + return *ptr; + } + return defaultstr; +} + + +/* put all the paramaters into an environment */ +static char **fill_envp(struct dhcpMessage *packet) +{ + int num_options = 0; + int i, j; + char **envp; + unsigned char *temp; + char over = 0; + + if (packet == NULL) + num_options = 0; + else { + for (i = 0; options[i].code; i++) + if (get_option(packet, options[i].code)) + num_options++; + if (packet->siaddr) num_options++; + if ((temp = get_option(packet, DHCP_OPTION_OVER))) + over = *temp; + if (!(over & FILE_FIELD) && packet->file[0]) num_options++; + if (!(over & SNAME_FIELD) && packet->sname[0]) num_options++; + } + + envp = xmalloc((num_options + 5) * sizeof(char *)); + envp[0] = xmalloc(sizeof("interface=") + strlen(client_config.interface)); + sprintf(envp[0], "interface=%s", client_config.interface); + envp[1] = find_env("PATH", "PATH=/bin:/usr/bin:/sbin:/usr/sbin"); + envp[2] = find_env("HOME", "HOME=/"); + + if (packet == NULL) { + envp[3] = NULL; + return envp; + } + + envp[3] = xmalloc(sizeof("ip=255.255.255.255")); + sprintip(envp[3], "ip=", (unsigned char *) &packet->yiaddr); + for (i = 0, j = 4; options[i].code; i++) { + if ((temp = get_option(packet, options[i].code))) { + envp[j] = xmalloc(upper_length(temp[OPT_LEN - 2], &options[i]) + strlen(options[i].name) + 2); + fill_options(envp[j], temp, &options[i]); + j++; + } + } + if (packet->siaddr) { + envp[j] = xmalloc(sizeof("siaddr=255.255.255.255")); + sprintip(envp[j++], "siaddr=", (unsigned char *) &packet->siaddr); + } + if (!(over & FILE_FIELD) && packet->file[0]) { + /* watch out for invalid packets */ + packet->file[sizeof(packet->file) - 1] = '\0'; + envp[j] = xmalloc(sizeof("boot_file=") + strlen(packet->file)); + sprintf(envp[j++], "boot_file=%s", packet->file); + } + if (!(over & SNAME_FIELD) && packet->sname[0]) { + /* watch out for invalid packets */ + packet->sname[sizeof(packet->sname) - 1] = '\0'; + envp[j] = xmalloc(sizeof("sname=") + strlen(packet->sname)); + sprintf(envp[j++], "sname=%s", packet->sname); + } + envp[j] = NULL; + return envp; +} + + +/* Call a script with a par file and env vars */ +void run_script(struct dhcpMessage *packet, const char *name) +{ + int pid; + char **envp; + + if (client_config.script == NULL) + return; + + /* call script */ + pid = fork(); + if (pid) { + waitpid(pid, NULL, 0); + return; + } else if (pid == 0) { + envp = fill_envp(packet); + + /* close fd's? */ + + /* exec script */ + DEBUG(LOG_INFO, "execle'ing %s", client_config.script); + execle(client_config.script, client_config.script, + name, NULL, envp); + DHCPD_LOG(LOG_ERR, "script %s failed: %s", + client_config.script, strerror(errno)); + exit(1); + } +} diff --git a/platform/mcu/xr871/src/net/udhcp/script.h b/platform/mcu/xr871/src/net/udhcp/script.h new file mode 100644 index 0000000000..87a20cc170 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/script.h @@ -0,0 +1,6 @@ +#ifndef _SCRIPT_H +#define _SCRIPT_H + +void run_script(struct dhcpMessage *packet, const char *name); + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/serverpacket.c b/platform/mcu/xr871/src/net/udhcp/serverpacket.c new file mode 100644 index 0000000000..df20cfe3b8 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/serverpacket.c @@ -0,0 +1,428 @@ +/* serverpacket.c + * + * Constuct and send DHCP server packets + * + * Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifdef DHCPD_LWIP +#include +#else +#include +#include +#include +#endif +#include +#include +#include "packet.h" +#include "debug.h" +#include "dhcpd.h" +#include "options.h" +#include "leases.h" +#ifdef DHCPD_TIMEALT +#include "dhcp_time.h" +#else +#include +#endif +/* send a packet to giaddr using the kernel ip stack */ +static int send_packet_to_relay(struct dhcpMessage *payload) +{ + DEBUG(LOG_INFO, "Forwarding packet to relay"); + + return kernel_packet(payload, server_config.server, SERVER_PORT, + payload->giaddr, SERVER_PORT); +} + + +/* send a packet to a specific arp address and ip address by creating our own ip packet */ +static int send_packet_to_client(struct dhcpMessage *payload, int force_broadcast) +{ + unsigned char *chaddr; + u_int32_t ciaddr; + + if (force_broadcast) { + DEBUG(LOG_INFO, "broadcasting packet to client (NAK)"); + ciaddr = INADDR_BROADCAST; + chaddr = MAC_BCAST_ADDR; + } else if (payload->ciaddr) { + DEBUG(LOG_INFO, "unicasting packet to client ciaddr"); + ciaddr = payload->ciaddr; + chaddr = payload->chaddr; + } else if (ntohs(payload->flags) & BROADCAST_FLAG) { + DEBUG(LOG_INFO, "broadcasting packet to client (requested)"); + ciaddr = INADDR_BROADCAST; + chaddr = MAC_BCAST_ADDR; + } else { + DEBUG(LOG_INFO, "unicasting packet to client yiaddr"); + ciaddr = payload->yiaddr; + chaddr = payload->chaddr; + } + return raw_packet(payload, server_config.server, SERVER_PORT, + ciaddr, CLIENT_PORT, chaddr, server_config.ifindex); +} + + +/* send a dhcp packet, if force broadcast is set, the packet will be broadcast to the client */ +static int send_packet(struct dhcpMessage *payload, int force_broadcast) +{ + int ret; + + if (payload->giaddr) + ret = send_packet_to_relay(payload); + else ret = send_packet_to_client(payload, force_broadcast); + return ret; +} + + +static void init_packet(struct dhcpMessage *packet, struct dhcpMessage *oldpacket, char type) +{ + init_header(packet, type); + packet->xid = oldpacket->xid; + memcpy(packet->chaddr, oldpacket->chaddr, 16); + packet->flags = oldpacket->flags; + packet->giaddr = oldpacket->giaddr; + packet->ciaddr = oldpacket->ciaddr; + add_simple_option(packet->options, DHCP_SERVER_ID, server_config.server); +} + + +/* add in the bootp options */ +static void add_bootp_options(struct dhcpMessage *packet) +{ + packet->siaddr = server_config.siaddr; + if (server_config.sname) + strncpy((char *)packet->sname, server_config.sname, sizeof(packet->sname) - 1); + if (server_config.boot_file) + strncpy((char *)packet->file, server_config.boot_file, sizeof(packet->file) - 1); +} + + +/* send a DHCP OFFER to a DHCP DISCOVER */ +int sendOffer(struct dhcpMessage *oldpacket) +{ +#ifdef DHCPD_HEAP_REPLACE_STACK + struct dhcpMessage *packet; +#else + struct dhcpMessage packet; +#endif + struct dhcpOfferedAddr *lease = NULL; + u_int32_t req_align, lease_time_align = server_config.lease; + unsigned char *req, *lease_time; + struct option_set *curr; + //struct in_addr addr; + +#ifdef DHCPD_HEAP_REPLACE_STACK + packet = calloc(1,sizeof(struct dhcpMessage)); + if (!packet) { + DHCPD_LOG(LOG_ERR, "Calloc failed...%d",__LINE__); + return -1; + } + init_packet(packet, oldpacket, DHCPOFFER); +#else + init_packet(&packet, oldpacket, DHCPOFFER); +#endif + + /* ADDME: if static, short circuit */ + /* the client is in our lease/offered table */ + if ((lease = find_lease_by_chaddr(oldpacket->chaddr))) { + if (!lease_expired(lease)) + lease_time_align = lease->expires - time(0); +#ifdef DHCPD_HEAP_REPLACE_STACK + packet->yiaddr = lease->yiaddr; +#else + packet.yiaddr = lease->yiaddr; +#endif + /* Or the client has a requested ip */ + } else if ((req = get_option(oldpacket, DHCP_REQUESTED_IP)) && + + /* Don't look here (ugly hackish thing to do) */ + memcpy(&req_align, req, 4) && + + /* and the ip is in the lease range */ + ntohl(req_align) >= ntohl(server_config.start) && + ntohl(req_align) <= ntohl(server_config.end) && + + /* and its not already taken/offered */ /* ADDME: check that its not a static lease */ + ((!(lease = find_lease_by_yiaddr(req_align)) || + + /* or its taken, but expired */ /* ADDME: or maybe in here */ + lease_expired(lease)))) { +#ifdef DHCPD_HEAP_REPLACE_STACK + packet->yiaddr = req_align; /* FIXME: oh my, is there a host using this IP? */ +#else + packet.yiaddr = req_align; /* FIXME: oh my, is there a host using this IP? */ +#endif + + /* otherwise, find a free IP */ /*ADDME: is it a static lease? */ + } else { +#ifdef DHCPD_HEAP_REPLACE_STACK + packet->yiaddr = find_address(0); + /* try for an expired lease */ + if (!packet->yiaddr) packet->yiaddr = find_address(1); +#else + packet.yiaddr = find_address(0); + + /* try for an expired lease */ + if (!packet.yiaddr) packet.yiaddr = find_address(1); +#endif + } +#ifdef DHCPD_HEAP_REPLACE_STACK + if(!(packet->yiaddr)) { + if (packet != NULL) + free(packet); + +#else + if(!packet.yiaddr) { +#endif + DHCPD_LOG(LOG_WARNING, "no IP addresses to give -- OFFER abandoned"); + return -1; + } +#ifdef DHCPD_HEAP_REPLACE_STACK + if (!add_lease(packet->chaddr, packet->yiaddr, server_config.offer_time)) { + if (packet != NULL) { + free(packet); + packet = NULL; + } +#else + if (!add_lease(packet.chaddr, packet.yiaddr, server_config.offer_time)) { +#endif + DHCPD_LOG(LOG_WARNING, "lease pool is full -- OFFER abandoned"); + return -1; + } + + if ((lease_time = get_option(oldpacket, DHCP_LEASE_TIME))) { + memcpy(&lease_time_align, lease_time, 4); + lease_time_align = ntohl(lease_time_align); + if (lease_time_align > server_config.lease) + lease_time_align = server_config.lease; + } + + /* Make sure we aren't just using the lease time from the previous offer */ + if (lease_time_align < server_config.min_lease) + lease_time_align = server_config.lease; + /* ADDME: end of short circuit */ +#ifdef DHCPD_HEAP_REPLACE_STACK + struct netif *netif = netif_find(server_config.interface); + + add_simple_option(packet->options, DHCP_LEASE_TIME, htonl(lease_time_align)); +#ifdef __CONFIG_LWIP_V1 + add_simple_option(packet->options, DHCP_SUBNET, ip4_addr_get_u32(&netif->netmask)); + add_simple_option(packet->options, DHCP_ROUTER, ip4_addr_get_u32(&netif->gw)); + add_simple_option(packet->options, DHCP_DNS_SERVER, ip4_addr_get_u32(&netif->ip_addr)); +#elif LWIP_IPV4 /* now only for IPv4 */ + add_simple_option(packet->options, DHCP_SUBNET, ip4_addr_get_u32(ip_2_ip4(&netif->netmask))); + add_simple_option(packet->options, DHCP_ROUTER, ip4_addr_get_u32(ip_2_ip4(&netif->gw))); + add_simple_option(packet->options, DHCP_DNS_SERVER, ip4_addr_get_u32(ip_2_ip4(&netif->ip_addr))); +#else + #error "IPv4 not support!" +#endif + +#else + add_simple_option(packet.options, DHCP_LEASE_TIME, htonl(lease_time_align)); +#endif + + curr = server_config.options; + while (curr) { + if (curr->data[OPT_CODE] != DHCP_LEASE_TIME) +#ifdef DHCPD_HEAP_REPLACE_STACK + add_option_string(packet->options, curr->data); +#else + add_option_string(packet.options, curr->data); +#endif + curr = curr->next; + } +#ifdef DHCPD_HEAP_REPLACE_STACK + add_bootp_options(packet); + + //addr.s_addr = packet->yiaddr; + DHCPD_LOG(LOG_INFO, "sending OFFER of %s", inet_ntoa(packet->yiaddr)); + int ret = send_packet(packet, 0); + if (packet != NULL) { + free(packet); + packet = NULL; + } + return ret; +#else + add_bootp_options(&packet); + + addr.s_addr = packet.yiaddr; + DHCPD_LOG(LOG_INFO, "sending OFFER of %s", inet_ntoa(addr)); + return send_packet(&packet, 0); +#endif +} + + +int sendNAK(struct dhcpMessage *oldpacket) +{ +#ifdef DHCPD_HEAP_REPLACE_STACK + struct dhcpMessage *packet; +#else + struct dhcpMessage packet; +#endif +#ifdef DHCPD_HEAP_REPLACE_STACK + packet = calloc(1,sizeof(struct dhcpMessage)); + if (!packet) + DHCPD_LOG(LOG_ERR, "Calloc failed...%d",__LINE__); + init_packet(packet, oldpacket, DHCPNAK); +#else + init_packet(&packet, oldpacket, DHCPNAK); +#endif + + DEBUG(LOG_INFO, "sending NAK"); +#ifdef DHCPD_HEAP_REPLACE_STACK + int ret = send_packet(packet, 1); + if (packet != NULL) + free(packet); + return ret; +#else + return send_packet(&packet, 1); +#endif +} + + +int sendACK(struct dhcpMessage *oldpacket, u_int32_t yiaddr) +{ +#ifdef DHCPD_HEAP_REPLACE_STACK + struct dhcpMessage *packet; +#else + struct dhcpMessage packet; +#endif + struct option_set *curr; + unsigned char *lease_time; + u_int32_t lease_time_align = server_config.lease; + //struct in_addr addr; + +#ifdef DHCPD_HEAP_REPLACE_STACK + packet = calloc(1,sizeof(struct dhcpMessage)); + if (!packet) + DHCPD_LOG(LOG_ERR, "Calloc failed...%d",__LINE__); + init_packet(packet, oldpacket, DHCPACK); + packet->yiaddr = yiaddr; +#else + init_packet(&packet, oldpacket, DHCPACK); + + packet.yiaddr = yiaddr; +#endif + + if ((lease_time = get_option(oldpacket, DHCP_LEASE_TIME))) { + memcpy(&lease_time_align, lease_time, 4); + lease_time_align = ntohl(lease_time_align); + if (lease_time_align > server_config.lease) + lease_time_align = server_config.lease; + else if (lease_time_align < server_config.min_lease) + lease_time_align = server_config.lease; + } +#ifdef DHCPD_HEAP_REPLACE_STACK + struct netif *netif = netif_find(server_config.interface); + + add_simple_option(packet->options, DHCP_LEASE_TIME, htonl(lease_time_align)); +#ifdef __CONFIG_LWIP_V1 + add_simple_option(packet->options, DHCP_SUBNET, ip4_addr_get_u32(&netif->netmask)); + add_simple_option(packet->options, DHCP_ROUTER, ip4_addr_get_u32(&netif->gw)); + add_simple_option(packet->options, DHCP_DNS_SERVER, ip4_addr_get_u32(&netif->ip_addr)); +#elif LWIP_IPV4 /* now only for IPv4 */ + add_simple_option(packet->options, DHCP_SUBNET, ip4_addr_get_u32(ip_2_ip4(&netif->netmask))); + add_simple_option(packet->options, DHCP_ROUTER, ip4_addr_get_u32(ip_2_ip4(&netif->gw))); + add_simple_option(packet->options, DHCP_DNS_SERVER, ip4_addr_get_u32(ip_2_ip4(&netif->ip_addr))); +#else + #error "IPv4 not support!" +#endif + +#else + add_simple_option(packet.options, DHCP_LEASE_TIME, htonl(lease_time_align)); +#endif + curr = server_config.options; + while (curr) { + if (curr->data[OPT_CODE] != DHCP_LEASE_TIME) +#ifdef DHCPD_HEAP_REPLACE_STACK + add_option_string(packet->options, curr->data); +#else + add_option_string(packet.options, curr->data); +#endif + curr = curr->next; + } +#ifdef DHCPD_HEAP_REPLACE_STACK + add_bootp_options(packet); + + //addr.s_addr = packet->yiaddr; + DHCPD_LOG(LOG_INFO, "sending ACK to %s", inet_ntoa(packet->yiaddr)); + int ret = 0; + if (send_packet(packet, 0) < 0) + ret = -1; + + add_lease(packet->chaddr, packet->yiaddr, lease_time_align); + + if (packet) + free(packet); + return ret; +#else + add_bootp_options(&packet); + + //addr.s_addr = packet.yiaddr; + DHCPD_LOG(LOG_INFO, "sending ACK to %s", inet_ntoa(packet->yiaddr)); + + if (send_packet(&packet, 0) < 0) + return -1; + + add_lease(packet.chaddr, packet.yiaddr, lease_time_align); + return 0; +#endif +} + + +int send_inform(struct dhcpMessage *oldpacket) +{ +#ifdef DHCPD_HEAP_REPLACE_STACK + struct dhcpMessage *packet; +#else + struct dhcpMessage packet; +#endif + struct option_set *curr; +#ifdef DHCPD_HEAP_REPLACE_STACK + packet = calloc(1,sizeof(struct dhcpMessage)); + if (!packet) + DHCPD_LOG(LOG_ERR, "Calloc failed...%d",__LINE__); + init_packet(packet, oldpacket, DHCPACK); +#else + init_packet(&packet, oldpacket, DHCPACK); +#endif + + curr = server_config.options; + while (curr) { + if (curr->data[OPT_CODE] != DHCP_LEASE_TIME) +#ifdef DHCPD_HEAP_REPLACE_STACK + add_option_string(packet->options, curr->data); +#else + add_option_string(packet.options, curr->data); +#endif + curr = curr->next; + } +#ifdef DHCPD_HEAP_REPLACE_STACK + add_bootp_options(packet); + + int ret = send_packet(packet, 0); + if (packet) + free(packet); + return ret; +#else + add_bootp_options(&packet); + + return send_packet(&packet, 0); +#endif +} + + + diff --git a/platform/mcu/xr871/src/net/udhcp/serverpacket.h b/platform/mcu/xr871/src/net/udhcp/serverpacket.h new file mode 100644 index 0000000000..5a4fb27684 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/serverpacket.h @@ -0,0 +1,11 @@ +#ifndef _SERVERPACKET_H +#define _SERVERPACKET_H + + +int sendOffer(struct dhcpMessage *oldpacket); +int sendNAK(struct dhcpMessage *oldpacket); +int sendACK(struct dhcpMessage *oldpacket, u_int32_t yiaddr); +int send_inform(struct dhcpMessage *oldpacket); + + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/socket.c b/platform/mcu/xr871/src/net/udhcp/socket.c new file mode 100644 index 0000000000..5a517d43eb --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/socket.c @@ -0,0 +1,211 @@ +/* + * socket.c -- DHCP server client/server socket creation + * + * udhcp client/server + * Copyright (C) 1999 Matthew Ramsay + * Chris Trew + * + * Rewrite by Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#ifdef DHCPD_LWIP +#include +#else +#include +#include +#include +#include +#include +#include +#endif + +#ifndef DHCPD_FREERTOS +#include +#endif + +#include +#include + +#if __GLIBC__ >=2 && __GLIBC_MINOR >= 1 +#include +#include +#elif __LINUX +#include +#include +#include +#endif + +#ifdef DHCPD_LWIP +#include "netif/etharp.h" +#include "lwip/sockets.h" +#include +#include "dhcpd.h" +#endif +#include "debug.h" + +#ifdef DHCPD_USRCFG +#include "dhcpd_cfg.h" +#endif + +int read_interface(char *interface, int *ifindex, u_int32_t *addr, unsigned char *arp) +{ +#ifndef DHCPD_LWIP + int fd; + struct ifreq ifr; + struct sockaddr_in *our_ip; + + memset(&ifr, 0, sizeof(struct ifreq)); + if((fd = socket(AF_INET, SOCK_RAW, IPPROTO_RAW)) >= 0) { + ifr.ifr_addr.sa_family = AF_INET; + strcpy(ifr.ifr_name, interface); + + if (addr) { + if (ioctl(fd, SIOCGIFADDR, &ifr) == 0) { + our_ip = (struct sockaddr_in *) &ifr.ifr_addr; + *addr = our_ip->sin_addr.s_addr; + DEBUG(LOG_INFO, "%s (our ip) = %s", ifr.ifr_name, inet_ntoa(our_ip->sin_addr)); + } else { + DHCPD_LOG(LOG_ERR, "SIOCGIFADDR failed, is the interface up and configured?: %s", + strerror(errno)); + return -1; + } + } + + if (ioctl(fd, SIOCGIFINDEX, &ifr) == 0) { + DEBUG(LOG_INFO, "adapter index %d", ifr.ifr_ifindex); + *ifindex = ifr.ifr_ifindex; + } else { + DHCPD_LOG(LOG_ERR, "SIOCGIFINDEX failed!: %s", strerror(errno)); + return -1; + } + if (ioctl(fd, SIOCGIFHWADDR, &ifr) == 0) { + memcpy(arp, ifr.ifr_hwaddr.sa_data, 6); + DEBUG(LOG_INFO, "adapter hardware address %02x:%02x:%02x:%02x:%02x:%02x", + arp[0], arp[1], arp[2], arp[3], arp[4], arp[5]); + } else { + DHCPD_LOG(LOG_ERR, "SIOCGIFHWADDR failed!: %s", strerror(errno)); + return -1; + } + } else { + DHCPD_LOG(LOG_ERR, "socket failed!: %s", strerror(errno)); + return -1; + } + close(fd); +#else + struct netif *netif = netif_find(interface); + if (netif != NULL) + *ifindex = netif->num; + else + return -1; + + memcpy(addr, &(netif->ip_addr), 4); + memcpy(arp, netif->hwaddr, 6); + DHCPD_LOG(LOG_INFO, "Obtain addr :%s,hwaddr:[%02x:%02x:%02x:%02x:%02x:%02x]",inet_ntoa(*addr),arp[0],arp[1],arp[2],arp[3],arp[4],arp[5]); +#endif + return 0; +} + + +int listen_socket(unsigned int ip, int port, char *inf) +{ +#ifndef DHCPD_LWIP + struct ifreq interface; +#endif + int fd; + struct sockaddr_in addr; + int n = 1; + + DEBUG(LOG_INFO, "Opening listen socket on 0x%08x:%d %s\n", ip, port, inf); + if ((fd = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) { + DEBUG(LOG_ERR, "socket call failed: %s", strerror(errno)); + return -1; + } + + memset(&addr, 0, sizeof(addr)); + addr.sin_family = AF_INET; + addr.sin_port = htons(port); + addr.sin_addr.s_addr = ip; + + if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *) &n, sizeof(n)) == -1) { +#ifdef DHCPD_LWIP + closesocket(fd); +#else + close(fd); +#endif + return -1; + } + if (setsockopt(fd, SOL_SOCKET, SO_BROADCAST, (char *) &n, sizeof(n)) == -1) { +#ifdef DHCPD_LWIP + closesocket(fd); +#else + close(fd); +#endif + return -1; + } +#ifndef DHCPD_LWIP + strncpy(interface.ifr_ifrn.ifrn_name, inf, IFNAMSIZ); + if (setsockopt(fd, SOL_SOCKET, SO_BINDTODEVICE,(char *)&interface, sizeof(interface)) < 0) { + close(fd); + return -1; + } +#endif + if (bind(fd, (struct sockaddr *)&addr, sizeof(struct sockaddr)) == -1) { +#ifdef DHCPD_LWIP + closesocket(fd); +#else + close(fd); +#endif + return -1; + } + + return fd; +} + +#define ETH_P_IP ETHTYPE_IP +int raw_socket(int ifindex) +{ +#if 0 + int fd; + struct sockaddr_ll sock; + + DEBUG(LOG_INFO, "Opening raw socket on ifindex %d\n", ifindex); + if ((fd = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_IP))) < 0) { + DEBUG(LOG_ERR, "socket call failed: %s", strerror(errno)); + return -1; + } + + sock.sll_family = AF_PACKET; + sock.sll_protocol = htons(ETH_P_IP); + sock.sll_ifindex = ifindex; + if (bind(fd, (struct sockaddr *) &sock, sizeof(sock)) < 0) { + DEBUG(LOG_ERR, "bind call failed: %s", strerror(errno)); +#ifdef DHCPD_LWIP + closesocket(fd); +#else + close(fd); +#endif + return -1; + } + + return fd; + +#endif + return 0; +} + diff --git a/platform/mcu/xr871/src/net/udhcp/socket.h b/platform/mcu/xr871/src/net/udhcp/socket.h new file mode 100644 index 0000000000..333994b8f7 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/socket.h @@ -0,0 +1,9 @@ +/* socket.h */ +#ifndef _SOCKET_H +#define _SOCKET_H + +int read_interface(char *interface, int *ifindex, u_int32_t *addr, unsigned char *arp); +int listen_socket(unsigned int ip, int port, char *inf); +int raw_socket(int ifindex); + +#endif diff --git a/platform/mcu/xr871/src/net/udhcp/udhcp.mk b/platform/mcu/xr871/src/net/udhcp/udhcp.mk new file mode 100644 index 0000000000..5a720e5d1b --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/udhcp.mk @@ -0,0 +1,25 @@ +NAME := udhcp + +$(NAME)_TYPE := kernel + +$(NAME)_SOURCES := usr_dhcpd.c \ + arpping.c \ + files.c \ + leases.c \ + serverpacket.c \ + options.c \ + socket.c \ + packet.c \ + dhcp_time.c \ + dns_server.c + +VER := 0.9.8 +$(NAME)_CFLAGS += -DVERSION='"$(VER)"' -DXR_DHCPD +$(NAME)_CFLAGS += -DDHCPD_TIMEALT \ + -DDHCPD_LWIP \ + -DDHCPD_HEAP_REPLACE_STACK \ + -DDHCPD_USRCFG \ + -DDHCPD_FREERTOS \ + -DDHCPD_ICMPPING \ + -DDHCPD_LOW_LEVEL \ + -DDHCPD_DNS diff --git a/platform/mcu/xr871/src/net/udhcp/udhcpc.8 b/platform/mcu/xr871/src/net/udhcp/udhcpc.8 new file mode 100644 index 0000000000..752a736c0d --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/udhcpc.8 @@ -0,0 +1,208 @@ +.TH UDHCPC 8 2001-09-26 GNU/Linux "GNU/Linux Administrator's Manual" +.SH NAME +udhcpc \- very small DHCP client +.SH SYNOPSIS +.B udhcpc +.RI [ OPTION ]... +.SH DESCRIPTION +The udhcp client negotiates a lease with the DHCP server and +executes a script when it is obtained or lost. +.SH OPTIONS +.TP +.BI \-c\ CLIENTID ,\ \-\-clientid= CLIENTID +Send the client identifier +.IR CLIENTID . +.TP +.BR -f ,\ \-\-foreground +Do not fork after obtaining a lease. +.TP +.BI \-H\ HOSTNAME ,\ \-\-hostname= HOSTNAME +Send the client hostname +.IR HOSTNAME . +.TP +.BI \-h\ HOSTNAME +Alias for -H +.IR HOSTNAME . +.TP +.BI \-i\ INTERFACE ,\ \-\-interface= INTERFACE +Configure +.IR INTERFACE . +.TP +.BR -n ,\ \-\-now +Exit with failure if a lease cannot be obtained. +.TP +.BI \-p\ FILE ,\ \-\-pidfile= FILE +Write the process ID of the daemon to +.IR FILE . +.TP +.BR -q ,\ \-\-quit +Exit after obtaining a lease. +.TP +.BI \-r\ ADDRESS ,\ \-\-request= ADDRESS +Request IP address +.IR ADDRESS . +.TP +.BI \-s\ FILE ,\ \-\-script= FILE +Use script +.IR FILE . +.TP +.BR -v ,\ \-\-version +Display version. +.SH USAGE +When an event occurs, +.B udhcpc +executes a script. There are four possible arguments to this +script: +.TP +.B deconfig +.B deconfig +is used when +.B udhcpc +starts, and when a lease is lost. The script should put the +interface in an up, but deconfigured, state. +.TP +.B bound +.B bound +is used when +.B udhcpc +moves from an unbound to a bound state. The script should +configure the interface and set any other relevant parameters +(e.g., default gateway, dns server, etc.). +.TP +.B renew +.B renew +is used when +.B udhcpc +when a lease is renewed. The interface is already +configured, so the IP address will not change. Other parameters +(e.g., default gateway, subnet mask, dns server) may. +.TP +.B nak +.B nak +is used when +.B udhcpc +receieves a NAK packet from the server. The +enviromental variable +.B $message +will contain the reason for the +NAK message if the server included one. Processing this message +is optional, as the script will also be called with deconfig if +need be. +.PP +Parameters are passed to the script via the following environment +variables: +.TP +.B HOME +The inherited HOME, or "/" if it is unset. +.TP +.B PATH +The inherited PATH, or "/bin:/usr/bin:/sbin:/usr/sbin" if it is +unset. +.TP +.B interface +The interface. +.TP +.B ip +The client IP address. +.TP +.B siaddr +The BOOTP next server option. +.TP +.B sname +The BOOTP server name option. +.TP +.B boot_file +The BOOTP boot file option. +.TP +.B subnet +The subnet mask. +.TP +.B timezone +The timezone offset from UTC in seconds. +.TP +.B router +The list of routers. +.TP +.B timesvr +The list of time servers. +.TP +.B namesvr +The list of IEN 116 name servers. +.TP +.B dns +The list of DNS servers. +.TP +.B logsvr +The list of MIT-LCS UDP log servers. +.TP +.B cookiesvr +The list of RFC 865 cookie servers. +.TP +.B lprsvr +The list of LPR servers. +.TP +.B hostname +The host name. +.TP +.B bootsize +The length in 512-octet blocks of the bootfile. +.TP +.B domain +The domain name of the network. +.TP +.B swapsvr +The client's swap server. +.TP +.B rootpath +The path of the client's root dist. +.TP +.B ipttl +The TTL. +.TP +.B mtu +The MTU. +.TP +.B broadcast +The broadcast address. +.TP +.B ntpsrv +The list of NTP servers. +.TP +.B wins +The list of WINS servers. +.TP +.B lease +The lease time in seconds. +.TP +.B dhcptype +The DHCP message type (safely ignored). +.TP +.B serverid +The server IP address. +.TP +.B message +Reason for a DHCPNAK. +.TP +.B tftp +The TFTP server name. +.TP +.B bootfile +The bootfile name. +.SH FILES +.TP +.I /usr/share/udhcpc/default.script +Script run when leases are obtained or lost. +.SH NOTES +.B udhcpc +responds to the following signals: +.TP +.B SIGUSR1 +This signal causes +.B udhcpc +to renew the current lease or, if it does not have one, obtain a +new lease. +.TP +.B SIGUSR2 +This signal caused +.B udhcpc +to release the current lease. diff --git a/platform/mcu/xr871/src/net/udhcp/udhcpd.8 b/platform/mcu/xr871/src/net/udhcp/udhcpd.8 new file mode 100644 index 0000000000..be8fac888c --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/udhcpd.8 @@ -0,0 +1,17 @@ +.TH UDHCPD 8 2001-09-27 GNU/Linux "GNU/Linux Administrator's Manual" +.SH NAME +udhcpd \- very small DHCP server +.SH SYNOPSIS +.B udhcpd +.SH DESCRIPTION +The udhcp server negotiates leases with DHCP clients. +.SH FILES +.TP +.I /etc/udhcpd.conf +Configuration file. +.TP +.I /var/lib/misc/udhcpd.leases +Lease information file. +.SH SEE ALSO +.BR dumpleases (1), +.BR udhcpd.conf (8). diff --git a/platform/mcu/xr871/src/net/udhcp/udhcpd.conf.5 b/platform/mcu/xr871/src/net/udhcp/udhcpd.conf.5 new file mode 100644 index 0000000000..b86a9f51f0 --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/udhcpd.conf.5 @@ -0,0 +1,164 @@ +.TH UDHCPD.CONF 5 2001-09-26 GNU/Linux "GNU/Linux Administrator's Manual" +.SH NAME +udhcpd.conf \- udhcp server configuration file +.SH DESCRIPTION +The file +.I /etc/udhcpd.conf +contains configuration information specific to the udhcp server. +It should contain one configuration keyword per line, followed by +appropriate configuration information. +.SH OPTIONS +.TP +.BI start\ ADDRESS +The starting address of the IP lease block is +.IR ADDRESS . +The default is +.BR 192.168.0.20 . +.TP +.BI end\ ADDRESS +The ending address of the IP lease block is +.IR ADDRESS . +The default is +.BR 192.168.0.254 . +.TP +.BI interface\ INTERFACE +The udhcp server should listen on +.IR INTERFACE . +The default is +.BR eth0 . +.TP +.BI max_leases\ LEASES +Offer at most +.I LEASES +leases (including those reserved by OFFERs, DECLINEs, and ARP +conflicts). The default is +.BR 254 . +.TP +.BI remaining\ REMAINING +If +.I REMAINING +is +.BR yes , +store the time remaining for each lease. If it is +.BR no , +store the expiration time for each lease. The default is +.BR yes . +.TP +.BI auto_time\ SECONDS +Write the lease information to a file every +.I SECONDS +seconds. The default is +.BR 7200 . +.TP +.BI decline_time\ SECONDS +Reserve an IP for +.I SECONDS +seconds if a DHCP decline message is received. The default is +.BR 3600 . +.TP +.BI conflict_time\ SECONDS +Reserve an IP for +.I SECONDS +seconds if an ARP conflict occurs. The default is +.BR 3600 . +.TP +.BI offer_time\ SECONDS +Reserve an IP for +.I SECONDS +seconds if it is offered. The default is +.BR 60 . +.TP +.BI min_lease\ SECONDS +Reserve an IP for the full lease time if the lease to be given is less than +.I SECONDS +seconds. The default is +.BR 60 . +.TP +.BI lease_file\ FILE +Write the lease information to +.IR FILE . +The default is +.BR /var/lib/misc/udhcpd.leases . +.TP +.BI pidfile\ FILE +Write the process ID to +.IR FILE . +The default is +.BR /var/run/udhcpd.pid . +.TP +.BI notify_file\ FILE +Execute +.I FILE +after the lease information is written. By default, no file is executed. +.TP +.BI siaddr\ ADDRESS +BOOTP specific option. The default is +.BR 0.0.0.0 . +.TP +.BI sname\ NAME +BOOTP specific option. There is no default. +.TP +.BI boot_file\ FILE +BOOTP specific option. There is no default. +.TP +.BI option\ OPTION +DHCP specific option. +.RS +.TP +.BI subnet\ ADDRESS +.TP +.BI timezone\ OFFSET +.TP +.BI router\ ADDRESS... +.TP +.BI timesvr\ ADDRESS... +.TP +.BI namesvr\ ADDRESS... +.TP +.BI dns\ ADDRESS... +.TP +.BI logsvr\ ADDRESS... +.TP +.BI cookiesvr\ ADDRESS... +.TP +.BI lprsvr\ ADDRESS... +.TP +.BI hostname\ HOSTNAME +.TP +.BI bootsize\ SIZE +.TP +.BI domain\ DOMAIN +.TP +.BI swapsvr\ ADDRESS +.TP +.BI rootpath\ PATH +.TP +.BI ipttl\ TTL +.TP +.BI mtu\ MTU +.TP +.BI broadcast\ ADDRESS +.TP +.BI ntpsrv\ ADDRESS... +.TP +.BI wins\ ADDRESS... +.TP +.BI requestip\ ADDRESS +.TP +.BI lease\ SECONDS +.TP +.BI dhcptype\ TYPE +.TP +.BI serverid\ ADDRESS +.TP +.BI tftp\ FILE +.TP +.BI bootfile\ FILE +The default for +.B lease +is +.BR 864000 . +There are no defaults for the other options. +.RE +.SH SEE ALSO +.BR udhcpd (8). diff --git a/platform/mcu/xr871/src/net/udhcp/usr_dhcpd.c b/platform/mcu/xr871/src/net/udhcp/usr_dhcpd.c new file mode 100644 index 0000000000..191eb74ecc --- /dev/null +++ b/platform/mcu/xr871/src/net/udhcp/usr_dhcpd.c @@ -0,0 +1,333 @@ +/* dhcpd.c + * + * udhcp Server + * Copyright (C) 1999 Matthew Ramsay + * Chris Trew + * + * Rewrite by Russ Dill July 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lwip/sockets.h" +#include "debug.h" +#include "dhcpd.h" +#include "arpping.h" +#include "socket.h" +#include "options.h" +#include "files.h" +#include "leases.h" +#include "packet.h" +#include "serverpacket.h" +#include "net/udhcp/usr_dhcpd.h" +#include "dns.h" + +/* globals */ +struct dhcpOfferedAddr *leases = NULL; +struct server_config_t server_config; + +#define DHCPD_THREAD_STACK_SIZE (2 * 1024) +static OS_Thread_t g_dhcpd_thread; + +static void udhcpd_start(void *arg) +{ +#ifdef DHCPD_DNS + fd_set fds; + int maxfdp; + int ret; + + int dns_socket = -1; + char *dns_buf = NULL; + dns_buf = malloc(DNS_BUF_SIZE); + if (!dns_buf) { + DNS_ERR("dns buf malloc faild\n"); + return; + } +#endif + int server_socket = -1; + int bytes = 0; + struct dhcpMessage *packet = NULL; + packet = malloc(sizeof(*packet)); + if (!packet) { + DHCPD_LOG(LOG_ERR, "udhcp server (v%s) started", VERSION); +#ifdef DHCPD_DNS + free(dns_buf); +#endif + return; + } + unsigned char *state; + unsigned char *server_id, *requested; + uint32_t server_id_align, requested_align; + struct option_set *option; + struct dhcpOfferedAddr *lease; + struct dhcp_server_info *server_param = NULL; + if (arg != NULL) + server_param = (struct dhcp_server_info *) arg; + + DEBUG(LOG_INFO, "udhcp server (v%s) started", VERSION); + + memset(&server_config, 0, sizeof(struct server_config_t)); + init_config(); + + if (server_param != NULL && server_param->lease_time > server_config.min_lease) { + server_config.lease = server_param->lease_time; + } else if ((option = find_option(server_config.options, DHCP_LEASE_TIME))) { + memcpy(&server_config.lease, option->data + 2, 4); + server_config.lease = ntohl(server_config.lease); + } else + server_config.lease = LEASE_TIME; + + if (read_interface(server_config.interface, &server_config.ifindex, + &server_config.server, server_config.arp) < 0) { + goto exit_server; + } + + if (server_param != NULL && server_param->max_leases > 0) + server_config.max_leases = server_param->max_leases; + + if (server_param != NULL && server_param->addr_start != 0 + && server_param->addr_end != 0 + && ntohl(server_param->addr_end) >= ntohl(server_param->addr_start)) { + server_config.start = server_param->addr_start; + server_config.end = server_param->addr_end; + } + if ((ntohl(server_param->addr_end) - ntohl(server_param->addr_start)) > (server_config.max_leases - 1)) + server_config.end = htonl((ntohl(server_config.start) + server_config.max_leases - 1)); + + leases = malloc(sizeof(struct dhcpOfferedAddr) * server_config.max_leases); + memset(leases, 0, sizeof(struct dhcpOfferedAddr) * server_config.max_leases); + DEBUG(LOG_DEBUG, "start ip=%s", inet_ntoa(server_config.start)); + DEBUG(LOG_DEBUG, "end ip=%s", inet_ntoa(server_config.end)); + + while(1) { /* loop until universe collapses */ + + if (server_socket < 0) + if ((server_socket = listen_socket(INADDR_ANY, SERVER_PORT, server_config.interface)) < 0) { + DEBUG(LOG_ERR, "FATAL: couldn't create server socket, %s", strerror(errno)); + goto exit_server; + } +#ifdef DHCPD_DNS + if (dns_socket < 0) + if ((dns_socket = dns_listen_socket()) < 0) { + DNS_ERR("FATAL: couldn't create dns server socket\n"); + goto exit_server; + } + + FD_ZERO(&fds); + FD_SET(server_socket, &fds); + FD_SET(dns_socket, &fds); + maxfdp = server_socket > dns_socket ? server_socket + 1 : dns_socket + 1; + ret = select(maxfdp, &fds, NULL, NULL, NULL); + if (ret < 0) + goto exit_server; + else if (ret == 0) + continue; + if (FD_ISSET(dns_socket, &fds)) + dns_server(dns_socket, dns_buf, DNS_BUF_SIZE); + + if (FD_ISSET(server_socket, &fds)) { +#endif + if ((bytes = get_packet(packet, server_socket)) < 0) { /* this waits for a packet - idle */ + if (bytes == -1 && errno != EINTR) { + DEBUG(LOG_INFO, "error on read, %s, reopening socket", strerror(errno)); + closesocket(server_socket); + server_socket = -1; + } else if (bytes == -3) { + DEBUG(LOG_INFO, "exit server.."); + closesocket(server_socket); + server_socket = -1; + goto exit_server; + } + continue; + } + + if ((state = get_option(packet, DHCP_MESSAGE_TYPE)) == NULL) { + DEBUG(LOG_ERR, "couldn't get option from packet, ignoring"); + continue; + } + /* ADDME: look for a static lease */ + lease = find_lease_by_chaddr(packet->chaddr); + DEBUG(LOG_INFO, "MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + packet->chaddr[0],packet->chaddr[1], + packet->chaddr[2],packet->chaddr[3], + packet->chaddr[4],packet->chaddr[5]); + switch (state[0]) { + case DHCPDISCOVER: + DEBUG(LOG_INFO,"received DISCOVER"); + if (sendOffer(packet) < 0) { + DEBUG(LOG_ERR, "send OFFER failed"); + } + break; + case DHCPREQUEST: + DEBUG(LOG_INFO, "received REQUEST"); + requested = get_option(packet, DHCP_REQUESTED_IP); + server_id = get_option(packet, DHCP_SERVER_ID); + + if (requested) { + memcpy(&requested_align, requested, 4); + DEBUG(LOG_INFO, "requeste id = %s", inet_ntoa(requested_align)); + } + if (server_id) { + memcpy(&server_id_align, server_id, 4); + DEBUG(LOG_INFO, "server id = %s", inet_ntoa(server_id_align)); + } + + if (lease) { /*ADDME: or static lease */ + if (server_id) { + /* SELECTING State */ + DEBUG(LOG_INFO, "server_id = %08x", ntohl(server_id_align)); + if (server_id_align == server_config.server && requested && + requested_align == lease->yiaddr) { + sendACK(packet, lease->yiaddr); + } + } else { + if (requested) { + /* INIT-REBOOT State */ + if (lease->yiaddr == requested_align) + sendACK(packet, lease->yiaddr); + else sendNAK(packet); + } else { + /* RENEWING or REBINDING State */ + if (lease->yiaddr == packet->ciaddr) + sendACK(packet, lease->yiaddr); + else { + /* don't know what to do!!!! */ + sendNAK(packet); + } + } + } + + /* what to do if we have no record of the client */ + } else if (server_id) { + /* SELECTING State */ + + } else if (requested) { + /* INIT-REBOOT State */ + if ((lease = find_lease_by_yiaddr(requested_align))) { + if (lease_expired(lease)) { + /* probably best if we drop this lease */ + memset(lease->chaddr, 0, 16); + /* make some contention for this address */ + } else sendNAK(packet); + } else { + sendNAK(packet); + } + } else { + /* RENEWING or REBINDING State */ + } + break; + case DHCPDECLINE: + DEBUG(LOG_INFO,"received DECLINE"); + if (lease) { + memset(lease->chaddr, 0, 16); + lease->expires = time(0) + server_config.decline_time; + } + break; + case DHCPRELEASE: + DEBUG(LOG_INFO,"received RELEASE"); + if (lease) lease->expires = time(0); + break; + case DHCPINFORM: + DEBUG(LOG_INFO,"received INFORM"); + send_inform(packet); + break; + default: + DEBUG(LOG_WARNING, "unsupported DHCP message (%02x) -- ignoring", state[0]); + } +#ifdef DHCPD_DNS + } +#endif + } + +exit_server: +#ifdef DHCPD_DNS + if (dns_buf != NULL) { + free(dns_buf); + dns_buf = NULL; + } + if (dns_socket >= 0) + closesocket(dns_socket); +#endif + if (packet != NULL ) { + free(packet); + packet = NULL; + } + if (leases != NULL) { + free(leases); + leases = NULL; + } + OS_ThreadDelete(&g_dhcpd_thread); +} + +static int udhcpd_stop(void) +{ + int fd; + struct sockaddr_in addr_serv; + char *stop_msg = ""; + if ((fd = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) { + DEBUG(LOG_ERR, "socket call failed: %s", strerror(errno)); + return -1; + } + memset(&addr_serv, 0, sizeof(addr_serv)); + addr_serv.sin_family = AF_INET; + addr_serv.sin_port = htons(SERVER_PORT); + addr_serv.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + sendto(fd, stop_msg, strlen(stop_msg), 0, + (struct sockaddr *)&addr_serv, sizeof(addr_serv)); + closesocket(fd); + return 0; +} + +void dhcp_server_start(const struct dhcp_server_info *arg) +{ + if (OS_ThreadIsValid(&g_dhcpd_thread)) { + return; + } + + if (OS_ThreadCreate(&g_dhcpd_thread, + "", + udhcpd_start, + (void *) arg, + OS_THREAD_PRIO_APP, + DHCPD_THREAD_STACK_SIZE) != OS_OK) { + DEBUG(LOG_ERR, "create main task failed\n"); + } +} + +void dhcp_server_stop(void) +{ + if (!OS_ThreadIsValid(&g_dhcpd_thread)) { + return; + } + + if (udhcpd_stop() != 0) { + DEBUG(LOG_ERR, "stop dhcp server failed\n"); + return; + } + + while (OS_ThreadIsValid(&g_dhcpd_thread)) { + OS_MSleep(1); /* wait for thread termination */ + } + DEBUG(LOG_INFO, "stop dhcp server success\n"); +} diff --git a/platform/mcu/xr871/src/net/wlan/airkiss/airkiss.h b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss.h new file mode 100644 index 0000000000..11f42722e2 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss.h @@ -0,0 +1,236 @@ +/* + * airkiss.h + * + * Created on: 2015-1-26 + * Author: peterfan + */ + +#ifndef AIRKISS_H_ +#define AIRKISS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AIRKISS_ENABLE_CRYPTΪ1AirKissܹ + */ +#ifndef AIRKISS_ENABLE_CRYPT +#define AIRKISS_ENABLE_CRYPT 1 +#endif + + +typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num); +typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num); +typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num); +typedef int (*airkiss_printf_fn) (const char* format, ...); + + +/* + * AirKissãĿǰһЩص + */ +typedef struct +{ + /* + * Ϊٿļc׼⺯Ҫϲʹṩ + * printfΪNULL + */ + airkiss_memset_fn memset; + airkiss_memcpy_fn memcpy; + airkiss_memcmp_fn memcmp; + airkiss_printf_fn printf; + +} airkiss_config_t; + + + +/* + * AirKiss APIҪĽṹ壬Ϊȫֱͨmalloc̬ + */ +typedef struct +{ + int dummyap[26]; + int dummy[32]; +} airkiss_context_t; + + + +/* + * AirKissɹĽ + */ +typedef struct +{ + char* pwd; /* wifi룬'\0'β */ + char* ssid; /* wifi ssid'\0'β */ + unsigned char pwd_length; /* wifi볤 */ + unsigned char ssid_length; /* wifi ssid */ + unsigned char random; /* ֵAirKissЭ飬wifiӳɹҪͨudp10000˿ڹ㲥ֵAirKissͶˣ΢ſͻ˻AirKissDebugger֪AirKissóɹ */ + unsigned char reserved; /* ֵ */ +} airkiss_result_t; + + + +/* + * airkiss_recv()µķֵ + */ +typedef enum +{ + /* ⴦airkiss_recv()ֱɹ */ + AIRKISS_STATUS_CONTINUE = 0, + + /* wifiŵѾϲӦֹͣлŵ */ + AIRKISS_STATUS_CHANNEL_LOCKED = 1, + + /* ɹԵairkiss_get_result()ȡý */ + AIRKISS_STATUS_COMPLETE = 2 + +} airkiss_status_t; + + + +#if AIRKISS_ENABLE_CRYPT + +/* + * ýkeyΪ128bitkey128bitĬ0 + * + * ֵ + * < 0ͨDz + * 0ɹ + */ +int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length); + +#endif + + + +/* + * ȡAirKiss汾Ϣ + */ +const char* airkiss_version(void); + + + +/* + * ʼAirKiss⣬ҪcontextԶε + * + * ֵ + * < 0ͨDz + * 0ɹ + */ +int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config); + + + +/* + * WiFi Promiscuous Mode󣬽յİairkiss_recvԽн + * + * ˵ + * frame802.11 frame mac header(must contain at least first 24 bytes) + * lengthtotal frame length + * + * ֵ + * < 0ͨDz + * >= 0ɹοairkiss_status_t + */ +int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length); + + + +/* + * airkiss_recv()AIRKISS_STATUS_COMPLETE󣬵ô˺ȡAirKiss + * + * ֵ + * < 0״̬AIRKISS_STATUS_COMPLETE + * 0ɹ + */ +int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result); + + +/* + * ϲлŵԺ󣬿Եһ±ӿ建棬ŵĸʣעõ߼airkiss_init֮ + * + * ֵ + * < 0ͨDz + * 0ɹ + */ +int airkiss_change_channel(airkiss_context_t* context); + +/* + * + * ʵAPI΢API + * + */ + +/* + * airkiss_lan_recv()ķֵ + */ +typedef enum +{ + /* ṩݻȲ */ + AIRKISS_LAN_ERR_OVERFLOW = -5, + + /* ǰ汾ֵָ֧ */ + AIRKISS_LAN_ERR_CMD = -4, + + /* ݳ */ + AIRKISS_LAN_ERR_PAKE = -3, + + /* ݲ */ + AIRKISS_LAN_ERR_PARA = -2, + + /* ݴ */ + AIRKISS_LAN_ERR_PKG = -1, + + /* ĸʽȷDzҪ豸ݰ */ + AIRKISS_LAN_CONTINUE = 0, + + /* յ豸ݰ */ + AIRKISS_LAN_SSDP_REQ = 1, + + /* ݰ */ + AIRKISS_LAN_PAKE_READY = 2 + + +} airkiss_lan_ret_t; + + +typedef enum +{ + AIRKISS_LAN_SSDP_REQ_CMD = 0x1, + AIRKISS_LAN_SSDP_RESP_CMD = 0x1001, + AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002 +} airkiss_lan_cmdid_t; + +/* + * 豸ģʽ󣬽յİairkiss_lan_recvԽн + * + * ˵ + * body802.11 frame mac header(must contain at least first 24 bytes) + * lengthtotal frame length + * configAirKissص + * + * ֵ + * < 0οairkiss_lan_ret_tͨDZݳ + * >= 0ɹοairkiss_lan_ret_t + */ +int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config); + +/* + * 豸ҪЭʱñӿݰ + * + * ˵ + * body802.11 frame mac header(must contain at least first 24 bytes) + * lengthtotal frame length + * configAirKissص + * + * ֵ + * < 0οairkiss_lan_ret_tͨDZݳ + * >= 0ɹοairkiss_lan_ret_t + */ +int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config); + +#ifdef __cplusplus +} +#endif + +#endif /* AIRKISS_H_ */ diff --git a/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_ack.c b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_ack.c new file mode 100644 index 0000000000..564c340029 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_ack.c @@ -0,0 +1,151 @@ +#include + +#include "kernel/os/os.h" +#include "lwip/sockets.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +#include "airkiss.h" + +enum loglevel{ + OFF = 0, + ERROR = 1, + INFO = 2, +}; + +#define g_debuglevel ERROR + +#define AIRKISS_ACK_DBG(level, fmt, args...) do { \ + if (level <= g_debuglevel) \ + printf("[airkiss ack]"fmt,##args); \ + } while (0) + + +static struct netif *wlan_netif; + +#define MAX_TIME 4294967295 +#define AIRKISS_ACK_UDP_PORT 10000 + +static const airkiss_config_t ak_config = { + (airkiss_memset_fn)&memset, + (airkiss_memcpy_fn)&memcpy, + (airkiss_memcmp_fn)&memcmp, + (airkiss_printf_fn)&printf + }; + +static uint32_t airkiss_d_time(uint32_t start_time, uint32_t os_time) +{ + uint32_t d_time = 0; + if (start_time <= os_time) + d_time = os_time - start_time; + else + d_time = MAX_TIME - start_time + os_time; + return d_time; +} + +static int airkiss_ack_successful(uint32_t random_num) +{ + uint8_t num[1]; + num[0] = (uint8_t)random_num; + + struct netif *nif = wlan_netif; + + if (nif == NULL) + return 0; + if (netif_is_up(nif) && netif_is_link_up(nif)) { + AIRKISS_ACK_DBG(INFO, "airkiss ack start\n"); + + int ak_ack_socket_id = lwip_socket(AF_INET, SOCK_DGRAM, 0); + if (ak_ack_socket_id < 0) { + AIRKISS_ACK_DBG(ERROR, "%s(), %d, create socket fail\n", __func__, __LINE__); + return 0; + } + + struct sockaddr_in addr; + memset(&addr, 0, sizeof(addr)); + + addr.sin_port = htons(AIRKISS_ACK_UDP_PORT); + addr.sin_family = AF_INET; + if (inet_aton("255.255.255.255", &addr.sin_addr) < 0) { + AIRKISS_ACK_DBG(ERROR, "%s(), %d, inet_aton error\n", __func__, __LINE__); + return 0; + } + + int tmp = 1; + int ret = setsockopt(ak_ack_socket_id, SOL_SOCKET, SO_BROADCAST, &tmp, sizeof(int)); + if (ret != 0) { + AIRKISS_ACK_DBG(ERROR, "%s(), %d, setsockopt error\n", __func__, __LINE__); + lwip_close(ak_ack_socket_id); + return 0; + } + + int i = 0; + for (i = 0; i < 300; i ++) { + int ret = lwip_sendto(ak_ack_socket_id, num, + 1, 0,(struct sockaddr *)&addr, sizeof(addr)); + if (ret == -1) { + AIRKISS_ACK_DBG(ERROR, "%s(), %d, udp send error, %d\n", __func__, __LINE__, OS_GetErrno()); + lwip_close(ak_ack_socket_id); + return 0; + } + OS_MSleep(1); + } + + lwip_close(ak_ack_socket_id); + return 1; + } + return 0; +} + +static uint8_t airkiss_ack_run = 0; + +static int airkiss_ack(uint32_t random_num, uint32_t time_out_ms) +{ + uint32_t start_time = OS_JiffiesToMSecs(OS_GetJiffies()); + uint32_t os_time = 0; + + while (airkiss_ack_run) { + if (airkiss_ack_successful(random_num)) + break; + + os_time = OS_JiffiesToMSecs(OS_GetJiffies()); + uint32_t d_time = airkiss_d_time(start_time, os_time); + if (d_time >= time_out_ms) + return -1; + + OS_MSleep(100); + } + + AIRKISS_ACK_DBG(INFO, "airkiss ack end\n"); + + return 0; +} + +static int airkiss_ack_start(struct netif *nif, uint32_t random_num, uint32_t timeout_ms) +{ + AIRKISS_ACK_DBG(INFO, "ack start\n"); + + if (nif == NULL) + return -1; + + wlan_netif = nif; + airkiss_ack_run = 1; + + return airkiss_ack(random_num, timeout_ms); +} + +static void airkiss_ack_stop(void) +{ + airkiss_ack_run = 0; +} + +int wlan_airkiss_ack_start(struct netif *nif, uint32_t random_num, uint32_t timeout_ms) +{ + return airkiss_ack_start(nif, random_num, timeout_ms); +} + +int wlan_airkiss_ack_stop(void) +{ + airkiss_ack_stop(); + return 0; +} diff --git a/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_discover.c b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_discover.c new file mode 100644 index 0000000000..0e49f24044 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_discover.c @@ -0,0 +1,314 @@ +#include "string.h" + +#include "kernel/os/os.h" +#include "lwip/sockets.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +#include "airkiss.h" + +enum loglevel{ + OFF = 0, + ERROR = 1, + INFO = 2, +}; + +#define g_debuglevel ERROR + +#define AIRKISS_DISCOVER_DBG(level, fmt, args...) do { \ + if (level <= g_debuglevel) \ + printf("[airkiss ack]"fmt,##args); \ + } while (0) + +typedef struct { + char *app_id; + char *device_id; + uint32_t ack_period_ms; +} Airkiss_Online_Ack_Info; + +const airkiss_config_t akconf ={ + (airkiss_memset_fn)&memset, + (airkiss_memcpy_fn)&memcpy, + (airkiss_memcmp_fn)&memcmp, + (airkiss_printf_fn)&printf +}; + +#define AIRKISS_LAN_PORT 12476 +static Airkiss_Online_Ack_Info ack_info; + +/************************************************************************************************************/ +/** + * allwin + */ +static void airkiss_device_online_ack(Airkiss_Online_Ack_Info *info, int socket_id) +{ + AIRKISS_DISCOVER_DBG(INFO, "into airkiss_device_online_ack\n"); + + uint8_t ak_online_ack_buf[200]; + uint16_t ak_online_buf_len = 200; + int ret = airkiss_lan_pack(AIRKISS_LAN_SSDP_NOTIFY_CMD, + //wechat_public_id, device_id, + info->app_id, info->device_id, + 0, 0, + ak_online_ack_buf, &ak_online_buf_len, + &akconf); + + if (ret == AIRKISS_LAN_PAKE_READY) { + struct sockaddr_in addr; + memset(&addr, 0, sizeof(addr)); + + addr.sin_port = htons(AIRKISS_LAN_PORT); + addr.sin_family = AF_INET; + if (inet_aton("255.255.255.255", &addr.sin_addr) < 0) { + AIRKISS_DISCOVER_DBG(ERROR, "%s(), %d, inet_aton error\n", __func__, __LINE__); + return; + } + + int tmp = 1; + int ret = setsockopt(socket_id, SOL_SOCKET, SO_BROADCAST, &tmp, sizeof(int)); + if (ret != 0) { + AIRKISS_DISCOVER_DBG(ERROR, "%s(), %d, setsockopt error\n", __func__, __LINE__); + return; + } + ret = lwip_sendto(socket_id, ak_online_ack_buf, ak_online_buf_len, + 0,(const struct sockaddr *)&addr, sizeof(addr)); + if (ret == -1) + AIRKISS_DISCOVER_DBG(ERROR, "%s(), %d, udp send error\n", __func__, __LINE__); + } +} + +static OS_Thread_t g_airkiss_cycle_ack_thread; +#define AIRKISS_CYCLE_ACK_THREAD_STACK_SIZE 1024 * 1 +static uint8_t airkiss_cycle_ack_run = 0; + +static void airkiss_cycle_ack_task(void* param) +{ + Airkiss_Online_Ack_Info *info = (Airkiss_Online_Ack_Info *) param; + int socket_id; + struct sockaddr_in addr; + + socket_id = socket(AF_INET ,SOCK_DGRAM, 0); + if (socket_id < 0) { + AIRKISS_DISCOVER_DBG(ERROR,"create sock error! %s, %d\n", __func__, __LINE__); + return; + } + + memset(&addr, 0, sizeof(addr)); + addr.sin_family=AF_INET; + addr.sin_port= htons(AIRKISS_LAN_PORT); + addr.sin_addr.s_addr=htonl(INADDR_ANY) ; + + if (bind(socket_id, (struct sockaddr*)&addr, sizeof(addr))<0) { + AIRKISS_DISCOVER_DBG(ERROR,"bind sock error! %s, %d\n", __func__, __LINE__); + return; + } + + while(airkiss_cycle_ack_run){ + airkiss_device_online_ack(info, socket_id); + OS_MSleep(info->ack_period_ms); + } + /*since lan discovery should be send always,so we will never reach this*/ + OS_ThreadDelete(&g_airkiss_cycle_ack_thread); +} + +static int airkiss_online_cycle_ack_start(Airkiss_Online_Ack_Info *param) +{ + ack_info = *param; + airkiss_cycle_ack_run = 1; + + if (OS_ThreadCreate(&g_airkiss_cycle_ack_thread, + "", + airkiss_cycle_ack_task, + (void *)&ack_info, + OS_THREAD_PRIO_APP, + AIRKISS_CYCLE_ACK_THREAD_STACK_SIZE) != OS_OK) { + AIRKISS_DISCOVER_DBG(ERROR, "%s(), %d create airkiss ask thread failed\n", __func__, __LINE__); + return -1; + } + + return 0; +} + +static void airkiss_online_cycle_ack_stop(void) +{ + airkiss_cycle_ack_run = 0; + while (OS_ThreadIsValid (&g_airkiss_cycle_ack_thread)) + OS_MSleep(100); +} + +static int airkiss_send_active_lan_discovery_packets(int client_socket_fd, Airkiss_Online_Ack_Info *info) +{ + int ret = -1; + struct sockaddr_in to_addr; + uint8_t lan_buf[200]; + uint16_t lan_buf_len = sizeof(lan_buf); + + ret = airkiss_lan_pack(AIRKISS_LAN_SSDP_NOTIFY_CMD, info->app_id, info->device_id, 0, 0, lan_buf, &lan_buf_len, &akconf); + if (ret != AIRKISS_LAN_PAKE_READY) { + AIRKISS_DISCOVER_DBG(ERROR, "airkiss pack lan packet error!\n"); + return -1; + } + + + FD_ZERO(&to_addr); + to_addr.sin_family = AF_INET; + to_addr.sin_port = htons(AIRKISS_LAN_PORT); + to_addr.sin_addr.s_addr =inet_addr("255.255.255.255"); + + int tmp = 1; + ret = setsockopt(client_socket_fd, SOL_SOCKET, SO_BROADCAST, &tmp, sizeof(int)); + if (ret != 0) { + AIRKISS_DISCOVER_DBG(ERROR, "%s(), %d, setsockopt error\n", __func__, __LINE__); + return -1; + } + + ret = sendto(client_socket_fd, (unsigned char *)lan_buf, lan_buf_len, 0, (struct sockaddr *) &to_addr, sizeof(struct sockaddr)); + if(ret == -1){ + AIRKISS_DISCOVER_DBG(ERROR, "UDP send error %s, %d\n", __func__, __LINE__); + return -1; + } + + return 0; +} + +static void airkiss_lan_server_reply(int client_socket_fd, struct sockaddr_in addr, Airkiss_Online_Ack_Info *info, + char *pdata, unsigned short len) +{ + airkiss_lan_ret_t ret = -1; + airkiss_lan_ret_t pack_ret; + uint8_t lan_buf[200]; + uint16_t lan_buf_len = sizeof(lan_buf); + + ret = airkiss_lan_recv(pdata, len, &akconf); + + switch (ret){ + case AIRKISS_LAN_SSDP_REQ: + addr.sin_port = htons(AIRKISS_LAN_PORT); + lan_buf_len = sizeof(lan_buf); + pack_ret = airkiss_lan_pack(AIRKISS_LAN_SSDP_RESP_CMD, info->app_id, info->device_id, 0, 0, lan_buf, &lan_buf_len, &akconf); + if (pack_ret != AIRKISS_LAN_PAKE_READY) { + AIRKISS_DISCOVER_DBG(ERROR, "Pack lan packet error! %s, %d\n", __func__, __LINE__); + return; + } + + AIRKISS_DISCOVER_DBG(ERROR, "AIRKISS_LAN_SSDP_REQ !\n"); + ret = sendto(client_socket_fd, (unsigned char *)lan_buf, lan_buf_len, 0, (struct sockaddr *) &addr, sizeof(struct sockaddr)); + if(ret != 0){ + AIRKISS_DISCOVER_DBG(ERROR, "lan_server_reply sendto ret=%d\n", ret); + } + break; + default: + AIRKISS_DISCOVER_DBG(ERROR,"Pack is not ssdq req!\n"); + break; + } +} + +static OS_Thread_t g_airkiss_online_dialog_thread; +#define AIRKISS_ONLINE_DIALOG_THREAD_STACK_SIZE 1024 * 1 +static uint8_t airkiss_dialog_run = 0; + +static void airkiss_online_dialog_task(void *arg) +{ + Airkiss_Online_Ack_Info *info = (Airkiss_Online_Ack_Info *)arg; + int server_sock_fd,len; + struct sockaddr_in addr; + int sock_timeout_val = 1000; /* 1000 ms */ + int addr_len = sizeof(struct sockaddr_in); + char buffer[256] = {0}; + + if((server_sock_fd = socket(AF_INET,SOCK_DGRAM,0)) < 0){ + AIRKISS_DISCOVER_DBG(ERROR, "create sock error!\n"); + airkiss_dialog_run = 0; + return; + } + + memset(&addr, 0, sizeof(addr)); + addr.sin_family=AF_INET; + addr.sin_port = htons(AIRKISS_LAN_PORT); + addr.sin_addr.s_addr=htonl(INADDR_ANY) ; + + if (bind(server_sock_fd, (struct sockaddr *)&addr, sizeof(addr))<0) { + AIRKISS_DISCOVER_DBG(ERROR, "bind sock error!\n"); + airkiss_dialog_run = 0; + return; + } + + int ret = setsockopt(server_sock_fd, SOL_SOCKET, SO_RCVTIMEO, &sock_timeout_val, sizeof(sock_timeout_val)); + if (ret != 0) { + AIRKISS_DISCOVER_DBG(ERROR, "%s(), %d, setsockopt error\n", __func__, __LINE__); + } + + memset(&buffer, 0, sizeof(buffer)); + len = recvfrom(server_sock_fd, buffer, sizeof(buffer), 0 , (struct sockaddr *)&addr , (socklen_t *)&addr_len); + + if (len != -1) { + airkiss_lan_server_reply(server_sock_fd, addr, info, buffer, len); + } + + while (airkiss_dialog_run) { + if (airkiss_send_active_lan_discovery_packets(server_sock_fd, info) == -1) + break; + OS_MSleep(info->ack_period_ms); + } + + OS_ThreadDelete(&g_airkiss_online_dialog_thread); +} + +static int airkiss_online_dialog_mode_start(Airkiss_Online_Ack_Info *param) +{ + ack_info = *param; + if (airkiss_dialog_run) { + AIRKISS_DISCOVER_DBG(ERROR, "airkiss online already start %s(), %d \n", __func__, __LINE__); + return -1; + } + airkiss_dialog_run = 1; + + if (OS_ThreadCreate(&g_airkiss_online_dialog_thread, + "", + airkiss_online_dialog_task, + (void *)&ack_info, + OS_THREAD_PRIO_APP, + AIRKISS_ONLINE_DIALOG_THREAD_STACK_SIZE) != OS_OK) { + AIRKISS_DISCOVER_DBG(ERROR, "create airkiss ask thread failed %s(), %d \n", __func__, __LINE__); + return -1; + } + + return 0; +} + +static void airkiss_online_dialog_mode_stop(void) +{ + airkiss_dialog_run = 0; + while (OS_ThreadIsValid (&g_airkiss_cycle_ack_thread)) + OS_MSleep(100); +} + +int wlan_airkiss_online_cycle_ack_start(char *app_id, char *drv_id, uint32_t period_ms) +{ + Airkiss_Online_Ack_Info param; + param.app_id = app_id; + param.device_id = drv_id; + param.ack_period_ms = period_ms; + return airkiss_online_cycle_ack_start(¶m); +} + +int wlan_airkiss_online_cycle_ack_stop(void) +{ + airkiss_online_cycle_ack_stop(); + return 0; +} + +int wlan_airkiss_online_dialog_mode_start(char *app_id, char *drv_id, uint32_t period_ms) +{ + Airkiss_Online_Ack_Info param; + param.app_id = app_id; + param.device_id = drv_id; + param.ack_period_ms = period_ms; + return airkiss_online_dialog_mode_start(¶m); +} + +int wlan_airkiss_online_dialog_mode_stop(void) +{ + airkiss_online_dialog_mode_stop(); + return 0; +} diff --git a/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_main.c b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_main.c new file mode 100644 index 0000000000..f0727aa530 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/airkiss/airkiss_main.c @@ -0,0 +1,261 @@ +#include "stdio.h" +#include "stdlib.h" +#include "errno.h" +#include "string.h" +#include "sys/mbuf.h" +#include "kernel/os/os.h" +#include "net/wlan/wlan.h" + +#include "net/wlan/wlan_airkiss.h" +#include "airkiss.h" + +enum loglevel{ + OFF = 0, + ERROR = 1, + INFO = 2, +}; + +#define g_debuglevel INFO + +#define AIRKISS_DBG(level, fmt, args...) do { \ + if (level <= g_debuglevel) \ + printf("[airkiss]"fmt,##args); \ + } while (0) + +enum { + AK_END = 0, + AK_SEARCH_CHAN, + AK_LOCKED_CHAN, +}; + +static uint8_t ak_ctrl = 0; +static airkiss_context_t ak_context; +static airkiss_result_t priv_ak_result; +static airkiss_status_t ak_sta = AIRKISS_STATUS_CONTINUE; +static const airkiss_config_t config = { + (airkiss_memset_fn)&memset, + (airkiss_memcpy_fn)&memcpy, + (airkiss_memcmp_fn)&memcmp, + (airkiss_printf_fn)&printf + }; + +#define AK_KEY_LEN 16 +#define CHTABLESIZE 13 +#define MAX_TIME 4294967295 + +static char ak_key[AK_KEY_LEN]; +static struct netif *priv_nif = NULL; + +static uint32_t d_time(uint32_t time1, uint32_t time2) +{ + uint32_t d_time = 0; + if (time1 <= time2) + d_time = time2 - time1; + else + d_time = MAX_TIME - time1 + time2; + return d_time; +} + +static void airkiss_macframe(uint8_t *data, uint32_t len, void *info) +{ + ak_sta = airkiss_recv(&ak_context, data, len); + + if (ak_sta == AIRKISS_STATUS_COMPLETE || ak_ctrl == AK_END) { + wlan_monitor_set_rx_cb(priv_nif, NULL); + AIRKISS_DBG(INFO, "%s(), %d, airkiss complete\n", __func__, __LINE__); + + if (ak_ctrl) { + airkiss_get_result(&ak_context, &priv_ak_result); + AIRKISS_DBG(INFO, "ssid %s\n", priv_ak_result.ssid); + AIRKISS_DBG(INFO, "pwd %s\n", priv_ak_result.pwd); + AIRKISS_DBG(INFO, "random %d\n", priv_ak_result.random); + AIRKISS_DBG(INFO, "%s, %d airkiss end !!!!! \n", __func__, __LINE__); + } else + AIRKISS_DBG(ERROR, "%s, %d airkiss get result error\n", __func__, __LINE__); + + ak_ctrl = AK_END; + } else if (ak_sta == AIRKISS_STATUS_CHANNEL_LOCKED) { + AIRKISS_DBG(INFO, "airkiss channel locked\n"); + ak_ctrl = AK_LOCKED_CHAN; + } else if (ak_sta < 0) + AIRKISS_DBG(ERROR, "%s, %d airkiss recv error %d\n", __func__, __LINE__, ak_sta); +} + +static int airkiss_wifi_set_channel(struct netif *nif, int16_t ch) +{ + int ret = wlan_monitor_set_channel(nif, ch); + if (ret == -1) + AIRKISS_DBG(ERROR, "%s, %d airkiss set channel error\n", __func__, __LINE__); + + return ret; +} + +static void airkiss_config(void) +{ + int ret = -1; + AIRKISS_DBG(INFO, "%s\n", airkiss_version()); + + ret = airkiss_init(&ak_context, &config); + if (ret != 0) + AIRKISS_DBG(ERROR, "%s, %d, airkiss init error\n", __func__, __LINE__); + if(ak_key[0] != 0) { + ret = airkiss_set_key(&ak_context, (const unsigned char *)ak_key, AK_KEY_LEN); + if (ret != 0) + AIRKISS_DBG(ERROR, "%s, %d, airkiss set key error\n", __func__, __LINE__); + } +} + +static void airkiss_reset(void) +{ + /* release resource of airkiss */ + airkiss_change_channel(&ak_context); + priv_ak_result.ssid = NULL; + priv_ak_result.pwd = NULL; +} + +static void airkiss_search(int16_t * ch_buff) +{ + int i = 0; + + while (1) { + if (ak_ctrl == AK_SEARCH_CHAN) { + if (ak_sta == AIRKISS_STATUS_CONTINUE) { + airkiss_wifi_set_channel(priv_nif, ch_buff[i++]); + airkiss_reset(); + } + + if (i >= CHTABLESIZE) + i = 0; + } else if (ak_ctrl == AK_LOCKED_CHAN) + break; + else if (ak_ctrl == AK_END) + break; + + OS_MSleep(100); + } +} + +static int airkiss_read_result(wlan_airkiss_result_t *result) +{ + if (priv_ak_result.ssid != NULL) { + if (priv_ak_result.ssid_length > WLAN_SSID_MAX_LEN) { + AIRKISS_DBG(ERROR, "Invalid ssid len %d\n", priv_ak_result.ssid_length); + return -1; + } + + if (priv_ak_result.pwd_length > WLAN_PASSPHRASE_MAX_LEN) { + AIRKISS_DBG(ERROR, "Invalid passphrase len %d\n", priv_ak_result.pwd_length); + return -1; + } + + memcpy(result->ssid, priv_ak_result.ssid, priv_ak_result.ssid_length); + result->ssid_len = priv_ak_result.ssid_length; + + if (priv_ak_result.pwd_length > 0 && priv_ak_result.pwd != NULL) { + memcpy(result->passphrase, priv_ak_result.pwd, priv_ak_result.pwd_length); + result->passphrase[priv_ak_result.pwd_length] = '\0'; + } else { + result->passphrase[0] = '\0'; + } + + result->random_num = priv_ak_result.random; + return 0; + } + + return -1; +} + +static int airkiss_set_aeskey(const char *key, uint32_t length) +{ + if (length != AK_KEY_LEN) + return -1; + + memcpy(ak_key, key, AK_KEY_LEN); + + return 0; +} + +static void airkiss_close(void) +{ + ak_ctrl = AK_END; + + if (wlan_monitor_set_rx_cb(priv_nif, NULL) != 0) { + AIRKISS_DBG(ERROR, "%s(),%d monitor set rx cb error\n", __func__, __LINE__); + } + + airkiss_reset(); +} + +static wlan_airkiss_status_t airkiss_start(struct netif *nif, + uint32_t timeout_ms, + wlan_airkiss_result_t *result) +{ + int ret = -1; + wlan_airkiss_status_t status = WLAN_AIRKISS_FAIL; + int16_t ak_ch_buffer[CHTABLESIZE] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}; + + AIRKISS_DBG(INFO, "start\n"); + + if (nif == NULL || result == NULL) { + AIRKISS_DBG(ERROR, "%s(),%d, nif %p, result %p\n", __func__, __LINE__, nif, result); + return WLAN_AIRKISS_INVALID; + } + + priv_nif = nif; + airkiss_config(); + + AIRKISS_DBG(INFO, "monitor_register\n"); + + ret = wlan_monitor_set_rx_cb(priv_nif, airkiss_macframe); + if (ret != 0) { + AIRKISS_DBG(ERROR, "%s(),%d monitor set rx cb fail\n", __func__, __LINE__); + goto out; + } + + uint32_t start_time = OS_JiffiesToMSecs(OS_GetJiffies()); + + ak_ctrl = AK_SEARCH_CHAN; + airkiss_search(ak_ch_buffer); + + while (ak_ctrl) { + uint32_t d_t = d_time(start_time, OS_JiffiesToMSecs(OS_GetJiffies())); + if (d_t >= timeout_ms) { + airkiss_close(); + status = WLAN_AIRKISS_TIMEOUT; + goto out; + } + + OS_MSleep(100); + } + + ret = airkiss_read_result(result); + if (ret == 0) { + status = WLAN_AIRKISS_SUCCESS; + } + +out: + airkiss_reset(); + return status; +} + +int wlan_airkiss_set_key(const char *key, uint32_t len) +{ + if (key == NULL || len != WLAN_AIRKISS_KEY_LEN) { + AIRKISS_DBG(ERROR, "invalid airkiss key (%p, %d)\n", key, len); + return -1; + } + + return airkiss_set_aeskey(key, len); +} + +wlan_airkiss_status_t wlan_airkiss_start(struct netif *nif, uint32_t timeout_ms, + wlan_airkiss_result_t *result) +{ + return airkiss_start(nif, timeout_ms, result); +} + +int wlan_airkiss_stop(void) +{ + airkiss_close(); + return 0; +} diff --git a/platform/mcu/xr871/src/net/wlan/ethernetif.c b/platform/mcu/xr871/src/net/wlan/ethernetif.c new file mode 100644 index 0000000000..3a4f75bd42 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/ethernetif.c @@ -0,0 +1,529 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/tcpip.h" +#include "lwip/dhcp.h" +#include "lwip/etharp.h" +#include "lwip/ethip6.h" +#include "lwip/netifapi.h" +#include "net/wlan/ethernetif.h" +#include +#include "sys/mbuf.h" +#include "sys/xr_util.h" +#ifdef __CONFIG_ARCH_DUAL_CORE +#include "sys/ducc/ducc_app.h" + #else +#include "net80211/net80211_ifnet.h" +#endif + +#define ETH_DBG_ON 0 +#define ETH_WRN_ON 1 +#define ETH_ERR_ON 1 +#define ETH_ABORT_ON 1 + +#define ETH_SYSLOG printf +#define ETH_ABORT() sys_abort() + +#define ETH_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + ETH_SYSLOG(fmt, ##arg); \ + } while (0) + +#define ETH_DBG(fmt, arg...) ETH_LOG(ETH_DBG_ON, "[eth] "fmt, ##arg) +#define ETH_WRN(fmt, arg...) ETH_LOG(ETH_WRN_ON, "[eth WRN] "fmt, ##arg) +#define ETH_ERR(fmt, arg...) \ + do { \ + ETH_LOG(ETH_ERR_ON, "[eth ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (ETH_ABORT_ON) \ + ETH_ABORT(); \ + } while (0) + +#define ETHER_MTU_MAX 1500 +#define NETIF_LINK_SPEED_BPS (100 * 1000 * 1000) +#define NETIF_ATTACH_BASE_FLAGS (NETIF_FLAG_BROADCAST | \ + NETIF_FLAG_ETHARP | \ + NETIF_FLAG_ETHERNET | \ + NETIF_FLAG_IGMP) +#if LWIP_IPV6 +#define NETIF_ATTACH_FLAGS (NETIF_ATTACH_BASE_FLAGS | NETIF_FLAG_MLD6) +#else +#define NETIF_ATTACH_FLAGS (NETIF_ATTACH_BASE_FLAGS) +#endif + +struct ethernetif { + struct netif nif; + enum wlan_mode mode; +}; + +#define ethernetif2netif(eth) ((struct netif *)(eth)) +#define netif2ethernetif(nif) ((struct ethernetif *)(nif)) + +static struct ethernetif g_eth_netif; + +#if LWIP_NETIF_HOSTNAME +#define NETIF_HOSTNAME_MAX_LEN 32 +static char g_netif_hostname[NETIF_HOSTNAME_MAX_LEN]; + +void ethernetif_set_hostname(char *hostname) +{ + if (hostname != NULL) { + strlcpy(g_netif_hostname, hostname, NETIF_HOSTNAME_MAX_LEN); + } +} +#endif /* LWIP_NETIF_HOSTNAME */ + +static err_t tcpip_null_input(struct pbuf *p, struct netif *nif) +{ + ETH_WRN("%s() called\n", __func__); + pbuf_free(p); + return ERR_OK; +} + +#if LWIP_IPV4 +static err_t ethernetif_null_ip4output(struct netif *nif, struct pbuf *p, const ip4_addr_t *ip4addr) +{ + ETH_WRN("%s() called\n", __func__); + return ERR_IF; +} +#endif + +#if LWIP_IPV6 +static err_t ethernetif_null_ip6output(struct netif *nif, struct pbuf *p, const ip6_addr_t *ip6addr) +{ + ETH_WRN("%s() called\n", __func__); + return ERR_IF; +} +#endif + +static err_t ethernetif_null_linkoutput(struct netif *nif, struct pbuf *p) +{ + ETH_WRN("%s() called\n", __func__); + return ERR_IF; +} + +#ifdef __CONFIG_ARCH_DUAL_CORE + +#if (LWIP_MBUF_SUPPORT == 0) +static __inline struct mbuf *eth_pbuf2mbuf(struct pbuf *p) +{ + struct ducc_param_mbuf_get param; + struct mbuf *m; + struct pbuf *q; + uint8_t *data; + int32_t left; + + /* get a mbuf */ + param.len = p->tot_len; + param.tx = 1; + param.mbuf = NULL; + if (ducc_app_ioctl(DUCC_APP_CMD_MBUF_GET, ¶m) != 0) { + return NULL; + } + + /* copy all data to mbuf */ + m = param.mbuf; + data = mtod(m, uint8_t *); + left = m->m_len; + for (q = p; q != NULL; q = q->next) { + if (left >= q->len) { + memcpy(data, q->payload, q->len); + data += q->len; + left -= q->len; + } else { + break; + } + } + if (left != 0) { + ETH_ERR("left %d, total %u\n", left, p->tot_len); + ducc_app_ioctl(DUCC_APP_CMD_MBUF_FREE, m); + return NULL; + } + return m; +} +#endif /* (LWIP_MBUF_SUPPORT == 0) */ + +/* NB: @p is freed by Lwip. */ +static err_t ethernetif_linkoutput(struct netif *nif, struct pbuf *p) +{ + struct ducc_param_wlan_linkoutput param; + struct mbuf *m; + int ret; + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + +#if (LWIP_MBUF_SUPPORT == 0) + m = eth_pbuf2mbuf(p); +#elif (LWIP_MBUF_SUPPORT == 1) + m = mb_pbuf2mbuf(p); +#endif /* LWIP_MBUF_SUPPORT */ + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + if (m == NULL) { + ETH_DBG("pbuf2mbuf() failed\n"); + LINK_STATS_INC(link.memerr); + MIB2_STATS_NETIF_INC(nif, ifoutdiscards); + return ERR_MEM; + } + param.mbuf = m; + param.ifp = nif->state; + ret = ducc_app_ioctl(DUCC_APP_CMD_WLAN_LINKOUTPUT, ¶m); + if (ret != 0) { + ETH_WRN("linkoutput failed (%d)\n", ret); + LINK_STATS_INC(link.err); + MIB2_STATS_NETIF_INC(nif, ifouterrors); + } else { + LINK_STATS_INC(link.xmit); +#if MIB2_STATS + MIB2_STATS_NETIF_ADD(nif, ifoutoctets, p->tot_len); + if (((u8_t*)p->payload)[0] & 1) { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(nif, ifoutnucastpkts); + } else { + /* unicast packet */ + MIB2_STATS_NETIF_INC(nif, ifoutucastpkts); + } +#endif + } + return ERR_OK; +} + +#if LWIP_IPV4 +static err_t ethernetif_ip4output(struct netif *nif, struct pbuf *p, const ip4_addr_t *ip4addr) +{ + if (!netif_is_link_up(nif)) { + ETH_DBG("netif %p is link down\n", nif); + return ERR_IF; + } + + return etharp_output(nif, p, ip4addr); +} +#endif + +#if LWIP_IPV6 +static err_t ethernetif_ip6output(struct netif *nif, struct pbuf *p, const ip6_addr_t *ip6addr) +{ + if (!netif_is_link_up(nif)) { + ETH_DBG("netif %p is link down\n", nif); + return ERR_IF; + } + + return ethip6_output(nif, p, ip6addr); +} +#endif + +#endif /* __CONFIG_ARCH_DUAL_CORE */ + +/* NB: call by RX task to process received data */ +err_t ethernetif_input(struct netif *nif, struct pbuf *p) +{ + err_t err = ERR_MEM; + + do { + if (p == NULL) { + ETH_DBG("pbuf is NULL\n"); + LINK_STATS_INC(link.memerr); + break; + } +#if ETH_PAD_SIZE + if (pbuf_header(p, ETH_PAD_SIZE) != 0) { + /* add padding word for LwIP */ + ETH_WRN("pbuf_header(%d) failed!\n", ETH_PAD_SIZE); + LINK_STATS_INC(link.memerr); + break; + } +#endif /* ETH_PAD_SIZE */ + + /* send data to LwIP, nif->input() == tcpip_input() */ + err = nif->input(p, nif); + if (err != ERR_OK) { + ETH_WRN("lwip process data failed, err %d!\n", err); +// LINK_STATS_INC(link.err); + } else { + p = NULL; /* pbuf will be freed by LwIP */ + } + } while (0); + + if (p) { + pbuf_free(p); + } + + __asm("nop"); +#if (LINK_STATS || MIB2_STATS) + if (err == ERR_OK) { + LINK_STATS_INC(link.recv); + #if MIB2_STATS + MIB2_STATS_NETIF_ADD(nif, ifinoctets, p->tot_len); + if (((u8_t*)p->payload)[0] & 1) { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(nif, ifinnucastpkts); + } else { + /* unicast packet*/ + MIB2_STATS_NETIF_INC(nif, ifinucastpkts); + } + #endif + } else { + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(nif, ifindiscards); + } +#endif /* (LINK_STATS || MIB2_STATS) */ + return err; +} + +#if (LWIP_MBUF_SUPPORT == 0) +err_t ethernetif_raw_input(struct netif *nif, uint8_t *data, u16_t len) +{ + struct pbuf *p, *q; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + if (p != NULL) { +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + /* We iterate over the pbuf chain until we have read the entire packet into the pbuf. */ + for(q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The available data + * in the pbuf is given by the q->len variable. + * This does not necessarily have to be a memcpy, you can also preallocate + * pbufs for a DMA-enabled MAC and after receiving truncate it to the + * actually received size. In this case, ensure the tot_len member of the + * pbuf is the sum of the chained pbuf len members. + */ + memcpy(q->payload, data, q->len); + data += q->len; + } + } + return ethernetif_input(nif, p); +} +#endif /* (LWIP_MBUF_SUPPORT == 0) */ + +static err_t ethernetif_hw_init(struct netif *nif, enum wlan_mode mode) +{ +#ifdef __CONFIG_ARCH_DUAL_CORE + char name[4]; + name[0] = nif->name[0]; + name[1] = nif->name[1]; + name[2] = nif->num + '0'; + name[3] = '\0'; + + struct ducc_param_wlan_create param; + param.mode = mode; + param.nif = nif; + param.name = name; + param.ifp = NULL; + if (ducc_app_ioctl(DUCC_APP_CMD_WLAN_IF_CREATE, ¶m) != 0) { + ETH_ERR("wlan interface create failed\n"); + return ERR_IF; + } + nif->state = param.ifp; + + struct ducc_param_wlan_get_mac_addr param2; + param2.ifp = nif->state; + param2.buf = nif->hwaddr; + param2.buf_len = ETHARP_HWADDR_LEN; + + if (ducc_app_ioctl(DUCC_APP_CMD_WLAN_GET_MAC_ADDR, ¶m2) != ETHARP_HWADDR_LEN) { + ETH_ERR("get mac addr failed\n"); + ducc_app_ioctl(DUCC_APP_CMD_WLAN_IF_DELETE, nif->state); + nif->state = NULL; + return ERR_IF; + } +#else /* __CONFIG_ARCH_DUAL_CORE */ + nif->state = net80211_ifnet_create(mode, nif); + if (nif->state == NULL) { + ETH_ERR("wlan interface create failed\n"); + return ERR_IF; + } +#endif /* __CONFIG_ARCH_DUAL_CORE */ + return ERR_OK; +} + +static void ethernetif_hw_deinit(struct netif *nif) +{ +#ifdef __CONFIG_ARCH_DUAL_CORE + ducc_app_ioctl(DUCC_APP_CMD_WLAN_IF_DELETE, nif->state); +#else + net80211_ifnet_delete(nif->state); +#endif +} + +static err_t ethernetif_init(struct netif *nif, enum wlan_mode mode) +{ + if (mode == WLAN_MODE_STA || mode == WLAN_MODE_HOSTAP) { +// nif->input = tcpip_input; +#ifdef __CONFIG_ARCH_DUAL_CORE + #if LWIP_IPV4 + nif->output = ethernetif_ip4output; + #endif + #if LWIP_IPV6 + nif->output_ip6 = ethernetif_ip6output; + #endif /* LWIP_IPV6 */ + nif->linkoutput = ethernetif_linkoutput; +#else /* __CONFIG_ARCH_DUAL_CORE */ + #if LWIP_IPV4 + nif->output = etharp_output; + #endif + #if LWIP_IPV6 + nif->output_ip6 = ethip6_output; + #endif /* LWIP_IPV6 */ + nif->linkoutput = net80211_linkoutput; +#endif /* __CONFIG_ARCH_DUAL_CORE */ + } else if (mode == WLAN_MODE_MONITOR) { +// nif->input = tcpip_null_input; +#if LWIP_IPV4 + nif->output = ethernetif_null_ip4output; +#endif +#if LWIP_IPV6 + nif->output_ip6 = ethernetif_null_ip6output; +#endif /* LWIP_IPV6 */ + nif->linkoutput = ethernetif_null_linkoutput; + } else { + ETH_ERR("mode %d\n", mode); + return ERR_ARG; + } + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + nif->hostname = g_netif_hostname; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + MIB2_INIT_NETIF(nif, snmp_ifType_ethernet_csmacd, NETIF_LINK_SPEED_BPS); + + nif->name[0] = 'e'; + nif->name[1] = 'n'; + nif->mtu = ETHER_MTU_MAX; + nif->hwaddr_len = ETHARP_HWADDR_LEN; + nif->flags |= NETIF_ATTACH_FLAGS; + +#if (LWIP_IPV6 && LWIP_IPV6_MLD) + /* + * For hardware/netifs that implement MAC filtering. + * All-nodes link-local is handled by default, so we must let + * the hardware know to allow multicast packets in. + * Should set mld_mac_filter previously. + */ + if (nif->mld_mac_filter != NULL) { + ip6_addr_t ip6_allnodes_ll; + ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll); + nif->mld_mac_filter(nif, &ip6_allnodes_ll, NETIF_ADD_MAC_FILTER); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + + /* initialize the hardware */ + return ethernetif_hw_init(nif, mode); +} + +static err_t ethernetif_sta_init(struct netif *nif) +{ + return ethernetif_init(nif, WLAN_MODE_STA); +} + +static err_t ethernetif_hostap_init(struct netif *nif) +{ + return ethernetif_init(nif, WLAN_MODE_HOSTAP); +} + +static err_t ethernetif_monitor_init(struct netif *nif) +{ + return ethernetif_init(nif, WLAN_MODE_MONITOR); +} + +struct netif *ethernetif_create(enum wlan_mode mode) +{ + netif_init_fn init_fn; + netif_input_fn input_fn; + struct netif *nif; + + if (mode == WLAN_MODE_STA) { + init_fn = ethernetif_sta_init; + input_fn = tcpip_input; + } else if (mode == WLAN_MODE_HOSTAP) { + init_fn = ethernetif_hostap_init; + input_fn = tcpip_input; + } else if (mode == WLAN_MODE_MONITOR) { + init_fn = ethernetif_monitor_init; + input_fn = tcpip_null_input; + } else { + ETH_ERR("mode %d\n", mode); + return NULL; + } + + nif = ethernetif2netif(&g_eth_netif); + memset(nif, 0, sizeof(*nif)); + g_eth_netif.mode = mode; + + /* add netif */ +#if LWIP_IPV4 + netifapi_netif_add(nif, NULL, NULL, NULL, NULL, init_fn, input_fn); +#else + netifapi_netif_add(nif, NULL, init_fn, input_fn); +#endif + netifapi_netif_set_default(nif); + return nif; + +} + +void ethernetif_delete(struct netif *nif) +{ + /* remove netif from LwIP stack */ + netifapi_netif_remove(nif); + netifapi_netif_common(nif, dhcp_cleanup, NULL); + nif->flags &= ~NETIF_ATTACH_FLAGS; + ethernetif_hw_deinit(nif); +} + +enum wlan_mode ethernetif_get_mode(struct netif *nif) +{ + if (nif == ethernetif2netif(&g_eth_netif)) { + return g_eth_netif.mode; + } else { + return WLAN_MODE_INVALID; + } +} diff --git a/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_ack.c b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_ack.c new file mode 100644 index 0000000000..9cfcf272e1 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_ack.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "kernel/os/os.h" +#include "lwip/sockets.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +enum loglevel{ + OFF = 0, + ERROR = 1, + INFO = 2, +}; + +#define g_debuglevel ERROR + +#define SMART_ACK_DBG(level, fmt, args...) do { \ + if (level <= g_debuglevel) \ + printf("[sc ack]"fmt,##args); \ + } while (0) + + +static struct netif *wlan_netif; + +#define MAX_TIME 4294967295 +#define SC_ACK_UDP_PORT 10000 + +static uint32_t sc_d_time(uint32_t start_time, uint32_t os_time) +{ + uint32_t d_time = 0; + if (start_time <= os_time) + d_time = os_time - start_time; + else + d_time = MAX_TIME - start_time + os_time; + return d_time; +} + +static int sc_ack_successful(uint32_t random_num) +{ + uint8_t num[1]; + num[0] = (uint8_t)random_num; + + struct netif *nif = wlan_netif; + + if (nif == NULL) + return 0; + if (netif_is_up(nif) && netif_is_link_up(nif)) { + SMART_ACK_DBG(INFO, "airkiss ack start\n"); + + int ak_ack_socket_id = lwip_socket(AF_INET, SOCK_DGRAM, 0); + if (ak_ack_socket_id < 0) { + SMART_ACK_DBG(ERROR, "%s(), %d, create socket fail\n", __func__, __LINE__); + return 0; + } + + struct sockaddr_in addr; + memset(&addr, 0, sizeof(addr)); + + addr.sin_port = htons(SC_ACK_UDP_PORT); + addr.sin_family = AF_INET; + if (inet_aton("239.0.0.1", &addr.sin_addr) < 0) { + SMART_ACK_DBG(ERROR, "%s(), %d, inet_aton error\n", __func__, __LINE__); + return 0; + } + + int tmp = 1; + int ret = setsockopt(ak_ack_socket_id, SOL_SOCKET, SO_BROADCAST, &tmp, sizeof(int)); + if (ret != 0) { + SMART_ACK_DBG(ERROR, "%s(), %d, setsockopt error\n", __func__, __LINE__); + lwip_close(ak_ack_socket_id); + return 0; + } + + int i = 0; + for (i = 0; i < 300; i ++) { + int ret = lwip_sendto(ak_ack_socket_id, num, + 1, 0,(struct sockaddr *)&addr, sizeof(addr)); + if (ret == -1) { + SMART_ACK_DBG(ERROR, "%s(), %d, udp send error, %d\n", __func__, __LINE__, OS_GetErrno()); + lwip_close(ak_ack_socket_id); + return 0; + } + OS_MSleep(1); + } + + lwip_close(ak_ack_socket_id); + return 1; + } + return 0; +} + +static uint8_t sc_ack_run = 0; + +static int sc_ack(uint32_t random_num, uint32_t time_out_ms) +{ + uint32_t start_time = OS_JiffiesToMSecs(OS_GetJiffies()); + uint32_t os_time = 0; + + while (sc_ack_run) { + if (sc_ack_successful(random_num)) + break; + + os_time = OS_JiffiesToMSecs(OS_GetJiffies()); + uint32_t d_time = sc_d_time(start_time, os_time); + if (d_time >= time_out_ms) + return -1; + + OS_MSleep(100); + } + + SMART_ACK_DBG(INFO, "smart_config ack end\n"); + + return 0; +} + +static int smart_config_ack_start(struct netif *nif, uint32_t random_num, uint32_t timeout_ms) +{ + SMART_ACK_DBG(INFO, "%s(), %d smart_config ask start\n", __func__, __LINE__); + + if (nif == NULL) + return -1; + + wlan_netif = nif; + sc_ack_run = 1; + + return sc_ack(random_num, timeout_ms); +} + +static void smart_config_ack_stop(void) +{ + sc_ack_run = 0; +} + +int wlan_smart_config_ack_start(struct netif *nif, uint32_t random_num, uint32_t timeout_ms) +{ + return smart_config_ack_start(nif, random_num, timeout_ms); +} + +int wlan_smart_config_ack_stop(void) +{ + smart_config_ack_stop(); + return 0; +} diff --git a/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_crc.c b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_crc.c new file mode 100644 index 0000000000..f50c8e7e2f --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_crc.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "smart_config_crc.h" +#include "driver/chip/hal_crypto.h" + +#define CRC8_INIT 0x0 +#define CRC8_POLY 0x31 + +unsigned char cal_crc8(const unsigned char *in, int num) +{ + unsigned char crc = CRC8_INIT; + int i, j; + + for (i = 0; i < num; i++ ){ + crc ^= in[i]; + for(j = 0; j < 8; j++){ + if (crc & 0x1) + crc = (crc >> 1) ^ CRC8_POLY; + else + crc = crc >> 1; + } + + } + + return crc; +} + +static int aes_decrypt(char *aes_key, char *enc_data, uint32_t enc_data_len, char *dec_buf) +{ + HAL_Status status = HAL_ERROR; + CE_AES_Config aes_cfg; + memset(&aes_cfg, 0, sizeof(aes_cfg)); + + sprintf((char*)aes_cfg.key, aes_key); + aes_cfg.keysize = CE_CTL_AES_KEYSIZE_128BITS; + aes_cfg.mode = CE_CRYPT_MODE_ECB; //CBC; + aes_cfg.src = CE_CTL_KEYSOURCE_INPUT; + + //HAL_CE_Init(); + + status = HAL_AES_Decrypt(&aes_cfg, (uint8_t*)enc_data, (uint8_t*)dec_buf, enc_data_len); + if (status != HAL_OK) { + printf("AES decrypt error %d\n", status); + return -1; + } + + return 0; +} + +static int aes_128_decrypt_block(char *key, char *in, int in_len, char *out) +{ + if (aes_decrypt(key, in, in_len, out) != 0) { + printf("ce decrypt error\n"); + return -1; + } + + return 0; +} + +int aes_ebc_decrypt(char *in, char* out, int in_len, char *key) +{ + int ret = -1; + + ret = aes_128_decrypt_block(key, in, in_len, out); + + return ret; +} diff --git a/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_crc.h b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_crc.h new file mode 100644 index 0000000000..14e8996a4a --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_crc.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SC_CRC_H__ +#define __SC_CRC_H__ + +typedef unsigned char uint8_t; + +#include + +unsigned char cal_crc8(const unsigned char* in, int num); +//return 0 on success, len should be times of AES_BLOCK_SIZE, caller handles de-padding +int aes_ebc_decrypt(char *in, char* out, int in_len, char *key); + +#endif diff --git a/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_decode.c b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_decode.c new file mode 100644 index 0000000000..62f2203e4d --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_decode.c @@ -0,0 +1,370 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "types.h" + +#include "smart_config_crc.h" +#include "smart_config_decode.h" + +enum loglevel{ + OFF = 0, + ERROR = 1, + INFO = 2, +}; + +#define g_debuglevel ERROR + +#define SC_DECODE_DBG(level, fmt, args...) \ + do { \ + if (level <= g_debuglevel) \ + printf("[smart config]"fmt,##args); \ + } while (0) + +#define __SC_BUG() \ + do { printf("BUG at %s:%d!\n", __func__, __LINE__); while (1);} while (0) + +#define SC_BUG_ON(condition) do { if (condition) __SC_BUG(); } while(0) + +#define LOCDED_FIELD 4 + +enum LEADCODE_SEQ { + LEAD_CODE_NOME, + LEAD_CODE_GET_CHANNEL, + LEAD_CODE_GET_SSIDPWD_SIZE, + LEAD_CODE_GET_PWD_SIZE, + LEAD_CODE_GET_ROUND_NUM, + LEAD_CODE_COMPLETE, +}; + +#define IEEE80211_ADDR_LEN 6 + +struct ieee80211_frame { + uint8_t i_fc[2]; + uint8_t i_dur[2]; + uint8_t i_addr1[IEEE80211_ADDR_LEN]; + uint8_t i_addr2[IEEE80211_ADDR_LEN]; + uint8_t i_addr3[IEEE80211_ADDR_LEN]; + uint8_t i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} __packed; + +extern void print_hex_dump_bytes(const char *prefix_str, int prefix_type, + const void *buf, size_t len); + +static int dec_valid_packet_count(uint8_t *count_pkt, uint8_t packet_num) +{ + /* count Success return 1, else return 0 */ + int check; + + if (packet_num > 127) + return 0; + + /* if data already exist, return 1,else return 0; if data is null return -1 */ + check = (((*(count_pkt + packet_num / 8)) & (1 << (8 - (packet_num % 8) - 1))) > 0); + if (check == 1) + return 0; + + *(count_pkt + packet_num / 8) |= 1 << (8 - (packet_num % 8) - 1); + + return 1; +} + +static enum LEADCODE_SEQ dec_get_lead_code(SC_Priv *sc_priv, struct ieee80211_frame *iframe, SC_Lead_Code *lead_code) +{ + uint8_t *sa = iframe->i_addr2; + uint8_t packet_num = iframe->i_addr3[3]; + uint8_t *data = &iframe->i_addr3[4]; + uint8_t *crc = &iframe->i_addr3[5]; + + /* the leadcode complete return 1,else return 0 */ + if ((sc_priv->Sc_Status != SC_LOCKED_CHAN) || \ + (lead_code->ssidpwd_size == 0) || (lead_code->pwd_size == -1) || \ + (lead_code->random_num == 0)) { + ;//SC_DECODE_DBG(INFO, "%s, %d\n", __func__, __LINE__); + } else { + SC_DECODE_DBG(INFO, "lead complete!!!\n"); + SC_DECODE_DBG(INFO, "ssidpwd_size : %d\n", lead_code->ssidpwd_size); + SC_DECODE_DBG(INFO, "pwd_size : %d\n", lead_code->pwd_size); + SC_DECODE_DBG(INFO, "round_num : %d\n", lead_code->random_num); + SC_DECODE_DBG(INFO, "channel : %d\n", lead_code->channel); + if (sc_priv->locked_mac_flag) { + sc_priv->locked_mac_flag = 0; + } + return LEAD_CODE_COMPLETE; + } + + if (packet_num > 0 && packet_num <= LOCDED_FIELD) { + /*crc check the leadcode*/ + uint8_t crc8 = cal_crc8(data, 1); + if (crc8 != *crc) + return LEAD_CODE_NOME; + + SC_DECODE_DBG(INFO, "get_leadcode\n"); + if (!sc_priv->locked_mac_flag) { + SC_DECODE_DBG(INFO, "locked src:\n"); + memcpy(sc_priv->locked_mac, sa, 6); + sc_priv->locked_mac_flag = 1; + print_hex_dump_bytes(NULL, 0, sc_priv->locked_mac, 6); + } + + if(packet_num == LEAD_CODE_GET_CHANNEL) { + lead_code->channel = *data; + sc_priv->Sc_Status = SC_LOCKED_CHAN; + SC_DECODE_DBG(INFO, "CHANNEL LOCKED : %d\n", lead_code->channel); + return LEAD_CODE_GET_CHANNEL; + } else if (packet_num == LEAD_CODE_GET_SSIDPWD_SIZE) { + lead_code->ssidpwd_size = *data; + lead_code->packet_sum = lead_code->ssidpwd_size / 2 + 1 + lead_code->ssidpwd_size % 2; + SC_DECODE_DBG(INFO, "PACKET_SUM %d \n", lead_code->packet_sum); + return LEAD_CODE_GET_SSIDPWD_SIZE; + } else if (packet_num == LEAD_CODE_GET_PWD_SIZE) { + lead_code->pwd_size = *data; + return LEAD_CODE_GET_PWD_SIZE; + } else if (packet_num == LEAD_CODE_GET_ROUND_NUM) { + lead_code->random_num = *data; + return LEAD_CODE_GET_ROUND_NUM; + } + } + + return LEAD_CODE_NOME; +} + +static int dec_data_decode(SC_Priv *sc_priv, SC_Result *result, SC_Lead_Code *lead_code, uint8_t *src_data_buff) +{ + int i = 0; + uint8_t src_ssid_size = 0; + uint8_t src_pwd_size = 0; + uint8_t crc8_pwd = 0; + uint8_t crc8_ssid = 0; + uint8_t *src_pwd_data = NULL; + uint8_t *src_ssid_data = NULL; + + src_ssid_size = lead_code->ssidpwd_size - lead_code->pwd_size; + src_pwd_size = lead_code->pwd_size; + SC_DECODE_DBG(INFO, "DATA_DECODE PWD_SIZE : %d SSID_SIZE : %d\n",\ + src_pwd_size, src_ssid_size); + + src_pwd_data = src_data_buff; + src_ssid_data = src_data_buff + src_pwd_size; + + if (sc_priv->Aes_Key[0] != 0) { + uint8_t temp_pwd[66]; + uint8_t temp_ssid[65]; + + SC_BUG_ON(src_pwd_size >= 66); + SC_BUG_ON(src_ssid_size >= 65); + memset(temp_pwd , 0, 66); + memset(temp_ssid, 0, 65); + + SC_DECODE_DBG(INFO, "DATA_DECODE pwd:\n"); + + if (src_pwd_size) { + if (aes_ebc_decrypt((char *)src_pwd_data, (char *) \ + temp_pwd, src_pwd_size, sc_priv->Aes_Key) == 0) { + int pwd_dlen; + + pwd_dlen = *(temp_pwd + src_pwd_size - 1); + SC_DECODE_DBG(INFO, "pwd_dlen: %d\n", pwd_dlen); + for (i = 0; i < pwd_dlen; i++) { + int value = *(temp_pwd + src_pwd_size - 1 - i); + if (value != pwd_dlen) { + SC_DECODE_DBG(ERROR, "%s(), %d, aes pwd err, value:%d\n", __func__, __LINE__, value); + return 0; + } + } + result->pwd_size = src_pwd_size - pwd_dlen; + memcpy(result->pwd, temp_pwd, strlen((const char *)temp_pwd)); + } else + SC_DECODE_DBG(ERROR, "%s,%d, aes pwd err\n", __func__, __LINE__); + } + if (src_ssid_size) { + if (aes_ebc_decrypt((char *)src_ssid_data, \ + (char *)temp_ssid, src_ssid_size, sc_priv->Aes_Key) == 0) { + int ssid_dlen = *(temp_ssid + src_ssid_size - 1); + + SC_DECODE_DBG(INFO, "ssid_dlen: %d\n", ssid_dlen); + for (i = 0; i < ssid_dlen; i++) { + int value = *(temp_ssid + src_ssid_size - 1 - i); + if (value != ssid_dlen) { + SC_DECODE_DBG(ERROR, "%s,%d, aes ssid err, value:%d\n", + __func__, __LINE__, value); + return 0; + } + } + result->ssid_size = src_ssid_size- ssid_dlen; + memcpy(result->ssid, temp_ssid, strlen((const char *)temp_ssid)); + } else + SC_DECODE_DBG(ERROR, "%s,%d, aes ssid err\n", __func__, __LINE__); + } + + *(result->pwd + result->pwd_size) = 0; + *(result->ssid + result->ssid_size) = 0; + } else if (sc_priv->Aes_Key[0] == 0) { + SC_BUG_ON(src_ssid_size >= 65); + SC_BUG_ON(src_pwd_size >= 66); + result->ssid_size = src_ssid_size; + result->pwd_size = src_pwd_size; + + memcpy(result->ssid, src_ssid_data, result->ssid_size); + memcpy(result->pwd, src_pwd_data, result->pwd_size); + + *(result->pwd + result->pwd_size) = 0; + *(result->ssid + result->ssid_size) = 0; + } + + result->random_num = lead_code->random_num; + SC_DECODE_DBG(INFO, "pwd:%s, ssid:%s\n", result->pwd, result->ssid); + + i = (lead_code->ssidpwd_size % 2); + + crc8_pwd = *(src_data_buff + lead_code->ssidpwd_size + i); + + if (cal_crc8(result->pwd, result->pwd_size) != crc8_pwd) { + src_data_buff[0] = 0; + SC_DECODE_DBG(ERROR, "%s,%d pwd crc check err\n", __func__, __LINE__); + + return 0; + } + + crc8_ssid = *(src_data_buff + lead_code->ssidpwd_size + i + 1); + + if (cal_crc8(result->ssid, result->ssid_size) != crc8_ssid) { + src_data_buff[0] = 0; + SC_DECODE_DBG(ERROR, "%s,%d ssid crc check err\n", __func__, __LINE__); + + return 0; + } + + src_data_buff[0] = 0; + + return 1; +} + +/*save data*/ +static int dec_push_data(struct ieee80211_frame *iframe, SC_Lead_Code *lead_code, uint8_t *src_data_buff) +{ + uint8_t packet_num = iframe->i_addr3[3]; + uint8_t *data = &iframe->i_addr3[4]; + int d = 0; + + packet_num -= 5; + + if (dec_valid_packet_count(lead_code->count_pkt, packet_num) == 1) + lead_code->packet_count += 1; + SC_DECODE_DBG(INFO, "push packet_num : %d\n", packet_num); + + *(src_data_buff + packet_num * 2 ) = *data; + *(src_data_buff + packet_num * 2 + 1) = *(data + 1); + d = lead_code->packet_count - lead_code->packet_sum; + + return d; +} + +SMART_CONFIG_STATUS_T sc_dec_packet_deoced(SC_Priv *sc_priv, uint8_t *data) +{ + struct ieee80211_frame *iframe = (struct ieee80211_frame *)data; + uint8_t packet_num = iframe->i_addr3[3]; + int ret; + + SC_BUG_ON(!sc_priv); + + if ((iframe->i_addr3[0] == SC_ADD0) && (iframe->i_addr3[1] == SC_ADD1) && \ + (iframe->i_addr3[2]== SC_ADD2)) + ; + else + return sc_priv->Sc_Status; + + if (!sc_priv->lead_code_inited) { + memset(&sc_priv->lead_code , 0, sizeof(SC_Lead_Code)); + sc_priv->lead_code.pwd_size = -1; + sc_priv->lead_code_inited = 1; + } + + if (sc_priv->lead_code.lead_complete_flag == 0) { + ret = dec_get_lead_code(sc_priv, iframe, &sc_priv->lead_code); + if(ret == LEAD_CODE_COMPLETE) + sc_priv->lead_code.lead_complete_flag = 1; + return sc_priv->Sc_Status; + } + + if (packet_num <= 4) + return sc_priv->Sc_Status; + + if (sc_priv->lead_code.lead_complete_flag == 1 && packet_num <= 127) { + if (dec_push_data(iframe, &sc_priv->lead_code, sc_priv->src_data_buff) != 0) + return sc_priv->Sc_Status; + } + + if (sc_priv->lead_code.packet_sum == sc_priv->lead_code.packet_count){ + SC_DECODE_DBG(INFO, "DATA IS ALL RECEIVE\n"); + SC_DECODE_DBG(INFO, "data_decode\n"); + int data_decode_ret = dec_data_decode(sc_priv, &sc_priv->sc_result, &sc_priv->lead_code, sc_priv->src_data_buff); + if (data_decode_ret) { + SC_DECODE_DBG(INFO, "decode success\n"); + sc_priv->Sc_Status = SC_COMPLETED; + } else { + SC_DECODE_DBG(INFO, "decode err\n"); + if (sc_priv->lead_code_inited) { + sc_priv->lead_code_inited = 0; + } + + if (sc_priv->src_data_buff[0]) { + sc_priv->src_data_buff[0] = 0; + } + + sc_priv->Sc_Status = SC_END; + } + } + + return sc_priv->Sc_Status; +} + +int sc_set_aeskey(SC_Priv *sc_priv, const char *key, uint32_t length) +{ + if (length != SC_KEY_LEN) + return -1; + + memcpy(sc_priv->Aes_Key, key, SC_KEY_LEN); + + return 0; +} + +uint16_t sc_read_locked_channel(SC_Priv *sc_priv) +{ + return sc_priv->lead_code.channel; +} + +SC_Result *sc_read_result(SC_Priv *sc_priv) +{ + return (sc_priv->sc_result.ssid[0] ? &sc_priv->sc_result : NULL); +} diff --git a/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_decode.h b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_decode.h new file mode 100644 index 0000000000..2f199c829c --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_decode.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SC_DECODE_H__ +#define __SC_DECODE_H__ + +#include "types.h" + +#define SC_ADD0 0x01 +#define SC_ADD1 0x00 +#define SC_ADD2 0X5E + +typedef enum { + SC_VALUE_FALSE = 0, + SC_VALUE_TRUE = 1, +} SC_BOOL; + +typedef enum { + SC_VALUE_NOT_READY, + SC_VALUE_COMPLETE, +} SC_RESULT_STA; + +typedef enum { + SC_END = 0, + SC_SEARCH_CHAN, + SC_LOCKED_CHAN, + SC_COMPLETED, +} SMART_CONFIG_STATUS_T; + +typedef struct { + uint8_t ssid[65]; + uint8_t pwd[66]; + uint8_t ssid_size ; + uint8_t pwd_size ; + uint8_t random_num; +} SC_Result; + +typedef struct { + int channel; + int ssidpwd_size; + int pwd_size; + int packet_sum; + int packet_count; + uint8_t random_num; + uint8_t lead_complete_flag; + uint8_t count_pkt[16]; +} SC_Lead_Code; + +#define SC_KEY_LEN 16 + +typedef struct { + char Aes_Key[SC_KEY_LEN]; + SC_Lead_Code lead_code; + int lead_code_inited; + SMART_CONFIG_STATUS_T sc_ctrl; + uint8_t locked_mac[6]; + int locked_mac_flag; + SMART_CONFIG_STATUS_T Sc_Status; + SC_Result sc_result; + uint8_t src_data_buff[1500]; +} SC_Priv; + +SMART_CONFIG_STATUS_T sc_dec_packet_deoced(SC_Priv *sc_priv, uint8_t *data); +SC_Result *sc_read_result(SC_Priv *sc_priv); +uint16_t sc_read_locked_channel(SC_Priv *sc_priv); +/* the key length must be 16 byte */ +int sc_set_aeskey(SC_Priv *sc_priv, const char *key, uint32_t length); + +#endif /* __SC_DECODE_H__ */ diff --git a/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_main.c b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_main.c new file mode 100644 index 0000000000..63d4c02bd8 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/smartconfig/smart_config_main.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stdio.h" +#include "stdlib.h" +#include "errno.h" +#include "string.h" +#include "sys/mbuf.h" +#include "kernel/os/os.h" +#include "net/wlan/wlan.h" + +#include "net/wlan/wlan_smart_config.h" +#include "smart_config_decode.h" + +enum loglevel{ + OFF = 0, + ERROR = 1, + INFO = 2, +}; + +#define g_debuglevel ERROR + +#define SMART_DBG(level, fmt, args...) \ + do { \ + if (level <= g_debuglevel) \ + printf("[smart config]"fmt,##args); \ + } while (0) + +#define MAX_TIME 4294967295 +static struct netif *priv_nif = NULL; +SC_Priv *sc_priv; + +static uint32_t d_time(uint32_t time1, uint32_t time2) +{ + uint32_t d_time = 0; + if (time1 <= time2) + d_time = time2 - time1; + else + d_time = MAX_TIME - time1 + time2; + return d_time; +} + +static int smartconfig_wifi_set_channel(struct netif *nif, int16_t ch) +{ + return wlan_monitor_set_channel(nif, ch); +} + +static void process_macframe(uint8_t *data, uint32_t len, void *info) +{ + /* make sure frame is qos data frame. */ + SMART_CONFIG_STATUS_T sta = sc_dec_packet_deoced(sc_priv, data); + + if (sta == SC_COMPLETED) { + SMART_DBG(INFO, "%s(),%d complete\n", __func__, __LINE__); + sc_priv->sc_ctrl = SC_END; + + if (wlan_monitor_set_rx_cb(priv_nif, NULL) == -1) + SMART_DBG(ERROR, "%s(),%d monitor set rx cb error\n", __func__, __LINE__); + } else if (sta == SC_LOCKED_CHAN) { + sc_priv->sc_ctrl = SC_LOCKED_CHAN; + } +} + +static int smartconfig_read_result(wlan_smart_config_result_t *result) +{ + SC_Result *sc_result = sc_read_result(sc_priv); + + if (sc_result != NULL) { + if (sc_result->ssid_size > WLAN_SSID_MAX_LEN) { + SMART_DBG(ERROR, "Invalid ssid len %d\n", sc_result->ssid_size); + return -1; + } + + if (sc_result->pwd_size > WLAN_PASSPHRASE_MAX_LEN) { + SMART_DBG(ERROR, "Invalid passphrase len %d\n", sc_result->pwd_size); + return -1; + } + + SMART_DBG(INFO, "smart config: ssid: %.32s, passphrase: %s, random_num: %d\n", + sc_result->ssid, sc_result->pwd, sc_result->random_num); + + memcpy(result->ssid, sc_result->ssid, sc_result->ssid_size); + result->ssid_len = sc_result->ssid_size; + + if (sc_result->pwd_size > 0 && sc_result->pwd != NULL) { + memcpy(result->passphrase, sc_result->pwd, sc_result->pwd_size); + result->passphrase[sc_result->pwd_size] = '\0'; + } else { + result->passphrase[0] = '\0'; + } + + result->random_num = sc_result->random_num; + return 0; + } + + return -1; +} + +/* the key length must be 16 byte */ +static int smartconfig_set_key(const char *key, uint32_t length) +{ + if (!sc_priv) { + sc_priv = malloc(sizeof(SC_Priv)); + if (!sc_priv) { + SMART_DBG(ERROR, "%s(),%d, malloc faild!\n", __func__, __LINE__); + return -1; + } + memset(sc_priv, 0, sizeof(SC_Priv)); + } + + return sc_set_aeskey(sc_priv, key, length); +} + +static void smartconfig_close(void) +{ + SMART_DBG(INFO, "close\n"); + + if (sc_priv) { + if (wlan_monitor_set_rx_cb(priv_nif, NULL) != 0) + SMART_DBG(ERROR, "%s(),%d monitor set rx cb fail\n", __func__, __LINE__); + + sc_priv->sc_ctrl = SC_END; + OS_MSleep(150); + free(sc_priv); + sc_priv = NULL; + } +} + +static wlan_smart_config_status_t smartconfig_start(struct netif *nif, + uint32_t timeout_ms, + wlan_smart_config_result_t *result) +{ + int ret = -1; + wlan_smart_config_status_t status = WLAN_SMART_CONFIG_FAIL; + int16_t channel = 0; + int16_t channel_burrer[] = {1, 6, 12, 2, 3, 4, 5, 7, 8, 9, 10, 11, 13}; + + if (nif == NULL || result == NULL) { + SMART_DBG(ERROR, "%s(),%d, nif %p, result %p\n", __func__, __LINE__, nif, result); + return WLAN_SMART_CONFIG_INVALID; + } + + priv_nif = nif; + SMART_DBG(INFO, "start\n"); + + if (!sc_priv) { + sc_priv = malloc(sizeof(SC_Priv)); + if (!sc_priv) { + SMART_DBG(ERROR, "malloc faild!\n"); + return status; + } + memset(sc_priv, 0, sizeof(SC_Priv)); + } + + sc_priv->sc_ctrl = SC_SEARCH_CHAN; + + SMART_DBG(INFO, "monitor_register\n"); + ret = wlan_monitor_set_rx_cb(priv_nif, process_macframe); + if (ret != 0) { + SMART_DBG(ERROR, "%s(),%d monitor set rx cb fail\n", __func__, __LINE__); + goto out; + } + + uint32_t start_time = OS_JiffiesToMSecs(OS_GetJiffies()); + + while (1) { + if (sc_priv->sc_ctrl == SC_SEARCH_CHAN) { + smartconfig_wifi_set_channel(priv_nif, channel_burrer[channel]); + + if (++channel >= sizeof(channel_burrer)) + channel = 0; + } else if (sc_priv->sc_ctrl == SC_LOCKED_CHAN) { + if (sc_read_locked_channel(sc_priv)) + smartconfig_wifi_set_channel(priv_nif, sc_read_locked_channel(sc_priv)); + + SMART_DBG(INFO, "channel locked\n"); + while (sc_priv->sc_ctrl) { + OS_MSleep(10); + } + break; + } else if (sc_priv->sc_ctrl == SC_END) { + break; + } + uint32_t d_t = d_time(start_time, OS_JiffiesToMSecs(OS_GetJiffies())); + if (d_t >= timeout_ms) { + smartconfig_close(); + status = WLAN_SMART_CONFIG_TIMEOUT; + goto out; + } + + OS_MSleep(100); + } + + ret = smartconfig_read_result(result); + if (ret == 0) { + status = WLAN_SMART_CONFIG_SUCCESS; + } + +out: + if (sc_priv) { + free(sc_priv); + sc_priv = NULL; + } + SMART_DBG(INFO, "end\n"); + return status; +} + +int wlan_smart_config_set_key(const char *key, uint32_t len) +{ + if (key == NULL || len != WLAN_SMART_CONFIG_KEY_LEN) { + SMART_DBG(ERROR, "invalid smart config key (%p, %d)\n", key, len); + return -1; + } + + return smartconfig_set_key(key, len); +} + +wlan_smart_config_status_t wlan_smart_config_start(struct netif *nif, + uint32_t timeout_ms, + wlan_smart_config_result_t *result) +{ + return smartconfig_start(nif, timeout_ms, result); +} + +int wlan_smart_config_stop(void) +{ + smartconfig_close(); + return 0; +} diff --git a/platform/mcu/xr871/src/net/wlan/wlan.c b/platform/mcu/xr871/src/net/wlan/wlan.c new file mode 100644 index 0000000000..b4ba1d9209 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/wlan.c @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +#include "wlan_debug.h" +#include "wpa_ctrl_req.h" +#include "lwip/netif.h" +#include "sys/ducc/ducc_net.h" +#include "sys/ducc/ducc_app.h" + +#include "net/wlan/wlan.h" +#include "net/wlan/wlan_defs.h" + +#include "kernel/os/os.h" + +#define WLAN_ASSERT_POINTER(p) \ + do { \ + if (p == NULL) { \ + WLAN_ERR("invalid parameter\n"); \ + return -1; \ + } \ + } while (0) + +/** + * @brief Configure station in a convenient way to join a specified network + * @param[in] ssid Network name, length is [1, 32] + * @param[in] ssid_len The length of network name + * @param[in] psk Network password, in one of the optional formats: + * - NULL, to join an OPEN network + * - an ASCII string, length is [8, 63] + * - a hex string (two characters per octet of PSK), length is 64 + * @return 0 on success, -1 on failure + * + * @note This way is only adapted to join an OPEN, WPA-PSK, WPA2-PSK or + * WPA-PSK/WPA2-PSK network. + */ +int wlan_sta_set(uint8_t *ssid, uint8_t ssid_len, uint8_t *psk) +{ + WLAN_ASSERT_POINTER(ssid); + + if ((ssid_len == 0) || (ssid_len > 32)) { + WLAN_ERR("invalid ssid len %d\n", ssid_len); + return -1; + } + + wlan_sta_config_t config; + wlan_memset(&config, 0, sizeof(config)); + + /* ssid */ + config.field = WLAN_STA_FIELD_SSID; + wlan_memcpy(config.u.ssid.ssid, ssid, ssid_len); + config.u.ssid.ssid_len = ssid_len; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + /* auth_alg: OPEN */ + config.field = WLAN_STA_FIELD_AUTH_ALG; + config.u.auth_alg = WPA_AUTH_ALG_OPEN; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + if (psk == NULL) { + /* key_mgmt: NONE */ + config.field = WLAN_STA_FIELD_KEY_MGMT; + config.u.key_mgmt = WPA_KEY_MGMT_NONE; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + } else { + /* psk */ + config.field = WLAN_STA_FIELD_PSK; + wlan_strlcpy((char *)config.u.psk, (char *)psk, sizeof(config.u.psk)); + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + /* proto: WPA | RSN */ + config.field = WLAN_STA_FIELD_PROTO; + config.u.proto = WPA_PROTO_WPA | WPA_PROTO_RSN; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + /* key_mgmt: PSK */ + config.field = WLAN_STA_FIELD_KEY_MGMT; + config.u.key_mgmt = WPA_KEY_MGMT_PSK; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + /* pairwise: CCMP | TKIP */ + config.field = WLAN_STA_FIELD_PAIRWISE_CIPHER; + config.u.pairwise_cipher = WPA_CIPHER_CCMP | WPA_CIPHER_TKIP; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + /* group: CCMP | TKIP | WEP40 | WEP104 */ + config.field = WLAN_STA_FIELD_GROUP_CIPHER; + config.u.pairwise_cipher = WPA_CIPHER_CCMP | WPA_CIPHER_TKIP + | WPA_CIPHER_WEP40 | WPA_CIPHER_WEP104; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + } + + /* scan_ssid: 1 */ + config.field = WLAN_STA_FIELD_SCAN_SSID; + config.u.scan_ssid = 1; + if (wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, &config) != 0) + return -1; + + return 0; +} + +/** + * @brief Set station specified field configuration + * @param[in] config Pointer to the configuration + * @return 0 on success, -1 on failure + */ +int wlan_sta_set_config(wlan_sta_config_t *config) +{ + WLAN_ASSERT_POINTER(config); + + return wpa_ctrl_request(WPA_CTRL_CMD_STA_SET, config); +} + +/** + * @brief Get station specified field configuration + * @param[in] config Pointer to the configuration + * @return 0 on success, -1 on failure + */ +int wlan_sta_get_config(wlan_sta_config_t *config) +{ + WLAN_ASSERT_POINTER(config); + + return wpa_ctrl_request(WPA_CTRL_CMD_STA_GET, config); +} + +/** + * @brief Enable the station + * @return 0 on success, -1 on failure + */ +int wlan_sta_enable(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_ENABLE, NULL); +} + +/** + * @brief Disable the station + * @return 0 on success, -1 on failure + */ +int wlan_sta_disable(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_DISABLE, NULL); +} + +/** + * @brief Station scan once + * @return 0 on success, -1 on failure + */ +int wlan_sta_scan_once(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_SCAN, NULL); +} + +/** + * @brief Get station scan results + * @param[in] results Pointer to the scan results + * @return 0 on success, -1 on failure + */ +int wlan_sta_scan_result(wlan_sta_scan_results_t *results) +{ + WLAN_ASSERT_POINTER(results); + + return wpa_ctrl_request(WPA_CTRL_CMD_STA_SCAN_RESULTS, results); +} + +/** + * @brief Set station scan interval + * @param[in] sec Scan interval in Seconds + * @return 0 on success, -1 on failure + */ +int wlan_sta_scan_interval(int sec) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_SCAN_INTERVAL, (void *)sec); +} + +/** + * @brief Flush station old BSS entries + * @param[in] age Maximum entry age in seconds + * @return 0 on success, -1 on failure + * + * @note Remove BSS entries that have not been updated during the last @age + * seconds. + */ +int wlan_sta_bss_flush(int age) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_BSS_FLUSH, (void *)age); +} + +/** + * @brief Request a new connection + * @return 0 on success, -1 on failure + */ +int wlan_sta_connect(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_REASSOCIATE, NULL); +} + +/** + * @brief Disconnect the current connection + * @return 0 on success, -1 on failure + */ +int wlan_sta_disconnect(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_DISCONNECT, NULL); +} + +/** + * @brief Get station connection state + * @param[in] state Pointer to the connection state + * @return 0 on success, -1 on failure + */ +int wlan_sta_state(wlan_sta_states_t *state) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_STATE, state); +} + +/** + * @brief Get the information of connected AP + * @param[in] ap Pointer to the AP information + * @return 0 on success, -1 on failure + */ +int wlan_sta_ap_info(wlan_sta_ap_t *ap) +{ + WLAN_ASSERT_POINTER(ap); + + return wpa_ctrl_request(WPA_CTRL_CMD_STA_AP, ap); +} + +/** + * @brief Start the WPS negotiation with PBC method + * @return 0 on success, -1 on failure + * + * @note WPS will be turned off automatically after two minutes. + */ +int wlan_sta_wps_pbc(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_STA_WPS_PBC, NULL); +} + +/** + * @brief Get a random valid WPS PIN + * @param[in] wps Pointer to the WPS pin + * @return 0 on success, -1 on failure + */ +int wlan_sta_wps_pin_get(wlan_sta_wps_pin_t *wps) +{ + WLAN_ASSERT_POINTER(wps); + + return wpa_ctrl_request(WPA_CTRL_CMD_STA_WPS_GET_PIN, wps); +} + +/** + * @brief Start the WPS negotiation with PIN method + * @param[in] wps Pointer to the WPS pin + * @return 0 on success, -1 on failure + * + * @note WPS will be turned off automatically after two minutes. + */ +int wlan_sta_wps_pin_set(wlan_sta_wps_pin_t *wps) +{ + WLAN_ASSERT_POINTER(wps); + + return wpa_ctrl_request(WPA_CTRL_CMD_STA_WPS_SET_PIN, wps); +} + +/** + * @brief Configure AP in a convenient way to build a specified network + * @param[in] ssid Network name, length is [1, 32] + * @param[in] ssid_len The length of network name + * @param[in] psk Network password, in one of the optional formats: + * - NULL, to build an OPEN network + * - an ASCII string, length is [8, 63] + * - a hex string (two characters per octet of PSK), length is 64 + * @return 0 on success, -1 on failure + * + * @note This way is only adapted to build an OPEN or WPA-PSK/WPA2-PSK network. + */ +int wlan_ap_set(uint8_t *ssid, uint8_t ssid_len, uint8_t *psk) +{ + WLAN_ASSERT_POINTER(ssid); + + if ((ssid_len == 0) || (ssid_len > 32)) { + WLAN_ERR("invalid ssid len %d\n", ssid_len); + return -1; + } + + wlan_ap_config_t config; + wlan_memset(&config, 0, sizeof(config)); + + /* ssid */ + config.field = WLAN_AP_FIELD_SSID; + wlan_memcpy(config.u.ssid.ssid, ssid, ssid_len); + config.u.ssid.ssid_len = ssid_len; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + /* auth_alg: OPEN */ + config.field = WLAN_AP_FIELD_AUTH_ALG; + config.u.auth_alg = WPA_AUTH_ALG_OPEN; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + if (psk == NULL) { + /* proto: 0 */ + config.field = WLAN_AP_FIELD_PROTO; + config.u.proto = 0; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + /* key_mgmt: NONE */ + config.field = WLAN_AP_FIELD_KEY_MGMT; + config.u.key_mgmt = WPA_KEY_MGMT_NONE; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + } else { + /* psk */ + config.field = WLAN_AP_FIELD_PSK; + wlan_strlcpy((char *)config.u.psk, (char *)psk, sizeof(config.u.psk)); + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + /* proto: WPA | RSN */ + config.field = WLAN_AP_FIELD_PROTO; + config.u.proto = WPA_PROTO_WPA | WPA_PROTO_RSN; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + /* key_mgmt: PSK */ + config.field = WLAN_AP_FIELD_KEY_MGMT; + config.u.key_mgmt = WPA_KEY_MGMT_PSK; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + } + + /* wpa_cipher: TKIP */ + config.field = WLAN_AP_FIELD_WPA_CIPHER; + config.u.wpa_cipher = WPA_CIPHER_TKIP; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + /* rsn_cipher: CCMP */ + config.field = WLAN_AP_FIELD_RSN_CIPHER; + config.u.rsn_cipher = WPA_CIPHER_CCMP; + if (wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, &config) != 0) + return -1; + + return 0; +} + +/** + * @brief Set AP specified field configuration + * @param[in] config Pointer to the configuration + * @return 0 on success, -1 on failure + */ +int wlan_ap_set_config(wlan_ap_config_t *config) +{ + WLAN_ASSERT_POINTER(config); + + return wpa_ctrl_request(WPA_CTRL_CMD_AP_SET, config); +} + +/** + * @brief Get AP specified field configuration + * @param[in] config Pointer to the configuration + * @return 0 on success, -1 on failure + */ +int wlan_ap_get_config(wlan_ap_config_t *config) +{ + WLAN_ASSERT_POINTER(config); + + return wpa_ctrl_request(WPA_CTRL_CMD_AP_GET, config); +} + +/** + * @brief Enable the AP + * @return 0 on success, -1 on failure + */ +int wlan_ap_enable(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_AP_ENABLE, NULL); +} + +/** + * @brief Reload AP configuration + * @return 0 on success, -1 on failure + */ +int wlan_ap_reload(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_AP_RELOAD, NULL); +} + +/** + * @brief Disable the AP + * @return 0 on success, -1 on failure + */ +int wlan_ap_disable(void) +{ + return wpa_ctrl_request(WPA_CTRL_CMD_AP_DISABLE, NULL); +} + +/** + * @brief Get the number of connected stations + * @param[in] num Pointer to the number + * @return 0 on success, -1 on failure + */ +int wlan_ap_sta_num(int *num) +{ + WLAN_ASSERT_POINTER(num); + + return wpa_ctrl_request(WPA_CTRL_CMD_AP_STA_NUM, num); +} + +/** + * @brief Get the information of connected stations + * @param[in] stas Pointer to the stations information + * @return 0 on success, -1 on failure + */ +int wlan_ap_sta_info(wlan_ap_stas_t *stas) +{ + WLAN_ASSERT_POINTER(stas); + + return wpa_ctrl_request(WPA_CTRL_CMD_AP_STA_INFO, stas); +} + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ diff --git a/platform/mcu/xr871/src/net/wlan/wlan.mk b/platform/mcu/xr871/src/net/wlan/wlan.mk new file mode 100644 index 0000000000..4349603a88 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/wlan.mk @@ -0,0 +1,13 @@ +NAME := wlan + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := airkiss/airkiss_ack.c \ + airkiss/airkiss_discover.c \ + airkiss/airkiss_main.c \ + smartconfig/smart_config_ack.c \ + smartconfig/smart_config_crc.c \ + smartconfig/smart_config_decode.c \ + smartconfig/smart_config_main.c \ + ethernetif.c \ + wlan.c \ + wlan_ctrl.c diff --git a/platform/mcu/xr871/src/net/wlan/wlan_ctrl.c b/platform/mcu/xr871/src/net/wlan/wlan_ctrl.c new file mode 100644 index 0000000000..4e96d87b52 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/wlan_ctrl.c @@ -0,0 +1,572 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +#include "wlan_debug.h" +#include "wpa_ctrl_req.h" + +#include "pm/pm.h" +#include "sys/image.h" +#include "net/wlan/wlan.h" +#include "xz/decompress.h" +#include "sys/ducc/ducc_net.h" +#include "sys/ducc/ducc_app.h" +#include "driver/chip/hal_util.h" +#include "driver/chip/hal_ccm.h" +#include "driver/chip/hal_prcm.h" +#include "driver/chip/hal_efuse.h" +#include "kernel/os/os_semaphore.h" + +int wpa_ctrl_request(wpa_ctrl_cmd_t cmd, void *data) +{ + struct ducc_param_wlan_wpa_ctrl_req param; + param.cmd = cmd; + param.data = data; + + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_WPA_CTRL_REQUEST, ¶m); +} + +static __inline int wpa_ctrl_open(void) +{ + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_WPA_CTRL_OPEN, NULL); +} + +static __inline void wpa_ctrl_close(void) +{ + ducc_app_ioctl(DUCC_APP_CMD_WLAN_WPA_CTRL_CLOSE, NULL); +} + +int wlan_start(struct netif *nif) +{ + if (ducc_app_ioctl(DUCC_APP_CMD_WLAN_START, nif->state) != 0) { + return -1; + } + + return wpa_ctrl_open(); +} + +/* Note: make sure wlan is disconnect before calling wlan_stop() */ +int wlan_stop(void) +{ + if (ducc_app_ioctl(DUCC_APP_CMD_WLAN_STOP, NULL) != 0) { + return -1; + } + wpa_ctrl_close(); + return 0; +} + +int wlan_set_mac_addr(uint8_t *mac_addr, int mac_len) +{ + struct ducc_param_wlan_set_mac_addr param; + param.mac_addr = mac_addr; + param.mac_len = mac_len; + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_SET_MAC_ADDR, ¶m); +} + +int wlan_set_ip_addr(struct netif *nif, uint8_t *ip_addr, int ip_len) +{ + struct ducc_param_wlan_set_ip_addr param; + param.ifp = nif->state; + param.ip_addr = ip_addr; + param.ip_len = ip_len; + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_SET_IP_ADDR, ¶m); +} + +/** + * @brief Set application-specified IE to specified management frame + * @param[in] nif Pointer to the network interface + * @param[in] type Management frame type to be set + * eg. (IEEE80211_FC_TYPE_MGMT | IEEE80211_FC_STYPE_BEACON) + * @param[in] ie Pointer to application-specified IE data + * @param[in] ie_len Length of application-specified IE data + * @return 0 on success + * + * @note To delete existing application-specified IE, set ie to NULL, or set + * ie_len to 0. + */ +int wlan_set_appie(struct netif *nif, uint8_t type, uint8_t *ie, uint16_t ie_len) +{ + struct ducc_param_wlan_appie param; + enum wlan_mode mode = ethernetif_get_mode(nif); + + if (mode != WLAN_MODE_STA && mode != WLAN_MODE_HOSTAP) { + WLAN_DBG("unsupport mode %d\n", mode); + return -1; + } + + param.ifp = nif->state; + param.type = type; + param.ie = ie; + param.ie_len = ie_len; + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_SET_APPIE, ¶m); +} + +/* monitor */ +static wlan_monitor_rx_cb m_wlan_monitor_rx_cb = NULL; + +#define DUMP_MON_DATA 0 +#if DUMP_MON_DATA +#define DUMPDLEN 40 +uint8_t dump_data[DUMPDLEN]; +#endif + +void wlan_monitor_input(struct netif *nif, uint8_t *data, uint32_t len, void *info) +{ + #if DUMP_MON_DATA + { + uint32_t dump_len = len > DUMPDLEN ? DUMPDLEN : len; + memset(dump_data, 0, dump_len); + memcpy(dump_data, data, dump_len); + if( dump_data[4] == 0x01 && dump_data[5] == 0x00 && dump_data[6] == 0x5e ) { + for(int i= 4; i < dump_len ;i++) { + printf("0x%02x ", dump_data[i]); + } + printf("\n"); + } + } + #endif + + if (m_wlan_monitor_rx_cb) { + m_wlan_monitor_rx_cb(data, len, info); + } +} + +int wlan_monitor_set_rx_cb(struct netif *nif, wlan_monitor_rx_cb cb) +{ + int enable = cb ? 1 : 0; + m_wlan_monitor_rx_cb = cb; + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_MONITOR_ENABLE_RX, (void *)enable); +} + +int wlan_monitor_set_channel(struct netif *nif, int16_t channel) +{ + struct ducc_param_wlan_mon_set_chan param; + enum wlan_mode mode = ethernetif_get_mode(nif); + + if (mode != WLAN_MODE_MONITOR) { + WLAN_DBG("NOT in monitor mode, current mode %d\n", mode); + return -1; + } + + param.ifp = nif->state; + param.channel = channel; + return ducc_app_ioctl(DUCC_APP_CMD_WLAN_MONITOR_SET_CHAN, ¶m); +} + +/* PM */ +#ifdef CONFIG_PM +static int m_wlan_suspending; + +static int wlan_power_notify(enum suspend_state_t state) +{ + return ducc_app_ioctl(DUCC_APP_CMD_POWER_NOTIFY, (void *)state); +} + +int wlan_wakeup_net(void) +{ + return wlan_power_notify(PM_MODE_ON); +} + +static int wlan_power_callback(int state) +{ + m_wlan_suspending = 0; + + return 0; +} + +static int wlan_sys_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + int err = 0; + uint32_t _timeout = OS_GetTicks() + OS_SecsToJiffies(3); + + switch (state) { + case PM_MODE_STANDBY: + m_wlan_suspending = 1; + wlan_power_notify(PM_MODE_ON); + wlan_power_notify(state); + while (!HAL_PRCM_IsCPUNDeepSleep() && m_wlan_suspending && + OS_TimeBefore(OS_GetTicks(), _timeout)) { + OS_MSleep(5); + } + if (OS_TimeAfterEqual(OS_GetTicks(), _timeout) || !m_wlan_suspending) { + err = -1; + break; + } + OS_MSleep(2); + break; + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + /* step1: notify net cpu to switch to HOSC, turn off SYSCLK2 and enter WFI state. */ + m_wlan_suspending = 1; + wlan_power_notify(PM_MODE_POWEROFF); + while (!HAL_PRCM_IsCPUNSleep() && m_wlan_suspending) { + OS_MSleep(5); + } + if (!m_wlan_suspending) + WLAN_WARN("wlan poweroff faild!\n"); + OS_MSleep(5); /* wait net cpu enter wfi */ + + /* step2: writel(0x00, GPRCM_SYS2_CRTL) to reset and isolation network system. */ + HAL_PRCM_EnableSys2Isolation(); + HAL_PRCM_ForceCPUNReset(); + HAL_PRCM_ForceSys2Reset(); + OS_MSleep(5); + HAL_PRCM_DisableSys2Power(); + WLAN_DBG("%s okay\n", __func__); + break; + default: + break; + } + + return err; +} + +static int wlan_sys_resume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_STANDBY: + /* maybe wakeup net at this time better than later by other cmds */ + pm_set_sync_magic(); + wlan_power_notify(PM_MODE_ON); + m_wlan_suspending = 0; + WLAN_DBG("%s okay\n", __func__); + break; + default: + break; + } + + return 0; +} + +static struct soc_device_driver m_wlan_sys_drv = { + .name = "wlan_sys", + .suspend = wlan_sys_suspend, + .resume = wlan_sys_resume, +}; + +static struct soc_device m_wlan_sys_dev = { + .name = "wlan_sys", + .driver = &m_wlan_sys_drv, +}; + +#define WLAN_SYS_DEV (&m_wlan_sys_dev) + +#else /* CONFIG_PM */ + +static int wlan_power_callback(int state) +{ + return 0; +} + +#define WLAN_SYS_DEV NULL + +#endif /* CONFIG_PM */ + +static OS_Semaphore_t m_ducc_sync_sem; /* use to sync with net system */ +static ducc_cb_func m_wlan_net_sys_cb = NULL; + +#define COMP_BUF_SIZE (4 * 1024) +#define STREAN_FOOT_LEN 12 + +static uint32_t wlan_net_uncompress_size(uint32_t image_id, section_header_t *sh, uint8_t *buf, uint32_t buf_size) +{ + uint32_t read_len = 0; + + if (buf_size < 1204) { + WLAN_ERR("%s: %d The buf size minimum 1KB, buf_size %d\n", __func__, __LINE__, buf_size); + goto error; + } + + read_len = image_read(image_id, IMAGE_SEG_BODY, sh->body_len - STREAN_FOOT_LEN, buf, STREAN_FOOT_LEN); + if (read_len != STREAN_FOOT_LEN) { + WLAN_ERR("%s: %d read image error, len %d\n", __func__, __LINE__, read_len); + goto error; + } + + uint32_t index_len = xz_index_len(buf); + + read_len = image_read(image_id, IMAGE_SEG_BODY, sh->body_len - STREAN_FOOT_LEN - index_len, buf, index_len); + if (read_len != index_len) { + WLAN_ERR("%s: %d read image error, len %d\n", __func__, __LINE__, read_len); + goto error; + } + + return xz_file_uncompress_size(buf, read_len); + + error: + return 0; +} + +static int wlan_compress_bin(uint32_t image_id, section_header_t *sh) +{ + struct xz_buf stream; + uint32_t read_len = 0; + uint32_t ret; + uint32_t d_len = 0; + uint32_t compress_len = 0; + uint32_t read_count = 0; + uint32_t last_len = 0; + uint16_t checksum = 0; + uint8_t *read_buf = NULL; + int umcompress_sta = 0; + int i = 0; + + read_buf = (uint8_t *)malloc(COMP_BUF_SIZE); + if (!read_buf) { + WLAN_ERR("%s: %d malloc error\n", __func__, __LINE__); + goto error; + } + + checksum += sh->data_chksum; + last_len = sh->body_len % COMP_BUF_SIZE; + read_count = (sh->body_len + COMP_BUF_SIZE - 1 ) & (~(COMP_BUF_SIZE - 1)); + read_count /= COMP_BUF_SIZE; + if (last_len) + read_count -= 1; + + d_len = wlan_net_uncompress_size(image_id, sh, read_buf, COMP_BUF_SIZE); + + if (!xz_uncompress_init(&stream)) { + WLAN_ERR("%s: %d xz uncompress init error\n", __func__, __LINE__); + goto error; + } + + read_len = COMP_BUF_SIZE; + for (i = 0; i <= read_count; i ++) { + if (i == read_count) + read_len = last_len; + + ret = image_read(image_id, IMAGE_SEG_BODY, i * COMP_BUF_SIZE, read_buf, read_len); + if (ret != read_len) { + WLAN_ERR("%s: %d read image error, len %d\n", __func__, __LINE__, ret); + goto error; + } + + checksum += image_get_checksum(read_buf, read_len); + + umcompress_sta = xz_uncompress_stream(&stream, read_buf, read_len, + (uint8_t *)sh->load_addr, d_len, &compress_len); + if (umcompress_sta != XZ_OK && umcompress_sta != XZ_STREAM_END) { + WLAN_ERR("%s: %d uncompress error %d\n", __func__, __LINE__, umcompress_sta); + goto error; + } + sh->load_addr += compress_len; + d_len -= compress_len; + } + + if (checksum != 0xFFFF) { + WLAN_ERR("%s: checksum error error, checksum %d\n", __func__, checksum); + goto error; + } + + xz_uncompress_end(); + free(read_buf); + return 0; +error: + free(read_buf); + return -1; +} + +static int wlan_load_net_bin(enum wlan_mode mode) +{ + section_header_t section_header; + section_header_t *sh = §ion_header; + uint32_t image_id; + + image_id = (mode == WLAN_MODE_HOSTAP) ? IMAGE_NET_AP_ID : IMAGE_NET_ID; + + if (image_read(image_id, IMAGE_SEG_HEADER, 0, sh, IMAGE_HEADER_SIZE) != IMAGE_HEADER_SIZE + || (image_check_header(sh) == IMAGE_INVALID)) { + WLAN_ERR("%s: failed to load net section\n", __func__); + return -1; + } + + if (sh->attribute & (1 << 4)) { + if (wlan_compress_bin(image_id, sh) == -1) + return -1; + } else { + if ((image_read(image_id, IMAGE_SEG_BODY, 0, (void *)sh->load_addr, sh->body_len) != sh->body_len) + || (image_check_data(sh, (void *)sh->load_addr, sh->data_size, NULL, 0) == IMAGE_INVALID)) { + WLAN_ERR("%s: failed to load net section\n", __func__); + return -1; + } + } + + return 0; +} + +static int wlan_get_wlan_bin(int type, int offset, uint8_t *buf, int len) +{ + uint32_t id; + section_header_t section_header; + section_header_t *sh = §ion_header; + + switch (type) { + case DUCC_WLAN_BIN_TYPE_BL: + id = IMAGE_WLAN_BL_ID; + break; + case DUCC_WLAN_BIN_TYPE_FW: + id = IMAGE_WLAN_FW_ID; + break; + case DUCC_WLAN_BIN_TYPE_SDD: + id = IMAGE_WLAN_SDD_ID; + break; + default: + WLAN_ERR("invalid wlan bin type\n"); + return 0; + } + + if (offset == 0) { + if (image_read(id, IMAGE_SEG_HEADER, 0, sh, IMAGE_HEADER_SIZE) != IMAGE_HEADER_SIZE) { + WLAN_ERR("load section (id: %#08x) header failed\n", id); + return 0; + } + if (image_check_header(sh) == IMAGE_INVALID) { + WLAN_ERR("check section (id: %#08x) header failed\n", id); + return 0; + } + + if (len > sh->body_len) + len = sh->body_len; + } + + if (image_read(id, IMAGE_SEG_BODY, offset, buf, len) != len) { + WLAN_ERR("load section (id: %#010x) body failed\n", id); + return 0; + } + + if (offset == 0) + return sh->body_len; + else + return len; +} + +static int wlan_sys_callback(uint32_t param0, uint32_t param1) +{ + struct ducc_param_wlan_bin *p; + struct ducc_param_efuse *efuse; + + switch (param0) { + case DUCC_NET_CMD_SYS_EVENT: + switch (param1) { + case DUCC_NET_SYS_READY: + OS_SemaphoreRelease(&m_ducc_sync_sem); + break; + default: + break; + } + break; + case DUCC_NET_CMD_POWER_NOTIFY: + wlan_power_callback(param1); + break; + case DUCC_NET_CMD_BIN_READ: + p = (struct ducc_param_wlan_bin *)param1; + return wlan_get_wlan_bin(p->type, p->index, p->buf, p->len); + case DUCC_NET_CMD_EFUSE_READ: + efuse = (struct ducc_param_efuse *)param1; + if (HAL_EFUSE_Read(efuse->start_bit, efuse->bit_num, efuse->data) != HAL_OK) + return -1; + default: + if (m_wlan_net_sys_cb) { + return m_wlan_net_sys_cb(param0, param1); + } + break; + } + return 0; +} + +int wlan_sys_init(enum wlan_mode mode, ducc_cb_func cb) +{ +#ifndef __CONFIG_ARCH_MEM_PATCH + HAL_PRCM_DisableSys2(); + HAL_PRCM_DisableSys2Power(); + HAL_PRCM_EnableSys2Power(); +#endif + + m_wlan_net_sys_cb = cb; + OS_SemaphoreCreateBinary(&m_ducc_sync_sem); + +#ifndef __CONFIG_ARCH_MEM_PATCH + HAL_PRCM_DisableSys2Isolation(); + HAL_PRCM_ReleaseSys2Reset(); + HAL_UDelay(500); +#endif + + if (wlan_load_net_bin(mode) != 0) { + WLAN_ERR("%s: wlan load net bin failed\n", __func__); + +#ifndef __CONFIG_ARCH_MEM_PATCH + HAL_PRCM_ForceSys2Reset(); + HAL_PRCM_EnableSys2Isolation(); + HAL_PRCM_DisableSys2Power(); + HAL_PRCM_DisableSys2(); +#endif + + return -1; + } + + struct ducc_app_param param = { wlan_sys_callback }; + ducc_app_start(¶m); + + HAL_PRCM_ReleaseCPUNReset(); + OS_SemaphoreWait(&m_ducc_sync_sem, OS_WAIT_FOREVER); + OS_SemaphoreDelete(&m_ducc_sync_sem); + WLAN_DBG("wlan sys init done\n"); + +#ifdef CONFIG_PM + pm_register_ops(WLAN_SYS_DEV); +#endif + + return 0; +} + +int wlan_sys_deinit(void) +{ +#ifdef CONFIG_PM + pm_unregister_ops(WLAN_SYS_DEV); +#endif + + HAL_PRCM_ForceCPUNReset(); + WLAN_DBG("wlan sys deinit done\n"); + + ducc_app_stop(); + m_wlan_net_sys_cb = NULL; + +#ifndef __CONFIG_ARCH_MEM_PATCH + HAL_PRCM_ForceSys2Reset(); + HAL_PRCM_EnableSys2Isolation(); + HAL_PRCM_DisableSys2Power(); + HAL_PRCM_DisableSys2(); +#endif + + return 0; +} + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ diff --git a/platform/mcu/xr871/src/net/wlan/wlan_debug.h b/platform/mcu/xr871/src/net/wlan/wlan_debug.h new file mode 100644 index 0000000000..f44294d0b1 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/wlan_debug.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_WLAN_DEBUG_H_ +#define _NET_WLAN_WLAN_DEBUG_H_ + +#include +#include +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define wlan_malloc(l) malloc(l) +#define wlan_free(p) free(p) +#define wlan_memcpy(d, s, n) memcpy(d, s, n) +#define wlan_memset(s, c, n) memset(s, c, n) +#define wlan_strlen(s) strlen(s) +#define wlan_strlcpy(d, s, n) strlcpy(d, s, n) + +#define WLAN_DBG_ON 0 +#define WLAN_WARN_ON 1 +#define WLAN_ERR_ON 1 +#define WLAN_ABORT_ON 0 + +#define WLAN_SYSLOG printf +#define WLAN_ABORT() sys_abort() + +#define WLAN_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + WLAN_SYSLOG(fmt, ##arg); \ + } while (0) + +#define WLAN_DBG(fmt, arg...) \ + WLAN_LOG(WLAN_DBG_ON, "[wlan] "fmt, ##arg) + +#define WLAN_WARN(fmt, arg...) \ + WLAN_LOG(WLAN_WARN_ON, "[wlan WARN] "fmt, ##arg) + +#define WLAN_ERR(fmt, arg...) \ + do { \ + WLAN_LOG(WLAN_ERR_ON, "[wlan ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (WLAN_ABORT_ON) \ + WLAN_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _NET_WLAN_WLAN_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/net/wlan/wpa_ctrl_req.h b/platform/mcu/xr871/src/net/wlan/wpa_ctrl_req.h new file mode 100644 index 0000000000..12977e8a23 --- /dev/null +++ b/platform/mcu/xr871/src/net/wlan/wpa_ctrl_req.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _NET_WLAN_WPA_CTRL_REQ_H_ +#define _NET_WLAN_WPA_CTRL_REQ_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief WPA control command definition + */ +typedef enum wpa_ctrl_cmd { + /* STA */ + WPA_CTRL_CMD_STA_SCAN, + WPA_CTRL_CMD_STA_SCAN_RESULTS, + WPA_CTRL_CMD_STA_SCAN_INTERVAL, + + WPA_CTRL_CMD_STA_REASSOCIATE, + WPA_CTRL_CMD_STA_REATTACH, + WPA_CTRL_CMD_STA_RECONNECT, + WPA_CTRL_CMD_STA_TERMINATE, + WPA_CTRL_CMD_STA_DISCONNECT, + + WPA_CTRL_CMD_STA_ENABLE, + WPA_CTRL_CMD_STA_DISABLE, + + WPA_CTRL_CMD_STA_SET, + WPA_CTRL_CMD_STA_GET, + WPA_CTRL_CMD_STA_AUTOCONNECT, + + WPA_CTRL_CMD_STA_STATE, + WPA_CTRL_CMD_STA_AP, + + WPA_CTRL_CMD_STA_BSS_EXPIRE_AGE, + WPA_CTRL_CMD_STA_BSS_EXPIRE_COUNT, + WPA_CTRL_CMD_STA_BSS_FLUSH, + + WPA_CTRL_CMD_STA_WPS_PBC, + WPA_CTRL_CMD_STA_WPS_GET_PIN, + WPA_CTRL_CMD_STA_WPS_SET_PIN, + + /* softAP */ + WPA_CTRL_CMD_AP_ENABLE, + WPA_CTRL_CMD_AP_RELOAD, + WPA_CTRL_CMD_AP_DISABLE, + WPA_CTRL_CMD_AP_TERMINATE, + + WPA_CTRL_CMD_AP_SET, + WPA_CTRL_CMD_AP_GET, + WPA_CTRL_CMD_AP_STA_NUM, + WPA_CTRL_CMD_AP_STA_INFO, +} wpa_ctrl_cmd_t; + +int wpa_ctrl_request(wpa_ctrl_cmd_t cmd, void *data); + +#ifdef __cplusplus +} +#endif + +#endif /* _NET_WLAN_WPA_CTRL_REQ_H_ */ diff --git a/platform/mcu/xr871/src/ota/ota.c b/platform/mcu/xr871/src/ota/ota.c new file mode 100644 index 0000000000..674bfa1ade --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota.c @@ -0,0 +1,765 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ota_i.h" +#include "ota_debug.h" +#include "ota_file.h" +#include "ota_http.h" +#include "sys/ota.h" +#include "sys/fdcm.h" +#include "sys/image.h" +#include "driver/chip/hal_crypto.h" +#include "driver/chip/hal_flash.h" +#include "driver/chip/hal_wdg.h" + +static ota_priv_t ota_priv; + +/** + * @brief Initialize the OTA service according to the specified parameters + * @param[in] param Pointer to image_ota_param_t structure + * @retval ota_status_t, OTA_STATUS_OK on success + */ +ota_status_t ota_init(image_ota_param_t *param) +{ + if (param == NULL) { + OTA_ERR("param %p\n", param); + return OTA_STATUS_ERROR; + } + + ota_priv.flash[IMAGE_SEQ_1ST] = param->flash[IMAGE_SEQ_1ST]; + ota_priv.addr[IMAGE_SEQ_1ST] = param->addr[IMAGE_SEQ_1ST]; + ota_priv.flash[IMAGE_SEQ_2ND] = param->flash[IMAGE_SEQ_2ND]; + ota_priv.addr[IMAGE_SEQ_2ND] = param->addr[IMAGE_SEQ_2ND]; + ota_priv.image_size = param->image_size; + ota_priv.boot_size = param->boot_size; + ota_priv.get_size = 0; + + OTA_DBG("%s(), %d, flash_1st %d, addr_1st %#010x, flash_2nd %d, " + "addr_2nd %#010x, image_size %#010x, boot_size %#010x\n", + __func__, __LINE__, + ota_priv.flash[IMAGE_SEQ_1ST], ota_priv.addr[IMAGE_SEQ_1ST], + ota_priv.flash[IMAGE_SEQ_2ND], ota_priv.addr[IMAGE_SEQ_2ND], + ota_priv.image_size, ota_priv.boot_size); + + return OTA_STATUS_OK; +} + +/** + * @brief DeInitialize the OTA service + * @return None + */ +void ota_deinit(void) +{ + ota_priv.flash[IMAGE_SEQ_1ST] = 0; + ota_priv.addr[IMAGE_SEQ_1ST] = IMAGE_INVALID_ADDR; + ota_priv.flash[IMAGE_SEQ_2ND] = 0; + ota_priv.addr[IMAGE_SEQ_2ND] = IMAGE_INVALID_ADDR; + ota_priv.image_size = 0; + ota_priv.boot_size = 0; + ota_priv.get_size = 0; +} + +static ota_status_t ota_read_boot_cfg(ota_boot_cfg_t *boot_cfg) +{ + fdcm_handle_t *fdcm_hdl; + + fdcm_hdl = fdcm_open(ota_priv.flash[IMAGE_SEQ_2ND], ota_priv.addr[IMAGE_SEQ_2ND], ota_priv.boot_size); + if (fdcm_hdl == NULL) { + OTA_ERR("fdcm hdl %p\n", fdcm_hdl); + return OTA_STATUS_ERROR; + } + + if (fdcm_read(fdcm_hdl, boot_cfg, OTA_BOOT_CFG_SIZE) != OTA_BOOT_CFG_SIZE) { + OTA_ERR("fdcm read failed\n"); + fdcm_close(fdcm_hdl); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, boot image %#06x, boot state %#06x\n", + __func__, __LINE__, boot_cfg->boot_image, boot_cfg->boot_state); + + fdcm_close(fdcm_hdl); + return OTA_STATUS_OK; +} + +static ota_status_t ota_write_boot_cfg(ota_boot_cfg_t * boot_cfg) +{ + fdcm_handle_t *fdcm_hdl; + + fdcm_hdl = fdcm_open(ota_priv.flash[IMAGE_SEQ_2ND], ota_priv.addr[IMAGE_SEQ_2ND], ota_priv.boot_size); + if (fdcm_hdl == NULL) { + OTA_ERR("fdcm hdl %p\n", fdcm_hdl); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, boot image %#06x, boot state %#06x\n", + __func__, __LINE__, boot_cfg->boot_image, boot_cfg->boot_state); + + if (fdcm_write(fdcm_hdl, boot_cfg, OTA_BOOT_CFG_SIZE) != OTA_BOOT_CFG_SIZE) { + OTA_ERR("fdcm write failed\n"); + fdcm_close(fdcm_hdl); + return OTA_STATUS_ERROR; + } + + fdcm_close(fdcm_hdl); + return OTA_STATUS_OK; +} + +/** + * @brief Get the OTA configuration + * @param[in] cfg Pointer to OTA configuration + * @retval ota_status_t, OTA_STATUS_OK on success + */ +ota_status_t ota_read_cfg(ota_cfg_t *cfg) +{ + ota_boot_cfg_t boot_cfg; + + if ((cfg == NULL) + || (ota_priv.boot_size == 0) + || (ota_priv.addr[IMAGE_SEQ_2ND] == IMAGE_INVALID_ADDR)) { + OTA_ERR("cfg %p, boot size %#010x, addr 2nd %#010x\n", + cfg, ota_priv.boot_size, ota_priv.addr[IMAGE_SEQ_2ND]); + return OTA_STATUS_ERROR; + } + + if (ota_read_boot_cfg(&boot_cfg) != OTA_STATUS_OK) { + OTA_ERR("read boot cfg failed\n"); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, boot image %#06x, boot state %#06x\n", + __func__, __LINE__, boot_cfg.boot_image, boot_cfg.boot_state); + + if (boot_cfg.boot_image == OTA_BOOT_IMAGE_1ST) { + cfg->image = OTA_IMAGE_1ST; + } else if (boot_cfg.boot_image == OTA_BOOT_IMAGE_2ND) { + cfg->image = OTA_IMAGE_2ND; + } else { + OTA_ERR("boot image %#06x\n", boot_cfg.boot_image); + return OTA_STATUS_ERROR; + } + + if (boot_cfg.boot_state == OTA_BOOT_STATE_UNVERIFIED) { + cfg->state = OTA_STATE_UNVERIFIED; + } else if (boot_cfg.boot_state == OTA_BOOT_STATE_VERIFIED) { + cfg->state = OTA_STATE_VERIFIED; + } else { + OTA_ERR("boot state %#06x\n", boot_cfg.boot_state); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, image %d, state %d\n", __func__, __LINE__, cfg->image, cfg->state); + + return OTA_STATUS_OK; +} + +/** + * @brief Set the OTA configuration + * @param[in] cfg Pointer to OTA configuration + * @retval ota_status_t, OTA_STATUS_OK on success + */ +ota_status_t ota_write_cfg(ota_cfg_t *cfg) +{ + ota_boot_cfg_t boot_cfg; + + if ((cfg == NULL) + || (ota_priv.boot_size == 0) + || (ota_priv.addr[IMAGE_SEQ_2ND] == IMAGE_INVALID_ADDR)) { + OTA_ERR("cfg %p, boot size %#010x, addr 2nd %#010x\n", + cfg, ota_priv.boot_size, ota_priv.addr[IMAGE_SEQ_2ND]); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, image %d, state %d\n", __func__, __LINE__, cfg->image, cfg->state); + + if (cfg->image == OTA_IMAGE_1ST) { + boot_cfg.boot_image = OTA_BOOT_IMAGE_1ST; + } else if (cfg->image == OTA_IMAGE_2ND) { + boot_cfg.boot_image = OTA_BOOT_IMAGE_2ND; + } else { + OTA_ERR("image %d\n", cfg->image); + return OTA_STATUS_ERROR; + } + + if (cfg->state == OTA_STATE_UNVERIFIED) { + boot_cfg.boot_state= OTA_BOOT_STATE_UNVERIFIED; + } else if (cfg->state == OTA_STATE_VERIFIED) { + boot_cfg.boot_state = OTA_BOOT_STATE_VERIFIED; + } else { + OTA_ERR("tate %d\n", cfg->state); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, boot image %#06x, boot state %#06x\n", + __func__, __LINE__, boot_cfg.boot_image, boot_cfg.boot_state); + + if (ota_write_boot_cfg(&boot_cfg) != OTA_STATUS_OK) { + OTA_ERR("write boot cfg failed\n"); + return OTA_STATUS_ERROR; + } + + return OTA_STATUS_OK; +} + +static ota_status_t ota_erase_flash(uint32_t flash, uint32_t addr, uint32_t size) +{ + uint32_t start; + uint32_t multiples; + FlashEraseMode erase_size; + HAL_Status status; + + OTA_DBG("%s(), %d, flash %d, addr %#010x, size %#010x\n", + __func__, __LINE__, flash, addr, size); + + if ((size >= (64 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_64KB, addr, &start) == HAL_OK) + && (addr == start) + && ((size & 0xFFFF) == 0)) { + multiples = size / (64 << 10); + erase_size = FLASH_ERASE_64KB; + } else if ((size >= (32 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_32KB, addr, &start) == HAL_OK) + && (addr == start) + && ((size & 0x7FFF) == 0)) { + multiples = size / (32 << 10); + erase_size = FLASH_ERASE_32KB; + } else if ((size >= (4 << 10)) + && (HAL_Flash_MemoryOf(flash, FLASH_ERASE_4KB, addr, &start) == HAL_OK) + && (addr == start) + && ((size & 0xFFF) == 0)) { + multiples = size / (4 << 10); + erase_size = FLASH_ERASE_4KB; + } else { + OTA_ERR("flash %d, addr %#010x, size %#010x\n", flash, addr, size); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, erase size %#010x, multiples %d\n", + __func__, __LINE__, erase_size, multiples); + + if (HAL_Flash_Open(flash, OTA_FLASH_TIMEOUT) != HAL_OK) { + OTA_ERR("flash %d\n", flash); + return OTA_STATUS_ERROR; + } + + status = HAL_Flash_Erase(flash, erase_size, addr, multiples); + if (status != HAL_OK) { + OTA_ERR("status %d\n", status); + HAL_Flash_Close(flash); + return OTA_STATUS_ERROR; + } + + HAL_Flash_Close(flash); + return OTA_STATUS_OK; +} + +static ota_status_t ota_update_image_process(image_seq_t seq, void *url, + ota_update_init_t init_cb, + ota_update_get_t get_cb) +{ + ota_status_t status; + uint32_t flash; + uint32_t addr; + uint32_t boot_size; + uint32_t recv_size; + uint32_t image_size; + uint8_t *ota_buf; + uint8_t eof_flag; + uint8_t cnt; + + flash = ota_priv.flash[seq]; + addr = ota_priv.addr[seq] + ota_priv.boot_size; + + OTA_DBG("%s(), %d, seq %d, flash %d, addr %#010x\n", __func__, __LINE__, seq, flash, addr); + OTA_SYSLOG("OTA: erase flash...\n"); + + if (ota_erase_flash(flash, addr, ota_priv.image_size - ota_priv.boot_size) != OTA_STATUS_OK) { + OTA_ERR("flash %d, addr %#010x, image size %#010x\n", flash, addr, ota_priv.image_size); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, erase flash success\n", __func__, __LINE__); + + if (init_cb(url) != OTA_STATUS_OK) { + OTA_ERR("ota update init failed\n"); + return OTA_STATUS_ERROR; + } + + ota_buf = ota_malloc(OTA_BUF_SIZE); + if (ota_buf == NULL) { + OTA_ERR("ota buf %p\n", ota_buf); + return OTA_STATUS_ERROR; + } + + OTA_SYSLOG("OTA: start loading image...\n"); + cnt = 0; + + ota_priv.get_size = 0; + boot_size = ota_priv.boot_size; + while (boot_size > 0) { + if (boot_size > OTA_BUF_SIZE) + status = get_cb(ota_buf, OTA_BUF_SIZE, &recv_size, &eof_flag); + else + status = get_cb(ota_buf, boot_size, &recv_size, &eof_flag); + + if ((status != OTA_STATUS_OK) || eof_flag) { + OTA_ERR("status %d, eof %d\n", status, eof_flag); + ota_free(ota_buf); + return OTA_STATUS_ERROR; + } + boot_size -= recv_size; + ota_priv.get_size += recv_size; + + cnt++; + if (cnt == 100) { + OTA_SYSLOG("OTA: loading image(%#010x)...\n", ota_priv.get_size); + cnt = 0; + } + } + + OTA_DBG("%s(), %d, load bootloader success\n", __func__, __LINE__); + + if (HAL_Flash_Open(flash, OTA_FLASH_TIMEOUT) != HAL_OK) { + OTA_ERR("flash %d\n", flash); + ota_free(ota_buf); + return OTA_STATUS_ERROR; + } + + image_size = ota_priv.image_size; + while (image_size > 0) { + if (image_size > OTA_BUF_SIZE) + status = get_cb(ota_buf, OTA_BUF_SIZE, &recv_size, &eof_flag); + else + status = get_cb(ota_buf, image_size, &recv_size, &eof_flag); + + if (status != OTA_STATUS_OK) { + OTA_ERR("status %d\n", status); + HAL_Flash_Close(flash); + ota_free(ota_buf); + return OTA_STATUS_ERROR; + } + image_size -= recv_size; + ota_priv.get_size += recv_size; + + if (HAL_Flash_Write(flash, addr, ota_buf, recv_size) != HAL_OK) { + OTA_ERR("flash %d, addr %#010x, size %#010x\n", flash, addr, recv_size); + HAL_Flash_Close(flash); + ota_free(ota_buf); + return OTA_STATUS_ERROR; + } + addr += recv_size; + if (eof_flag) + break; + + cnt++; + if (cnt == 100) { + OTA_SYSLOG("OTA: loading image(%#010x)...\n", ota_priv.get_size); + cnt = 0; + } + } + + HAL_Flash_Close(flash); + ota_free(ota_buf); + + OTA_SYSLOG("OTA: finish loading image(%#010x).\n", ota_priv.get_size); + + if (image_check_sections(seq) != IMAGE_VALID) { + OTA_ERR("ota check image failed\n"); + return OTA_STATUS_ERROR; + } + + OTA_SYSLOG("OTA: finish checking image.\n"); + return OTA_STATUS_OK; +} + +static ota_status_t ota_update_image(void *url, + ota_update_init_t init_cb, + ota_update_get_t get_cb) +{ + ota_boot_cfg_t boot_cfg; + image_seq_t seq; + + if ((ota_priv.image_size == 0) || (ota_priv.boot_size == 0)) { + OTA_ERR("need to init, image size %#010x, boot size %#010x\n", + ota_priv.image_size, ota_priv.boot_size); + return OTA_STATUS_ERROR; + } + + if (ota_read_boot_cfg(&boot_cfg) != OTA_STATUS_OK) { + OTA_ERR("read boot cfg failed\n"); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, boot image %#06x, boot state %#06x\n", + __func__, __LINE__, boot_cfg.boot_image, boot_cfg.boot_state); + + if (((boot_cfg.boot_image == OTA_BOOT_IMAGE_1ST) && (boot_cfg.boot_state == OTA_BOOT_STATE_UNVERIFIED)) + || ((boot_cfg.boot_image == OTA_BOOT_IMAGE_2ND) && (boot_cfg.boot_state == OTA_BOOT_STATE_VERIFIED))) { + seq = IMAGE_SEQ_1ST; + boot_cfg.boot_image = OTA_BOOT_IMAGE_1ST; + } else if (((boot_cfg.boot_image == OTA_BOOT_IMAGE_1ST) && (boot_cfg.boot_state == OTA_BOOT_STATE_VERIFIED)) + || ((boot_cfg.boot_image == OTA_BOOT_IMAGE_2ND) && (boot_cfg.boot_state == OTA_BOOT_STATE_UNVERIFIED))) { + seq = IMAGE_SEQ_2ND; + boot_cfg.boot_image = OTA_BOOT_IMAGE_2ND; + } else { + OTA_ERR("image %#06x, state %#06x\n", boot_cfg.boot_image, boot_cfg.boot_state); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, seq %d\n", __func__, __LINE__, seq); + + if (ota_update_image_process(seq, url, init_cb, get_cb) != OTA_STATUS_OK) { + OTA_ERR("ota update image failed\n"); + return OTA_STATUS_ERROR; + } + + boot_cfg.boot_state = OTA_BOOT_STATE_UNVERIFIED; + return ota_write_boot_cfg(&boot_cfg); +} + +/** + * @brief Get the image file with the specified protocol and write to flash + * @param[in] protocol Pointer to the protocol of getting image file + * @param[in] url URL of the image file + * @retval ota_status_t, OTA_STATUS_OK on success + */ +ota_status_t ota_get_image(ota_protocol_t protocol, void *url) +{ + if (url == NULL) { + OTA_ERR("url %p\n", url); + return OTA_STATUS_ERROR; + } + + switch (protocol) { + case OTA_PROTOCOL_FILE: + return ota_update_image(url, ota_update_file_init, ota_update_file_get); + case OTA_PROTOCOL_HTTP: + return ota_update_image(url, ota_update_http_init, ota_update_http_get); + default: + OTA_ERR("invalid protocol %d\n", protocol); + return OTA_STATUS_ERROR; + } +} + +static ota_status_t ota_verify_image_append_process(uint32_t flash, + uint32_t addr, + uint32_t size, + ota_verify_append_t append, + void *hdl) +{ + uint32_t read_size; + uint8_t *buf; + + buf = ota_malloc(OTA_BUF_SIZE); + if (buf == NULL) { + OTA_ERR("buf %p\n", buf); + return OTA_STATUS_ERROR; + } + + if (HAL_Flash_Open(flash, OTA_FLASH_TIMEOUT) != HAL_OK) { + OTA_ERR("flash %d\n", flash); + ota_free(buf); + return OTA_STATUS_ERROR; + } + + while (size > 0) { + read_size = size > OTA_BUF_SIZE ? OTA_BUF_SIZE : size; + if ((HAL_Flash_Read(flash, addr, buf, read_size) != HAL_OK) + || (append(hdl, buf, read_size) != HAL_OK)) { + OTA_ERR("flash %d, addr %#010x, size %#010x\n", flash, addr, read_size); + HAL_Flash_Close(flash); + ota_free(buf); + return OTA_STATUS_ERROR; + } + size -= read_size; + addr += read_size; + } + + HAL_Flash_Close(flash); + ota_free(buf); + return OTA_STATUS_OK; +} + +static ota_status_t ota_verify_image_append(ota_boot_cfg_t *cfg, + ota_verify_append_t append, + void *hdl) +{ + image_seq_t seq; + + if (cfg->boot_image == OTA_BOOT_IMAGE_1ST) { + seq = IMAGE_SEQ_1ST; + } else if (cfg->boot_image == OTA_BOOT_IMAGE_2ND) { + seq = IMAGE_SEQ_2ND; + } else { + OTA_ERR("invalid boot image %#06x\n", cfg->boot_image); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, image %#06x, seq %d\n", __func__, __LINE__, cfg->boot_image, seq); + + if ((ota_verify_image_append_process(ota_priv.flash[IMAGE_SEQ_1ST], + ota_priv.addr[IMAGE_SEQ_1ST], + ota_priv.boot_size, + append, + hdl) != OTA_STATUS_OK) + || (ota_verify_image_append_process(ota_priv.flash[seq], + ota_priv.addr[seq] + ota_priv.boot_size, + ota_priv.get_size - ota_priv.boot_size, + append, + hdl) != OTA_STATUS_OK)) { + OTA_ERR("append failed, seq %d\n", seq); + return OTA_STATUS_ERROR; + } + + return OTA_STATUS_OK; +} + +static inline ota_status_t ota_verify_image_none(ota_boot_cfg_t *cfg, uint32_t *value) +{ + cfg->boot_state = OTA_BOOT_STATE_VERIFIED; + return OTA_STATUS_OK; +} + +static ota_status_t ota_verify_image_crc32(ota_boot_cfg_t *cfg, uint32_t *value) +{ + CE_CRC_Handler hdl; + uint32_t crc; + + if (HAL_CRC_Init(&hdl, CE_CRC32, ota_priv.get_size) != HAL_OK) { + OTA_ERR("CRC init failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_verify_image_append(cfg, + (ota_verify_append_t)HAL_CRC_Append, + (void *)&hdl) != OTA_STATUS_OK) { + OTA_ERR("CRC append failed\n"); + return OTA_STATUS_ERROR; + } + + if (HAL_CRC_Finish(&hdl, &crc) != HAL_OK) { + OTA_ERR("CRC finish failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_memcmp(value, &crc, sizeof(crc)) == 0) { + cfg->boot_state = OTA_BOOT_STATE_VERIFIED; + } else { + OTA_WARN("%s(), %d, value %#010x, crc %#010x\n", + __func__, __LINE__, *value, crc); + cfg->boot_state = OTA_BOOT_STATE_UNVERIFIED; + } + + OTA_DBG("%s(), %d, state %#06x, value %#010x, crc %#010x\n", + __func__, __LINE__, cfg->boot_state, *value, crc); + + return OTA_STATUS_OK; +} + +static ota_status_t ota_verify_image_md5(ota_boot_cfg_t *cfg, uint32_t *value) +{ + CE_MD5_Handler hdl; + uint32_t digest[4]; + + if (HAL_MD5_Init(&hdl, CE_CTL_IVMODE_SHA_MD5_FIPS180, NULL) != HAL_OK) { + OTA_ERR("MD5 init failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_verify_image_append(cfg, + (ota_verify_append_t)HAL_MD5_Append, + (void *)&hdl) != OTA_STATUS_OK) { + OTA_ERR("MD5 append failed\n"); + return OTA_STATUS_ERROR; + } + + if (HAL_MD5_Finish(&hdl, digest) != HAL_OK) { + OTA_ERR("MD5 finish failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_memcmp(value, digest, sizeof(digest)) == 0) { + cfg->boot_state = OTA_BOOT_STATE_VERIFIED; + } else { + OTA_WARN("%s(), %d, value[0] %#010x, digest[0] %#010x\n", + __func__, __LINE__, value[0], digest[0]); + cfg->boot_state = OTA_BOOT_STATE_UNVERIFIED; + } + + OTA_DBG("%s(), %d, state %#06x, value[0] %#010x, digest[0] %#010x\n", + __func__, __LINE__, cfg->boot_state, value[0], digest[0]); + + return OTA_STATUS_OK; +} + +static ota_status_t ota_verify_image_sha1(ota_boot_cfg_t *cfg, uint32_t *value) +{ + CE_SHA1_Handler hdl; + uint32_t digest[5]; + + if (HAL_SHA1_Init(&hdl, CE_CTL_IVMODE_SHA_MD5_FIPS180, NULL) != HAL_OK) { + OTA_ERR("SHA1 init failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_verify_image_append(cfg, + (ota_verify_append_t)HAL_SHA1_Append, + (void *)&hdl) != OTA_STATUS_OK) { + OTA_ERR("SHA1 append failed\n"); + return OTA_STATUS_ERROR; + } + + if (HAL_SHA1_Finish(&hdl, digest) != HAL_OK) { + OTA_ERR("SHA1 finish failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_memcmp(value, digest, sizeof(digest)) == 0) { + cfg->boot_state = OTA_BOOT_STATE_VERIFIED; + } else { + OTA_WARN("%s(), %d, value[0] %#010x, digest[0] %#010x\n", + __func__, __LINE__, value[0], digest[0]); + cfg->boot_state = OTA_BOOT_STATE_UNVERIFIED; + } + + OTA_DBG("%s(), %d, state %#06x, value[0] %#010x, digest[0] %#010x\n", + __func__, __LINE__, cfg->boot_state, value[0], digest[0]); + + return OTA_STATUS_OK; +} + +static ota_status_t ota_verify_image_sha256(ota_boot_cfg_t *cfg, uint32_t *value) +{ + CE_SHA256_Handler hdl; + uint32_t digest[8]; + + if (HAL_SHA256_Init(&hdl, CE_CTL_IVMODE_SHA_MD5_FIPS180, NULL) != HAL_OK) { + OTA_ERR("SHA256 init failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_verify_image_append(cfg, + (ota_verify_append_t)HAL_SHA256_Append, + (void *)&hdl) != OTA_STATUS_OK) { + OTA_ERR("SHA256 append failed\n"); + return OTA_STATUS_ERROR; + } + + if (HAL_SHA256_Finish(&hdl, digest) != HAL_OK) { + OTA_ERR("SHA256 finish failed\n"); + return OTA_STATUS_ERROR; + } + + if (ota_memcmp(value, digest, sizeof(digest)) == 0) { + cfg->boot_state = OTA_BOOT_STATE_VERIFIED; + } else { + OTA_WARN("%s(), %d, value[0] %#010x, digest[0] %#010x\n", + __func__, __LINE__, value[0], digest[0]); + cfg->boot_state = OTA_BOOT_STATE_UNVERIFIED; + } + + OTA_DBG("%s(), %d, state %#06x, value[0] %#010x, digest[0] %#010x\n", + __func__, __LINE__, cfg->boot_state, value[0], digest[0]); + + return OTA_STATUS_OK; +} + +/** + * @brief Verify the image file and modify OTA configuration correspondingly + * @param[in] verify Verification algorithm + * @param[in] value Pointer to standard value of the verification algorithm + * @retval ota_status_t, OTA_STATUS_OK on success + */ +ota_status_t ota_verify_image(ota_verify_t verify, uint32_t *value) +{ + ota_boot_cfg_t boot_cfg; + ota_status_t status; + + if ((verify != OTA_VERIFY_NONE) && (value == NULL)) { + OTA_ERR("verify %d, res %p\n", verify, value); + return OTA_STATUS_ERROR; + } + + if (ota_priv.get_size == 0) { + OTA_ERR("need to get image, get size %#010x\n", ota_priv.get_size); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, verify %d, get size %#010x\n", + __func__, __LINE__, verify, ota_priv.get_size); + + if (ota_read_boot_cfg(&boot_cfg) != OTA_STATUS_OK) { + OTA_ERR("read boot cfg failed\n"); + return OTA_STATUS_ERROR; + } + + switch (verify) { + case OTA_VERIFY_NONE: + status = ota_verify_image_none(&boot_cfg, value); + break; + case OTA_VERIFY_CRC32: + status = ota_verify_image_crc32(&boot_cfg, value); + break; + case OTA_VERIFY_MD5: + status = ota_verify_image_md5(&boot_cfg, value); + break; + case OTA_VERIFY_SHA1: + status = ota_verify_image_sha1(&boot_cfg, value); + break; + case OTA_VERIFY_SHA256: + status = ota_verify_image_sha256(&boot_cfg, value); + break; + default: + OTA_ERR("invalid verify %d\n", verify); + return OTA_STATUS_ERROR; + } + + if (status != OTA_STATUS_OK) { + OTA_ERR("status %d, verify %d\n", status, verify); + return OTA_STATUS_ERROR; + } + + return ota_write_boot_cfg(&boot_cfg); +} + +/** + * @brief Reboot system + * @return None + */ +void ota_reboot_system(void) +{ + OTA_DBG("%s(), %d, OTA: reboot.\n", __func__, __LINE__); + HAL_WDG_Reboot(); +} + +void ota_set_size(uint32_t size) +{ + ota_priv.get_size = size; + +} diff --git a/platform/mcu/xr871/src/ota/ota.mk b/platform/mcu/xr871/src/ota/ota.mk new file mode 100644 index 0000000000..d0d5ec0b51 --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota.mk @@ -0,0 +1,6 @@ +NAME := ota + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := ota.c \ + ota_file.c \ + ota_http.c diff --git a/platform/mcu/xr871/src/ota/ota_debug.h b/platform/mcu/xr871/src/ota/ota_debug.h new file mode 100644 index 0000000000..d87fd727db --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota_debug.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _OTA_DEBUG_H_ +#define _OTA_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define OTA_DBG_ON 0 +#define OTA_WARN_ON 1 +#define OTA_ERR_ON 1 +#define OTA_ABORT_ON 0 + +#define OTA_SYSLOG printf +#define OTA_ABORT() sys_abort() + +#define OTA_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + OTA_SYSLOG(fmt, ##arg); \ + } while (0) + +#define OTA_DBG(fmt, arg...) OTA_LOG(OTA_DBG_ON, "[OTA] "fmt, ##arg) +#define OTA_WARN(fmt, arg...) OTA_LOG(OTA_WARN_ON, "[OTA WARN] "fmt, ##arg) +#define OTA_ERR(fmt, arg...) \ + do { \ + OTA_LOG(OTA_ERR_ON, "[OTA ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (OTA_ABORT_ON) \ + OTA_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _OTA_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/ota/ota_file.c b/platform/mcu/xr871/src/ota/ota_file.c new file mode 100644 index 0000000000..4d5948189b --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota_file.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "ota_i.h" +#include "ota_debug.h" +#include "ota_file.h" +#include "ff.h" + +typedef struct ota_fs_param { + char *url; + FRESULT res; + FIL file; +} ota_fs_param_t; + +static ota_fs_param_t g_fs_param; + +ota_status_t ota_update_file_init(void *url) +{ + g_fs_param.url = strdup((char *)url + 7); + + g_fs_param.res = f_open(&g_fs_param.file, g_fs_param.url, FA_READ | FA_OPEN_EXISTING); + if (g_fs_param.res != FR_OK) { + OTA_ERR("open res %d\n", g_fs_param.res); + return OTA_STATUS_ERROR; + } + + OTA_DBG("%s(), %d, open success\n", __func__, __LINE__); + + return OTA_STATUS_OK; +} + +ota_status_t ota_update_file_get(uint8_t *buf, uint32_t buf_size, uint32_t *recv_size, uint8_t *eof_flag) +{ + g_fs_param.res = f_read(&g_fs_param.file, buf, buf_size, recv_size); + if (g_fs_param.res != FR_OK) { + OTA_ERR("read res %d\n", g_fs_param.res); + return OTA_STATUS_ERROR; + } + + if (*recv_size < buf_size) { + *eof_flag = 1; + f_close(&g_fs_param.file); + } else + *eof_flag = 0; + + return OTA_STATUS_OK; +} + diff --git a/platform/mcu/xr871/src/ota/ota_file.h b/platform/mcu/xr871/src/ota/ota_file.h new file mode 100644 index 0000000000..57d9d83c4f --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota_file.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _OTA_FILE_H_ +#define _OTA_FILE_H_ + +#include "types.h" +#include "sys/ota.h" + +#ifdef __cplusplus +extern "C" { +#endif + +ota_status_t ota_update_file_init(void *url); +ota_status_t ota_update_file_get(uint8_t *buf, uint32_t buf_size, uint32_t *recv_size, uint8_t *eof_flag); + +#ifdef __cplusplus +} +#endif + +#endif /* _OTA_FILE_H_ */ diff --git a/platform/mcu/xr871/src/ota/ota_http.c b/platform/mcu/xr871/src/ota/ota_http.c new file mode 100644 index 0000000000..a3bf609848 --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota_http.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "ota_i.h" +#include "ota_debug.h" +#include "ota_http.h" +//TODO: #include "net/HTTPClient/HTTPCUsr_api.h" + +//TODO: static HTTPParameters g_http_param; + +ota_status_t ota_update_http_init(void *url) +{ +//TODO: ota_memset(&g_http_param, 0, sizeof(g_http_param)); +//TODO: ota_memcpy(g_http_param.Uri, url, strlen(url)); + + return OTA_STATUS_OK; +} + +ota_status_t ota_update_http_get(uint8_t *buf, uint32_t buf_size, uint32_t *recv_size, uint8_t *eof_flag) +{ +//TODO: int ret; +//TODO: +//TODO: ret = HTTPC_get(&g_http_param, (CHAR *)buf, (INT32)buf_size, (INT32 *)recv_size); +//TODO: if (ret == HTTP_CLIENT_SUCCESS) { +//TODO: *eof_flag = 0; +//TODO: return OTA_STATUS_OK; +//TODO: } else if (ret == HTTP_CLIENT_EOS) { +//TODO: *eof_flag = 1; +//TODO: return OTA_STATUS_OK; +//TODO: } else { +//TODO: OTA_ERR("ret %d\n", ret); +//TODO: return OTA_STATUS_ERROR; +//TODO: } + return OTA_STATUS_ERROR; +} + diff --git a/platform/mcu/xr871/src/ota/ota_http.h b/platform/mcu/xr871/src/ota/ota_http.h new file mode 100644 index 0000000000..c3b25988a2 --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota_http.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _OTA_HTTP_H_ +#define _OTA_HTTP_H_ + +#include "types.h" +#include "sys/ota.h" + +#ifdef __cplusplus +extern "C" { +#endif + +ota_status_t ota_update_http_init(void *url); +ota_status_t ota_update_http_get(uint8_t *buf, uint32_t buf_size, uint32_t *recv_size, uint8_t *eof_flag); + +#ifdef __cplusplus +} +#endif + +#endif /* _OTA_HTTP_H_ */ diff --git a/platform/mcu/xr871/src/ota/ota_i.h b/platform/mcu/xr871/src/ota/ota_i.h new file mode 100644 index 0000000000..744f4def0f --- /dev/null +++ b/platform/mcu/xr871/src/ota/ota_i.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _OTA_I_H_ +#define _OTA_I_H_ + +#include +#include "types.h" +#include "sys/ota.h" +#include "driver/chip/hal_crypto.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ota_malloc(l) malloc(l) +#define ota_free(p) free(p) +#define ota_memcpy(d, s, n) memcpy(d, s, n) +#define ota_memset(s, c, n) memset(s, c, n) +#define ota_memcmp(a, b, l) memcmp(a, b, l) + +#define OTA_BUF_SIZE (2 << 10) +#define OTA_FLASH_TIMEOUT (5000) + +#define OTA_BOOT_IMAGE_1ST (0x5555) +#define OTA_BOOT_IMAGE_2ND (0xAAAA) +#define OTA_BOOT_STATE_UNVERIFIED (0x6996) +#define OTA_BOOT_STATE_VERIFIED (0x9669) + +typedef struct { + uint16_t boot_image; + uint16_t boot_state; +} ota_boot_cfg_t; + +#define OTA_BOOT_CFG_SIZE sizeof(ota_boot_cfg_t) + +typedef struct { + uint32_t flash[IMAGE_SEQ_NUM]; + uint32_t addr[IMAGE_SEQ_NUM]; + uint32_t image_size; + uint32_t boot_size; + uint32_t get_size; +} ota_priv_t; + +typedef ota_status_t (*ota_update_init_t)(void *url); +typedef ota_status_t (*ota_update_get_t)(uint8_t *buf, uint32_t buf_size, uint32_t *recv_size, uint8_t *eof_flag); + +typedef HAL_Status (*ota_verify_append_t)(void *hdl, uint8_t *data, uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* _OTA_I_H_ */ diff --git a/platform/mcu/xr871/src/pm/pm.c b/platform/mcu/xr871/src/pm/pm.c new file mode 100644 index 0000000000..c8b5762d6e --- /dev/null +++ b/platform/mcu/xr871/src/pm/pm.c @@ -0,0 +1,1058 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "stdlib.h" + +#include "sys/io.h" +#include "errno.h" +#include "sys/list.h" +#include "sys/interrupt.h" +#include "sys/param.h" +#include "kernel/os/os_thread.h" + +#include "driver/chip/system_chip.h" +#include "driver/chip/chip.h" +#include "driver/chip/hal_wakeup.h" +#include "driver/chip/hal_prcm.h" +#include "driver/chip/hal_ccm.h" +#include "driver/chip/hal_util.h" + +#include "pm/pm.h" +#include "pm_i.h" +#include "port.h" + +#ifdef CONFIG_PM + +typedef enum { + PM_SHUTDOWN = 0, + PM_REBOOT = 1, +} pm_operate_t; + +#define nop() __NOP() +#define isb() __ISB() +#define dsb() __DSB() +#define dmb() __DMB() +#define wfi() __WFI() +#define wfe() __WFE() + +#define PM_SYS "appos" +#define PM_SetCPUBootFlag(f) HAL_PRCM_SetCPUABootFlag(f) +#define PM_SetCPUBootArg(a) HAL_PRCM_SetCPUABootArg(a) +#define PM_SystemDeinit() SystemDeInit(SYSTEM_DEINIT_FLAG_RESET_CLK) +#define pm_udelay(us) HAL_UDelay(us) + +static struct arm_CMX_core_regs vault_arm_registers; +#define __set_last_record_step(s) HAL_PRCM_SetCPUAPrivateData(s) +#define __get_last_record_step() HAL_PRCM_GetCPUAPrivateData() + +static const char *const pm_states[PM_MODE_MAX] = { + [PM_MODE_ON] = "on", + [PM_MODE_SLEEP] = "sleep", + [PM_MODE_STANDBY] = "standby", + [PM_MODE_HIBERNATION] = "hibernation", + [PM_MODE_POWEROFF] = "poweroff", +}; + +static int __suspend_begin(enum suspend_state_t state) +{ + /* set SEVONPEND flag */ + if (state < PM_MODE_POWEROFF) { + SCB->SCR = 0x10; + } else { + SCB->SCR = 0x14; + } + return 0; +} + +static inline void __record_dbg_status(int val) +{ + __set_last_record_step(val); + dsb(); + isb(); +} + +/* power off whole system, save user data to flash before call this func. + * BE SUURE: all hardware has been closed and it's prcm config setted to default value. + * @type:0:shutdown, 1:reboot */ +static void pm_power_off(pm_operate_t type) +{ + __record_dbg_status(PM_POWEROFF | 0); + + if (type == PM_REBOOT) { + NVIC_SystemReset(); /* never return */ + } + +#ifdef __CONFIG_ARCH_APP_CORE + /* step 1 & 2 has been done when wlan sys poweroff */ + /* step3: writel(0x0f, GPRCM_SYS1_WAKEUP_CTRL) to tell PMU that turn on + * SW1, SW2, SRSW1, LDO before release application system reset signal. */ + HAL_PRCM_SetSys1WakeupPowerFlags(0x0f); + __record_dbg_status(PM_POWEROFF | 5); + + /* step4: writel(0x0f, GPRCM_SYS1_SLEEP_CTRL) to tell PMU that turn off SW1, + * SW3 SRSW1, LDO after pull down application system reset signal. */ + HAL_PRCM_SetSys1SleepPowerFlags(0x0f); + __record_dbg_status(PM_POWEROFF | 7); + + /* step5: switch to HOSC, close SYS1_CLK. */ + PM_SystemDeinit(); + __record_dbg_status(PM_POWEROFF | 9); + + /* step6: set nvic deepsleep flag, and enter wfe. */ + PM_SetCPUBootFlag(0); + + __disable_fault_irq(); + __disable_irq(); + + while (1) { + wfe(); + } + __record_dbg_status(PM_POWEROFF | 0x0ff); + +#else /* net cpu */ + /* check wifi is closed by app? */ + PM_WARN_ON(HAL_PRCM_IsSys3Release()); + + /* step1: cpu to switch to HOSC */ + HAL_PRCM_SetCPUNClk(PRCM_CPU_CLK_SRC_HFCLK, PRCM_SYS_CLK_FACTOR_80M); + __record_dbg_status(PM_POWEROFF | 1); + + /* step2: turn off SYSCLK2. */ + HAL_PRCM_DisableSysClk2(PRCM_SYS_CLK_FACTOR_80M); + __record_dbg_status(PM_POWEROFF | 3); + PM_SystemDeinit(); + + /* step3: enter WFI state */ + arch_suspend_disable_irqs(); + while (1) + wfi(); + __record_dbg_status(PM_POWEROFF | 0x0ff); +#endif +} + +static void __suspend_enter(enum suspend_state_t state) +{ + __record_dbg_status(PM_SUSPEND_ENTER | 5); + + if (HAL_Wakeup_SetSrc()) + return ; + + debug_jtag_deinit(); + __record_dbg_status(PM_SUSPEND_ENTER | 6); + + PM_LOGN("device info. rst:%x clk:%x\n", CCM->BUS_PERIPH_RST_CTRL, + CCM->BUS_PERIPH_CLK_CTRL); /* debug info. */ + + PM_SetCPUBootArg((uint32_t)&vault_arm_registers); + + if (state == PM_MODE_POWEROFF) { +#ifdef __CONFIG_ARCH_APP_CORE + HAL_Wakeup_SetIOHold((1 << WAKEUP_IO_MAX) - 1); +#endif + pm_power_off(PM_SHUTDOWN); /* never return */ + } else if (state < PM_MODE_STANDBY) { + /* TODO: set system bus to low freq */ + __cpu_sleep(state); + /* TODO: restore system bus to normal freq */ + } else { + __cpu_suspend(state); + } + + PM_BUG_ON(!arch_irq_get_flags()); + + debug_jtag_init(); + + HAL_Wakeup_ClrSrc(); +} + +static void __suspend_end(enum suspend_state_t state) +{ + /* clear SEVONPEND flag */ + SCB->SCR = 0x0; +} + +static const struct platform_suspend_ops suspend_ops = +{ + .begin = __suspend_begin, + .prepare = platform_prepare, + .enter = __suspend_enter, + .wake = platform_wake, + .end = __suspend_end, +}; + +static volatile int user_sel_power_mode = PM_MODE_ON; + +static int valid_state(enum suspend_state_t state) +{ + if (user_sel_power_mode == PM_MODE_ON) + return 0; + + return (user_sel_power_mode == state); +} + +#ifdef CONFIG_PM_DEBUG +static int pm_test_level = TEST_NONE; + +static unsigned long suspend_test_start_time; + +static void suspend_test_start(void) +{ + suspend_test_start_time = ktime_get(); +} + +static void suspend_test_finish(const char *label) +{ + long nj = ktime_get() - suspend_test_start_time; + unsigned msec; + + msec = ktime_to_msecs(abs(nj)); + PM_LOGN("%s took %d ms\n", label, msec); +} + +static int suspend_test(int level) +{ + if (pm_test_level == level) { + PM_LOGD("suspend debug:%d Return.\n", level); + return 1; + } + return 0; +} + +/** + * @brief Set suspend test level. + * @param level: + * @arg level->Suspend will exit when run up to setted level. + */ +void pm_set_test_level(enum suspend_test_level_t level) +{ + pm_test_level = level; +} + +void pm_dump_regs(unsigned int flag) +{ + if (flag & 1<<0) { /* cpu */ + int i, j; + + PM_LOGD("regs:\n"); + PM_LOGD("msp:0x%08x, psp:0x%08x, psr:0x%08x, primask:0x%08x\n", + vault_arm_registers.msp, vault_arm_registers.psp, + vault_arm_registers.psr, vault_arm_registers.primask); + PM_LOGD("faultmask:0x%08x, basepri:0x%08x, control:0x%08x\n", + vault_arm_registers.faultmask, vault_arm_registers.basepri, + vault_arm_registers.control); + for (i = 0; i < 3; i++) { + for (j = 0; j < 4; j++) { + PM_LOGD("reg[%d]:0x%08x ", j+i*4, + vault_arm_registers.reg12[j+i*4]); + } + PM_LOGD("\n"); + } + PM_LOGD("last step:%x\n", __get_last_record_step()); + } + if (flag & 1<<1) { /* nvic */ + //nvic_print_regs(); + } + if (flag & 1<<2) { /* ccmu */ + //ccm_print_regs(); + } + if (flag & 1<<3) { /* gpio */ + //gpio_print_regs(); + } +} + +static void dpm_show_time(ktime_t starttime, enum suspend_state_t state, char *info) +{ + ktime_t calltime; + + calltime = ktime_get(); + PM_LOGD("%s of devices complete after %d ms\n", info ? info : "", (int)(calltime - starttime)); +} + +#else +#define suspend_test_start() +#define suspend_test_finish(x...) +#define suspend_test(l) 0 +void pm_set_test_level(enum suspend_test_level_t level) {;} +#define pm_dump_regs(flag) +#define dpm_show_time(x...) +#endif + +static LIST_HEAD_DEF(dpm_late_early_list); +static LIST_HEAD_DEF(dpm_noirq_list); + +static LIST_HEAD_DEF(dpm_list); +static LIST_HEAD_DEF(dpm_suspended_list); + +#ifdef CONFIG_PM_DEBUG +static struct suspend_stats suspend_stats; + +void parse_dpm_list(struct list_head *head, unsigned int idx) +{ + struct list_head *list; + struct soc_device *dev; + + PM_DBG("(%p)", head); + list_for_each(list, head) { + dev = to_device(list, idx); + PM_DBG("-->%s(%p)", dev->name, dev); + } + PM_DBG("\n"); +} +#endif + +static unsigned int initcall_debug_delay_us = 0; + +/** + * @brief Set delay ms in debug mode. + * @note To prevent mutual interference between devices. + * @param ms: + * @arg ms->The delayed ms between two devices. + */ +void pm_set_debug_delay_ms(unsigned int ms) +{ + initcall_debug_delay_us = ms * 1000; +} + +/** + * check_wakeup_irqs - check if any wake-up interrupts are pending + */ +int check_wakeup_irqs(void) +{ + int i; + unsigned int *addr; + unsigned int val; + + /* Check if there are any interrupts pending */ + addr = (unsigned int *)NVIC->ISPR; + for (i = 0; i < DIV_ROUND_UP(NVIC_PERIPH_IRQ_NUM, 32); i++) { + val= addr[i]; + if (val & nvic_int_mask[i]) { + PM_LOGN("nvic[%d]:%x, mask:%x\n", i, val, nvic_int_mask[i]); + return 1; + } + } + + return 0; +} + +/** + * dpm_suspend_noirq - Execute "noirq suspend" callbacks for all devices. + * @state: PM transition of the system being carried out. + * + * Prevent device drivers from receiving interrupts and call the "noirq" suspend + * handlers for all non-sysdev devices. + */ +static int dpm_suspend_noirq(enum suspend_state_t state) +{ + struct soc_device *dev = NULL; +#ifdef CONFIG_PM_DEBUG + ktime_t starttime = ktime_get(); +#endif + int error = 0; + + while (!list_empty(&dpm_late_early_list)) { + dev = to_device(dpm_late_early_list.next, PM_OP_NOIRQ); + + get_device(dev); + + error = dev->driver->suspend_noirq(dev, state); + if (initcall_debug_delay_us > 0) { + PM_LOGD("sleep %d ms for debug.\n", initcall_debug_delay_us); + pm_udelay(initcall_debug_delay_us); + } + + if (error || !arch_irq_get_flags()) { + PM_LOGE("%s suspend noirq failed! primask:%d\n", + dev->name, (int)arch_irq_get_flags()); + put_device(dev); + break; + } + list_move(&dev->node[PM_OP_NOIRQ], &dpm_noirq_list); + dsb(); + isb(); + put_device(dev); + + if (check_wakeup_irqs()) { + error = -1; + break; + } + } + +#ifdef CONFIG_PM_DEBUG + if (error) { + suspend_stats.failed_suspend_noirq++; + if (dev && dev->name) + memcpy(suspend_stats.failed_devs, dev->name, MAX_DEV_NAME); + suspend_stats.last_failed_step = TEST_DEVICES; + dpm_show_time(starttime, state, "noirq"); + } +#endif + + return error; +} + +/** + * dpm_suspend - Execute "suspend" callbacks for all devices. + * @state: PM transition of the system being carried out. + */ +static int dpm_suspend(enum suspend_state_t state) +{ + struct soc_device *dev = NULL; +#ifdef CONFIG_PM_DEBUG + ktime_t starttime = ktime_get(); +#endif + int error = 0; + + while (!list_empty(&dpm_list)) { + dev = to_device(dpm_list.next, PM_OP_NORMAL); + + get_device(dev); + error = dev->driver->suspend(dev, state); + if (initcall_debug_delay_us > 0) { + PM_LOGD("sleep %d ms for debug.\n", initcall_debug_delay_us); + pm_udelay(initcall_debug_delay_us); + } + + if (error) { + PM_LOGE("%s suspend failed!\n", dev->name); + put_device(dev); + break; + } + list_move(&dev->node[PM_OP_NORMAL], &dpm_suspended_list); + dsb(); + isb(); + put_device(dev); + } + +#ifdef CONFIG_PM_DEBUG + if (error) { + suspend_stats.failed_suspend++; + if (dev && dev->name) + memcpy(suspend_stats.failed_devs, dev->name, MAX_DEV_NAME); + suspend_stats.last_failed_step = TEST_DEVICES; + dpm_show_time(starttime, state, "suspend"); + } +#endif + + return error; +} + +/** + * dpm_resume_noirq - Execute "noirq resume" callbacks for all devices. + * @state: PM transition of the system being carried out. + * + * Call the "noirq" resume handlers for all devices in dpm_noirq_list and + * enable device drivers to receive interrupts. + */ +static void dpm_resume_noirq(enum suspend_state_t state) +{ + struct soc_device *dev; + ktime_t starttime = ktime_get(); + int error; + + while (!list_empty(&dpm_noirq_list)) { + dev = to_device(dpm_noirq_list.next, PM_OP_NOIRQ); + + get_device(dev); + list_move(&dev->node[PM_OP_NOIRQ], &dpm_late_early_list); + dsb(); + isb(); + + error = dev->driver->resume_noirq(dev, state); +#ifdef CONFIG_PM_DEBUG + if (error) { + suspend_stats.failed_resume_noirq++; + PM_LOGE("%s resume noirq failed!\n", dev->name); + } +#else + (void)error; + (void)starttime; +#endif + + put_device(dev); + } + dpm_show_time(starttime, state, "noirq"); +} + +/** + * dpm_resume - Execute "resume" callbacks for non-sysdev devices. + * @state: PM transition of the system being carried out. + * + * Execute the appropriate "resume" callback for all devices whose status + * indicates that they are suspended. + */ +static void dpm_resume(enum suspend_state_t state) +{ + struct soc_device *dev; + ktime_t starttime = ktime_get(); + int error; + + while (!list_empty(&dpm_suspended_list)) { + dev = to_device(dpm_suspended_list.next, PM_OP_NORMAL); + + get_device(dev); + list_move(&dev->node[PM_OP_NORMAL], &dpm_list); + dsb(); + isb(); + + error = dev->driver->resume(dev, state); +#ifdef CONFIG_PM_DEBUG + if (error) { + suspend_stats.failed_resume++; + PM_LOGE("%s resume failed!\n", dev->name); + } +#else + (void)error; + (void)starttime; +#endif + + put_device(dev); + } + dpm_show_time(starttime, state, "resume"); +} + +/** + * suspend_enter - Make the system enter the given sleep state. + * @state: System sleep state to enter. + * @wakeup: Returns information that the sleep state should not be re-entered. + * + * This function should be called after devices have been suspended. + */ +static int suspend_enter(enum suspend_state_t state) +{ + int wakeup; + int error; + + if (suspend_ops.prepare) { + error = suspend_ops.prepare(state); + if (error) + goto Platform_finish; + } + + arch_suspend_disable_irqs(); + + wakeup = check_wakeup_irqs(); + if (wakeup) { + error = -1; + goto Platform_finish; + } + + __record_dbg_status(PM_SUSPEND_DEVICES | 0x10); + suspend_test_start(); + error = dpm_suspend_noirq(state); + if (error) { +#ifdef CONFIG_PM_DEBUG + suspend_stats.fail++; + PM_LOGE("Some devices noirq failed to suspend\n"); + parse_dpm_list(&dpm_noirq_list, PM_OP_NOIRQ); +#endif + goto Resume_noirq_devices; + } + + suspend_test_finish("suspend noirq devices"); + if (suspend_test(TEST_DEVICES)) + goto Resume_noirq_devices; + + __record_dbg_status(PM_SUSPEND_ENTER); + + __record_dbg_status(PM_SUSPEND_ENTER | 1); + if (suspend_test(TEST_PLATFORM)) + goto Platform_wake; + + __record_dbg_status(PM_SUSPEND_ENTER | 2); + wakeup = check_wakeup_irqs(); + if (!(suspend_test(TEST_CORE) || wakeup)) { + __record_dbg_status(PM_SUSPEND_ENTER | 3); + suspend_ops.enter(state); + __record_dbg_status(PM_SUSPEND_ENTER | 4); + } + +Platform_wake: + if (suspend_ops.wake) + suspend_ops.wake(state); + +Resume_noirq_devices: + __record_dbg_status(PM_RESUME_DEVICES | 0x10); + suspend_test_start(); + dpm_resume_noirq(state); + suspend_test_finish("resume noirq devices"); + +Platform_finish: + arch_suspend_enable_irqs(); + + return wakeup; +} + +/** + * suspend_devices_and_enter - Suspend devices and enter system sleep state. + * @state: System sleep state to enter. + */ +static int suspend_devices_and_enter(enum suspend_state_t state) +{ + int error; + + __record_dbg_status(PM_EARLY_SUSPEND); + if (!valid_state(state)) { + return -1; + } + + __record_dbg_status(PM_SUSPEND_BEGIN); + if (suspend_ops.begin) { + error = suspend_ops.begin(state); + if (error) + goto Close; + } + + __record_dbg_status(PM_SUSPEND_DEVICES); + suspend_test_start(); + error = dpm_suspend(state); + if (error) { +#ifdef CONFIG_PM_DEBUG + suspend_stats.fail++; +#endif + PM_LOGE("Some devices failed to suspend\n"); + goto Resume_devices; + } +#ifdef CONFIG_PM_DEBUG + suspend_stats.success++; +#endif + suspend_test_finish("suspend devices"); + if (suspend_test(TEST_DEVICES)) + goto Resume_devices; + + OS_ThreadSuspendScheduler(); + __record_dbg_status(PM_SUSPEND_ENTER); + suspend_enter(state); + OS_ThreadResumeScheduler(); + +Resume_devices: + __record_dbg_status(PM_RESUME_DEVICES); + suspend_test_start(); + dpm_resume(state); + suspend_test_finish("resume devices"); + +Close: + __record_dbg_status(PM_RESUME_END); + if (suspend_ops.end) + suspend_ops.end(state); + __record_dbg_status(PM_RESUME_COMPLETE); + + return error; +} + +/** + * @brief Register a set of system core operations. + * @note Not use printf for this func maybe called very earlier. + * @param dev: + * @arg dev->Device will be registered. + * @retval 0 if success or other if failed. + */ +int pm_register_ops(struct soc_device *dev) +{ + struct list_head *hd; + struct soc_device *dev_c; + unsigned long flags; + unsigned int valid; + + if (!dev) + return -EINVAL; + + valid = dev->node[PM_OP_NORMAL].next || dev->node[PM_OP_NORMAL].prev; + if (valid) + PM_BUG_ON(!list_empty(&dev->node[PM_OP_NORMAL])); + valid = dev->node[PM_OP_NOIRQ].next || dev->node[PM_OP_NOIRQ].prev; + if (valid) + PM_BUG_ON((!list_empty(&dev->node[PM_OP_NOIRQ]))); + PM_BUG_ON(!dev->driver || + ((!dev->driver->suspend_noirq || !dev->driver->resume_noirq) && + (!dev->driver->suspend || !dev->driver->resume))); + + if (dev->driver->suspend || dev->driver->resume) { + PM_BUG_ON(!dev->driver->suspend || !dev->driver->resume); + list_for_each(hd, &dpm_list) { + dev_c = to_device(hd, PM_OP_NORMAL); + if (dev_c == dev) { + goto next; + } + } + + INIT_LIST_HEAD(&dev->node[PM_OP_NORMAL]); + flags = arch_irq_save(); + list_add(&dev->node[PM_OP_NORMAL], &dpm_list); + arch_irq_restore(flags); + } + +next: + if (dev->driver->suspend_noirq || dev->driver->resume_noirq) { + PM_BUG_ON(!dev->driver->suspend_noirq || !dev->driver->resume_noirq); + list_for_each(hd, &dpm_late_early_list) { + dev_c = to_device(hd, PM_OP_NOIRQ); + if (dev_c == dev) { + return -1; + } + } + + INIT_LIST_HEAD(&dev->node[PM_OP_NOIRQ]); + flags = arch_irq_save(); + list_add(&dev->node[PM_OP_NOIRQ], &dpm_late_early_list); + arch_irq_restore(flags); + } + + return 0; +} + +/** + * @brief Unregister a set of system core operations. + * @param dev: + * @arg dev->Device will be unregistered. + * @retval 0 if success or other if failed. + */ +int pm_unregister_ops(struct soc_device *dev) +{ + unsigned long flags; + + if (!dev) + return -EINVAL; + + if (dev->driver->suspend) { + PM_BUG_ON(!dev->node[PM_OP_NORMAL].next || !dev->node[PM_OP_NORMAL].prev); + PM_BUG_ON(list_empty(&dev->node[PM_OP_NORMAL])); + } + if (dev->driver->suspend_noirq) { + PM_BUG_ON(!dev->node[PM_OP_NOIRQ].next || !dev->node[PM_OP_NOIRQ].prev); + PM_BUG_ON(list_empty(&dev->node[PM_OP_NOIRQ])); + } + + flags = arch_irq_save(); + if (dev->driver->suspend) + list_del(&dev->node[PM_OP_NORMAL]); + if (dev->driver->suspend_noirq) + list_del(&dev->node[PM_OP_NOIRQ]); + arch_irq_restore(flags); + + return 0; +} + +void pm_select_mode(enum suspend_state_t state) +{ + user_sel_power_mode = state; +} + +#ifdef CONFIG_PM_DEBUG +/** @brief Show suspend statistic info. */ +void pm_stats_show(void) +{ + PM_LOGN("suspend state:\n" + " success:%d\n" + " fail:%d\n" + " failed_suspend:%d\n" + " failed_resume:%d\n" + " last_failed_step:%d\n" + " last_failed_device:%s\n" + " last_wakeup_event:%x\n", + suspend_stats.success, suspend_stats.fail, + suspend_stats.failed_suspend, suspend_stats.failed_resume, + suspend_stats.last_failed_step, suspend_stats.failed_devs, + HAL_Wakeup_GetEvent()); +} +#else +void pm_stats_show(void) +{ +} +#endif + +/** + * @brief Initialize the PM-related part of a device object. + * @note not use printf for this fun is called very earlier. + * @retval 0 if success or other if failed. + */ +int pm_init(void) +{ + HAL_Wakeup_Init(); + +#ifdef __CONFIG_ARCH_APP_CORE +#if 0 + HAL_PRCM_EnableSys2Power(); + pm_udelay(10000); + HAL_PRCM_DisableSys2Power(); + pm_udelay(10000); +#endif + + /* set prcm to default value for prcm keep it's last time value. */ + HAL_PRCM_SetSys1WakeupPowerFlags(0x0f); + HAL_PRCM_SetSys1SleepPowerFlags(0x0e); + HAL_PRCM_Start(); +#endif + + return 0; +} + +#ifdef __CONFIG_ARCH_APP_CORE +static pm_wlan_power_onoff pm_wlan_power_onoff_cb = NULL; +static int pm_wlan_mode_platform_config = PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF; + +/** + * @brief Select wlan power modes when enter pm. + * @note Wlan power on/off calback will called when pm enter select modes. + * @param wlan_power_cb: + * @arg wlan_power_cb->Wlan power on/off calback. + * @param select: + * @arg select->The selected modes set. + * retval 0 if success or other if failed. + */ +int pm_register_wlan_power_onoff(pm_wlan_power_onoff wlan_power_cb, unsigned int select) +{ + if ((select & (PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF)) != + (PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF)) { + PM_LOGW("wlan should power off when hibernateion/poweroff!\n"); + return -1; + } + pm_wlan_power_onoff_cb = wlan_power_cb; + pm_wlan_mode_platform_config = select | PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF; + PM_LOGN("wlan mode:%x\n", pm_wlan_mode_platform_config); + + return 0; +} + +/** @brief unregister wlan power on/off callback. */ +void pm_unregister_wlan_power_onoff(void) +{ + pm_wlan_power_onoff_cb = NULL; +} +#endif + +#ifdef __CONFIG_ARCH_APP_CORE +static int pm_mode_platform_config = PM_SUPPORT_SLEEP | PM_SUPPORT_STANDBY | PM_SUPPORT_POWEROFF; + +/** + * @brief Select pm modes used on this platform. + * @note Select modes at init for some modes are not used on some platforms. + * This will prevent enter unselect modes. + * @param select: + * @arg select->The selected modes set. + */ +void pm_mode_platform_select(unsigned int select) +{ + pm_mode_platform_config = select; + if (!(select & (PM_SUPPORT_SLEEP | PM_SUPPORT_STANDBY | \ + PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF))) { + PM_LOGW("slect wrong mode!\n"); + return ; + } + PM_LOGN("mode select:%x\n", select); +} + +static int pm_wlan_alive_platform_config = PM_SUPPORT_SLEEP | PM_SUPPORT_STANDBY; + +int pm_wlan_alive_platform_select(unsigned int select) +{ + if (select & (PM_SUPPORT_HIBERNATION | PM_SUPPORT_POWEROFF)) { + PM_LOGW("net can't be alive when hiberantion or poweroff!\n"); + return -1; + } + pm_wlan_alive_platform_config = select; + PM_LOGN("net alive select:%x\n", select); + + return 0; +} + +/** + * @brief Set a magin to synchronize with net. + */ +void pm_set_sync_magic(void) +{ + PM_SetCPUBootArg(PM_SYNC_MAGIC); /* set flag to notify net to run */ +} +#endif + + +/** + * @brief Set system to a lowpower mode. + * @param state: + * @arg state->The lowpower mode will enter. + * @retval 0 if success or other if failed. + */ +int pm_enter_mode(enum suspend_state_t state) +{ + int err, record; + enum suspend_state_t state_use = state; +#ifdef __CONFIG_ARCH_APP_CORE + int net_alive, loop; + + if (!(pm_mode_platform_config & (1 << state))) { + for (loop = (1 << state_use); loop; loop >>= 1) { + if (pm_mode_platform_config & loop) { + break; + } + state_use--; + } + } +#endif + + PM_BUG_ON(state_use >= PM_MODE_MAX); + + if (state_use < PM_MODE_SLEEP) + return 0; + + pm_select_mode(state_use); + PM_LOGD(PM_SYS" enter mode: %s\n", pm_states[state_use]); + record = __get_last_record_step(); + if (record != PM_RESUME_COMPLETE) + PM_LOGN("last suspend record:%x\n", record); +#ifdef CONFIG_PM_DEBUG + parse_dpm_list(&dpm_list, PM_OP_NORMAL); /* debug info. */ + parse_dpm_list(&dpm_late_early_list, PM_OP_NOIRQ); +#endif +#ifdef __CONFIG_ARCH_APP_CORE + net_alive = HAL_PRCM_IsCPUNReleased(); + if (net_alive && (pm_wlan_mode_platform_config & (1 << state_use)) && pm_wlan_power_onoff_cb) { + pm_wlan_power_onoff_cb(0); + } +#endif + + err = suspend_devices_and_enter(state_use); + +#ifdef __CONFIG_ARCH_APP_CORE + pm_set_sync_magic(); + + if (net_alive && (pm_wlan_mode_platform_config & (1 << state_use)) && pm_wlan_power_onoff_cb) { + pm_wlan_power_onoff_cb(1); + } +#endif + + return err; +} + +//#define CONFIG_PM_TEST 1 + +#ifdef CONFIG_PM_TEST + +static int test_suspend_noirq(struct soc_device *dev, enum suspend_state_t state) +{ + PM_LOGD("%s %s okay\n", dev->name, __func__); + + //if (!strcmp(dev->name, "dev_test1")) + // return -1; + //else + return 0; +} + +static int test_resume_noirq(struct soc_device *dev, enum suspend_state_t state) +{ + PM_LOGD("%s %s okay\n", dev->name, __func__); + + return 0; +} + +static int test_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + PM_LOGD("%s %s okay\n", dev->name, __func__); + + //if (!strcmp(dev->name, "dev_test1")) + // return -1; + //else + return 0; +} + +static int test_resume(struct soc_device *dev, enum suspend_state_t state) +{ + PM_LOGD("%s %s okay\n", dev->name, __func__); + + return 0; +} + +static struct soc_device_driver drv_test1 = { + .name = "drv_test1", + .suspend = &test_suspend, + .resume = &test_resume, +}; +static struct soc_device dev_test1 = { + .name = "dev_test1", + .driver = &drv_test1, +}; + +static struct soc_device_driver drv_test2 = { + .name = "drv_test2", + .suspend = &test_suspend, + .resume = &test_resume, +}; +static struct soc_device dev_test2 = { + .name = "dev_test2", + .driver = &drv_test2, +}; + +static struct soc_device_driver drv_test3 = { + .name = "drv_test3", + .suspend_noirq = &test_suspend_noirq, + .resume_noirq = &test_resume_noirq, + .suspend = &test_suspend, + .resume = &test_resume, +}; +static struct soc_device dev_test3 = { + .name = "dev_test3", + .driver = &drv_test3, +}; + +int pm_test(void) +{ + struct list_head *hd = &dpm_list; + struct soc_device *dev; + + pm_register_ops(&dev_test1); + pm_register_ops(&dev_test2); + pm_register_ops(&dev_test2); + pm_register_ops(&dev_test3); + + parse_dpm_list(&dpm_list, PM_OP_NORMAL); + parse_dpm_list(&dpm_late_early_list, PM_OP_NOIRQ); + + PM_LOGD("dpm_list:\n"); + while (!list_is_last(hd, &dpm_list)) { + dev = to_device(hd->next, PM_OP_NORMAL); + hd = hd->next; + PM_LOGD("name: %s\n", dev->name); + } + + PM_LOGD("dpm_late_early_list:\n"); + hd = &dpm_late_early_list; + while (!list_is_last(hd, &dpm_late_early_list)) { + dev = to_device(hd->next, PM_OP_NOIRQ); + hd = hd->next; + PM_LOGD("name: %s\n", dev->name); + } + + return 0; +} +#endif + +#endif /* CONFIG_PM */ diff --git a/platform/mcu/xr871/src/pm/pm.mk b/platform/mcu/xr871/src/pm/pm.mk new file mode 100644 index 0000000000..2861c76179 --- /dev/null +++ b/platform/mcu/xr871/src/pm/pm.mk @@ -0,0 +1,5 @@ +NAME := pm + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := pm.c \ + port.c diff --git a/platform/mcu/xr871/src/pm/pm_i.h b/platform/mcu/xr871/src/pm/pm_i.h new file mode 100644 index 0000000000..3c2a626548 --- /dev/null +++ b/platform/mcu/xr871/src/pm/pm_i.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PM_H +#define __PM_H + +#include "pm/pm.h" + +#ifdef CONFIG_PM + +#define CONFIG_PM_DEBUG 1 + +#ifdef CONFIG_PM_DEBUG +#define PM_DBG(format, args...) do {printf(format, ##args);} while (0) +#define PM_LOGD(format, args...) do {printf("PM: "format, ##args);} while (0) +#define PM_LOGN(format, args...) do {printf("PM: "format, ##args);} while (0) +#define PM_LOGW(format, args...) do {printf("PM: WAR "format, ##args);} while (0) +#define PM_LOGE(format, args...) do {printf("PM: ERR "format, ##args);} while (0) +#define PM_LOGA(format, args...) do {printf("PM: "format, ##args);} while (0) +#else +#define PM_DBG(x...) +#define PM_LOGD(x...) +#define PM_LOGN(x...) +#define PM_LOGW(x...) +#define PM_LOGE(x...) +#define PM_LOGA(x...) +#endif +#define PM_BUG_ON(v) do {if(v) {printf("PM: BUG at %s:%d!\n", __func__, __LINE__); while (1);}} while (0) +#define PM_WARN_ON(v) do {if(v) {printf("PM: WARN at %s:%d!\n", __func__, __LINE__);}} while (0) + +#ifdef CONFIG_PM_DEBUG +#define MAX_DEV_NAME 40 +struct suspend_stats { + int success; + int fail; + int failed_suspend_noirq; + int failed_suspend; + int failed_resume; + int failed_resume_noirq; + char failed_devs[MAX_DEV_NAME]; + int last_failed_step; +}; +#endif + +#define PM_EARLY_SUSPEND (1<<16) +#define PM_SUSPEND_BEGIN (2<<16) +#define PM_SUSPEND_DEVICES (3<<16) +#define PM_SUSPEND_ENTER (4<<16) +#define PM_RESUME_SYSTEM (6<<16) +#define PM_RESUME_DEVICES (7<<16) +#define PM_RESUME_END (8<<16) +#define PM_RESUME_COMPLETE (9<<16) +#define PM_RESUME_ERROR (0x0e<<16) +#define PM_SUSPEND_FAIL_FLAG (0xFFFF) +#define PM_FIRST_BOOT_FLAG (0x0000) + +#define PM_POWEROFF (0x0a<<16) + +#define PM_SYNC_MAGIC (0x7FF2DCCD) + +/** + * @brief Data constructs for implementation in assembly. + * @note systick saved by timer subsys. + */ +struct arm_CMX_core_regs { + unsigned int msp; + unsigned int psp; + unsigned int psr; + unsigned int primask; + unsigned int faultmask; + unsigned int basepri; + unsigned int control; + unsigned int reg12[16]; /* used only for debug */ +}; + +/** + * @brief Callbacks for managing platform dependent system sleep states. + * + * @begin: Initialise a transition to given system sleep state. + * @begin() is executed right prior to suspending devices. The information + * conveyed to the platform code by @begin() should be disregarded by it as + * soon as @end() is executed. If @begin() fails (ie. returns nonzero), + * @prepare(), @enter() and @finish() will not be called. + * + * @prepare: Prepare the platform for entering the system sleep state indicated. + * @prepare() is called right after devices have been suspended (ie. the + * appropriate .suspend() method has been executed for each device) and + * before device drivers' late suspend callbacks are executed. It returns + * 0 on success or a negative error code otherwise, in which case the + * system cannot enter the desired sleep state. + * + * @enter: Enter the system sleep state indicated. + * It returns 0 on success or a negative error code otherwise, in which + * case the system cannot enter the desired sleep state. + * + * @wake: Called when the system has just left a sleep state, right after + * the CPU have been enabled and before device drivers' early resume + * callbacks are executed. + * It is always called after @enter(). + * + * @end: Called after resuming devices, to indicate to the platform that the + * system has returned to the working state or the transition to the sleep + * state has been aborted. + * Platforms implementing @begin() should also provide a @end() which + * cleans up transitions aborted before @enter(). + */ +struct platform_suspend_ops { + int (*begin)(enum suspend_state_t state); + int (*prepare)(enum suspend_state_t state); + void (*enter)(enum suspend_state_t state); + void (*wake)(enum suspend_state_t state); + void (*end)(enum suspend_state_t state); +}; + +#define to_device(ptr_module, idx) \ + __containerof(ptr_module, struct soc_device, node[idx]) +#define get_device(d) d->ref++ +#define put_device(d) d->ref-- + +extern void __cpu_sleep(enum suspend_state_t state); +extern void __cpu_suspend(enum suspend_state_t state); +#endif + +#endif diff --git a/platform/mcu/xr871/src/pm/port.c b/platform/mcu/xr871/src/pm/port.c new file mode 100644 index 0000000000..c91774fbd6 --- /dev/null +++ b/platform/mcu/xr871/src/pm/port.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include "sys/io.h" +#include "errno.h" +#include "sys/list.h" + +#include "driver/chip/chip.h" +#include "driver/chip/hal_wakeup.h" +#include "driver/chip/hal_prcm.h" +#include "driver/chip/hal_nvic.h" + +#include "pm/pm.h" +#include "pm_i.h" +#include "port.h" + +#ifdef CONFIG_PM + +/* It is better that all interrupts are managed by itself, the interrupt should + * be disable by it's driver if it is not used during suspend. We use this mask + * for a sample concentrated cometrue, 1: use this irq as wakeup source */ +unsigned int nvic_int_mask[] = { + NVIC_PERIPH_IRQ_MASK0, +#if (MAX_IRQn > 32) + NVIC_PERIPH_IRQ_MASK1, +#endif +}; + +ct_assert((sizeof(nvic_int_mask) + 3) / 4 >= (NVIC_PERIPH_IRQ_NUM + 31)/32); + +void debug_jtag_init(void) +{ +#ifdef CONFIG_PM_DEBUG + /* at this time gpio is reset state */ +/* + GPIO_InitParam param; + + param.mode = GPIOB_P2_F2_SWD_TMS; + param.driving = GPIO_DRIVING_LEVEL_1; + param.pull = GPIO_PULL_UP; + HAL_GPIO_Init(GPIO_PORT_B, GPIO_PIN_2, ¶m); + + param.mode = GPIOB_P3_F2_SWD_TCK; + param.driving = GPIO_DRIVING_LEVEL_1; + param.pull = GPIO_PULL_UP; + HAL_GPIO_Init(GPIO_PORT_B, GPIO_PIN_3, ¶m); +*/ +#endif +} + +void debug_jtag_deinit(void) +{ +#ifdef CONFIG_PM_DEBUG + //HAL_GPIO_DeInit(GPIO_PORT_B, GPIO_PIN_2); + //HAL_GPIO_DeInit(GPIO_PORT_B, GPIO_PIN_3); +#endif +} + +static NVIC_IRQHandler uart_rx_back; + +static void uart_rx_callback(void) +{ + HAL_NVIC_DisableIRQ(N_UART_IRQn); + HAL_NVIC_ClearPendingIRQ(N_UART_IRQn); +} + +int platform_prepare(enum suspend_state_t state) +{ + uart_rx_back = HAL_NVIC_GetIRQHandler(N_UART_IRQn); + + HAL_NVIC_SetIRQHandler(N_UART_IRQn, uart_rx_callback); + HAL_NVIC_EnableIRQ(N_UART_IRQn); + + return 0; +} + +void platform_wake(enum suspend_state_t state) +{ + HAL_NVIC_EnableIRQ(N_UART_IRQn); + __ISB(); + __NOP(); + HAL_NVIC_SetIRQHandler(N_UART_IRQn, uart_rx_back); +} + +#endif diff --git a/platform/mcu/xr871/src/pm/port.h b/platform/mcu/xr871/src/pm/port.h new file mode 100644 index 0000000000..2ac8ec6a99 --- /dev/null +++ b/platform/mcu/xr871/src/pm/port.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PM_PORT_H +#define __PM_PORT_H + +#include "sys/interrupt.h" +#include "kernel/os/os_time.h" +#include "pm/pm.h" + +#include "driver/chip/hal_rtc.h" + +#ifdef CONFIG_PM + +#define ct_assert(e) extern char (*ct_assert(void)) [sizeof(char[1 - 2*!(e)])] + +#if defined(__CONFIG_CHIP_XR871) +#define ktime_t uint64_t +#define ktime_get() (HAL_RTC_GetFreeRunTime() / 1000) +#define ktime_to_msecs(t) (t) +#else +#define ktime_t uint32_t +#define ktime_get() OS_GetTicks() +#define ktime_to_msecs(t) OS_MSecsToJiffies(t) +#endif + +#define arch_suspend_disable_irqs __disable_irq +#define arch_suspend_enable_irqs __enable_irq + +extern unsigned int nvic_int_mask[]; + +extern void debug_jtag_init(void); +extern void debug_jtag_deinit(void); + +int platform_prepare(enum suspend_state_t state); +extern void platform_wake(enum suspend_state_t state); + +#endif + +#endif /* __PM_PORT_H */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc.c b/platform/mcu/xr871/src/sys/ducc/ducc.c new file mode 100644 index 0000000000..4b247be379 --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ducc_os.h" +#include "ducc_debug.h" +#include "ducc.h" + + +/* + * ducc semaphore is used to wait respond from another cpu core. + */ + +#define DUCC_SEM_NUM DUCC_TYPE_NUM + +static ducc_semaphore_t ducc_req_sem[DUCC_SEM_NUM]; +#ifdef __CONFIG_ARCH_APP_CORE +static ducc_semaphore_t *g_ducc_req_sem[DUCC_ID_NUM] = { + [DUCC_ID_APP2NET_NORMAL] = NULL, + [DUCC_ID_APP2NET_DATA] = NULL, + [DUCC_ID_NET2APP_NORMAL] = &ducc_req_sem[0], + [DUCC_ID_NET2APP_DATA] = &ducc_req_sem[1], +}; +#elif (defined(__CONFIG_ARCH_NET_CORE)) +static ducc_semaphore_t *g_ducc_req_sem[DUCC_ID_NUM] = { + [DUCC_ID_APP2NET_NORMAL] = &ducc_req_sem[0], + [DUCC_ID_APP2NET_DATA] = &ducc_req_sem[1], + [DUCC_ID_NET2APP_NORMAL] = NULL, + [DUCC_ID_NET2APP_DATA] = NULL, +}; +#endif /* __CONFIG_ARCH_APP_CORE */ + + +int ducc_req_init(uint32_t id) +{ + return ducc_semaphore_create(g_ducc_req_sem[id], 0); +} + +void ducc_req_deinit(uint32_t id) +{ + ducc_semaphore_delete(g_ducc_req_sem[id]); +} + +int ducc_req_wait(uint32_t id) +{ + return ducc_semaphore_wait(g_ducc_req_sem[id]); +} + +void ducc_req_release(uint32_t id) +{ + ducc_semaphore_release(g_ducc_req_sem[id]); +} diff --git a/platform/mcu/xr871/src/sys/ducc/ducc.h b/platform/mcu/xr871/src/sys/ducc/ducc.h new file mode 100644 index 0000000000..a197f7ddfe --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_H_ +#define _SYS_DUCC_DUCC_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* simulate h/w msgbox using timers and registers or not */ +#define DUCC_SIMULATE_HW_MBOX 0 + +enum DUCC_ID { + DUCC_ID_APP2NET_NORMAL = 0, + DUCC_ID_APP2NET_DATA, + DUCC_ID_NET2APP_NORMAL, + DUCC_ID_NET2APP_DATA, + + DUCC_ID_NUM +}; + +#define DUCC_DIR_NUM 2 /* APP2NET, NET2APP */ +#define DUCC_TYPE_NUM 2 /* NORMAL, DATA */ + +struct ducc_req { +#if DUCC_SIMULATE_HW_MBOX + uint32_t id; +#endif + uint32_t cmd; + uint32_t param; + int result; /* @out */ +}; + +#define DUCC_RELEASE_REQ_MAGIC 0xfa050000 +#define DUCC_RELEASE_REQ_MASK 0xffff0000 +#define DUCC_RELEASE_REQ_VAL(id) \ + ((void *)(DUCC_RELEASE_REQ_MAGIC | (id))) +#define DUCC_IS_RELEASE_REQ(r) \ + ((((uint32_t)(r)) & DUCC_RELEASE_REQ_MASK) == DUCC_RELEASE_REQ_MAGIC) +#define DUCC_RELEASE_REQ_ID(r) \ + (((uint32_t)(r)) & ~DUCC_RELEASE_REQ_MASK) + +int ducc_req_init(uint32_t id); +void ducc_req_deinit(uint32_t id); +int ducc_req_wait(uint32_t id); +void ducc_req_release(uint32_t id); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_H_ */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_app.c b/platform/mcu/xr871/src/sys/ducc/ducc_app.c new file mode 100644 index 0000000000..75f4bc02c5 --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_app.c @@ -0,0 +1,433 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) + +#include "ducc_os.h" +#include "sys/ducc/ducc_addr.h" +#include "sys/ducc/ducc_app.h" +#include "sys/ducc/ducc_net.h" +#include "sys/mbuf.h" +#include "sys/image.h" +#include "net/wlan/wlan.h" + +#include "ducc_debug.h" +#include "ducc_mbox.h" +#include "ducc.h" +#include "pm/pm.h" + + +/* resouce for normal functions */ +#define DUCC_APP_NORMAL_THREAD_PRIO OS_PRIORITY_ABOVE_NORMAL +#define DUCC_APP_NORMAL_THREAD_STACK_SIZE (8 * 1024) +static ducc_thread_t g_ducc_app_normal_thread; +static ducc_mutex_t g_ducc_app_normal_mutex; + +/* resouce for functions about TX/RX */ +#define DUCC_APP_DATA_THREAD_PRIO OS_PRIORITY_NORMAL +#define DUCC_APP_DATA_THREAD_STACK_SIZE (8 * 1024) +static ducc_thread_t g_ducc_app_data_thread; +static ducc_mutex_t g_ducc_app_data_mutex; + +/* marcos for request */ +#define DUCC_APP_REQ_SEND(id, r) ducc_mbox_send(id, r) +#define DUCC_APP_REQ_RECV(id) ducc_mbox_recv(id, DUCC_WAIT_FOREVER) + +#define DUCC_APP_REQ_WAIT(id) ducc_req_wait(id) +#define DUCC_APP_REQ_RELEASE(id) ducc_req_release(id) + +/* convert pointer from net core to app core */ +#define DUCC_APP_PTR(p) ((void *)DUCC_NETMEM_NET2APP(p)) + +static ducc_cb_func ducc_app_cb = NULL; + +#ifdef CONFIG_PM + +static int8_t g_ducc_hw_mbox_suspending = 0; + +static int ducc_hw_mbox_suspend(struct soc_device *dev, enum suspend_state_t state) +{ + g_ducc_hw_mbox_suspending = 1; + + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + case PM_MODE_POWEROFF: + ducc_mbox_deinit(DUCC_ID_NET2APP_DATA, 0, 1); + ducc_mbox_deinit(DUCC_ID_APP2NET_DATA, 1, 1); + + ducc_mbox_deinit(DUCC_ID_NET2APP_NORMAL, 0, 1); + ducc_mbox_deinit(DUCC_ID_APP2NET_NORMAL, 1, 1); + DUCC_DBG("%s okay\n", __func__); + break; + default: + break; + } + + return 0; +} + +static int ducc_hw_mbox_resume(struct soc_device *dev, enum suspend_state_t state) +{ + switch (state) { + case PM_MODE_SLEEP: + break; + case PM_MODE_STANDBY: + case PM_MODE_HIBERNATION: + ducc_mbox_init(DUCC_ID_APP2NET_NORMAL, 1, 1); + ducc_mbox_init(DUCC_ID_NET2APP_NORMAL, 0, 1); + + ducc_mbox_init(DUCC_ID_APP2NET_DATA, 1, 1); + ducc_mbox_init(DUCC_ID_NET2APP_DATA, 0, 1); + + __asm(" dsb \n"); + __asm(" isb \n"); + DUCC_DBG("%s okay\n", __func__); + break; + default: + break; + } + + g_ducc_hw_mbox_suspending = 0; + + return 0; +} + +void hw_mbox_print_regs(void) +{ + //hex_dump_bytes(&hw_mbox_reg_store, sizeof(hw_mbox_reg_store)); +} + +static struct soc_device_driver ducc_hw_mbox_drv = { + .name = "hw_mbox", + .suspend = ducc_hw_mbox_suspend, + .resume = ducc_hw_mbox_resume, +}; + +static struct soc_device ducc_hw_mbox_dev = { + .name = "hw_mbox", + .driver = &ducc_hw_mbox_drv, +}; + +#define DUCC_HW_MBOX_DEV (&ducc_hw_mbox_dev) +#else +#define DUCC_HW_MBOX_DEV NULL +#endif + +int ducc_app_ioctl(enum ducc_app_cmd cmd, void *param) +{ + struct ducc_req req; + ducc_mutex_t *mutex; + uint32_t send_id, wait_id; + + DUCC_APP_DBG("send req %d\n", cmd); +#ifdef CONFIG_PM + if (g_ducc_hw_mbox_suspending) { + DUCC_ERR("send req %d when suspending\n", cmd); + return -1; + } +#endif + + if (DUCC_APP_IS_DATA_CMD(cmd)) { + mutex = &g_ducc_app_data_mutex; + send_id = DUCC_ID_APP2NET_DATA; + wait_id = DUCC_ID_NET2APP_DATA; + } else { + mutex = &g_ducc_app_normal_mutex; + send_id = DUCC_ID_APP2NET_NORMAL; + wait_id = DUCC_ID_NET2APP_NORMAL; + } + + ducc_mutex_lock(mutex); + +#if DUCC_SIMULATE_HW_MBOX + req.id = send_id; +#endif + req.cmd = (uint32_t)cmd; + req.param = (uint32_t)param; + req.result = -1; + + do { + if (DUCC_APP_REQ_SEND(send_id, &req) < 0) { + DUCC_WARN("send req %d failed\n", cmd); + break; + } + + DUCC_APP_DBG("wait req %d\n", cmd); + if (DUCC_APP_REQ_WAIT(wait_id) < 0) { + DUCC_WARN("wait req %d failed\n", cmd); + break; + } + } while (0); + + DUCC_APP_DBG("wait req %d done\n", cmd); + + ducc_mutex_unlock(mutex); + + return req.result; +} + +static volatile uint32_t ducc_app_normal_task_term; + +static void ducc_app_normal_task(void *arg) +{ + uint32_t recv_id = DUCC_ID_NET2APP_NORMAL; + uint32_t send_id = DUCC_ID_APP2NET_NORMAL; + void *net_req; + struct ducc_req *req; + struct ducc_param_efuse *efuse; + + while (1) { + net_req = DUCC_APP_REQ_RECV(recv_id); + + if (ducc_app_normal_task_term) + break; + + if (net_req == NULL) { + DUCC_WARN("invalid net req\n"); + continue; + } + + req = DUCC_APP_PTR(net_req); +#if DUCC_SIMULATE_HW_MBOX + if (req->id != recv_id) { + DUCC_WARN("invalid net req, id 0x%x\n", req->id); + continue; + } +#endif + DUCC_APP_DBG("exec req %d\n", req->cmd); + + switch (req->cmd) { +#if (__CONFIG_MBUF_IMPL_MODE == 1) + case DUCC_NET_CMD_MBUF_GET: + { + struct ducc_param_mbuf_get *p = DUCC_APP_PTR(req->param); + struct mbuf *m = mb_get(p->len, p->tx); + if (m) { + MBUF_APP2NET(m); + p->mbuf = m; + req->result = 0; + } else { + req->result = -1; + } + break; + } + case DUCC_NET_CMD_MBUF_FREE: + { + struct mbuf *m = (struct mbuf *)req->param; + MBUF_NET2APP(m); + mb_free(m); + req->result = 0; + break; + } +#endif /* (__CONFIG_MBUF_IMPL_MODE == 1) */ + case DUCC_NET_CMD_POWER_NOTIFY: + if (ducc_app_cb) + ducc_app_cb(req->cmd, req->param); + break; + case DUCC_NET_CMD_BIN_READ: + if (ducc_app_cb) { + struct ducc_param_wlan_bin *p = DUCC_APP_PTR(req->param); + p->buf = (void *)DUCC_NETMEM_NET2APP(p->buf); + req->result = ducc_app_cb(DUCC_NET_CMD_BIN_READ, (uint32_t)p); + p->buf = (void *)DUCC_NETMEM_APP2NET(p->buf); + } else { + req->result = 0; + } + break; + case DUCC_NET_CMD_EFUSE_READ: + efuse = DUCC_APP_PTR(req->param); + efuse->data = (void *)DUCC_NETMEM_NET2APP(efuse->data); + req->result = ducc_app_cb(DUCC_NET_CMD_EFUSE_READ, (uint32_t)efuse); + efuse->data = (void *)DUCC_NETMEM_APP2NET(efuse->data); + break; + case DUCC_NET_CMD_SYS_EVENT: + case DUCC_NET_CMD_WLAN_EVENT: + if (ducc_app_cb) + ducc_app_cb(req->cmd, req->param); + req->result = 0; + break; + default: + DUCC_WARN("invalid command %d\n", req->cmd); + break; + }; + + DUCC_APP_DBG("exec req %d done\n", req->cmd); + + DUCC_APP_REQ_SEND(send_id, DUCC_RELEASE_REQ_VAL(send_id)); + } + + ducc_app_normal_task_term = 0; + ducc_thread_exit(&g_ducc_app_normal_thread); +} + +static volatile uint32_t ducc_app_data_task_term; + +static void ducc_app_data_task(void *arg) +{ + uint32_t recv_id = DUCC_ID_NET2APP_DATA; + uint32_t send_id = DUCC_ID_APP2NET_DATA; + void *net_req; + struct ducc_req *req; + + while (1) { + net_req = DUCC_APP_REQ_RECV(recv_id); + + if (ducc_app_data_task_term) + break; + + if (net_req == NULL) { + DUCC_WARN("invalid net req\n"); + continue; + } + + req = DUCC_APP_PTR(net_req); +#if DUCC_SIMULATE_HW_MBOX + if (req->id != recv_id) { + DUCC_WARN("invalid net req, id 0x%x\n", req->id); + continue; + } +#endif + DUCC_APP_DBG("exec req %d\n", req->cmd); + + switch (req->cmd) { + case DUCC_NET_CMD_WLAN_INPUT: + { + struct ducc_param_wlan_input *p = DUCC_APP_PTR(req->param); +#if (__CONFIG_MBUF_IMPL_MODE == 0) + req->result = (ethernetif_raw_input(p->nif, + DUCC_APP_PTR(p->data), + p->len) == ERR_OK ? 0 : -1); +#elif (__CONFIG_MBUF_IMPL_MODE == 1) + struct mbuf *m; + struct pbuf *pb; + m = p->mbuf; + MBUF_NET2APP(m); + pb = mb_mbuf2pbuf(m); /* data including Ethernet header */ + mb_free(m); /* useless now, should be freed */ + req->result = (ethernetif_input(p->nif, pb) == ERR_OK ? 0 : -1); +#endif /* __CONFIG_MBUF_IMPL_MODE */ + break; + } + case DUCC_NET_CMD_WLAN_MONITOR_INPUT: + { + struct ducc_param_wlan_mon_input *p = DUCC_APP_PTR(req->param); + wlan_monitor_input(p->nif, DUCC_APP_PTR(p->data), p->len, + p->info ? DUCC_APP_PTR(p->info) : NULL); + req->result = 0; + break; + } + default: + DUCC_WARN("invalid command %d\n", req->cmd); + break; + }; + + DUCC_APP_DBG("exec req %d done\n", req->cmd); + + DUCC_APP_REQ_SEND(send_id, DUCC_RELEASE_REQ_VAL(send_id)); + } + + ducc_app_data_task_term = 0; + ducc_thread_exit(&g_ducc_app_data_thread); +} + +int ducc_app_start(struct ducc_app_param *param) +{ + ducc_app_cb = param->cb; + + ducc_mutex_create(&g_ducc_app_normal_mutex); + ducc_req_init(DUCC_ID_NET2APP_NORMAL); + ducc_mbox_init(DUCC_ID_APP2NET_NORMAL, 1, 0); + ducc_mbox_init(DUCC_ID_NET2APP_NORMAL, 0, 0); + + ducc_mutex_create(&g_ducc_app_data_mutex); + ducc_req_init(DUCC_ID_NET2APP_DATA); + ducc_mbox_init(DUCC_ID_APP2NET_DATA, 1, 0); + ducc_mbox_init(DUCC_ID_NET2APP_DATA, 0, 0); + + ducc_app_normal_task_term = 0; + if (ducc_thread_create(&g_ducc_app_normal_thread, + ducc_app_normal_task, + NULL, + DUCC_APP_NORMAL_THREAD_PRIO, + DUCC_APP_NORMAL_THREAD_STACK_SIZE) != 0) { + DUCC_ERR("create thread failed\n"); + return -1; + } + + ducc_app_data_task_term = 0; + if (ducc_thread_create(&g_ducc_app_data_thread, + ducc_app_data_task, + NULL, + DUCC_APP_DATA_THREAD_PRIO, + DUCC_APP_DATA_THREAD_STACK_SIZE) != 0) { + DUCC_ERR("create thread failed\n"); + return -1; + } +#ifdef CONFIG_PM + pm_register_ops(DUCC_HW_MBOX_DEV); +#endif + + return 0; +} + +int ducc_app_stop(void) +{ +#ifdef CONFIG_PM + pm_unregister_ops(DUCC_HW_MBOX_DEV); +#endif + + ducc_app_data_task_term = 1; + ducc_mbox_msg_callback(DUCC_ID_NET2APP_DATA, NULL); + while (ducc_app_data_task_term) + OS_MSleep(2); + + ducc_app_normal_task_term = 1; + ducc_mbox_msg_callback(DUCC_ID_NET2APP_NORMAL, NULL); + while (ducc_app_normal_task_term) + OS_MSleep(2); + + ducc_mbox_deinit(DUCC_ID_NET2APP_DATA, 0, 0); + ducc_mbox_deinit(DUCC_ID_APP2NET_DATA, 1, 0); + ducc_req_deinit(DUCC_ID_NET2APP_DATA); + ducc_mutex_delete(&g_ducc_app_data_mutex); + + ducc_mbox_deinit(DUCC_ID_NET2APP_NORMAL, 0, 0); + ducc_mbox_deinit(DUCC_ID_APP2NET_NORMAL, 1, 0); + ducc_req_deinit(DUCC_ID_NET2APP_NORMAL); + ducc_mutex_delete(&g_ducc_app_normal_mutex); + + ducc_app_cb = NULL; + + return 0; +} + +#endif /* (defined(__CONFIG_ARCH_DUAL_CORE) && defined(__CONFIG_ARCH_APP_CORE)) */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_debug.h b/platform/mcu/xr871/src/sys/ducc/ducc_debug.h new file mode 100644 index 0000000000..50e7a7ee9a --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_debug.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_DEBUG_H_ +#define _SYS_DUCC_DUCC_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUCC_DEBUG_ON 0 +#define DUCC_WARN_ON 1 +#define DUCC_ERR_ON 1 +#define DUCC_ABORT_ON 0 + +#define DUCC_DBG_WLAN 1 +#define DUCC_DBG_NET 1 +#define DUCC_DBG_APP 1 +#define DUCC_DBG_MBOX 1 +#define DUCC_DBG_HW_MBOX 1 + +#define DUCC_SYSLOG printf +#define DUCC_ABORT() sys_abort() + +#define DUCC_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + DUCC_SYSLOG(fmt, ##arg); \ + } while (0) + +#define DUCC_DBG(fmt, arg...) \ + DUCC_LOG(DUCC_DEBUG_ON, "[ducc] "fmt, ##arg) + +#define DUCC_WLAN_DBG(fmt, arg...) \ + DUCC_LOG(DUCC_DEBUG_ON && DUCC_DBG_WLAN, "[ducc wlan] "fmt, ##arg) + +#define DUCC_NET_DBG(fmt, arg...) \ + DUCC_LOG(DUCC_DEBUG_ON && DUCC_DBG_NET, "[ducc net] "fmt, ##arg) + +#define DUCC_APP_DBG(fmt, arg...) \ + DUCC_LOG(DUCC_DEBUG_ON && DUCC_DBG_APP, "[ducc app] "fmt, ##arg) + +#define DUCC_MBOX_DBG(fmt, arg...) \ + DUCC_LOG(DUCC_DEBUG_ON && DUCC_DBG_MBOX, "[ducc mbox] "fmt, ##arg) + +#define DUCC_HW_MBOX_DBG(fmt, arg...) \ + DUCC_LOG(DUCC_DEBUG_ON && DUCC_DBG_HW_MBOX, "[ducc hw-mbox] "fmt, ##arg) + +#define DUCC_WARN(fmt, arg...) \ + DUCC_LOG(DUCC_WARN_ON, "[ducc WARN] %s():%d, "fmt, __func__, __LINE__, ##arg) + +#define DUCC_ERR(fmt, arg...) \ + do { \ + DUCC_LOG(DUCC_ERR_ON, "[ducc ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (DUCC_ABORT_ON) \ + DUCC_ABORT(); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_hw_mbox.c b/platform/mcu/xr871/src/sys/ducc/ducc_hw_mbox.c new file mode 100644 index 0000000000..a1efc91723 --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_hw_mbox.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "driver/chip/hal_mbox.h" +#include "ducc_mbox.h" +#include "ducc_debug.h" + +#ifdef __CONFIG_ARCH_DUAL_CORE + +#define DUCC_OPT_HW_MBOX_PM_PATCH HAL_MBOX_PM_PATCH /* use MBOX_A only */ + +#if DUCC_OPT_HW_MBOX_PM_PATCH + +#define DUCC_HW_MBOX MBOX_A +#define DUCC_HW_MBOX_TX DUCC_HW_MBOX +#define DUCC_HW_MBOX_RX DUCC_HW_MBOX + +#ifdef __CONFIG_ARCH_APP_CORE + #define DUCC_HW_MBOX_SELF MBOX_USER0 + #define DUCC_HW_MBOX_OTHER MBOX_USER1 +#elif (defined(__CONFIG_ARCH_NET_CORE)) + #define DUCC_HW_MBOX_SELF MBOX_USER1 + #define DUCC_HW_MBOX_OTHER MBOX_USER0 +#endif /* __CONFIG_ARCH_APP_CORE */ + +uint8_t g_ducc_hw_mbox_init_cnt = 0; + +#ifdef __CONFIG_ARCH_APP_CORE + +int ducc_hw_mbox_init(uint32_t id, int is_tx) +{ + MBOX_Queue queue = (MBOX_Queue)id; + + if (g_ducc_hw_mbox_init_cnt++ == 0) { + HAL_MBOX_Init(DUCC_HW_MBOX); + HAL_MBOX_EnableIRQ(DUCC_HW_MBOX); + } + + if (is_tx) { + /* init sender and receiver of queue */ + HAL_MBOX_QueueInit(DUCC_HW_MBOX, DUCC_HW_MBOX_SELF, queue, MBOX_DIR_TX); + + /* enable receiver's irq */ + HAL_MBOX_QueueEnableIRQ(DUCC_HW_MBOX, DUCC_HW_MBOX_OTHER, queue, MBOX_DIR_RX); + } else { + /* init sender and receiver of queue */ + HAL_MBOX_QueueInit(DUCC_HW_MBOX, DUCC_HW_MBOX_SELF, queue, MBOX_DIR_RX); + + /* enable receiver's irq */ + HAL_MBOX_QueueEnableIRQ(DUCC_HW_MBOX, DUCC_HW_MBOX_SELF, queue, MBOX_DIR_RX); + } + + return 0; +} + +int ducc_hw_mbox_deinit(uint32_t id, int is_tx) +{ + MBOX_Queue queue = (MBOX_Queue)id; + + if (is_tx) { + HAL_MBOX_QueueDisableIRQ(DUCC_HW_MBOX, DUCC_HW_MBOX_OTHER, queue, MBOX_DIR_RX); + HAL_MBOX_QueueDeInit(DUCC_HW_MBOX, DUCC_HW_MBOX_SELF, queue, MBOX_DIR_TX); + + } else { + HAL_MBOX_QueueDisableIRQ(DUCC_HW_MBOX, DUCC_HW_MBOX_SELF, queue, MBOX_DIR_RX); + HAL_MBOX_QueueDeInit(DUCC_HW_MBOX, DUCC_HW_MBOX_SELF, queue, MBOX_DIR_RX); + } + + if ((g_ducc_hw_mbox_init_cnt > 0) && (--g_ducc_hw_mbox_init_cnt == 0)) { + HAL_MBOX_DisableIRQ(DUCC_HW_MBOX); + HAL_MBOX_DeInit(DUCC_HW_MBOX); + } + + return 0; +} + +#elif (defined(__CONFIG_ARCH_NET_CORE)) + +int ducc_hw_mbox_init(uint32_t id, int is_tx) +{ + if (g_ducc_hw_mbox_init_cnt++ == 0) { + HAL_MBOX_EnableIRQ(DUCC_HW_MBOX); + } + return 0; +} + +int ducc_hw_mbox_deinit(uint32_t id, int is_tx) +{ + if ((g_ducc_hw_mbox_init_cnt > 0) && (--g_ducc_hw_mbox_init_cnt == 0)) { + HAL_MBOX_DisableIRQ(DUCC_HW_MBOX); + } + return 0; +} + +#endif /* __CONFIG_ARCH_APP_CORE */ + +#else /* DUCC_OPT_HW_MBOX_PM_PATCH */ + +#ifdef __CONFIG_ARCH_APP_CORE + #define DUCC_HW_MBOX_TX MBOX_A + #define DUCC_HW_MBOX_TX_USER MBOX_USER0 + #define DUCC_HW_MBOX_RX MBOX_N + #define DUCC_HW_MBOX_RX_USER MBOX_USER1 +#elif (defined(__CONFIG_ARCH_NET_CORE)) + #define DUCC_HW_MBOX_TX MBOX_N + #define DUCC_HW_MBOX_TX_USER MBOX_USER0 + #define DUCC_HW_MBOX_RX MBOX_A + #define DUCC_HW_MBOX_RX_USER MBOX_USER1 +#endif /* __CONFIG_ARCH_APP_CORE */ + +uint8_t g_ducc_hw_mbox_enable = 0; + +int ducc_hw_mbox_init(uint32_t id, int is_tx) +{ + MBOX_T *mbox; + MBOX_User user; + MBOX_Queue queue; + MBOX_Direction dir; + + if (g_ducc_hw_mbox_enable == 0) { + HAL_MBOX_Init(DUCC_HW_MBOX_TX); + HAL_MBOX_Init(DUCC_HW_MBOX_RX); + g_ducc_hw_mbox_enable = 1; + } + + queue = (MBOX_Queue)id; + if (is_tx) { + mbox = DUCC_HW_MBOX_TX; + user = DUCC_HW_MBOX_TX_USER; + dir = MBOX_DIR_TX; + } else { + mbox = DUCC_HW_MBOX_RX; + user = DUCC_HW_MBOX_RX_USER; + dir = MBOX_DIR_RX; + } + HAL_MBOX_QueueInit(mbox, user, queue, dir); + if (!is_tx) { + HAL_MBOX_QueueEnableIRQ(mbox, user, queue, dir); + } + + return 0; +} + +int ducc_hw_mbox_deinit(uint32_t id, int is_tx) +{ + MBOX_T *mbox; + MBOX_User user; + MBOX_Queue queue; + MBOX_Direction dir; + + queue = (MBOX_Queue)id; + if (is_tx) { + mbox = DUCC_HW_MBOX_TX; + user = DUCC_HW_MBOX_TX_USER; + dir = MBOX_DIR_TX; + } else { + mbox = DUCC_HW_MBOX_RX; + user = DUCC_HW_MBOX_RX_USER; + dir = MBOX_DIR_RX; + } + if (!is_tx) { + HAL_MBOX_QueueDisableIRQ(mbox, user, queue, dir); + } + HAL_MBOX_QueueDeInit(mbox, user, queue, dir); + + if (g_ducc_hw_mbox_enable == 1) { + HAL_MBOX_DeInit(DUCC_HW_MBOX_TX); + HAL_MBOX_DeInit(DUCC_HW_MBOX_RX); + g_ducc_hw_mbox_enable = 0; + } + + return 0; +} + +#endif /* DUCC_OPT_HW_MBOX_PM_PATCH */ + +int ducc_hw_mbox_send(uint32_t id, void *msg) +{ + MBOX_T *mbox = DUCC_HW_MBOX_TX; + MBOX_Queue queue = (MBOX_Queue)id; +#if DUCC_WARN_ON + int i = 0; +#endif + + while (HAL_MBOX_QueueIsFull(mbox, queue)) { +#if DUCC_WARN_ON + if (++i > 1000) { + DUCC_WARN("h/w mbox %d (%p) is full\n", queue, mbox); + i = 0; + } +#endif + } + + HAL_MBOX_QueuePutMsg(mbox, queue, (uint32_t)msg); + return 0; +} + +#if 0 +int ducc_hw_mbox_recv(uint32_t id, void **msg) +{ + MBOX_T *mbox = DUCC_HW_MBOX_RX; + MBOX_Queue queue = (MBOX_Queue)id; + + if (HAL_MBOX_QueueGetMsgNum(mbox, queue) > 0) { + *msg = (void *)HAL_MBOX_QueueGetMsg(queue); + return 0; + } + + DUCC_WARN("h/w mbox %d (%p) is empty\n", queue, mbox); + return -1; +} +#endif + +void MBOX_IRQCallback(MBOX_T *mbox, MBOX_Queue queue, MBOX_Direction dir) +{ + uint32_t id = queue; + void *msg; + + DUCC_HW_MBOX_DBG("%s(), mbox %p, queue %d, dir %d\n", __func__, mbox, queue, dir); + + if (dir == MBOX_DIR_RX) { + if (mbox != DUCC_HW_MBOX_RX) { + DUCC_WARN("mbox %p != %p (rx mbox)\n", mbox, DUCC_HW_MBOX_RX); + return; + } + + if (HAL_MBOX_QueueGetMsgNum(mbox, queue) > 0) { + msg = (void *)HAL_MBOX_QueueGetMsg(mbox, queue); + } else { + DUCC_WARN("h/w mbox %d (%p) is empty\n", queue, mbox); + return; + } + +#if 0 // only for test + DUCC_HW_MBOX_DBG("%s(), queue %d, dir %d, msg %u\n", __func__, queue, dir, (uint32_t)msg); + return; +#endif + ducc_mbox_msg_callback(id, msg); + } else { + DUCC_WARN("mbox %p tx irq!\n", mbox); + } +} + +#endif /* __CONFIG_ARCH_DUAL_CORE */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_hw_mbox.h b/platform/mcu/xr871/src/sys/ducc/ducc_hw_mbox.h new file mode 100644 index 0000000000..51d5f2069f --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_hw_mbox.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_HW_MBOX_H_ +#define _SYS_DUCC_DUCC_HW_MBOX_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int ducc_hw_mbox_init(uint32_t id, int is_tx); +int ducc_hw_mbox_deinit(uint32_t id, int is_tx); +int ducc_hw_mbox_send(uint32_t id, void *msg); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_HW_MBOX_H_ */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_mbox.c b/platform/mcu/xr871/src/sys/ducc/ducc_mbox.c new file mode 100644 index 0000000000..bdef4d9a5f --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_mbox.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ducc.h" +#include "ducc_os.h" +#include "ducc_debug.h" +#include "ducc_hw_mbox.h" + + +/* + * ducc mbox is used to buffer/receive message from another cpu core. + */ + +#define DUCC_MBOX_SIZE 8 +#define DUCC_MBOX_NUM DUCC_TYPE_NUM + +static ducc_msgqueue_t ducc_mbox[DUCC_MBOX_NUM]; + +#ifdef __CONFIG_ARCH_APP_CORE +static ducc_msgqueue_t *g_ducc_mbox[DUCC_ID_NUM] = { + [DUCC_ID_APP2NET_NORMAL] = NULL, + [DUCC_ID_APP2NET_DATA] = NULL, + [DUCC_ID_NET2APP_NORMAL] = &ducc_mbox[0], + [DUCC_ID_NET2APP_DATA] = &ducc_mbox[1], +}; +#elif (defined(__CONFIG_ARCH_NET_CORE)) +static ducc_msgqueue_t *g_ducc_mbox[DUCC_ID_NUM] = { + [DUCC_ID_APP2NET_NORMAL] = &ducc_mbox[0], + [DUCC_ID_APP2NET_DATA] = &ducc_mbox[1], + [DUCC_ID_NET2APP_NORMAL] = NULL, + [DUCC_ID_NET2APP_DATA] = NULL, +}; +#endif /* __CONFIG_ARCH_APP_CORE */ + +int ducc_mbox_init(uint32_t id, int is_tx, uint32_t suspending) +{ + if (id >= DUCC_ID_NUM) { + DUCC_ERR("invalid mbox id 0x%x\n", id); + return -1; + } + + if (ducc_hw_mbox_init(id, is_tx) != 0) { + return -1; + } + + if (is_tx || suspending) + return 0; + + ducc_msgqueue_t *mbox = g_ducc_mbox[id]; + + if (ducc_msgqueue_is_valid(mbox)) { + DUCC_MBOX_DBG("mbox 0x%x already inited\n", id); + return 0; + } + + if (ducc_msgqueue_create(mbox, DUCC_MBOX_SIZE) != 0) { + DUCC_ERR("ducc_msgqueue_create() failed\n"); + return -1; + } + + return 0; +} + +int ducc_mbox_deinit(uint32_t id, int is_tx, uint32_t suspending) +{ + if (id >= DUCC_ID_NUM) { + DUCC_ERR("invalid mbox id 0x%x\n", id); + return -1; + } + + if (ducc_hw_mbox_deinit(id, is_tx) != 0) { + return -1; + } + + if (is_tx || suspending) + return 0; + + ducc_msgqueue_t *mbox = g_ducc_mbox[id]; + + if (!ducc_msgqueue_is_valid(mbox)) { + DUCC_MBOX_DBG("mbox 0x%x already deinited\n", id); + return 0; + } + + ducc_msgqueue_delete(mbox); + + return 0; +} + +int ducc_mbox_send(uint32_t id, void *msg) +{ + if (ducc_hw_mbox_send(id, msg) != 0) { + DUCC_ERR("ducc_hw_mbox_send() failed, id 0x%x\n", id); + return -1; + } + return 0; +} + +void *ducc_mbox_recv(uint32_t id, uint32_t timeout) +{ + void *msg; + int ret = ducc_msgqueue_recv(g_ducc_mbox[id], &msg, timeout); + return (ret == 0 ? msg : NULL); +} + +void ducc_mbox_msg_callback(uint32_t id, void *msg) +{ + if (msg == DUCC_RELEASE_REQ_VAL(id)) { + ducc_req_release(id); + return; + } + + if (ducc_msgqueue_send(g_ducc_mbox[id], msg, 0) != 0) { + DUCC_ERR("ducc_msgqueue_send() failed, id %u\n", id); + } +} diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_mbox.h b/platform/mcu/xr871/src/sys/ducc/ducc_mbox.h new file mode 100644 index 0000000000..388228810e --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_mbox.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_MBOX_H_ +#define _SYS_DUCC_DUCC_MBOX_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int ducc_mbox_init(uint32_t id, int is_tx, uint32_t suspending); +int ducc_mbox_deinit(uint32_t id, int is_tx, uint32_t suspending); +int ducc_mbox_send(uint32_t id, void *msg); +void *ducc_mbox_recv(uint32_t id, uint32_t timeout); +void ducc_mbox_msg_callback(uint32_t id, void *msg); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_MBOX_H_ */ diff --git a/platform/mcu/xr871/src/sys/ducc/ducc_os.h b/platform/mcu/xr871/src/sys/ducc/ducc_os.h new file mode 100644 index 0000000000..4b82e29aa0 --- /dev/null +++ b/platform/mcu/xr871/src/sys/ducc/ducc_os.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SYS_DUCC_DUCC_OS_H_ +#define _SYS_DUCC_DUCC_OS_H_ + +#include "kernel/os/os.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUCC_WAIT_FOREVER OS_WAIT_FOREVER +#define DUCC_OS_OK OS_OK + +/* Semaphore */ +typedef OS_Semaphore_t ducc_semaphore_t; + +static __inline int ducc_semaphore_create(ducc_semaphore_t *sem, uint32_t initCount) +{ + return OS_SemaphoreCreate(sem, initCount, OS_SEMAPHORE_MAX_COUNT) == OS_OK ? 0 : -1; +} + +static __inline void ducc_semaphore_delete(ducc_semaphore_t *sem) +{ + OS_SemaphoreDelete(sem); +} + +static __inline int ducc_semaphore_wait(ducc_semaphore_t *sem) +{ + return OS_SemaphoreWait(sem, OS_WAIT_FOREVER) == OS_OK ? 0 : -1; +} + +static __inline void ducc_semaphore_release(ducc_semaphore_t *sem) +{ + OS_SemaphoreRelease(sem); +} + +/* Mutex */ +typedef OS_Mutex_t ducc_mutex_t; + +static __inline int ducc_mutex_create(ducc_mutex_t *mtx) +{ + return OS_MutexCreate(mtx) == OS_OK ? 0 : -1; +} + +static __inline void ducc_mutex_delete(ducc_mutex_t *mtx) +{ + OS_MutexDelete(mtx); +} + +static __inline void ducc_mutex_lock(ducc_mutex_t *mtx) +{ + OS_MutexLock(mtx, OS_WAIT_FOREVER); +} + +static __inline void ducc_mutex_unlock(ducc_mutex_t *mtx) +{ + OS_MutexUnlock(mtx); +} + +/* Message Queue */ +typedef OS_Queue_t ducc_msgqueue_t; + +static __inline int ducc_msgqueue_create(ducc_msgqueue_t *queue, uint32_t queueLen) +{ + return OS_MsgQueueCreate(queue, queueLen) == OS_OK ? 0 : -1; +} + +static __inline void ducc_msgqueue_delete(ducc_msgqueue_t *queue) +{ + OS_MsgQueueDelete(queue); +} + +static __inline int ducc_msgqueue_send(ducc_msgqueue_t *queue, void *msg, uint32_t waitMS) +{ + return OS_MsgQueueSend(queue, msg, waitMS) == OS_OK ? 0 : -1; +} + +static __inline int ducc_msgqueue_recv(ducc_msgqueue_t *queue, void **msg, uint32_t waitMS) +{ + return OS_MsgQueueReceive(queue, msg, waitMS) == OS_OK ? 0 : -1; +} + +static __inline int ducc_msgqueue_is_valid(ducc_msgqueue_t *queue) +{ + return OS_QueueIsValid(queue); +} + +/* Thread */ +typedef OS_Thread_t ducc_thread_t; +typedef OS_ThreadEntry_t ducc_thread_entry_t; + +static __inline int ducc_thread_create(ducc_thread_t *thread, + ducc_thread_entry_t entry, void *arg, + int priority, uint32_t stack_size) +{ + return OS_ThreadCreate(thread, "", entry, arg, priority, stack_size)== OS_OK ? 0 : -1; +} + +static __inline void ducc_thread_exit(ducc_thread_t *thread) +{ + OS_ThreadDelete(thread); +} + +/* memory */ +//#define ducc_malloc(l) malloc(l) +//#define ducc_free(p) free(p) +#define ducc_memcpy(d, s, l) memcpy(d, s, l) +#define ducc_memset(d, c, l) memset(d, c, l) +#define ducc_memcmp(a, b, l) memcmp(a, b, l) +#define ducc_memmove(d, s, n) memmove(d, s, n) +#define ducc_strcmp(a, b) strcmp(a, b) + + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_DUCC_DUCC_OS_H_ */ diff --git a/platform/mcu/xr871/src/sys/mbuf/mbuf_1.c b/platform/mcu/xr871/src/sys/mbuf/mbuf_1.c new file mode 100644 index 0000000000..ccf2e2a24d --- /dev/null +++ b/platform/mcu/xr871/src/sys/mbuf/mbuf_1.c @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if (__CONFIG_MBUF_IMPL_MODE == 1) + +#include "sys/mbuf_1.h" +#include "mbuf_util.h" + +#if (defined(__CONFIG_ARCH_APP_CORE) || !defined(__CONFIG_ARCH_DUAL_CORE)) + +#include "lwip/pbuf.h" +#include "lwip/mem.h" +#include "lwip/memp.h" + +/* Init mbuf data info from pbuf, no sanity checks */ +static void mb_data_init(struct mbuf *m, struct pbuf *p) +{ + m->m_pbuf = p; + m->m_data = p->payload; + m->m_len = p->tot_len; + m->m_pkthdr.len = p->tot_len; + m->m_headspace = pbuf_head_space(p); + if (p->mb_flags & PBUF_FLAG_MBUF_SPACE) + m->m_tailspace = MBUF_TAIL_SPACE; + p->mb_flags |= PBUF_FLAG_MBUF_REF; +} + +/* + * Alloc a new mbuf without pbuf, zero the header. + */ +static struct mbuf *mb_alloc() +{ + struct mbuf *m = memp_malloc(MEMP_MBUF); + if (m) { + MB_MEMSET(m, 0, sizeof(struct mbuf)); + m->m_flags = M_PKTHDR; + } else { + MBUF_WRN("Out of memory in pbuf pool for mbuf\n"); + } + return m; +} + +/* + * @param tx + * - 1 means mbuf is used to do Tx, always alloc it from PBUF_RAM. + * - 0 means mbuf is used to do RX, try to alloc it from PBUF_POOL first + * @return a mbuf including @len data + */ +struct mbuf *mb_get(int len, int tx) +{ + if (len < 0) + return NULL; + + if (len > PBUF_POOL_BUFSIZE) { + MBUF_WRN("try to get large data, len %d\n", len); + } + + struct mbuf *m = mb_alloc(); + if (m == NULL) { + return NULL; + } + + struct pbuf *p; +#if LWIP_PBUF_POOL_SMALL + int pbuf_pool_small = 0; +#endif + int tot_len = len; + pbuf_type type = (tx || len > PBUF_POOL_BUFSIZE) ? PBUF_RAM : PBUF_POOL; + if (type == PBUF_RAM) { + /* space is not reserved after pbuf_alloc(), add more space */ + tot_len += MBUF_HEAD_SPACE + MBUF_TAIL_SPACE; + } +#if LWIP_PBUF_POOL_SMALL + else if (len <= PBUF_POOL_SMALL_BUFSIZE) { + pbuf_pool_small = 1; + } + +retry: + p = pbuf_alloc_ext(PBUF_MBUF_RAW, tot_len, type, pbuf_pool_small); + if (p == NULL) { + MBUF_DBG("pbuf_alloc_ext() failed, tot_len %d, type %d, small %d\n", + tot_len, type, pbuf_pool_small); + if (pbuf_pool_small) { + /* try to get pbuf from bigger pbuf pools */ + pbuf_pool_small = 0; + goto retry; + } + mb_free(m); + return NULL; + } +#else /* LWIP_PBUF_POOL_SMALL */ + p = pbuf_alloc(PBUF_MBUF_RAW, tot_len, type); + if (p == NULL) { + MBUF_DBG("pbuf_alloc() failed, tot_len %d, type %d\n", tot_len, type); + mb_free(m); + return NULL; + } +#endif /* LWIP_PBUF_POOL_SMALL */ + if (type == PBUF_RAM) { + /* reserved head and tail space of pbuf */ + pbuf_header(p, -MBUF_HEAD_SPACE); + p->len -= MBUF_TAIL_SPACE; + p->tot_len -= MBUF_TAIL_SPACE; + p->mb_flags |= PBUF_FLAG_MBUF_SPACE; + } + + mb_data_init(m, p); + return m; +} + +/* + * Free a mbuf. + */ +void mb_free(struct mbuf *m) +{ + if (m == NULL) { + MBUF_WRN("mb_free(), m is NULL\n"); + return; + } + + struct pbuf *p = m->m_pbuf; + if (p) { + p->mb_flags &= ~PBUF_FLAG_MBUF_REF; + pbuf_free(p); + } + memp_free(MEMP_MBUF, m); +} + +/* + * Create a new mbuf including all pbuf data. + */ +struct mbuf *mb_pbuf2mbuf(void *p) +{ + struct pbuf *pb = p; + struct mbuf *m; + + if ((pbuf_clen(pb) > 1) || ((pb->mb_flags & PBUF_FLAG_MBUF_SPACE) == 0)) { + /* copy all data from @pb to a new single pbuf */ + m = mb_get(pb->tot_len, 1); + if (m == NULL) + return NULL; + + if (pbuf_copy_partial(pb, m->m_data, pb->tot_len, 0) != pb->tot_len) { + mb_free(m); + return NULL; + } + } else { + /* no need to copy data, link @pb to a new mbuf header */ + m = mb_alloc(); + if (m == NULL) + return NULL; + + pbuf_ref(pb); /* @pb is referenced by @m now */ + mb_data_init(m, pb); + } + return m; +} + +/* + * Return a pbuf included in a mbuf + */ +void *mb_mbuf2pbuf(struct mbuf *m) +{ + struct pbuf *p = m->m_pbuf; + + p->payload = m->m_data; + p->tot_len = m->m_len; + p->len = m->m_len; + if (m->m_tailspace >= MBUF_TAIL_SPACE) + p->mb_flags |= PBUF_FLAG_MBUF_SPACE; + pbuf_ref(p); /* add reference to avoid freed from @m */ + return p; +} + +#endif /* (defined(__CONFIG_ARCH_APP_CORE) || !defined(__CONFIG_ARCH_DUAL_CORE)) */ +#endif /* (__CONFIG_MBUF_IMPL_MODE == 1) */ diff --git a/platform/mcu/xr871/src/sys/mbuf/mbuf_debug.h b/platform/mcu/xr871/src/sys/mbuf/mbuf_debug.h new file mode 100644 index 0000000000..f461474c79 --- /dev/null +++ b/platform/mcu/xr871/src/sys/mbuf/mbuf_debug.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MBUF_DEBUG_H_ +#define _MBUF_DEBUG_H_ + +#include +#include "sys/xr_util.h" + +/* + * Debug + */ +#define MBUF_DBG_ON 0 +#define MBUF_WRN_ON 0 +#define MBUF_ERR_ON 1 +#define MBUF_ABORT_ON 0 + +#define MBUF_SYSLOG printf +#define MBUF_ABORT() sys_abort() + +#define MBUF_LOG(flags, fmt, arg...) \ + do { \ + if (flags) \ + MBUF_SYSLOG(fmt, ##arg); \ + } while (0) + +#define MBUF_DBG(fmt, arg...) MBUF_LOG(MBUF_DBG_ON, "[mbuf] "fmt, ##arg) +#define MBUF_WRN(fmt, arg...) MBUF_LOG(MBUF_WRN_ON, "[mbuf WRN] "fmt, ##arg) +#define MBUF_ERR(fmt, arg...) \ + do { \ + MBUF_LOG(MBUF_ERR_ON, "[mbuf ERR] %s():%d, "fmt, \ + __func__, __LINE__, ##arg); \ + if (MBUF_ABORT_ON) \ + MBUF_ABORT(); \ + } while (0) + +#endif /* _MBUF_DEBUG_H_ */ diff --git a/platform/mcu/xr871/src/sys/mbuf/mbuf_util.h b/platform/mcu/xr871/src/sys/mbuf/mbuf_util.h new file mode 100644 index 0000000000..6293fbebb6 --- /dev/null +++ b/platform/mcu/xr871/src/sys/mbuf/mbuf_util.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MBUF_UTIL_H_ +#define _MBUF_UTIL_H_ + +#include +#include "mbuf_debug.h" + +/* + * Memory + */ +#define MB_MEMCPY(d, s, l) memcpy(d, s, l) +#define MB_MEMSET(d, c, l) memset(d, c, l) +#define MB_MEMCMP(a, b, l) memcmp(a, b, l) +#define MB_MEMMOVE(d, s, n) memmove(d, s, n) + +#endif /* _MBUF_UTIL_H_ */ diff --git a/platform/mcu/xr871/src/sys/sys.mk b/platform/mcu/xr871/src/sys/sys.mk new file mode 100644 index 0000000000..771fb0fafc --- /dev/null +++ b/platform/mcu/xr871/src/sys/sys.mk @@ -0,0 +1,11 @@ +NAME := sys + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := ducc/ducc.c \ + ducc/ducc_app.c \ + ducc/ducc_hw_mbox.c \ + ducc/ducc_mbox.c \ + mbuf/mbuf_1.c + + + diff --git a/platform/mcu/xr871/src/xz/decompress.c b/platform/mcu/xr871/src/xz/decompress.c new file mode 100644 index 0000000000..d1661d2036 --- /dev/null +++ b/platform/mcu/xr871/src/xz/decompress.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "xz/decompress.h" + +static struct xz_dec *s; + +int xz_uncompress_init(struct xz_buf *stream) +{ + xz_crc32_init(); + /* + * Support up to 32 KiB dictionary. The actually needed memory + * is allocated once the headers have been parsed. + */ + s = xz_dec_init(XZ_DYNALLOC, 1 << 15); + if (s == NULL) { + return -1; + } + + stream->in_pos = 0; + stream->in_size = 0; + stream->out_pos = 0; + stream->out_size = 0; + + return 1; +} + +int xz_uncompress_stream(struct xz_buf *stream, uint8_t *sbuf, uint32_t slen, + uint8_t *dbuf, uint32_t dlen, uint32_t *decomp_len) +{ + int status; + *decomp_len = 0; + + stream->in = sbuf; + stream->out = dbuf; + + if (stream->in_pos == stream->in_size) { + stream->in_size = slen; + stream->in_pos = 0; + } + + stream->out_size = dlen; + stream->out_pos = 0; + + status = xz_dec_run(s, stream); + + *decomp_len = stream->out_pos; + + return status; +} + +void xz_uncompress_end() +{ + xz_dec_end(s); +} + +static size_t xz_len_decode(const uint8_t buf[], size_t size_max, uint32_t *num) +{ + if (size_max == 0) + return 0; + + if (size_max > 9) + size_max = 9; + + *num = buf[0] & 0x7F; + size_t i = 0; + + while (buf[i++] & 0x80) { + if (i >= size_max || buf[i] == 0x00) + return 0; + + *num |= (uint32_t)(buf[i] & 0x7F) << (i * 7); + } + + return i; +} + +uint32_t xz_index_len(uint8_t *stream_footer) +{ + + uint32_t len = (stream_footer[7] << 24) + + (stream_footer[6] << 16) + + (stream_footer[5] << 8) + + stream_footer[4]; + return (len + 1) * 4; +} + +uint32_t xz_file_uncompress_size(uint8_t *index, uint32_t len) +{ + uint32_t num_len = 0; + uint32_t uncompress_size = 0; + uint8_t *temp = &index[1]; + + num_len += xz_len_decode(temp, len, &uncompress_size); + num_len += xz_len_decode(&temp[num_len], len - num_len, &uncompress_size); + xz_len_decode(&temp[num_len], len - num_len, &uncompress_size); + return uncompress_size; +} diff --git a/platform/mcu/xr871/src/xz/xz.h b/platform/mcu/xr871/src/xz/xz.h new file mode 100644 index 0000000000..d94d68bc42 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz.h @@ -0,0 +1,286 @@ +/* + * XZ decompressor + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_H +#define XZ_H + +#ifdef __KERNEL__ +# include +# include +# include +#else +# include +# include +# include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* In Linux, this is used to make extern functions static when needed. */ +#ifndef XZ_EXTERN +# define XZ_EXTERN extern +#endif + +/** + * enum xz_mode - Operation mode + * + * @XZ_SINGLE: Single-call mode. This uses less RAM than + * than multi-call modes, because the LZMA2 + * dictionary doesn't need to be allocated as + * part of the decoder state. All required data + * structures are allocated at initialization, + * so xz_dec_run() cannot return XZ_MEM_ERROR. + * @XZ_PREALLOC: Multi-call mode with preallocated LZMA2 + * dictionary buffer. All data structures are + * allocated at initialization, so xz_dec_run() + * cannot return XZ_MEM_ERROR. + * @XZ_DYNALLOC: Multi-call mode. The LZMA2 dictionary is + * allocated once the required size has been + * parsed from the stream headers. If the + * allocation fails, xz_dec_run() will return + * XZ_MEM_ERROR. + * + * It is possible to enable support only for a subset of the above + * modes at compile time by defining XZ_DEC_SINGLE, XZ_DEC_PREALLOC, + * or XZ_DEC_DYNALLOC. The xz_dec kernel module is always compiled + * with support for all operation modes, but the preboot code may + * be built with fewer features to minimize code size. + */ +enum xz_mode { + XZ_SINGLE, + XZ_PREALLOC, + XZ_DYNALLOC +}; + +/** + * enum xz_ret - Return codes + * @XZ_OK: Everything is OK so far. More input or more + * output space is required to continue. This + * return code is possible only in multi-call mode + * (XZ_PREALLOC or XZ_DYNALLOC). + * @XZ_STREAM_END: Operation finished successfully. + * @XZ_UNSUPPORTED_CHECK: Integrity check type is not supported. Decoding + * is still possible in multi-call mode by simply + * calling xz_dec_run() again. + * Note that this return value is used only if + * XZ_DEC_ANY_CHECK was defined at build time, + * which is not used in the kernel. Unsupported + * check types return XZ_OPTIONS_ERROR if + * XZ_DEC_ANY_CHECK was not defined at build time. + * @XZ_MEM_ERROR: Allocating memory failed. This return code is + * possible only if the decoder was initialized + * with XZ_DYNALLOC. The amount of memory that was + * tried to be allocated was no more than the + * dict_max argument given to xz_dec_init(). + * @XZ_MEMLIMIT_ERROR: A bigger LZMA2 dictionary would be needed than + * allowed by the dict_max argument given to + * xz_dec_init(). This return value is possible + * only in multi-call mode (XZ_PREALLOC or + * XZ_DYNALLOC); the single-call mode (XZ_SINGLE) + * ignores the dict_max argument. + * @XZ_FORMAT_ERROR: File format was not recognized (wrong magic + * bytes). + * @XZ_OPTIONS_ERROR: This implementation doesn't support the requested + * compression options. In the decoder this means + * that the header CRC32 matches, but the header + * itself specifies something that we don't support. + * @XZ_DATA_ERROR: Compressed data is corrupt. + * @XZ_BUF_ERROR: Cannot make any progress. Details are slightly + * different between multi-call and single-call + * mode; more information below. + * + * In multi-call mode, XZ_BUF_ERROR is returned when two consecutive calls + * to XZ code cannot consume any input and cannot produce any new output. + * This happens when there is no new input available, or the output buffer + * is full while at least one output byte is still pending. Assuming your + * code is not buggy, you can get this error only when decoding a compressed + * stream that is truncated or otherwise corrupt. + * + * In single-call mode, XZ_BUF_ERROR is returned only when the output buffer + * is too small or the compressed input is corrupt in a way that makes the + * decoder produce more output than the caller expected. When it is + * (relatively) clear that the compressed input is truncated, XZ_DATA_ERROR + * is used instead of XZ_BUF_ERROR. + */ +enum xz_ret { + XZ_OK, + XZ_STREAM_END, + XZ_UNSUPPORTED_CHECK, + XZ_MEM_ERROR, + XZ_MEMLIMIT_ERROR, + XZ_FORMAT_ERROR, + XZ_OPTIONS_ERROR, + XZ_DATA_ERROR, + XZ_BUF_ERROR +}; + +/** + * struct xz_buf - Passing input and output buffers to XZ code + * @in: Beginning of the input buffer. This may be NULL if and only + * if in_pos is equal to in_size. + * @in_pos: Current position in the input buffer. This must not exceed + * in_size. + * @in_size: Size of the input buffer + * @out: Beginning of the output buffer. This may be NULL if and only + * if out_pos is equal to out_size. + * @out_pos: Current position in the output buffer. This must not exceed + * out_size. + * @out_size: Size of the output buffer + * + * Only the contents of the output buffer from out[out_pos] onward, and + * the variables in_pos and out_pos are modified by the XZ code. + */ +struct xz_buf { + const uint8_t *in; + size_t in_pos; + size_t in_size; + + uint8_t *out; + size_t out_pos; + size_t out_size; +}; + +/** + * struct xz_dec - Opaque type to hold the XZ decoder state + */ +struct xz_dec; + +/** + * xz_dec_init() - Allocate and initialize a XZ decoder state + * @mode: Operation mode + * @dict_max: Maximum size of the LZMA2 dictionary (history buffer) for + * multi-call decoding. This is ignored in single-call mode + * (mode == XZ_SINGLE). LZMA2 dictionary is always 2^n bytes + * or 2^n + 2^(n-1) bytes (the latter sizes are less common + * in practice), so other values for dict_max don't make sense. + * In the kernel, dictionary sizes of 64 KiB, 128 KiB, 256 KiB, + * 512 KiB, and 1 MiB are probably the only reasonable values, + * except for kernel and initramfs images where a bigger + * dictionary can be fine and useful. + * + * Single-call mode (XZ_SINGLE): xz_dec_run() decodes the whole stream at + * once. The caller must provide enough output space or the decoding will + * fail. The output space is used as the dictionary buffer, which is why + * there is no need to allocate the dictionary as part of the decoder's + * internal state. + * + * Because the output buffer is used as the workspace, streams encoded using + * a big dictionary are not a problem in single-call mode. It is enough that + * the output buffer is big enough to hold the actual uncompressed data; it + * can be smaller than the dictionary size stored in the stream headers. + * + * Multi-call mode with preallocated dictionary (XZ_PREALLOC): dict_max bytes + * of memory is preallocated for the LZMA2 dictionary. This way there is no + * risk that xz_dec_run() could run out of memory, since xz_dec_run() will + * never allocate any memory. Instead, if the preallocated dictionary is too + * small for decoding the given input stream, xz_dec_run() will return + * XZ_MEMLIMIT_ERROR. Thus, it is important to know what kind of data will be + * decoded to avoid allocating excessive amount of memory for the dictionary. + * + * Multi-call mode with dynamically allocated dictionary (XZ_DYNALLOC): + * dict_max specifies the maximum allowed dictionary size that xz_dec_run() + * may allocate once it has parsed the dictionary size from the stream + * headers. This way excessive allocations can be avoided while still + * limiting the maximum memory usage to a sane value to prevent running the + * system out of memory when decompressing streams from untrusted sources. + * + * On success, xz_dec_init() returns a pointer to struct xz_dec, which is + * ready to be used with xz_dec_run(). If memory allocation fails, + * xz_dec_init() returns NULL. + */ +XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max); + +/** + * xz_dec_run() - Run the XZ decoder + * @s: Decoder state allocated using xz_dec_init() + * @b: Input and output buffers + * + * The possible return values depend on build options and operation mode. + * See enum xz_ret for details. + * + * Note that if an error occurs in single-call mode (return value is not + * XZ_STREAM_END), b->in_pos and b->out_pos are not modified and the + * contents of the output buffer from b->out[b->out_pos] onward are + * undefined. This is true even after XZ_BUF_ERROR, because with some filter + * chains, there may be a second pass over the output buffer, and this pass + * cannot be properly done if the output buffer is truncated. Thus, you + * cannot give the single-call decoder a too small buffer and then expect to + * get that amount valid data from the beginning of the stream. You must use + * the multi-call decoder if you don't want to uncompress the whole stream. + */ +XZ_EXTERN enum xz_ret xz_dec_run(struct xz_dec *s, struct xz_buf *b); + +/** + * xz_dec_reset() - Reset an already allocated decoder state + * @s: Decoder state allocated using xz_dec_init() + * + * This function can be used to reset the multi-call decoder state without + * freeing and reallocating memory with xz_dec_end() and xz_dec_init(). + * + * In single-call mode, xz_dec_reset() is always called in the beginning of + * xz_dec_run(). Thus, explicit call to xz_dec_reset() is useful only in + * multi-call mode. + */ +XZ_EXTERN void xz_dec_reset(struct xz_dec *s); + +/** + * xz_dec_end() - Free the memory allocated for the decoder state + * @s: Decoder state allocated using xz_dec_init(). If s is NULL, + * this function does nothing. + */ +XZ_EXTERN void xz_dec_end(struct xz_dec *s); + +/* + * Standalone build (userspace build or in-kernel build for boot time use) + * needs a CRC32 implementation. For normal in-kernel use, kernel's own + * CRC32 module is used instead, and users of this module don't need to + * care about the functions below. + */ +#ifndef XZ_INTERNAL_CRC32 +# ifdef __KERNEL__ +# define XZ_INTERNAL_CRC32 0 +# else +# define XZ_INTERNAL_CRC32 1 +# endif +#endif + +#if XZ_INTERNAL_CRC32 +/* + * This must be called before any other xz_* function to initialize + * the CRC32 lookup table. + */ +XZ_EXTERN void xz_crc32_init(void); + +/* + * Update CRC32 value using the polynomial from IEEE-802.3. To start a new + * calculation, the third argument must be zero. To continue the calculation, + * the previously returned value is passed as the third argument. + */ +XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc); +#endif + +#ifdef __cplusplus +} +#endif + +/* This function verifies if the input buffer matches the xz header. + * If so, it returns 0 else -1 */ +static inline int verify_xz_header(uint8_t *buffer) +{ + const uint8_t xz_header[6] = { 0xFD, '7', 'z', 'X', 'Z', 0x00 }; + if (buffer) { + if (!memcmp(buffer, xz_header, 6)) + return 0; + } + return -1; +} +#endif diff --git a/platform/mcu/xr871/src/xz/xz.mk b/platform/mcu/xr871/src/xz/xz.mk new file mode 100644 index 0000000000..71229bdda5 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz.mk @@ -0,0 +1,7 @@ +NAME := xz + +$(NAME)_TYPE := kernel +$(NAME)_SOURCES := decompress.c \ + xz_crc32.c \ + xz_dec_lzma2.c \ + xz_dec_stream.c diff --git a/platform/mcu/xr871/src/xz/xz_config.h b/platform/mcu/xr871/src/xz/xz_config.h new file mode 100644 index 0000000000..c2cc774c0e --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_config.h @@ -0,0 +1,111 @@ +/* + * Private includes and definitions for userspace use of XZ Embedded + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_CONFIG_H +#define XZ_CONFIG_H + +/* Uncomment as needed to enable BCJ filter decoders. */ +/* #define XZ_DEC_X86 */ +/* #define XZ_DEC_POWERPC */ +/* #define XZ_DEC_IA64 */ +/* #define XZ_DEC_ARM */ +/* #define XZ_DEC_ARMTHUMB */ +/* #define XZ_DEC_SPARC */ + +#include +#include +#include +#include + +#include "xz/xz.h" + + +#define kmalloc(size, flags) malloc(size) +#define kfree(ptr) free(ptr) +#define vmalloc(size) malloc(size) +#define vfree(ptr) free(ptr) + +#define memeq(a, b, size) (memcmp(a, b, size) == 0) +#define memzero(buf, size) memset(buf, 0, size) + +#ifndef min +# define min(x, y) ((x) < (y) ? (x) : (y)) +#endif +#define min_t(type, x, y) min(x, y) + +/* + * Some functions have been marked with __always_inline to keep the + * performance reasonable even when the compiler is optimizing for + * small code size. You may be able to save a few bytes by #defining + * __always_inline to plain inline, but don't complain if the code + * becomes slow. + * + * NOTE: System headers on GNU/Linux may #define this macro already, + * so if you want to change it, you need to #undef it first. + */ +#ifndef __always_inline +# ifdef __GNUC__ +# define __always_inline \ + inline __attribute__((__always_inline__)) +# else +# define __always_inline inline +# endif +#endif + +/* Inline functions to access unaligned unsigned 32-bit integers */ +#ifndef get_unaligned_le32 +static inline uint32_t get_unaligned_le32(const uint8_t *buf) +{ + return (uint32_t)buf[0] + | ((uint32_t)buf[1] << 8) + | ((uint32_t)buf[2] << 16) + | ((uint32_t)buf[3] << 24); +} +#endif + +#ifndef get_unaligned_be32 +static inline uint32_t get_unaligned_be32(const uint8_t *buf) +{ + return (uint32_t)(buf[0] << 24) + | ((uint32_t)buf[1] << 16) + | ((uint32_t)buf[2] << 8) + | (uint32_t)buf[3]; +} +#endif + +#ifndef put_unaligned_le32 +static inline void put_unaligned_le32(uint32_t val, uint8_t *buf) +{ + buf[0] = (uint8_t)val; + buf[1] = (uint8_t)(val >> 8); + buf[2] = (uint8_t)(val >> 16); + buf[3] = (uint8_t)(val >> 24); +} +#endif + +#ifndef put_unaligned_be32 +static inline void put_unaligned_be32(uint32_t val, uint8_t *buf) +{ + buf[0] = (uint8_t)(val >> 24); + buf[1] = (uint8_t)(val >> 16); + buf[2] = (uint8_t)(val >> 8); + buf[3] = (uint8_t)val; +} +#endif + +/* + * Use get_unaligned_le32() also for aligned access for simplicity. On + * little endian systems, #define get_le32(ptr) (*(const uint32_t *)(ptr)) + * could save a few bytes in code size. + */ +#ifndef get_le32 +# define get_le32 get_unaligned_le32 +#endif + +#endif diff --git a/platform/mcu/xr871/src/xz/xz_crc32.c b/platform/mcu/xr871/src/xz/xz_crc32.c new file mode 100644 index 0000000000..e48ab95f24 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_crc32.c @@ -0,0 +1,89 @@ +/* + * CRC32 using the polynomial from IEEE-802.3 + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +/* + * This is not the fastest implementation, but it is pretty compact. + * The fastest versions of xz_crc32() on modern CPUs without hardware + * accelerated CRC instruction are 3-5 times as fast as this version, + * but they are bigger and use more memory for the lookup table. + */ + +#include "xz_private.h" + +/* + * STATIC_RW_DATA is used in the pre-boot environment on some architectures. + * See for details. + */ +#ifndef STATIC_RW_DATA +# define STATIC_RW_DATA static +#endif + +static const uint32_t xz_crc32_table[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +XZ_EXTERN void xz_crc32_init(void) +{ + return; +} + +XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc) +{ + crc = ~crc; + + while (size != 0) { + crc = xz_crc32_table[*buf++ ^ (crc & 0xFF)] ^ (crc >> 8); + --size; + } + + return ~crc; +} diff --git a/platform/mcu/xr871/src/xz/xz_dec_lzma2.c b/platform/mcu/xr871/src/xz/xz_dec_lzma2.c new file mode 100644 index 0000000000..0c58f16949 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_dec_lzma2.c @@ -0,0 +1,1172 @@ +/* + * LZMA2 decoder + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#include "xz_private.h" +#include "xz_lzma2.h" +#include "compiler.h" + +/* + * Range decoder initialization eats the first five bytes of each LZMA chunk. + */ +#define RC_INIT_BYTES 5 + +/* + * Minimum number of usable input buffer to safely decode one LZMA symbol. + * The worst case is that we decode 22 bits using probabilities and 26 + * direct bits. This may decode at maximum of 20 bytes of input. However, + * lzma_main() does an extra normalization before returning, thus we + * need to put 21 here. + */ +#define LZMA_IN_REQUIRED 21 + +/* + * Dictionary (history buffer) + * + * These are always true: + * start <= pos <= full <= end + * pos <= limit <= end + * + * In multi-call mode, also these are true: + * end == size + * size <= size_max + * allocated <= size + * + * Most of these variables are size_t to support single-call mode, + * in which the dictionary variables address the actual output + * buffer directly. + */ +struct dictionary { + /* Beginning of the history buffer */ + uint8_t *buf; + + /* Old position in buf (before decoding more data) */ + size_t start; + + /* Position in buf */ + size_t pos; + + /* + * How full dictionary is. This is used to detect corrupt input that + * would read beyond the beginning of the uncompressed stream. + */ + size_t full; + + /* Write limit; we don't write to buf[limit] or later bytes. */ + size_t limit; + + /* + * End of the dictionary buffer. In multi-call mode, this is + * the same as the dictionary size. In single-call mode, this + * indicates the size of the output buffer. + */ + size_t end; + + /* + * Size of the dictionary as specified in Block Header. This is used + * together with "full" to detect corrupt input that would make us + * read beyond the beginning of the uncompressed stream. + */ + uint32_t size; + + /* + * Maximum allowed dictionary size in multi-call mode. + * This is ignored in single-call mode. + */ + uint32_t size_max; + + /* + * Amount of memory currently allocated for the dictionary. + * This is used only with XZ_DYNALLOC. (With XZ_PREALLOC, + * size_max is always the same as the allocated size.) + */ + uint32_t allocated; + + /* Operation mode */ + enum xz_mode mode; +}; + +/* Range decoder */ +struct rc_dec { + uint32_t range; + uint32_t code; + + /* + * Number of initializing bytes remaining to be read + * by rc_read_init(). + */ + uint32_t init_bytes_left; + + /* + * Buffer from which we read our input. It can be either + * temp.buf or the caller-provided input buffer. + */ + const uint8_t *in; + size_t in_pos; + size_t in_limit; +}; + +/* Probabilities for a length decoder. */ +struct lzma_len_dec { + /* Probability of match length being at least 10 */ + uint16_t choice; + + /* Probability of match length being at least 18 */ + uint16_t choice2; + + /* Probabilities for match lengths 2-9 */ + uint16_t low[POS_STATES_MAX][LEN_LOW_SYMBOLS]; + + /* Probabilities for match lengths 10-17 */ + uint16_t mid[POS_STATES_MAX][LEN_MID_SYMBOLS]; + + /* Probabilities for match lengths 18-273 */ + uint16_t high[LEN_HIGH_SYMBOLS]; +}; + +struct lzma_dec { + /* Distances of latest four matches */ + uint32_t rep0; + uint32_t rep1; + uint32_t rep2; + uint32_t rep3; + + /* Types of the most recently seen LZMA symbols */ + enum lzma_state state; + + /* + * Length of a match. This is updated so that dict_repeat can + * be called again to finish repeating the whole match. + */ + uint32_t len; + + /* + * LZMA properties or related bit masks (number of literal + * context bits, a mask dervied from the number of literal + * position bits, and a mask dervied from the number + * position bits) + */ + uint32_t lc; + uint32_t literal_pos_mask; /* (1 << lp) - 1 */ + uint32_t pos_mask; /* (1 << pb) - 1 */ + + /* If 1, it's a match. Otherwise it's a single 8-bit literal. */ + uint16_t is_match[STATES][POS_STATES_MAX]; + + /* If 1, it's a repeated match. The distance is one of rep0 .. rep3. */ + uint16_t is_rep[STATES]; + + /* + * If 0, distance of a repeated match is rep0. + * Otherwise check is_rep1. + */ + uint16_t is_rep0[STATES]; + + /* + * If 0, distance of a repeated match is rep1. + * Otherwise check is_rep2. + */ + uint16_t is_rep1[STATES]; + + /* If 0, distance of a repeated match is rep2. Otherwise it is rep3. */ + uint16_t is_rep2[STATES]; + + /* + * If 1, the repeated match has length of one byte. Otherwise + * the length is decoded from rep_len_decoder. + */ + uint16_t is_rep0_long[STATES][POS_STATES_MAX]; + + /* + * Probability tree for the highest two bits of the match + * distance. There is a separate probability tree for match + * lengths of 2 (i.e. MATCH_LEN_MIN), 3, 4, and [5, 273]. + */ + uint16_t dist_slot[DIST_STATES][DIST_SLOTS]; + + /* + * Probility trees for additional bits for match distance + * when the distance is in the range [4, 127]. + */ + uint16_t dist_special[FULL_DISTANCES - DIST_MODEL_END]; + + /* + * Probability tree for the lowest four bits of a match + * distance that is equal to or greater than 128. + */ + uint16_t dist_align[ALIGN_SIZE]; + + /* Length of a normal match */ + struct lzma_len_dec match_len_dec; + + /* Length of a repeated match */ + struct lzma_len_dec rep_len_dec; + + /* Probabilities of literals */ + uint16_t literal[LITERAL_CODERS_MAX][LITERAL_CODER_SIZE]; +}; + +struct lzma2_dec { + /* Position in xz_dec_lzma2_run(). */ + enum lzma2_seq { + SEQ_CONTROL, + SEQ_UNCOMPRESSED_1, + SEQ_UNCOMPRESSED_2, + SEQ_COMPRESSED_0, + SEQ_COMPRESSED_1, + SEQ_PROPERTIES, + SEQ_LZMA_PREPARE, + SEQ_LZMA_RUN, + SEQ_COPY + } sequence; + + /* Next position after decoding the compressed size of the chunk. */ + enum lzma2_seq next_sequence; + + /* Uncompressed size of LZMA chunk (2 MiB at maximum) */ + uint32_t uncompressed; + + /* + * Compressed size of LZMA chunk or compressed/uncompressed + * size of uncompressed chunk (64 KiB at maximum) + */ + uint32_t compressed; + + /* + * True if dictionary reset is needed. This is false before + * the first chunk (LZMA or uncompressed). + */ + bool need_dict_reset; + + /* + * True if new LZMA properties are needed. This is false + * before the first LZMA chunk. + */ + bool need_props; +}; + +struct xz_dec_lzma2 { + /* + * The order below is important on x86 to reduce code size and + * it shouldn't hurt on other platforms. Everything up to and + * including lzma.pos_mask are in the first 128 bytes on x86-32, + * which allows using smaller instructions to access those + * variables. On x86-64, fewer variables fit into the first 128 + * bytes, but this is still the best order without sacrificing + * the readability by splitting the structures. + */ + struct rc_dec rc; + struct dictionary dict; + struct lzma2_dec lzma2; + struct lzma_dec lzma; + + /* + * Temporary buffer which holds small number of input bytes between + * decoder calls. See lzma2_lzma() for details. + */ + struct { + uint32_t size; + uint8_t buf[3 * LZMA_IN_REQUIRED]; + } temp; +}; + +/************** + * Dictionary * + **************/ + +/* + * Reset the dictionary state. When in single-call mode, set up the beginning + * of the dictionary to point to the actual output buffer. + */ +static void dict_reset(struct dictionary *dict, struct xz_buf *b) +{ + if (DEC_IS_SINGLE(dict->mode)) { + dict->buf = b->out + b->out_pos; + dict->end = b->out_size - b->out_pos; + } + + dict->start = 0; + dict->pos = 0; + dict->limit = 0; + dict->full = 0; +} + +/* Set dictionary write limit */ +static void dict_limit(struct dictionary *dict, size_t out_max) +{ + if (dict->end - dict->pos <= out_max) + dict->limit = dict->end; + else + dict->limit = dict->pos + out_max; +} + +/* Return true if at least one byte can be written into the dictionary. */ +static inline bool dict_has_space(const struct dictionary *dict) +{ + return dict->pos < dict->limit; +} + +/* + * Get a byte from the dictionary at the given distance. The distance is + * assumed to valid, or as a special case, zero when the dictionary is + * still empty. This special case is needed for single-call decoding to + * avoid writing a '\0' to the end of the destination buffer. + */ +static inline uint32_t dict_get(const struct dictionary *dict, uint32_t dist) +{ + size_t offset = dict->pos - dist - 1; + + if (dist >= dict->pos) + offset += dict->end; + + return dict->full > 0 ? dict->buf[offset] : 0; +} + +/* + * Put one byte into the dictionary. It is assumed that there is space for it. + */ +static inline void dict_put(struct dictionary *dict, uint8_t byte) +{ + dict->buf[dict->pos++] = byte; + + if (dict->full < dict->pos) + dict->full = dict->pos; +} + +/* + * Repeat given number of bytes from the given distance. If the distance is + * invalid, false is returned. On success, true is returned and *len is + * updated to indicate how many bytes were left to be repeated. + */ +static bool dict_repeat(struct dictionary *dict, uint32_t *len, uint32_t dist) +{ + size_t back; + uint32_t left; + + if (dist >= dict->full || dist >= dict->size) + return false; + + left = min_t(size_t, dict->limit - dict->pos, *len); + *len -= left; + + back = dict->pos - dist - 1; + if (dist >= dict->pos) + back += dict->end; + + do { + dict->buf[dict->pos++] = dict->buf[back++]; + if (back == dict->end) + back = 0; + } while (--left > 0); + + if (dict->full < dict->pos) + dict->full = dict->pos; + + return true; +} + +/* Copy uncompressed data as is from input to dictionary and output buffers. */ +static void dict_uncompressed(struct dictionary *dict, struct xz_buf *b, + uint32_t *left) +{ + size_t copy_size; + + while (*left > 0 && b->in_pos < b->in_size + && b->out_pos < b->out_size) { + copy_size = min(b->in_size - b->in_pos, + b->out_size - b->out_pos); + if (copy_size > dict->end - dict->pos) + copy_size = dict->end - dict->pos; + if (copy_size > *left) + copy_size = *left; + + *left -= copy_size; + + memcpy(dict->buf + dict->pos, b->in + b->in_pos, copy_size); + dict->pos += copy_size; + + if (dict->full < dict->pos) + dict->full = dict->pos; + + if (DEC_IS_MULTI(dict->mode)) { + if (dict->pos == dict->end) + dict->pos = 0; + + memcpy(b->out + b->out_pos, b->in + b->in_pos, + copy_size); + } + + dict->start = dict->pos; + + b->out_pos += copy_size; + b->in_pos += copy_size; + } +} + +/* + * Flush pending data from dictionary to b->out. It is assumed that there is + * enough space in b->out. This is guaranteed because caller uses dict_limit() + * before decoding data into the dictionary. + */ +static uint32_t dict_flush(struct dictionary *dict, struct xz_buf *b) +{ + size_t copy_size = dict->pos - dict->start; + + if (DEC_IS_MULTI(dict->mode)) { + if (dict->pos == dict->end) + dict->pos = 0; + + memcpy(b->out + b->out_pos, dict->buf + dict->start, + copy_size); + } + + dict->start = dict->pos; + b->out_pos += copy_size; + return copy_size; +} + +/***************** + * Range decoder * + *****************/ + +/* Reset the range decoder. */ +static void rc_reset(struct rc_dec *rc) +{ + rc->range = (uint32_t)-1; + rc->code = 0; + rc->init_bytes_left = RC_INIT_BYTES; +} + +/* + * Read the first five initial bytes into rc->code if they haven't been + * read already. (Yes, the first byte gets completely ignored.) + */ +static bool rc_read_init(struct rc_dec *rc, struct xz_buf *b) +{ + while (rc->init_bytes_left > 0) { + if (b->in_pos == b->in_size) + return false; + + rc->code = (rc->code << 8) + b->in[b->in_pos++]; + --rc->init_bytes_left; + } + + return true; +} + +/* Return true if there may not be enough input for the next decoding loop. */ +static inline bool rc_limit_exceeded(const struct rc_dec *rc) +{ + return rc->in_pos > rc->in_limit; +} + +/* + * Return true if it is possible (from point of view of range decoder) that + * we have reached the end of the LZMA chunk. + */ +static inline bool rc_is_finished(const struct rc_dec *rc) +{ + return rc->code == 0; +} + +/* Read the next input byte if needed. */ +static __always_inline void rc_normalize(struct rc_dec *rc) +{ + if (rc->range < RC_TOP_VALUE) { + rc->range <<= RC_SHIFT_BITS; + rc->code = (rc->code << RC_SHIFT_BITS) + rc->in[rc->in_pos++]; + } +} + +/* + * Decode one bit. In some versions, this function has been splitted in three + * functions so that the compiler is supposed to be able to more easily avoid + * an extra branch. In this particular version of the LZMA decoder, this + * doesn't seem to be a good idea (tested with GCC 3.3.6, 3.4.6, and 4.3.3 + * on x86). Using a non-splitted version results in nicer looking code too. + * + * NOTE: This must return an int. Do not make it return a bool or the speed + * of the code generated by GCC 3.x decreases 10-15 %. (GCC 4.3 doesn't care, + * and it generates 10-20 % faster code than GCC 3.x from this file anyway.) + */ +static __always_inline int rc_bit(struct rc_dec *rc, uint16_t *prob) +{ + uint32_t bound; + int bit; + + rc_normalize(rc); + bound = (rc->range >> RC_BIT_MODEL_TOTAL_BITS) * *prob; + if (rc->code < bound) { + rc->range = bound; + *prob += (RC_BIT_MODEL_TOTAL - *prob) >> RC_MOVE_BITS; + bit = 0; + } else { + rc->range -= bound; + rc->code -= bound; + *prob -= *prob >> RC_MOVE_BITS; + bit = 1; + } + + return bit; +} + +/* Decode a bittree starting from the most significant bit. */ +static __always_inline uint32_t rc_bittree(struct rc_dec *rc, + uint16_t *probs, uint32_t limit) +{ + uint32_t symbol = 1; + + do { + if (rc_bit(rc, &probs[symbol])) + symbol = (symbol << 1) + 1; + else + symbol <<= 1; + } while (symbol < limit); + + return symbol; +} + +/* Decode a bittree starting from the least significant bit. */ +static __always_inline void rc_bittree_reverse(struct rc_dec *rc, + uint16_t *probs, + uint32_t *dest, uint32_t limit) +{ + uint32_t symbol = 1; + uint32_t i = 0; + + do { + if (rc_bit(rc, &probs[symbol])) { + symbol = (symbol << 1) + 1; + *dest += 1 << i; + } else { + symbol <<= 1; + } + } while (++i < limit); +} + +/* Decode direct bits (fixed fifty-fifty probability) */ +static inline void rc_direct(struct rc_dec *rc, uint32_t *dest, uint32_t limit) +{ + uint32_t mask; + + do { + rc_normalize(rc); + rc->range >>= 1; + rc->code -= rc->range; + mask = (uint32_t)0 - (rc->code >> 31); + rc->code += rc->range & mask; + *dest = (*dest << 1) + (mask + 1); + } while (--limit > 0); +} + +/******** + * LZMA * + ********/ + +/* Get pointer to literal coder probability array. */ +static uint16_t *lzma_literal_probs(struct xz_dec_lzma2 *s) +{ + uint32_t prev_byte = dict_get(&s->dict, 0); + uint32_t low = prev_byte >> (8 - s->lzma.lc); + uint32_t high = (s->dict.pos & s->lzma.literal_pos_mask) << s->lzma.lc; + return s->lzma.literal[low + high]; +} + +/* Decode a literal (one 8-bit byte) */ +static void lzma_literal(struct xz_dec_lzma2 *s) +{ + uint16_t *probs; + uint32_t symbol; + uint32_t match_byte; + uint32_t match_bit; + uint32_t offset; + uint32_t i; + + probs = lzma_literal_probs(s); + + if (lzma_state_is_literal(s->lzma.state)) { + symbol = rc_bittree(&s->rc, probs, 0x100); + } else { + symbol = 1; + match_byte = dict_get(&s->dict, s->lzma.rep0) << 1; + offset = 0x100; + + do { + match_bit = match_byte & offset; + match_byte <<= 1; + i = offset + match_bit + symbol; + + if (rc_bit(&s->rc, &probs[i])) { + symbol = (symbol << 1) + 1; + offset &= match_bit; + } else { + symbol <<= 1; + offset &= ~match_bit; + } + } while (symbol < 0x100); + } + + dict_put(&s->dict, (uint8_t)symbol); + lzma_state_literal(&s->lzma.state); +} + +/* Decode the length of the match into s->lzma.len. */ +static void lzma_len(struct xz_dec_lzma2 *s, struct lzma_len_dec *l, + uint32_t pos_state) +{ + uint16_t *probs; + uint32_t limit; + + if (!rc_bit(&s->rc, &l->choice)) { + probs = l->low[pos_state]; + limit = LEN_LOW_SYMBOLS; + s->lzma.len = MATCH_LEN_MIN; + } else { + if (!rc_bit(&s->rc, &l->choice2)) { + probs = l->mid[pos_state]; + limit = LEN_MID_SYMBOLS; + s->lzma.len = MATCH_LEN_MIN + LEN_LOW_SYMBOLS; + } else { + probs = l->high; + limit = LEN_HIGH_SYMBOLS; + s->lzma.len = MATCH_LEN_MIN + LEN_LOW_SYMBOLS + + LEN_MID_SYMBOLS; + } + } + + s->lzma.len += rc_bittree(&s->rc, probs, limit) - limit; +} + +/* Decode a match. The distance will be stored in s->lzma.rep0. */ +static void lzma_match(struct xz_dec_lzma2 *s, uint32_t pos_state) +{ + uint16_t *probs; + uint32_t dist_slot; + uint32_t limit; + + lzma_state_match(&s->lzma.state); + + s->lzma.rep3 = s->lzma.rep2; + s->lzma.rep2 = s->lzma.rep1; + s->lzma.rep1 = s->lzma.rep0; + + lzma_len(s, &s->lzma.match_len_dec, pos_state); + + probs = s->lzma.dist_slot[lzma_get_dist_state(s->lzma.len)]; + dist_slot = rc_bittree(&s->rc, probs, DIST_SLOTS) - DIST_SLOTS; + + if (dist_slot < DIST_MODEL_START) { + s->lzma.rep0 = dist_slot; + } else { + limit = (dist_slot >> 1) - 1; + s->lzma.rep0 = 2 + (dist_slot & 1); + + if (dist_slot < DIST_MODEL_END) { + s->lzma.rep0 <<= limit; + probs = s->lzma.dist_special + s->lzma.rep0 + - dist_slot - 1; + rc_bittree_reverse(&s->rc, probs, + &s->lzma.rep0, limit); + } else { + rc_direct(&s->rc, &s->lzma.rep0, limit - ALIGN_BITS); + s->lzma.rep0 <<= ALIGN_BITS; + rc_bittree_reverse(&s->rc, s->lzma.dist_align, + &s->lzma.rep0, ALIGN_BITS); + } + } +} + +/* + * Decode a repeated match. The distance is one of the four most recently + * seen matches. The distance will be stored in s->lzma.rep0. + */ +static void lzma_rep_match(struct xz_dec_lzma2 *s, uint32_t pos_state) +{ + uint32_t tmp; + + if (!rc_bit(&s->rc, &s->lzma.is_rep0[s->lzma.state])) { + if (!rc_bit(&s->rc, &s->lzma.is_rep0_long[ + s->lzma.state][pos_state])) { + lzma_state_short_rep(&s->lzma.state); + s->lzma.len = 1; + return; + } + } else { + if (!rc_bit(&s->rc, &s->lzma.is_rep1[s->lzma.state])) { + tmp = s->lzma.rep1; + } else { + if (!rc_bit(&s->rc, &s->lzma.is_rep2[s->lzma.state])) { + tmp = s->lzma.rep2; + } else { + tmp = s->lzma.rep3; + s->lzma.rep3 = s->lzma.rep2; + } + + s->lzma.rep2 = s->lzma.rep1; + } + + s->lzma.rep1 = s->lzma.rep0; + s->lzma.rep0 = tmp; + } + + lzma_state_long_rep(&s->lzma.state); + lzma_len(s, &s->lzma.rep_len_dec, pos_state); +} + +/* LZMA decoder core */ +static bool lzma_main(struct xz_dec_lzma2 *s) +{ + uint32_t pos_state; + + /* + * If the dictionary was reached during the previous call, try to + * finish the possibly pending repeat in the dictionary. + */ + if (dict_has_space(&s->dict) && s->lzma.len > 0) + dict_repeat(&s->dict, &s->lzma.len, s->lzma.rep0); + + /* + * Decode more LZMA symbols. One iteration may consume up to + * LZMA_IN_REQUIRED - 1 bytes. + */ + while (dict_has_space(&s->dict) && !rc_limit_exceeded(&s->rc)) { + pos_state = s->dict.pos & s->lzma.pos_mask; + + if (!rc_bit(&s->rc, &s->lzma.is_match[ + s->lzma.state][pos_state])) { + lzma_literal(s); + } else { + if (rc_bit(&s->rc, &s->lzma.is_rep[s->lzma.state])) + lzma_rep_match(s, pos_state); + else + lzma_match(s, pos_state); + + if (!dict_repeat(&s->dict, &s->lzma.len, s->lzma.rep0)) + return false; + } + } + + /* + * Having the range decoder always normalized when we are outside + * this function makes it easier to correctly handle end of the chunk. + */ + rc_normalize(&s->rc); + + return true; +} + +/* + * Reset the LZMA decoder and range decoder state. Dictionary is nore reset + * here, because LZMA state may be reset without resetting the dictionary. + */ +static void lzma_reset(struct xz_dec_lzma2 *s) +{ + uint16_t *probs; + size_t i; + + s->lzma.state = STATE_LIT_LIT; + s->lzma.rep0 = 0; + s->lzma.rep1 = 0; + s->lzma.rep2 = 0; + s->lzma.rep3 = 0; + + /* + * All probabilities are initialized to the same value. This hack + * makes the code smaller by avoiding a separate loop for each + * probability array. + * + * This could be optimized so that only that part of literal + * probabilities that are actually required. In the common case + * we would write 12 KiB less. + */ + probs = s->lzma.is_match[0]; + for (i = 0; i < PROBS_TOTAL; ++i) + probs[i] = RC_BIT_MODEL_TOTAL / 2; + + rc_reset(&s->rc); +} + +/* + * Decode and validate LZMA properties (lc/lp/pb) and calculate the bit masks + * from the decoded lp and pb values. On success, the LZMA decoder state is + * reset and true is returned. + */ +static bool lzma_props(struct xz_dec_lzma2 *s, uint8_t props) +{ + if (props > (4 * 5 + 4) * 9 + 8) + return false; + + s->lzma.pos_mask = 0; + while (props >= 9 * 5) { + props -= 9 * 5; + ++s->lzma.pos_mask; + } + + s->lzma.pos_mask = (1 << s->lzma.pos_mask) - 1; + + s->lzma.literal_pos_mask = 0; + while (props >= 9) { + props -= 9; + ++s->lzma.literal_pos_mask; + } + + s->lzma.lc = props; + + if (s->lzma.lc + s->lzma.literal_pos_mask > 4) + return false; + + s->lzma.literal_pos_mask = (1 << s->lzma.literal_pos_mask) - 1; + + lzma_reset(s); + + return true; +} + +/********* + * LZMA2 * + *********/ + +/* + * The LZMA decoder assumes that if the input limit (s->rc.in_limit) hasn't + * been exceeded, it is safe to read up to LZMA_IN_REQUIRED bytes. This + * wrapper function takes care of making the LZMA decoder's assumption safe. + * + * As long as there is plenty of input left to be decoded in the current LZMA + * chunk, we decode directly from the caller-supplied input buffer until + * there's LZMA_IN_REQUIRED bytes left. Those remaining bytes are copied into + * s->temp.buf, which (hopefully) gets filled on the next call to this + * function. We decode a few bytes from the temporary buffer so that we can + * continue decoding from the caller-supplied input buffer again. + */ +static bool lzma2_lzma(struct xz_dec_lzma2 *s, struct xz_buf *b) +{ + size_t in_avail; + uint32_t tmp; + + in_avail = b->in_size - b->in_pos; + if (s->temp.size > 0 || s->lzma2.compressed == 0) { + tmp = 2 * LZMA_IN_REQUIRED - s->temp.size; + if (tmp > s->lzma2.compressed - s->temp.size) + tmp = s->lzma2.compressed - s->temp.size; + if (tmp > in_avail) + tmp = in_avail; + + memcpy(s->temp.buf + s->temp.size, b->in + b->in_pos, tmp); + + if (s->temp.size + tmp == s->lzma2.compressed) { + memzero(s->temp.buf + s->temp.size + tmp, + sizeof(s->temp.buf) + - s->temp.size - tmp); + s->rc.in_limit = s->temp.size + tmp; + } else if (s->temp.size + tmp < LZMA_IN_REQUIRED) { + s->temp.size += tmp; + b->in_pos += tmp; + return true; + } else { + s->rc.in_limit = s->temp.size + tmp - LZMA_IN_REQUIRED; + } + + s->rc.in = s->temp.buf; + s->rc.in_pos = 0; + + if (!lzma_main(s) || s->rc.in_pos > s->temp.size + tmp) + return false; + + s->lzma2.compressed -= s->rc.in_pos; + + if (s->rc.in_pos < s->temp.size) { + s->temp.size -= s->rc.in_pos; + memmove(s->temp.buf, s->temp.buf + s->rc.in_pos, + s->temp.size); + return true; + } + + b->in_pos += s->rc.in_pos - s->temp.size; + s->temp.size = 0; + } + + in_avail = b->in_size - b->in_pos; + if (in_avail >= LZMA_IN_REQUIRED) { + s->rc.in = b->in; + s->rc.in_pos = b->in_pos; + + if (in_avail >= s->lzma2.compressed + LZMA_IN_REQUIRED) + s->rc.in_limit = b->in_pos + s->lzma2.compressed; + else + s->rc.in_limit = b->in_size - LZMA_IN_REQUIRED; + + if (!lzma_main(s)) + return false; + + in_avail = s->rc.in_pos - b->in_pos; + if (in_avail > s->lzma2.compressed) + return false; + + s->lzma2.compressed -= in_avail; + b->in_pos = s->rc.in_pos; + } + + in_avail = b->in_size - b->in_pos; + if (in_avail < LZMA_IN_REQUIRED) { + if (in_avail > s->lzma2.compressed) + in_avail = s->lzma2.compressed; + + memcpy(s->temp.buf, b->in + b->in_pos, in_avail); + s->temp.size = in_avail; + b->in_pos += in_avail; + } + + return true; +} + +/* + * Take care of the LZMA2 control layer, and forward the job of actual LZMA + * decoding or copying of uncompressed chunks to other functions. + */ +XZ_EXTERN enum xz_ret xz_dec_lzma2_run(struct xz_dec_lzma2 *s, + struct xz_buf *b) +{ + uint32_t tmp; + + while (b->in_pos < b->in_size || s->lzma2.sequence == SEQ_LZMA_RUN) { + switch (s->lzma2.sequence) { + case SEQ_CONTROL: + /* + * LZMA2 control byte + * + * Exact values: + * 0x00 End marker + * 0x01 Dictionary reset followed by + * an uncompressed chunk + * 0x02 Uncompressed chunk (no dictionary reset) + * + * Highest three bits (s->control & 0xE0): + * 0xE0 Dictionary reset, new properties and state + * reset, followed by LZMA compressed chunk + * 0xC0 New properties and state reset, followed + * by LZMA compressed chunk (no dictionary + * reset) + * 0xA0 State reset using old properties, + * followed by LZMA compressed chunk (no + * dictionary reset) + * 0x80 LZMA chunk (no dictionary or state reset) + * + * For LZMA compressed chunks, the lowest five bits + * (s->control & 1F) are the highest bits of the + * uncompressed size (bits 16-20). + * + * A new LZMA2 stream must begin with a dictionary + * reset. The first LZMA chunk must set new + * properties and reset the LZMA state. + * + * Values that don't match anything described above + * are invalid and we return XZ_DATA_ERROR. + */ + tmp = b->in[b->in_pos++]; + + if (tmp == 0x00) + return XZ_STREAM_END; + + if (tmp >= 0xE0 || tmp == 0x01) { + s->lzma2.need_props = true; + s->lzma2.need_dict_reset = false; + dict_reset(&s->dict, b); + } else if (s->lzma2.need_dict_reset) { + return XZ_DATA_ERROR; + } + + if (tmp >= 0x80) { + s->lzma2.uncompressed = (tmp & 0x1F) << 16; + s->lzma2.sequence = SEQ_UNCOMPRESSED_1; + + if (tmp >= 0xC0) { + /* + * When there are new properties, + * state reset is done at + * SEQ_PROPERTIES. + */ + s->lzma2.need_props = false; + s->lzma2.next_sequence + = SEQ_PROPERTIES; + + } else if (s->lzma2.need_props) { + return XZ_DATA_ERROR; + + } else { + s->lzma2.next_sequence + = SEQ_LZMA_PREPARE; + if (tmp >= 0xA0) + lzma_reset(s); + } + } else { + if (tmp > 0x02) + return XZ_DATA_ERROR; + + s->lzma2.sequence = SEQ_COMPRESSED_0; + s->lzma2.next_sequence = SEQ_COPY; + } + + break; + + case SEQ_UNCOMPRESSED_1: + s->lzma2.uncompressed + += (uint32_t)b->in[b->in_pos++] << 8; + s->lzma2.sequence = SEQ_UNCOMPRESSED_2; + break; + + case SEQ_UNCOMPRESSED_2: + s->lzma2.uncompressed + += (uint32_t)b->in[b->in_pos++] + 1; + s->lzma2.sequence = SEQ_COMPRESSED_0; + break; + + case SEQ_COMPRESSED_0: + s->lzma2.compressed + = (uint32_t)b->in[b->in_pos++] << 8; + s->lzma2.sequence = SEQ_COMPRESSED_1; + break; + + case SEQ_COMPRESSED_1: + s->lzma2.compressed + += (uint32_t)b->in[b->in_pos++] + 1; + s->lzma2.sequence = s->lzma2.next_sequence; + break; + + case SEQ_PROPERTIES: + if (!lzma_props(s, b->in[b->in_pos++])) + return XZ_DATA_ERROR; + + s->lzma2.sequence = SEQ_LZMA_PREPARE; + + case SEQ_LZMA_PREPARE: + if (s->lzma2.compressed < RC_INIT_BYTES) + return XZ_DATA_ERROR; + + if (!rc_read_init(&s->rc, b)) + return XZ_OK; + + s->lzma2.compressed -= RC_INIT_BYTES; + s->lzma2.sequence = SEQ_LZMA_RUN; + + case SEQ_LZMA_RUN: + /* + * Set dictionary limit to indicate how much we want + * to be encoded at maximum. Decode new data into the + * dictionary. Flush the new data from dictionary to + * b->out. Check if we finished decoding this chunk. + * In case the dictionary got full but we didn't fill + * the output buffer yet, we may run this loop + * multiple times without changing s->lzma2.sequence. + */ + dict_limit(&s->dict, min_t(size_t, + b->out_size - b->out_pos, + s->lzma2.uncompressed)); + if (!lzma2_lzma(s, b)) + return XZ_DATA_ERROR; + + s->lzma2.uncompressed -= dict_flush(&s->dict, b); + + if (s->lzma2.uncompressed == 0) { + if (s->lzma2.compressed > 0 || s->lzma.len > 0 + || !rc_is_finished(&s->rc)) + return XZ_DATA_ERROR; + + rc_reset(&s->rc); + s->lzma2.sequence = SEQ_CONTROL; + + } else if (b->out_pos == b->out_size + || (b->in_pos == b->in_size + && s->temp.size + < s->lzma2.compressed)) { + return XZ_OK; + } + + break; + + case SEQ_COPY: + dict_uncompressed(&s->dict, b, &s->lzma2.compressed); + if (s->lzma2.compressed > 0) + return XZ_OK; + + s->lzma2.sequence = SEQ_CONTROL; + break; + } + } + + return XZ_OK; +} + +XZ_EXTERN struct xz_dec_lzma2 *xz_dec_lzma2_create(enum xz_mode mode, + uint32_t dict_max) +{ + struct xz_dec_lzma2 *s = kmalloc(sizeof(*s), GFP_KERNEL); + if (s == NULL) + return NULL; + + s->dict.mode = mode; + s->dict.size_max = dict_max; + + if (DEC_IS_PREALLOC(mode)) { + s->dict.buf = vmalloc(dict_max); + if (s->dict.buf == NULL) { + kfree(s); + return NULL; + } + } else if (DEC_IS_DYNALLOC(mode)) { + s->dict.buf = NULL; + s->dict.allocated = 0; + } + + return s; +} + +XZ_EXTERN enum xz_ret xz_dec_lzma2_reset(struct xz_dec_lzma2 *s, uint8_t props) +{ + /* This limits dictionary size to 3 GiB to keep parsing simpler. */ + if (props > 39) + return XZ_OPTIONS_ERROR; + + s->dict.size = 2 + (props & 1); + s->dict.size <<= (props >> 1) + 11; + + if (DEC_IS_MULTI(s->dict.mode)) { + if (s->dict.size > s->dict.size_max) + return XZ_MEMLIMIT_ERROR; + + s->dict.end = s->dict.size; + + if (DEC_IS_DYNALLOC(s->dict.mode)) { + if (s->dict.allocated < s->dict.size) { + vfree(s->dict.buf); + s->dict.buf = vmalloc(s->dict.size); + if (s->dict.buf == NULL) { + s->dict.allocated = 0; + return XZ_MEM_ERROR; + } + } + } + } + + s->lzma.len = 0; + + s->lzma2.sequence = SEQ_CONTROL; + s->lzma2.need_dict_reset = true; + + s->temp.size = 0; + + return XZ_OK; +} + +XZ_EXTERN void xz_dec_lzma2_end(struct xz_dec_lzma2 *s) +{ + if (DEC_IS_MULTI(s->dict.mode)) + vfree(s->dict.buf); + + kfree(s); +} diff --git a/platform/mcu/xr871/src/xz/xz_dec_stream.c b/platform/mcu/xr871/src/xz/xz_dec_stream.c new file mode 100644 index 0000000000..ac809b1e64 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_dec_stream.c @@ -0,0 +1,821 @@ +/* + * .xz Stream decoder + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#include "xz_private.h" +#include "xz_stream.h" + +/* Hash used to validate the Index field */ +struct xz_dec_hash { + vli_type unpadded; + vli_type uncompressed; + uint32_t crc32; +}; + +struct xz_dec { + /* Position in dec_main() */ + enum { + SEQ_STREAM_HEADER, + SEQ_BLOCK_START, + SEQ_BLOCK_HEADER, + SEQ_BLOCK_UNCOMPRESS, + SEQ_BLOCK_PADDING, + SEQ_BLOCK_CHECK, + SEQ_INDEX, + SEQ_INDEX_PADDING, + SEQ_INDEX_CRC32, + SEQ_STREAM_FOOTER + } sequence; + + /* Position in variable-length integers and Check fields */ + uint32_t pos; + + /* Variable-length integer decoded by dec_vli() */ + vli_type vli; + + /* Saved in_pos and out_pos */ + size_t in_start; + size_t out_start; + + /* CRC32 value in Block or Index */ + uint32_t crc32; + + /* Type of the integrity check calculated from uncompressed data */ + enum xz_check check_type; + + /* Operation mode */ + enum xz_mode mode; + + /* + * True if the next call to xz_dec_run() is allowed to return + * XZ_BUF_ERROR. + */ + bool allow_buf_error; + + /* Information stored in Block Header */ + struct { + /* + * Value stored in the Compressed Size field, or + * VLI_UNKNOWN if Compressed Size is not present. + */ + vli_type compressed; + + /* + * Value stored in the Uncompressed Size field, or + * VLI_UNKNOWN if Uncompressed Size is not present. + */ + vli_type uncompressed; + + /* Size of the Block Header field */ + uint32_t size; + } block_header; + + /* Information collected when decoding Blocks */ + struct { + /* Observed compressed size of the current Block */ + vli_type compressed; + + /* Observed uncompressed size of the current Block */ + vli_type uncompressed; + + /* Number of Blocks decoded so far */ + vli_type count; + + /* + * Hash calculated from the Block sizes. This is used to + * validate the Index field. + */ + struct xz_dec_hash hash; + } block; + + /* Variables needed when verifying the Index field */ + struct { + /* Position in dec_index() */ + enum { + SEQ_INDEX_COUNT, + SEQ_INDEX_UNPADDED, + SEQ_INDEX_UNCOMPRESSED + } sequence; + + /* Size of the Index in bytes */ + vli_type size; + + /* Number of Records (matches block.count in valid files) */ + vli_type count; + + /* + * Hash calculated from the Records (matches block.hash in + * valid files). + */ + struct xz_dec_hash hash; + } index; + + /* + * Temporary buffer needed to hold Stream Header, Block Header, + * and Stream Footer. The Block Header is the biggest (1 KiB) + * so we reserve space according to that. buf[] has to be aligned + * to a multiple of four bytes; the size_t variables before it + * should guarantee this. + */ + struct { + size_t pos; + size_t size; + uint8_t buf[1024]; + } temp; + + struct xz_dec_lzma2 *lzma2; + +#ifdef XZ_DEC_BCJ + struct xz_dec_bcj *bcj; + bool bcj_active; +#endif +}; + +#ifdef XZ_DEC_ANY_CHECK +/* Sizes of the Check field with different Check IDs */ +static const uint8_t check_sizes[16] = { + 0, + 4, 4, 4, + 8, 8, 8, + 16, 16, 16, + 32, 32, 32, + 64, 64, 64 +}; +#endif + +/* + * Fill s->temp by copying data starting from b->in[b->in_pos]. Caller + * must have set s->temp.pos to indicate how much data we are supposed + * to copy into s->temp.buf. Return true once s->temp.pos has reached + * s->temp.size. + */ +static bool fill_temp(struct xz_dec *s, struct xz_buf *b) +{ + size_t copy_size = min_t(size_t, + b->in_size - b->in_pos, s->temp.size - s->temp.pos); + + memcpy(s->temp.buf + s->temp.pos, b->in + b->in_pos, copy_size); + b->in_pos += copy_size; + s->temp.pos += copy_size; + + if (s->temp.pos == s->temp.size) { + s->temp.pos = 0; + return true; + } + + return false; +} + +/* Decode a variable-length integer (little-endian base-128 encoding) */ +static enum xz_ret dec_vli(struct xz_dec *s, const uint8_t *in, + size_t *in_pos, size_t in_size) +{ + uint8_t byte; + + if (s->pos == 0) + s->vli = 0; + + while (*in_pos < in_size) { + byte = in[*in_pos]; + ++*in_pos; + + s->vli |= (vli_type)(byte & 0x7F) << s->pos; + + if ((byte & 0x80) == 0) { + /* Don't allow non-minimal encodings. */ + if (byte == 0 && s->pos != 0) + return XZ_DATA_ERROR; + + s->pos = 0; + return XZ_STREAM_END; + } + + s->pos += 7; + if (s->pos == 7 * VLI_BYTES_MAX) + return XZ_DATA_ERROR; + } + + return XZ_OK; +} + +/* + * Decode the Compressed Data field from a Block. Update and validate + * the observed compressed and uncompressed sizes of the Block so that + * they don't exceed the values possibly stored in the Block Header + * (validation assumes that no integer overflow occurs, since vli_type + * is normally uint64_t). Update the CRC32 if presence of the CRC32 + * field was indicated in Stream Header. + * + * Once the decoding is finished, validate that the observed sizes match + * the sizes possibly stored in the Block Header. Update the hash and + * Block count, which are later used to validate the Index field. + */ +static enum xz_ret dec_block(struct xz_dec *s, struct xz_buf *b) +{ + enum xz_ret ret; + + s->in_start = b->in_pos; + s->out_start = b->out_pos; + +#ifdef XZ_DEC_BCJ + if (s->bcj_active) + ret = xz_dec_bcj_run(s->bcj, s->lzma2, b); + else +#endif + ret = xz_dec_lzma2_run(s->lzma2, b); + + s->block.compressed += b->in_pos - s->in_start; + s->block.uncompressed += b->out_pos - s->out_start; + + /* + * There is no need to separately check for VLI_UNKNOWN, since + * the observed sizes are always smaller than VLI_UNKNOWN. + */ + if (s->block.compressed > s->block_header.compressed + || s->block.uncompressed + > s->block_header.uncompressed) + return XZ_DATA_ERROR; + + if (s->check_type == XZ_CHECK_CRC32) + s->crc32 = xz_crc32(b->out + s->out_start, + b->out_pos - s->out_start, s->crc32); + + if (ret == XZ_STREAM_END) { + if (s->block_header.compressed != VLI_UNKNOWN + && s->block_header.compressed + != s->block.compressed) + return XZ_DATA_ERROR; + + if (s->block_header.uncompressed != VLI_UNKNOWN + && s->block_header.uncompressed + != s->block.uncompressed) + return XZ_DATA_ERROR; + + s->block.hash.unpadded += s->block_header.size + + s->block.compressed; + +#ifdef XZ_DEC_ANY_CHECK + s->block.hash.unpadded += check_sizes[s->check_type]; +#else + if (s->check_type == XZ_CHECK_CRC32) + s->block.hash.unpadded += 4; +#endif + + s->block.hash.uncompressed += s->block.uncompressed; + s->block.hash.crc32 = xz_crc32( + (const uint8_t *)&s->block.hash, + sizeof(s->block.hash), s->block.hash.crc32); + + ++s->block.count; + } + + return ret; +} + +/* Update the Index size and the CRC32 value. */ +static void index_update(struct xz_dec *s, const struct xz_buf *b) +{ + size_t in_used = b->in_pos - s->in_start; + s->index.size += in_used; + s->crc32 = xz_crc32(b->in + s->in_start, in_used, s->crc32); +} + +/* + * Decode the Number of Records, Unpadded Size, and Uncompressed Size + * fields from the Index field. That is, Index Padding and CRC32 are not + * decoded by this function. + * + * This can return XZ_OK (more input needed), XZ_STREAM_END (everything + * successfully decoded), or XZ_DATA_ERROR (input is corrupt). + */ +static enum xz_ret dec_index(struct xz_dec *s, struct xz_buf *b) +{ + enum xz_ret ret; + + do { + ret = dec_vli(s, b->in, &b->in_pos, b->in_size); + if (ret != XZ_STREAM_END) { + index_update(s, b); + return ret; + } + + switch (s->index.sequence) { + case SEQ_INDEX_COUNT: + s->index.count = s->vli; + + /* + * Validate that the Number of Records field + * indicates the same number of Records as + * there were Blocks in the Stream. + */ + if (s->index.count != s->block.count) + return XZ_DATA_ERROR; + + s->index.sequence = SEQ_INDEX_UNPADDED; + break; + + case SEQ_INDEX_UNPADDED: + s->index.hash.unpadded += s->vli; + s->index.sequence = SEQ_INDEX_UNCOMPRESSED; + break; + + case SEQ_INDEX_UNCOMPRESSED: + s->index.hash.uncompressed += s->vli; + s->index.hash.crc32 = xz_crc32( + (const uint8_t *)&s->index.hash, + sizeof(s->index.hash), + s->index.hash.crc32); + --s->index.count; + s->index.sequence = SEQ_INDEX_UNPADDED; + break; + } + } while (s->index.count > 0); + + return XZ_STREAM_END; +} + +/* + * Validate that the next four input bytes match the value of s->crc32. + * s->pos must be zero when starting to validate the first byte. + */ +static enum xz_ret crc32_validate(struct xz_dec *s, struct xz_buf *b) +{ + do { + if (b->in_pos == b->in_size) + return XZ_OK; + + if (((s->crc32 >> s->pos) & 0xFF) != b->in[b->in_pos++]) + return XZ_DATA_ERROR; + + s->pos += 8; + + } while (s->pos < 32); + + s->crc32 = 0; + s->pos = 0; + + return XZ_STREAM_END; +} + +#ifdef XZ_DEC_ANY_CHECK +/* + * Skip over the Check field when the Check ID is not supported. + * Returns true once the whole Check field has been skipped over. + */ +static bool check_skip(struct xz_dec *s, struct xz_buf *b) +{ + while (s->pos < check_sizes[s->check_type]) { + if (b->in_pos == b->in_size) + return false; + + ++b->in_pos; + ++s->pos; + } + + s->pos = 0; + + return true; +} +#endif + +/* Decode the Stream Header field (the first 12 bytes of the .xz Stream). */ +static enum xz_ret dec_stream_header(struct xz_dec *s) +{ + if (!memeq(s->temp.buf, HEADER_MAGIC, HEADER_MAGIC_SIZE)) + return XZ_FORMAT_ERROR; + + if (xz_crc32(s->temp.buf + HEADER_MAGIC_SIZE, 2, 0) + != get_le32(s->temp.buf + HEADER_MAGIC_SIZE + 2)) + return XZ_DATA_ERROR; + + if (s->temp.buf[HEADER_MAGIC_SIZE] != 0) + return XZ_OPTIONS_ERROR; + + /* + * Of integrity checks, we support only none (Check ID = 0) and + * CRC32 (Check ID = 1). However, if XZ_DEC_ANY_CHECK is defined, + * we will accept other check types too, but then the check won't + * be verified and a warning (XZ_UNSUPPORTED_CHECK) will be given. + */ + s->check_type = s->temp.buf[HEADER_MAGIC_SIZE + 1]; + +#ifdef XZ_DEC_ANY_CHECK + if (s->check_type > XZ_CHECK_MAX) + return XZ_OPTIONS_ERROR; + + if (s->check_type > XZ_CHECK_CRC32) + return XZ_UNSUPPORTED_CHECK; +#else + if (s->check_type > XZ_CHECK_CRC32) + return XZ_OPTIONS_ERROR; +#endif + + return XZ_OK; +} + +/* Decode the Stream Footer field (the last 12 bytes of the .xz Stream) */ +static enum xz_ret dec_stream_footer(struct xz_dec *s) +{ + if (!memeq(s->temp.buf + 10, FOOTER_MAGIC, FOOTER_MAGIC_SIZE)) + return XZ_DATA_ERROR; + + if (xz_crc32(s->temp.buf + 4, 6, 0) != get_le32(s->temp.buf)) + return XZ_DATA_ERROR; + + /* + * Validate Backward Size. Note that we never added the size of the + * Index CRC32 field to s->index.size, thus we use s->index.size / 4 + * instead of s->index.size / 4 - 1. + */ + if ((s->index.size >> 2) != get_le32(s->temp.buf + 4)) + return XZ_DATA_ERROR; + + if (s->temp.buf[8] != 0 || s->temp.buf[9] != s->check_type) + return XZ_DATA_ERROR; + + /* + * Use XZ_STREAM_END instead of XZ_OK to be more convenient + * for the caller. + */ + return XZ_STREAM_END; +} + +/* Decode the Block Header and initialize the filter chain. */ +static enum xz_ret dec_block_header(struct xz_dec *s) +{ + enum xz_ret ret; + + /* + * Validate the CRC32. We know that the temp buffer is at least + * eight bytes so this is safe. + */ + s->temp.size -= 4; + if (xz_crc32(s->temp.buf, s->temp.size, 0) + != get_le32(s->temp.buf + s->temp.size)) + return XZ_DATA_ERROR; + + s->temp.pos = 2; + + /* + * Catch unsupported Block Flags. We support only one or two filters + * in the chain, so we catch that with the same test. + */ +#ifdef XZ_DEC_BCJ + if (s->temp.buf[1] & 0x3E) +#else + if (s->temp.buf[1] & 0x3F) +#endif + return XZ_OPTIONS_ERROR; + + /* Compressed Size */ + if (s->temp.buf[1] & 0x40) { + if (dec_vli(s, s->temp.buf, &s->temp.pos, s->temp.size) + != XZ_STREAM_END) + return XZ_DATA_ERROR; + + s->block_header.compressed = s->vli; + } else { + s->block_header.compressed = VLI_UNKNOWN; + } + + /* Uncompressed Size */ + if (s->temp.buf[1] & 0x80) { + if (dec_vli(s, s->temp.buf, &s->temp.pos, s->temp.size) + != XZ_STREAM_END) + return XZ_DATA_ERROR; + + s->block_header.uncompressed = s->vli; + } else { + s->block_header.uncompressed = VLI_UNKNOWN; + } + +#ifdef XZ_DEC_BCJ + /* If there are two filters, the first one must be a BCJ filter. */ + s->bcj_active = s->temp.buf[1] & 0x01; + if (s->bcj_active) { + if (s->temp.size - s->temp.pos < 2) + return XZ_OPTIONS_ERROR; + + ret = xz_dec_bcj_reset(s->bcj, s->temp.buf[s->temp.pos++]); + if (ret != XZ_OK) + return ret; + + /* + * We don't support custom start offset, + * so Size of Properties must be zero. + */ + if (s->temp.buf[s->temp.pos++] != 0x00) + return XZ_OPTIONS_ERROR; + } +#endif + + /* Valid Filter Flags always take at least two bytes. */ + if (s->temp.size - s->temp.pos < 2) + return XZ_DATA_ERROR; + + /* Filter ID = LZMA2 */ + if (s->temp.buf[s->temp.pos++] != 0x21) + return XZ_OPTIONS_ERROR; + + /* Size of Properties = 1-byte Filter Properties */ + if (s->temp.buf[s->temp.pos++] != 0x01) + return XZ_OPTIONS_ERROR; + + /* Filter Properties contains LZMA2 dictionary size. */ + if (s->temp.size - s->temp.pos < 1) + return XZ_DATA_ERROR; + + ret = xz_dec_lzma2_reset(s->lzma2, s->temp.buf[s->temp.pos++]); + if (ret != XZ_OK) + return ret; + + /* The rest must be Header Padding. */ + while (s->temp.pos < s->temp.size) + if (s->temp.buf[s->temp.pos++] != 0x00) + return XZ_OPTIONS_ERROR; + + s->temp.pos = 0; + s->block.compressed = 0; + s->block.uncompressed = 0; + + return XZ_OK; +} + +static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b) +{ + enum xz_ret ret; + + /* + * Store the start position for the case when we are in the middle + * of the Index field. + */ + s->in_start = b->in_pos; + + while (true) { + switch (s->sequence) { + case SEQ_STREAM_HEADER: + /* + * Stream Header is copied to s->temp, and then + * decoded from there. This way if the caller + * gives us only little input at a time, we can + * still keep the Stream Header decoding code + * simple. Similar approach is used in many places + * in this file. + */ + if (!fill_temp(s, b)) + return XZ_OK; + + /* + * If dec_stream_header() returns + * XZ_UNSUPPORTED_CHECK, it is still possible + * to continue decoding if working in multi-call + * mode. Thus, update s->sequence before calling + * dec_stream_header(). + */ + s->sequence = SEQ_BLOCK_START; + + ret = dec_stream_header(s); + if (ret != XZ_OK) + return ret; + + case SEQ_BLOCK_START: + /* We need one byte of input to continue. */ + if (b->in_pos == b->in_size) + return XZ_OK; + + /* See if this is the beginning of the Index field. */ + if (b->in[b->in_pos] == 0) { + s->in_start = b->in_pos++; + s->sequence = SEQ_INDEX; + break; + } + + /* + * Calculate the size of the Block Header and + * prepare to decode it. + */ + s->block_header.size + = ((uint32_t)b->in[b->in_pos] + 1) * 4; + + s->temp.size = s->block_header.size; + s->temp.pos = 0; + s->sequence = SEQ_BLOCK_HEADER; + + case SEQ_BLOCK_HEADER: + if (!fill_temp(s, b)) + return XZ_OK; + + ret = dec_block_header(s); + if (ret != XZ_OK) + return ret; + + s->sequence = SEQ_BLOCK_UNCOMPRESS; + + case SEQ_BLOCK_UNCOMPRESS: + ret = dec_block(s, b); + if (ret != XZ_STREAM_END) + return ret; + + s->sequence = SEQ_BLOCK_PADDING; + + case SEQ_BLOCK_PADDING: + /* + * Size of Compressed Data + Block Padding + * must be a multiple of four. We don't need + * s->block.compressed for anything else + * anymore, so we use it here to test the size + * of the Block Padding field. + */ + while (s->block.compressed & 3) { + if (b->in_pos == b->in_size) + return XZ_OK; + + if (b->in[b->in_pos++] != 0) + return XZ_DATA_ERROR; + + ++s->block.compressed; + } + + s->sequence = SEQ_BLOCK_CHECK; + + case SEQ_BLOCK_CHECK: + if (s->check_type == XZ_CHECK_CRC32) { + ret = crc32_validate(s, b); + if (ret != XZ_STREAM_END) + return ret; + } +#ifdef XZ_DEC_ANY_CHECK + else if (!check_skip(s, b)) { + return XZ_OK; + } +#endif + + s->sequence = SEQ_BLOCK_START; + break; + + case SEQ_INDEX: + ret = dec_index(s, b); + if (ret != XZ_STREAM_END) + return ret; + + s->sequence = SEQ_INDEX_PADDING; + + case SEQ_INDEX_PADDING: + while ((s->index.size + (b->in_pos - s->in_start)) + & 3) { + if (b->in_pos == b->in_size) { + index_update(s, b); + return XZ_OK; + } + + if (b->in[b->in_pos++] != 0) + return XZ_DATA_ERROR; + } + + /* Finish the CRC32 value and Index size. */ + index_update(s, b); + + /* Compare the hashes to validate the Index field. */ + if (!memeq(&s->block.hash, &s->index.hash, + sizeof(s->block.hash))) + return XZ_DATA_ERROR; + + s->sequence = SEQ_INDEX_CRC32; + + case SEQ_INDEX_CRC32: + ret = crc32_validate(s, b); + if (ret != XZ_STREAM_END) + return ret; + + s->temp.size = STREAM_HEADER_SIZE; + s->sequence = SEQ_STREAM_FOOTER; + + case SEQ_STREAM_FOOTER: + if (!fill_temp(s, b)) + return XZ_OK; + + return dec_stream_footer(s); + } + } + + /* Never reached */ +} + +/* + * xz_dec_run() is a wrapper for dec_main() to handle some special cases in + * multi-call and single-call decoding. + * + * In multi-call mode, we must return XZ_BUF_ERROR when it seems clear that we + * are not going to make any progress anymore. This is to prevent the caller + * from calling us infinitely when the input file is truncated or otherwise + * corrupt. Since zlib-style API allows that the caller fills the input buffer + * only when the decoder doesn't produce any new output, we have to be careful + * to avoid returning XZ_BUF_ERROR too easily: XZ_BUF_ERROR is returned only + * after the second consecutive call to xz_dec_run() that makes no progress. + * + * In single-call mode, if we couldn't decode everything and no error + * occurred, either the input is truncated or the output buffer is too small. + * Since we know that the last input byte never produces any output, we know + * that if all the input was consumed and decoding wasn't finished, the file + * must be corrupt. Otherwise the output buffer has to be too small or the + * file is corrupt in a way that decoding it produces too big output. + * + * If single-call decoding fails, we reset b->in_pos and b->out_pos back to + * their original values. This is because with some filter chains there won't + * be any valid uncompressed data in the output buffer unless the decoding + * actually succeeds (that's the price to pay of using the output buffer as + * the workspace). + */ +XZ_EXTERN enum xz_ret xz_dec_run(struct xz_dec *s, struct xz_buf *b) +{ + size_t in_start; + size_t out_start; + enum xz_ret ret; + + if (DEC_IS_SINGLE(s->mode)) + xz_dec_reset(s); + + in_start = b->in_pos; + out_start = b->out_pos; + ret = dec_main(s, b); + + if (DEC_IS_SINGLE(s->mode)) { + if (ret == XZ_OK) + ret = b->in_pos == b->in_size + ? XZ_DATA_ERROR : XZ_BUF_ERROR; + + if (ret != XZ_STREAM_END) { + b->in_pos = in_start; + b->out_pos = out_start; + } + + } else if (ret == XZ_OK && in_start == b->in_pos + && out_start == b->out_pos) { + if (s->allow_buf_error) + ret = XZ_BUF_ERROR; + + s->allow_buf_error = true; + } else { + s->allow_buf_error = false; + } + + return ret; +} + +XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max) +{ + struct xz_dec *s = kmalloc(sizeof(*s), GFP_KERNEL); + if (s == NULL) + return NULL; + + s->mode = mode; + +#ifdef XZ_DEC_BCJ + s->bcj = xz_dec_bcj_create(DEC_IS_SINGLE(mode)); + if (s->bcj == NULL) + goto error_bcj; +#endif + + s->lzma2 = xz_dec_lzma2_create(mode, dict_max); + if (s->lzma2 == NULL) + goto error_lzma2; + + xz_dec_reset(s); + return s; + +error_lzma2: +#ifdef XZ_DEC_BCJ + xz_dec_bcj_end(s->bcj); +error_bcj: +#endif + kfree(s); + return NULL; +} + +XZ_EXTERN void xz_dec_reset(struct xz_dec *s) +{ + s->sequence = SEQ_STREAM_HEADER; + s->allow_buf_error = false; + s->pos = 0; + s->crc32 = 0; + memzero(&s->block, sizeof(s->block)); + memzero(&s->index, sizeof(s->index)); + s->temp.pos = 0; + s->temp.size = STREAM_HEADER_SIZE; +} + +XZ_EXTERN void xz_dec_end(struct xz_dec *s) +{ + if (s != NULL) { + xz_dec_lzma2_end(s->lzma2); +#ifdef XZ_DEC_BCJ + xz_dec_bcj_end(s->bcj); +#endif + kfree(s); + } +} diff --git a/platform/mcu/xr871/src/xz/xz_lzma2.h b/platform/mcu/xr871/src/xz/xz_lzma2.h new file mode 100644 index 0000000000..071d67bee9 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_lzma2.h @@ -0,0 +1,204 @@ +/* + * LZMA2 definitions + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_LZMA2_H +#define XZ_LZMA2_H + +/* Range coder constants */ +#define RC_SHIFT_BITS 8 +#define RC_TOP_BITS 24 +#define RC_TOP_VALUE (1 << RC_TOP_BITS) +#define RC_BIT_MODEL_TOTAL_BITS 11 +#define RC_BIT_MODEL_TOTAL (1 << RC_BIT_MODEL_TOTAL_BITS) +#define RC_MOVE_BITS 5 + +/* + * Maximum number of position states. A position state is the lowest pb + * number of bits of the current uncompressed offset. In some places there + * are different sets of probabilities for different position states. + */ +#define POS_STATES_MAX (1 << 4) + +/* + * This enum is used to track which LZMA symbols have occurred most recently + * and in which order. This information is used to predict the next symbol. + * + * Symbols: + * - Literal: One 8-bit byte + * - Match: Repeat a chunk of data at some distance + * - Long repeat: Multi-byte match at a recently seen distance + * - Short repeat: One-byte repeat at a recently seen distance + * + * The symbol names are in from STATE_oldest_older_previous. REP means + * either short or long repeated match, and NONLIT means any non-literal. + */ +enum lzma_state { + STATE_LIT_LIT, + STATE_MATCH_LIT_LIT, + STATE_REP_LIT_LIT, + STATE_SHORTREP_LIT_LIT, + STATE_MATCH_LIT, + STATE_REP_LIT, + STATE_SHORTREP_LIT, + STATE_LIT_MATCH, + STATE_LIT_LONGREP, + STATE_LIT_SHORTREP, + STATE_NONLIT_MATCH, + STATE_NONLIT_REP +}; + +/* Total number of states */ +#define STATES 12 + +/* The lowest 7 states indicate that the previous state was a literal. */ +#define LIT_STATES 7 + +/* Indicate that the latest symbol was a literal. */ +static inline void lzma_state_literal(enum lzma_state *state) +{ + if (*state <= STATE_SHORTREP_LIT_LIT) + *state = STATE_LIT_LIT; + else if (*state <= STATE_LIT_SHORTREP) + *state -= 3; + else + *state -= 6; +} + +/* Indicate that the latest symbol was a match. */ +static inline void lzma_state_match(enum lzma_state *state) +{ + *state = *state < LIT_STATES ? STATE_LIT_MATCH : STATE_NONLIT_MATCH; +} + +/* Indicate that the latest state was a long repeated match. */ +static inline void lzma_state_long_rep(enum lzma_state *state) +{ + *state = *state < LIT_STATES ? STATE_LIT_LONGREP : STATE_NONLIT_REP; +} + +/* Indicate that the latest symbol was a short match. */ +static inline void lzma_state_short_rep(enum lzma_state *state) +{ + *state = *state < LIT_STATES ? STATE_LIT_SHORTREP : STATE_NONLIT_REP; +} + +/* Test if the previous symbol was a literal. */ +static inline bool lzma_state_is_literal(enum lzma_state state) +{ + return state < LIT_STATES; +} + +/* Each literal coder is divided in three sections: + * - 0x001-0x0FF: Without match byte + * - 0x101-0x1FF: With match byte; match bit is 0 + * - 0x201-0x2FF: With match byte; match bit is 1 + * + * Match byte is used when the previous LZMA symbol was something else than + * a literal (that is, it was some kind of match). + */ +#define LITERAL_CODER_SIZE 0x300 + +/* Maximum number of literal coders */ +#define LITERAL_CODERS_MAX (1 << 4) + +/* Minimum length of a match is two bytes. */ +#define MATCH_LEN_MIN 2 + +/* Match length is encoded with 4, 5, or 10 bits. + * + * Length Bits + * 2-9 4 = Choice=0 + 3 bits + * 10-17 5 = Choice=1 + Choice2=0 + 3 bits + * 18-273 10 = Choice=1 + Choice2=1 + 8 bits + */ +#define LEN_LOW_BITS 3 +#define LEN_LOW_SYMBOLS (1 << LEN_LOW_BITS) +#define LEN_MID_BITS 3 +#define LEN_MID_SYMBOLS (1 << LEN_MID_BITS) +#define LEN_HIGH_BITS 8 +#define LEN_HIGH_SYMBOLS (1 << LEN_HIGH_BITS) +#define LEN_SYMBOLS (LEN_LOW_SYMBOLS + LEN_MID_SYMBOLS + LEN_HIGH_SYMBOLS) + +/* + * Maximum length of a match is 273 which is a result of the encoding + * described above. + */ +#define MATCH_LEN_MAX (MATCH_LEN_MIN + LEN_SYMBOLS - 1) + +/* + * Different sets of probabilities are used for match distances that have + * very short match length: Lengths of 2, 3, and 4 bytes have a separate + * set of probabilities for each length. The matches with longer length + * use a shared set of probabilities. + */ +#define DIST_STATES 4 + +/* + * Get the index of the appropriate probability array for decoding + * the distance slot. + */ +static inline uint32_t lzma_get_dist_state(uint32_t len) +{ + return len < DIST_STATES + MATCH_LEN_MIN + ? len - MATCH_LEN_MIN : DIST_STATES - 1; +} + +/* + * The highest two bits of a 32-bit match distance are encoded using six bits. + * This six-bit value is called a distance slot. This way encoding a 32-bit + * value takes 6-36 bits, larger values taking more bits. + */ +#define DIST_SLOT_BITS 6 +#define DIST_SLOTS (1 << DIST_SLOT_BITS) + +/* Match distances up to 127 are fully encoded using probabilities. Since + * the highest two bits (distance slot) are always encoded using six bits, + * the distances 0-3 don't need any additional bits to encode, since the + * distance slot itself is the same as the actual distance. DIST_MODEL_START + * indicates the first distance slot where at least one additional bit is + * needed. + */ +#define DIST_MODEL_START 4 + +/* + * Match distances greater than 127 are encoded in three pieces: + * - distance slot: the highest two bits + * - direct bits: 2-26 bits below the highest two bits + * - alignment bits: four lowest bits + * + * Direct bits don't use any probabilities. + * + * The distance slot value of 14 is for distances 128-191. + */ +#define DIST_MODEL_END 14 + +/* Distance slots that indicate a distance <= 127. */ +#define FULL_DISTANCES_BITS (DIST_MODEL_END / 2) +#define FULL_DISTANCES (1 << FULL_DISTANCES_BITS) + +/* + * For match distances greater than 127, only the highest two bits and the + * lowest four bits (alignment) is encoded using probabilities. + */ +#define ALIGN_BITS 4 +#define ALIGN_SIZE (1 << ALIGN_BITS) +#define ALIGN_MASK (ALIGN_SIZE - 1) + +/* Total number of all probability variables */ +#define PROBS_TOTAL (1846 + LITERAL_CODERS_MAX * LITERAL_CODER_SIZE) + +/* + * LZMA remembers the four most recent match distances. Reusing these + * distances tends to take less space than re-encoding the actual + * distance value. + */ +#define REPS 4 + +#endif diff --git a/platform/mcu/xr871/src/xz/xz_private.h b/platform/mcu/xr871/src/xz/xz_private.h new file mode 100644 index 0000000000..482b90f363 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_private.h @@ -0,0 +1,156 @@ +/* + * Private includes and definitions + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_PRIVATE_H +#define XZ_PRIVATE_H + +#ifdef __KERNEL__ +# include +# include +# include + /* XZ_PREBOOT may be defined only via decompress_unxz.c. */ +# ifndef XZ_PREBOOT +# include +# include +# include +# ifdef CONFIG_XZ_DEC_X86 +# define XZ_DEC_X86 +# endif +# ifdef CONFIG_XZ_DEC_POWERPC +# define XZ_DEC_POWERPC +# endif +# ifdef CONFIG_XZ_DEC_IA64 +# define XZ_DEC_IA64 +# endif +# ifdef CONFIG_XZ_DEC_ARM +# define XZ_DEC_ARM +# endif +# ifdef CONFIG_XZ_DEC_ARMTHUMB +# define XZ_DEC_ARMTHUMB +# endif +# ifdef CONFIG_XZ_DEC_SPARC +# define XZ_DEC_SPARC +# endif +# define memeq(a, b, size) (memcmp(a, b, size) == 0) +# define memzero(buf, size) memset(buf, 0, size) +# endif +# define get_le32(p) le32_to_cpup((const uint32_t *)(p)) +#else + /* + * For userspace builds, use a separate header to define the required + * macros and functions. This makes it easier to adapt the code into + * different environments and avoids clutter in the Linux kernel tree. + */ +# include "xz_config.h" +#endif + +/* If no specific decoding mode is requested, enable support for all modes. */ +#if !defined(XZ_DEC_SINGLE) && !defined(XZ_DEC_PREALLOC) \ + && !defined(XZ_DEC_DYNALLOC) +# define XZ_DEC_SINGLE +# define XZ_DEC_PREALLOC +# define XZ_DEC_DYNALLOC +#endif + +/* + * The DEC_IS_foo(mode) macros are used in "if" statements. If only some + * of the supported modes are enabled, these macros will evaluate to true or + * false at compile time and thus allow the compiler to omit unneeded code. + */ +#ifdef XZ_DEC_SINGLE +# define DEC_IS_SINGLE(mode) ((mode) == XZ_SINGLE) +#else +# define DEC_IS_SINGLE(mode) (false) +#endif + +#ifdef XZ_DEC_PREALLOC +# define DEC_IS_PREALLOC(mode) ((mode) == XZ_PREALLOC) +#else +# define DEC_IS_PREALLOC(mode) (false) +#endif + +#ifdef XZ_DEC_DYNALLOC +# define DEC_IS_DYNALLOC(mode) ((mode) == XZ_DYNALLOC) +#else +# define DEC_IS_DYNALLOC(mode) (false) +#endif + +#if !defined(XZ_DEC_SINGLE) +# define DEC_IS_MULTI(mode) (true) +#elif defined(XZ_DEC_PREALLOC) || defined(XZ_DEC_DYNALLOC) +# define DEC_IS_MULTI(mode) ((mode) != XZ_SINGLE) +#else +# define DEC_IS_MULTI(mode) (false) +#endif + +/* + * If any of the BCJ filter decoders are wanted, define XZ_DEC_BCJ. + * XZ_DEC_BCJ is used to enable generic support for BCJ decoders. + */ +#ifndef XZ_DEC_BCJ +# if defined(XZ_DEC_X86) || defined(XZ_DEC_POWERPC) \ + || defined(XZ_DEC_IA64) || defined(XZ_DEC_ARM) \ + || defined(XZ_DEC_ARM) || defined(XZ_DEC_ARMTHUMB) \ + || defined(XZ_DEC_SPARC) +# define XZ_DEC_BCJ +# endif +#endif + +/* + * Allocate memory for LZMA2 decoder. xz_dec_lzma2_reset() must be used + * before calling xz_dec_lzma2_run(). + */ +XZ_EXTERN struct xz_dec_lzma2 *xz_dec_lzma2_create(enum xz_mode mode, + uint32_t dict_max); + +/* + * Decode the LZMA2 properties (one byte) and reset the decoder. Return + * XZ_OK on success, XZ_MEMLIMIT_ERROR if the preallocated dictionary is not + * big enough, and XZ_OPTIONS_ERROR if props indicates something that this + * decoder doesn't support. + */ +XZ_EXTERN enum xz_ret xz_dec_lzma2_reset(struct xz_dec_lzma2 *s, + uint8_t props); + +/* Decode raw LZMA2 stream from b->in to b->out. */ +XZ_EXTERN enum xz_ret xz_dec_lzma2_run(struct xz_dec_lzma2 *s, + struct xz_buf *b); + +/* Free the memory allocated for the LZMA2 decoder. */ +XZ_EXTERN void xz_dec_lzma2_end(struct xz_dec_lzma2 *s); + +#ifdef XZ_DEC_BCJ +/* + * Allocate memory for BCJ decoders. xz_dec_bcj_reset() must be used before + * calling xz_dec_bcj_run(). + */ +XZ_EXTERN struct xz_dec_bcj *xz_dec_bcj_create(bool single_call); + +/* + * Decode the Filter ID of a BCJ filter. This implementation doesn't + * support custom start offsets, so no decoding of Filter Properties + * is needed. Returns XZ_OK if the given Filter ID is supported. + * Otherwise XZ_OPTIONS_ERROR is returned. + */ +XZ_EXTERN enum xz_ret xz_dec_bcj_reset(struct xz_dec_bcj *s, uint8_t id); + +/* + * Decode raw BCJ + LZMA2 stream. This must be used only if there actually is + * a BCJ filter in the chain. If the chain has only LZMA2, xz_dec_lzma2_run() + * must be called directly. + */ +XZ_EXTERN enum xz_ret xz_dec_bcj_run(struct xz_dec_bcj *s, + struct xz_dec_lzma2 *lzma2, + struct xz_buf *b); + +/* Free the memory allocated for the BCJ filters. */ +#define xz_dec_bcj_end(s) kfree(s) +#endif + +#endif diff --git a/platform/mcu/xr871/src/xz/xz_stream.h b/platform/mcu/xr871/src/xz/xz_stream.h new file mode 100644 index 0000000000..66cb5a7055 --- /dev/null +++ b/platform/mcu/xr871/src/xz/xz_stream.h @@ -0,0 +1,62 @@ +/* + * Definitions for handling the .xz file format + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_STREAM_H +#define XZ_STREAM_H + +#if defined(__KERNEL__) && !XZ_INTERNAL_CRC32 +# include +# undef crc32 +# define xz_crc32(buf, size, crc) \ + (~crc32_le(~(uint32_t)(crc), buf, size)) +#endif + +/* + * See the .xz file format specification at + * http://tukaani.org/xz/xz-file-format.txt + * to understand the container format. + */ + +#define STREAM_HEADER_SIZE 12 + +#define HEADER_MAGIC "\3757zXZ" +#define HEADER_MAGIC_SIZE 6 + +#define FOOTER_MAGIC "YZ" +#define FOOTER_MAGIC_SIZE 2 + +/* + * Variable-length integer can hold a 63-bit unsigned integer or a special + * value indicating that the value is unknown. + * + * Experimental: vli_type can be defined to uint32_t to save a few bytes + * in code size (no effect on speed). Doing so limits the uncompressed and + * compressed size of the file to less than 256 MiB and may also weaken + * error detection slightly. + */ +typedef uint64_t vli_type; + +#define VLI_MAX ((vli_type)-1 / 2) +#define VLI_UNKNOWN ((vli_type)-1) + +/* Maximum encoded size of a VLI */ +#define VLI_BYTES_MAX (sizeof(vli_type) * 8 / 7) + +/* Integrity Check types */ +enum xz_check { + XZ_CHECK_NONE = 0, + XZ_CHECK_CRC32 = 1, + XZ_CHECK_CRC64 = 4, + XZ_CHECK_SHA256 = 10 +}; + +/* Maximum possible Check ID */ +#define XZ_CHECK_MAX 15 + +#endif diff --git a/platform/mcu/xr871/tools/calc_flash_offs b/platform/mcu/xr871/tools/calc_flash_offs new file mode 100644 index 0000000000..8fccf4a4c5 --- /dev/null +++ b/platform/mcu/xr871/tools/calc_flash_offs @@ -0,0 +1,43 @@ +#!/bin/bash + +XZ="" +if [ "$1" == "-z" ];then +XZ=".xz" +fi + +BOOT=boot.bin +APP=app.bin +XIP=app-xip.bin +NET=net.bin${XZ} +NETAP=net_ap.bin${XZ} +WLANBL=wlan_bl.bin +WLANFW=wlan_fw.bin +WLANSDD=wlan_sdd.bin + +BOOT_SZ=`ls -l ${BOOT} | awk '{print $5}'` +APP_SZ=`ls -l ${APP} | awk '{print $5}'` +XIP_SZ=`ls -l ${XIP} | awk '{print $5}'` +NET_SZ=`ls -l ${NET} | awk '{print $5}'` +NETAP_SZ=`ls -l ${NETAP} | awk '{print $5}'` +WLANBL_SZ=`ls -l ${WLANBL} | awk '{print $5}'` +WLANFW_SZ=`ls -l ${WLANFW} | awk '{print $5}'` +WLANSDD_SZ=`ls -l ${WLANSDD} | awk '{print $5}'` + +BOOT_OFFS=0 +#APP_OFFS=$[BOOT_OFFS + BOOT_SZ + 64 + $[1024 - $[$[BOOT_SZ + 64] & 1023]]] +APP_OFFS=32768 +XIP_OFFS=$[APP_OFFS + APP_SZ + 64 + $[1024 - $[$[APP_SZ + 64] & 1023]]] +NET_OFFS=$[XIP_OFFS + XIP_SZ + 64 + $[1024 - $[$[XIP_SZ + 64] & 1023]]] +NETAP_OFFS=$[NET_OFFS + NET_SZ + 64 + $[1024 - $[$[NET_SZ + 64] & 1023]]] +WLANBL_OFFS=$[NETAP_OFFS + NETAP_SZ + 64 + $[1024 - $[$[NETAP_SZ + 64] & 1023]]] +WLANFW_OFFS=$[WLANBL_OFFS + WLANBL_SZ + 64 + $[1024 - $[$[WLANBL_SZ + 64] & 1023]]] +WLANSDD_OFFS=$[WLANFW_OFFS + WLANFW_SZ + 64 + $[1024 - $[$[WLANFW_SZ + 64] & 1023]]] + +printf "%-16s sz: %-8d offs: %-dK\n" $BOOT $BOOT_SZ $[BOOT_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $APP $APP_SZ $[APP_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $XIP $XIP_SZ $[XIP_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $NET $NET_SZ $[NET_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $NETAP $NETAP_SZ $[NETAP_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $WLANBL $WLANBL_SZ $[WLANBL_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $WLANFW $WLANFW_SZ $[WLANFW_OFFS/1024] +printf "%-16s sz: %-8d offs: %-dK\n" $WLANSDD $WLANSDD_SZ $[WLANSDD_OFFS/1024] diff --git a/platform/mcu/xr871/tools/mkimage b/platform/mcu/xr871/tools/mkimage new file mode 100644 index 0000000000000000000000000000000000000000..e9464de8a014331dc6f5e689e3d68c10a0c6113e GIT binary patch literal 45880 zcmeHwdwi6|)&G+lh6rpxP`ocOXix|Nkp{dimxYCLiAt0zbQ6*di6+@J+2vA=#BQQ& zS2S3)*!OKsTi!OcRcWo51P#ljEcUe}sI95x)zzZ!u1js|HLp_k_dRE3o_+R)w!hEs z^LhXHJ(|qSIcLtCIdkUBd1mGzTdd0#WoBe(>dDlu)2QShWnqx`t!b+t;-Z9=Y9lp^ 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KEEP(*(.text.Reset_Handler)) + KEEP(*(.cpu_text)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + /* All text end */ + __text_end__ = .; + } > RAM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > RAM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > RAM + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackBottom = __StackTop - 0x400; + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + PROVIDE(heap_start = __end__); + PROVIDE(heap_end = __StackBottom); + PROVIDE(heap_len = heap_end - heap_start); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/platform/mcu/xr871/xr871.ld b/platform/mcu/xr871/xr871.ld new file mode 100644 index 0000000000..30ccba7cf6 --- /dev/null +++ b/platform/mcu/xr871/xr871.ld @@ -0,0 +1,170 @@ +/* +***************************************************************************** +** +** File : XR871.ld +** +** Abstract : Linker script for XR871 Device with +** 2048KByte FLASH, 448KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : Xradio Technology XR871 +** +** Environment : Gcc +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** +***************************************************************************** +*/ + +/* Specify the memory areas */ +MEMORY +{ + RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 448K + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 256K +} + +__RAM_BASE = ORIGIN(RAM); + +ENTRY(Reset_Handler) + +SECTIONS +{ +/* + .xip : + { + __xip_start__ = .; + /* All xip end * / + __xip_end__ = .; + } > FLASH +*/ + + .text : + { + __text_start__ = .; + KEEP(*(.isr_vector)) + KEEP(*(.text.Reset_Handler)) + KEEP(*(.cpu_text)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + /* All text end */ + __text_end__ = .; + } > RAM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > RAM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > RAM + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackBottom = __StackTop - 0x400; + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + PROVIDE(heap_start = __end__); + PROVIDE(heap_end = __StackBottom); + PROVIDE(heap_len = heap_end - heap_start); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/platform/mcu/xr871/xr871.mk b/platform/mcu/xr871/xr871.mk new file mode 100644 index 0000000000..1e24570bfe --- /dev/null +++ b/platform/mcu/xr871/xr871.mk @@ -0,0 +1,106 @@ +NAME := xr871 + +HOST_OPENOCD := xr871 + +$(NAME)_TYPE := kernel + +no_with_lwip := 0 +no_with_xip := 0 +no_with_image_compress := 0 +no_with_ota := 0 + +GLOBAL_DEFINES += CONFIG_AOS_KV_MULTIPTN_MODE +GLOBAL_DEFINES += CONFIG_AOS_KV_PTN=6 +GLOBAL_DEFINES += CONFIG_AOS_KV_SECOND_PTN=7 +GLOBAL_DEFINES += CONFIG_AOS_KV_PTN_SIZE=4096 +GLOBAL_DEFINES += CONFIG_AOS_KV_BUFFER_SIZE=8192 +GLOBAL_DEFINES += CONFIG_AOS_FATFS_SUPPORT_MMC +GLOBAL_DEFINES += CONFIG_AOS_FATFS_SUPPORT + +$(NAME)_INCLUDES += . +GLOBAL_INCLUDES += aos +GLOBAL_INCLUDES += include +GLOBAL_INCLUDES += include/net/lwip +GLOBAL_INCLUDES += include/driver/cmsis +GLOBAL_INCLUDES += project +GLOBAL_INCLUDES += project/main +GLOBAL_INCLUDES += project/common/framework +GLOBAL_INCLUDES += project/common/board/xr871_evb_main + +$(NAME)_COMPONENTS += platform/arch/arm/armv7m +$(NAME)_COMPONENTS += rhino hal protocols.net yloop framework.common netmgr mbedtls modules.fs.fatfs vcall libc digest_algorithm +$(NAME)_COMPONENTS += platform/mcu/xr871/src/driver/chip +$(NAME)_COMPONENTS += platform/mcu/xr871/src/image +$(NAME)_COMPONENTS += platform/mcu/xr871/src/net/udhcp +$(NAME)_COMPONENTS += platform/mcu/xr871/src/net/wlan +$(NAME)_COMPONENTS += platform/mcu/xr871/src/ota +$(NAME)_COMPONENTS += platform/mcu/xr871/src/pm +$(NAME)_COMPONENTS += platform/mcu/xr871/src/efpg +$(NAME)_COMPONENTS += platform/mcu/xr871/src/sys +$(NAME)_COMPONENTS += platform/mcu/xr871/src/xz +$(NAME)_COMPONENTS += platform/mcu/xr871/src/net/lwip +$(NAME)_COMPONENTS += platform/mcu/xr871/src/console +$(NAME)_COMPONENTS += platform/mcu/xr871/project +$(NAME)_COMPONENTS += platform/mcu/xr871/aos + +$(NAME)_COMPONENTS += platform/mcu/xr871/src/audio/audio_manager +$(NAME)_COMPONENTS += platform/mcu/xr871/src/audio/audio_pcm +$(NAME)_COMPONENTS += platform/mcu/xr871/src/cedarx +$(NAME)_COMPONENTS += platform/mcu/xr871/lib/libmp3 +#$(NAME)_COMPONENTS += platform/mcu/xr871/lib/libamr +#$(NAME)_COMPONENTS += platform/mcu/xr871/lib/libamren + +GLOBAL_ASMFLAGS += -mcpu=cortex-m4 \ + -mthumb \ + -mfpu=fpv4-sp-d16 \ + -mfloat-abi=softfp + +GLOBAL_CFLAGS += -mcpu=cortex-m4 \ + -mthumb \ + -mfpu=fpv4-sp-d16 \ + -mfloat-abi=softfp + +GLOBAL_CFLAGS += -include prj_config.h +GLOBAL_CFLAGS += -w +GLOBAL_CFLAGS += -fno-common \ + -fmessage-length=0 \ + -fno-exceptions \ + -ffunction-sections \ + -fdata-sections \ + -fomit-frame-pointer \ + -Wall \ + -Werror \ + -Wno-error=unused-function \ + -MMD -MP \ + -Os -DNDEBUG + +GLOBAL_CFLAGS += -D__CONFIG_OS_USE_YUNOS +GLOBAL_CFLAGS += -D__CONFIG_CHIP_XR871 +GLOBAL_CFLAGS += -D__CONFIG_CPU_CM4F +GLOBAL_CFLAGS += -D__CONFIG_ARCH_DUAL_CORE +GLOBAL_CFLAGS += -D__CONFIG_ARCH_APP_CORE +GLOBAL_CFLAGS += -D__CONFIG_LIBC_REDEFINE_GCC_INT32_TYPE +GLOBAL_CFLAGS += -D__CONFIG_LIBC_PRINTF_FLOAT +GLOBAL_CFLAGS += -D__CONFIG_LIBC_SCANF_FLOAT +GLOBAL_CFLAGS += -D__CONFIG_MALLOC_USE_STDLIB +GLOBAL_CFLAGS += -D__CONFIG_MBUF_IMPL_MODE=0 +GLOBAL_CFLAGS += -D__PRJ_CONFIG_WLAN_STA_AP + +ifneq ($(no_with_xip),1) +GLOBAL_CFLAGS += -D__PRJ_CONFIG_XIP +endif + +ifneq ($(no_with_image_compress),1) +GLOBAL_CFLAGS += -D__PRJ_CONFIG_IMG_COMPRESS +endif + +GLOBAL_LDFLAGS += -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp +GLOBAL_LDFLAGS += -Wl,--gc-sections --specs=nano.specs +GLOBAL_LDFLAGS += -Wl,--wrap,main +GLOBAL_LDFLAGS += -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifneq ($(no_with_xip),1) +GLOBAL_LINK_SCRIPT += platform/mcu/xr871/xr871-xip.ld +else +GLOBAL_LINK_SCRIPT += platform/mcu/xr871/xr871.ld +endif