Make SpyDrNet internals completely generic

[jacobdbrown4]

SpyDrNet is designed to parse in any netlist type, allow for manipulation, and compose any netlist type. However, not all netlist types are treated equally in SpyDrNet. I will use the b13 netlist to illustrate:

In the EDIF version of the b13 netlist, all of the instance properties look like the following:

{'.NS': 'EDIF', '.NAME': 'tx_conta[4]_i_1', 'EDIF.identifier': 'tx_conta_4__i_1', 'EDIF.properties': [{'identifier': 'INIT', 'value': "64'h2AAAAAAA80000000"}]}
{'.NS': 'EDIF', '.NAME': 'tx_conta[5]_i_1', 'EDIF.identifier': 'tx_conta_5__i_1', 'EDIF.properties': [{'identifier': 'INIT', 'value': "8'h28"}, {'identifier': 'SOFT_HLUTNM', 'value': 'soft_lutpair3'}]}
{'.NS': 'EDIF', '.NAME': 'tx_conta[6]_i_1', 'EDIF.identifier': 'tx_conta_6__i_1', 'EDIF.properties': [{'identifier': 'INIT', 'value': "16'hAA80"}, {'identifier': 'SOFT_HLUTNM', 'value': 'soft_lutpair3'}]}
{'.NS': 'EDIF', '.NAME': 'tx_conta[6]_i_2', 'EDIF.identifier': 'tx_conta_6__i_2', 'EDIF.properties': [{'identifier': 'INIT', 'value': "32'h80000000"}, {'identifier': 'SOFT_HLUTNM', 'value': 'soft_lutpair2'}]}
{'.NS': 'EDIF', '.NAME': 'tx_conta_reg[0]', 'EDIF.identifier': 'tx_conta_reg_0_', 'EDIF.properties': [{'identifier': 'INIT', 'value': "1'b0"}]}
{'.NS': 'EDIF', '.NAME': 'tx_conta_reg[1]', 'EDIF.identifier': 'tx_conta_reg_1_', 'EDIF.properties': [{'identifier': 'INIT', 'value': "1'b0"}]}

And then for the Verilog version, the instance properties look like:

{'.NS': 'DEFAULT', '.NAME': '\\conta_tmp[1]_i_1 ', 'VERILOG.InlineConstraints': {'SOFT_HLUTNM': '"soft_lutpair10"'}, 'VERILOG.Parameters': {'INIT': "4'h6"}}
{'.NS': 'DEFAULT', '.NAME': '\\conta_tmp[2]_i_1 ', 'VERILOG.InlineConstraints': {'SOFT_HLUTNM': '"soft_lutpair10"'}, 'VERILOG.Parameters': {'INIT': "8'h6A"}}
{'.NS': 'DEFAULT', '.NAME': '\\conta_tmp_reg[0] ', 'VERILOG.InlineConstraints': {}, 'VERILOG.Parameters': {'INIT': "1'b0"}}
{'.NS': 'DEFAULT', '.NAME': '\\conta_tmp_reg[1] ', 'VERILOG.InlineConstraints': {}, 'VERILOG.Parameters': {'INIT': "1'b0"}}
{'.NS': 'DEFAULT', '.NAME': '\\conta_tmp_reg[2] ', 'VERILOG.InlineConstraints': {}, 'VERILOG.Parameters': {'INIT': "1'b0"}}
{'.NS': 'DEFAULT', '.NAME': '\\data_in[0]_IBUF_inst ', 'VERILOG.InlineConstraints': {'OPT_INSERTED': None, 'OPT_MODIFIED': '"MLO "'}}
{'.NS': 'DEFAULT', '.NAME': '\\data_in[1]_IBUF_inst ', 'VERILOG.InlineConstraints': {'OPT_INSERTED': None, 'OPT_MODIFIED': '"MLO "'}}
{'.NS': 'DEFAULT', '.NAME': '\\data_in[2]_IBUF_inst ', 'VERILOG.InlineConstraints': {'OPT_INSERTED': None, 'OPT_MODIFIED': '"MLO "'}}
{'.NS': 'DEFAULT', '.NAME': '\\data_in[3]_IBUF_inst ', 'VERILOG.InlineConstraints': {'OPT_INSERTED': None, 'OPT_MODIFIED': '"MLO "'}}

Both the EDIF and Verilog Composers look for specific things such as EDIF.properties (for EDIF composer) and Verilog.Parameters (for Verilog composer). This hinders the flexibility of SpyDrNet. One example of it causing problems is when doing TMR...we used to have just one voter whose properties were EDIF specific. Because the Verilog composer doesn't "look for" properties formatted in the "EDIF way", voters in a Verilog netlist are missing important properties. I created a fix for this by making separate voters for EDIF and Verilog (and EBLIF) and allowing one to specify which one to use. This patch works, but probably isn't great. Another instance of this problem is that the library that contains all the primitives instanced in the design is named "hdi_primitives" in EDIF and "SDN.verilog_primitives" in Verilog. These are just two examples of where these netlist-type-specific-ness causes problems.

It would be great if all properties (and other info) were formatted the same way throughout SpyDrNet. Instead of "EDIF.properties" and Verilog.Parameters" we could have just "Properties". Instead of "hdi_primitives" and "SDN.verilog_primitives" we could have "primitives".

This would be a great undertaking to make happen. EDIF and Verilog netlists are very different, so the effort to make this happen may not be worth it. However, if we could make this happen, I feel it would greatly improve spydrnet. At the very least, we could have a "netlist translator" that could translate things that are formatted for EDIF to the Verilog format and vice versa.

[jacobdbrown4]

Also see #145

[jacobdbrown4]

See #53 and #54 for some additional insight