Use of ~LONGESTPERIOD prevents absolute time calculation in Clash simulation

[martijnbastiaan]

Xilinx's primitive models use a global set/reset (GSR) that is used to implement initial values. This reset signal is (by default) defined as asserted for 100 ns. Therefore, to faithfully replicate the VHDL/Verilog model, Clash simulation will have to know the absolute simulation time. Unfortunately, Clash's clock generation primitives wait for ~LONGESTPERIOD before it makes clock tick, a value only known at RTL compile time.

---

Encountered in: #2452. Waveform:

Note that the first three cycles (0000, 0001, 0002) are ignored by the pipeline because GSR is asserted.

---

@christiaanb Do you remember the rationale behind ~LONGESTPERIOD? Could we simply deprecate it / set it to a static value?

[christiaanb]

It was done to fix issue #2001 so a static value will always be wrong if we have clock period that is longer than said static value.

So perhaps we can add a static value on top of ~LONGESTPERIOD.

[christiaanb]

Why do we even model GSR in #2452? According to https://docs.xilinx.com/r/en-US/ug900-vivado-logic-simulation/Global-Set-and-Reset-Net you only want to deal with explicit GSR in post-synt/post-impl simulation.

[christiaanb]

Perhaps we want to change:

clash-compiler/tests/src/Test/Tasty/Vivado.hs

Line 92 in 053669c

launch_simulation

to: lauch_simulation -mode behavioral

See also: https://docs.xilinx.com/r/2021.2-English/ug900-vivado-logic-simulation/Behavioral-Simulation

[DigitalBrains1]

Huh, I never realised we were not running a behavioural simulation in Xilinx 😅

I agree, let's switch to behavioural simulation. Perhaps it will even be less hideously slow.

[martijnbastiaan]

Why do we even model GSR in #2452?

It's what the Xilinx's XPM_CDC_GRAY model does (unless #ifdef ONESPIN). The GSR is defined by verunilibs's glbl.v. So if we want a faithful correspondence between Verilog/VHDL simulation and Clash simulation we'll need to replicate what the GSR does. (It's not a hard requirement for me for that PR, but not be able to query the absolute time during Clash simulation does seem like a fundamental shortcoming to me.)

Perhaps we want to change:

+

Huh, I never realised we were not running a behavioural simulation in Xilinx

We do :). behavioral is the default.

[martijnbastiaan]

So perhaps we can add a static value on top of ~LONGESTPERIOD.

Adding 100 ns would entirely sidestep my issues.

[christiaanb]

@martijnbastiaan where in the docs does it say that behavioral is the default? https://docs.xilinx.com/r/2021.2-English/ug900-vivado-logic-simulation/Behavioral-Simulation seems to suggest otherwise.

[martijnbastiaan]

UG835 on launch_simulation:

Running with launch_simulation -mode behavioral gives me:

GSR would be the global reset, glblGSR_xpmcdc is the reset line in XPM_CDC_GRAY (copied from GSR).

Edit: which is to say, I believe the GSR is always modeled / taken into account in XPM_CDC_GRAY.

[christiaanb]

We've released v1.8.0, which includes a fix for this issue.