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<!DOCTYPE HTML>
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<td><b>研究生:</b></td>
<td><b>畢業年份:</b></td>
<td style='width:60%'><b>畢業論文題目:</b></td>
<td><b>畢業後就職公司:</b></td>
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<table id='mytable' style='padding-left:4px;'>
<th style='width:96px;'>研究生</th>
<th>畢業年份</th>
<th style='width:60%'>畢業論文題目</th>
<th>畢業後就職公司</th>
<tr>
<td>黃明傑</td>
<td>2024年(碩)</td>
<td> Realizing High-Density Ternary Content Addressable Memory with Resistive-Gate Transistor Array </td>
<td>致新科技 </td>
</tr>
<tr>
<td>黃育承</td>
<td>2024年(碩)</td>
<td> The Implementation of a Ferroelectric Memory Array </td>
<td>旺宏電子 </td>
</tr>
<tr>
<td>高子承</td>
<td>2024年(碩)</td>
<td> The Implementation of a 16nm FinFET-Based Compute-In-Memory Macro </td>
<td>群聯電子 </td>
</tr>
<tr>
<td>李亞竹</td>
<td>2024年(碩)</td>
<td> The Integration of a Vertical Resistance Random Access Memory Array with CMOS platform </td>
<td> </td>
</tr>
<tr>
<td>林禹良</td>
<td>2023年(碩)</td>
<td> An Energy Efficient Inference Processor of Neural Network Based on Resistive-gate FinFET </td>
<td>工研院 </td>
</tr>
<tr>
<td>梁宸維</td>
<td>2022年(碩)</td>
<td> A Cryptographic Platform Implemented by OTP in 16 nm FinFET Technology </td>
<td>台積電</td>
</tr>
<tr>
<td>林明佑</td>
<td>2022年(碩)</td>
<td> Identity-authentication of AIoT Devices through Physical Unclonable Function Implemented on 40nm CMOS Platform </td>
<td>聯發科技</td>
</tr>
<tr>
<td>李穆穎</td>
<td>2022年(碩)</td>
<td> The Implementation of Physical Unclonable Function (PUF) on a Resistive-Gate FinFET Memory Array </td>
<td>高通</td>
</tr>
<tr>
<td>林亮君</td>
<td>2022年(碩)</td>
<td> The Implementation of Physical Unclonable Function (PUF) Based on FinFET Variation </td>
<td>台積電</td>
</tr>
<tr>
<td>張壬奎</td>
<td>2022年(碩)</td>
<td> Improved HfZrO2 Fe-FinFET Memory to Realizing Highly-Reliable Multi-bit Operation </td>
<td>台積電</td>
</tr>
<tr>
<td>蔡岳穎</td>
<td>2021年(碩)</td>
<td> The Chip Implementation of Universal-Security-Function (USF) on a 40 nm CMOS Technology </td>
<td>聯發科技</td>
</tr>
<tr>
<td>楊尚霖</td>
<td>2021年(碩)</td>
<td> The Design and Fabrication of One Time Programmable Memory with Junction Fuse Mechanism Implemented on 16nm FinFET Process </td>
<td>聯發科技</td>
</tr>
<tr>
<td>蔡瑋倫</td>
<td>2021年(碩)</td>
<td> Performance Improvement on the Design of Nonvolatile Memory Using Ferroelectric Field Effect Transistor </td>
<td>高通</td>
</tr>
<tr>
<td>楊文燿</td>
<td>2020年(碩)</td>
<td> Gate Resistance Switching FinFET Array for True-Random-Number Generator Application </td>
<td>台積電</td>
</tr>
<tr>
<td>陳冠廷</td>
<td>2020年(碩)</td>
<td> The Multi-Level Operation of One-Transistor Resistive Random-Access Memory with Gate-Resistance Switching </td>
<td>台積電</td>
</tr>
<tr>
<td>王韋鈞</td>
<td>2020年(碩)</td>
<td> A New Architecture of Physical-unclonable-function Chip and Its Implementations </td>
<td>攻博(Georgia Tech, USA)</td>
</tr>
<tr>
<td>邱致豪</td>
<td>2020年(碩)</td>
<td> The Design of Tunnenling FET with Fin Structure for Low Voltage and Low Power Applications </td>
<td>世界先進</td>
</tr>
<tr>
<td>羅煜民</td>
<td>2020年(碩)</td>
<td> Embedded One Time Programming Memory Based on FinFET </td>
<td>旺宏電子</td>
</tr>
<tr>
<td>郭俊麟</td>
<td>2020年(碩)</td>
<td> The Implementation of Neuromorphic Computing Network By Multiple Levels Resistance Random Access Memory </td>
<td></td>
</tr>
<tr>
<td>陳柏因</td>
<td>2020年(碩)</td>
<td> Resistance-Gate Switching Nonvolatile Memory for Neuromorphic Network Application </td>
<td>瑞昱半導體</td>
</tr>
<tr>
<td>蔣兆凱</td>
<td>2019年(碩)</td>
<td> Improved High Performance FinFET and Its Prediction Down to 3nm Technology Node </td>
<td>聯發科技</td>
</tr>
<tr>
<td>莊晴智</td>
<td>2019年(碩)</td>
<td> The Design and Fabrication of One Time Programmable Memory with Gate Floating Anti-Fuse Breakdown </td>
<td>台積電</td>
</tr>
<tr>
<td>蕭亦雯</td>
<td>2019年(碩)</td>
<td> The Construction of Physical Unclonable Function(PUF) and True-Random-Number Generator(TRNG) Based on FinFET Variation </td>
<td>台積電</td>
</tr>
<tr>
<td>李芳立</td>
<td>2019年(碩)</td>
<td> Novel Design of High-performance Negative-Capacitance Fiekd Effect Transistors </td>
<td>台積電</td>
</tr>
<tr>
<td>白軒</td>
<td>2019年(碩)</td>
<td> The Design and Fabrication of FinFET with Both Air Trench and Air Spacer </td>
<td>台積電</td>
</tr>
<tr>
<td>張峻瑋</td>
<td>2018年(碩)</td>
<td> The Design and Fabrication of Next Generation One Time Programmable Memory Based on the Dielectric Fuse Breakdown </td>
<td>台積電</td>
</tr>
<tr>
<td>鄭智鴻</td>
<td>2018年(碩)</td>
<td>The Design and Optimization of ReRAM and Transistor in The Novel 1T Resistance-Gate NVM</td>
<td>群聯科技</td>
</tr>
<tr>
<td>王宏瑋</td>
<td>2018年(碩)</td>
<td> The Design of a Two-bit-per cell One Time Programming Memory with Physical Unclonable Function</td>
<td>世界先進</td>
</tr>
<tr>
<td>林建里</td>
<td>2018年(碩)</td>
<td> A New Architecture of FinFET for High Performance and the Analysis on Its RF Characteristics</td>
<td>聯電</td>
</tr>
<tr>
<td>江孟儒</td>
<td>2017年(碩)</td>
<td> A New Temperature Measurement Technique of the Self-Heating Effect in 14nm FinFET and Its Impact on the Transport Mechanism</td>
<td>台積電</td>
</tr>
<tr>
<td>陳泓文</td>
<td>2017年(碩)</td>
<td> A New FinFET-based Field Programmable Synapse Array (FPSA) for Artificial Neural Network Applications</td>
<td>台積電</td>
</tr>
<tr>
<td>郭彥成</td>
<td>2017年(碩)</td>
<td> The Design of a Resistance Flash Memory on a Pure CMOS Logic Compatible 14 nm FinFET Platform</td>
<td>美光</td>
</tr>
<tr>
<td>李俊葳</td>
<td>2016年(碩)</td>
<td> Fabrication of Tunnelling FET and the Analysis on the Trap-assisted tunneling</td>
<td>世界先進</td>
</tr>
<tr>
<td>范揚群</td>
<td>2016年(碩)</td>
<td> A New Theory and Its Experimental Verifications of Geometric Variation in Advanced Trigate FinFETs</td>
<td>世界先進</td>
</tr>
<tr>
<td>程皓瑋</td>
<td>2016年(碩)</td>
<td> A Novel ReWritable One-Time-Programming Memory Realized by Dielectric-fuse of RRAM for Embedded Applicatiion</td>
<td>聯電</td>
</tr>
<tr>
<td>吳家偉</td>
<td>2015年(碩)</td>
<td></td>
<td>自行創業</td>
</tr>
<tr>
<td>莊賀凱</td>
<td>2015年(碩)</td>
<td> Fabrication and Analysis of Silicon-Based Vertical-Type Tunneling Field-Effect Transistor</td>
<td>聯電</td>
</tr>
<tr>
<td>趙堉斌</td>
<td>2015年(碩)</td>
<td> Design of the Complementary Face-Tunneling FET for Ultra-low Power Applications</td>
<td>台積電</td>
</tr>
<tr>
<td>王亭堯</td>
<td>2015年(碩)</</td>
<td></td>
<td>休學</td>
</tr>
<tr>
<td>黃智宏</td>
<td>2015年(碩)</td>
<td> A One-Time-Programmable Array Based on a New Dielectric Fuse Breakdown Mechanism</td>
<td>聯電</td>
</tr>
<tr>
<td>王元鼎</td>
<td>2015年(碩)</td>
<td> New Understandings on the Correlation Between Work-function Fluctuation and Vth Variation in HKMG CMOS Devices</td>
<td>聯電</td>
</tr>
<tr>
<td>楊勝博</td>
<td>2015年(碩)</td>
<td> The Design and Optimization of a Low Power Bi-layer Resistance RAM</td>
<td>聯電</td>
</tr>
<tr>
<td>莊嘉暉</td>
<td>2014年(碩)</td>
<td>The Design and Fabrication of Low Power Bi-layer RRAM and the study of Its Conduction Mechanism</td>
<td>台積電</td>
</tr>
<tr>
<td>洪健珉</td>
<td>2014年(碩)</td>
<td>A Circuit Level Variability Model of Basic Logic Circuits in Trigate CMOS Devices</td>
<td>台積電</td>
</tr>
<tr>
<td>呂品毅</td>
<td>2014年(碩)</td>
<td>A New Methodology on the Investigation of Dielectric Breakdown in High-K Metal-Gate CMOS Devices</td>
<td>聯電</td>
</tr>
<tr>
<td>張貫宇</td>
<td>2014年(碩)</td>
<td>Performance Enhancement of Tunneling Field Effect Transistor by a New Current Enhancing Scheme</td>
<td>華邦電</td>
</tr>
<tr>
<td>林宗慶</td>
<td>2013年(碩)</td>
<td>Experimental Determination of the Ballistic Transport Characteristics of Nanoscale Trigate MOSFETs</td>
<td>台積電</td>
</tr>
<tr>
<td>伍邦齊</td>
<td>2013年(碩)</td>
<td>The Investigation of Oxide Traps in Advanced HfO2 Gate Dielectric nMOSFETs</td>
<td>台積電</td>
</tr>
<tr>
<td>林尚墩</td>
<td>2013年(碩)</td>
<td>The Impact of the Gate Current Variation on the Trigate MOSFETs</td>
<td>台積電</td>
</tr>
<tr>
<td>王漢樽</td>
<td>2013年(碩)</td>
<td>The Investigation of Endurance and Data Retention for U-Shaped MTP SONOS Flash Memory</td>
<td>聯電</td>
</tr>
<tr>
<td>陳敬翰</td>
<td>2013年(碩)</td>
<td>The Study of Device Characteristics and the Random Telegraph Noise Analysis in HfO2-based Resistive Random Access Memory</td>
<td>聯電</td>
</tr>
<tr>
<td>蔡政達</td>
<td>2012年(碩)</td>
<td>Investigation of the Mechanism and Reliability of a U-Shaped MTP SONOS Flash Memory Cell by a CMOS Logic Process</td>
<td>友達</td>
</tr>
<tr>
<td>蔡侑璉</td>
<td>2012年(碩)</td>
<td>The Multi-trap Analysis of Trigate MOSFETs Using the Random Telegraph Noise Measurement</td>
<td></td>
</tr>
<tr>
<td>黃英傑</td>
<td>2012年(碩)</td>
<td>The Random Telegraph Noise (RTN) Analysis of Multi-Level Operation Methods in HfO2-based Resistive Random Access Memory</td>
<td>聯電</td>
</tr>
<tr>
<td>蔡漢旻</td>
<td>2012年(碩)</td>
<td>The Random Trap Induced Fluctuations of Bulk Tri-Gate Devices by A New Trap Profiling Technique</td>
<td>台積電</td>
</tr>
<tr>
<td>周承翰</td>
<td>2011年(碩)</td>
<td>The Investigation of a Novel Operationing Method for Two-Bit Split-Gate SONOS Flash Memory</td>
<td>旺宏</td>
</tr>
<tr>
<td>曾元宏</td>
<td>2010年(碩)</td>
<td>The Physical Model of the Switching Dynamics in HfO2-based Resistive Random Access Memory</td>
<td>攻博</td>
</tr>
<tr>
<td>程政穎</td>
<td>2010年(碩)</td>
<td>The Random Dopants and Random Traps Induced Threshold Voltage Variations in Strained CMOS Devices</td>
<td>旺宏</td>
</tr>
<tr>
<td>何永涵</td>
<td>2010年(碩)</td>
<td>The Investigation of Charge Loss Mechanism in Dual-Bit Split-Gate SONOS Flash Memory</td>
<td>旺宏</td>
</tr>
<tr>
<td>鄭士嵩</td>
<td>2010年(碩)</td>
<td>A New Experimental Determination of Transport Parameters in High Performance Schottky-Barrier MOSFETs</td>
<td>友達</td>
</tr>
<tr>
<td>林米華</td>
<td>2009年(碩)</td>
<td>The Observation of Strain Induced Drain Current Instability in Advanced CMOS Devices Using Random Telegraph Noise Analysis</td>
<td>台積電</td>
</tr>
<tr>
<td>鄧安舜</td>
<td>2009年(碩)</td>
<td>The Carrier Transport and Channel Backscattering Characteristics of Nanoscale Schottky-Barrier MOSFETs</td>
<td>旺宏</td>
</tr>
<tr>
<td>張健宏</td>
<td>2009年(碩)</td>
<td>The Drain Current Fluctuation Studied through Random Telegraph Noise in High-k Dielectric n-MOSFETs</td>
<td>台積電</td>
</tr>
<tr>
<td>王振鵬</td>
<td>2009年(碩)</td>
<td>The Understanding of the Switching Mechanism and Related Reliability Issues in HfO2-Based Resistive Random Access Memory</td>
<td>攻博</td>
</tr>
<tr>
<td>謝易叡</td>
<td>2008年(碩)</td>
<td>An improved Interface Traps Profiling on the Study of Reliability in Strained CMOS Devices</td>
<td>攻博</td>
</tr>
<tr>
<td>張文彥</td>
<td>2008年(碩)</td>
<td>Transport Analysis and the Reliability Correlation in Nanoscale Strained-Silicon Devices</td>
<td>攻博</td>
</tr>
<tr>
<td>郭建鴻</td>
<td>2008年(碩)</td>
<td>Investigation of the Mechanism and Reliability in a Two-Bit SONOS Flash Memory</td>
<td>台積電</td>
</tr>
<tr>
<td>張家銘</td>
<td>2008年(碩)</td>
<td>The Observation of Gate Current Instability in High-k Gate Dielectric MOSFET by a New Gate Current Random Telegraph Noise Approach</td>
<td>台積電</td>
</tr>
<tr>
<td>曾友良</td>
<td>2008年(碩)</td>
<td>Investigation of Reliability in Advanced Hf-Based High-k Gate Dielectrics nMOSFETs</td>
<td>晶豪科</td>
</tr>
<tr>
<td>蔡亞峻</td>
<td>2007年(碩)</td>
<td>The Channel Backscattering Characteristics of Nanoscale Strained-CMOS and Its Correlation to the Reliability</td>
<td>旺宏</td>
</tr>
<tr>
<td>黃大正</td>
<td>2007年(碩)</td>
<td>Strained Related Reliability Issues for CMOS Devices of 65nm Generation and Beyond</td>
<td>台積電</td>
</tr>
<tr>
<td>黃耀賢</td>
<td>2007年(碩)</td>
<td>Performance and Reliability Evaluation of a Low Voltage and High Speed P-channel Floating Gate Flash Memory</td>
<td>茂德</td>
</tr>
<tr>
<td>曾元亨</td>
<td>2007年(碩)</td>
<td>The Investigation of the Mechanism and Reliability for Low Voltage Operation SONOS Flash Memory Devices</td>
<td>攻博</td>
</tr>
<tr>
<td>朱益輝</td>
<td>2005年(碩)</td>
<td>A Low Leakage Charge Pumping Measurement Technique for High-K MOSFET’s</td>
<td></td>
</tr>
<tr>
<td>李冠德</td>
<td>2005年(碩)</td>
<td>The Impact of Interfacial Layer and the Halo Implant on the Reliability of High K Dielectric CMOS Devices</td>
<td></td>
</tr>
<tr>
<td>陳靖泓</td>
<td>2005年(碩)</td>
<td>The Investigation of Data Retention and Endurance in a Nitride Storage Flash Memory</td>
<td></td>
</tr>
<tr>
<td>吳書仁</td>
<td>2005年(碩)</td>
<td>(110)矽晶面CMOS元件的熱載子與負偏壓不穩定可靠性研究與分析</td>
<td></td>
</tr>
<tr>
<td>劉又仁</td>
<td>2005年(碩)</td>
<td>Investigation of Hot Carrier Reliabilities in Strained-Silicon Nanoscale CMOS Devices</td>
<td></td>
</tr>
<tr>
<td>林佑聰</td>
<td>2004年(碩)</td>
<td>BiAND式快閃記憶體的耐久度與資料儲存特性上的可靠度分析</td>
<td></td>
</tr>
<tr>
<td>馮信榮</td>
<td>2004年(碩)</td>
<td>Low Leakage Charge Pumping Measurement Techniques for Advanced CMOS with Gate Oxide in the 1nm Range</td>
<td></td>
</tr>
<tr>
<td>葉昌樺</td>
<td>2004年(碩)</td>
<td>淺溝槽隔離層元件與應變矽元件的熱載子可靠性研究與分析</td>
<td></td>
</tr>
<tr>
<td>顧子強</td>
<td>2004年(碩)</td>
<td>Understanding of the Hot Carrier and NBTI Effects for Advanced CMOS Devices with SiON and N/O stack</td>
<td></td>
</tr>
<tr>
<td>蔣步堯</td>
<td>2003年(碩)</td>
<td>The Investigation of Data Retention in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell</td>
<td></td>
</tr>
<tr>
<td>陳尚志</td>
<td>2002年(博)</td>
<td>The Investigation of Gate Oxide Interface and Process-Induced Device Reliability in Deep-Submicron and Nanometer CMOS Devices</td>
<td></td>
</tr>
<tr>
<td>羅大剛</td>
<td>2002年(碩)</td>
<td>Hot Carrier and NBTI Reliability Evaluation of Dual-Gate CMOS Devices Using an Improved Gated-Diode Measurement</td>
<td></td>
</tr>
<tr>
<td>林新富</td>
<td>2002年(碩)</td>
<td>Performance and Reliability Improvement of Flash EEPROM with Pocket-Implanted Drain Structure</td>
<td></td>
</tr>
<tr>
<td>林旭益</td>
<td>2002年(碩)</td>
<td>高頻CMOS元件基板SPICE模型建立RF CMOS Substrate Modeling in Spice</td>
<td></td>
</tr>
<tr>
<td>蔡皓偉</td>
<td>2001年(碩)</td>
<td>Improvement of the Performance and the Reliability in P-channel Flash Memory with Various Floating-gate Materials</td>
<td></td>
</tr>
<tr>
<td>林漢紋</td>
<td>2001年(碩)</td>
<td>An Accurate Gate Resistance Spice Model for RF IC Applications</td>
<td></td>
</tr>
<tr>
<td>林清淳</td>
<td>2001年(碩)</td>
<td>使用多重氧化層技術成長隻雙閘極金氧半元件偏壓與溫度效應之可靠性研究</td>
<td></td>
</tr>
<tr>
<td>陳映仁</td>
<td>2001年(碩)</td>
<td>Performance and Reliability Studies of Flash Memories with Drain Avalanche Hot Electron Injection Scheme</td>
<td></td>
</tr>
<tr>
<td>吳柏璋</td>
<td>2000年(碩)</td>
<td>不同浮動閘極材料N通道快閃記憶體資料保存特性研究</td>
<td></td>
</tr>
<tr>
<td>曾當貴</td>
<td>2000年(碩)</td>
<td>應用於電路模擬器含有溫度效應的複晶矽薄膜電晶體模式</td>
<td></td>
</tr>
<tr>
<td>高瑄苓</td>
<td>2000年(碩)</td>
<td>電荷幫浦法於薄閘極氧化層淺接面延伸結構之N型金氧半元件電漿蝕刻傷害之研究</td>
<td></td>
</tr>
<tr>
<td>易成名</td>
<td>1999年(博)</td>
<td>快閃式記憶體元件中熱載子注入導致的可靠性問題研究</td>
<td></td>
</tr>
<tr>
<td>陳奇祥</td>
<td>1999年(博)</td>
<td>複晶矽薄膜電晶體元件模式與電路模擬器之建立</td>
<td></td>
</tr>
<tr>
<td>吳尚修</td>
<td>1999年(碩)</td>
<td>可用於快閃式記憶體反覆寫入抹除前後之直流與暫態模式</td>
<td></td>
</tr>
<tr>
<td>廖勝泰</td>
<td>1999年(碩)</td>
<td>與P通道快閃記憶體性能與可靠性之比較研究</td>
<td></td>
</tr>
<tr>
<td>楊文杰</td>
<td>1999年(碩)</td>
<td>淺凹槽隔離深次微米互補金氧半元件窄寬度效應熱載子可靠性的研究</td>
<td></td>
</tr>
<tr>
<td>何之浩</td>
<td>1999年(碩)</td>
<td>利用P型浮動閘極材料改善N通道快閃記憶體的性能與可靠性之研究</td>
<td></td>
</tr>
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