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<!DOCTYPE HTML>
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<div class="contenttitle">發表論文</div>
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<p class="title">      DSML      發表論文一覽</p>
<p class="title">      頂級會議論文 (IEDM & VLSI-TECH)</p>
<li>[1] E. R. Hsieh, W. L. Tsai, S. S. Chung et al., “The First Embedded 14nm FeFinFET NVM: 2T1CFE Array,” Symp. on VLSI Technology, Kyoto, June 13-19, 2021.</li>
<li>[2] W. C. Wang, C. C. Chuang, E. R. Hsieh, S. S. Chung et al., “A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password,” in IEDM Tech. Dig., San Francisco CA, Dec. 12-16, 2020.</li>
<li>[3] W. Y. Yang, B. Y. Chen, E. R. Hsieh, S. S. Chung et al., “Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator,” in IEDM Tech. Dig., San Francisco CA, Dec. 12-16, 2020.</li>
<li>[4] Y. Xiao, E. R. Hsieh, S. S. Chung et al., “Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG),” in IEDM Tech. Dig., San Francisco CA, Dec. 7-11, 2019.</li>
<li>[5] E. R. Hsieh, H. W. Wang, S. S. Chung et al., “Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era,” Symp. on VLSI Technology, Kyoto, June 9-14, 2019.</li>
<li>[6] E. R. Hsieh, H. Y. Chang, S. S. Chung et al., “A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance,” Symp. on VLSI Technology, Kyoto, June 9-14, 2019.</li>
<li>[7] E. R. Hsieh, C. W. Chang, S. S. Chung et al., “The Demonstration of Gate Dielectric-Fuse 4kb OTP Memory Feasible for Embedded Applications in High-K Metal-gate CMOS Generations and Beyond,” Symp. on VLSI Circuits, Kyoto, June 9-14, 2019.</li>
<li>[8] S. S. Chung., “Embedded Resistive Switching Non-Volatile Memory Technology for 28nm and Beyond High-k Metal-Gate Generations,” accepted by IEEE VLSI-TECH, 2019.</li>
<li>[9] J. L. Kuo, E R. Hsieh et al., “An Energy Efficient FinFET‐based Field Programmable Synapse Array (FPSA) Feasible for One‐ shot Learning on EDGE AI,” accepted by IEEE VLSI-TECH, 2018.</li>
<li>[10] E R. Hsieh, S. S. Chung et al., "First Demonstration of Flash RRAM on Pure CMOS Logic 14nm FinFET Platform Featuring Excellent Immunity to Sneak-path and MLC Capability, " accepted by IEEE VLSI-TECH, 2017.(highlight)</li>
<li>[11] E R. Hsieh, S. S. Chung et al., “A new variation plot to examine the interfacial-dipole induced work-function variation in advanced high-k metal-gate CMOS devices,” IEEE VLSI-TECH, 2016, pp.166-167.</li>
<li>[12] E R. Hsieh, S. S. Chung et al., “The Demonstration of Low-cost and Logic Process Fully-compatible OTP Memory on Advanced CMOS with a Newly Found Dielectric Fuse Breakdown,” IEEE IEDM, 2015, pp. 3.4.1- pp. 3.4.4.</li>
<li>[13] E R. Hsieh, S. S. Chung et al., “A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology,” IEEE IEDM, 2014, pp. 12.2.1-12.2.4.</li>
<li>[14] E R. Hsieh, S. S. Chung et al., “The Experimental Demonstration of the BTI-induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices,” IEEE VLSI Symposia on Tech., 2014, pp. 12.4.1-12.4.2. (citied 7 times)</li>
<li>[15] E R. Hsieh, S. S. Chung et al., “Gate Current Variation: A New Theory and Practice on Investigating the off-state Leakage of Trigate MOSFETs and the Power Dissipation of SRAM,” IEEE IEDM, 2013, pp. 31.2.1-31.2.4. (citied 1 times)</li>
<li>[16] E R. Hsieh, S. S. Chung et al., “The Understanding of Multi-level RTN in Trigate MOSFETs through the 2D Profiling of Traps and its Impact on SRAM Performance: A New Failure Mechanism Found,” IEEE IEDM, 2012, pp. 19.2.1-19.2.4. (citied 9 times)</li>
<li>[17] H. M. Tsai, E R. Hsieh, S. S. Chung et al., “The Understanding of the Trap Induced Variation in Bulk Tri-gate Devices by a Novel Random Trap Trpofiling(RTP) Technique,” IEEE VLSI Symposia on TECH., 2012, pp. 189-190.(citied 5 times)</li>
<li>[18] E R. Hsieh, S. S. Chung et al., “A Novel and Direct Experimental Observation of the Discrete Dopant Effect in Ultra-scaled CMOS Devices,” IEEE VLSI Symposia on TECH., 2011, pp. 194-195. (citied 2 times)</li>
<li>[19] S. S. Chung, E R. Hsieh et al., “Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor (Si:C S/DE),” IEEE VLSI Symposia on TECH., 2009. pp. 158-159. (citied 4 times)</li>
<li>[20] M. H. Lin, E R. Hsieh, S. S. Chung et al., “A New Observation of Strain-induced Slow Traps in Advanced CMOS Technology with Process-induced Strain Using Random Telegraph Noise Measurement,” IEEE VLSI Symposia on TECH., 2009, pp. 52-53. (citied 11 times)</li>
<li>[21] E R. Hsieh, S. S. Chung et al., “A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-ballistic Regime,” IEEE IEDM, 2009, pp. 779-782. (citied 2 times)</li>
<li>[22] S. S. Chung, E R. Hsieh et al., “More Strain and Less Stress-the guideline for Developing High-end Strained CMOS Technologies with Acceptable Reliability,” IEEE IEDM, 2008, pp. 435-438. (citied 8 times)</li>
<p class="title">      其他會議論文 (IRPS , VLSI-TSA , SNW , IPFA , SSDM …)</p>
<li>[1] M. Y. Lee, C. H. Chiu, E. R. Hsieh, S. S. Chung et al., “Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism,” IEEE SNW (Virtual), Kyoto, June 13-, 2021.</li>
<li>[2] A. Gupta, C. K. Chiang, E. R. Hsieh, S. S. Chung et al., “Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance,” IEEE VLSI-TSA, (Virtual), Hsinchu, April 20-23, 2020.</li>
<li>[3] W. Y. Yang, E. R. Hsieh, S. S. Chung et al., “A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path,” in IEEE IRPS, (Virtual), March 21-24, 2021.</li>
<li>[4] W. Y. Yang, E. R. Hsieh, S. S. Chung et al., “A Self-align Gate-last Resistive Gate Switching FinFET Nonvolatile Memory Feasible for Embedded Applications,” IEEE SNW (Virtual), Hawaii, June 12-13, 2020.</li>
<li>[5] (Invited) S. S. Chung, “The Advances of OTP Memory for Embedded Applications in HKMG Generation and Beyond,” IEEE ICSICT, October 30- Nov. 2, 2019.</li>
<li>[6] F. L. Li, E. R. Hsieh, S. S. Chung et al., “A New Structure of High-performance Source/drain Coupling Negative-capacitance FET Featuring Excellent Short-channel Controllability and Near Hysteresis-free,” International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2-5, 2019.</li>
<li>[7] Y. C. Luo, F. L. Li, E. R. Hsieh, S. S. Chung et al., “The Guideline on Designing a High Performance NC MOSFET by Matching the Gate Capacitance and Mobility Enhancement,” IEEE VLSI-TSA, Apr. 22-25, 2019.</li>
<li>[8] (Invited) S. S. Chung, “Resistive Switching Non-volatile Memory Feasible for 28nm and Beyond Embedded Logic CMOS Technology,” IEEE IMW, May 12-15, 2019.</li>
<li>[9] Y. J. Lo, E. R. Hsieh and et al., “A Novel Experimental Approach to Extracting Negative Capacitances: Newly found Negative DIBL Effect in 14nm NC-FinFET and the Way to Achieve Hysteresis-free,” SSDM, 2018.</li>
<li>[10] E. R. Hsieh, S. S. Chung, and et al., “A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications, ” VLSI-TSA, 2018.</li>
<li>[11] E. R. Hsieh, S. S. Chung, and et al., “ A Novel Approach to Localize the Channel Temperature Induced by the Self-heating Effect in 14nm High-k Metal-gate FinFET,” EDTM, 2018.</li>
<li>[12] E R. Hsieh, S. S. Chung, and et al., “ The Experimental Observations of a New Dielectric-fuse Breakdown in a Bilayer-RRAM Devices to Realize the OTP Functionality,” SSDM, 2017.</li>
<li>[13] D. H. Huang, E R. Hsieh, and et al., “The impact of TiN barrier on the NBTI in an advanced high-k metal-gate p-channel MOSFET,” IEEE IPFA, 2017</li>
<li>[14] E R. Hsieh, S. S. Chung, and et al., “The issues on the power consumption of trigate FinFET: The design and manufacturing guidelines,” IEEE IPFA, 2017</li>
<li>[15] E R. Hsieh, S. S. Chung, and et al., “The guideline on designing face-tunneling FET for large-scale-device applications in IoT, ” IEEE SNW, 2017, pp. 3-4.</li>
<li>[16] E R. Hsieh, S. S. Chung, and et al., “A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications,” IEEE VLSI-TSA, 2017.</li>
<li>[17] E R. Hsieh, S. S. Chung, and et al., “ Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs,” IEEE EDTM, 2017, p. 7M-3.</li>
<li>[18] E R. Hsieh, S. S. Chung, and et al., “Geometric Variation: A Novel Approach to Examine the SurfaceRoughness and the Line Roughness Effects in Trigate FinFETs,” IEEE EDTM, 2017, p. 7M-3.</li>
<li>[19] E R. Hsieh, H. T. Wang, S. S. Chung, and et al., “Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory,” IEEE IPFA, 2016, p. 38.</li>
<li>[20] E R. Hsieh, C. Wu, S. S. Chung, and et al., “The Experimental Observation of Soft-Error Enhanced NBTI Degradation in Trigate FinFETs for the near-Cosmic Exploration of Drones,” SSDM, 2016, p. A-7-05.</li>
<li>[21] E R. Hsieh, C. H. Chuang, S. S. Chung, and et al., “An Innovative 1T1R Dipole Dynamic Random Access Memory(DiRAM) Featuring High Speed, ultra-low Power, and Low Voltage Operation, “ IEEE VLSI-TSA, 2016, p. 58.</li>
<li>[22] E R. Hsieh, P. Y. Lu, S. S. Chung, and et al., “ The RTN measurement technique on leakage path finding in advanced high-k metal gate CMOS devices, “ IEEE IPFA, 2015, p. 9-1.</li>
<li>[23] E R. Hsieh, Y. S. Lin, Y. B. Zhao, S. S. Chung, and et al., “Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications, ” IEEE SNW, 2015, p. 6-2.</li>
<li>[24] Y. B. Zhao, E. R. Hsieh, C. H. Chien, S. S. Chung, and et al., “Design of Complementary Raised Drain Tunneling FET for Ultra-low Voltage Application,”JSAP SSDM, 2015, p. K-1-2.</li>
<li>[25] C. M. Huang, K. C. Li, E R. Hsieh, S.S. Chung et al., “A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects,” IEEE SNW, 2014, p.164.</li>
<li>[26] P. C. Wu, E R. Hsieh, P. Y. Lu, S. S. Chung, and et al., “The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO 2 high-k metal gate 28nm CMOS devices,” IEEE VLSI-TSA, 2014, p. 69. (citied 2 times)</li>
<li>[27] E R. Hsieh, P. C. Wu, S. S. Chung, and et al., “A New Method to Effectively Separate PBTI-induced Shallow and Deep Energy Traps in a 28nm High-k Metal Gate MOSFET,” JSAP SSDM, 2014, p. F-1-5.</li>
<li>[28] E R. Hsieh, P. C. Wu, S. S. Chung, and et al., “The Understanding of the Bulk Trigate MOSFETs Reliability through the Manipulation of RTN Traps,”IEEE VLSI-TSA, 2013, p. 45.</li>
<li>[29] E. R. Hsieh, H. M. Tsai, S. S. Chung, and et al., “New Observations on the Corner Effect and STI-Induced Effect in Trigate CMOS Devices,” JSAP, SSDM, 2013, p. 708.</li>
<li>[30] E R. Hsieh, S. S. Chung, and et al., “The Impact of the Carrier Transport in the Random Dopant Induced Drain Current Variation in the Saturation Regime of Advanced Strained-silicon CMOS Devices,”IEEE SNW, 2012, p.78.(citied 1 times)</li>
<li>[31] E R. Hsieh, S. S. Chung, and et al., “New Criteria for the RDF Induced Drain Current Variation Considering Strain and Transport Effects in Strain-silicon CMOS Devices, ”IEEE VLSI-TSA, 2012, p. 26. (citied 1 times)</li>
<li>[32] E. R. Hsieh, H. M. Tsai, S. S. Chung, and et al.., “ The Experimental Observation of the Process Induced Random Dopant Effect in Trigate MOSFETs” JSAP, SSDM, 2012, p. 128.</li>
<li>[33] E. R. Hsieh, S. S. Chung, and et al., “A Novel and Direct Measurement of the Mobility on Very Small Dimension CMOS Devices with Channel Length Down to 20nm,”JSAP SSDM, 2012, p. E-9-3.</li>
<li>[34] X. S. Cheng, E R. Hsieh, S. S. Chung, and et al., “Experimental Determination of the Transport Parameters in High Performance Dopant-segregated Schottky-barrier MOSFETs,” IEEE VLSI-TSA, 2011, p. 120.</li>
<li>[35] E R. Hsieh, S. S. Chung, and et al., “New Observations on the Physical Mechanism of the Vth-variation in Nanoscale CMOS Devices after Long-term Stress,”IEEE IRPS, 2011, pp. XT.9.1 - XT.9.2. (citied 2 times)</li>
<li>[36] E R. Hsieh, C. Y. Cheng, S. S. Chung, and et al., “Random Trap Fluctuation (RTF) Induced Vth Variability and the Impact on the Reliability of Strained-Silicon CMOS Devices,” JSAP SSDM, 2011, p. D-5-2.</li>
<li>[37] E R. Hsieh, S. S. Chung, and et al., “A New Type of Inverter with Junctionless (J-Less) Transistors,” IEEE SNW, 2010, p. P2.7. (citied 3 times)</li>
<li>[38] M. H. Lin, E. R. Hsieh, S. S. Chung, and et al, “The Understanding of Strain-induced Device Degradation in Advanced MOSFETs with Process-induced Strain Technology of 65nm Node and Beyond,”IEEE IRPS, 2010, p. 1053.(citied 4 times)</li>
<li>[39] C. H. Chang, E. R. Hsieh, S. S. Chung, and et al, “The Investigation of the Stress-induced Traps and its Correlation to PBTI in High-k dielectrics nMSOFETs by the RTN Measurement Technique,”IEEE VLSI-TSA, 2010, p. 70.</li>
<li>[40] C. Y. Cheng, E R. Hsieh, S. S. Chung, and et al., “The Observation of the Random Dopant Fluctuation in Strained-SOI Devices,”JSAP SSDM, 2010, p. P-3-5.</li>
<li>[41] E R. Hsieh, Y. H. Chu, G. D. Lee, S. S. Chung, and et al., “Separation of Interface and Bulk Traps in advanced High-k Gate Dielectric MOSFETs from a Low-Leakage Charge Pumping Technique,”JSAP SSDM, 2009, p.C-6-5L.</li>
<li>[42] E R. Hsieh, D. W. Chang, S. S. Chung, and et al., “The Ballistic Transport and Reliability of the SOI and Strained-SOI nMSOFETs with 65nm Node and beyond Technology,”IEEE VLSI-TSA, 2009, p. 120. (citied 1 times)</li>
<p class="title">      期刊論文</p>
<li>[1] E R. Hsieh, M. R. Jaing, J. L. Lin, S. S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, and O. Cheng, "An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET." IEEE J-EDS, vol. 6, pp. 866-874(2018).</li>
<li>[2] E Ray Hsieh, Yen Chen Kuo, Chih-Hung Cheng, Jing Ling Kuo, Meng-Ru Jiang, Jian-Li Lin, Hung-Wen Chen, Steve S Chung, Chuan-Hsi Liu, Tse Pu Chen, Shih An Huang, Tai-Ju Chen, Osbert Cheng, “A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path,” IEEE, Transactions on Electron Devices, vol. 64, No. 12, pp. 4910-4918(2017). (I.F.=2.605)</li>
<li>[3] E R. Hsieh and S. S. Chung, “A Theory and Experimental Method to Evaluate Surface Roughness Variation of Trigate Metal Oxide Semiconductor Field Effect Transistors,”AIP, Journal of Applied Physics, vol. 119, p. 204502 (2016).</li>
<li>[4] E R. Hsieh and S. S. Chung, “The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement,” AIP, Applied Physic Letters, vol. 107, No. 24, p. 243506 (2015).</li>
<li>[5] E R. Hsieh and S. S. Chung, “The understanding of the drain-current fluctuation in a silicon-carbon source-drain strained n-channel metal-oxide-semiconductor field-effect transistors,” AIP, Applied Physic Letters, vol. 104, No. 20, p. 203503 (2014). (citied 1 times)</li>
<li>[6] E R. Hsieh and S. S. Chung, “The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors,” AIP, Applied Physic Letters, vol. 101, No. 22, p. 223505 (2012). (citied 3 times)</li>
<li>[7] E R. Hsieh and S. S. Chung, “The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors,” AIP,Applied Physic Letters, vol. 96, No. 9, p. 093501 (2010).(citied 14 times)</li>
<p class="title">      碩士與博士論文</p>
<li><span class="newmark">NEW </span> (碩論) <a href="" style="text-decoration: none;" >利用鰭式電晶體之變異性實現物理不可複製函數<br>
   The Implementation of Physical Unclonable Function (PUF) Based on FinFET Variation<br></a>
<div style="text-align:right;">新竹市 : 國立陽明交通大學, 2022[民111]  指導教授 莊紹勳  作者 林亮君 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="" style="text-decoration: none;" >以改良的氧化鋯鉿鐵電鰭式記憶體來實現可靠的多位元操作<br>
   Improved HfZrO2 Fe-FinFET Memory to Realizing Highly-Reliable Multi-bit Operation<br></a>
<div style="text-align:right;">新竹市 : 國立陽明交通大學, 2022[民111]  指導教授 莊紹勳  作者 張壬奎 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="" style="text-decoration: none;" >以40 nm CMOS技術實現通用安全函數功能晶片<br>
   The Chip Implementation of Universal-Security-Function (USF) on a 40 nm CMOS Technology<br></a>
<div style="text-align:right;">新竹市 : 國立陽明交通大學, 2021[民110]  指導教授 莊紹勳  作者 蔡岳穎 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="" style="text-decoration: none;" >以16奈米鰭式場效電晶體實現接面熔絲崩潰型單次編程記憶體晶片之設計與製作<br>
   The Design and Fabrication of One Time Programmable Memory with Junction Fuse Mechanism Implemented on 16nm FinFET Process<br></a>
<div style="text-align:right;">新竹市 : 國立陽明交通大學, 2021[民110]  指導教授 莊紹勳  作者 楊尚霖 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="https://hdl.handle.net/11296/em7v38" style="text-decoration: none;" >阻變式閘極電阻式記憶體的多階儲存單元操作<br>
   The Multi-Level Operation of One-Transistor Resistive Random-Access Memory with Gate-Resistance Switching<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2020[民109]  指導教授 莊紹勳  作者 陳冠廷 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="https://hdl.handle.net/11296/q34cm7" style="text-decoration: none;" >阻變式閘極鰭式場效電晶體陣列於亂數產生器之應用<br>
   Gate Resistance Switching FinFET Array for True-Random-Number Generator Application<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2020[民109]  指導教授 莊紹勳  作者 楊文燿 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="https://hdl.handle.net/11296/9wbza4" style="text-decoration: none;" >一種新穎物理不可複製函數晶片的實現<br>
   A New Architecture of Physical-unclonable-function Chip and Its Implementations<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2020[民109]  指導教授 莊紹勳  作者 王韋鈞 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="https://hdl.handle.net/11296/fx9yvt" style="text-decoration: none;" >運用多階層式電阻式記憶體實現類神經網路運算<br>
   The Implementation of Neuromorphic Computing Network By Multiple Levels Resistance Random Access Memory<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2020[民109]  指導教授 莊紹勳  作者 郭俊麟 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="https://hdl.handle.net/11296/73vjfu" style="text-decoration: none;" >低電壓低功耗之鰭式穿隧電晶體設計<br>
   The Design of Tunneling FET with Fin Structure for Low Voltage and Low Power Applications<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2020[民109]  指導教授 莊紹勳  作者 邱致豪 <div></li>
<li><span class="newmark">NEW </span> (碩論) <a href="https://hdl.handle.net/11296/49a5jv" style="text-decoration: none;" >阻變式閘極非揮發性記憶體於類神經網路之應用<br>
   Resistance-Gate Switching Nonvolatile Memory for Neuromorphic Network Application<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2020[民109]  指導教授 莊紹勳  作者 陳柏因 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/9bgf3d" style="text-decoration: none;" >改良型高性能鰭式電晶體結構 及3奈米技術節點的預測<br>
   Improved High Performance FinFET and Its Prediction Down to 3nm Technology Node<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2019[民108]  指導教授 莊紹勳  作者 蔣兆凱 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/g3858j" style="text-decoration: none;" >閘極浮接介電質反熔絲崩潰型單次編程記憶體晶片之設計與製作<br>
   The Design and Fabrication of One Time Programmable Memory with Gate Floating Anti-Fuse Breakdown<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2019[民108]  指導教授 莊紹勳  作者 莊晴智 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/amf6h9" style="text-decoration: none;" >高性能空氣隔離與空氣側壁鰭式電晶體之設計與製作<br>
   The Design and Fabrication of FinFET with Both Air Trench Isolation and Air Spacer<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2019[民108]  指導教授 莊紹勳  作者 白軒 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/8ryr27" style="text-decoration: none;" >運用鰭式場效電晶體變異性建構物理不可複製函數與亂數產生器<br>
   The Construction of Physical Unclonable Function (PUF) and True-Random-Number Generator (TRNG) Based on FinFET Variation<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2019[民108]  指導教授 莊紹勳  作者 蕭亦雯 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/8386e5" style="text-decoration: none;" >阻變式閘極非揮發性記憶體的設計與最佳化<br>
   The Design and Optimization of the One Transistor Resistance Switching Nonvolatile Memory<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2018[民107]  指導教授 莊紹勳  作者 鄭智鴻 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/5jz34s" style="text-decoration: none;" >新世代介電質熔絲崩潰型單次編程記憶體晶片之設計與製作<br>
   The Design and Fabrication of Next Generation One Time Programmable Memory Based on the Dielectric Fuse Breakdown<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2018[民107]  指導教授 莊紹勳  作者 張峻瑋 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/nhxk6a" style="text-decoration: none;" >新穎高性能鰭式電晶體結構 及其高頻特性分析<br>
   A New Architecture of FinFET for High Performance and the Analysis on Its RF Characteristics<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2017[民106]  指導教授 莊紹勳  作者 林建里 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/7s8738" style="text-decoration: none;" >14奈米鰭式電晶體自熱效應的新穎溫度量測方法 及其對傳輸機制之影響<br>
   A New Temperature Measurement Technique of the Self-Heating Effect in 14nm FinFET and Its Impact on the Transport Mechanism<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2017[民106]  指導教授 莊紹勳  作者 江孟儒 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/7bgxyr" style="text-decoration: none;" >一種新穎的鰭式電晶體可程式神經陣列 在人工神經網路的應用<br>
   A New FinFET-based Field Programmable Synapse Array (FPSA) for Artificial Neural Network Applications<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2017[民106]  指導教授 莊紹勳  作者 陳泓文 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/hrm83h" style="text-decoration: none;" >與14奈米鰭式電晶體CMOS邏輯製程相容的電阻式快閃記憶體設計<br>
   The Design of a Resistance Flash Memory on a Pure CMOS Logic Compatible 14 nm FinFET Platform<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2017[民106]  指導教授 劉傳璽，莊紹勳  作者 郭彥成 <div></li>
<li></span> (博論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070380108%22.&searchmode=basic" style="text-decoration: none;" >三維電晶體由製程與長時間操作導致電特性變異之多面向探討<br>
   Various Aspects of the Process and Stress Induced Variabilities in Tri-gate Transistors<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2016[民105]  指導教授 莊紹勳  作者 謝易叡 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070350141%22.&searchmode=basic" style="text-decoration: none;" >利用介電層熔斷崩潰之電阻式記憶單元設計新穎的內嵌式可重寫單次寫入唯讀記憶體<br>
   A Novel ReWritable One-Time-Programming Memory Realized by Dielectric-fuse of RRAM for Embedded Applications<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2016[民105]  指導教授 莊紹勳  作者 程皓瑋 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/sxhh95" style="text-decoration: none;" >穿隧式電晶體的製備與缺陷輔助穿隧分析<br>
   Fabrication of Tunnelling FET and the Analysis on the Trap-assisted tunneling<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2016[民105]  指導教授 李敏鴻，莊紹勳  作者 李俊葳 <div></li>
<li></span> (碩論) <a href="https://hdl.handle.net/11296/jfcybg" style="text-decoration: none;" >一種驗證先進三閘極電晶體幾何變異之理論與實驗方法<br>
   A New Theory and Its Experimental Verifications of Geometric Variation in Advanced Trigate FinFETs<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2016[民105]  指導教授 劉傳璽，莊紹勳  作者 范揚群 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070250105%22.&searchmode=basic" style="text-decoration: none;" >互補式面穿隧場效電晶體之結構設計與低功耗電路應用探討 <br>
   Design of the Complementary Face-Tunneling FET for Ultra-low Power Applications <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2015[民104]  指導教授 莊紹勳  作者 趙堉斌 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070250178%22.&searchmode=basic" style="text-decoration: none;" >高介電層金屬閘極CMOS電晶體功函數與臨界電壓變異之關聯性探討 <br>
   New Understandings on the Correlation Between Work-function Fluctuation and Vth Variation in HKMG CMOS Devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2015[民104]  指導教授 莊紹勳  作者 王元鼑 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi/ccd=wTMXFw/record?r1=11&h1=1" style="text-decoration: none;" >淺溝渠隔離氧化層對三維閘極電晶體的可靠性影響 <br>
   The Impact of the Shallow Trench Isolation on the Reliability of Trigate MOSFET<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2015[民104]  指導教授 莊紹勳  作者 吳嘉偉<div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070250150%22.&searchmode=basic" style="text-decoration: none;" >運用介電層熔斷崩潰機制設計新穎的單次寫入唯讀記憶體 <br>
   A One-Time-Programmable Array Based on a New Dielectric Fuse Breakdown Mechanism <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2015[民104]  指導教授 莊紹勳  作者 黃智宏 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070250183%22.&searchmode=basic" style="text-decoration: none;" >雙介電層低功耗電阻式記憶體之設計與最佳化 <br>
   The Design and Optimization of a Low Power Bi-layer Resistance RAM <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2015[民104]  指導教授 莊紹勳  作者 楊勝博 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070150147%22.&searchmode=basic" style="text-decoration: none;" >三維金氧半電晶體基本邏輯閘電路的變異性模型 <br>
   A Circuit Level Variability Model of Basic Logic Circuits in Trigate CMOS Devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2014[民103]  指導教授 莊紹勳  作者 洪健珉 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi/ccd=wTMXFw/record?r1=13&h1=1" style="text-decoration: none;" >探討金屬高介電層互補式金氧半電晶體崩潰的新穎方法 <br>
   A New Methodology on the Investigation of Dielectric Breakdown in High-K Metal-Gate CMOS Devices<br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2014[民103]  指導教授 莊紹勳  作者 呂品毅 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070150168%22.&searchmode=basic" style="text-decoration: none;" >雙介電層低功耗電阻式記憶體之設計與導通機制探討 <br>
   The Design and Fabrication of Low Power Bi-layer RRAM and the Study of Its Conduction Mechanism <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2013[民102]  指導教授 莊紹勳  作者 莊嘉暉 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070050168%22.&searchmode=basic" style="text-decoration: none;" >二氧化鉿高介電層之N通道金氧半電晶體氧化層缺陷研究 <br>
   The Investigation of Oxide Traps in Advanced HfO2 Gate Dielectric nMOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2013[民102]  指導教授 莊紹勳  作者 伍邦齊 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070050171%22.&searchmode=basic" style="text-decoration: none;" >由實驗方法分析三維金氧半電晶體的彈道傳輸特性 <br>
   Experimental Determination of the Ballistic Transport Characteristics of Nanoscale Trigate MOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2013[民102]  指導教授 莊紹勳  作者 林宗慶<div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070050147%22.&searchmode=basic" style="text-decoration: none;" >閘極漏電流的變異對三維金氧半電晶體的影響 <br>
   The Impact of the Gate Current Variation on the Trigate MOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2013[民102]  指導教授 莊紹勳  作者 林尚墩 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT070050167%22.&searchmode=basic" style="text-decoration: none;" >U型多重讀寫氮化矽快閃式記憶體之耐久性及資料保存探討 <br>
   The Investigation of Endurance and Data Retention for U-Shaped MTP SONOS Flash Memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2013[民102]  指導教授 莊紹勳  作者 王漢樽 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079911568%22.&searchmode=basic" style="text-decoration: none;" >二氧化鉿電阻式記憶體多位元操作之隨機電報雜訊分析 <br>
   The Random Telegraph Noise (RTN) Analysis of Multi-Level Operation Methods in HfO2-based ResistiveRandom    Access Memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2015[民104]  指導教授 莊紹勳  作者 黃英傑<div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079911548%22.&searchmode=basic" style="text-decoration: none;" >使用新的量測方法探討三面閘極金氧半電晶體 氧化層隨機陷阱造成之擾動效應 <br>
   The Random Trap Induced Fluctuations of Bulk Tri-gate Devices by a New Trap Profiling Technique <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2012[民101]  指導教授 莊紹勳  作者 蔡漢旻 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079911553%22.&searchmode=basic" style="text-decoration: none;" >運用隨機電報訊號方法分析三閘極電晶體的多層級氧化層陷阱 <br>
   The Multi-trap Analysis of Trigate MOSFETs Using the Random Telegraph Noise Measurement <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2012[民101]  指導教授 莊紹勳  作者 蔡侑璉 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079911581%22.&searchmode=basic" style="text-decoration: none;" >CMOS製程相容U型多重讀寫氮化矽快閃式記憶體之物理機制與可靠性探討 <br>
  Investigation of the Mechanism and Reliability of a U-Shaped MTP SONOS Flash Memory Cell by a CMOS Logic Process <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2012[民101]  指導教授 莊紹勳  作者 蔡政達 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079811550%22.&searchmode=basic" style="text-decoration: none;" >二位元分離式閘極氮化矽快閃式記憶體之先進操作方法探討 <br>
   The investigation of a novel operating method for two-bit split gate SONOS flash memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2011[民100]  指導教授 莊紹勳  作者 周承翰 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079711572%22.&searchmode=basic" style="text-decoration: none;" >二位元分離式閘極氮化矽快閃式記憶體之漏電機制探討 <br>
   The investigation of charge loss mechanism in dual-bit split-gate SONOS flash memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2010[民99]  指導教授 莊紹勳  作者 何永涵 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079711524%22.&searchmode=basic" style="text-decoration: none;" >二氧化鉿基底電阻式記憶體之動態轉換物理模型 <br>
   The physical model of the switching dynamics in HfO2-based resistive random access memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2010[民99]  指導教授 莊紹勳  作者 曾元宏 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079711580%22.&searchmode=basic" style="text-decoration: none;" >決定高效能蕭特基金氧半場效應電晶體傳輸參數的新實驗方法 <br>
    A new experimental determination of transport parameters in high performance schottky-barrier MOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2010[民99]  指導教授 莊紹勳  作者 鄭士嵩 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079711560%22.&searchmode=basic" style="text-decoration: none;" >應變矽CMOS元件中隨機摻雜與隨機界面缺陷引起的臨界電壓變異度研究 <br>
   The random dopants and random traps induced threshold voltage variations in strained CMOS devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2010[民99]  指導教授 莊紹勳  作者 程政穎 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079611576%22.&searchmode=basic" style="text-decoration: none;" >二氧化鉿薄膜電阻式隨機存取記憶體之轉換機制及可靠度探討 <br>
   The Understanding of the Switching Mechanism and Related Reliability Issues in HfO2-Based Resistive Random    Access Memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2009[民98]  指導教授 莊紹勳  作者 王振鵬 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079611542%22.&searchmode=basic" style="text-decoration: none;" >奈米級蕭特基金氧半場效電晶體之載子傳輸特性與通道背向散射研究 <br>
   TThe Carrier Transport and Channel Backscattering Characteristics of Nanoscale Schottky-Barrier MOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2009[民98]  指導教授 莊紹勳  作者 鄧安舜 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079611560%22.&searchmode=basic" style="text-decoration: none;" >隨機電報訊號量測於高閘極介電層N通道金氧半電晶體汲極電流波動之探討 <br>
   The Drain Current Fluctuation Investigated through Random Telegraph Noise in High-k Dielectric n-MOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2009[民98]  指導教授 莊紹勳  作者 張健宏 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT079611529%22.&searchmode=basic" style="text-decoration: none;" >隨機電報訊號量測法應用於前瞻CMOS元件應變技術引致的汲極電流不穩定性之研究 <br>
   The Observation of Strain Induced Drain Current Instability in Advanced CMOS Devices Using Random Telegraph Noise Analysis <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2009[民98]  指導教授 莊紹勳  作者 林米華 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi/ccd=Xferpr/login?jstimes=1&loadingjs=1&userid=guest&o=dwebmge&cache=1500279079916" style="text-decoration: none;" >一種改良的介面缺陷之橫向剖面分析應用於奈米級應變矽CMOS元件之可靠度探討 <br>
   An improved Interface Traps Profiling on the Study of Reliability in Strained CMOS Devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2008[民97]  指導教授 莊紹勳  作者 謝易叡 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009511570%22.&searchmode=basic" style="text-decoration: none;" >二位元SONOS快閃式記憶體之物理機制與可靠性探討 <br>
   Investigation of the Mechanism and Reliability in a Two-Bit SONOS Flash Memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2008[民97]  指導教授 莊紹勳  作者 郭建鴻 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009511599%22.&searchmode=basic" style="text-decoration: none;" >以鉿為基底之高介電常數閘極介電層之N通道金氧半 電晶體可靠度探討 <br>
   Investigation of Reliability in Advanced Hf-Based High-k Gate Dielectrics nMOSFETs <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2008[民97]  指導教授 莊紹勳  作者 曾友良 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009511548%22.&searchmode=basic" style="text-decoration: none;" >奈米應變矽元件載子傳輸模型分析與其可靠度相關性探討 <br>
   Transport Analysis and the Reliability Correlation in Nanoscale Strained-Silicon Devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2008[民97]  指導教授 莊紹勳  作者 張文彥 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009511574%22.&searchmode=basic" style="text-decoration: none;" >探討高閘極介電層N通道金氧半電晶體的新穎閘極電流隨機電報量測法 <br>
   The Observation of Gate Current Instability in High-k Gate Dielectric MOSFET by a New Gate Current Random     Telegraph Noise Approach <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2008[民97]  指導教授 莊紹勳  作者 張家銘 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009494503%22.&searchmode=basic" style="text-decoration: none;" >低電壓且高速操作的P通道快閃式記憶體元件性能及可靠性研究 <br>
   Performance and Reliability Evaluation of a Low Voltage and High Speed P-channel Floating Gate Flash Memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2007[民96]  指導教授 莊紹勳  作者 黃耀賢 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009411577%22.&searchmode=basic" style="text-decoration: none;" >奈米應變矽CMOS元件之通道背向散射特性與可靠度之相關性研究 <br>
   The Channel Backscattering Characteristics of Nanoscale Strained-CMOS and Its Correlation to the Reliability <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2007[民96]  指導教授 莊紹勳  作者 蔡亞峻 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009211541%22.&searchmode=basic" style="text-decoration: none;" >不同界面層與環狀植入對高介電氧化層CMOS元件可靠性影響之研究 <br>
   The Impact of Interfacial Layer and the Halo Implant on the Reliability of High K Dielectric CMOS Devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2005[民94]  指導教授 莊紹勳  作者 李冠德 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009211574%22.&searchmode=basic" style="text-decoration: none;" >高介電氧化層MOSFET元件之低漏電電荷幫浦量測技術 <br>
   A Low Leakage Charge Pumping Measurement Technique for High-K MOSFET’s <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2005[民94]  指導教授 莊紹勳  作者 朱益輝 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009211540%22.&searchmode=basic" style="text-decoration: none;" >氮化矽記憶體元件資料保存及耐久性之探討 <br>
   The Investigation of Data Retention and Endurance in a Nitride Storage Flash Memory <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2005[民94]  指導教授 莊紹勳  作者 陳靖泓 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009211557%22.&searchmode=basic" style="text-decoration: none;" >應變矽奈米CMOS元件的熱載子可靠性研究與分析 <br>
   Investigation of Hot Carrier Reliabilities in Strained-Silicon Nanoscale CMOS Devices <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2005[民94]  指導教授 莊紹勳  作者 劉又仁 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009111540%22.&searchmode=basic" style="text-decoration: none;" >先進互補式金氧半元件的閘極層厚度1nm範圍下之低漏電電荷幫浦量測技術 <br>
   Low Leakage Charge Pumping Measurement Techniques for Advanced CMOS with Gate Oxide in the 1nm Range <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2004[民93]  指導教授 莊紹勳  作者 馮信榮 <div></li>
<li></span> (碩論) <a href="http://etd.lib.nctu.edu.tw/cgi-bin/gs32/tugsweb.cgi?o=dnctucdr&s=id=%22GT009111576%22.&searchmode=basic" style="text-decoration: none;" >先進氮化超薄氧化層及堆疊氧化層結構CMOS元件在熱載子與高溫負偏壓操作下的探討 <br>
   Understanding of the Hot Carrier and NBTI Effects for Advanced CMOS Devices with SiON and N/O stack <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2004[民93]  指導教授 莊紹勳  作者 顧子強 <div></li>
<li></span> (碩論) <a href="http://webpac.lib.nctu.edu.tw/F/L3KKI1TXBLUN42C6BAED6G5VHMVC4BB8PAUUID41HM3RIVLKGS-03842?func=item-global&doc_library=TOP01&doc_number=000949806&year=&volume=&sub_library=" style="text-decoration: none;" >具有直接穿隧氧化層氮化矽記憶體資料保存特性之探討 <br>
   The Investigation of Data Retention in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 2003[民92]  指導教授 莊紹勳  作者 蔣步堯 <div></li>
<li></span> (碩論) <a href="http://webpac.lib.nctu.edu.tw/F/L3KKI1TXBLUN42C6BAED6G5VHMVC4BB8PAUUID41HM3RIVLKGS-01021?func=item-global&doc_library=TOP01&doc_number=000784313&year=&volume=&sub_library=" style="text-decoration: none;" >渠溝隔離金氧半電晶體的模擬與模式 <br>
   SThe Simulation and Modeling of a Trench-Isolated MOS Transistor <br></a>
<div style="text-align:right;">新竹市 : 國立交通大學, 1990[民79]  指導教授 莊紹勳  作者 李東奇 <div></li>
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