Question of the verlilog

[Natsuki-Min]

I just cant get across.I read the Verlilog.If I'm not mistaken, in your Verilog code, you've implemented the write portion using a variable named bytecnt to achieve receiving 16-bit data at a time, but it's directly set to 1. However, the transmitting side still sends 16 bits at a time. According to this logic, it would send a single byte of data twice. Is this really the intended design?

[Natsuki-Min]

Bsides that，have you successfully found out whether casio caculator has the debug point？

[Fraserbc]

Hi sorry for not responding, I didn't see the this issue. The verilog works because I'm using a non-blocking assignment and so the if (r_byte_cnt) begin doesn't actually see the 1 until the second time around

[Fraserbc]

Also no I sadly never found the debug port