From 85fd6164a5e55824e58d440a086acdb8ae440f83 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Wed, 28 Aug 2024 17:16:10 +0000 Subject: [PATCH] dts: stm32_gpio: add GPIO banks RIF configurations for stm32mp257f-ev1 Add initial RIF GPIO configuration for stm32mp257f-ev1 board. Signed-off-by: Gatien Chevallier Reviewed-by: Etienne Carriere --- .../dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi | 234 ++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi b/core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi index 110dd08a7b6..24a7f741b38 100644 --- a/core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi +++ b/core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi @@ -137,3 +137,237 @@ >; st,glocked = ; }; + +&gpioa { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiob { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioc { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiod { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioe { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiof { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiog { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioh { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioi { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioj { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(10), EMPTY_SEMWL, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN) + RIFPROT(RIF_IOPORT_PIN(11), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(12), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(13), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(14), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(15), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpiok { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +}; + +&gpioz { + st,protreg = < + RIFPROT(RIF_IOPORT_PIN(0), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(1), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(5), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(6), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(7), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(8), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + RIFPROT(RIF_IOPORT_PIN(9), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID0, RIF_SEM_DIS, RIF_CFDIS) + >; +};