From 8b19d9f9d9b00cf6a2f1009397d8c2effdffa993 Mon Sep 17 00:00:00 2001 From: Alvin Chang Date: Wed, 24 Jul 2024 23:24:19 +0800 Subject: [PATCH] core: riscv: Let platform choose native and foreign interrupts Platform may want to choose different types of native and foreign interrupts. This commit adds two definitions for the platforms: 1. PLAT_THREAD_EXCP_FOREIGN_INTR: to define platform specific foreign interrupts 2. PLAT_THREAD_EXCP_NATIVE_INTR: to define platform specific native interrupts. For RISC-V virt machine, we define external interrupts as foreign interrupts, and mtimer/software interrupts as native interrupts. For RISC-V spike platform, the definitions are same as virt machine. Signed-off-by: Alvin Chang Reviewed-by: Yu Chien Peter Lin Acked-by: Jens Wiklander --- core/arch/riscv/include/kernel/thread_arch.h | 28 +++++++++----------- core/arch/riscv/plat-spike/platform_config.h | 4 +++ core/arch/riscv/plat-virt/platform_config.h | 4 +++ 3 files changed, 21 insertions(+), 15 deletions(-) diff --git a/core/arch/riscv/include/kernel/thread_arch.h b/core/arch/riscv/include/kernel/thread_arch.h index 5e2f100f359..7bc27872c0a 100644 --- a/core/arch/riscv/include/kernel/thread_arch.h +++ b/core/arch/riscv/include/kernel/thread_arch.h @@ -8,10 +8,22 @@ #ifndef __ASSEMBLER__ #include -#include #include #endif +#include +#include + +/* + * Each RISC-V platform must define their own values. + * See core/arch/riscv/plat-virt/platform_config.h for example. + */ +#define THREAD_EXCP_FOREIGN_INTR PLAT_THREAD_EXCP_FOREIGN_INTR +#define THREAD_EXCP_NATIVE_INTR PLAT_THREAD_EXCP_NATIVE_INTR + +#define THREAD_EXCP_ALL (THREAD_EXCP_FOREIGN_INTR |\ + THREAD_EXCP_NATIVE_INTR) + #ifndef __ASSEMBLER__ #define THREAD_CORE_LOCAL_ALIGNED __aligned(16) @@ -154,20 +166,6 @@ struct thread_ctx_regs { struct user_mode_ctx; -/* - * These flags should vary according to the privilege mode selected - * to run OP-TEE core on (M/HS/S). For now default to S-Mode. - */ - -#define CSR_XIE_SIE BIT64(IRQ_XSOFT) -#define CSR_XIE_TIE BIT64(IRQ_XTIMER) -#define CSR_XIE_EIE BIT64(IRQ_XEXT) - -#define THREAD_EXCP_FOREIGN_INTR CSR_XIE_EIE -#define THREAD_EXCP_NATIVE_INTR (CSR_XIE_SIE | CSR_XIE_TIE) -#define THREAD_EXCP_ALL (THREAD_EXCP_FOREIGN_INTR |\ - THREAD_EXCP_NATIVE_INTR) - #ifdef CFG_WITH_VFP uint32_t thread_kernel_enable_vfp(void); void thread_kernel_disable_vfp(uint32_t state); diff --git a/core/arch/riscv/plat-spike/platform_config.h b/core/arch/riscv/plat-spike/platform_config.h index 7a3ff4305aa..528dad5e483 100644 --- a/core/arch/riscv/plat-spike/platform_config.h +++ b/core/arch/riscv/plat-spike/platform_config.h @@ -9,6 +9,7 @@ #define PLATFORM_CONFIG_H #include +#include #ifndef HTIF_BASE #define HTIF_BASE 0x40008000 @@ -19,4 +20,7 @@ #define CLINT_BASE 0x02000000 #endif +#define PLAT_THREAD_EXCP_FOREIGN_INTR (CSR_XIE_EIE) +#define PLAT_THREAD_EXCP_NATIVE_INTR (CSR_XIE_SIE | CSR_XIE_TIE) + #endif diff --git a/core/arch/riscv/plat-virt/platform_config.h b/core/arch/riscv/plat-virt/platform_config.h index 064cca29cf2..9fe6b50c51e 100644 --- a/core/arch/riscv/plat-virt/platform_config.h +++ b/core/arch/riscv/plat-virt/platform_config.h @@ -9,6 +9,7 @@ #define PLATFORM_CONFIG_H #include +#include /* The stack pointer is always kept 16-byte aligned */ #define STACK_ALIGNMENT 16 @@ -92,4 +93,7 @@ #define RISCV_MTIME_RATE 1000000 #endif +#define PLAT_THREAD_EXCP_FOREIGN_INTR (CSR_XIE_EIE) +#define PLAT_THREAD_EXCP_NATIVE_INTR (CSR_XIE_SIE | CSR_XIE_TIE) + #endif /*PLATFORM_CONFIG_H*/