From 9f16a05bc4e9b5cfdd28bcb6ac9b597645071404 Mon Sep 17 00:00:00 2001 From: Alvin Chang Date: Tue, 26 Sep 2023 17:31:08 +0800 Subject: [PATCH] core: riscv: Implement thread_vector_table for ABI and FIQ entries Implement thread_vector_table which only includes entries for standard ABI, fast ABI, and foreign interrupts. Most of code is referenced from ARM architecture. The thread_vector_table will be registered into higher privileged software, such as M-mode firmware. The higher privileged software can jump(mret) to OP-TEE based on this vector table. Signed-off-by: Alvin Chang --- core/arch/riscv/kernel/asm-defines.c | 4 ++ core/arch/riscv/kernel/thread_optee_abi_rv.S | 65 ++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/core/arch/riscv/kernel/asm-defines.c b/core/arch/riscv/kernel/asm-defines.c index d74c2c1e08b..df8f84b11b5 100644 --- a/core/arch/riscv/kernel/asm-defines.c +++ b/core/arch/riscv/kernel/asm-defines.c @@ -86,4 +86,8 @@ DEFINES DEFINE(CORE_MMU_CONFIG_SIZE, sizeof(struct core_mmu_config)); DEFINE(CORE_MMU_CONFIG_SATP, offsetof(struct core_mmu_config, satp)); + + /* struct thread_abi_args */ + DEFINE(THREAD_ABI_ARGS_A0, offsetof(struct thread_abi_args, a0)); + DEFINE(THREAD_ABI_ARGS_SIZE, sizeof(struct thread_abi_args)); } diff --git a/core/arch/riscv/kernel/thread_optee_abi_rv.S b/core/arch/riscv/kernel/thread_optee_abi_rv.S index 99e4f7b8f03..a49a72abe09 100644 --- a/core/arch/riscv/kernel/thread_optee_abi_rv.S +++ b/core/arch/riscv/kernel/thread_optee_abi_rv.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* * Copyright 2023 NXP + * Copyright (c) 2023 Andes Technology Corporation */ #include @@ -123,3 +124,67 @@ FUNC thread_rpc , : addi sp, sp, REGOFF(4) ret END_FUNC thread_rpc + +LOCAL_FUNC vector_std_abi_entry, : , .identity_map + jal thread_handle_std_abi + /* + * Normally thread_handle_std_abi() should return via + * thread_exit(), thread_rpc(), but if thread_handle_std_abi() + * hasn't switched stack (error detected) it will do a normal "C" + * return. + */ + /* Restore thread_handle_std_abi() return value */ + mv a1, a0 + li a2, 0 + li a3, 0 + li a4, 0 + li a0, TEEABI_OPTEED_RETURN_CALL_DONE + + /* Return to untrusted domain */ + j teeabi_return_to_ree +END_FUNC vector_std_abi_entry + +LOCAL_FUNC vector_fast_abi_entry , : , .identity_map + addi sp, sp, -THREAD_ABI_ARGS_SIZE + store_xregs sp, THREAD_ABI_ARGS_A0, REG_A0, REG_A7 + mv a0, sp + jal thread_handle_fast_abi + load_xregs sp, THREAD_ABI_ARGS_A0, REG_A1, REG_A7 + addi sp, sp, THREAD_ABI_ARGS_SIZE + + li a0, TEEABI_OPTEED_RETURN_CALL_DONE + /* Return to untrusted domain */ + j teeabi_return_to_ree +END_FUNC vector_fast_abi_entry + +LOCAL_FUNC vector_fiq_entry , : , .identity_map + /* Secure Monitor received a FIQ and passed control to us. */ + jal interrupt_main_handler + + li a0, TEEABI_OPTEED_RETURN_FIQ_DONE + /* Return to untrusted domain */ + j teeabi_return_to_ree +END_FUNC vector_fiq_entry + +/* + * Vector table supplied to M-mode secure monitor (e.g., openSBI) at + * initialization. + * + * Note that M-mode secure monitor depends on the layout of this vector table, + * any change in layout has to be synced with M-mode secure monitor. + */ +FUNC thread_vector_table , : , .identity_map, , nobti + .option push + .option norvc + j vector_std_abi_entry + j vector_fast_abi_entry + j . + j . + j . + j . + j vector_fiq_entry + j . + j . + .option pop +END_FUNC thread_vector_table +DECLARE_KEEP_PAGER thread_vector_table