From e3b48433ff6c04c94c43acd2241d06e030f16a8f Mon Sep 17 00:00:00 2001 From: James Molloy Date: Mon, 21 Oct 2024 09:19:02 -0700 Subject: [PATCH] [xls][mlir] Add CodegenFlags and SchedulingOptionsFlags to xls_translate's options struct Also accept ABSL flags in the xls_translate binary. This removes the half-implemented set of flags that we'd baked into xls_translate and allows the user to provide their own flags on the command line. PiperOrigin-RevId: 688161886 --- .../testdata/integration/soft_blocks_lut.mlir | 2 +- .../testdata/translate_combinational.mlir | 4 +-- .../mlir/tools/xls_translate/xls_translate.cc | 27 ++----------------- .../mlir/tools/xls_translate/xls_translate.h | 27 +++++++++++-------- .../tools/xls_translate/xls_translate_main.cc | 20 ++++++++++++-- 5 files changed, 39 insertions(+), 41 deletions(-) diff --git a/xls/contrib/mlir/testdata/integration/soft_blocks_lut.mlir b/xls/contrib/mlir/testdata/integration/soft_blocks_lut.mlir index fa81952362..534521f7d2 100644 --- a/xls/contrib/mlir/testdata/integration/soft_blocks_lut.mlir +++ b/xls/contrib/mlir/testdata/integration/soft_blocks_lut.mlir @@ -3,7 +3,7 @@ // RUN: > %t // RUN: xls/contrib/mlir/xls_opt --xls-lower %s \ -// RUN: | xls/contrib/mlir/xls_translate --mlir-xls-to-verilog \ +// RUN: | xls/contrib/mlir/xls_translate --mlir-xls-to-verilog -- --delay_model=asap7 --generator=combinational \ // RUN: | FileCheck --check-prefix=CHECK-VERILOG %s // RUN: xls/tools/codegen_main %t \ diff --git a/xls/contrib/mlir/testdata/translate_combinational.mlir b/xls/contrib/mlir/testdata/translate_combinational.mlir index 2244cddb8c..fbc2335159 100644 --- a/xls/contrib/mlir/testdata/translate_combinational.mlir +++ b/xls/contrib/mlir/testdata/translate_combinational.mlir @@ -1,5 +1,5 @@ -// RUN: xls/contrib/mlir/xls_translate --mlir-xls-to-xls %s --main-function=combinational -- 2>&1 | FileCheck %s --dump-input-filter=all --check-prefix=XLS -// RUN: xls/contrib/mlir/xls_translate --mlir-xls-to-verilog %s --main-function=combinational -- 2>&1 | FileCheck %s --dump-input-filter=all --check-prefix=VERILOG-COMB +// RUN: xls/contrib/mlir/xls_translate --mlir-xls-to-xls %s --main-function=combinational -- --delay_model=asap7 --generator=combinational 2>&1 | FileCheck %s --dump-input-filter=all --check-prefix=XLS +// RUN: xls/contrib/mlir/xls_translate --mlir-xls-to-verilog %s --main-function=combinational -- --delay_model=asap7 --generator=combinational 2>&1 | FileCheck %s --dump-input-filter=all --check-prefix=VERILOG-COMB // XLS: fn combinational([[ARG0:.*]]: bits[8]{{.*}}, [[ARG1:.*]]: bits[8]{{.*}}, [[ARG2:.*]]: bits[8]{{.*}}) -> bits[8] { // XLS: [[DIFF:[a-z0-9.]+]]: bits[8] = sub([[ARG0]], [[ARG1]] diff --git a/xls/contrib/mlir/tools/xls_translate/xls_translate.cc b/xls/contrib/mlir/tools/xls_translate/xls_translate.cc index c7f7ebee54..c8185f6a26 100644 --- a/xls/contrib/mlir/tools/xls_translate/xls_translate.cc +++ b/xls/contrib/mlir/tools/xls_translate/xls_translate.cc @@ -1283,32 +1283,9 @@ LogicalResult MlirXlsToXlsTranslate(Operation* op, llvm::raw_ostream& output, return success(); } - auto scheduling_options_flags_proto = ::xls::GetSchedulingOptionsFlagsProto(); - if (!scheduling_options_flags_proto.ok()) { - llvm::errs() << "Failed to get scheduling options flags proto: " - << scheduling_options_flags_proto.status().message() << "\n"; - return failure(); - } - auto codegen_flags_proto = ::xls::GetCodegenFlags(); - if (!codegen_flags_proto.ok()) { - llvm::errs() << "Failed to get codegen flags proto: " - << codegen_flags_proto.status().message() << "\n"; - return failure(); - } - - if (options.pipeline_stages > 0) { - codegen_flags_proto->set_generator(::xls::GENERATOR_KIND_PIPELINE); - } else { - codegen_flags_proto->set_generator(::xls::GENERATOR_KIND_COMBINATIONAL); - } - codegen_flags_proto->set_register_merge_strategy( - ::xls::RegisterMergeStrategyProto::STRATEGY_DONT_MERGE); - scheduling_options_flags_proto->set_delay_model(options.delay_model); - scheduling_options_flags_proto->set_pipeline_stages(options.pipeline_stages); - codegen_flags_proto->set_reset(options.reset_signal_name); - auto xls_codegen_results = ::xls::ScheduleAndCodegenPackage( - package->get(), *scheduling_options_flags_proto, *codegen_flags_proto, + package->get(), options.scheduling_options_flags_proto, + options.codegen_flags_proto, /*with_delay_model=*/false); if (!xls_codegen_results.ok()) { llvm::errs() << "Failed to codegen: " diff --git a/xls/contrib/mlir/tools/xls_translate/xls_translate.h b/xls/contrib/mlir/tools/xls_translate/xls_translate.h index 8f6798ea8a..e170693457 100644 --- a/xls/contrib/mlir/tools/xls_translate/xls_translate.h +++ b/xls/contrib/mlir/tools/xls_translate/xls_translate.h @@ -19,9 +19,14 @@ #include #include "absl/container/flat_hash_map.h" +#include "absl/log/check.h" #include "absl/status/statusor.h" #include "llvm/include/llvm/ADT/StringRef.h" #include "mlir/include/mlir/Support/LLVM.h" +#include "xls/tools/codegen_flags.h" +#include "xls/tools/codegen_flags.pb.h" +#include "xls/tools/scheduling_options_flags.h" +#include "xls/tools/scheduling_options_flags.pb.h" namespace mlir { class Operation; @@ -50,6 +55,12 @@ class DslxPackageCache { absl::flat_hash_map> cache; }; +template +T DieUnlessOk(const absl::StatusOr& status_or) { + CHECK_OK(status_or.status()); + return status_or.value(); +} + struct MlirXlsToXlsTranslateOptions { // The name of the main function to translate. llvm::StringRef main_function = ""; @@ -69,17 +80,11 @@ struct MlirXlsToXlsTranslateOptions { // Optional cache for DSLX translation results. DslxPackageCache* dslx_cache = nullptr; - // Verilog emission options. - - // The number of pipeline stages to (attempt to) generate. If zero, the - // combinational generator will be used. - int pipeline_stages = 0; - - // The delay model to use. - std::string delay_model = "asap7"; - - // The name of the reset signal. - std::string reset_signal_name = "rst"; + // Codegen options. + ::xls::CodegenFlagsProto codegen_flags_proto = + DieUnlessOk(::xls::GetCodegenFlags()); + ::xls::SchedulingOptionsFlagsProto scheduling_options_flags_proto = + DieUnlessOk(::xls::GetSchedulingOptionsFlagsProto()); }; // Translates an operation with XLS dialect to DSLX. diff --git a/xls/contrib/mlir/tools/xls_translate/xls_translate_main.cc b/xls/contrib/mlir/tools/xls_translate/xls_translate_main.cc index 9f4cd5e247..1ca989b4a9 100644 --- a/xls/contrib/mlir/tools/xls_translate/xls_translate_main.cc +++ b/xls/contrib/mlir/tools/xls_translate/xls_translate_main.cc @@ -103,6 +103,22 @@ TranslateFromMLIRRegistration mlirXlsToVerilogTranslateRegistration( } // namespace mlir::xls int main(int argc, char** argv) { - xls_init_xls("Initializing XLS", 1, argv); - return failed(mlir::mlirTranslateMain(argc, argv, "XLS translator\n")); + // We allow ABSL flags to be passed to this binary after a double-dash: + // xls_translate ... -- --alsologtostderr + char** mlir_argv = argv; + char** absl_argv = argv; + int mlir_argc = argc, absl_argc = 1; + for (int i = 0; i < argc; ++i) { + if (std::string(argv[i]) == std::string("--")) { + // -- found; split into MLIR and ABSL args. + absl_argv = &argv[i]; // -- becomes argv[0] for absl. + mlir_argc = i; + absl_argc = argc - i; + break; + } + } + xls_init_xls("Initializing XLS", absl_argc, absl_argv); + + return failed( + mlir::mlirTranslateMain(mlir_argc, mlir_argv, "XLS translator\n")); }