From 435cf62a3edd9ad2dc31ddc5dc2befed8bdaede0 Mon Sep 17 00:00:00 2001 From: clbigger Date: Wed, 22 May 2024 11:51:33 -0700 Subject: [PATCH 1/2] Update for Ecore TMA 3.6 --- GRR/metrics/grandridge_metrics.json | 2229 +++++++++++++++- GRR/metrics/perf/grandridge_metrics_perf.json | 548 +++- .../perf/sierraforest_metrics_perf.json | 590 +++- SRF/metrics/sierraforest_metrics.json | 2369 ++++++++++++++++- 4 files changed, 5560 insertions(+), 176 deletions(-) diff --git a/GRR/metrics/grandridge_metrics.json b/GRR/metrics/grandridge_metrics.json index 53a42b4c..a33b0afa 100644 --- a/GRR/metrics/grandridge_metrics.json +++ b/GRR/metrics/grandridge_metrics.json @@ -2,9 +2,11 @@ "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", "Info": "Performance Monitoring Metrics for Intel(R) Grand Ridge Base Transceiver Station Family0", - "DatePublished": "02/12/2024", + "DatePublished": "05/21/2024", "Version": "0", - "Legend": "" + "Legend": "", + "TmaVersion": "3.6", + "TmaFlavor": "Public" }, "Metrics": [ { @@ -31,9 +33,7 @@ ], "Formula": "(a / b * c) / 1000000000", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "uncore_frequency", @@ -59,9 +59,7 @@ ], "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "cpu_utilization", @@ -82,9 +80,7 @@ "Constants": [], "Formula": "100 * a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "cpi", @@ -105,9 +101,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l2_mpi", @@ -128,9 +122,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "memory_bandwidth_read", @@ -151,9 +143,7 @@ "Constants": [], "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM" }, { "MetricName": "memory_bandwidth_write", @@ -174,9 +164,7 @@ "Constants": [], "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM" }, { "MetricName": "memory_bandwidth_total", @@ -205,15 +193,13 @@ "Constants": [], "Formula": "((a + b + c + d) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM" }, { "MetricName": "loads_retired_per_instr", "LegacyName": "metric_loads retired per instr", "Level": 1, - "BriefDescription": "", + "BriefDescription": "Load operations retired per instruction", "UnitOfMeasure": "per instruction", "Events": [ { @@ -228,15 +214,13 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "stores_retired_per_instr", "LegacyName": "metric_stores retired per instr", "Level": 1, - "BriefDescription": "", + "BriefDescription": "Store operations retired per instruction", "UnitOfMeasure": "per instruction", "Events": [ { @@ -251,9 +235,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l1d_demand_data_read_hits_per_instr", @@ -274,9 +256,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", @@ -297,9 +277,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l2_demand_data_read_hits_per_instr", @@ -320,9 +298,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l2_demand_data_read_mpi", @@ -343,9 +319,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "llc_data_read_mpi_demand_plus_prefetch", @@ -374,9 +348,7 @@ "Constants": [], "Formula": "(a + b + c) / d", "Category": "", - "Threshold": "", - "ResolutionLevels": "SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "SOCKET, SYSTEM" }, { "MetricName": "llc_code_read_mpi_demand_plus_prefetch", @@ -401,9 +373,7 @@ "Constants": [], "Formula": "(a + b) / d", "Category": "", - "Threshold": "", - "ResolutionLevels": "SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "SOCKET, SYSTEM" }, { "MetricName": "llc_demand_data_read_miss_latency", @@ -437,9 +407,7 @@ ], "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "itlb_2nd_level_mpi", @@ -460,9 +428,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "itlb_2nd_level_large_page_mpi", @@ -483,9 +449,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "dtlb_2nd_level_load_mpi", @@ -506,9 +470,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", @@ -529,9 +491,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "dtlb_2nd_level_store_mpi", @@ -552,9 +512,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "io_bandwidth_read", @@ -571,9 +529,7 @@ "Constants": [], "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "io_bandwidth_write", @@ -594,9 +550,2132 @@ "Constants": [], "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "ResolutionLevels": "CHA, SOCKET, SYSTEM" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "IFetch_Latency", + "LegacyName": "metric_TMA_..IFetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.frontend_latency / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ICACHE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.icache / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....ICache_Misses(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ITLB_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.itlb_miss / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....ITLB_Misses(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Detect", + "LegacyName": "metric_TMA_....Branch_Detect(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.branch_detect / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Branch_Detect(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Resteer", + "LegacyName": "metric_TMA_....Branch_Resteer(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.branch_resteer / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Branch_Resteer(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "IFetch_Bandwidth", + "LegacyName": "metric_TMA_..IFetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.frontend_bandwidth / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Cisc", + "LegacyName": "metric_TMA_....Cisc(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.CISC", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.cisc / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Cisc(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Decode", + "LegacyName": "metric_TMA_....Decode(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.DECODE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.decode / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Decode(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Predecode", + "LegacyName": "metric_TMA_....Predecode(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.PREDECODE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.predecode / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Predecode(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Other_FB", + "LegacyName": "metric_TMA_....Other_FB(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.OTHER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.other / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Other_FB(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.mispredict / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Branch_Mispredicts(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.machine_clears / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Nuke", + "LegacyName": "metric_TMA_....Nuke(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.NUKE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.nuke / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Nuke(%) >0.05 && metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Fast_Nuke", + "LegacyName": "metric_TMA_....Fast_Nuke(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.fastnuke / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Fast_Nuke(%) >0.05 && metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.alloc_restrictions / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Core_Bound(%) >0.10 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Allocation_Restriction", + "LegacyName": "metric_TMA_....Allocation_Restriction(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.alloc_restrictions / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Allocation_Restriction(%) >0.10 && metric_TMA_..Core_Bound(%) >0.10 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Resource_Bound", + "LegacyName": "metric_TMA_..Resource_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + }, + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( ( 6 ) * ( b ) ) ) - ( c / ( ( 6 ) * ( b ) ) ) ) )", + "BaseFormula": " ( ( topdown_be_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) ) ) - tma_core_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Mem_Scheduler", + "LegacyName": "metric_TMA_....Mem_Scheduler(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Mem_Scheduler(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Non_Mem_Scheduler", + "LegacyName": "metric_TMA_....Non_Mem_Scheduler(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.non_mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Non_Mem_Scheduler(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Register", + "LegacyName": "metric_TMA_....Register(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.REGISTER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.register / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Register(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Reorder_Buffer", + "LegacyName": "metric_TMA_....Reorder_Buffer(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.reorder_buffer / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Reorder_Buffer(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Serialization", + "LegacyName": "metric_TMA_....Serialization(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.SERIALIZATION", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.serialization / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Serialization(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "Counts the number of issue slots that result in retirement slots", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_retiring.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Retiring(%) >0.75" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_Mem_Exec_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_Mem_Exec_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * ld_head.any_at_ret / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem_Exec" + }, + { + "MetricName": "Info_Bottleneck_Load_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_Load_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_load.all / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Load_Store_Miss" + }, + { + "MetricName": "Info_Bottleneck_DTLB_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_DTLB_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.DTLB_MISS_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.PGWALK_AT_RET", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a + b ) / ( c )", + "BaseFormula": " 100 * ( ld_head.dtlb_miss_at_ret + ld_head.pgwalk_at_ret ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_IFetch_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_IFetch_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.all / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Ifetch" + }, + { + "MetricName": "Info_Core_IPC", + "LegacyName": "metric_TMA_Info_Core_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " inst_retired.any / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Core_CPI", + "LegacyName": "metric_TMA_Info_Core_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": " ( cpu_clk_unhalted.core ) / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Core_UPI", + "LegacyName": "metric_TMA_Info_Core_UPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " topdown_retiring.all_p / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_FLOPS_RETIRED.ALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " fp_flops_retired.all / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_inst_retired.near_call", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpFarBranch", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_inst_retired.far_branch:user", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpMispredict", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMispredict", + "Level": 1, + "BriefDescription": "Instructions per retired Branch Misprediction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.all_branches", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND", + "Alias": "b" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b - c )", + "BaseFormula": " inst_retired.any / ( br_misp_retired.cond - br_misp_retired.cond_taken )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired conditional Branch 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mem_bound_stalls_load.l2_hit / mem_bound_stalls_load.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Miss_Bound_LoadMissBound_with_L3Hit", + "LegacyName": "metric_TMA_Info_Load_Miss_Bound_%_LoadMissBound_with_L3Hit", + "Level": 1, + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.LLC_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_bound_stalls_load.llc_hit / mem_bound_stalls_load.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Ifetch_Miss_Bound_IfetchMissBound_with_L2Hit", + "LegacyName": "metric_TMA_Info_Ifetch_Miss_Bound_%_IfetchMissBound_with_L2Hit", + "Level": 1, + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.l2_hit / ( mem_bound_stalls_ifetch.all )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Ifetch_Miss_Bound_IfetchMissBound_with_L3Hit", + "LegacyName": "metric_TMA_Info_Ifetch_Miss_Bound_%_IfetchMissBound_with_L3Hit", + "Level": 1, + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.llc_hit / ( mem_bound_stalls_ifetch.all )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Mispredict_Bound_Branch_Mispredict_Ratio", + "LegacyName": "metric_TMA_Info_Br_Mispredict_Bound_Branch_Mispredict_Ratio", + "Level": 1, + "BriefDescription": "Ratio of all branches which mispredict", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_misp_retired.all_branches / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Mispredict_Bound_Branch_Mispredict_to_Unknown_Branch_Ratio", + "LegacyName": "metric_TMA_Info_Br_Mispredict_Bound_Branch_Mispredict_to_Unknown_Branch_Ratio", + "Level": 1, + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_misp_retired.all_branches / baclears.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_FP_Assist_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_FP_Assist_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.FP_ASSIST", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.fp_assist / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_Page_Fault_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_Page_Fault_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.page_fault / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_SMC_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_SMC_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.SMC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.smc / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Store_Buffer_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Store_Buffer_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.ST_BUF", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.st_buf / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Load_Buffer_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Load_Buffer_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.LD_BUF", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.ld_buf / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Mem_RSV_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Mem_RSV_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.RSV", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.rsv / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Serialization_Tpause_Cycles", + "LegacyName": "metric_TMA_Info_Serialization _%_Tpause_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "SERIALIZATION.C01_MS_SCB", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( ( 6 ) * ( b ) )", + "BaseFormula": " 100 * serialization.c01_ms_scb / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": " ( cpu_clk_unhalted.core ) / cpu_clk_unhalted.ref_tsc", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE_P:sup", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " cpu_clk_unhalted.core_p:sup / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "BaseFormula": " cpu_clk_unhalted.ref_tsc / tsc", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b )", + "BaseFormula": " ( cpu_clk_unhalted.core_p ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "Threshold": { + "Formula": "metric_TMA_Info_System_MUX > 1.1 || metric_TMA_Info_System_MUX < 0.9" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_FLOPS_RETIRED.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a / ( ( durationtimeinmilliseconds / 1000 ) * 1000000000 )", + "BaseFormula": " fp_flops_retired.all / ( ( duration_time ) * 1000000000 )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" } ] } \ No newline at end of file diff --git a/GRR/metrics/perf/grandridge_metrics_perf.json b/GRR/metrics/perf/grandridge_metrics_perf.json index 0d6331a5..0e4b6768 100644 --- a/GRR/metrics/perf/grandridge_metrics_perf.json +++ b/GRR/metrics/perf/grandridge_metrics_perf.json @@ -56,14 +56,14 @@ "ScaleUnit": "1MB/s" }, { - "BriefDescription": "", + "BriefDescription": "Load operations retired per instruction", "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", "MetricGroup": "", "MetricName": "loads_retired_per_instr", "ScaleUnit": "1per_instr" }, { - "BriefDescription": "", + "BriefDescription": "Store operations retired per instruction", "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", "MetricGroup": "", "MetricName": "stores_retired_per_instr", @@ -166,5 +166,549 @@ "MetricGroup": "", "MetricName": "io_bandwidth_write", "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_frontend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots", + "MetricName": "tma_ifetch_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_icache_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB_MISS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_itlb_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_branch_detect", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_branch_resteer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots", + "MetricName": "tma_ifetch_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_cisc", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_decode", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_predecode", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_other_fb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_bad_speculation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots", + "MetricName": "tma_branch_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots", + "MetricName": "tma_machine_clears", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group;Slots", + "MetricName": "tma_nuke", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group;Slots", + "MetricName": "tma_fast_nuke", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_backend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group;Slots", + "MetricName": "tma_core_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group;Slots", + "MetricName": "tma_allocation_restriction", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation", + "MetricExpr": "( ( TOPDOWN_BE_BOUND.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) ) ) - tma_core_bound )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group;Slots", + "MetricName": "tma_resource_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_mem_scheduler", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_non_mem_scheduler", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_register", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_reorder_buffer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_serialization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that result in retirement slots", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_retiring", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "MetricExpr": "100 * LD_HEAD.ANY_AT_RET / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Mem_Exec;Cycles", + "MetricName": "tma_info_bottleneck_mem_exec_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.ALL / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Load_Store_Miss;Cycles", + "MetricName": "tma_info_bottleneck_load_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss", + "MetricExpr": "100 * ( LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET ) / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Cycles", + "MetricName": "tma_info_bottleneck_dtlb_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.ALL / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Ifetch;Cycles", + "MetricName": "tma_info_bottleneck_ifetch_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_core_ipc" + }, + { + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "( CPU_CLK_UNHALTED.CORE ) / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_core_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_core_upi" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Flops", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipcall" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipfarbranch" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / ( BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN )", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired return Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_indirect" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation", + "MetricExpr": "INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction", + "MetricExpr": "INST_RETIRED.ANY / ( FP_INST_RETIRED.128B_DP + FP_INST_RETIRED.128B_SP )", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_avx128" + }, + { + "BriefDescription": "Percentage of all uops which are microcode ops", + "MetricExpr": "100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_microcode_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_idiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_x87_uop_ratio" + }, + { + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_ipstore" + }, + { + "BriefDescription": "Ratio of mem load uops to all uops", + "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_memload_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_load_splits_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads that perform one or more locks", + "MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_load_locks_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_blocks_loads_with_storefwdblk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with an address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_blocks_loads_with_adressaliasing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss", + "MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_stlbhit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk", + "MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_pagewalk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match", + "MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_storefwding", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_otherpipelineblks", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss", + "MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_l1miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full", + "MetricExpr": "100 * ( MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL ) * ( TOPDOWN_BE_BOUND.MEM_SCHEDULER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) ) )", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_store_bound" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement", + "MetricExpr": "100 * ( LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_LOAD.ALL ) / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_load_bound" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block", + "MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_l1_bound" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STALLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l2hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STALLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l3hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / ( MEM_BOUND_STALLS_IFETCH.ALL )", + "MetricGroup": "", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / ( MEM_BOUND_STALLS_IFETCH.ALL )", + "MetricGroup": "", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_ratio" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricGroup": "", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio" + }, + { + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists", + "MetricExpr": "1000 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assist_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults", + "MetricExpr": "1000 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fault_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code", + "MetricExpr": "1000 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_buffer_stalls_store_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_buffer_stalls_load_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_buffer_stalls_mem_rsv_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction ", + "MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "", + "MetricName": "tma_info_serialization_tpause_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.CORE ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.CORE_P:k / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "( CPU_CLK_UNHALTED.CORE_P ) / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / ( ( duration_time ) * 1000000000 )", + "MetricGroup": "Flops", + "MetricName": "tma_info_system_gflops" } ] \ No newline at end of file diff --git a/SRF/metrics/perf/sierraforest_metrics_perf.json b/SRF/metrics/perf/sierraforest_metrics_perf.json index db621769..b120bdf7 100644 --- a/SRF/metrics/perf/sierraforest_metrics_perf.json +++ b/SRF/metrics/perf/sierraforest_metrics_perf.json @@ -77,14 +77,14 @@ "ScaleUnit": "1MB/s" }, { - "BriefDescription": "", + "BriefDescription": "Load operations retired per instruction", "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", "MetricGroup": "", "MetricName": "loads_retired_per_instr", "ScaleUnit": "1per_instr" }, { - "BriefDescription": "", + "BriefDescription": "Store operations retired per instruction", "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", "MetricGroup": "", "MetricName": "stores_retired_per_instr", @@ -188,6 +188,34 @@ "MetricName": "io_bandwidth_write", "ScaleUnit": "1MB/s" }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read_remote", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write_remote", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time", @@ -215,5 +243,563 @@ "MetricGroup": "", "MetricName": "llc_miss_remote_memory_bandwidth_write", "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traffic contoller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "iio_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "iio_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_frontend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots", + "MetricName": "tma_ifetch_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_icache_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB_MISS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_itlb_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_branch_detect", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group;Slots", + "MetricName": "tma_branch_resteer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group;Slots", + "MetricName": "tma_ifetch_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_cisc", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_decode", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_predecode", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group;Slots", + "MetricName": "tma_other_fb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_bad_speculation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots", + "MetricName": "tma_branch_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group;Slots", + "MetricName": "tma_machine_clears", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group;Slots", + "MetricName": "tma_nuke", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group;Slots", + "MetricName": "tma_fast_nuke", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_backend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group;Slots", + "MetricName": "tma_core_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group;Slots", + "MetricName": "tma_allocation_restriction", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation", + "MetricExpr": "( ( TOPDOWN_BE_BOUND.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) ) ) - tma_core_bound )", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group;Slots", + "MetricName": "tma_resource_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_mem_scheduler", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_non_mem_scheduler", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_register", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_reorder_buffer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group;Slots", + "MetricName": "tma_serialization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that result in retirement slots", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "TopdownL1;tma_L1_group;Slots", + "MetricName": "tma_retiring", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "MetricExpr": "100 * LD_HEAD.ANY_AT_RET / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Mem_Exec;Cycles", + "MetricName": "tma_info_bottleneck_mem_exec_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.ALL / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Load_Store_Miss;Cycles", + "MetricName": "tma_info_bottleneck_load_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss", + "MetricExpr": "100 * ( LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET ) / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Cycles", + "MetricName": "tma_info_bottleneck_dtlb_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.ALL / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Ifetch;Cycles", + "MetricName": "tma_info_bottleneck_ifetch_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_core_ipc" + }, + { + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "( CPU_CLK_UNHALTED.CORE ) / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_core_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_core_upi" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "Flops", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipcall" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipfarbranch" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / ( BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN )", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired return Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "", + "MetricName": "tma_info_br_inst_mix_ipmisp_indirect" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation", + "MetricExpr": "INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction", + "MetricExpr": "INST_RETIRED.ANY / ( FP_INST_RETIRED.128B_DP + FP_INST_RETIRED.128B_SP )", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_avx128" + }, + { + "BriefDescription": "Percentage of all uops which are microcode ops", + "MetricExpr": "100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_microcode_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_idiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_uop_mix_x87_uop_ratio" + }, + { + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_ipstore" + }, + { + "BriefDescription": "Ratio of mem load uops to all uops", + "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING.ALL_P", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_memload_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_load_splits_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads that perform one or more locks", + "MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_mix_load_locks_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_blocks_loads_with_storefwdblk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with an address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_blocks_loads_with_adressaliasing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss", + "MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_stlbhit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk", + "MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_pagewalk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match", + "MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_storefwding", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_otherpipelineblks", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss", + "MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricGroup": "", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_l1miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full", + "MetricExpr": "100 * ( MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL ) * ( TOPDOWN_BE_BOUND.MEM_SCHEDULER / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) ) )", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_store_bound" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement", + "MetricExpr": "100 * ( LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_LOAD.ALL ) / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_load_bound" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block", + "MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_l1_bound" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STALLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l2hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STALLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l3hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / ( MEM_BOUND_STALLS_IFETCH.ALL )", + "MetricGroup": "", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / ( MEM_BOUND_STALLS_IFETCH.ALL )", + "MetricGroup": "", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_ratio" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricGroup": "", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio" + }, + { + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists", + "MetricExpr": "1000 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assist_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults", + "MetricExpr": "1000 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fault_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code", + "MetricExpr": "1000 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_buffer_stalls_store_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_buffer_stalls_load_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_buffer_stalls_mem_rsv_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction ", + "MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / ( ( 6 ) * ( CPU_CLK_UNHALTED.CORE ) )", + "MetricGroup": "", + "MetricName": "tma_info_serialization_tpause_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.CORE ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.CORE_P:k / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "( CPU_CLK_UNHALTED.CORE_P ) / ( CPU_CLK_UNHALTED.CORE )", + "MetricGroup": "", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / ( ( duration_time ) * 1000000000 )", + "MetricGroup": "Flops", + "MetricName": "tma_info_system_gflops" } ] \ No newline at end of file diff --git a/SRF/metrics/sierraforest_metrics.json b/SRF/metrics/sierraforest_metrics.json index e0d91a9f..d4cbdfdb 100644 --- a/SRF/metrics/sierraforest_metrics.json +++ b/SRF/metrics/sierraforest_metrics.json @@ -1,10 +1,12 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor Scalable Family0", - "DatePublished": "02/12/2024", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with E-cores0", + "DatePublished": "05/21/2024", "Version": "0", - "Legend": "" + "Legend": "", + "TmaVersion": "3.6", + "TmaFlavor": "Public" }, "Metrics": [ { @@ -31,9 +33,7 @@ ], "Formula": "(a / b * c) / 1000000000", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "uncore_frequency", @@ -59,9 +59,7 @@ ], "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "cpu_utilization", @@ -82,9 +80,7 @@ "Constants": [], "Formula": "100 * a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "cpi", @@ -105,9 +101,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l2_mpi", @@ -128,9 +122,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "numa_reads_addressed_to_local_dram", @@ -159,9 +151,7 @@ "Constants": [], "Formula": "100 * (a + b) / (a + b + c + d)", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "numa_reads_addressed_to_remote_dram", @@ -190,9 +180,7 @@ "Constants": [], "Formula": "100 * (c + d) / (a + b + c + d)", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "memory_bandwidth_read", @@ -213,9 +201,7 @@ "Constants": [], "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM" }, { "MetricName": "memory_bandwidth_write", @@ -236,9 +222,7 @@ "Constants": [], "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM" }, { "MetricName": "memory_bandwidth_total", @@ -267,9 +251,7 @@ "Constants": [], "Formula": "((a + b + c + d) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM" }, { "MetricName": "upi_data_transmit_bw", @@ -286,15 +268,13 @@ "Constants": [], "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "UPI, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "UPI, SOCKET, SYSTEM" }, { "MetricName": "loads_retired_per_instr", "LegacyName": "metric_loads retired per instr", "Level": 1, - "BriefDescription": "", + "BriefDescription": "Load operations retired per instruction", "UnitOfMeasure": "per instruction", "Events": [ { @@ -309,15 +289,13 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "stores_retired_per_instr", "LegacyName": "metric_stores retired per instr", "Level": 1, - "BriefDescription": "", + "BriefDescription": "Store operations retired per instruction", "UnitOfMeasure": "per instruction", "Events": [ { @@ -332,9 +310,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l1d_demand_data_read_hits_per_instr", @@ -355,9 +331,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", @@ -378,9 +352,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l2_demand_data_read_hits_per_instr", @@ -401,9 +373,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "l2_demand_data_read_mpi", @@ -424,9 +394,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "llc_data_read_mpi_demand_plus_prefetch", @@ -455,9 +423,7 @@ "Constants": [], "Formula": "(a + b + c) / d", "Category": "", - "Threshold": "", - "ResolutionLevels": "SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "SOCKET, SYSTEM" }, { "MetricName": "llc_code_read_mpi_demand_plus_prefetch", @@ -482,9 +448,7 @@ "Constants": [], "Formula": "(a + b) / d", "Category": "", - "Threshold": "", - "ResolutionLevels": "SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "SOCKET, SYSTEM" }, { "MetricName": "llc_demand_data_read_miss_latency", @@ -518,9 +482,7 @@ ], "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "itlb_2nd_level_mpi", @@ -541,9 +503,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "itlb_2nd_level_large_page_mpi", @@ -564,9 +524,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "dtlb_2nd_level_load_mpi", @@ -587,9 +545,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", @@ -610,9 +566,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "dtlb_2nd_level_store_mpi", @@ -633,9 +587,7 @@ "Constants": [], "Formula": "a / b", "Category": "", - "Threshold": "", - "ResolutionLevels": "CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CORE, SOCKET, SYSTEM" }, { "MetricName": "io_bandwidth_read", @@ -652,9 +604,7 @@ "Constants": [], "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "io_bandwidth_write", @@ -675,9 +625,83 @@ "Constants": [], "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "llc_miss_local_memory_bandwidth_read", @@ -694,9 +718,7 @@ "Constants": [], "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "llc_miss_local_memory_bandwidth_write", @@ -713,9 +735,7 @@ "Constants": [], "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "llc_miss_remote_memory_bandwidth_read", @@ -732,9 +752,7 @@ "Constants": [], "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" + "ResolutionLevels": "CHA, SOCKET, SYSTEM" }, { "MetricName": "llc_miss_remote_memory_bandwidth_write", @@ -751,9 +769,2166 @@ "Constants": [], "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "ResolutionLevels": "CHA, SOCKET, SYSTEM" + }, + { + "MetricName": "iio_bandwidth_read", + "LegacyName": "metric_IIO_bandwidth_read (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic contoller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM" + }, + { + "MetricName": "iio_bandwidth_write", + "LegacyName": "metric_IIO_bandwidth_write (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "IFetch_Latency", + "LegacyName": "metric_TMA_..IFetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.frontend_latency / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ICACHE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.icache / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....ICache_Misses(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ITLB_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.itlb_miss / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....ITLB_Misses(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Detect", + "LegacyName": "metric_TMA_....Branch_Detect(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.branch_detect / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Branch_Detect(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Resteer", + "LegacyName": "metric_TMA_....Branch_Resteer(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.branch_resteer / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Branch_Resteer(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "IFetch_Bandwidth", + "LegacyName": "metric_TMA_..IFetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.frontend_bandwidth / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Cisc", + "LegacyName": "metric_TMA_....Cisc(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.CISC", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.cisc / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Cisc(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Decode", + "LegacyName": "metric_TMA_....Decode(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.DECODE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.decode / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Decode(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" + }, + { + "MetricName": "Predecode", + "LegacyName": "metric_TMA_....Predecode(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.PREDECODE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.predecode / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Predecode(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Other_FB", + "LegacyName": "metric_TMA_....Other_FB(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.OTHER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.other / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Other_FB(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.mispredict / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Branch_Mispredicts(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.machine_clears / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Nuke", + "LegacyName": "metric_TMA_....Nuke(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.NUKE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.nuke / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Nuke(%) >0.05 && metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Fast_Nuke", + "LegacyName": "metric_TMA_....Fast_Nuke(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.fastnuke / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Fast_Nuke(%) >0.05 && metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.alloc_restrictions / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Core_Bound(%) >0.10 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Allocation_Restriction", + "LegacyName": "metric_TMA_....Allocation_Restriction(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.alloc_restrictions / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Allocation_Restriction(%) >0.10 && metric_TMA_..Core_Bound(%) >0.10 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Resource_Bound", + "LegacyName": "metric_TMA_..Resource_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + }, + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( ( 6 ) * ( b ) ) ) - ( c / ( ( 6 ) * ( b ) ) ) ) )", + "BaseFormula": " ( ( topdown_be_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) ) ) - tma_core_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Mem_Scheduler", + "LegacyName": "metric_TMA_....Mem_Scheduler(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Mem_Scheduler(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Non_Mem_Scheduler", + "LegacyName": "metric_TMA_....Non_Mem_Scheduler(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.non_mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Non_Mem_Scheduler(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Register", + "LegacyName": "metric_TMA_....Register(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.REGISTER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.register / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Register(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Reorder_Buffer", + "LegacyName": "metric_TMA_....Reorder_Buffer(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.reorder_buffer / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Reorder_Buffer(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Serialization", + "LegacyName": "metric_TMA_....Serialization(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.SERIALIZATION", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.serialization / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Serialization(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "Counts the number of issue slots that result in retirement slots", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_retiring.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Retiring(%) >0.75" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_Mem_Exec_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_Mem_Exec_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * ld_head.any_at_ret / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem_Exec" + }, + { + "MetricName": "Info_Bottleneck_Load_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_Load_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_load.all / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Load_Store_Miss" + }, + { + "MetricName": "Info_Bottleneck_DTLB_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_DTLB_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.DTLB_MISS_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.PGWALK_AT_RET", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a + b ) / ( c )", + "BaseFormula": " 100 * ( ld_head.dtlb_miss_at_ret + ld_head.pgwalk_at_ret ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_IFetch_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_IFetch_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.all / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Ifetch" + }, + { + "MetricName": "Info_Core_IPC", + "LegacyName": "metric_TMA_Info_Core_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " inst_retired.any / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": 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SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_FLOPS_RETIRED.ALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " fp_flops_retired.all / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + 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to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_inst_retired.far_branch:user", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpMispredict", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMispredict", + "Level": 1, + "BriefDescription": "Instructions per retired Branch Misprediction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.all_branches", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND", + "Alias": "b" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b - c )", + "BaseFormula": " inst_retired.any / ( br_misp_retired.cond - br_misp_retired.cond_taken )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Inst_Mix_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired conditional Branch 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+ "MetricName": "Info_Br_Inst_Mix_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Br_Inst_Mix_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.indirect", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Arith_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Arith_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_FLOPS_RETIRED.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / fp_flops_retired.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + }, + { + "MetricName": "Info_Arith_Inst_Mix_IpFPArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Arith_Inst_Mix_IpFPArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_INST_RETIRED.32B_SP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / fp_inst_retired.32b_sp", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + }, + { + "MetricName": "Info_Arith_Inst_Mix_IpFPArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Arith_Inst_Mix_IpFPArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_INST_RETIRED.64B_DP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / fp_inst_retired.64b_dp", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + }, + { + "MetricName": "Info_Arith_Inst_Mix_IpFPArith_AVX128", + "LegacyName": "metric_TMA_Info_Arith_Inst_Mix_IpFPArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_INST_RETIRED.128B_DP", + "Alias": "b" + }, + { + "Name": "FP_INST_RETIRED.128B_SP", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": " inst_retired.any / ( fp_inst_retired.128b_dp + fp_inst_retired.128b_sp )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + }, + { + "MetricName": "Info_Uop_Mix_Microcode_Uop_Ratio", + "LegacyName": "metric_TMA_Info_Uop_Mix_Microcode_Uop_Ratio", + "Level": 1, + "BriefDescription": "Percentage of all uops which are microcode ops", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * uops_retired.ms / topdown_retiring.all_p", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Uop_Mix_FPDiv_Uop_Ratio", + "LegacyName": "metric_TMA_Info_Uop_Mix_FPDiv_Uop_Ratio", + "Level": 1, + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.FPDIV", + "Alias": "a" + }, + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * uops_retired.fpdiv / topdown_retiring.all_p", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Uop_Mix_IDiv_Uop_Ratio", + "LegacyName": "metric_TMA_Info_Uop_Mix_IDiv_Uop_Ratio", + "Level": 1, + "BriefDescription": "Percentage of all uops which are IDiv uops", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.IDIV", + "Alias": "a" + }, + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * uops_retired.idiv / topdown_retiring.all_p", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Uop_Mix_X87_Uop_Ratio", + "LegacyName": "metric_TMA_Info_Uop_Mix_X87_Uop_Ratio", + "Level": 1, + "BriefDescription": "Percentage of all uops which are x87 uops", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.X87", + "Alias": "a" + }, + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * uops_retired.x87 / topdown_retiring.all_p", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Mem_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / mem_uops_retired.all_loads", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Mem_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / mem_uops_retired.all_stores", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Mix_MemLoad_Ratio", + "LegacyName": "metric_TMA_Info_Mem_Mix_MemLoad_Ratio", + "Level": 1, + "BriefDescription": "Ratio of mem load uops to all uops", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * mem_uops_retired.all_loads / topdown_retiring.all_p", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Mix_Load_Splits_Ratio", + "LegacyName": "metric_TMA_Info_Mem_Mix_Load_Splits_Ratio", + "Level": 1, + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_uops_retired.split_loads / mem_uops_retired.all_loads", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Mix_Load_Locks_Ratio", + "LegacyName": "metric_TMA_Info_Mem_Mix_Load_Locks_Ratio", + "Level": 1, + "BriefDescription": "Percentage of total non-speculative loads that perform one or more locks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_uops_retired.lock_loads / mem_uops_retired.all_loads", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Blocks_Loads_with_StoreFwdBlk", + "LegacyName": "metric_TMA_Info_Mem_Exec_Blocks_%_Loads_with_StoreFwdBlk", + "Level": 1, + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.DATA_UNKNOWN", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_blocks.data_unknown / mem_uops_retired.all_loads", + "Category": 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second level TLB miss", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.DTLB_MISS_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.dtlb_miss_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_Pagewalk", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_Pagewalk", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.PGWALK_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.pgwalk_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_StoreFwding", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_StoreFwding", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.ST_ADDR_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.st_addr_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_OtherPipelineBlks", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_OtherPipelineBlks", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.OTHER_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.other_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_L1miss", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_L1miss", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.L1_MISS_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.l1_miss_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Load_Store_Bound_Store_Bound", + "LegacyName": "metric_TMA_Info_Load_Store_Bound_Store_Bound", + "Level": 1, + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.ST_BUF", + "Alias": "a" + }, + { + "Name": "MEM_SCHEDULER_BLOCK.ALL", + "Alias": "b" + }, + { + "Name": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / b ) * ( c / ( ( 6 ) * ( d ) ) )", + "BaseFormula": " 100 * ( mem_scheduler_block.st_buf / mem_scheduler_block.all ) * ( topdown_be_bound.mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) ) )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Store_Bound_Load_Bound", + "LegacyName": "metric_TMA_Info_Load_Store_Bound_Load_Bound", + "Level": 1, + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LD_HEAD.L1_BOUND_AT_RET", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a + b ) / ( c )", + "BaseFormula": " 100 * ( ld_head.l1_bound_at_ret + mem_bound_stalls_load.all ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Store_Bound_L1_Bound", + "LegacyName": "metric_TMA_Info_Load_Store_Bound_L1_Bound", + "Level": 1, + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LD_HEAD.L1_BOUND_AT_RET", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * ld_head.l1_bound_at_ret / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Miss_Bound_LoadMissBound_with_L2Hit", + "LegacyName": "metric_TMA_Info_Load_Miss_Bound_%_LoadMissBound_with_L2Hit", + "Level": 1, + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_bound_stalls_load.l2_hit / mem_bound_stalls_load.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Miss_Bound_LoadMissBound_with_L3Hit", + "LegacyName": "metric_TMA_Info_Load_Miss_Bound_%_LoadMissBound_with_L3Hit", + "Level": 1, + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.LLC_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_bound_stalls_load.llc_hit / mem_bound_stalls_load.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Ifetch_Miss_Bound_IfetchMissBound_with_L2Hit", + "LegacyName": "metric_TMA_Info_Ifetch_Miss_Bound_%_IfetchMissBound_with_L2Hit", + "Level": 1, + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.l2_hit / ( mem_bound_stalls_ifetch.all )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Ifetch_Miss_Bound_IfetchMissBound_with_L3Hit", + "LegacyName": "metric_TMA_Info_Ifetch_Miss_Bound_%_IfetchMissBound_with_L3Hit", + "Level": 1, + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.llc_hit / ( mem_bound_stalls_ifetch.all )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Mispredict_Bound_Branch_Mispredict_Ratio", + "LegacyName": "metric_TMA_Info_Br_Mispredict_Bound_Branch_Mispredict_Ratio", + "Level": 1, + "BriefDescription": "Ratio of all branches which mispredict", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_misp_retired.all_branches / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Mispredict_Bound_Branch_Mispredict_to_Unknown_Branch_Ratio", + "LegacyName": "metric_TMA_Info_Br_Mispredict_Bound_Branch_Mispredict_to_Unknown_Branch_Ratio", + "Level": 1, + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_misp_retired.all_branches / baclears.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_FP_Assist_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_FP_Assist_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.FP_ASSIST", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.fp_assist / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_Page_Fault_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_Page_Fault_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.page_fault / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_SMC_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_SMC_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.SMC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.smc / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Store_Buffer_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Store_Buffer_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.ST_BUF", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.st_buf / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Load_Buffer_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Load_Buffer_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.LD_BUF", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.ld_buf / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Mem_RSV_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Mem_RSV_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.RSV", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.rsv / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Serialization_Tpause_Cycles", + "LegacyName": "metric_TMA_Info_Serialization _%_Tpause_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "SERIALIZATION.C01_MS_SCB", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( ( 6 ) * ( b ) )", + "BaseFormula": " 100 * serialization.c01_ms_scb / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": " ( cpu_clk_unhalted.core ) / cpu_clk_unhalted.ref_tsc", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE_P:sup", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " cpu_clk_unhalted.core_p:sup / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "BaseFormula": " cpu_clk_unhalted.ref_tsc / tsc", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b )", + "BaseFormula": " ( cpu_clk_unhalted.core_p ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "Threshold": { + "Formula": "metric_TMA_Info_System_MUX > 1.1 || metric_TMA_Info_System_MUX < 0.9" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_FLOPS_RETIRED.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a / ( ( durationtimeinmilliseconds / 1000 ) * 1000000000 )", + "BaseFormula": " fp_flops_retired.all / ( ( duration_time ) * 1000000000 )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" } ] } \ No newline at end of file From f7fe30147fe8ca5e1f6e3349ddc86543900ac5fa Mon Sep 17 00:00:00 2001 From: clbigger Date: Wed, 22 May 2024 14:40:45 -0700 Subject: [PATCH 2/2] Fix for missing event translation --- GRR/metrics/perf/grandridge_metrics_perf.json | 2 +- SRF/metrics/perf/sierraforest_metrics_perf.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/GRR/metrics/perf/grandridge_metrics_perf.json b/GRR/metrics/perf/grandridge_metrics_perf.json index 0e4b6768..6f83e41a 100644 --- a/GRR/metrics/perf/grandridge_metrics_perf.json +++ b/GRR/metrics/perf/grandridge_metrics_perf.json @@ -416,7 +416,7 @@ }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "", "MetricName": "tma_info_br_inst_mix_ipfarbranch" }, diff --git a/SRF/metrics/perf/sierraforest_metrics_perf.json b/SRF/metrics/perf/sierraforest_metrics_perf.json index b120bdf7..c521adc1 100644 --- a/SRF/metrics/perf/sierraforest_metrics_perf.json +++ b/SRF/metrics/perf/sierraforest_metrics_perf.json @@ -507,7 +507,7 @@ }, { "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "", "MetricName": "tma_info_br_inst_mix_ipfarbranch" },