diff --git a/BDX/metrics/broadwellx_metrics.json b/BDX/metrics/broadwellx_metrics.json index 39f7ef4d..04821502 100644 --- a/BDX/metrics/broadwellx_metrics.json +++ b/BDX/metrics/broadwellx_metrics.json @@ -1,10 +1,12 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor E5 v4 Family Based on the Broadwell Microarchitecture - V", - "DatePublished": "05/12/2023", - "Version": "", - "Legend": "" + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor E5 v4 Family Based on the Broadwell Microarchitecture0", + "DatePublished": "01/17/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" }, "Metrics": [ { @@ -850,20 +852,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1;PGO" }, { @@ -887,20 +880,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Frontend;TmaL2" }, { @@ -924,8 +908,8 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;IcMiss" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;IcMiss" }, { "MetricName": "ITLB_Misses", @@ -953,11 +937,11 @@ } ], "Constants": [], - "Formula": "100 * ( ( 14 * a + b + 7 * c ) / ( d ) )", + "Formula": "100 * ( ( ( 14 * a + b + 7 * c ) ) / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" }, { "MetricName": "Branch_Resteers", @@ -988,7 +972,7 @@ "Formula": "100 * ( ( 12 ) * ( a + b + c ) / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { @@ -1020,7 +1004,7 @@ "Formula": "100 * ( a * ( ( 12 ) * ( a + b + c ) / ( d ) ) / ( a + b + c ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueBM", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts" }, { @@ -1052,7 +1036,7 @@ "Formula": "100 * ( a * ( ( 12 ) * ( b + a + c ) / ( d ) ) / ( b + a + c ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears" }, { @@ -1060,7 +1044,7 @@ "LegacyName": "metric_TMA_......Unknown_Branches(%)", "ParentCategory": "Branch_Resteers", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "UnitOfMeasure": "percent", "Events": [ { @@ -1084,19 +1068,19 @@ "Formula": "100 * ( ( ( 12 ) * ( a + b + c ) / ( d ) ) - ( a * ( ( 12 ) * ( a + b + c ) / ( d ) ) / ( a + b + c ) ) - ( b * ( ( 12 ) * ( a + b + c ) / ( d ) ) / ( a + b + c ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat" }, { - "MetricName": "DSB_Switches", - "LegacyName": "metric_TMA_....DSB_Switches(%)", + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Name": "IDQ.MS_SWITCHES", "Alias": "a" }, { @@ -1105,18 +1089,18 @@ } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DSBmiss;FetchLat" + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq" }, { "MetricName": "LCP", "LegacyName": "metric_TMA_....LCP(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "UnitOfMeasure": "percent", "Events": [ { @@ -1132,19 +1116,19 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { - "MetricName": "MS_Switches", - "LegacyName": "metric_TMA_....MS_Switches(%)", + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.MS_SWITCHES", + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "Alias": "a" }, { @@ -1153,11 +1137,11 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "FetchLat;MicroSeq" + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat" }, { "MetricName": "Fetch_Bandwidth", @@ -1184,20 +1168,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( 4 ) * d / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( 4 ) * d / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P & #HighIPC; $issueFB", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "Threshold": "> 20; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2" }, { @@ -1225,20 +1200,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, { @@ -1266,20 +1232,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSB;FetchBW" }, { @@ -1314,20 +1271,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1371,20 +1319,11 @@ "Alias": "h" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( g / 2 ) if smt_on else ( h ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( g / 2 ) if ( 1 ) else ( h ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueBM", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts;TmaL2" }, { @@ -1428,20 +1367,11 @@ "Alias": "h" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueMC; $issueSyncxn", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears;TmaL2" }, { @@ -1480,20 +1410,11 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if smt_on else g ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 20", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1569,20 +1490,11 @@ "Alias": "p" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a + b ) / ( ( c + d - ( e if ( ( f / ( g ) ) > 1.8 ) else h ) - ( i if ( ( ( 4 ) * j / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( g ) ) ) ) > 0.1 ) else 0 ) + b ) ) ) * ( 1 - ( ( l / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( g ) ) ) ) + ( ( m - ( n ) + ( 4 ) * ( ( o / 2 ) if smt_on else p ) ) / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( g ) ) ) ) + ( ( n ) / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( g ) ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( ( c + d - ( e if ( ( f / ( g ) ) > 1.8 ) else h ) - ( i if ( ( ( 4 ) * j / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( g ) ) ) ) > 0.1 ) else 0 ) + b ) ) ) * ( 1 - ( ( l / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( g ) ) ) ) + ( ( m - ( n ) + ( 4 ) * ( ( o / 2 ) if ( 1 ) else p ) ) / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( g ) ) ) ) + ( ( n ) / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( g ) ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2" }, { @@ -1610,8 +1522,8 @@ "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueL1; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "DTLB_Load", @@ -1642,7 +1554,7 @@ "Formula": "100 * ( ( ( 8 ) * a + b + 7 * c ) / ( d ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1663,10 +1575,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1695,10 +1607,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / b ) * ( min( c , d ) ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / b ) * ( min( c , d ) ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueRFO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore" }, { @@ -1731,10 +1643,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1758,7 +1670,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1794,7 +1706,7 @@ "Formula": "100 * ( ( a / ( b + c ) ) * d / ( e ) )", "Category": "TMA", "Threshold": "> 30; $issueBW; $issueSL; $issueSmSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW" }, { @@ -1822,8 +1734,8 @@ "Formula": "100 * ( ( a - b ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "L3_Bound", @@ -1854,8 +1766,8 @@ "Formula": "100 * ( ( a / ( a + ( 7 ) * b ) ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "Contested_Accesses", @@ -1911,10 +1823,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 60 ) * ( a * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) + ( 43 ) * ( f * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 60 ) * ( a * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) + ( 43 ) * ( f * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -1971,10 +1883,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 43 ) * ( a * ( 1 + b / ( ( c + d + a + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 43 ) * ( a * ( 1 + b / ( ( c + d + a + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Snoop" }, { @@ -1982,7 +1894,7 @@ "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", "UnitOfMeasure": "percent", "Events": [ { @@ -2031,10 +1943,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 41 ) * ( a * ( 1 + b / ( ( c + a + d + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 41 ) * ( a * ( 1 + b / ( ( c + a + d + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat" }, { @@ -2058,20 +1970,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a / 2 ) if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a / 2 ) if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 30 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2100,10 +2003,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 1 - ( a / ( a + ( 7 ) * b ) ) ) * c / ( d ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 1 - ( a / ( a + ( 7 ) * b ) ) ) * c / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2111,7 +2014,7 @@ "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2127,7 +2030,7 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2135,7 +2038,7 @@ "LegacyName": "metric_TMA_......MEM_Latency(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2155,12 +2058,12 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { - "MetricName": "Local_DRAM", - "LegacyName": "metric_TMA_........Local_DRAM(%)", + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", @@ -2212,18 +2115,18 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + a + h + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + a + h + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server" }, { - "MetricName": "Remote_DRAM", - "LegacyName": "metric_TMA_........Remote_DRAM(%)", + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2272,10 +2175,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 310 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + a + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 310 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + a + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server;Snoop" }, { @@ -2283,7 +2186,7 @@ "LegacyName": "metric_TMA_........Remote_Cache(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2332,10 +2235,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) + ( 180 ) * ( j * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) + ( 180 ) * ( j * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Server;Snoop" }, { @@ -2359,7 +2262,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2392,10 +2295,10 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a * ( 9 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "Formula": "100 * ( min( ( ( ( a * ( 9 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { @@ -2420,10 +2323,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 200 ) * a + ( 60 ) * b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 200 ) * a + ( 60 ) * b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -2447,20 +2350,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 2 * a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( 2 * a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2489,10 +2383,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 8 ) * a + b + 7 * c ) / ( d ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 8 ) * a + b + 7 * c ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2568,20 +2462,11 @@ "Alias": "p" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if smt_on else g ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) - ( ( ( h + i ) / ( ( j + k - ( l if ( ( m / ( c ) ) > 1.8 ) else n ) - ( o if ( ( ( 4 ) * p / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) > 0.1 ) else 0 ) + i ) ) ) * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if smt_on else g ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) - ( ( ( h + i ) / ( ( j + k - ( l if ( ( m / ( c ) ) > 1.8 ) else n ) - ( o if ( ( ( 4 ) * p / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) > 0.1 ) else 0 ) + i ) ) ) * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2;Compute" }, { @@ -2605,20 +2490,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2674,20 +2550,11 @@ "Alias": "k" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a + b - ( c if ( ( d / ( e ) ) > 1.8 ) else f ) - ( g if ( ( ( 4 ) * h / ( ( 4 ) * ( ( i / 2 ) if smt_on else ( e ) ) ) ) > 0.1 ) else 0 ) + j ) ) - j - k ) / ( e ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a + b - ( c if ( ( d / ( e ) ) > 1.8 ) else f ) - ( g if ( ( ( 4 ) * h / ( ( 4 ) * ( ( i / 2 ) if ( 1 ) else ( e ) ) ) ) > 0.1 ) else 0 ) + j ) ) - j - k ) / ( e ) )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2723,20 +2590,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / 2 if smt_on else ( b - ( c if ( ( ( 4 ) * d / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( e / 2 ) if smt_on else ( f ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / 2 if ( 1 ) else ( b - ( c if ( ( ( 4 ) * d / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( e / 2 ) if ( 1 ) else ( f ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2772,20 +2630,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else ( c - d ) ) / ( ( e / 2 ) if smt_on else ( f ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else ( c - d ) ) / ( ( e / 2 ) if ( 1 ) else ( f ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueL1", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2821,20 +2670,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else ( c - d ) ) / ( ( e / 2 ) if smt_on else ( f ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else ( c - d ) ) / ( ( e / 2 ) if ( 1 ) else ( f ) ) )", "Category": "TMA", "Threshold": "> 15 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2862,20 +2702,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a / 2 ) if smt_on else b ) / ( ( c / 2 ) if smt_on else ( d ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a / 2 ) if ( 1 ) else b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) )", "Category": "TMA", - "Threshold": "> 70 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2911,20 +2742,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2948,20 +2770,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -2985,20 +2798,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3022,20 +2826,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3043,7 +2838,7 @@ "LegacyName": "metric_TMA_..........Port_6(%)", "ParentCategory": "ALU_Op_Utilization", "Level": 6, - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "UnitOfMeasure": "percent", "Events": [ { @@ -3059,20 +2854,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3108,20 +2894,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3145,20 +2922,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3182,20 +2950,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3219,20 +2978,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3256,20 +3006,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3293,20 +3034,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3329,20 +3061,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "(> 70 | Heavy_Operations)", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -3350,7 +3073,7 @@ "LegacyName": "metric_TMA_..Light_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3374,20 +3097,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( ( a ) / d ) * e / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( ( a ) / d ) * e / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -3420,10 +3134,10 @@ } ], "Constants": [], - "Formula": "100 * ( ( a * ( ( b ) / c ) / ( b ) ) + ( ( d ) / ( b ) ) + ( min( ( ( e ) / ( b ) ) , ( 1 ) ) ) )", + "Formula": "100 * ( ( a * ( ( b ) / c ) / ( b ) ) + ( ( d ) / ( b ) ) + ( min( ( ( e ) / ( b ) ) , ( 1.0 ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "HPC" }, { @@ -3451,7 +3165,7 @@ "Formula": "100 * ( a * ( ( b ) / c ) / ( b ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -3475,7 +3189,7 @@ "Formula": "100 * ( ( a ) / ( b ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3496,10 +3210,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a ) / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3524,10 +3238,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3552,10 +3266,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3563,7 +3277,7 @@ "LegacyName": "metric_TMA_..Heavy_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3587,20 +3301,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) )", "Category": "TMA", "Threshold": "> 10", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -3632,20 +3337,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC; $issueMS", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MicroSeq" }, { @@ -3669,20 +3365,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( min( ( ( 100 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) , ( 1 ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( ( 66 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3718,86 +3405,175 @@ "Alias": "f" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( min( ( ( 66 ) * f / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) , ( 1.0 ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "INST_RETIRED.ANY", + "Alias": "a" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" } ], - "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) - ( min( ( ( 100 ) * f / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) , ( 1 ) ) ) ) )", + "Constants": [], + "Formula": "a / ( b )", "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" }, { - "MetricName": "Info_Core_CoreIPC", - "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", "Level": 1, - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "BriefDescription": "Uops Per Instruction", "UnitOfMeasure": "", "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, { "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Name": "BR_INST_RETIRED.NEAR_TAKEN", "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" }, { "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "c" + "Alias": "b" } ], - "Constants": [ + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" } ], - "Formula": "a / ( ( b / 2 ) if smt_on else ( c ) )", + "Constants": [], + "Formula": "( 4 ) * ( ( a / 2 ) if ( 1 ) else ( b ) )", "Category": "TMA", "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Ret;SMT;TmaL1" + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" }, { - "MetricName": "Info_Inst_Mix_IpTB", - "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", "Level": 1, - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UOPS_EXECUTED.THREAD", "Alias": "a" }, { - "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" } ], "Constants": [], "Formula": "a / b", "Category": "TMA", - "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" }, { - "MetricName": "Info_Bad_Spec_IpMispredict", - "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", "Level": 1, - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "UnitOfMeasure": "", "Events": [ { @@ -3805,39 +3581,1496 @@ "Alias": "a" }, { - "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "a / b", + "Formula": "a / ( ( b / 2 ) if ( 1 ) else ( c ) )", "Category": "TMA", - "Threshold": "< 200", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Bad;BadSpec;BrMispredicts" + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" }, { - "MetricName": "Info_Memory_L2MPKI", - "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", "Level": 1, - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "BriefDescription": "Floating Point Operations Per Cycle", "UnitOfMeasure": "", "Events": [ { - "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Name": "FP_ARITH_INST_RETIRED.SCALAR", "Alias": "a" }, { - "Name": "INST_RETIRED.ANY", + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" } ], "Constants": [], - "Formula": "1000 * a / b", + "Formula": "( a + 2 * b + 4 * c + 8 * d ) / ( ( e / 2 ) if ( 1 ) else ( f ) )", "Category": "TMA", "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Mem;Backend;CacheMisses" + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0x3c", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( ( a ) + ( b ) ) / ( 2 * ( ( c / 2 ) if ( 1 ) else ( d ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a / 2 ) if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( b + 2 * c + 4 * d + 8 * e )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0x3c", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b ) + ( c ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE:c1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "LSD.UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "c" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( ( a + b + c + d ) )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "BR_MISP_EXEC.INDIRECT", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a ) / ( ( ( b ) / c ) * d )", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_DURATION", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_DURATION", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_DURATION", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "e" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "( a + b + c + 7 * ( d + e + f ) ) / ( 2 * ( ( g / 2 ) if ( 1 ) else ( h ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 8 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a + 2 * b + 4 * c + 8 * d ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / ( b / 2 ) if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182", + "Alias": "a" + }, + { + "Name": "UNC_C_TOR_INSERTS.MISS_OPCODE:opc=0x182", + "Alias": "b" + }, + { + "Name": "UNC_C_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182", + "Alias": "a" + }, + { + "Name": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM, CBOX", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" } ] } \ No newline at end of file diff --git a/BDX/metrics/perf/broadwellx_metrics_perf.json b/BDX/metrics/perf/broadwellx_metrics_perf.json index 2c0599f1..9565a539 100644 --- a/BDX/metrics/perf/broadwellx_metrics_perf.json +++ b/BDX/metrics/perf/broadwellx_metrics_perf.json @@ -239,14 +239,14 @@ }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "MetricExpr": "( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "ScaleUnit": "100%" @@ -254,14 +254,14 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", "MetricExpr": "( ICACHE.IFDATA_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "( ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ITLB_MISSES.WALK_COMPLETED ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricExpr": "( ( ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ITLB_MISSES.WALK_COMPLETED ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%" }, @@ -287,85 +287,85 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "MetricExpr": "( ( ( 12 ) * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( BR_MISP_RETIRED.ALL_BRANCHES * ( ( 12 ) * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) ) - ( MACHINE_CLEARS.COUNT * ( ( 12 ) * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) ) )", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "MetricExpr": "( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_mite", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "MetricExpr": "( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_dsb", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "MetricExpr": "( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "ScaleUnit": "100%" @@ -373,7 +373,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", "MetricExpr": "( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "ScaleUnit": "100%" }, @@ -386,21 +386,21 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "MetricExpr": "( min( ( ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_lock_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "ScaleUnit": "100%" @@ -422,61 +422,61 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", "MetricExpr": "( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", "MetricExpr": "( ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) * CYCLE_ACTIVITY.STALLS_L2_MISS / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "MetricExpr": "( min( ( ( ( 60 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 60 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "MetricExpr": "( min( ( ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_data_sharing", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "MetricExpr": "( min( ( ( 41 ) * ( MEM_LOAD_UOPS_RETIRED.L3_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( 41 ) * ( MEM_LOAD_UOPS_RETIRED.L3_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", - "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_sq_full", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "MetricExpr": "( min( ( ( 1 - ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) * CYCLE_ACTIVITY.STALLS_L2_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 1 - ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) * CYCLE_ACTIVITY.STALLS_L2_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_latency", @@ -484,21 +484,21 @@ }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "MetricExpr": "( min( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", + "MetricName": "tma_local_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( 310 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( 310 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", + "MetricName": "tma_remote_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 180 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 180 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_remote_cache", "ScaleUnit": "100%" @@ -512,175 +512,175 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "MetricExpr": "( ( ( L2_RQSTS.RFO_HIT * ( 9 ) * ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( min( ( ( ( L2_RQSTS.RFO_HIT * ( 9 ) * ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "MetricExpr": "( min( ( ( ( 200 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + ( 60 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 200 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + ( 60 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_false_sharing", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", - "MetricExpr": "( 2 * MEM_UOPS_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( 2 * MEM_UOPS_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_split_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", - "MetricExpr": "( min( ( ( ( 8 ) * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 8 ) * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "MetricExpr": "( ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricExpr": "( ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", - "MetricExpr": "( ARITH.FPU_DIV_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ARITH.FPU_DIV_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "MetricExpr": "( ( ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( ( ( ( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - ( UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_ports_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ ) / 2 if #SMT_on else ( CYCLE_ACTIVITY.STALLS_TOTAL - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ ) / 2 if ( 1 ) else ( CYCLE_ACTIVITY.STALLS_TOTAL - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) / 2 if #SMT_on else ( UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) / 2 if ( 1 ) else ( UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / 2 if #SMT_on else ( UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / 2 if ( 1 ) else ( UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 ) if ( 1 ) else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_3m", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_5", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_4", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_7", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", - "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_light_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "MetricExpr": "( ( INST_RETIRED.X87 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) )", + "MetricExpr": "( ( INST_RETIRED.X87 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) ) )", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", "ScaleUnit": "100%" @@ -701,75 +701,449 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_fp_vector", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_128b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_256b", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_microcode_sequencer", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", - "MetricExpr": "( min( ( ( 100 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 66 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_assists", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 100 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 66 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_cisc", "ScaleUnit": "100%" }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" + }, { "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_info_core_coreipc" }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" + }, { "BriefDescription": "Instruction per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_info_inst_mix_iptb" }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ / 2 ) if ( 1 ) else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", "MetricName": "tma_info_bad_spec_ipmispredict" }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "( INST_RETIRED.ANY ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * BR_MISP_EXEC.INDIRECT )", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB )", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Mem;Backend;CacheMisses;TopdownL1;tma_L1_group", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 8 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cbox@UNC_C_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( ( cbox@UNC_C_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Total package Power in Watts", + "MetricExpr": "( FREERUN_PKG_ENERGY_STATUS * ( 61 ) + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( ( ( duration_time * 1000 ) / 1000 ) * ( 1000000 ) )", + "MetricGroup": "Power;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox@UNC_C_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" } ] \ No newline at end of file diff --git a/CLX/metrics/cascadelakex_metrics.json b/CLX/metrics/cascadelakex_metrics.json index 1b66fe44..f6b53755 100644 --- a/CLX/metrics/cascadelakex_metrics.json +++ b/CLX/metrics/cascadelakex_metrics.json @@ -1,10 +1,12 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product - V", - "DatePublished": "11/09/2023", - "Version": "", - "Legend": "" + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 2nd Generation Intel(R) Xeon(R) Processor Scalable Family based on Cascade Lake product0", + "DatePublished": "01/17/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" }, "Metrics": [ { @@ -984,6 +986,25 @@ "ResolutionLevels": "CHA, SOCKET, SYSTEM", "MetricGroup": "" }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, { "MetricName": "upi_data_receive_bw", "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", @@ -1023,20 +1044,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1;PGO" }, { @@ -1060,20 +1072,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Frontend;TmaL2" }, { @@ -1101,8 +1104,8 @@ "Formula": "100 * ( ( a + 2 * b ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;IcMiss" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;IcMiss" }, { "MetricName": "ITLB_Misses", @@ -1113,7 +1116,7 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "ICACHE_64B.IFTAG_STALL", + "Name": "ICACHE_TAG.STALLS", "Alias": "a" }, { @@ -1125,8 +1128,8 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" }, { "MetricName": "Branch_Resteers", @@ -1153,7 +1156,7 @@ "Formula": "100 * ( a / ( b ) + ( ( 9 ) * c / ( b ) ) )", "Category": "TMA", "Threshold": "> 5 & P; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { @@ -1185,7 +1188,7 @@ "Formula": "100 * ( ( a / ( a + b ) ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueBM", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts" }, { @@ -1217,7 +1220,7 @@ "Formula": "100 * ( ( 1 - ( a / ( a + b ) ) ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears" }, { @@ -1225,7 +1228,7 @@ "LegacyName": "metric_TMA_......Unknown_Branches(%)", "ParentCategory": "Branch_Resteers", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "UnitOfMeasure": "percent", "Events": [ { @@ -1241,19 +1244,19 @@ "Formula": "100 * ( ( 9 ) * a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat" }, { - "MetricName": "DSB_Switches", - "LegacyName": "metric_TMA_....DSB_Switches(%)", + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Name": "IDQ.MS_SWITCHES", "Alias": "a" }, { @@ -1262,22 +1265,22 @@ } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DSBmiss;FetchLat" + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq" }, { "MetricName": "LCP", "LegacyName": "metric_TMA_....LCP(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "ILD_STALL.LCP", + "Name": "DECODE.LCP", "Alias": "a" }, { @@ -1289,19 +1292,19 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { - "MetricName": "MS_Switches", - "LegacyName": "metric_TMA_....MS_Switches(%)", + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.MS_SWITCHES", + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "Alias": "a" }, { @@ -1310,11 +1313,11 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "FetchLat;MicroSeq" + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat" }, { "MetricName": "Fetch_Bandwidth", @@ -1341,20 +1344,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( 4 ) * d / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( 4 ) * d / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P & #HighIPC; $issueFB", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "Threshold": "> 20; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2" }, { @@ -1382,20 +1376,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, { @@ -1423,20 +1408,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P; $issueD0", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, { @@ -1448,11 +1424,11 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "Name": "IDQ.DSB_CYCLES_ANY", "Alias": "a" }, { - "Name": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "Name": "IDQ.DSB_CYCLES_OK", "Alias": "b" }, { @@ -1464,20 +1440,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSB;FetchBW" }, { @@ -1512,20 +1479,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1569,21 +1527,64 @@ "Alias": "h" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( g / 2 ) if ( 1 ) else ( h ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "d" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "e" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" } ], - "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( g / 2 ) if smt_on else ( h ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( max( ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( g / 2 ) if ( 1 ) else ( h ) ) ) ) ) * ( 1 - a / ( i - b ) ) , 0.0001 ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueBM", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2" + "Threshold": "> 5 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" }, { "MetricName": "Machine_Clears", @@ -1626,21 +1627,64 @@ "Alias": "h" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueMC; $issueSyncxn", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears;TmaL2" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "b" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "c" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "g" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "i" } ], - "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( max( ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) ) ) * ( 1 - i / h ) , 0.0001 ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueMC; $issueSyncxn", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", - "MetricGroup": "BadSpec;MachineClears;TmaL2" + "Threshold": "> 5 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Machine_Clears" }, { "MetricName": "Backend_Bound", @@ -1674,20 +1718,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 20", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1747,20 +1782,11 @@ "Alias": "l" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a + b ) / ( c + ( d + ( ( e ) / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( g ) ) ) ) * h ) + b ) ) * ( 1 - ( i / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( g ) ) ) ) - ( j + ( 4 ) * ( ( k / 2 ) if smt_on else l ) ) / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( g ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( c + ( d + ( ( e ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) * h ) + b ) ) * ( 1 - ( i / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) - ( j + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2" }, { @@ -1788,8 +1814,8 @@ "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueL1; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "DTLB_Load", @@ -1824,7 +1850,7 @@ "Formula": "100 * ( min( ( 9 ) * a + b , max( c - d , 0 ) ) / ( e ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1860,7 +1886,7 @@ "Formula": "100 * ( ( min( ( 9 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1884,7 +1910,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1905,10 +1931,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1945,10 +1971,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 12 * max( 0 , a - b ) + ( a / c ) * ( ( 11 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 12 * max( 0 , a - b ) + ( a / c ) * ( ( 11 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueRFO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore" }, { @@ -1981,10 +2007,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2008,7 +2034,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2044,7 +2070,7 @@ "Formula": "100 * ( ( a / ( b + c ) ) * d / ( e ) )", "Category": "TMA", "Threshold": "> 30; $issueBW; $issueSL; $issueSmSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW" }, { @@ -2088,8 +2114,8 @@ "Formula": "100 * ( ( ( a * ( 1 + ( b / c ) ) ) / ( ( a * ( 1 + ( b / c ) ) ) + d ) ) * ( ( e - f ) / ( g ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "L3_Bound", @@ -2116,8 +2142,8 @@ "Formula": "100 * ( ( a - b ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "Contested_Accesses", @@ -2170,10 +2196,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -2227,10 +2253,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Snoop" }, { @@ -2238,7 +2264,7 @@ "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", "UnitOfMeasure": "percent", "Events": [ { @@ -2272,10 +2298,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e ) * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat" }, { @@ -2299,20 +2325,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a / 2 ) if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a / 2 ) if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 30 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2381,10 +2398,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) / ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) + ( 25 * ( ( m * ( 1 + ( f / g ) ) ) ) + 33 * ( ( n * ( 1 + ( f / g ) ) ) ) ) ) ) ) ) * ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) ) if ( ( 1000000 ) * ( n + m ) > g ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) / ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) + ( 25 * ( m * ( 1 + ( f / g ) ) ) + 33 * ( n * ( 1 + ( f / g ) ) ) ) ) ) ) * ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) ) if ( ( 1000000 ) * ( n + m ) > g ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2392,7 +2409,7 @@ "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2408,7 +2425,7 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2416,7 +2433,7 @@ "LegacyName": "metric_TMA_......MEM_Latency(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2436,12 +2453,12 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { - "MetricName": "Local_DRAM", - "LegacyName": "metric_TMA_........Local_DRAM(%)", + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", @@ -2478,18 +2495,18 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server" }, { - "MetricName": "Remote_DRAM", - "LegacyName": "metric_TMA_........Remote_DRAM(%)", + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2523,10 +2540,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 147.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 147.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server;Snoop" }, { @@ -2534,7 +2551,7 @@ "LegacyName": "metric_TMA_........Remote_Cache(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2572,10 +2589,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Server;Snoop" }, { @@ -2644,10 +2661,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( ( 1 - ( ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( ( g * ( 1 + ( b / c ) ) ) ) + 33 * ( ( h * ( 1 + ( b / c ) ) ) ) ) ) ) ) ) * ( i / ( j ) + ( ( k - l ) / ( j ) ) - ( ( ( m * ( 1 + ( b / c ) ) ) / ( ( m * ( 1 + ( b / c ) ) ) + n ) ) * ( ( k - l ) / ( j ) ) ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 1 - ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( g * ( 1 + ( b / c ) ) ) + 33 * ( h * ( 1 + ( b / c ) ) ) ) ) ) ) * ( i / ( j ) + ( ( k - l ) / ( j ) ) - ( ( ( m * ( 1 + ( b / c ) ) ) / ( ( m * ( 1 + ( b / c ) ) ) + n ) ) * ( ( k - l ) / ( j ) ) ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;Server;TmaL3mem" }, { @@ -2671,7 +2688,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2704,10 +2721,10 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a * ( 11 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "Formula": "100 * ( min( ( ( ( a * ( 11 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { @@ -2753,10 +2770,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * ( e + f ) + ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * ( g + h ) ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f ) + ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( g + h ) ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -2780,20 +2797,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2821,20 +2829,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if smt_on else ( d ) ) ) , ( 1 ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2862,20 +2861,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if smt_on else ( d ) ) ) , ( 1 ) ) ) - ( b / ( ( c / 2 ) if smt_on else ( d ) ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) - ( min( ( b / ( ( c / 2 ) if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2899,20 +2889,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2972,20 +2953,11 @@ "Alias": "l" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2;Compute" }, { @@ -3009,7 +2981,55 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PARTIAL_RAT_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueSO", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ROB_MISC_EVENTS.PAUSE_INST", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 40 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3025,52 +3045,67 @@ "Alias": "a" }, { - "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", "Alias": "b" }, { - "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", "Alias": "c" }, { - "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "d" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "UOPS_ISSUED.ANY", "Alias": "e" }, { - "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", "Alias": "f" }, { - "Name": "ARITH.DIVIDER_ACTIVE", + "Name": "INT_MISC.RECOVERY_CYCLES", "Alias": "g" }, { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "Alias": "h" }, { - "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "i" - } - ], - "Constants": [ + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "m" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "n" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "o" } ], - "Formula": "100 * ( ( a + ( b + ( ( c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * f ) ) / ( e ) if ( g < ( h - i ) ) else ( b + ( ( c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * f ) / ( e ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a + ( ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( ( ( h + i ) / ( j + ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) + i ) ) * ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) ) ) * n ) / ( d ) * ( j - h ) / ( d ) ) * ( d ) + ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) ) / ( d ) if ( o < ( j - h ) ) else ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) / ( d ) )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3082,116 +3117,91 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "Alias": "a" }, { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", "Alias": "b" }, { - "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", "Alias": "c" }, { - "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "d" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "UOPS_ISSUED.ANY", "Alias": "e" - } - ], - "Constants": [ + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "f" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / 2 if smt_on else b - c ) / ( ( d / 2 ) if smt_on else ( e ) ) )", - "Category": "TMA", - "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "PortsUtil" - }, - { - "MetricName": "Serializing_Operation", - "LegacyName": "metric_TMA_........Serializing_Operation(%)", - "ParentCategory": "Ports_Utilized_0", - "Level": 5, - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", - "UnitOfMeasure": "percent", - "Events": [ + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "g" + }, { - "Name": "PARTIAL_RAT_STALLS.SCOREBOARD", - "Alias": "a" + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "h" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "b" - } - ], - "Constants": [], - "Formula": "100 * ( a / ( b ) )", - "Category": "TMA", - "Threshold": "> 10 & P; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "PortsUtil" - }, - { - "MetricName": "Slow_Pause", - "LegacyName": "metric_TMA_..........Slow_Pause(%)", - "ParentCategory": "Serializing_Operation", - "Level": 6, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", - "UnitOfMeasure": "percent", - "Events": [ + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "i" + }, { - "Name": "ROB_MISC_EVENTS.PAUSE_INST", - "Alias": "a" + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "b" + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "m" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "n" } ], "Constants": [], - "Formula": "100 * ( 40 * a / ( b ) )", + "Formula": "100 * ( ( a + ( ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( ( ( h + i ) / ( j + ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) + i ) ) * ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) ) ) * n ) / ( d ) * ( j - h ) / ( d ) )", "Category": "TMA", - "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "Threshold": "> 20 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" }, { "MetricName": "Mixing_Vectors", "LegacyName": "metric_TMA_........Mixing_Vectors(%)", "ParentCategory": "Ports_Utilized_0", "Level": 5, - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", "UnitOfMeasure": "percent", "Events": [ - { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "a" - }, { "Name": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "Alias": "b" + "Alias": "a" }, { "Name": "UOPS_ISSUED.ANY", - "Alias": "c" + "Alias": "b" } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) * b / c ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( a / b ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5; $issueMV", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3223,20 +3233,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else c ) / ( ( d / 2 ) if smt_on else ( e ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else c ) / ( ( d / 2 ) if ( 1 ) else ( e ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueL1", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3268,20 +3269,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else c ) / ( ( d / 2 ) if smt_on else ( e ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else c ) / ( ( d / 2 ) if ( 1 ) else ( e ) ) )", "Category": "TMA", "Threshold": "> 15 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3305,20 +3297,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / 2 if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / 2 if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", - "Threshold": "> 70 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3354,20 +3337,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3391,20 +3365,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -3428,20 +3393,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3465,20 +3421,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3486,7 +3433,7 @@ "LegacyName": "metric_TMA_..........Port_6(%)", "ParentCategory": "ALU_Op_Utilization", "Level": 6, - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "UnitOfMeasure": "percent", "Events": [ { @@ -3502,20 +3449,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3551,20 +3489,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3588,20 +3517,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3625,20 +3545,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3662,20 +3573,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3699,20 +3601,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3736,20 +3629,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3772,20 +3656,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "(> 70 | Heavy_Operations)", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -3793,7 +3668,7 @@ "LegacyName": "metric_TMA_..Light_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3817,20 +3692,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -3870,20 +3736,11 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * d / e ) + ( ( f ) / ( a ) ) + ( min( ( ( g ) / ( a ) ) , ( 1 ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * d / e ) + ( ( f ) / ( a ) ) + ( min( ( ( g ) / ( a ) ) , ( 1.0 ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "HPC" }, { @@ -3915,20 +3772,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * d / e )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * d / e )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -3952,7 +3800,7 @@ "Formula": "100 * ( ( a ) / ( b ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3973,10 +3821,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a ) / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -4001,10 +3849,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -4029,10 +3877,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -4057,10 +3905,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -4068,7 +3916,7 @@ "LegacyName": "metric_TMA_....Memory_Operations(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", "UnitOfMeasure": "percent", "Events": [ { @@ -4096,20 +3944,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * f / e )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * f / e )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { @@ -4117,7 +3956,7 @@ "LegacyName": "metric_TMA_....Fused_Instructions(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", "UnitOfMeasure": "percent", "Events": [ { @@ -4141,21 +3980,12 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * d / ( a ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * d / ( a ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" }, { "MetricName": "Non_Fused_Branches", @@ -4190,28 +4020,19 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( f - d ) / ( a ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( f - d ) / ( a ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" }, { - "MetricName": "Nop_Instructions", - "LegacyName": "metric_TMA_....Nop_Instructions(%)", + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "UnitOfMeasure": "percent", "Events": [ { @@ -4235,32 +4056,43 @@ "Alias": "e" }, { - "Name": "INST_RETIRED.NOP", + "Name": "UOPS_EXECUTED.X87", "Alias": "f" - } - ], - "Constants": [ + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "i" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "MEM_INST_RETIRED.ANY", + "Alias": "j" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "k" } ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * f / ( a ) )", + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) - ( ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * f / g ) + ( ( h ) / ( a ) ) + ( min( ( ( i ) / ( a ) ) , ( 1.0 ) ) ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * j / e ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * d / ( a ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( k - d ) / ( a ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 30 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { - "MetricName": "Other_Light_Ops", - "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", "ParentCategory": "Light_Operations", - "Level": 3, - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", "UnitOfMeasure": "percent", "Events": [ { @@ -4283,49 +4115,16 @@ "Name": "INST_RETIRED.ANY", "Alias": "e" }, - { - "Name": "UOPS_EXECUTED.X87", - "Alias": "f" - }, - { - "Name": "UOPS_EXECUTED.THREAD", - "Alias": "g" - }, - { - "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", - "Alias": "h" - }, - { - "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", - "Alias": "i" - }, - { - "Name": "MEM_INST_RETIRED.ANY", - "Alias": "j" - }, - { - "Name": "BR_INST_RETIRED.ALL_BRANCHES", - "Alias": "k" - }, { "Name": "INST_RETIRED.NOP", - "Alias": "l" - } - ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Alias": "f" } ], - "Formula": "100 * ( max( 0 , ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) - ( ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * f / g ) + ( ( h ) / ( a ) ) + ( min( ( ( i ) / ( a ) ) , ( 1 ) ) ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * j / e ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * d / ( a ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( k - d ) / ( a ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * l / ( a ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * f / ( a ) )", "Category": "TMA", - "Threshold": "> 30 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 10 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { @@ -4333,7 +4132,7 @@ "LegacyName": "metric_TMA_..Heavy_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -4357,20 +4156,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) )", "Category": "TMA", "Threshold": "> 10", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -4410,20 +4200,11 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) - ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueD0", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -4455,20 +4236,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC; $issueMS", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MicroSeq" }, { @@ -4496,21 +4268,40 @@ "Alias": "d" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( min( ( ( 34 ) * ( a + b ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ASSIST.ANY", + "Alias": "a" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], - "Formula": "100 * ( min( ( ( 100 ) * ( a + b ) / ( ( 4 ) * ( ( c / 2 ) if smt_on else ( d ) ) ) ) , ( 1 ) ) )", + "Constants": [], + "Formula": "100 * ( 34 * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "Threshold": "> 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" }, { "MetricName": "CISC", @@ -4549,126 +4340,4668 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) - ( min( ( ( 100 ) * ( f + g ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) , ( 1 ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( min( ( ( 34 ) * ( f + g ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) , ( 1.0 ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { - "MetricName": "Info_Core_CoreIPC", - "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "MetricName": "Info_Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Info_Bottleneck_Mispredictions", "Level": 1, - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UOPS_RETIRED.RETIRE_SLOTS", "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "IDQ.MS_UOPS", "Alias": "c" - } - ], - "Constants": [ + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "g" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "m" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "n" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "o" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "p" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "q" + }, + { + "Name": "DECODE.LCP", + "Alias": "r" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( ( 9 ) * p / ( e ) ) ) + ( min( ( ( 2 ) * q / ( e ) ) , ( 1.0 ) ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Info_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "d" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "e" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "f" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( ( 9 ) * g / ( c ) ) ) + ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB" + }, + { + "MetricName": "Info_Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Info_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "e" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "f" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "i" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "k" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "n" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "q" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "r" + }, + { + "Name": "DECODE.LCP", + "Alias": "s" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "t" + }, + { + "Name": "UOPS_RETIRED.MACRO_FUSED", + "Alias": "u" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "v" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "w" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "x" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( g / ( g + h ) ) * m / ( c ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) + ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) - ( ( ( ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( d ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) * ( ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( g / ( g + h ) ) * m / ( c ) ) * ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) / ( ( ( g / ( g + h ) ) * m / ( c ) ) + ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) + ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( p / ( c ) ) + ( ( n + 2 * o ) / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) + ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW;Frontend" + }, + { + "MetricName": "Info_Bottleneck_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Info_Bottleneck_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_a" + }, + { + "Name": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "Alias": "a_b" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "a_f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Alias": "a_g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Alias": "a_h" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_i" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_j" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_k" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_l" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_m" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_n" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_o" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_p" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_q" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_r" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_s" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_t" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_u" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_v" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_w" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "a_x" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "h" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "i" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "j" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "k" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "l" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", 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1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( g ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_e * ( 1 + ( q / r ) / 2 ) ) / ( g ) ) , ( 1.0 ) ) ) + ( ( ( a_k / 2 ) if ( 1 ) else a_k ) / ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( ( e ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) * h ) + b ) ) * ( 1 - ( i / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) - ( j + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) ) * ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( g ) ) ) / ( ( max( ( a - n ) / ( g ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( g ) ) ) + ( ( o - m ) / ( g ) ) + ( min( ( ( ( m / ( g ) + ( ( n - o ) / ( g ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( g ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( 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) else ( g ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( a_p * ( 11 ) * ( 1 - ( a_q / a_r ) ) ) + ( 1 - ( a_q / a_r ) ) * ( min( g , a_s ) ) ) / ( g ) ) , ( 1.0 ) ) ) ) ) + ( ( ( j - ( e ) + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) - ( ( a_w / ( a_w + a_x ) ) * ( ( j - ( e ) + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) ) ) * ( 1 - ( max( ( ( ( j - ( e ) + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) - ( ( a_w / ( a_w + a_x ) ) * ( ( j - ( e ) + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) ) ) * ( 1 - a_y / a_x ) , 0.0001 ) ) / ( ( max( ( ( ( j - ( e ) + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) - ( ( a_w / ( a_w + a_x ) ) * ( ( j - ( e ) + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) ) ) * ( 1 - a_y / a_x ) , 0.0001 ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueTLB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Info_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "d" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "e" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "m" + }, + { + "Name": "PARTIAL_RAT_STALLS.SCOREBOARD", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "o" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "p" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "Alias": "q" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "r" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( ( 1 - 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g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) ) ) + ( ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( ( ( o + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * p ) / ( c ) * ( i - g ) / ( c ) ) * ( c ) + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) ) / ( c ) if ( m < ( i - g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) / ( ( m / ( c ) ) + ( n / ( c ) ) + ( ( ( ( o + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * p ) / ( c ) * ( i - g ) / ( c ) ) * ( c ) + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) ) / ( c ) if ( m < ( i - g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) ) ) * ( ( ( q / 2 if ( 1 ) else q ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) / ( ( ( o + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * p ) / ( c ) * ( i - g ) / ( c ) ) + ( ( ( r - s ) / 2 if ( 1 ) else j ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( ( ( s - q ) / 2 if ( 1 ) else l ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( ( q / 2 if ( 1 ) else q ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueComp", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor" + }, + { + "MetricName": "Info_Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_a" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_b" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a_d" + }, + { + "Name": "PARTIAL_RAT_STALLS.SCOREBOARD", + "Alias": "a_e" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "a_f" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a_g" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "a_h" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.MACRO_FUSED", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "g" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "h" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "i" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "j" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "m" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "n" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "o" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "p" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "s" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "x" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "y" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "z" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( ( ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) / ( ( ( ( ( a ) + f - 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( n / ( n + o ) ) ) * l / ( e ) ) + ( ( 9 ) * m / ( e ) ) ) ) / ( ( ( s + 2 * t ) / ( e ) ) + ( u / ( e ) ) + ( l / ( e ) + ( ( 9 ) * m / ( e ) ) ) + ( min( ( ( 2 ) * k / ( e ) ) , ( 1.0 ) ) ) + ( v / ( e ) ) + ( w / ( e ) ) ) ) + ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( max( ( ( n / ( n + o ) ) * ( ( b - ( a ) + ( 4 ) * ( ( p / 2 ) if ( 1 ) else q ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) * ( 1 - n / ( r - o ) ) , 0.0001 ) ) / ( ( n / ( n + o ) ) * ( ( b - ( a ) + ( 4 ) * ( ( p / 2 ) if ( 1 ) else q ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) ) * ( ( n / ( n + o ) ) * ( ( b - ( a ) + ( 4 ) * ( ( p / 2 ) if ( 1 ) else q ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) + ( ( ( ( b - ( a ) + ( 4 ) * ( ( p / 2 ) if ( 1 ) else q ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( ( n / ( n + o ) ) * ( ( b - ( a ) + ( 4 ) * ( ( p / 2 ) if ( 1 ) else q ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) ) * ( max( ( ( ( b - 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( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( ( ( a_s / 2 ) if ( 1 ) else a_s ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w * ( a_x / ( a_x + a_y ) ) ) + ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( c ) / a_t ) * a_u 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a_h ) ) * a_j / ( c ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_r ) ) / ( c ) - ( ( min( c , a_q ) ) / ( c ) ) ) / ( ( ( min( c , a_q ) ) / ( c ) ) + ( ( min( c , a_r ) ) / ( c ) - ( ( min( c , a_q ) ) / ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 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) * ( b_a + a_w * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) , ( 1.0 ) ) ) + ( ( ( a_s / 2 ) if ( 1 ) else a_s ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( z / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( min( ( ( ( b_l * ( 11 ) * ( 1 - ( b_i / b_k ) ) ) + ( 1 - ( b_i / b_k ) ) * ( min( c , b_m ) ) ) / ( c ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( b_l * ( 11 ) * ( 1 - ( b_i / b_k ) ) ) + ( 1 - ( b_i / b_k ) ) * ( min( c , b_m ) ) ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_p + b_q ) + ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_r + b_s ) ) / ( c ) ) , ( 1.0 ) ) ) + ( b_t / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( min( ( ( ( 9 ) * b_u + b_v ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( max( ( y - a_e ) / ( c ) , 0 ) ) / max( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) , ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) ) * ( ( min( ( 9 ) * b_d + b_e , max( b_f - b_g , 0 ) ) / ( c ) ) / max( ( max( ( y - a_e ) / ( c ) , 0 ) ) , ( ( min( ( 9 ) * b_d + b_e , max( b_f - b_g , 0 ) ) / ( c ) ) + ( min( ( 13 * b_h / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , b_i - b_j ) + ( b_i / b_k ) * ( ( 11 ) * b_l + ( min( c , b_m ) ) ) ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( b_c / ( a_i + a_h ) ) * b_n / ( c ) ) , ( 1.0 ) ) ) + ( b_o / ( c ) ) + ( ( b_c / ( a_i + a_h ) ) * a_j / ( c ) ) ) ) ) + ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( z / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( min( ( ( ( 9 ) * b_u + b_v ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( b_l * ( 11 ) * ( 1 - ( b_i / b_k ) ) ) + ( 1 - ( b_i / b_k ) ) * ( min( c , b_m ) ) ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_p + b_q ) + ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_r + b_s ) ) / ( c ) ) , ( 1.0 ) ) ) + ( b_t / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( min( ( ( ( 9 ) * b_u + b_v ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_r ) ) / ( c ) - ( ( min( c , a_q ) ) / ( c ) ) ) / ( ( ( min( c , a_q ) ) / ( c ) ) + ( ( min( c , a_r ) ) / ( c ) - ( ( min( c , a_q ) ) / ( c ) ) ) ) ) * ( min( ( ( ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_n + ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_m ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 80 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_l * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 147.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_k * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_n + ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_m ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) ) + ( ( ( a_f - a_d ) / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( min( ( ( ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w * ( a_x / ( a_x + a_y ) ) ) + ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a + a_w * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w * ( a_x / ( a_x + a_y ) ) ) + ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_z ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a + a_w * ( 1 - ( a_x / ( a_x + a_y ) ) ) ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b * ( 1 + ( a_h / a_i ) / 2 ) ) / ( c ) ) , ( 1.0 ) ) ) + ( ( ( a_s / 2 ) if ( 1 ) else a_s ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( z / ( c ) ) / ( ( max( ( y - a_e ) / ( c ) , 0 ) ) + ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) / ( ( 19 * ( a_k * ( 1 + ( a_h / a_i ) ) ) + 10 * ( ( a_l * ( 1 + ( a_h / a_i ) ) ) + ( a_m * ( 1 + ( a_h / a_i ) ) ) + ( a_n * ( 1 + ( a_h / a_i ) ) ) ) ) + ( 25 * ( a_o * ( 1 + ( a_h / a_i ) ) ) + 33 * ( a_p * ( 1 + ( a_h / a_i ) ) ) ) ) ) ) * ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) if ( ( 1000000 ) * ( a_p + a_o ) > a_i ) else 0 ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( min( ( ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_p + b_q ) + ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_r + b_s ) ) / ( c ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( b_l * ( 11 ) * ( 1 - ( b_i / b_k ) ) ) + ( 1 - ( b_i / b_k ) ) * ( min( c , b_m ) ) ) / ( c ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_p + b_q ) + ( 47.5 * ( ( ( c ) / a_t ) * a_u / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( b_r + b_s ) ) / ( c ) ) , ( 1.0 ) ) ) + ( b_t / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( min( ( ( ( 9 ) * b_u + b_v ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( b_l * ( 11 ) * ( 1 - ( b_i / b_k ) ) ) + ( 1 - ( b_i / b_k ) ) * ( min( c , b_m ) ) ) / ( c ) ) , ( 1.0 ) ) ) ) ) + ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( 1 - ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( 1 - b_w / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( 1 - b_w / q ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( b_x / ( c ) ) / ( ( b_x / ( c ) ) + ( b_y / ( c ) ) + ( ( ( ( b_z + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a ) / ( c ) * ( a_a - y ) / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_x < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( ( ( b_z + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a ) / ( c ) * ( a_a - y ) / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_x < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) / ( c ) ) / ( ( b_x / ( c ) ) + ( b_y / ( c ) ) + ( ( ( ( b_z + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a ) / ( c ) * ( a_a - y ) / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_x < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) * ( ( ( c_b / 2 if ( 1 ) else c_b ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) / ( ( ( b_z + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a ) / ( c ) * ( a_a - y ) / ( c ) ) + ( ( ( c_c - c_d ) / 2 if ( 1 ) else a_b ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( ( ( c_d - c_b ) / 2 if ( 1 ) else a_c ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) + ( ( c_b / 2 if ( 1 ) else c_b ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( h / ( c ) + ( ( 9 ) * g / ( c ) ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( ( 9 ) * g / ( c ) ) ) + ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( 1 - b_w / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( 1 - b_w / q ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( b_y / ( c ) ) + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a / ( c ) * ( ( b_z + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a ) / ( c ) * ( a_a - y ) / ( c ) ) ) / ( ( b_x / ( c ) ) + ( b_y / ( c ) ) + ( ( ( ( b_z + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * c_a ) / ( c ) * ( a_a - y ) / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_x < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) + ( 100 * ( ( c_e + c_f ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( 100 * ( ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( c_e + c_f ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a + b ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Bottleneck_Base_Non_Br", + "LegacyName": "metric_TMA_Info_Bottleneck_Base_Non_Br", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.MACRO_FUSED", + "Alias": "h" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "i" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "j" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( d + e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( a ) + h - i ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( j + k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( a ) + h - i ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( 4 ) * ( ( a / 2 ) if ( 1 ) else ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( ( f / 2 ) if ( 1 ) else ( g ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( ( a ) + ( b ) ) / ( 2 * ( ( c / 2 ) if ( 1 ) else ( d ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a / 2 ) if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Botlnk_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "d" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "e" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "m" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "n" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "p" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) / ( ( ( ( m + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * n ) / ( c ) * ( i - g ) / ( c ) ) * ( c ) + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) ) / ( c ) if ( o < ( i - g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) if ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) < ( ( ( ( m + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * n ) / ( c ) * ( i - g ) / ( c ) ) * ( c ) + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) ) / ( c ) if ( o < ( i - g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) else 1 ) if ( 1 - p / ( q / 2 ) if ( 1 ) else 0 ) > 0.5 else 0", + "Category": "TMA", + "Threshold": "> 50", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( b + 2 * c + 4 * d + 8 * e + 16 * f )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b ) + ( c ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ROB_MISC_EVENTS.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.T0:u0xF", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "b" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 100000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( a + b + c )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.COUNT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "a" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b + 2", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 50", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Botlnk_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "d" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "e" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "f" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "i" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "j" + }, + { + "Name": "DECODE.LCP", + "Alias": "k" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "l" + }, + { + "Name": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "Alias": "m" + }, + { + "Name": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "Alias": "n" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "o" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "p" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( d / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( g / ( c ) ) + ( h / ( c ) + ( ( 9 ) * i / ( c ) ) ) + ( min( ( ( 2 ) * j / ( c ) ) , ( 1.0 ) ) ) + ( k / ( c ) ) + ( d / ( c ) ) ) + ( ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( m - n ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) / 2 ) / ( ( ( m - n ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) / 2 ) + ( ( o - p ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) / 2 ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Botlnk_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "d" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "e" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "g" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( d + 2 * e ) / ( c ) ) / ( ( ( d + 2 * e ) / ( c ) ) + ( f / ( c ) ) + ( g / ( c ) + ( ( 9 ) * h / ( c ) ) ) + ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueFL", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "BR_MISP_EXEC.INDIRECT", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a ) / ( ( ( b ) / c ) * d )", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "g" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "m" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "n" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "o" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "p" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "q" + }, + { + "Name": "DECODE.LCP", + "Alias": "r" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( ( 9 ) * p / ( e ) ) ) + ( min( ( ( 2 ) * q / ( e ) ) , ( 1.0 ) ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) ) * ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) / f / 100", + "Category": "TMA", + "Threshold": "; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NOT_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.CONDITIONAL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NOT_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NOT_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a - ( b - c ) - 2 * d ) / e", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "EPT.WALK_PENDING", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( a + b + c + d ) / ( 2 * ( ( e / 2 ) if ( 1 ) else ( f ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 112 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License0_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License0_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL0_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / 2 / ( ( b / 2 ) if ( 1 ) else ( c ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License1_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License1_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL1_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / 2 / ( ( b / 2 ) if ( 1 ) else ( c ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License2_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License2_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL2_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / 2 / ( ( b / 2 ) if ( 1 ) else ( c ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / ( b / 2 ) if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" } ], - "Formula": "a / ( ( b / 2 ) if smt_on else ( c ) )", + "Constants": [], + "Formula": "a / b", "Category": "TMA", "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Ret;SMT;TmaL1" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" }, { - "MetricName": "Info_Core_IpMispredict", - "LegacyName": "metric_TMA_Info_Core_IpMispredict", + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", "Level": 1, - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UNC_M_CAS_COUNT.RD", "Alias": "a" }, { - "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", "Alias": "b" } ], "Constants": [], "Formula": "a / b", "Category": "TMA", - "Threshold": "< 200", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Bad;BadSpec;BrMispredicts" + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" }, { - "MetricName": "Info_Inst_Mix_IpTB", - "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "MetricName": "Info_System_MEM_PMM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_PMM_Read_Latency", "Level": 1, - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", "Alias": "a" }, { - "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Name": "UNC_M_PMM_RPQ_INSERTS", "Alias": "b" + }, + { + "Name": "UNC_M_CLOCKTICKS:one_unit", + "Alias": "c" } ], "Constants": [], - "Formula": "a / b", + "Formula": "( ( 1000000000 ) * ( a / b ) / c )", "Category": "TMA", - "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" }, { - "MetricName": "Info_Memory_L2MPKI", - "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", "Level": 1, - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", "UnitOfMeasure": "", "Events": [ { - "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Name": "UNC_M_RPQ_OCCUPANCY", "Alias": "a" }, { - "Name": "INST_RETIRED.ANY", + "Name": "UNC_M_RPQ_INSERTS", "Alias": "b" + }, + { + "Name": "UNC_M_CLOCKTICKS:one_unit", + "Alias": "c" } ], "Constants": [], - "Formula": "1000 * a / b", + "Formula": "( 1000000000 ) * ( a / b ) / c", "Category": "TMA", "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Mem;Backend;CacheMisses" + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Read_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Read_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Write_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Write_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Alias": "a" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Alias": "b" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Alias": "c" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b + c + d ) * 4 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Alias": "a" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Alias": "b" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Alias": "c" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b + c + d ) * 4 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" } ] } \ No newline at end of file diff --git a/CLX/metrics/perf/cascadelakex_metrics_perf.json b/CLX/metrics/perf/cascadelakex_metrics_perf.json index 6307e27a..10823c6e 100644 --- a/CLX/metrics/perf/cascadelakex_metrics_perf.json +++ b/CLX/metrics/perf/cascadelakex_metrics_perf.json @@ -279,6 +279,13 @@ "MetricName": "llc_miss_remote_memory_bandwidth_read", "ScaleUnit": "1MB/s" }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", "MetricExpr": "( UNC_UPI_RxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", @@ -288,14 +295,14 @@ }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "MetricExpr": "( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "ScaleUnit": "100%" @@ -303,14 +310,14 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", "MetricExpr": "( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "( ICACHE_64B.IFTAG_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricExpr": "( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%" }, @@ -336,92 +343,106 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "MetricExpr": "( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "MetricExpr": "( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "MetricExpr": "( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_mite", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", "MetricName": "tma_decoder0_alone", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "MetricExpr": "( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_dsb", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) )", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) )", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "ScaleUnit": "100%" + }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "MetricExpr": "( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "ScaleUnit": "100%" @@ -429,7 +450,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", "MetricExpr": "( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "ScaleUnit": "100%" }, @@ -456,21 +477,21 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "MetricExpr": "( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_lock_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "ScaleUnit": "100%" @@ -492,61 +513,61 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", "MetricExpr": "( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", "MetricExpr": "( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "MetricExpr": "( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "MetricExpr": "( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_data_sharing", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "MetricExpr": "( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", - "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_sq_full", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_latency", @@ -554,28 +575,28 @@ }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", + "MetricName": "tma_local_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", + "MetricName": "tma_remote_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_remote_cache", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", - "MetricExpr": "( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "ScaleUnit": "100%" @@ -589,49 +610,49 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "MetricExpr": "( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "MetricExpr": "( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_false_sharing", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", - "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_split_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", - "MetricExpr": "( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) ) - ( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( min( ( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) - ( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_hit", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_miss", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "MetricExpr": "( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "ScaleUnit": "100%" @@ -643,163 +664,163 @@ "MetricName": "tma_divider", "ScaleUnit": "100%" }, - { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "MetricExpr": "( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "MetricExpr": "( ( UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "ScaleUnit": "100%" - }, { "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", "MetricExpr": "( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", "MetricName": "tma_serializing_operation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", "MetricExpr": "( 40 * ROB_MISC_EVENTS.PAUSE_INST / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", "MetricName": "tma_slow_pause", "ScaleUnit": "100%" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "MetricExpr": "( min( ( ( CPU_CLK_UNHALTED.THREAD ) * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "MetricExpr": "( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "MetricExpr": "( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricExpr": "( min( ( UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", "MetricName": "tma_mixing_vectors", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if ( 1 ) else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if ( 1 ) else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_3m", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_5", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_4", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_7", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", - "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_light_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) )", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) ) )", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", "ScaleUnit": "100%" }, { "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD )", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD )", "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", "ScaleUnit": "100%" @@ -813,113 +834,289 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_fp_vector", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_128b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_256b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_512b", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_memory_operations", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fused_instructions", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_non_fused_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) ) ) )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", + "MetricName": "tma_other_light_ops", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) ) ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_few_uops_instructions", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_microcode_sequencer", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", - "MetricExpr": "( min( ( ( 100 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_assists", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "MetricExpr": "( 34 * FP_ASSIST.ANY / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 100 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_cisc", "ScaleUnit": "100%" }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( 100 * ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_big_code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchBW;Frontend;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryTLB;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_data_tlbs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "MetricExpr": "100 * ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) )", + "MetricGroup": "Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_synchronization" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "MetricExpr": "100 * ( 100 * ( ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if ( 1 ) else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if ( 1 ) else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricGroup": "Cor;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_compute_bound_est" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Bad;Cor;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_irregular_overhead" + }, + { + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "MetricExpr": "100 - ( ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if ( 1 ) else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if ( 1 ) else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricGroup": "Cor;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_other_bottlenecks" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_branching_overhead" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * ( 100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_base_non_br" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" + }, { "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_info_core_coreipc" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", - "MetricName": "tma_info_core_ipmispredict" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "100 * ( 1 - ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) / ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) if ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) < ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) else 1 ) if ( 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if ( 1 ) else 0 ) > 0.5 else 0", + "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_core_bound_likely" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" }, { "BriefDescription": "Instruction per taken branch", @@ -927,10 +1124,521 @@ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_info_inst_mix_iptb" }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx512" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / ROB_MISC_EVENTS.PAUSE_INST", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ippause" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipswpf" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY )", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_ipassist" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@ )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=0x1@", + "MetricGroup": "Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", + "MetricGroup": "DSBmiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ + 2", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipdsb_miss_ret" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) / ( ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) + ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) ) ) )", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_dsb_misses" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_ic_misses" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "( INST_RETIRED.ANY ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * BR_MISP_EXEC.INDIRECT )", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( 100 * ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )", + "MetricGroup": "BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "( BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.COND - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki_load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Mem;Backend;CacheMisses;TopdownL1;tma_L1_group", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1000 * L2_LINES_OUT.SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 112 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cha@UNC_CHA_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) if ( 1 ) else CORE_POWER.LVL0_TURBO_LICENSE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license0_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) if ( 1 ) else CORE_POWER.LVL1_TURBO_LICENSE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license1_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) if ( 1 ) else CORE_POWER.LVL2_TURBO_LICENSE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license2_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( ( cha@UNC_CHA_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( ( 1000000000 ) * ( UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS ) / imc_0@event\\=0x0@ )", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_pmm_read_latency" + }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( 1000000000 ) * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / imc_0@event\\=0x0@", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_dram_read_latency" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_RPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_read_bw" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_WPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_write_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_read_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_write_bw" + }, + { + "BriefDescription": "Total package Power in Watts", + "MetricExpr": "( FREERUN_PKG_ENERGY_STATUS * ( 61 ) + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( ( ( duration_time * 1000 ) / 1000 ) * ( 1000000 ) )", + "MetricGroup": "Power;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" } ] \ No newline at end of file diff --git a/HSX/metrics/haswellx_metrics.json b/HSX/metrics/haswellx_metrics.json index 145f393b..d0dad8e1 100644 --- a/HSX/metrics/haswellx_metrics.json +++ b/HSX/metrics/haswellx_metrics.json @@ -1,10 +1,12 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture - V", - "DatePublished": "05/12/2023", - "Version": "", - "Legend": "" + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture0", + "DatePublished": "01/17/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" }, "Metrics": [ { @@ -854,20 +856,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1;PGO" }, { @@ -891,20 +884,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 4 ) * ( min( a , b ) ) / ( ( 4 ) * ( ( c / 2 ) if smt_on else ( a ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 4 ) * ( min( a , b ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( a ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Frontend;TmaL2" }, { @@ -928,8 +912,8 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;IcMiss" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;IcMiss" }, { "MetricName": "ITLB_Misses", @@ -953,11 +937,11 @@ } ], "Constants": [], - "Formula": "100 * ( ( 14 * a + b ) / ( c ) )", + "Formula": "100 * ( ( ( 14 * a + b ) ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" }, { "MetricName": "Branch_Resteers", @@ -988,19 +972,19 @@ "Formula": "100 * ( ( 12 ) * ( a + b + c ) / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { - "MetricName": "DSB_Switches", - "LegacyName": "metric_TMA_....DSB_Switches(%)", + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Name": "IDQ.MS_SWITCHES", "Alias": "a" }, { @@ -1009,18 +993,18 @@ } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DSBmiss;FetchLat" + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq" }, { "MetricName": "LCP", "LegacyName": "metric_TMA_....LCP(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "UnitOfMeasure": "percent", "Events": [ { @@ -1036,19 +1020,19 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { - "MetricName": "MS_Switches", - "LegacyName": "metric_TMA_....MS_Switches(%)", + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.MS_SWITCHES", + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "Alias": "a" }, { @@ -1057,11 +1041,11 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "FetchLat;MicroSeq" + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat" }, { "MetricName": "Fetch_Bandwidth", @@ -1088,20 +1072,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( 4 ) * ( min( c , d ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( 4 ) * ( min( c , d ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P & #HighIPC; $issueFB", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "Threshold": "> 20; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2" }, { @@ -1129,20 +1104,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, { @@ -1170,20 +1136,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSB;FetchBW" }, { @@ -1218,20 +1175,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1275,20 +1223,11 @@ "Alias": "h" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( g / 2 ) if smt_on else ( h ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( g / 2 ) if ( 1 ) else ( h ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueBM", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts;TmaL2" }, { @@ -1332,20 +1271,11 @@ "Alias": "h" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueMC; $issueSyncxn", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears;TmaL2" }, { @@ -1384,20 +1314,11 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if smt_on else g ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 20", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1473,20 +1394,11 @@ "Alias": "p" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( min( a , b ) ) + c ) / ( ( ( min( a , d ) ) + ( e - ( f if ( ( g / ( a ) ) > 1.8 ) else h ) ) / 2 - ( i if ( ( ( 4 ) * ( min( a , j ) ) / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( a ) ) ) ) > 0.1 ) else 0 ) + c ) if smt_on else ( ( min( a , d ) ) + e - ( f if ( ( g / ( a ) ) > 1.8 ) else h ) - ( i if ( ( ( 4 ) * ( min( a , j ) ) / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( a ) ) ) ) > 0.1 ) else 0 ) + c ) ) ) * ( 1 - ( ( l / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( a ) ) ) ) + ( ( m - ( n ) + ( 4 ) * ( ( o / 2 ) if smt_on else p ) ) / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( a ) ) ) ) + ( ( n ) / ( ( 4 ) * ( ( k / 2 ) if smt_on else ( a ) ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( min( a , b ) ) + c ) / ( ( ( min( a , d ) ) + ( e - ( f if ( ( g / ( a ) ) > 1.8 ) else h ) ) / 2 - ( i if ( ( ( 4 ) * ( min( a , j ) ) / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( a ) ) ) ) > 0.1 ) else 0 ) + c ) if ( 1 ) else ( ( min( a , d ) ) + e - ( f if ( ( g / ( a ) ) > 1.8 ) else h ) - ( i if ( ( ( 4 ) * ( min( a , j ) ) / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( a ) ) ) ) > 0.1 ) else 0 ) + c ) ) ) * ( 1 - ( ( l / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( a ) ) ) ) + ( ( m - ( n ) + ( 4 ) * ( ( o / 2 ) if ( 1 ) else p ) ) / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( a ) ) ) ) + ( ( n ) / ( ( 4 ) * ( ( k / 2 ) if ( 1 ) else ( a ) ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2" }, { @@ -1514,8 +1426,8 @@ "Formula": "100 * ( max( ( ( min( a , b ) ) - c ) / ( a ) , 0 ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueL1; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "DTLB_Load", @@ -1542,7 +1454,7 @@ "Formula": "100 * ( ( ( 8 ) * a + b ) / ( c ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1563,10 +1475,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1595,10 +1507,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / b ) * ( min( c , d ) ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / b ) * ( min( c , d ) ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueRFO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore" }, { @@ -1631,10 +1543,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1658,7 +1570,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1694,7 +1606,7 @@ "Formula": "100 * ( ( a / ( b + c ) ) * d / ( e ) )", "Category": "TMA", "Threshold": "> 30; $issueBW; $issueSL; $issueSmSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW" }, { @@ -1722,8 +1634,8 @@ "Formula": "100 * ( ( a - b ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "L3_Bound", @@ -1754,8 +1666,8 @@ "Formula": "100 * ( ( a / ( a + ( 7 ) * b ) ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "Contested_Accesses", @@ -1811,10 +1723,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 60 ) * ( a * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) + ( 43 ) * ( f * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 60 ) * ( a * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) + ( 43 ) * ( f * ( 1 + b / ( ( c + d + e + a + f ) + g + h + i + j ) ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -1871,10 +1783,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 43 ) * ( a * ( 1 + b / ( ( c + d + a + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 43 ) * ( a * ( 1 + b / ( ( c + d + a + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Snoop" }, { @@ -1882,7 +1794,7 @@ "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", "UnitOfMeasure": "percent", "Events": [ { @@ -1931,10 +1843,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 41 ) * ( a * ( 1 + b / ( ( c + a + d + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 41 ) * ( a * ( 1 + b / ( ( c + a + d + e + f ) + g + h + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat" }, { @@ -1958,20 +1870,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a / 2 ) if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a / 2 ) if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 30 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2000,10 +1903,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 1 - ( a / ( a + ( 7 ) * b ) ) ) * c / ( d ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 1 - ( a / ( a + ( 7 ) * b ) ) ) * c / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2011,7 +1914,7 @@ "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2027,7 +1930,7 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2035,7 +1938,7 @@ "LegacyName": "metric_TMA_......MEM_Latency(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2055,12 +1958,12 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { - "MetricName": "Local_DRAM", - "LegacyName": "metric_TMA_........Local_DRAM(%)", + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", @@ -2112,18 +2015,18 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + a + h + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + a + h + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server" }, { - "MetricName": "Remote_DRAM", - "LegacyName": "metric_TMA_........Remote_DRAM(%)", + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2172,10 +2075,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 310 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + a + i + j ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 310 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + a + i + j ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server;Snoop" }, { @@ -2183,7 +2086,7 @@ "LegacyName": "metric_TMA_........Remote_Cache(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2232,10 +2135,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) + ( 180 ) * ( j * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) ) / ( k ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 200 ) * ( a * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) + ( 180 ) * ( j * ( 1 + b / ( ( c + d + e + f + g ) + h + i + a + j ) ) ) ) / ( k ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Server;Snoop" }, { @@ -2259,7 +2162,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2292,10 +2195,10 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a * ( 9 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "Formula": "100 * ( min( ( ( ( a * ( 9 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { @@ -2320,10 +2223,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 200 ) * a + ( 60 ) * b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 200 ) * a + ( 60 ) * b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -2347,20 +2250,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 2 * a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( 2 * a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2385,10 +2279,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 8 ) * a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 8 ) * a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2464,20 +2358,11 @@ "Alias": "p" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if smt_on else g ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) - ( ( ( ( min( c , h ) ) + i ) / ( ( ( min( c , j ) ) + ( k - ( l if ( ( m / ( c ) ) > 1.8 ) else n ) ) / 2 - ( o if ( ( ( 4 ) * ( min( c , p ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) > 0.1 ) else 0 ) + i ) if smt_on else ( ( min( c , j ) ) + k - ( l if ( ( m / ( c ) ) > 1.8 ) else n ) - ( o if ( ( ( 4 ) * ( min( c , p ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) > 0.1 ) else 0 ) + i ) ) ) * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if smt_on else g ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) - ( ( ( ( min( c , h ) ) + i ) / ( ( ( min( c , j ) ) + ( k - ( l if ( ( m / ( c ) ) > 1.8 ) else n ) ) / 2 - ( o if ( ( ( 4 ) * ( min( c , p ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) > 0.1 ) else 0 ) + i ) if ( 1 ) else ( ( min( c , j ) ) + k - ( l if ( ( m / ( c ) ) > 1.8 ) else n ) - ( o if ( ( ( 4 ) * ( min( c , p ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) > 0.1 ) else 0 ) + i ) ) ) * ( 1 - ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( d - ( e ) + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) + ( ( e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2;Compute" }, { @@ -2501,20 +2386,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 10 * a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( 10 * a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2570,20 +2446,11 @@ "Alias": "k" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( ( min( a , b ) ) + ( c - ( d if ( ( e / ( a ) ) > 1.8 ) else f ) ) / 2 - ( g if ( ( ( 4 ) * ( min( a , h ) ) / ( ( 4 ) * ( ( i / 2 ) if smt_on else ( a ) ) ) ) > 0.1 ) else 0 ) + j ) if smt_on else ( ( min( a , b ) ) + c - ( d if ( ( e / ( a ) ) > 1.8 ) else f ) - ( g if ( ( ( 4 ) * ( min( a , h ) ) / ( ( 4 ) * ( ( i / 2 ) if smt_on else ( a ) ) ) ) > 0.1 ) else 0 ) + j ) ) - j - ( min( a , k ) ) ) / ( a ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( ( min( a , b ) ) + ( c - ( d if ( ( e / ( a ) ) > 1.8 ) else f ) ) / 2 - ( g if ( ( ( 4 ) * ( min( a , h ) ) / ( ( 4 ) * ( ( i / 2 ) if ( 1 ) else ( a ) ) ) ) > 0.1 ) else 0 ) + j ) if ( 1 ) else ( ( min( a , b ) ) + c - ( d if ( ( e / ( a ) ) > 1.8 ) else f ) - ( g if ( ( ( 4 ) * ( min( a , h ) ) / ( ( 4 ) * ( ( i / 2 ) if ( 1 ) else ( a ) ) ) ) > 0.1 ) else 0 ) + j ) ) - j - ( min( a , k ) ) ) / ( a ) )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2619,20 +2486,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / 2 if smt_on else ( ( min( b , c ) ) - ( d if ( ( ( 4 ) * ( min( b , e ) ) / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( b ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( f / 2 ) if smt_on else ( b ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / 2 if ( 1 ) else ( ( min( b , c ) ) - ( d if ( ( ( 4 ) * ( min( b , e ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( b ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( f / 2 ) if ( 1 ) else ( b ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2660,20 +2518,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else ( a - b ) ) / ( ( c / 2 ) if smt_on else ( d ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else ( a - b ) ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueL1", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2701,20 +2550,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else ( a - b ) ) / ( ( c / 2 ) if smt_on else ( d ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else ( a - b ) ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) )", "Category": "TMA", "Threshold": "> 15 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2738,20 +2578,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a / 2 ) if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a / 2 ) if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", - "Threshold": "> 70 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2787,20 +2618,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2824,20 +2646,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -2861,20 +2674,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2898,20 +2702,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2919,7 +2714,7 @@ "LegacyName": "metric_TMA_..........Port_6(%)", "ParentCategory": "ALU_Op_Utilization", "Level": 6, - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "UnitOfMeasure": "percent", "Events": [ { @@ -2935,20 +2730,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2984,20 +2770,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3021,20 +2798,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3058,20 +2826,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3095,20 +2854,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3132,20 +2882,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3169,20 +2910,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3205,20 +2937,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "(> 70 | Heavy_Operations)", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -3226,7 +2949,7 @@ "LegacyName": "metric_TMA_..Light_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3250,56 +2973,19 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( ( a ) / d ) * e / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( ( a ) / d ) * e / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, - { - "MetricName": "X87_Use", - "LegacyName": "metric_TMA_......X87_Use(%)", - "ParentCategory": "Ports_Utilization", - "Level": 4, - "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "UnitOfMeasure": "percent", - "Events": [ - { - "Name": "INST_RETIRED.X87", - "Alias": "a" - }, - { - "Name": "UOPS_RETIRED.RETIRE_SLOTS", - "Alias": "b" - }, - { - "Name": "INST_RETIRED.ANY", - "Alias": "c" - } - ], - "Constants": [], - "Formula": "100 * ( a * ( ( b ) / c ) / ( b ) )", - "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Compute" - }, { "MetricName": "Heavy_Operations", "LegacyName": "metric_TMA_..Heavy_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3323,20 +3009,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) )", "Category": "TMA", "Threshold": "> 10", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -3368,20 +3045,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC; $issueMS", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MicroSeq" }, { @@ -3405,20 +3073,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( min( ( ( 100 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) , ( 1 ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( ( 66 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3454,21 +3113,146 @@ "Alias": "f" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( min( ( ( 66 ) * f / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) , ( 1.0 ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "INST_RETIRED.ANY", + "Alias": "a" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" } ], - "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) - ( min( ( ( 100 ) * f / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) , ( 1 ) ) ) ) )", + "Constants": [], + "Formula": "a / ( b )", "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( 4 ) * ( ( a / 2 ) if ( 1 ) else ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" }, { "MetricName": "Info_Core_CoreIPC", @@ -3490,27 +3274,64 @@ "Alias": "c" } ], - "Constants": [ + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "UOPS_EXECUTED.CORE", + "Alias": "a" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "UOPS_EXECUTED.CORE:c1", + "Alias": "b" } ], - "Formula": "a / ( ( b / 2 ) if smt_on else ( c ) )", + "Constants": [], + "Formula": "( a / 2 / ( ( b / 2 ) if ( 1 ) else b ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else b )", "Category": "TMA", "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Ret;SMT;TmaL1" + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" }, { - "MetricName": "Info_Inst_Mix_IpTB", - "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", "Level": 1, - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a / 2 ) if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", "UnitOfMeasure": "", "Events": [ { @@ -3518,22 +3339,22 @@ "Alias": "a" }, { - "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", "Alias": "b" } ], "Constants": [], "Formula": "a / b", "Category": "TMA", - "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + "Threshold": "< 3", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" }, { - "MetricName": "Info_Bad_Spec_IpMispredict", - "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", "Level": 1, - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", "UnitOfMeasure": "", "Events": [ { @@ -3541,39 +3362,997 @@ "Alias": "a" }, { - "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Name": "MEM_UOPS_RETIRED.ALL_STORES", "Alias": "b" } ], "Constants": [], "Formula": "a / b", "Category": "TMA", - "Threshold": "< 200", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Bad;BadSpec;BrMispredicts" + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" }, { - "MetricName": "Info_Memory_L2MPKI", - "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", "Level": 1, - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", "UnitOfMeasure": "", "Events": [ { - "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Name": "INST_RETIRED.ANY", "Alias": "a" }, { - "Name": "INST_RETIRED.ANY", + "Name": "BR_INST_RETIRED.ALL_BRANCHES", "Alias": "b" } ], "Constants": [], - "Formula": "1000 * a / b", + "Formula": "a / b", "Category": "TMA", - "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Mem;Backend;CacheMisses" + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "LSD.UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "c" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( ( a + b + c + d ) )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "BR_MISP_EXEC.INDIRECT", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a ) / ( ( ( b ) / c ) * d )", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_DURATION", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_DURATION", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_DURATION", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( ( d / 2 ) if ( 1 ) else ( e ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 8 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / ( b / 2 ) if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182", + "Alias": "a" + }, + { + "Name": "UNC_C_TOR_INSERTS.MISS_OPCODE:opc=0x182", + "Alias": "b" + }, + { + "Name": "UNC_C_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182", + "Alias": "a" + }, + { + "Name": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_C_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" } ] } \ No newline at end of file diff --git a/HSX/metrics/perf/haswellx_metrics_perf.json b/HSX/metrics/perf/haswellx_metrics_perf.json index edf7e6c2..c723f5ff 100644 --- a/HSX/metrics/perf/haswellx_metrics_perf.json +++ b/HSX/metrics/perf/haswellx_metrics_perf.json @@ -239,14 +239,14 @@ }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "MetricExpr": "( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "ScaleUnit": "100%" @@ -254,14 +254,14 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", "MetricExpr": "( ICACHE.IFDATA_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "( ( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricExpr": "( ( ( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%" }, @@ -273,78 +273,78 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "MetricExpr": "( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_mite", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "MetricExpr": "( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_dsb", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "MetricExpr": "( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "MetricExpr": "( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) + RESOURCE_STALLS.SB ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricExpr": "( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) + RESOURCE_STALLS.SB ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if ( 1 ) else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "ScaleUnit": "100%" @@ -352,7 +352,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", "MetricExpr": "( max( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) - CYCLE_ACTIVITY.STALLS_L1D_PENDING ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "ScaleUnit": "100%" }, @@ -365,21 +365,21 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "MetricExpr": "( min( ( ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_lock_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "ScaleUnit": "100%" @@ -401,61 +401,61 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", "MetricExpr": "( ( CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", "MetricExpr": "( ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "MetricExpr": "( min( ( ( ( 60 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 60 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "MetricExpr": "( min( ( ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 43 ) * ( MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_data_sharing", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "MetricExpr": "( min( ( ( 41 ) * ( MEM_LOAD_UOPS_RETIRED.L3_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( 41 ) * ( MEM_LOAD_UOPS_RETIRED.L3_HIT * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", - "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_sq_full", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "MetricExpr": "( min( ( ( 1 - ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 1 - ( MEM_LOAD_UOPS_RETIRED.L3_HIT / ( MEM_LOAD_UOPS_RETIRED.L3_HIT + ( 7 ) * MEM_LOAD_UOPS_RETIRED.L3_MISS ) ) ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_latency", @@ -463,21 +463,21 @@ }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "MetricExpr": "( min( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", + "MetricName": "tma_local_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( 310 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( 310 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", + "MetricName": "tma_remote_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 180 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 200 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) + ( 180 ) * ( MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / ( ( MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS ) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_remote_cache", "ScaleUnit": "100%" @@ -491,229 +491,506 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "MetricExpr": "( ( ( L2_RQSTS.RFO_HIT * ( 9 ) * ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( min( ( ( ( L2_RQSTS.RFO_HIT * ( 9 ) * ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "MetricExpr": "( min( ( ( ( 200 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + ( 60 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 200 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + ( 60 ) * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_false_sharing", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", - "MetricExpr": "( 2 * MEM_UOPS_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( 2 * MEM_UOPS_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_split_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", - "MetricExpr": "( min( ( ( ( 8 ) * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 8 ) * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "MetricExpr": "( ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) + RESOURCE_STALLS.SB ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricExpr": "( ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) + RESOURCE_STALLS.SB ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if ( 1 ) else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) ) * ( 1 - ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", - "MetricExpr": "( 10 * ARITH.DIVIDER_UOPS / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( 10 * ARITH.DIVIDER_UOPS / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "MetricExpr": "( ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) - RESOURCE_STALLS.SB - ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( ( ( ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / 2 - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) if ( 1 ) else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if ( ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) > 1.8 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) + RESOURCE_STALLS.SB ) ) - RESOURCE_STALLS.SB - ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_ports_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ ) / 2 if #SMT_on else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ ) / 2 if ( 1 ) else ( ( min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE ) ) - ( RS_EVENTS.EMPTY_CYCLES if ( ( ( 4 ) * ( min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) > 0.1 ) else 0 ) ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) / 2 if #SMT_on else ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) / 2 if ( 1 ) else ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / 2 if #SMT_on else ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / 2 if ( 1 ) else ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_3m", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_5", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_4", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_7", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", - "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_light_operations", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "MetricExpr": "( INST_RETIRED.X87 * ( ( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_x87_use", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_microcode_sequencer", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", - "MetricExpr": "( min( ( ( 100 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 66 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_assists", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 100 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 66 ) * OTHER_ASSISTS.ANY_WB_ASSIST / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_cisc", "ScaleUnit": "100%" }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, { "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_info_core_coreipc" }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ ) ) if ( 1 ) else UOPS_EXECUTED.CORE / ( ( cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ )", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" + }, { "BriefDescription": "Instruction per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_info_inst_mix_iptb" }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", "MetricName": "tma_info_bad_spec_ipmispredict" }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "( INST_RETIRED.ANY ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * BR_MISP_EXEC.INDIRECT )", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB )", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Mem;Backend;CacheMisses;TopdownL1;tma_L1_group", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 8 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cbox@UNC_C_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( ( cbox@UNC_C_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Total package Power in Watts", + "MetricExpr": "( FREERUN_PKG_ENERGY_STATUS * ( 61 ) + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( ( ( duration_time * 1000 ) / 1000 ) * ( 1000000 ) )", + "MetricGroup": "Power;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox@UNC_C_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" } ] \ No newline at end of file diff --git a/ICX/metrics/icelakex_metrics.json b/ICX/metrics/icelakex_metrics.json index 80f0a155..fe4a6c9c 100644 --- a/ICX/metrics/icelakex_metrics.json +++ b/ICX/metrics/icelakex_metrics.json @@ -1,10 +1,12 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V", - "DatePublished": "11/09/2023", - "Version": "", - "Legend": "" + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture0", + "DatePublished": "01/17/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" }, "Metrics": [ { @@ -1217,7 +1219,7 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "ICACHE_16B.IFDATA_STALL", + "Name": "ICACHE_DATA.STALLS", "Alias": "a" }, { @@ -1230,7 +1232,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;IcMiss" + "MetricGroup": "BigFootprint;FetchLat;IcMiss" }, { "MetricName": "ITLB_Misses", @@ -1241,7 +1243,7 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "ICACHE_64B.IFTAG_STALL", + "Name": "ICACHE_TAG.STALLS", "Alias": "a" }, { @@ -1254,7 +1256,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB" + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" }, { "MetricName": "Branch_Resteers", @@ -1353,7 +1355,7 @@ "LegacyName": "metric_TMA_......Unknown_Branches(%)", "ParentCategory": "Branch_Resteers", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "UnitOfMeasure": "percent", "Events": [ { @@ -1370,18 +1372,18 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat" + "MetricGroup": "BigFootprint;FetchLat" }, { - "MetricName": "DSB_Switches", - "LegacyName": "metric_TMA_....DSB_Switches(%)", + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Name": "IDQ.MS_SWITCHES", "Alias": "a" }, { @@ -1390,22 +1392,22 @@ } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( ( 3 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueFB", + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DSBmiss;FetchLat" + "MetricGroup": "FetchLat;MicroSeq" }, { "MetricName": "LCP", "LegacyName": "metric_TMA_....LCP(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "ILD_STALL.LCP", + "Name": "DECODE.LCP", "Alias": "a" }, { @@ -1421,15 +1423,15 @@ "MetricGroup": "FetchLat" }, { - "MetricName": "MS_Switches", - "LegacyName": "metric_TMA_....MS_Switches(%)", + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.MS_SWITCHES", + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "Alias": "a" }, { @@ -1438,11 +1440,11 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 3 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "Threshold": "> 5 & P; $issueFB", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "FetchLat;MicroSeq" + "MetricGroup": "DSBmiss;FetchLat" }, { "MetricName": "Fetch_Bandwidth", @@ -1484,7 +1486,7 @@ "Constants": [], "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * g - e ) / ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P & #HighIPC; $issueFB", + "Threshold": "> 20; $issueFB", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2" }, @@ -1507,10 +1509,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a - b ) / ( c ) / 2 )", + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -1535,10 +1541,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a - b ) / ( c ) / 2 )", + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P; $issueD0", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -1591,10 +1601,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a - b ) / ( c ) / 2 )", + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 15 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -1632,7 +1646,7 @@ "Alias": "f" }, { - "Name": "INT_MISC.RECOVERY_CYCLES:c1:e1", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "g" } ], @@ -1684,7 +1698,7 @@ "Alias": "h" }, { - "Name": "INT_MISC.RECOVERY_CYCLES:c1:e1", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "i" } ], @@ -1695,6 +1709,58 @@ "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts;TmaL2" }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( ( a / ( a + b ) ) * ( max( 1 - ( ( c / ( c + d + e + f ) - g / ( h ) ) + ( f / ( c + d + e + f ) + ( ( 5 ) * i ) / ( h ) ) + ( e / ( c + d + e + f ) ) ) , 0 ) ) ) * ( 1 - a / ( i - b ) ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, { "MetricName": "Machine_Clears", "LegacyName": "metric_TMA_..Machine_Clears(%)", @@ -1728,7 +1794,7 @@ "Alias": "f" }, { - "Name": "INT_MISC.RECOVERY_CYCLES:c1:e1", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "g" }, { @@ -1747,6 +1813,62 @@ "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears;TmaL2" }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( ( h / ( h + i ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( 1 - j / i ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Machine_Clears" + }, { "MetricName": "Backend_Bound", "LegacyName": "metric_TMA_Backend_Bound(%)", @@ -1771,7 +1893,7 @@ "Alias": "d" }, { - "Name": "INT_MISC.RECOVERY_CYCLES:c1:e1", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "e" }, { @@ -1831,7 +1953,7 @@ "Alias": "i" }, { - "Name": "INT_MISC.RECOVERY_CYCLES:c1:e1", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "j" }, { @@ -1872,7 +1994,7 @@ "Category": "TMA", "Threshold": "> 10 & P; $issueL1; $issueMC", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "DTLB_Load", @@ -1988,7 +2110,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2028,7 +2150,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueRFO", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2064,7 +2186,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2160,7 +2282,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "L3_Bound", @@ -2188,7 +2310,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "Contested_Accesses", @@ -2241,7 +2363,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 48 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 48 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2298,7 +2420,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2309,7 +2431,7 @@ "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", "UnitOfMeasure": "percent", "Events": [ { @@ -2343,7 +2465,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e ) * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat; ~overlap", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2439,7 +2561,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) / ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) + ( 25 * ( ( m * ( 1 + ( f / g ) ) ) ) + 33 * ( ( n * ( 1 + ( f / g ) ) ) ) ) ) ) ) ) * ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) ) if ( ( 1000000 ) * ( n + m ) > g ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) / ( ( 19 * ( i * ( 1 + ( f / g ) ) ) + 10 * ( ( j * ( 1 + ( f / g ) ) ) + ( k * ( 1 + ( f / g ) ) ) + ( l * ( 1 + ( f / g ) ) ) ) ) + ( 25 * ( m * ( 1 + ( f / g ) ) ) + 33 * ( n * ( 1 + ( f / g ) ) ) ) ) ) ) * ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) ) if ( ( 1000000 ) * ( n + m ) > g ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2450,7 +2572,7 @@ "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2474,7 +2596,7 @@ "LegacyName": "metric_TMA_......MEM_Latency(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2498,8 +2620,8 @@ "MetricGroup": "MemoryLat;Offcore" }, { - "MetricName": "Local_DRAM", - "LegacyName": "metric_TMA_........Local_DRAM(%)", + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", @@ -2536,18 +2658,18 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 66.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 66.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Server" }, { - "MetricName": "Remote_DRAM", - "LegacyName": "metric_TMA_........Remote_DRAM(%)", + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2581,7 +2703,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 131 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 131 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2592,7 +2714,7 @@ "LegacyName": "metric_TMA_........Remote_Cache(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2630,7 +2752,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2702,7 +2824,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( ( 1 - ( ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( ( g * ( 1 + ( b / c ) ) ) ) + 33 * ( ( h * ( 1 + ( b / c ) ) ) ) ) ) ) ) ) * ( i / ( j ) + ( ( k - l ) / ( j ) ) - ( ( ( m * ( 1 + ( b / c ) ) ) / ( ( m * ( 1 + ( b / c ) ) ) + n ) ) * ( ( k - l ) / ( j ) ) ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 1 - ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( g * ( 1 + ( b / c ) ) ) + 33 * ( h * ( 1 + ( b / c ) ) ) ) ) ) ) * ( i / ( j ) + ( ( k - l ) / ( j ) ) - ( ( ( m * ( 1 + ( b / c ) ) ) / ( ( m * ( 1 + ( b / c ) ) ) + n ) ) * ( ( k - l ) / ( j ) ) ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2762,7 +2884,7 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "Formula": "100 * ( min( ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2799,7 +2921,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( 48 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * e / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 48 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2820,10 +2942,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSpSt", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2847,7 +2973,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 9 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 9 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSmSt", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2872,10 +2998,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 7 ) * a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueTLB", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2900,10 +3030,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( min( ( ( ( 7 ) * a + b ) / ( c ) ) , ( 1 ) ) ) - ( b / ( c ) ) )", + "Formula": "100 * ( min( ( ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) - ( min( ( b / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2924,10 +3058,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( a / ( b if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2958,7 +3096,7 @@ "Alias": "d" }, { - "Name": "INT_MISC.RECOVERY_CYCLES:c1:e1", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "e" }, { @@ -3017,6 +3155,54 @@ "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueSO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC_RETIRED.PAUSE_INST", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 37 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, { "MetricName": "Ports_Utilization", "LegacyName": "metric_TMA_....Ports_Utilization(%)", @@ -3030,52 +3216,64 @@ "Alias": "a" }, { - "Name": "RESOURCE_STALLS.SCOREBOARD", + "Name": "PERF_METRICS.BACKEND_BOUND", "Alias": "b" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "c" }, { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "d" }, { - "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Name": "PERF_METRICS.RETIRING", "Alias": "e" }, { - "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Name": "INT_MISC.CLEARS_COUNT", "Alias": "f" }, { - "Name": "PERF_METRICS.RETIRING", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "g" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "Alias": "h" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "i" }, { - "Name": "PERF_METRICS.BACKEND_BOUND", + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", "Alias": "j" }, { - "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", "Alias": "k" }, { - "Name": "ARITH.DIVIDER_ACTIVE", + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", "Alias": "l" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "o" } ], "Constants": [], - "Formula": "100 * ( ( a + ( b / ( c ) ) * ( d - e ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) if ( l < ( d - e ) ) else ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )", + "Formula": "100 * ( ( ( ( a + ( max( 0 , ( b / ( c + d + e + b ) + ( ( 5 ) * f ) / ( g ) ) - ( ( ( h + i ) / ( j + ( k + ( e / ( c + d + e + b ) ) * l ) + i ) ) * ( b / ( c + d + e + b ) + ( ( 5 ) * f ) / ( g ) ) ) ) ) * m ) / ( n ) * ( j - h ) / ( n ) ) * ( n ) + ( k + ( e / ( c + d + e + b ) ) * l ) ) / ( n ) if ( o < ( j - h ) ) else ( k + ( e / ( c + d + e + b ) ) * l ) / ( n ) )", "Category": "TMA", "Threshold": "> 15 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3094,100 +3292,84 @@ "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "PERF_METRICS.BACKEND_BOUND", "Alias": "b" }, { - "Name": "RESOURCE_STALLS.SCOREBOARD", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "c" }, { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "d" }, { - "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Name": "PERF_METRICS.RETIRING", "Alias": "e" - } - ], - "Constants": [], - "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) * ( d - e ) / ( b ) )", - "Category": "TMA", - "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "PortsUtil" - }, - { - "MetricName": "Serializing_Operation", - "LegacyName": "metric_TMA_........Serializing_Operation(%)", - "ParentCategory": "Ports_Utilized_0", - "Level": 5, - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", - "UnitOfMeasure": "percent", - "Events": [ + }, { - "Name": "RESOURCE_STALLS.SCOREBOARD", - "Alias": "a" + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "f" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "b" - } - ], - "Constants": [], - "Formula": "100 * ( a / ( b ) )", - "Category": "TMA", - "Threshold": "> 10 & P; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "PortsUtil" - }, - { - "MetricName": "Slow_Pause", - "LegacyName": "metric_TMA_..........Slow_Pause(%)", - "ParentCategory": "Serializing_Operation", - "Level": 6, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", - "UnitOfMeasure": "percent", - "Events": [ + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, { - "Name": "MISC_RETIRED.PAUSE_INST", - "Alias": "a" + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "i" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "m" }, { "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "b" + "Alias": "n" } ], "Constants": [], - "Formula": "100 * ( 37 * a / ( b ) )", + "Formula": "100 * ( ( a + ( max( 0 , ( b / ( c + d + e + b ) + ( ( 5 ) * f ) / ( g ) ) - ( ( ( h + i ) / ( j + ( k + ( e / ( c + d + e + b ) ) * l ) + i ) ) * ( b / ( c + d + e + b ) + ( ( 5 ) * f ) / ( g ) ) ) ) ) * m ) / ( n ) * ( j - h ) / ( n ) )", "Category": "TMA", - "Threshold": "> 5 & P", + "Threshold": "> 20 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "MetricGroup": "PortsUtil" }, { "MetricName": "Mixing_Vectors", "LegacyName": "metric_TMA_........Mixing_Vectors(%)", "ParentCategory": "Ports_Utilized_0", "Level": 5, - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", "UnitOfMeasure": "percent", "Events": [ - { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "a" - }, { "Name": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "Alias": "b" + "Alias": "a" }, { "Name": "UOPS_ISSUED.ANY", - "Alias": "c" + "Alias": "b" } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) * b / c ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( a / b ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5; $issueMV", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3261,7 +3443,7 @@ "Constants": [], "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 70 & P", + "Threshold": "> 40 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, @@ -3292,12 +3474,16 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" } ], "Constants": [], - "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( e ) ) )", + "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( e if ( 1 ) else ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 60", + "Threshold": "> 40", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, @@ -3316,10 +3502,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3340,10 +3530,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3364,10 +3558,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3378,7 +3576,7 @@ "LegacyName": "metric_TMA_..........Port_6(%)", "ParentCategory": "ALU_Op_Utilization", "Level": 6, - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "UnitOfMeasure": "percent", "Events": [ { @@ -3388,10 +3586,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3412,10 +3614,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( 2 * ( b ) ) )", + "Formula": "100 * ( a / ( 2 * ( b if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 60", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3440,10 +3646,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a + b ) / ( 4 * ( c ) ) )", + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if ( 1 ) else ( d ) ) ) )", "Category": "TMA", "Threshold": "> 60", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3485,7 +3695,7 @@ "LegacyName": "metric_TMA_..Light_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3505,7 +3715,7 @@ "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "e" }, { @@ -3517,20 +3727,24 @@ "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" } ], "Constants": [], - "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) )", + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) )", "Category": "TMA", "Threshold": "> 60", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3582,7 +3796,7 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) + ( min( ( ( i ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) , ( 1 ) ) ) )", + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) + ( min( ( ( i ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) , ( 1.0 ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3702,7 +3916,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) / ( ( b / ( c + d + b + e ) ) * ( f ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a ) / ( ( b / ( c + d + b + e ) ) * ( f ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3746,7 +3960,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3790,7 +4004,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3834,7 +4048,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3845,7 +4059,7 @@ "LegacyName": "metric_TMA_....Memory_Operations(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", "UnitOfMeasure": "percent", "Events": [ { @@ -3865,7 +4079,7 @@ "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "e" }, { @@ -3877,28 +4091,32 @@ "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" }, { - "Name": "MEM_INST_RETIRED.ANY", + "Name": "IDQ.MITE_UOPS", "Alias": "k" }, { - "Name": "INST_RETIRED.ANY", + "Name": "MEM_INST_RETIRED.ANY", "Alias": "l" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "m" } ], "Constants": [], - "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) * k / l )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * l / m )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3929,7 +4147,7 @@ "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "e" }, { @@ -3941,35 +4159,39 @@ "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" }, { - "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Name": "IDQ.MITE_UOPS", "Alias": "k" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "l" } ], "Constants": [], - "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) * k / ( ( a / ( b + c + a + d ) ) * ( e ) ) )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * l / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "MetricGroup": "Branches;Pipeline" }, { - "MetricName": "Nop_Instructions", - "LegacyName": "metric_TMA_....Nop_Instructions(%)", + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "UnitOfMeasure": "percent", "Events": [ { @@ -3989,7 +4211,7 @@ "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "e" }, { @@ -4001,35 +4223,63 @@ "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" }, { - "Name": "INST_RETIRED.NOP", + "Name": "IDQ.MITE_UOPS", "Alias": "k" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "l" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "m" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "n" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "o" + }, + { + "Name": "MEM_INST_RETIRED.ANY", + "Alias": "p" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "q" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "r" } ], "Constants": [], - "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) * k / ( ( a / ( b + c + a + d ) ) * ( e ) ) )", + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * l / m ) + ( ( n ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) + ( min( ( ( o ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) , ( 1.0 ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * p / q ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", + "Threshold": "> 30 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { - "MetricName": "Other_Light_Ops", - "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", "ParentCategory": "Light_Operations", - "Level": 3, - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", "UnitOfMeasure": "percent", "Events": [ { @@ -4049,7 +4299,7 @@ "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "e" }, { @@ -4061,54 +4311,30 @@ "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" }, { - "Name": "UOPS_EXECUTED.X87", + "Name": "IDQ.MITE_UOPS", "Alias": "k" }, - { - "Name": "UOPS_EXECUTED.THREAD", - "Alias": "l" - }, - { - "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", - "Alias": "m" - }, - { - "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", - "Alias": "n" - }, - { - "Name": "MEM_INST_RETIRED.ANY", - "Alias": "o" - }, - { - "Name": "INST_RETIRED.ANY", - "Alias": "p" - }, - { - "Name": "BR_INST_RETIRED.ALL_BRANCHES", - "Alias": "q" - }, { "Name": "INST_RETIRED.NOP", - "Alias": "r" + "Alias": "l" } ], "Constants": [], - "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * k / l ) + ( ( m ) / ( ( a / ( b + c + a + d ) ) * ( e ) ) ) + ( min( ( ( n ) / ( ( a / ( b + c + a + d ) ) * ( e ) ) ) , ( 1 ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) * o / p ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) * q / ( ( a / ( b + c + a + d ) ) * ( e ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( e ) ) ) ) ) )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * l / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", "Category": "TMA", - "Threshold": "> 30 & P", + "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, @@ -4117,52 +4343,56 @@ "LegacyName": "metric_TMA_..Heavy_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { - "Name": "PERF_METRICS.RETIRING", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "a" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "IDQ.MS_UOPS", "Alias": "c" }, { - "Name": "PERF_METRICS.BACKEND_BOUND", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "PERF_METRICS.RETIRING", "Alias": "e" }, { - "Name": "UOPS_ISSUED.ANY", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "f" }, { - "Name": "IDQ.MS_UOPS", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "PERF_METRICS.BACKEND_BOUND", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" } ], "Constants": [], - "Formula": "100 * ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j )", + "Formula": "100 * ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k )", "Category": "TMA", "Threshold": "> 10", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -4177,48 +4407,52 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "PERF_METRICS.RETIRING", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "a" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "IDQ.MS_UOPS", "Alias": "c" }, { - "Name": "PERF_METRICS.BACKEND_BOUND", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "d" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "PERF_METRICS.RETIRING", "Alias": "e" }, { - "Name": "UOPS_ISSUED.ANY", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "f" }, { - "Name": "IDQ.MS_UOPS", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "g" }, { - "Name": "UOPS_DECODED.DEC0", + "Name": "PERF_METRICS.BACKEND_BOUND", "Alias": "h" }, { - "Name": "UOPS_DECODED.DEC0:c1", + "Name": "UOPS_DECODED.DEC0", "Alias": "i" }, { - "Name": "IDQ.MITE_UOPS", + "Name": "UOPS_DECODED.DEC0:c1", "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" } ], "Constants": [], - "Formula": "100 * ( ( ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) + ( a / ( b + c + a + d ) ) * ( h - i ) / j ) - ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) )", + "Formula": "100 * ( ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) - ( ( a / b ) * c / ( d ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueD0", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -4233,36 +4467,24 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "PERF_METRICS.RETIRING", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "a" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "IDQ.MS_UOPS", "Alias": "c" }, - { - "Name": "PERF_METRICS.BACKEND_BOUND", - "Alias": "d" - }, { "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "e" - }, - { - "Name": "UOPS_ISSUED.ANY", - "Alias": "f" - }, - { - "Name": "IDQ.MS_UOPS", - "Alias": "g" + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) )", + "Formula": "100 * ( ( a / b ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC; $issueMS", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -4286,12 +4508,36 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 100 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 34 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 34 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, { "MetricName": "CISC", "LegacyName": "metric_TMA_......CISC(%)", @@ -4301,136 +4547,4890 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "PERF_METRICS.RETIRING", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "a" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "IDQ.MS_UOPS", "Alias": "c" }, - { - "Name": "PERF_METRICS.BACKEND_BOUND", - "Alias": "d" - }, { "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "e" - }, - { - "Name": "UOPS_ISSUED.ANY", - "Alias": "f" - }, - { - "Name": "IDQ.MS_UOPS", - "Alias": "g" + "Alias": "d" }, { "Name": "ASSISTS.ANY", - "Alias": "h" + "Alias": "e" } ], "Constants": [], - "Formula": "100 * ( max( 0 , ( ( ( ( a / ( b + c + a + d ) ) * ( e ) ) / f ) * g / ( e ) ) - ( min( ( ( 100 ) * h / ( e ) ) , ( 1 ) ) ) ) )", + "Formula": "100 * ( max( 0 , ( ( a / b ) * c / ( d ) ) - ( min( ( ( 34 ) * e / ( d ) ) , ( 1.0 ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { - "MetricName": "Info_Core_CoreIPC", - "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "MetricName": "Info_Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Info_Bottleneck_Mispredictions", "Level": 1, - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" - } - ], - "Constants": [], - "Formula": "a / ( b )", - "Category": "TMA", - "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Ret;SMT;TmaL1" - }, - { - "MetricName": "Info_Core_IpMispredict", - "LegacyName": "metric_TMA_Info_Core_IpMispredict", - "Level": 1, - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", - "UnitOfMeasure": "", - "Events": [ + }, { - "Name": "INST_RETIRED.ANY", - "Alias": "a" + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" }, { "Name": "BR_MISP_RETIRED.ALL_BRANCHES", - "Alias": "b" + "Alias": "e" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "o" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "p" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "s" + }, + { + "Name": "DECODE.LCP", + "Alias": "t" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "u" } ], "Constants": [], - "Formula": "a / b", + "Formula": "100 * ( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( ( 10 ) * r / ( o ) ) ) + ( min( ( ( 3 ) * s / ( o ) ) , ( 1.0 ) ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) )", "Category": "TMA", - "Threshold": "< 200", + "Threshold": "> 20; $issueBM", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Bad, BadSpec, BrMispredicts" + "MetricGroup": "Bad;BadSpec;BrMispredicts" }, { - "MetricName": "Info_Inst_Mix_IpTB", - "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "MetricName": "Info_Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Info_Bottleneck_Big_Code", "Level": 1, - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "Alias": "a" }, { - "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Name": "INT_MISC.UOP_DROPPING", "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "f" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" } ], "Constants": [], - "Formula": "a / b", + "Formula": "100 * ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) )", "Category": "TMA", - "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "Threshold": "> 20", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB" }, { - "MetricName": "Info_Memory_L2MPKI", - "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "MetricName": "Info_Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Info_Bottleneck_Instruction_Fetch_BW", "Level": 1, - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", "UnitOfMeasure": "", "Events": [ { - "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "a" }, { - "Name": "INST_RETIRED.ANY", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "b" - } - ], - "Constants": [], - "Formula": "1000 * a / b", - "Category": "TMA", - "Threshold": "", + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "g" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "h" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "i" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "o" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "p" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "s" + }, + { + "Name": "DECODE.LCP", + "Alias": "t" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "u" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "v" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "w" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "x" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "y" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( ( 10 ) * r / ( o ) ) ) + ( min( ( ( 3 ) * s / ( o ) ) , ( 1.0 ) ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) - ( ( ( ( ( g / h ) * i / ( f ) ) / ( ( ( ( ( g / h ) * i / ( f ) ) + ( c / ( a + b + c + d ) ) * ( v - w ) / x ) - ( ( g / h ) * i / ( f ) ) ) + ( ( g / h ) * i / ( f ) ) ) ) * ( ( min( ( ( 34 ) * y / ( f ) ) , ( 1.0 ) ) ) / ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( min( ( ( 3 ) * s / ( o ) ) , ( 1.0 ) ) ) + ( n / ( o ) + ( ( 10 ) * r / ( o ) ) ) * ( ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( j / ( j + k ) ) * n / ( o ) ) * ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) / ( ( ( j / ( j + k ) ) * n / ( o ) ) + ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( ( 10 ) * r / ( o ) ) ) + ( min( ( ( 3 ) * s / ( o ) ) , ( 1.0 ) ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) - ( 100 * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( q / ( o ) ) + ( p / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( ( 10 ) * r / ( o ) ) ) + ( min( ( ( 3 ) * s / ( o ) ) , ( 1.0 ) ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW;Frontend" + }, + { + "MetricName": "Info_Bottleneck_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Info_Bottleneck_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_a" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a_b" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "a_f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_h" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_i" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_j" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_k" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_l" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_m" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_n" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_o" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_p" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_q" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_r" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_s" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_t" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_u" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_v" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_w" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_x" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "a_y" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "r" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "t" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "x" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "y" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_d" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( 100 * ( ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) * ( ( ( min( m , z ) ) / ( m ) ) / ( ( ( min( m , z ) ) / ( m ) ) + ( ( min( m , a_a ) ) / ( m ) - ( ( min( m , z ) ) / ( m ) ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( o - l ) / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) * ( ( a_b / ( m ) ) / ( ( min( ( ( ( ( 48 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_f * ( a_g / ( a_g + a_h ) ) ) + ( ( 47.5 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_i ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_j + a_f * ( 1 - ( a_g / ( a_g + a_h ) ) ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_c ) * a_d / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_k * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) , ( 1.0 ) ) ) + ( a_b / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( max( ( a - n ) / ( m ) , 0 ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) * ( ( a_l / ( m ) ) / ( ( min( ( 7 ) * a_m + a_n , max( a_o - a_p , 0 ) ) / ( m ) ) + ( min( ( 13 * a_q / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , a_r - a_s ) + ( a_r / a_t ) * ( ( 10 ) * a_u + ( min( m , a_v ) ) ) ) / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( a_w / ( r + q ) ) * a_x / ( m ) ) , ( 1.0 ) ) ) + ( a_y / ( m ) ) + ( a_l / ( m ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBW", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Cache_Memory_Latency", + "LegacyName": "metric_TMA_Info_Bottleneck_Cache_Memory_Latency", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "a_a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "a_f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_h" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_i" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_j" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a_k" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_l" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_m" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_n" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_o" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_p" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_q" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_r" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_s" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_t" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_u" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "r" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "t" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "x" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "y" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( 100 * ( ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) * ( ( ( min( m , z ) ) / ( m ) - ( ( min( m , a_a ) ) / ( m ) ) ) / ( ( ( min( m , a_a ) ) / ( m ) ) + ( ( min( m , z ) ) / ( m ) - ( ( min( m , a_a ) ) / ( m ) ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( o - l ) / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) * ( ( min( ( ( ( 23 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_e * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 48 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_f * ( a_g / ( a_g + a_h ) ) ) + ( ( 47.5 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_i ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_j + a_f * ( 1 - ( a_g / ( a_g + a_h ) ) ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_e * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) , ( 1.0 ) ) ) + ( a_k / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( b / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 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) ) * v ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) , ( 1.0 ) ) ) ) + ( ( ( o - l ) / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( min( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) / ( ( 19 * ( t * ( 1 + ( q / r ) ) ) + 10 * ( ( u * ( 1 + ( q / r ) ) ) + ( v * ( 1 + ( q / r ) ) ) + ( w * ( 1 + ( q / r ) ) ) ) ) + ( 25 * ( x * ( 1 + ( q / r ) ) ) + 33 * ( y * ( 1 + ( q / r ) ) ) ) ) ) ) * ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) if ( ( 1000000 ) * ( y + x ) > r ) else 0 ) ) , ( 1.0 ) ) ) + ( b / ( m ) ) ) ) * ( ( min( ( ( ( ( 48 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_e * ( a_f / ( a_f + a_g ) ) ) + ( ( 47.5 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_h ) 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( durationtimeinmilliseconds / 1000 ) ) ) ) * a_l / ( m ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( a_m * ( 10 ) * ( 1 - ( a_n / a_o ) ) ) + ( 1 - ( a_n / a_o ) ) * ( min( m , a_p ) ) ) / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( m ) / a_b ) * a_c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_l / ( m ) ) , ( 1.0 ) ) ) + ( a_q / ( a_r if ( 1 ) else ( m ) ) ) + ( min( ( 9 * a_s / ( m ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * a_t + a_u ) / ( a_r if ( 1 ) else ( m ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( a_m * ( 10 ) * ( 1 - ( a_n / a_o ) ) ) + ( 1 - ( a_n / a_o ) ) * ( min( m , a_p ) ) ) / ( m ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - a_v / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( a_w / ( a_w + a_x ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - a_v / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - a_v / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( a_w / ( a_w + a_x ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - a_v / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - a_y / a_x ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - a_v / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( a_w / ( a_w + a_x ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - a_v / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - a_y / a_x ) , 0.0001 ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueTLB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Info_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "o" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "p" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * ( l / ( m ) ) / ( ( l / ( m ) ) + ( n / ( m ) ) + ( ( ( ( o + ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * p ) / ( m ) * ( i - g ) / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( l < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * ( ( ( ( ( o + ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * p ) / ( m ) * ( i - g ) / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( l < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) / ( ( l / ( m ) ) + ( n / ( m ) ) + ( ( ( ( o + ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * p ) / ( m ) * ( i - g ) / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( l < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) ) ) * ( ( q / ( m ) ) / ( ( ( o + ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * p ) / ( m ) * ( i - g ) / ( m ) ) + ( j / ( m ) ) + ( k / ( m ) ) + ( q / ( m ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueComp", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor" + }, + { + "MetricName": "Info_Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a_a" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_d" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a_e" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_f" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "a_g" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a_h" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "a_i" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "n" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "p" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "s" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "t" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "u" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "v" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "w" + }, + { + "Name": "DECODE.LCP", + "Alias": "x" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "y" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "z" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( ( ( ( a / b ) * c / ( d ) ) / ( ( ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) - ( ( a / b ) * c / ( d ) ) ) + ( ( a / b ) * c / ( d ) ) ) ) * ( ( min( ( ( 34 ) * l / ( d ) ) , ( 1.0 ) ) ) / ( ( a / b ) * c / ( d ) ) ) ) * ( ( ( 5 ) * m - n ) / ( d ) ) * ( ( min( ( ( 3 ) * o / ( p ) ) , ( 1.0 ) ) ) + ( q / ( p ) + ( ( 10 ) * r / ( p ) ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * q / ( p ) ) + ( ( s / ( s + t ) ) * q / ( p ) ) * ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) / ( ( ( s / ( s + t ) ) * q / ( p ) ) + ( ( 1 - ( s / ( s + t ) ) ) * q / ( p ) ) + ( ( 10 ) * r / ( p ) ) ) ) / ( ( v / ( p ) ) + ( w / ( p ) ) + ( q / ( p ) + ( ( 10 ) * r / ( p ) ) ) + ( min( ( ( 3 ) * o / ( p ) ) , ( 1.0 ) ) ) + ( x / ( p ) ) + ( y / ( p ) ) ) ) + ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - z / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - z / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) - ( ( ( a_a + a_b ) / ( a_c + ( a_d + ( e / ( f + g + e + h ) ) * a_e ) + a_b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) ) ) ) * ( ( a_f / ( p ) ) + ( max( 0 , ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) - ( ( ( a_a + a_b ) / ( a_c + ( a_d + ( e / ( f + g + e + h ) ) * a_e ) + a_b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) ) ) ) * a_g / ( p ) * ( ( a_h + ( max( 0 , ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) - ( ( ( a_a + a_b ) / ( a_c + ( a_d + ( e / ( f + g + e + h ) ) * a_e ) + a_b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) ) ) ) * a_g ) / ( p ) * ( a_c - a_a ) / ( p ) ) ) / ( ( a_i / ( p ) ) + ( a_f / ( p ) ) + ( ( ( ( a_h + ( max( 0 , ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) - ( ( ( a_a + a_b ) / ( a_c + ( a_d + ( e / ( f + g + e + h ) ) * a_e ) + a_b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) ) ) ) * a_g ) / ( p ) * ( a_c - a_a ) / ( p ) ) * ( p ) + ( a_d + ( e / ( f + g + e + h ) ) * a_e ) ) / ( p ) if ( a_i < ( a_c - a_a ) ) else ( a_d + ( e / ( f + g + e + h ) ) * a_e ) / ( p ) ) ) ) + ( ( ( ( ( a / b ) * c / ( d ) ) / ( ( ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) - ( ( a / b ) * c / ( d ) ) ) + ( ( a / b ) * c / ( d ) ) ) ) * ( ( min( ( ( 34 ) * l / ( d ) ) , ( 1.0 ) ) ) / ( ( a / b ) * c / ( d ) ) ) ) * ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueMS", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Cor;Ret" + }, + { + "MetricName": "Info_Bottleneck_Other_Bottlenecks", + "LegacyName": "metric_TMA_Info_Bottleneck_Other_Bottlenecks", + "Level": 1, + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_a" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_b" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a_d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "a_e" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a_f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "a_g" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a_h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_j" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "a_k" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "a_l" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "a_m" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "a_n" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "a_o" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "a_p" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "a_q" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "a_r" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_s" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a_t" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_u" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "a_x" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_y" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_z" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "b_a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "b_b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "b_c" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "b_d" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "b_e" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b_f" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "b_g" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "b_h" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "b_i" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b_j" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b_k" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b_l" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "b_m" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "b_n" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "b_o" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "b_p" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "b_q" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "b_r" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "b_s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b_t" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "b_u" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "b_v" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b_w" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "b_x" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "b_y" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "b_z" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "c_a" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "c_b" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "c_c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c_d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c_e" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "f" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "l" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "m" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "n" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "o" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "p" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "q" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "r" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "s" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "t" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "u" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "v" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "w" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "x" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "y" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_v" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 - ( ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) + ( 100 * ( ( l / ( l + m + n + o ) - b / ( c ) ) - ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( min( ( ( 34 ) * y / ( c ) ) , ( 1.0 ) ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( s / ( s + t ) ) * h / ( e ) ) * ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) - ( 100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) ) + ( 100 * ( ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( ( min( e , a_r ) ) / ( e ) ) / ( ( ( min( e , a_r ) ) / ( e ) ) + ( ( min( e , a_s ) ) / ( e ) - ( ( min( e , a_r ) ) / ( e ) ) ) ) ) ) + ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_g - a_e ) / ( e ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( a_t / ( e ) ) / ( ( min( ( ( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x * ( a_y / ( a_y + a_z ) ) ) + ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b + a_x * ( 1 - ( a_y / ( a_y + a_z ) ) ) ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_i / a_j ) / 2 ) ) / ( e ) ) , ( 1.0 ) ) ) + ( a_t / ( e ) ) ) ) ) + ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( z - a_f ) / ( e ) , 0 ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( b_d / ( e ) ) / ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( min( ( 13 * b_i / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( e , b_n ) ) ) ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( b_o / ( a_j + a_i ) ) * b_p / ( e ) ) , ( 1.0 ) ) ) + ( b_q / ( e ) ) + ( b_d / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * 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a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( 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+ ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) + ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_a / ( e ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( min( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r / ( e ) ) , ( 1.0 ) ) ) + ( b_s / ( b_t if ( 1 ) else ( e ) ) ) + ( min( ( 9 * b_u / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * b_v + b_w ) / ( b_t if ( 1 ) else ( e ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( z - a_f ) / ( e ) , 0 ) ) / max( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) , ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) ) * ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) / max( ( max( ( z - a_f ) / ( e ) , 0 ) ) , ( ( min( ( 7 ) * b_e + b_f , max( b_g - b_h , 0 ) ) / ( e ) ) + ( min( ( 13 * b_i / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( e , b_n ) ) ) ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( b_o / ( a_j + a_i ) ) * b_p / ( e ) ) , ( 1.0 ) ) ) + ( b_q / ( e ) ) + ( b_d / ( e ) ) ) ) ) + ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_a / ( e ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( min( ( ( ( 7 ) * b_v + b_w ) / ( b_t if ( 1 ) else ( e ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r / ( e ) ) , ( 1.0 ) ) ) + ( b_s / ( b_t if ( 1 ) else ( e ) ) ) + ( min( ( 9 * b_u / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * b_v + b_w ) / ( b_t if ( 1 ) else ( e ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( ( min( e , a_s ) ) / ( e ) - ( ( min( e , a_r ) ) / ( e ) ) ) / ( ( ( min( e , a_r ) ) / ( e ) ) + ( ( min( e , a_s ) ) / ( e ) - ( ( min( e , a_r ) ) / ( e ) ) ) ) ) * ( min( ( ( ( ( 120 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_o + ( ( 120 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_n ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 66.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_m * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 131 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_l * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 120 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_o + ( ( 120 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_n ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) ) + ( ( ( a_g - a_e ) / ( e ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( ( min( ( ( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x * ( a_y / ( a_y + a_z ) ) ) + ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b + a_x * ( 1 - ( a_y / ( a_y + a_z ) ) ) ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x * ( a_y / ( a_y + a_z ) ) ) + ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_a ) ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_b + a_x * ( 1 - ( a_y / ( a_y + a_z ) ) ) ) * ( 1 + ( a_i / a_j ) / 2 ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( b_c * ( 1 + ( a_i / a_j ) / 2 ) ) / ( e ) ) , ( 1.0 ) ) ) + ( a_t / ( e ) ) ) + ( ( a_a / ( e ) ) / ( ( max( ( z - a_f ) / ( e ) , 0 ) ) + ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) + ( ( a_g - a_e ) / ( e ) ) + ( min( ( ( ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) / ( ( 19 * ( a_l * ( 1 + ( a_i / a_j ) ) ) + 10 * ( ( a_m * ( 1 + ( a_i / a_j ) ) ) + ( a_n * ( 1 + ( a_i / a_j ) ) ) + ( a_o * ( 1 + ( a_i / a_j ) ) ) ) ) + ( 25 * ( a_p * ( 1 + ( a_i / a_j ) ) ) + 33 * ( a_q * ( 1 + ( a_i / a_j ) ) ) ) ) ) ) * ( a_e / ( e ) + ( ( a_f - a_g ) / ( e ) ) - ( ( ( a_h * ( 1 + ( a_i / a_j ) ) ) / ( ( a_h * ( 1 + ( a_i / a_j ) ) ) + a_k ) ) * ( ( a_f - a_g ) / ( e ) ) ) ) ) if ( ( 1000000 ) * ( a_q + a_p ) > a_j ) else 0 ) ) , ( 1.0 ) ) ) + ( a_a / ( e ) ) ) ) * ( min( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r / ( e ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( e ) / a_u ) * a_v / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_r / ( e ) ) , ( 1.0 ) ) ) + ( b_s / ( b_t if ( 1 ) else ( e ) ) ) + ( min( ( 9 * b_u / ( e ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * b_v + b_w ) / ( b_t if ( 1 ) else ( e ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - b_x / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - b_x / t ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( b_y / ( e ) ) / ( ( b_y / ( e ) ) + ( b_z / ( e ) ) + ( ( ( ( c_a + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b ) / ( e ) * ( a_b - z ) / ( e ) ) * ( e ) + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) ) / ( e ) if ( b_y < ( a_b - z ) ) else ( a_c + ( n / ( l + m + n + o ) ) * a_d ) / ( e ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( ( ( ( c_a + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b ) / ( e ) * ( a_b - z ) / ( e ) ) * ( e ) + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) ) / ( e ) if ( b_y < ( a_b - z ) ) else ( a_c + ( n / ( l + m + n + o ) ) * a_d ) / ( e ) ) / ( ( b_y / ( e ) ) + ( b_z / ( e ) ) + ( ( ( ( c_a + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b ) / ( e ) * ( a_b - z ) / ( e ) ) * ( e ) + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) ) / ( e ) if ( b_y < ( a_b - z ) ) else ( a_c + ( n / ( l + m + n + o ) ) * a_d ) / ( e ) ) ) ) * ( ( c_c / ( e ) ) / ( ( ( c_a + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b ) / ( e ) * ( a_b - z ) / ( e ) ) + ( a_c / ( e ) ) + ( a_d / ( e ) ) + ( c_c / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( min( ( ( 34 ) * y / ( c ) ) , ( 1.0 ) ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( s / ( s + t ) ) * h / ( e ) ) * ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( ( 10 ) * g / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - b_x / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - b_x / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( b_z / ( e ) ) + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b / ( e ) * ( ( c_a + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b ) / ( e ) * ( a_b - z ) / ( e ) ) ) / ( ( b_y / ( e ) ) + ( b_z / ( e ) ) + ( ( ( ( c_a + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( z + a_a ) / ( a_b + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) + a_a ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_b ) / ( e ) * ( a_b - z ) / ( e ) ) * ( e ) + ( a_c + ( n / ( l + m + n + o ) ) * a_d ) ) / ( e ) if ( b_y < ( a_b - z ) ) else ( a_c + ( n / ( l + m + n + o ) ) * a_d ) / ( e ) ) ) ) + ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( min( ( ( 34 ) * y / ( c ) ) , ( 1.0 ) ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) + ( 100 * ( ( c_d + c_e ) / ( c ) ) ) + ( 100 * ( ( n / ( l + m + n + o ) ) - ( ( c_d + c_e ) / ( c ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( min( ( ( 34 ) * y / ( c ) ) , ( 1.0 ) ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a + b ) / ( c ) ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Bottleneck_Base_Non_Br", + "LegacyName": "metric_TMA_Info_Bottleneck_Base_Non_Br", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "h" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "i" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "j" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "k" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "l" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "m" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "n" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + a + d ) ) - ( ( e + f ) / ( g ) ) - ( ( ( ( ( h / i ) * j / ( g ) ) / ( ( ( ( ( h / i ) * j / ( g ) ) + ( a / ( b + c + a + d ) ) * ( k - l ) / m ) - ( ( h / i ) * j / ( g ) ) ) + ( ( h / i ) * j / ( g ) ) ) ) * ( ( min( ( ( 34 ) * n / ( g ) ) , ( 1.0 ) ) ) / ( ( h / i ) * j / ( g ) ) ) ) * ( ( ( h / i ) * j / ( g ) ) + ( a / ( b + c + a + d ) ) * ( k - l ) / m ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Info_Thread_Slots_Utilization", + "LegacyName": "metric_TMA_Info_Thread_Slots_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:percore", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b / 2 ) if ( 1 ) else 1", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "SMT;TmaL1" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( f if ( 1 ) else ( g ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( ( a ) + ( b ) ) / ( 2 * ( c if ( 1 ) else ( d ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Botlnk_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "l" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "p" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) / ( ( ( ( l + ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * m ) / ( n ) * ( i - g ) / ( n ) ) * ( n ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( n ) if ( o < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( n ) ) if ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) < ( ( ( ( l + ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * m ) / ( n ) * ( i - g ) / ( n ) ) * ( n ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( n ) if ( o < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( n ) ) else 1 ) if ( 1 - p / q if ( 1 ) else 0 ) > 0.5 else 0", + "Category": "TMA", + "Threshold": "> 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( b + 2 * c + 4 * d + 8 * e + 16 * f )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b ) + ( c ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MISC_RETIRED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.T0:u0xF", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "a" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Botlnk_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "f" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "i" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "j" + }, + { + "Name": "DECODE.LCP", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "l" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "m" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "n" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "o" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "p" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "q" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "r" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "s" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "t" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( d / ( e ) ) / ( ( f / ( e ) ) + ( g / ( e ) ) + ( h / ( e ) + ( ( 10 ) * i / ( e ) ) ) + ( min( ( ( 3 ) * j / ( e ) ) , ( 1.0 ) ) ) + ( k / ( e ) ) + ( d / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( ( p - q ) / ( r if ( 1 ) else ( e ) ) / 2 ) / ( ( ( p - q ) / ( r if ( 1 ) else ( e ) ) / 2 ) + ( ( s - t ) / ( r if ( 1 ) else ( e ) ) / 2 ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Botlnk_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "g" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( d / ( e ) ) / ( ( d / ( e ) ) + ( f / ( e ) ) + ( g / ( e ) + ( ( 10 ) * h / ( e ) ) ) + ( min( ( ( 3 ) * i / ( e ) ) , ( 1.0 ) ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueFL", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Ret", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Ret", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 500", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "o" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "p" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "s" + }, + { + "Name": "DECODE.LCP", + "Alias": "t" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "u" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( ( 10 ) * r / ( o ) ) ) + ( min( ( ( 3 ) * s / ( o ) ) , ( 1.0 ) ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) * ( d ) / e / 100", + "Category": "TMA", + "Threshold": "; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a - b - 2 * c ) / d", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Other_Branches", + "LegacyName": "metric_TMA_Info_Branches_Other_Branches", + "Level": 1, + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "1 - ( ( a / b ) + ( c / b ) + ( ( d + e ) / b ) + ( ( f - c - 2 * d ) / b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + }, + { + "Name": "L2_RQSTS.ALL_DEMAND_MISS", + "Alias": "c" + }, + { + "Name": "L2_RQSTS.SWPF_MISS", + "Alias": "d" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "1000 * ( ( a - b ) + c + d ) / ( e )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 2 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L3_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L3_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:u0x10", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_Bus_Lock_PKI", + "LegacyName": "metric_TMA_Info_Memory_Bus_Lock_PKI", + "Level": 1, + "BriefDescription": "\"Bus lock\" per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "SQ_MISC.BUS_LOCK", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 160 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License0_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License0_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL0_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License1_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License1_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL1_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License2_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License2_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL2_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / b if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_PMM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_PMM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( ( 1000000000 ) * ( a / b ) / c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Read_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Read_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Write_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Write_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b + c + d ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Mem;Backend;CacheMisses" + "MetricGroup": "Branches;OS" } ] } \ No newline at end of file diff --git a/ICX/metrics/perf/icelakex_metrics_perf.json b/ICX/metrics/perf/icelakex_metrics_perf.json index fec9fe95..6b490a74 100644 --- a/ICX/metrics/perf/icelakex_metrics_perf.json +++ b/ICX/metrics/perf/icelakex_metrics_perf.json @@ -330,15 +330,15 @@ }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "( ICACHE_16B.IFDATA_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricExpr": "( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "( ICACHE_64B.IFTAG_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricExpr": "( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%" }, @@ -364,31 +364,31 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "MetricExpr": "( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "MetricExpr": "( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "MetricExpr": "( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "MetricExpr": "( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", "ScaleUnit": "100%" }, { @@ -400,14 +400,14 @@ }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "MetricExpr": "( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricExpr": "( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_mite", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", "MetricName": "tma_decoder0_alone", "ScaleUnit": "100%" @@ -421,42 +421,56 @@ }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_dsb", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "MetricExpr": "( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) )", + "MetricExpr": "( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) )", + "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) )", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) )", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "MetricExpr": "( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) )", "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) )", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "ScaleUnit": "100%" + }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "MetricExpr": "( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) )", + "MetricExpr": "( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) )", + "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) )", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "ScaleUnit": "100%" @@ -464,7 +478,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", "MetricExpr": "( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "ScaleUnit": "100%" }, @@ -491,21 +505,21 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "MetricExpr": "( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_lock_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "ScaleUnit": "100%" @@ -527,34 +541,34 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", "MetricExpr": "( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", "MetricExpr": "( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "MetricExpr": "( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "MetricExpr": "( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_data_sharing", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "MetricExpr": "( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%" @@ -568,20 +582,20 @@ }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_latency", @@ -589,28 +603,28 @@ }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( 66.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 66.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", + "MetricName": "tma_local_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( 131 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 131 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", + "MetricName": "tma_remote_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_remote_cache", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", - "MetricExpr": "( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "ScaleUnit": "100%" @@ -624,56 +638,56 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "MetricExpr": "( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "MetricExpr": "( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_false_sharing", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", - "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_split_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", - "MetricExpr": "( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_streaming_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", - "MetricExpr": "( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) , ( 1 ) ) ) - ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( min( ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) - ( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_hit", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_miss", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "MetricExpr": "( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( slots ) ) ) ) )", + "MetricExpr": "( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) )", "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "ScaleUnit": "100%" @@ -685,37 +699,37 @@ "MetricName": "tma_divider", "ScaleUnit": "100%" }, - { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "MetricExpr": "( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( 0 * slots )", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "MetricExpr": "( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / ( CPU_CLK_UNHALTED.THREAD ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "ScaleUnit": "100%" - }, { "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", "MetricExpr": "( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", "MetricName": "tma_serializing_operation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", "MetricExpr": "( 37 * MISC_RETIRED.PAUSE_INST / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", "MetricName": "tma_slow_pause", "ScaleUnit": "100%" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "MetricExpr": "( min( ( ( CPU_CLK_UNHALTED.THREAD ) * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "MetricExpr": "( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "MetricExpr": "( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricExpr": "( min( ( UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", "MetricName": "tma_mixing_vectors", "ScaleUnit": "100%" @@ -743,49 +757,49 @@ }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "( ( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_0 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_0 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_1 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_1 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_5 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_5 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_5", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_6 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_6 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "( UOPS_DISPATCHED.PORT_2_3 / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_2_3 / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "( ( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" @@ -798,15 +812,15 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", - "MetricExpr": "( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_light_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) )", + "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) ) )", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", "ScaleUnit": "100%" @@ -827,106 +841,288 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_fp_vector", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_128b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_256b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_512b", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_memory_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", - "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * BR_INST_RETIRED.ALL_BRANCHES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * BR_INST_RETIRED.ALL_BRANCHES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_branch_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", - "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricExpr": "( max( 0 , ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * BR_INST_RETIRED.ALL_BRANCHES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", + "MetricName": "tma_other_light_ops", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "( max( 0 , ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * BR_INST_RETIRED.ALL_BRANCHES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "MetricExpr": "( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", - "MetricExpr": "( ( ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) )", + "MetricExpr": "( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) )", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_few_uops_instructions", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", - "MetricExpr": "( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) )", + "MetricExpr": "( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) )", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_microcode_sequencer", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", - "MetricExpr": "( min( ( ( 100 ) * ASSISTS.ANY / ( slots ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_assists", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "MetricExpr": "( 34 * ASSISTS.FP / ( slots ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "MetricExpr": "( max( 0 , ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) - ( min( ( ( 100 ) * ASSISTS.ANY / ( slots ) ) , ( 1 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) - ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_cisc", "ScaleUnit": "100%" }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( 100 * ( 1 - ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) + ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * ( 100 * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_big_code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( 1 - ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( 100 * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchBW;Frontend;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) , ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryTLB;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_data_tlbs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "MetricExpr": "100 * ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 66.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 131 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) )", + "MetricGroup": "Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_synchronization" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "MetricExpr": "100 * ( 100 * ( ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * ( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Cor;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_compute_bound_est" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * ( ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) * ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) )", + "MetricGroup": "Bad;Cor;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_irregular_overhead" + }, + { + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "MetricExpr": "100 - ( ( 100 * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 100 * ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( 1 - ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( 100 * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) + ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) , ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) * ( ( ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 66.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 131 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 120 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 23 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.L2_STALL / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + L1D_PEND_MISS.FB_FULL_PERIODS ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 48 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * ( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * ( ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) * ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) ) + ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) ) + ( 100 * ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) - ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) ) )", + "MetricGroup": "Cor;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_other_bottlenecks" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_branching_overhead" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) - ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) / ( ( ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) - ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) + ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( min( ( ( 34 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) ) ) * ( ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@ ) / IDQ.MITE_UOPS ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_base_non_br" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "( slots ) / ( TOPDOWN.SLOTS / 2 ) if ( 1 ) else 1", + "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots_utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" + }, { "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.DISTRIBUTED )", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_info_core_coreipc" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", - "MetricName": "tma_info_core_ipmispredict" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) ) / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "100 * ( 1 - ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) / ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) if ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) < ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) else 1 ) if ( 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0 ) > 0.5 else 0", + "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_core_bound_likely" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" }, { "BriefDescription": "Instruction per taken branch", @@ -934,10 +1130,551 @@ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_info_inst_mix_iptb" }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx512" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / MISC_RETIRED.PAUSE_INST", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ippause" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipswpf" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_ipassist" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@ )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=0x1@", + "MetricGroup": "Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "DSBmiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipdsb_miss_ret" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( max( 0 , ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) ) ) * ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) / ( ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) + ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) ) ) )", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_dsb_misses" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_ic_misses" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( 100 * ( 1 - ( 10 * ( ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( slots ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) + ( ( 5 ) * INT_MISC.CLEARS_COUNT ) / ( slots ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) + ( ( ( 5 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / ( slots ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 10 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( slots ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )", + "MetricGroup": "BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( ( BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES ) )", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_other_branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki_load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Mem;Backend;CacheMisses;TopdownL1;tma_L1_group", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / ( INST_RETIRED.ANY )", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1000 * L2_LINES_OUT.SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l3_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "1000 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_bus_lock_pki" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 160 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cha@UNC_CHA_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license0_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license1_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license2_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( ( cha@UNC_CHA_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( ( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha@UNC_CHA_CLOCKTICKS@ )", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_pmm_read_latency" + }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_dram_read_latency" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_RPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_read_bw" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_WPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_write_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_read_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_write_bw" + }, + { + "BriefDescription": "Total package Power in Watts", + "MetricExpr": "( FREERUN_PKG_ENERGY_STATUS * ( 61 ) + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( ( ( duration_time * 1000 ) / 1000 ) * ( 1000000 ) )", + "MetricGroup": "Power;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" } ] \ No newline at end of file diff --git a/SKX/metrics/perf/skylakex_metrics_perf.json b/SKX/metrics/perf/skylakex_metrics_perf.json index 25f717d1..d32c99f5 100644 --- a/SKX/metrics/perf/skylakex_metrics_perf.json +++ b/SKX/metrics/perf/skylakex_metrics_perf.json @@ -258,6 +258,13 @@ "MetricName": "llc_miss_remote_memory_bandwidth_read", "ScaleUnit": "1MB/s" }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", "MetricExpr": "( UNC_UPI_RxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", @@ -267,14 +274,14 @@ }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "MetricExpr": "( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "ScaleUnit": "100%" @@ -282,14 +289,14 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", "MetricExpr": "( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "( ICACHE_64B.IFTAG_STALL / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricExpr": "( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%" }, @@ -315,92 +322,106 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "MetricExpr": "( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "MetricExpr": "( ILD_STALL.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "MetricExpr": "( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "MetricExpr": "( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_mite", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", "MetricName": "tma_decoder0_alone", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "MetricExpr": "( ( IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_dsb", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) )", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) )", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "ScaleUnit": "100%" + }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "MetricExpr": "( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "ScaleUnit": "100%" @@ -408,7 +429,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", "MetricExpr": "( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "ScaleUnit": "100%" }, @@ -435,21 +456,21 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "MetricExpr": "( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_lock_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "ScaleUnit": "100%" @@ -471,61 +492,61 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", "MetricExpr": "( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", "MetricExpr": "( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "MetricExpr": "( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "MetricExpr": "( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_data_sharing", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "MetricExpr": "( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", - "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_sq_full", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "MetricExpr": "( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_latency", @@ -533,21 +554,21 @@ }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", + "MetricName": "tma_local_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", + "MetricName": "tma_remote_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / ( MEM_LOAD_RETIRED.L1_MISS ) ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_remote_cache", "ScaleUnit": "100%" @@ -561,49 +582,49 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "MetricExpr": "( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "MetricExpr": "( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_false_sharing", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", - "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_split_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", - "MetricExpr": "( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) ) - ( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( min( ( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) - ( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_hit", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_miss", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "MetricExpr": "( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", + "MetricExpr": "( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) )", "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "ScaleUnit": "100%" @@ -615,156 +636,156 @@ "MetricName": "tma_divider", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "MetricExpr": "( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "MetricExpr": "( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_ports_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "MetricExpr": "( ( UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_0", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", - "MetricExpr": "( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "MetricExpr": "( min( ( ( CPU_CLK_UNHALTED.THREAD ) * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricExpr": "( min( ( UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", "MetricName": "tma_mixing_vectors", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if ( 1 ) else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if ( 1 ) else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_3m", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6 ) / ( 4 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_0 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_1 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_5 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_5", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_6 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4 ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_3 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_4 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_4", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricExpr": "( UOPS_DISPATCHED_PORT.PORT_7 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", "MetricName": "tma_port_7", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", - "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_light_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) )", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) ) )", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", "ScaleUnit": "100%" }, { "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD )", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD )", "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", "ScaleUnit": "100%" @@ -778,124 +799,787 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_fp_vector", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_128b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_256b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_512b", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_memory_operations", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fused_instructions", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_non_fused_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1.0 ) ) ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) ) ) )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", + "MetricName": "tma_other_light_ops", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) , ( 1 ) ) ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * UOPS_RETIRED.MACRO_FUSED / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED ) / ( UOPS_RETIRED.RETIRE_SLOTS ) ) + ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) ) ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * INST_RETIRED.NOP / ( UOPS_RETIRED.RETIRE_SLOTS ) )", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", - "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricExpr": "( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_few_uops_instructions", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", - "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricExpr": "( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", "MetricName": "tma_microcode_sequencer", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", - "MetricExpr": "( min( ( ( 100 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_assists", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "MetricExpr": "( 34 * FP_ASSIST.ANY / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 100 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_cisc", "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( 100 * ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", - "MetricName": "tma_info_core_ipmispredict" + "MetricName": "tma_info_bottleneck_mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_big_code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchBW;Frontend;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) )", + "MetricGroup": "Mem;MemoryTLB;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_data_tlbs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "MetricExpr": "100 * ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) )", + "MetricGroup": "Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_synchronization" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "MetricExpr": "100 * ( 100 * ( ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if ( 1 ) else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if ( 1 ) else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricGroup": "Cor;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_compute_bound_est" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "MetricExpr": "100 * ( 100 * ( ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Bad;Cor;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_irregular_overhead" + }, + { + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "MetricExpr": "100 - ( ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 100 * ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) - ( 100 * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 9 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 12 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 11 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) ) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 147.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * ( 1 - ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / ( OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 20.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 3.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( ( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) if ( 1 ) else OFFCORE_REQUESTS_BUFFER.SQ_FULL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( CYCLE_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) + ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) / ( ( MEM_LOAD_RETIRED.L2_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ ) ) * ( ( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 110 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM ) + ( 47.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( ( 9 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( L2_RQSTS.RFO_HIT * ( 11 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2 ) / 2 if ( 1 ) else EXE_ACTIVITY.1_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / 2 if ( 1 ) else EXE_ACTIVITY.2_PORTS_UTIL ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if ( 1 ) else UOPS_EXECUTED.CORE_CYCLES_GE_3 ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) / ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) * ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIVIDER_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( PARTIAL_RAT_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) )", + "MetricGroup": "Cor;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_other_bottlenecks" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_branching_overhead" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * ( 100 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) , ( 1.0 ) ) ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_base_non_br" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" }, { "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_info_core_coreipc" }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "100 * ( 1 - ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) / ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) if ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) < ( ( ( ( EXE_ACTIVITY.EXE_BOUND_0_PORTS + ( ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / ( CYCLE_ACTIVITY.STALLS_TOTAL + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) + EXE_ACTIVITY.BOUND_ON_STORES ) ) * ( 1 - ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( UOPS_ISSUED.ANY + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) * RS_EVENTS.EMPTY_CYCLES ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIVIDER_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( ( UOPS_RETIRED.RETIRE_SLOTS ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * EXE_ACTIVITY.2_PORTS_UTIL ) / ( CPU_CLK_UNHALTED.THREAD ) ) else 1 ) if ( 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if ( 1 ) else 0 ) > 0.5 else 0", + "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_core_bound_likely" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" + }, { "BriefDescription": "Instruction per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_info_inst_mix_iptb" }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx512" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipswpf" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( UOPS_RETIRED.RETIRE_SLOTS ) / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ASSIST.ANY + OTHER_ASSISTS.ANY )", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_ipassist" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@ )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=0x1@", + "MetricGroup": "Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", + "MetricGroup": "DSBmiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ + 2", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipdsb_miss_ret" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( IDQ_UOPS_NOT_DELIVERED.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) - ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) / ( ( ( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) + ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) ) ) )", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_dsb_misses" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_ic_misses" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "( INST_RETIRED.ANY ) / ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * BR_MISP_EXEC.INDIRECT )", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( 100 * ( 1 - ( 10 * ( ( ( UOPS_RETIRED.RETIRE_SLOTS ) / UOPS_ISSUED.ANY ) * IDQ.MS_UOPS / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( max( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) * ( ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * ( ( UOPS_ISSUED.ANY - ( UOPS_RETIRED.RETIRE_SLOTS ) + ( 4 ) * ( ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if ( 1 ) else INT_MISC.RECOVERY_CYCLES ) ) / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( 4 ) * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( ( 9 ) * BACLEARS.ANY / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 2 ) * IDQ.MS_SWITCHES / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( 4 ) * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )", + "MetricGroup": "BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "( BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.COND - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki_load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Mem;Backend;CacheMisses;TopdownL1;tma_L1_group", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1000 * L2_LINES_OUT.SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 8 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cha@UNC_CHA_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) if ( 1 ) else CORE_POWER.LVL0_TURBO_LICENSE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license0_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) if ( 1 ) else CORE_POWER.LVL1_TURBO_LICENSE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license1_utilization" + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) if ( 1 ) else CORE_POWER.LVL2_TURBO_LICENSE / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power_license2_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( ( cha@UNC_CHA_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( 1000000000 ) * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / imc_0@event\\=0x0@", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_dram_read_latency" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_read_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_write_bw" + }, + { + "BriefDescription": "Total package Power in Watts", + "MetricExpr": "( FREERUN_PKG_ENERGY_STATUS * ( 61 ) + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( ( ( duration_time * 1000 ) / 1000 ) * ( 1000000 ) )", + "MetricGroup": "Power;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_power" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" } ] \ No newline at end of file diff --git a/SKX/metrics/skylakex_metrics.json b/SKX/metrics/skylakex_metrics.json index 2825b5dc..d8e94f18 100644 --- a/SKX/metrics/skylakex_metrics.json +++ b/SKX/metrics/skylakex_metrics.json @@ -1,10 +1,12 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor Scalable Family based on Skylake microarchitecture - V", - "DatePublished": "11/09/2023", - "Version": "", - "Legend": "" + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) Processor Scalable Family based on Skylake microarchitecture0", + "DatePublished": "01/17/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" }, "Metrics": [ { @@ -899,6 +901,25 @@ "ResolutionLevels": "CHA, SOCKET, SYSTEM", "MetricGroup": "" }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, { "MetricName": "upi_data_receive_bw", "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", @@ -938,20 +959,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1;PGO" }, { @@ -975,20 +987,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Frontend;TmaL2" }, { @@ -1016,8 +1019,8 @@ "Formula": "100 * ( ( a + 2 * b ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;IcMiss" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;IcMiss" }, { "MetricName": "ITLB_Misses", @@ -1028,7 +1031,7 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "ICACHE_64B.IFTAG_STALL", + "Name": "ICACHE_TAG.STALLS", "Alias": "a" }, { @@ -1040,8 +1043,8 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" }, { "MetricName": "Branch_Resteers", @@ -1068,7 +1071,7 @@ "Formula": "100 * ( a / ( b ) + ( ( 9 ) * c / ( b ) ) )", "Category": "TMA", "Threshold": "> 5 & P; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { @@ -1100,7 +1103,7 @@ "Formula": "100 * ( ( a / ( a + b ) ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueBM", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts" }, { @@ -1132,7 +1135,7 @@ "Formula": "100 * ( ( 1 - ( a / ( a + b ) ) ) * c / ( d ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears" }, { @@ -1140,7 +1143,7 @@ "LegacyName": "metric_TMA_......Unknown_Branches(%)", "ParentCategory": "Branch_Resteers", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "UnitOfMeasure": "percent", "Events": [ { @@ -1156,19 +1159,19 @@ "Formula": "100 * ( ( 9 ) * a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat" }, { - "MetricName": "DSB_Switches", - "LegacyName": "metric_TMA_....DSB_Switches(%)", + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Name": "IDQ.MS_SWITCHES", "Alias": "a" }, { @@ -1177,22 +1180,22 @@ } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DSBmiss;FetchLat" + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq" }, { "MetricName": "LCP", "LegacyName": "metric_TMA_....LCP(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "ILD_STALL.LCP", + "Name": "DECODE.LCP", "Alias": "a" }, { @@ -1204,19 +1207,19 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchLat" }, { - "MetricName": "MS_Switches", - "LegacyName": "metric_TMA_....MS_Switches(%)", + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.MS_SWITCHES", + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "Alias": "a" }, { @@ -1225,11 +1228,11 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 2 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "FetchLat;MicroSeq" + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat" }, { "MetricName": "Fetch_Bandwidth", @@ -1256,20 +1259,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( 4 ) * d / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( 4 ) * d / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P & #HighIPC; $issueFB", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "Threshold": "> 20; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2" }, { @@ -1297,20 +1291,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, { @@ -1338,20 +1323,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 10 & P; $issueD0", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, { @@ -1363,11 +1339,11 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "Name": "IDQ.DSB_CYCLES_ANY", "Alias": "a" }, { - "Name": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "Name": "IDQ.DSB_CYCLES_OK", "Alias": "b" }, { @@ -1379,20 +1355,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if smt_on else ( d ) ) / 2 )", + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DSB;FetchBW" }, { @@ -1427,20 +1394,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 15", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1484,21 +1442,64 @@ "Alias": "h" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( g / 2 ) if ( 1 ) else ( h ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "d" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "e" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" } ], - "Formula": "100 * ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( g / 2 ) if smt_on else ( h ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( max( ( ( a / ( a + b ) ) * ( ( c - ( d ) + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( g / 2 ) if ( 1 ) else ( h ) ) ) ) ) * ( 1 - a / ( i - b ) ) , 0.0001 ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueBM", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2" + "Threshold": "> 5 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" }, { "MetricName": "Machine_Clears", @@ -1541,21 +1542,64 @@ "Alias": "h" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueMC; $issueSyncxn", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears;TmaL2" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "b" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "c" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "g" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "i" } ], - "Formula": "100 * ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if smt_on else d ) ) / ( ( 4 ) * ( ( e / 2 ) if smt_on else ( f ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( max( ( ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) - ( ( g / ( g + h ) ) * ( ( a - ( b ) + ( 4 ) * ( ( c / 2 ) if ( 1 ) else d ) ) / ( ( 4 ) * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) ) ) ) * ( 1 - i / h ) , 0.0001 ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueMC; $issueSyncxn", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", - "MetricGroup": "BadSpec;MachineClears;TmaL2" + "Threshold": "> 5 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Machine_Clears" }, { "MetricName": "Backend_Bound", @@ -1589,20 +1633,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 20", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -1662,20 +1697,11 @@ "Alias": "l" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a + b ) / ( c + ( d + ( ( e ) / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( g ) ) ) ) * h ) + b ) ) * ( 1 - ( i / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( g ) ) ) ) - ( j + ( 4 ) * ( ( k / 2 ) if smt_on else l ) ) / ( ( 4 ) * ( ( f / 2 ) if smt_on else ( g ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( c + ( d + ( ( e ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) * h ) + b ) ) * ( 1 - ( i / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) - ( j + ( 4 ) * ( ( k / 2 ) if ( 1 ) else l ) ) / ( ( 4 ) * ( ( f / 2 ) if ( 1 ) else ( g ) ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2" }, { @@ -1703,8 +1729,8 @@ "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueL1; $issueMC", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "DTLB_Load", @@ -1739,7 +1765,7 @@ "Formula": "100 * ( min( ( 9 ) * a + b , max( c - d , 0 ) ) / ( e ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1775,7 +1801,7 @@ "Formula": "100 * ( ( min( ( 9 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1799,7 +1825,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -1820,10 +1846,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1860,10 +1886,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 12 * max( 0 , a - b ) + ( a / c ) * ( ( 11 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 12 * max( 0 , a - b ) + ( a / c ) * ( ( 11 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueRFO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore" }, { @@ -1896,10 +1922,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / ( b + c ) ) * d / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1923,7 +1949,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -1959,7 +1985,7 @@ "Formula": "100 * ( ( a / ( b + c ) ) * d / ( e ) )", "Category": "TMA", "Threshold": "> 30; $issueBW; $issueSL; $issueSmSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW" }, { @@ -2003,8 +2029,8 @@ "Formula": "100 * ( ( ( a * ( 1 + ( b / c ) ) ) / ( ( a * ( 1 + ( b / c ) ) ) + d ) ) * ( ( e - f ) / ( g ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "L3_Bound", @@ -2031,8 +2057,8 @@ "Formula": "100 * ( ( a - b ) / ( c ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "Contested_Accesses", @@ -2085,10 +2111,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -2142,10 +2168,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Snoop" }, { @@ -2153,7 +2179,7 @@ "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", "UnitOfMeasure": "percent", "Events": [ { @@ -2187,10 +2213,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e ) * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 3.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat" }, { @@ -2214,20 +2240,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a / 2 ) if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a / 2 ) if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 30 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2272,10 +2289,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2283,7 +2300,7 @@ "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2299,7 +2316,7 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueBW", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBW;Offcore" }, { @@ -2307,7 +2324,7 @@ "LegacyName": "metric_TMA_......MEM_Latency(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2327,12 +2344,12 @@ "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { - "MetricName": "Local_DRAM", - "LegacyName": "metric_TMA_........Local_DRAM(%)", + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", @@ -2369,18 +2386,18 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server" }, { - "MetricName": "Remote_DRAM", - "LegacyName": "metric_TMA_........Remote_DRAM(%)", + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2414,10 +2431,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 147.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 147.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Server;Snoop" }, { @@ -2425,7 +2442,7 @@ "LegacyName": "metric_TMA_........Remote_Cache(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2463,10 +2480,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Offcore;Server;Snoop" }, { @@ -2490,7 +2507,7 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryBound;TmaL3mem" }, { @@ -2523,10 +2540,10 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a * ( 11 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "Formula": "100 * ( min( ( ( ( a * ( 11 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryLat;Offcore" }, { @@ -2572,10 +2589,10 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * ( e + f ) + ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * ( g + h ) ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 110 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f ) + ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( g + h ) ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "DataSharing;Offcore;Snoop" }, { @@ -2599,20 +2616,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -2640,20 +2648,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if smt_on else ( d ) ) ) , ( 1 ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueTLB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2681,20 +2680,11 @@ "Alias": "d" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if smt_on else ( d ) ) ) , ( 1 ) ) ) - ( b / ( ( c / 2 ) if smt_on else ( d ) ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( ( min( ( ( ( 9 ) * a + b ) / ( ( c / 2 ) if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) - ( min( ( b / ( ( c / 2 ) if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2718,20 +2708,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( min( ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MemoryTLB" }, { @@ -2791,20 +2772,11 @@ "Alias": "l" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if smt_on else f ) ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Backend;TmaL2;Compute" }, { @@ -2828,9 +2800,33 @@ "Formula": "100 * ( a / ( b ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PARTIAL_RAT_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueSO", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, { "MetricName": "Ports_Utilization", "LegacyName": "metric_TMA_....Ports_Utilization(%)", @@ -2844,52 +2840,67 @@ "Alias": "a" }, { - "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", "Alias": "b" }, { - "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", "Alias": "c" }, { - "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "d" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "UOPS_ISSUED.ANY", "Alias": "e" }, { - "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", "Alias": "f" }, { - "Name": "ARITH.DIVIDER_ACTIVE", + "Name": "INT_MISC.RECOVERY_CYCLES", "Alias": "g" }, { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "Alias": "h" }, { - "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", "Alias": "i" - } - ], - "Constants": [ + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "m" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "n" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "o" } ], - "Formula": "100 * ( ( a + ( b + ( ( c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * f ) ) / ( e ) if ( g < ( h - i ) ) else ( b + ( ( c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) * f ) / ( e ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a + ( ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( ( ( h + i ) / ( j + ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) + i ) ) * ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) ) ) * n ) / ( d ) * ( j - h ) / ( d ) ) * ( d ) + ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) ) / ( d ) if ( o < ( j - h ) ) else ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) / ( d ) )", "Category": "TMA", "Threshold": "> 15 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2901,64 +2912,67 @@ "UnitOfMeasure": "percent", "Events": [ { - "Name": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "Alias": "a" }, { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", "Alias": "b" }, { - "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", "Alias": "c" }, { - "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "d" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "UOPS_ISSUED.ANY", "Alias": "e" - } - ], - "Constants": [ + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "f" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "g" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / 2 if smt_on else b - c ) / ( ( d / 2 ) if smt_on else ( e ) ) )", - "Category": "TMA", - "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "PortsUtil" - }, - { - "MetricName": "Serializing_Operation", - "LegacyName": "metric_TMA_........Serializing_Operation(%)", - "ParentCategory": "Ports_Utilized_0", - "Level": 5, - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", - "UnitOfMeasure": "percent", - "Events": [ + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "h" + }, { - "Name": "PARTIAL_RAT_STALLS.SCOREBOARD", - "Alias": "a" + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "i" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "b" + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "m" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "n" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( ( a + ( ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( ( ( h + i ) / ( j + ( k + ( ( l ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) * m ) + i ) ) * ( 1 - ( b / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) - ( e + ( 4 ) * ( ( f / 2 ) if ( 1 ) else g ) ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) ) ) * n ) / ( d ) * ( j - h ) / ( d ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueSO", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 20 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -2966,27 +2980,23 @@ "LegacyName": "metric_TMA_........Mixing_Vectors(%)", "ParentCategory": "Ports_Utilized_0", "Level": 5, - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", "UnitOfMeasure": "percent", "Events": [ - { - "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "a" - }, { "Name": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "Alias": "b" + "Alias": "a" }, { "Name": "UOPS_ISSUED.ANY", - "Alias": "c" + "Alias": "b" } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) * b / c ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( a / b ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5; $issueMV", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3018,20 +3028,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else c ) / ( ( d / 2 ) if smt_on else ( e ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else c ) / ( ( d / 2 ) if ( 1 ) else ( e ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueL1", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3063,20 +3064,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a - b ) / 2 if smt_on else c ) / ( ( d / 2 ) if smt_on else ( e ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a - b ) / 2 if ( 1 ) else c ) / ( ( d / 2 ) if ( 1 ) else ( e ) ) )", "Category": "TMA", "Threshold": "> 15 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3100,20 +3092,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a / 2 if smt_on else a ) / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( ( a / 2 if ( 1 ) else a ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", - "Threshold": "> 70 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { @@ -3149,20 +3132,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 40", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3186,20 +3160,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -3223,20 +3188,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3260,20 +3216,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3281,7 +3228,7 @@ "LegacyName": "metric_TMA_..........Port_6(%)", "ParentCategory": "ALU_Op_Utilization", "Level": 6, - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "UnitOfMeasure": "percent", "Events": [ { @@ -3297,20 +3244,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3346,20 +3284,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if smt_on else ( f ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a + b + c - d ) / ( 2 * ( ( e / 2 ) if ( 1 ) else ( f ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3383,20 +3312,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3420,20 +3340,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3457,20 +3368,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3494,20 +3396,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issueSpSt", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3531,20 +3424,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( a / ( ( b / 2 ) if smt_on else ( c ) ) )", + "Constants": [], + "Formula": "100 * ( a / ( ( b / 2 ) if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -3567,20 +3451,11 @@ "Alias": "c" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "(> 70 | Heavy_Operations)", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "TmaL1" }, { @@ -3588,7 +3463,7 @@ "LegacyName": "metric_TMA_..Light_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3612,20 +3487,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) )", "Category": "TMA", "Threshold": "> 60", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -3665,20 +3531,11 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * d / e ) + ( ( f ) / ( a ) ) + ( min( ( ( g ) / ( a ) ) , ( 1 ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * d / e ) + ( ( f ) / ( a ) ) + ( min( ( ( g ) / ( a ) ) , ( 1.0 ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "HPC" }, { @@ -3710,20 +3567,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * d / e )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * d / e )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute" }, { @@ -3747,7 +3595,7 @@ "Formula": "100 * ( ( a ) / ( b ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3768,10 +3616,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a ) / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a ) / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3796,10 +3644,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3824,10 +3672,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3852,10 +3700,10 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( c ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, { @@ -3863,7 +3711,7 @@ "LegacyName": "metric_TMA_....Memory_Operations(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", "UnitOfMeasure": "percent", "Events": [ { @@ -3891,20 +3739,11 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * f / e )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * f / e )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { @@ -3912,7 +3751,7 @@ "LegacyName": "metric_TMA_....Fused_Instructions(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", "UnitOfMeasure": "percent", "Events": [ { @@ -3936,21 +3775,12 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * d / ( a ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * d / ( a ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" }, { "MetricName": "Non_Fused_Branches", @@ -3985,28 +3815,19 @@ "Alias": "f" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( f - d ) / ( a ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( f - d ) / ( a ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" }, { - "MetricName": "Nop_Instructions", - "LegacyName": "metric_TMA_....Nop_Instructions(%)", + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "UnitOfMeasure": "percent", "Events": [ { @@ -4030,32 +3851,43 @@ "Alias": "e" }, { - "Name": "INST_RETIRED.NOP", + "Name": "UOPS_EXECUTED.X87", "Alias": "f" - } - ], - "Constants": [ + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "i" + }, + { + "Name": "MEM_INST_RETIRED.ANY", + "Alias": "j" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "k" } ], - "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * f / ( a ) )", + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) - ( ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * f / g ) + ( ( h ) / ( a ) ) + ( min( ( ( i ) / ( a ) ) , ( 1.0 ) ) ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * j / e ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * d / ( a ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( k - d ) / ( a ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 30 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { - "MetricName": "Other_Light_Ops", - "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", "ParentCategory": "Light_Operations", - "Level": 3, - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", "UnitOfMeasure": "percent", "Events": [ { @@ -4078,49 +3910,16 @@ "Name": "INST_RETIRED.ANY", "Alias": "e" }, - { - "Name": "UOPS_EXECUTED.X87", - "Alias": "f" - }, - { - "Name": "UOPS_EXECUTED.THREAD", - "Alias": "g" - }, - { - "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", - "Alias": "h" - }, - { - "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", - "Alias": "i" - }, - { - "Name": "MEM_INST_RETIRED.ANY", - "Alias": "j" - }, - { - "Name": "BR_INST_RETIRED.ALL_BRANCHES", - "Alias": "k" - }, { "Name": "INST_RETIRED.NOP", - "Alias": "l" - } - ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Alias": "f" } ], - "Formula": "100 * ( max( 0 , ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) - ( ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) * f / g ) + ( ( h ) / ( a ) ) + ( min( ( ( i ) / ( a ) ) , ( 1 ) ) ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * j / e ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * d / ( a ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * ( k - d ) / ( a ) ) + ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if smt_on else ( c ) ) ) ) ) * l / ( a ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) + d - e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * f / ( a ) )", "Category": "TMA", - "Threshold": "> 30 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "Threshold": "> 10 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { @@ -4128,7 +3927,7 @@ "LegacyName": "metric_TMA_..Heavy_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -4152,20 +3951,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) )", "Category": "TMA", "Threshold": "> 10", - "ResolutionLevels": " CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "Retire;TmaL2" }, { @@ -4205,20 +3995,11 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) - ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( ( a ) + b - c ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueD0", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { @@ -4250,20 +4031,11 @@ "Alias": "e" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) )", + "Constants": [], + "Formula": "100 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueMC; $issueMS", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "MicroSeq" }, { @@ -4291,21 +4063,40 @@ "Alias": "d" } ], - "Constants": [ + "Constants": [], + "Formula": "100 * ( min( ( ( 34 ) * ( a + b ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "FP_ASSIST.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], - "Formula": "100 * ( min( ( ( 100 ) * ( a + b ) / ( ( 4 ) * ( ( c / 2 ) if smt_on else ( d ) ) ) ) , ( 1 ) ) )", + "Constants": [], + "Formula": "100 * ( 34 * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "Threshold": "> 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" }, { "MetricName": "CISC", @@ -4344,126 +4135,4482 @@ "Alias": "g" } ], - "Constants": [ - { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" - }, - { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) - ( min( ( ( 100 ) * ( f + g ) / ( ( 4 ) * ( ( d / 2 ) if smt_on else ( e ) ) ) ) , ( 1 ) ) ) ) )", + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) - ( min( ( ( 34 ) * ( f + g ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) , ( 1.0 ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { - "MetricName": "Info_Core_IpMispredict", - "LegacyName": "metric_TMA_Info_Core_IpMispredict", + "MetricName": "Info_Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Info_Bottleneck_Mispredictions", "Level": 1, - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UOPS_RETIRED.RETIRE_SLOTS", "Alias": "a" }, { - "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Name": "UOPS_ISSUED.ANY", "Alias": "b" - } - ], - "Constants": [], - "Formula": "a / b", - "Category": "TMA", - "Threshold": "< 200", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Bad;BadSpec;BrMispredicts" - }, - { - "MetricName": "Info_Core_CoreIPC", - "LegacyName": "metric_TMA_Info_Core_CoreIPC", - "Level": 1, - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "UnitOfMeasure": "", - "Events": [ + }, { - "Name": "INST_RETIRED.ANY", - "Alias": "a" + "Name": "IDQ.MS_UOPS", + "Alias": "c" }, { "Name": "CPU_CLK_UNHALTED.THREAD_ANY", - "Alias": "b" + "Alias": "d" }, { "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "c" - } - ], - "Constants": [ + "Alias": "e" + }, { - "Name": "HYPERTHREADING_ON", - "Alias": "smt_on" + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" }, { - "Name": "THREADS_PER_CORE", - "Alias": "threads" - } - ], - "Formula": "a / ( ( b / 2 ) if smt_on else ( c ) )", - "Category": "TMA", - "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Ret;SMT;TmaL1" - }, - { - "MetricName": "Info_Inst_Mix_IpTB", - "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", - "Level": 1, - "BriefDescription": "Instruction per taken branch", - "UnitOfMeasure": "", - "Events": [ + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "g" + }, { - "Name": "INST_RETIRED.ANY", - "Alias": "a" + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "h" }, { - "Name": "BR_INST_RETIRED.NEAR_TAKEN", - "Alias": "b" + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "m" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "n" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "o" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "p" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "q" + }, + { + "Name": "DECODE.LCP", + "Alias": "r" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( ( 9 ) * p / ( e ) ) ) + ( min( ( ( 2 ) * q / ( e ) ) , ( 1.0 ) ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Info_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "d" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "e" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "f" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( d / ( c ) ) + ( ( e + 2 * f ) / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( ( 9 ) * g / ( c ) ) ) + ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB" + }, + { + "MetricName": "Info_Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Info_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "e" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "f" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "i" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "k" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "n" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "q" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "r" + }, + { + "Name": "DECODE.LCP", + "Alias": "s" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "t" + }, + { + "Name": "UOPS_RETIRED.MACRO_FUSED", + "Alias": "u" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "v" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "w" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "x" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( 1 - ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( g / ( g + h ) ) * m / ( c ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) + ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) - ( ( ( ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( d ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) * ( ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( g / ( g + h ) ) * m / ( c ) ) * ( 10 * ( ( ( d ) / e ) * f / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - g / ( k - h ) ) , 0.0001 ) ) / ( ( g / ( g + h ) ) * ( ( e - ( d ) + ( 4 ) * ( ( i / 2 ) if ( 1 ) else j ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) / ( ( ( g / ( g + h ) ) * m / ( c ) ) + ( ( 1 - ( g / ( g + h ) ) ) * m / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( ( 9 ) * q / ( c ) ) ) + ( min( ( ( 2 ) * r / ( c ) ) , ( 1.0 ) ) ) + ( s / ( c ) ) + ( t / ( c ) ) ) ) ) - ( 100 * ( ( 4 ) * l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( p / ( c ) ) + ( ( n + 2 * o ) / ( c ) ) + ( ( 9 ) * q / ( c ) ) ) / ( ( ( n + 2 * o ) / ( c ) ) + ( p / ( c ) ) + ( m / ( c ) + ( ( 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( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) + ( ( a_f - a_d ) / ( c ) ) + ( min( ( ( a_d / ( c ) + ( ( a_e - a_f ) / ( c ) ) - ( ( ( a_g * ( 1 + ( a_h / a_i ) ) ) / ( ( a_g * ( 1 + ( a_h / a_i ) ) ) + a_j ) ) * ( ( a_e - a_f ) / ( c ) ) ) ) ) , ( 1.0 ) ) ) + ( z / ( c ) ) ) ) * ( ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) / ( ( ( min( c , a_k ) ) / ( c ) ) + ( ( min( c , a_l ) ) / ( c ) - ( ( min( c , a_k ) ) / ( c ) ) ) ) ) * ( min( ( ( ( ( 110 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_q + ( ( 110 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 20.5 * ( ( ( c ) / a_n ) * a_o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_r ) * ( 1 + ( a_h / a_i ) / 2 ) / ( c ) ) , ( 1.0 ) ) ) / ( ( min( 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/ 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( h / ( c ) + ( ( 9 ) * g / ( c ) ) ) * ( ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( p / ( p + q ) ) * h / ( c ) ) * ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) / ( ( ( p / ( p + q ) ) * h / ( c ) ) + ( ( 1 - ( p / ( p + q ) ) ) * h / ( c ) ) + ( ( 9 ) * g / ( c ) ) ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( d / ( c ) ) + ( h / ( c ) + ( ( 9 ) * g / ( c ) ) ) + ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) + ( 10 * ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( max( ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( 1 - p / ( t - q ) ) , 0.0001 ) ) / ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( p / ( p + q ) ) * ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( 1 - b_u / q ) , 0.0001 ) ) / ( ( max( ( ( ( n - ( m ) + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( 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( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * b_y / ( c ) * ( ( b_x + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * b_y ) / ( c ) * ( a_a - y ) / ( c ) ) ) / ( ( b_v / ( c ) ) + ( b_w / ( c ) ) + ( ( ( ( b_x + ( ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( y + z ) / ( a_a + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) + z ) ) * ( 1 - ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( n + ( 4 ) * ( ( r / 2 ) if ( 1 ) else s ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * b_y ) / ( c ) * ( a_a - y ) / ( c ) ) * ( c ) + ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) ) / ( c ) if ( b_v < ( a_a - y ) ) else ( a_b + ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * a_c ) / ( c ) ) ) ) + ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) + ( 100 * ( ( c_c + c_d ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( 100 * ( ( ( m ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( c_c + c_d ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( w + x ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( m ) / n ) * o / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( m ) + u - v ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a + b ) / ( ( 4 ) * ( ( c / 2 ) if ( 1 ) else ( d ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Bottleneck_Base_Non_Br", + "LegacyName": "metric_TMA_Info_Bottleneck_Base_Non_Br", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.MACRO_FUSED", + "Alias": "h" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "i" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "j" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( d + e ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) / ( ( ( ( ( a ) + h - i ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) + ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( min( ( ( 34 ) * ( j + k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) , ( 1.0 ) ) ) / ( ( ( a ) / f ) * g / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * ( ( ( a ) + h - i ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( 4 ) * ( ( a / 2 ) if ( 1 ) else ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( ( f / 2 ) if ( 1 ) else ( g ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( ( a ) + ( b ) ) / ( 2 * ( ( c / 2 ) if ( 1 ) else ( d ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a / 2 ) if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Botlnk_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "d" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "e" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "m" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "n" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "p" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) / ( ( ( ( m + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * n ) / ( c ) * ( i - g ) / ( c ) ) * ( c ) + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) ) / ( c ) if ( o < ( i - g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) if ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) < ( ( ( ( m + ( ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( ( g + h ) / ( i + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) + h ) ) * ( 1 - ( a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( d + ( 4 ) * ( ( e / 2 ) if ( 1 ) else f ) ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) ) * n ) / ( c ) * ( i - g ) / ( c ) ) * ( c ) + ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) ) / ( c ) if ( o < ( i - g ) ) else ( j + ( ( k ) / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * l ) / ( c ) ) else 1 ) if ( 1 - p / ( q / 2 ) if ( 1 ) else 0 ) > 0.5 else 0", + "Category": "TMA", + "Threshold": "> 50", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( b + 2 * c + 4 * d + 8 * e + 16 * f )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b ) + ( c ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.T0:u0xF", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ASSIST.ANY", + "Alias": "b" + }, + { + "Name": "OTHER_ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "< 100000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( a + b + c )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.COUNT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "a" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b + 2", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 50", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Botlnk_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "d" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "e" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "f" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "i" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "j" + }, + { + "Name": "DECODE.LCP", + "Alias": "k" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "l" + }, + { + "Name": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "Alias": "m" + }, + { + "Name": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "Alias": "n" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "o" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "p" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( d / ( c ) ) / ( ( ( e + 2 * f ) / ( c ) ) + ( g / ( c ) ) + ( h / ( c ) + ( ( 9 ) * i / ( c ) ) ) + ( min( ( ( 2 ) * j / ( c ) ) , ( 1.0 ) ) ) + ( k / ( c ) ) + ( d / ( c ) ) ) + ( ( l / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) - ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) ) * ( ( m - n ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) / 2 ) / ( ( ( m - n ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) / 2 ) + ( ( o - p ) / ( ( b / 2 ) if ( 1 ) else ( c ) ) / 2 ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueFB", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Botlnk_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "d" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "e" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "g" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 4 ) * a / ( ( 4 ) * ( ( b / 2 ) if ( 1 ) else ( c ) ) ) ) * ( ( d + 2 * e ) / ( c ) ) / ( ( ( d + 2 * e ) / ( c ) ) + ( f / ( c ) ) + ( g / ( c ) + ( ( 9 ) * h / ( c ) ) ) + ( min( ( ( 2 ) * i / ( c ) ) , ( 1.0 ) ) ) + ( j / ( c ) ) + ( k / ( c ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueFL", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "BR_MISP_EXEC.INDIRECT", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a ) / ( ( ( b ) / c ) * d )", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.RETIRE_SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "g" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "INT_MISC.RECOVERY_CYCLES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "m" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "n" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "o" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "p" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "q" + }, + { + "Name": "DECODE.LCP", + "Alias": "r" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( ( ( a ) / b ) * c / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( max( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) * ( 1 - f / ( j - g ) ) , 0.0001 ) ) / ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) ) ) * ( ( ( f / ( f + g ) ) * ( ( b - ( a ) + ( 4 ) * ( ( h / 2 ) if ( 1 ) else i ) ) / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) ) + ( ( 4 ) * k / ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) ) * ( ( f / ( f + g ) ) * l / ( e ) ) / ( ( ( m + 2 * n ) / ( e ) ) + ( o / ( e ) ) + ( l / ( e ) + ( ( 9 ) * p / ( e ) ) ) + ( min( ( ( 2 ) * q / ( e ) ) , ( 1.0 ) ) ) + ( r / ( e ) ) + ( s / ( e ) ) ) ) ) * ( ( 4 ) * ( ( d / 2 ) if ( 1 ) else ( e ) ) ) / f / 100", + "Category": "TMA", + "Threshold": "; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NOT_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.CONDITIONAL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NOT_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NOT_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a - ( b - c ) - 2 * d ) / e", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "EPT.WALK_PENDING", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( a + b + c + d ) / ( 2 * ( ( e / 2 ) if ( 1 ) else ( f ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 8 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License0_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License0_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL0_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / 2 / ( ( b / 2 ) if ( 1 ) else ( c ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License1_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License1_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL1_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / 2 / ( ( b / 2 ) if ( 1 ) else ( c ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_Power_License2_Utilization", + "LegacyName": "metric_TMA_Info_System_Power_License2_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CORE_POWER.LVL2_TURBO_LICENSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD_ANY", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / 2 / ( ( b / 2 ) if ( 1 ) else ( c ) ) if ( 1 ) else a / ( ( b / 2 ) if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / ( b / 2 ) if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" } ], "Constants": [], "Formula": "a / b", "Category": "TMA", - "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + "Threshold": "> 0.05", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" }, { - "MetricName": "Info_Memory_L2MPKI", - "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", "Level": 1, - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "UnitOfMeasure": "", "Events": [ { - "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Name": "UNC_M_CAS_COUNT.RD", "Alias": "a" }, { - "Name": "INST_RETIRED.ANY", + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", "Alias": "b" } ], "Constants": [], - "Formula": "1000 * a / b", + "Formula": "a / b", "Category": "TMA", "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Mem;Backend;CacheMisses" + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_RPQ_OCCUPANCY", + "Alias": "a" + }, + { + "Name": "UNC_M_RPQ_INSERTS", + "Alias": "b" + }, + { + "Name": "UNC_M_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Alias": "a" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Alias": "b" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Alias": "c" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b + c + d ) * 4 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Alias": "a" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Alias": "b" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Alias": "c" + }, + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b + c + d ) * 4 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" } ] } \ No newline at end of file diff --git a/SPR/metrics/perf/sapphirerapids_metrics_perf.json b/SPR/metrics/perf/sapphirerapids_metrics_perf.json index b9979e7f..2d311891 100644 --- a/SPR/metrics/perf/sapphirerapids_metrics_perf.json +++ b/SPR/metrics/perf/sapphirerapids_metrics_perf.json @@ -1,4 +1,39 @@ [ + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_RxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_receive_bw", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "CPU operating frequency (in GHz)", "MetricExpr": "( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000", @@ -259,63 +294,49 @@ "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "MetricGroup": "", - "MetricName": "percent_uops_delivered_from_decoded_icache", + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", "ScaleUnit": "100%" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO ) / ( UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO ) )", "MetricGroup": "", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", "ScaleUnit": "100%" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM )", "MetricGroup": "", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time", - "MetricGroup": "", - "MetricName": "llc_miss_local_memory_bandwidth_read", - "ScaleUnit": "1MB/s" - }, - { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time", - "MetricGroup": "", - "MetricName": "llc_miss_local_memory_bandwidth_write", - "ScaleUnit": "1MB/s" - }, - { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time", + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", "MetricGroup": "", - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "MetricName": "percent_uops_delivered_from_decoded_icache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time", + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", "MetricGroup": "", - "MetricName": "llc_miss_remote_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "ScaleUnit": "100%" }, { - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", - "MetricExpr": "( UNC_UPI_RxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", "MetricGroup": "", - "MetricName": "upi_data_receive_bw", - "ScaleUnit": "1MB/s" + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "MetricExpr": "( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) )", "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", @@ -331,14 +352,14 @@ { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", "MetricExpr": "( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", "MetricExpr": "( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "ScaleUnit": "100%" }, @@ -364,31 +385,31 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "MetricExpr": "( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "MetricExpr": "( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "MetricExpr": "( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", "ScaleUnit": "100%" }, { @@ -400,21 +421,21 @@ }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "MetricExpr": "( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricExpr": "( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_mite", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", "MetricName": "tma_decoder0_alone", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )", + "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_dsb", "ScaleUnit": "100%" @@ -433,6 +454,13 @@ "MetricName": "tma_branch_mispredicts", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "( ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) ) + ( 0 * slots )", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", "MetricExpr": "( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) )", @@ -440,6 +468,13 @@ "MetricName": "tma_machine_clears", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) )", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "ScaleUnit": "100%" + }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "MetricExpr": "( ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", @@ -457,7 +492,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", "MetricExpr": "( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "ScaleUnit": "100%" }, @@ -484,21 +519,21 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "MetricExpr": "( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_lock_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "ScaleUnit": "100%" @@ -513,40 +548,40 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "MetricExpr": "( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "DataSharing;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricExpr": "( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "MetricExpr": "( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricExpr": "( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_data_sharing", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "MetricExpr": "( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", "MetricExpr": "( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", "MetricName": "tma_sq_full", @@ -554,13 +589,13 @@ }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_bandwidth", @@ -574,7 +609,7 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", "MetricName": "tma_mem_latency", @@ -582,28 +617,28 @@ }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "MetricExpr": "( min( ( ( ( 108 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 108 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", + "MetricName": "tma_local_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( 186 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 186 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_mem", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "MetricExpr": "( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "Offcore;Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_remote_cache", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", - "MetricExpr": "( min( ( ( ( ( 1 - ( ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) + 33 * ( ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "ScaleUnit": "100%" @@ -617,49 +652,49 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "MetricExpr": "( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricExpr": "( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "MetricExpr": "( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "DataSharing;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricExpr": "( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_false_sharing", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", - "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_split_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", - "MetricExpr": "( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_streaming_stores", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", - "MetricExpr": "( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", "MetricName": "tma_dtlb_store", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) , ( 1 ) ) ) - ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( min( ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) - ( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_hit", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", "MetricName": "tma_store_stlb_miss", "ScaleUnit": "100%" @@ -679,52 +714,66 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "MetricExpr": "( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( 0 * slots )", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "MetricExpr": "( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "MetricExpr": "( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / ( CPU_CLK_UNHALTED.THREAD ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "MetricExpr": "( CPU_CLK_UNHALTED.PAUSE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", - "MetricExpr": "( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "MetricExpr": "( CPU_CLK_UNHALTED.C01 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c01_wait", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", - "MetricExpr": "( CPU_CLK_UNHALTED.PAUSE / ( CPU_CLK_UNHALTED.THREAD ) )", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "MetricExpr": "( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c02_wait", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", - "MetricExpr": "( min( ( 13 * MISC2_RETIRED.LFENCE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricExpr": "( min( ( 13 * MISC2_RETIRED.LFENCE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", "MetricName": "tma_memory_fence", "ScaleUnit": "100%" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "MetricExpr": "( min( ( 160 * ASSISTS.SSE_AVX_MIX / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "MetricExpr": "( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Compute;HPC;Server;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_amx_busy", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations", - "MetricExpr": "( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", - "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_amx_busy", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "MetricExpr": "( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( 0 * slots )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "MetricExpr": "( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricExpr": "( min( ( 160 * ASSISTS.SSE_AVX_MIX / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", "ScaleUnit": "100%" }, { @@ -750,42 +799,42 @@ }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "( ( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6 ) / ( 5 * ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6 ) / ( 5 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_0 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_0 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_0", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_1 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_1 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "( UOPS_DISPATCHED.PORT_6 / ( CPU_CLK_UNHALTED.DISTRIBUTED ) )", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_6 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", "MetricName": "tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "( UOPS_DISPATCHED.PORT_2_3_10 / ( 3 * ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( UOPS_DISPATCHED.PORT_2_3_10 / ( 3 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_load_op_utilization", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "( ( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED ) ) )", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" @@ -798,71 +847,64 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * slots )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_light_operations", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired on AVX stack). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) + ( cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) )", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) ) )", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. Tip: consider compiler flags to generate newer AVX (or SSE) instruction sets; which typically perform better and feature vectors.", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) ) + ( 0 * slots )", "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has executed (retired). May overcount due to FMA double counting.", - "MetricExpr": "( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_fp_scalar", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has executed (retired) aggregated across all vector widths. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_fp_vector", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_128b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_256b", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", - "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", "MetricName": "tma_fp_vector_512b", "ScaleUnit": "100%" }, - { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.", - "MetricExpr": "( cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_amx", - "ScaleUnit": "100%" - }, { "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", - "MetricExpr": "( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) )", + "MetricExpr": "( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_int_operations", "ScaleUnit": "100%" @@ -875,63 +917,56 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", "MetricExpr": "( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", "MetricName": "tma_int_vector_256b", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.", - "MetricExpr": "( cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_L4_group;tma_int_operations_group", - "MetricName": "tma_int_amx", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.", - "MetricExpr": "( INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", - "MetricName": "tma_shuffles", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_memory_operations", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fused_instructions", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_non_fused_branches", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricExpr": "( max( 0 , ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) ) ) + ( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_light_operations_group", "MetricName": "tma_nop_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "( max( 0 , ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) + ( cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) + ( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=0x1@ / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_shuffles_256b", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops. This highly-correlates with the uop length of these instructions/flows.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "MetricExpr": "( ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", @@ -952,8 +987,8 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be hundreds of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. #Link: article for compiler flags of DAZ and FTZ", - "MetricExpr": "( min( ( ( 100 ) * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / ( slots ) ) , ( 1 ) ) )", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "MetricExpr": "( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_assists", "ScaleUnit": "100%" @@ -973,7 +1008,7 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", "MetricExpr": "( 63 * ASSISTS.SSE_AVX_MIX / ( slots ) )", "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_avx_assists", @@ -981,33 +1016,797 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "MetricExpr": "( max( 0 , ( UOPS_RETIRED.MS / ( slots ) ) - ( min( ( ( 100 ) * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / ( slots ) ) , ( 1 ) ) ) ) )", + "MetricExpr": "( max( 0 , ( UOPS_RETIRED.MS / ( slots ) ) - ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) ) )", "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricName": "tma_cisc", "ScaleUnit": "100%" }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_big_code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchBW;Frontend;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "MetricExpr": "( 100 * ( 100 * ( ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "MetricExpr": "( 100 * ( 100 * ( ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Mem;MemoryLat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_cache_memory_latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "( 100 * ( 100 * ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) , ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Mem;MemoryTLB;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_data_tlbs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 108 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 186 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) )", + "MetricGroup": "Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_memory_synchronization" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "MetricExpr": "( 100 * ( 100 * ( ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Cor;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_compute_bound_est" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "MetricExpr": "100 * ( 100 * ( ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) * ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + cpu@RS.EMPTY\\,umask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) * ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) )", + "MetricGroup": "Bad;Cor;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_irregular_overhead" + }, + { + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "MetricExpr": "100 - ( ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( 100 * ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 100 * ( ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) / max( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) , ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) / max( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) , ( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) ) ) ) ) + ( 100 * ( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( ( ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( 108 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 186 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) + ( ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) ) + ( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( min( ( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) ) + ( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) * ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + cpu@RS.EMPTY\\,umask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) * ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) ) + ( 100 * ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) - ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) )", + "MetricGroup": "Cor;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_other_bottlenecks" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_branching_overhead" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) - ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_base_non_br" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "( slots ) / ( TOPDOWN.SLOTS / 2 ) if ( 1 ) else 1", + "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots_utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" + }, { "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.DISTRIBUTED )", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_info_core_coreipc" }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5 ) / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "( 100 * ( 1 - ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) / ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) if ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) < ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) else 1 ) if ( 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0 ) > 0.5 else 0 ) + ( 0 * slots )", + "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_core_bound_likely" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" + }, { "BriefDescription": "Instruction per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", "MetricName": "tma_info_inst_mix_iptb" }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR", + "MetricGroup": "Flops;FpScalar;InsType;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_hp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx512" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / CPU_CLK_UNHALTED.PAUSE_INST", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ippause" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipswpf" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "MicroSeq;Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_strings_cycles" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_ipassist" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@ )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=0x1@", + "MetricGroup": "Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNOWN_BRANCH_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_unknown_branch_cost" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "DSBmiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipdsb_miss_ret" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( max( 0 , ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) ) ) * ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) / ( ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) + ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) ) ) )", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_dsb_misses" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_ic_misses" + }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", "MetricName": "tma_info_bad_spec_ipmispredict" }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( slots ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )", + "MetricGroup": "BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( ( BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES ) )", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_other_branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki_load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Mem;Backend;CacheMisses;TopdownL1;tma_L1_group", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1000 * L2_LINES_OUT.SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l3_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.READS_TO_CORE.ANY_RESPONSE / ( INST_RETIRED.ANY )", + "MetricGroup": "CacheHits;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_any_pki" + }, + { + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.READS_TO_CORE.L3_MISS / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_l3m_pki" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "MetricExpr": "1000 * OCR.MODIFIED_WRITE.ANY_RESPONSE / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_mwrite_any_pki" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "1000 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_bus_lock_pki" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 224 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cha@UNC_CHA_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "MetricExpr": "CPU_CLK_UNHALTED.C0_WAIT / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "C0Wait;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_c0_wait" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( ( cha@UNC_CHA_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( ( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha@UNC_CHA_CLOCKTICKS@ )", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_pmm_read_latency" + }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_dram_read_latency" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_RPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_read_bw" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_WPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_write_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_read_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_write_bw" + }, + { + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1000000", + "MetricGroup": "SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_upi_data_transmit_bw" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" + }, + { + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_offcore_bw" + }, + { + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_l3m_bw" + }, + { + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_dram_bw" } ] \ No newline at end of file diff --git a/SPR/metrics/perf/sapphirerapidshbm_flat_metrics_perf.json b/SPR/metrics/perf/sapphirerapidshbm_flat_metrics_perf.json new file mode 100644 index 00000000..4df713ff --- /dev/null +++ b/SPR/metrics/perf/sapphirerapidshbm_flat_metrics_perf.json @@ -0,0 +1,1766 @@ +[ + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "cpu_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_reads_addressed_to_local_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_reads_addressed_to_remote_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_transmit_bw", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "MetricExpr": "(( UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + UNC_M2M_DIRECTORY_UPDATE.ANY ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "MetricGroup": "", + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO ) / ( UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO ) )", + "MetricGroup": "", + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM )", + "MetricGroup": "", + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "MetricExpr": "( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) )", + "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "MetricExpr": "( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) )", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", + "MetricExpr": "( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_mispredicts_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "MetricExpr": "( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_clears_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "MetricExpr": "( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "MetricExpr": "( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_lcp", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "( max( 0 , ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) ) )", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "MetricExpr": "( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "MetricExpr": "( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "( ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) ) + ( 0 * slots )", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "MetricExpr": "( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) )", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "MetricExpr": "( ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "MetricExpr": "( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "MetricExpr": "( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "MetricExpr": "( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( DTLB_LOAD_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "( DTLB_LOAD_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "MetricExpr": "( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "MetricExpr": "( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "MetricExpr": "( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "MetricExpr": "( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "MetricExpr": "( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to High Bandwidth Memory (HBM) accesses by loads.", + "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) * OCR.DEMAND_DATA_RD.PMM / OCR.READS_TO_CORE.L3_MISS )", + "MetricGroup": "MemoryBound;Offcore;Server;TmaL3mem;TopdownL3;tma_L3_group", + "MetricName": "tma_hbm_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "MetricExpr": "( min( ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) - ( ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) * OCR.DEMAND_DATA_RD.PMM / OCR.READS_TO_CORE.L3_MISS ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group", + "MetricName": "tma_dram_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group", + "MetricName": "tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "MetricExpr": "( INT_MISC.MBA_STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group", + "MetricName": "tma_mba_stalls", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group", + "MetricName": "tma_mem_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "MetricExpr": "( min( ( ( ( 108 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_mem", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 186 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_mem", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "MetricExpr": "( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_pmm_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "MetricExpr": "( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_store_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "MetricExpr": "( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_split_stores", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "MetricExpr": "( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "MetricExpr": "( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "( min( ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) - ( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "MetricExpr": "( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "MetricExpr": "( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "MetricExpr": "( CPU_CLK_UNHALTED.PAUSE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "MetricExpr": "( CPU_CLK_UNHALTED.C01 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c01_wait", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "MetricExpr": "( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c02_wait", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "MetricExpr": "( min( ( 13 * MISC2_RETIRED.LFENCE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_memory_fence", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "MetricExpr": "( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Compute;HPC;Server;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_amx_busy", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "MetricExpr": "( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( 0 * slots )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "MetricExpr": "( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricExpr": "( min( ( 160 * ASSISTS.SSE_AVX_MIX / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "MetricExpr": "( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "MetricExpr": "( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6 ) / ( 5 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_0 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricName": "tma_port_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_1 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricName": "tma_port_1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_6 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricName": "tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "( UOPS_DISPATCHED.PORT_2_3_10 / ( 3 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) ) )", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) ) + ( 0 * slots )", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_fp_scalar", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_fp_vector", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", + "MetricName": "tma_fp_vector_128b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", + "MetricName": "tma_fp_vector_256b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", + "MetricName": "tma_fp_vector_512b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "MetricExpr": "( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_int_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "MetricExpr": "( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_int_vector_128b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "MetricExpr": "( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_int_vector_256b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricExpr": "( max( 0 , ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1.0 ) ) ) ) + ( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_shuffles_256b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "MetricExpr": "( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", + "MetricName": "tma_few_uops_instructions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "MetricExpr": "( UOPS_RETIRED.MS / ( slots ) )", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", + "MetricName": "tma_microcode_sequencer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "MetricExpr": "( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "MetricExpr": "( 99 * ASSISTS.PAGE_FAULT / ( slots ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_page_faults", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "MetricExpr": "( 30 * ASSISTS.FP / ( slots ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", + "MetricExpr": "( 63 * ASSISTS.SSE_AVX_MIX / ( slots ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_avx_assists", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "MetricExpr": "( max( 0 , ( UOPS_RETIRED.MS / ( slots ) ) - ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_big_code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchBW;Frontend;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "MetricExpr": "( 100 * ( 100 * ( ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Cor;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_compute_bound_est" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "MetricExpr": "100 * ( 100 * ( ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) * ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + cpu@RS.EMPTY\\,umask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) * ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) )", + "MetricGroup": "Bad;Cor;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_irregular_overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_branching_overhead" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) - ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1.0 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_base_non_br" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "( slots ) / ( TOPDOWN.SLOTS / 2 ) if ( 1 ) else 1", + "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots_utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_coreipc" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5 ) / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "( 100 * ( 1 - ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) / ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) if ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) < ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) else 1 ) if ( 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0 ) > 0.5 else 0 ) + ( 0 * slots )", + "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_core_bound_likely" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iptb" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR", + "MetricGroup": "Flops;FpScalar;InsType;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_hp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx512" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / CPU_CLK_UNHALTED.PAUSE_INST", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ippause" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipswpf" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "MicroSeq;Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_strings_cycles" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_ipassist" + }, + { + "BriefDescription": "i", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@ )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=0x1@", + "MetricGroup": "Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNOWN_BRANCH_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_unknown_branch_cost" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "DSBmiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipdsb_miss_ret" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( max( 0 , ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) ) ) * ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) / ( ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) + ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) ) ) )", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_dsb_misses" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_ic_misses" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1.0 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( slots ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )", + "MetricGroup": "BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( ( BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES ) )", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_other_branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki_load" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1000 * L2_LINES_OUT.SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l3_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.READS_TO_CORE.ANY_RESPONSE / ( INST_RETIRED.ANY )", + "MetricGroup": "CacheHits;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_any_pki" + }, + { + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.READS_TO_CORE.L3_MISS / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_l3m_pki" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "MetricExpr": "1000 * OCR.MODIFIED_WRITE.ANY_RESPONSE / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_mwrite_any_pki" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "1000 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_bus_lock_pki" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 224 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "High-Bandwidth Memory (HBM) accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.DEMAND_DATA_RD.PMM / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_hbm_pki" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cha@UNC_CHA_CLOCKTICKS@ ) / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "MetricExpr": "CPU_CLK_UNHALTED.C0_WAIT / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "C0Wait;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_c0_wait" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( ( cha@UNC_CHA_CLOCKTICKS@ ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( ( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha@UNC_CHA_CLOCKTICKS@ )", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_pmm_read_latency" + }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_dram_read_latency" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_RPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_read_bw" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_WPQ_INSERTS / ( 1000000000 ) ) / ( ( ( duration_time * 1000 ) / 1000 ) ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_write_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_read_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / ( 1000000000 ) / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_write_bw" + }, + { + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1000000", + "MetricGroup": "SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_upi_data_transmit_bw" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" + }, + { + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_offcore_bw" + }, + { + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_l3m_bw" + }, + { + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / ( ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_dram_bw" + }, + { + "BriefDescription": "Average HBM BW for Reads-to-Core. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.DEMAND_DATA_RD.PMM / 1e9 / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "HPC;Mem;MemoryBW;Server;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_hbm_bw" + } +] \ No newline at end of file diff --git a/SPR/metrics/perf/sapphirerapidshbm_only_metrics_perf.json b/SPR/metrics/perf/sapphirerapidshbm_only_metrics_perf.json new file mode 100644 index 00000000..f5ea6a47 --- /dev/null +++ b/SPR/metrics/perf/sapphirerapidshbm_only_metrics_perf.json @@ -0,0 +1,1775 @@ +[ + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_RxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_receive_bw", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000", + "MetricGroup": "", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "", + "MetricName": "cpu_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time", + "MetricGroup": "", + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "itlb_2nd_level_large_page_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "", + "MetricName": "dtlb_2nd_level_store_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_reads_addressed_to_local_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )", + "MetricGroup": "", + "MetricName": "numa_reads_addressed_to_remote_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time", + "MetricGroup": "", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "upi_data_transmit_bw", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "MetricExpr": "(( UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + UNC_M2M_DIRECTORY_UPDATE.ANY ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", + "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", + "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "pmem_memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / 1000000) / duration_time", + "MetricGroup": "", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "MetricGroup": "", + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO ) / ( UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO ) )", + "MetricGroup": "", + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM )", + "MetricGroup": "", + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_decoded_icache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )", + "MetricGroup": "", + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "MetricExpr": "( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) )", + "MetricGroup": "TmaL1;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "MetricExpr": "( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) )", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", + "MetricExpr": "( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_mispredicts_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "MetricExpr": "( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_clears_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "MetricExpr": "( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "MetricExpr": "( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "MetricExpr": "( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_lcp", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "MetricExpr": "( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_dsb_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "MetricExpr": "( max( 0 , ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) ) )", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "MetricExpr": "( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "( ( cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@ ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "MetricExpr": "( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "MetricExpr": "( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "MetricExpr": "( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "( ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) ) + ( 0 * slots )", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "MetricExpr": "( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) )", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) )", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "MetricExpr": "( ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "MetricExpr": "( ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "MetricExpr": "( max( ( EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) , 0 ) )", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "MetricExpr": "( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "( ( min( ( 7 ) * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) - ( DTLB_LOAD_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "( DTLB_LOAD_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "MetricExpr": "( min( ( 13 * LD_BLOCKS.STORE_FORWARD / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "MetricExpr": "( min( ( ( 16 * max( 0 , MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO ) + ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) * ( ( 10 ) * L2_RQSTS.RFO_HIT + ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", + "MetricExpr": "( min( ( ( L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY ) * LD_BLOCKS.NO_SR / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "MetricExpr": "( L1D_PEND_MISS.FB_FULL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "MetricExpr": "( ( MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "MetricExpr": "( min( ( ( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) + ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "MetricExpr": "( min( ( ( ( 79.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * ( 1 - ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / ( OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ) ) ) ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "MetricExpr": "( min( ( ( ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 4 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * ( MEM_LOAD_RETIRED.L3_HIT * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "MetricExpr": "( ( XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group", + "MetricName": "tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "MetricExpr": "( INT_MISC.MBA_STALLS / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group", + "MetricName": "tma_mba_stalls", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "MetricExpr": "( ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) ) / ( CPU_CLK_UNHALTED.THREAD ) - ( ( min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group", + "MetricName": "tma_mem_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "MetricExpr": "( min( ( ( ( 108 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_mem", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( 186 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_mem", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "MetricExpr": "( min( ( ( ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + ( ( 172.5 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) - ( 37 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) ) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD ) * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) / 2 ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "MetricExpr": "( min( ( ( ( ( 1 - ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) / ( ( 19 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 10 * ( ( MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + ( MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS ) ) ) ) ) ) ) * ( MEMORY_ACTIVITY.STALLS_L3_MISS / ( CPU_CLK_UNHALTED.THREAD ) ) ) if ( ( 1000000 ) * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_pmm_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "MetricExpr": "( EXE_ACTIVITY.BOUND_ON_STORES / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "MetricExpr": "( min( ( ( ( MEM_STORE_RETIRED.L2_HIT * ( 10 ) * ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) ) + ( 1 - ( MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES ) ) * ( min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO ) ) ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_store_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "MetricExpr": "( min( ( ( 80 * ( ( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) ) ) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "MetricExpr": "( MEM_INST_RETIRED.SPLIT_STORES / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_split_stores", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "MetricExpr": "( min( ( 9 * OCR.STREAMING_WR.ANY_RESPONSE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "MetricExpr": "( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "( min( ( ( min( ( ( ( 7 ) * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) ) - ( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "( min( ( DTLB_STORE_MISSES.WALK_ACTIVE / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) , ( 1 ) ) )", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "MetricExpr": "( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Backend;TmaL2;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "MetricExpr": "( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "MetricExpr": "( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "MetricExpr": "( CPU_CLK_UNHALTED.PAUSE / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "MetricExpr": "( CPU_CLK_UNHALTED.C01 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c01_wait", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "MetricExpr": "( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c02_wait", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "MetricExpr": "( min( ( 13 * MISC2_RETIRED.LFENCE / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_memory_fence", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "MetricExpr": "( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Compute;HPC;Server;TopdownL3;tma_L3_group;tma_ports_utilized_0_group", + "MetricName": "tma_amx_busy", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "MetricExpr": "( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( 0 * slots )", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "MetricExpr": "( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricExpr": "( min( ( 160 * ASSISTS.SSE_AVX_MIX / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "MetricExpr": "( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "MetricExpr": "( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6 ) / ( 5 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_0 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricName": "tma_port_0", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_1 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricName": "tma_port_1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "( UOPS_DISPATCHED.PORT_6 / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricName": "tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "( UOPS_DISPATCHED.PORT_2_3_10 / ( 3 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "( ( UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8 ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) )", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "MetricExpr": "( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) ) + ( 0 * slots )", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "MetricExpr": "( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_fp_scalar", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_fp_vector", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", + "MetricName": "tma_fp_vector_128b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", + "MetricName": "tma_fp_vector_256b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "MetricExpr": "( min( ( ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) )", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", + "MetricName": "tma_fp_vector_512b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "MetricExpr": "( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_int_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "MetricExpr": "( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_int_vector_128b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "MetricExpr": "( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_int_vector_256b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricExpr": "( max( 0 , ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) - ( ( ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD ) + ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( min( ( ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) , ( 1 ) ) ) ) + ( ( ( INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256 ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * MEM_UOP_RETIRED.ANY / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.MACRO_FUSED / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) + ( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED ) / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) ) ) ) )", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INST_RETIRED.NOP / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "MetricExpr": "( ( max( 0 , ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * INT_VEC_RETIRED.SHUFFLES / ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) )", + "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_shuffles_256b", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "MetricExpr": "( ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) + ( 0 * slots )", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "MetricExpr": "( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", + "MetricName": "tma_few_uops_instructions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "MetricExpr": "( UOPS_RETIRED.MS / ( slots ) )", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", + "MetricName": "tma_microcode_sequencer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "MetricExpr": "( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1 ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "MetricExpr": "( 99 * ASSISTS.PAGE_FAULT / ( slots ) )", + "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_page_faults", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "MetricExpr": "( 30 * ASSISTS.FP / ( slots ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", + "MetricExpr": "( 63 * ASSISTS.SSE_AVX_MIX / ( slots ) )", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_avx_assists", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "MetricExpr": "( max( 0 , ( UOPS_RETIRED.MS / ( slots ) ) - ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1 ) ) ) ) )", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) )", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_big_code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) - ( 100 * ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchBW;Frontend;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "MetricExpr": "( 100 * ( 100 * ( ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) * ( ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.1_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( EXE_ACTIVITY.2_PORTS_UTIL / ( CPU_CLK_UNHALTED.THREAD ) ) + ( UOPS_EXECUTED.CYCLES_GE_3 / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) ) ) ) + ( 0 * slots )", + "MetricGroup": "Cor;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_compute_bound_est" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "MetricExpr": "100 * ( 100 * ( ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) * ( ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) / ( ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ( 1 - ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) + ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) * ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) - ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( 1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + cpu@RS.EMPTY\\,umask\\=0x1@ / ( CPU_CLK_UNHALTED.THREAD ) * ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) / ( ( ARITH.DIV_ACTIVE / ( CPU_CLK_UNHALTED.THREAD ) ) + ( RESOURCE_STALLS.SCOREBOARD / ( CPU_CLK_UNHALTED.THREAD ) + ( CPU_CLK_UNHALTED.C02 / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( EXE.AMX_BUSY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) + ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) )", + "MetricGroup": "Bad;Cor;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_irregular_overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ( 100 * ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_branching_overhead" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * ( 100 * ( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( ( BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL ) / ( slots ) ) - ( ( ( ( UOPS_RETIRED.MS / ( slots ) ) / ( ( max( 0 , ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( UOPS_RETIRED.MS / ( slots ) ) ) ) + ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * ASSISTS.ANY / ( slots ) ) , ( 1 ) ) ) / ( UOPS_RETIRED.MS / ( slots ) ) ) ) * ( topdown\\-heavy\\-ops / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) )", + "MetricGroup": "Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bottleneck_base_non_br" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Ret;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uoppi" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_uptb" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / ( INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Pipeline;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "( slots ) / ( TOPDOWN.SLOTS / 2 ) if ( 1 ) else 1", + "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_slots_utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline;TopdownL1;tma_L1_group", + "MetricName": "tma_info_thread_execute_per_issue" + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;SMT;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_coreipc" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) )", + "MetricGroup": "Ret;Flops;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "MetricExpr": "( FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5 ) / ( 2 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_fp_arith_utilization" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "( 100 * ( 1 - ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) / ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) if ( max( 0 , ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) - ( topdown\\-mem\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) < ( ( ( ( cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu@RS.EMPTY\\,umask\\=0x1@ ) / ( CPU_CLK_UNHALTED.THREAD ) * ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) / ( CPU_CLK_UNHALTED.THREAD ) ) * ( CPU_CLK_UNHALTED.THREAD ) + ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) ) / ( CPU_CLK_UNHALTED.THREAD ) if ( ARITH.DIV_ACTIVE < ( CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS ) ) else ( EXE_ACTIVITY.1_PORTS_UTIL + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@ ) / ( CPU_CLK_UNHALTED.THREAD ) ) else 1 ) if ( 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0 ) > 0.5 else 0 ) + ( 0 * slots )", + "MetricGroup": "Cor;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_core_bound_likely" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipstore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipcall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iptb" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "MetricExpr": "INST_RETIRED.ANY / ( ( FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED2.SCALAR ) + ( cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR ) )", + "MetricGroup": "Flops;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR", + "MetricGroup": "Flops;FpScalar;InsType;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_hp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx256" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF )", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_iparith_avx512" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / CPU_CLK_UNHALTED.PAUSE_INST", + "MetricGroup": "Flops;FpVector;InsType;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ippause" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_ipswpf" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "( ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( slots ) ) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=0x1@", + "MetricGroup": "MicroSeq;Pipeline;Ret;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_strings_cycles" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_ipassist" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per physical core", + "MetricExpr": "UOPS_EXECUTED.THREAD / ( ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if ( 1 ) else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=0x1@ )", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=0x1@", + "MetricGroup": "Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( UOPS_ISSUED.ANY )", + "MetricGroup": "DSB;Fed;FetchBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_coverage" + }, + { + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNOWN_BRANCH_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_unknown_branch_cost" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "DSBmiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\\,cmask\\=0x1\\,edge\\=0x1@", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipdsb_miss_ret" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "( INST_RETIRED.ANY ) / BACLEARS.ANY", + "MetricGroup": "Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "MetricExpr": "1000 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( max( 0 , ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) - ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) ) ) * ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) / ( ( ( IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) + ( ( IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 ) ) ) )", + "MetricGroup": "DSBmiss;Fed;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_dsb_misses" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * ( 100 * ( ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) )", + "MetricGroup": "Fed;FetchLat;IcMiss;TopdownL1;tma_L1_group", + "MetricName": "tma_info_botlnk_ic_misses" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmispredict" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_ipmisp_indirect" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( 100 * ( 1 - ( 10 * ( UOPS_RETIRED.MS / ( slots ) ) * ( max( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) * ( 1 - BR_MISP_RETIRED.ALL_BRANCHES / ( INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT ) ) , 0.0001 ) ) / ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) ) * ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( ( topdown\\-fetch\\-lat / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) ) * ( ( ( topdown\\-br\\-mispredict / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) / ( max( 1 - ( ( topdown\\-fe\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) - INT_MISC.UOP_DROPPING / ( slots ) ) + ( topdown\\-be\\-bound / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) + ( topdown\\-retiring / ( topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound ) ) ) , 0 ) ) ) * INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) / ( ( ICACHE_DATA.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( ICACHE_TAG.STALLS / ( CPU_CLK_UNHALTED.THREAD ) ) + ( INT_MISC.CLEAR_RESTEER_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) + ( INT_MISC.UNKNOWN_BRANCH_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) + ( min( ( ( 3 ) * cpu@UOPS_RETIRED.MS\\,cmask\\=0x1\\,edge\\=0x1@ / ( UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY ) / ( CPU_CLK_UNHALTED.THREAD ) ) , ( 1 ) ) ) + ( DECODE.LCP / ( CPU_CLK_UNHALTED.THREAD ) ) + ( DSB2MITE_SWITCHES.PENALTY_CYCLES / ( CPU_CLK_UNHALTED.THREAD ) ) ) ) ) * ( slots ) / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )", + "MetricGroup": "BrMispredicts;TopdownL1;tma_L1_group", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( ( BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES ) + ( ( BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL ) / BR_INST_RETIRED.ALL_BRANCHES ) )", + "MetricGroup": "Bad;Branches;TopdownL1;tma_L1_group", + "MetricName": "tma_info_branches_other_branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_mlp" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1mpki_load" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheHits;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * ( CPU_CLK_UNHALTED.DISTRIBUTED if ( 1 ) else ( CPU_CLK_UNHALTED.THREAD ) ) )", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_page_walks_utilization" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1000 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "( 64 * L1D.REPLACEMENT / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "( 64 * L2_LINES_IN.ALL / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * LONGEST_LAT_CACHE.MISS / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "( 64 * OFFCORE_REQUESTS.ALL_REQUESTS / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryBW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1000 * L2_LINES_OUT.SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / ( INST_RETIRED.ANY )", + "MetricGroup": "L2Evicts;Mem;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l3_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=0x1@", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_data_l2_mlp" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.READS_TO_CORE.ANY_RESPONSE / ( INST_RETIRED.ANY )", + "MetricGroup": "CacheHits;Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_any_pki" + }, + { + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1000 * OCR.READS_TO_CORE.L3_MISS / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_read_l3m_pki" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "MetricExpr": "1000 * OCR.MODIFIED_WRITE.ANY_RESPONSE / ( INST_RETIRED.ANY )", + "MetricGroup": "Offcore;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_offcore_mwrite_any_pki" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1000 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "1000 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", + "MetricGroup": "Mem;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_bus_lock_pki" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ", + "MetricGroup": "HPC;Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "( 224 ) * ( CPU_CLK_UNHALTED.REF_TSC / #SYSTEM_TSC_FREQ )", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC ) * #SYSTEM_TSC_FREQ / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "Summary;Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "MetricExpr": "( cha@UNC_CHA_CLOCKTICKS@ ) / 1e9 / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "MetricExpr": "( ( 1 * FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( 1000000000 ) ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "Cor;Flops;HPC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_gflops" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD ) / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if ( 1 ) else 0", + "MetricGroup": "SMT;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu@INST_RETIRED.ANY_P@", + "MetricGroup": "OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_kernel_cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "MetricExpr": "CPU_CLK_UNHALTED.C0_WAIT / ( CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "C0Wait;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_c0_wait" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / ( 1000000000 ) ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_dram_bw_use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( ( cha@UNC_CHA_CLOCKTICKS@ ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "Mem;MemoryLat;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_read_latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@", + "MetricGroup": "Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_parallel_reads" + }, + { + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( ( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha@UNC_CHA_CLOCKTICKS@ )", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_pmm_read_latency" + }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "( 1000000000 ) * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mem_dram_read_latency" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_RPQ_INSERTS / ( 1000000000 ) ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_read_bw" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "( ( 64 * UNC_M_PMM_WPQ_INSERTS / ( 1000000000 ) ) / ( ( duration_time * 1000 ) / 1000 ) )", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_pmm_write_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_read_bw" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / ( 1000000000 ) / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "IoBW;MemOffcore;SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_io_write_bw" + }, + { + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1000000", + "MetricGroup": "SoC;Server;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_upi_data_transmit_bw" + }, + { + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_mux" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha@UNC_CHA_CLOCKTICKS@", + "MetricGroup": "SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / cpu@BR_INST_RETIRED.FAR_BRANCH@", + "MetricGroup": "Branches;OS;TopdownL1;tma_L1_group", + "MetricName": "tma_info_system_ipfarbranch" + }, + { + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_offcore_bw" + }, + { + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_l3m_bw" + }, + { + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / ( ( duration_time * 1000 ) / 1000 )", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;TopdownL1;tma_L1_group", + "MetricName": "tma_info_memory_r2c_dram_bw" + } +] \ No newline at end of file diff --git a/SPR/metrics/sapphirerapids_metrics.json b/SPR/metrics/sapphirerapids_metrics.json index 69f99d14..bd2c8c55 100644 --- a/SPR/metrics/sapphirerapids_metrics.json +++ b/SPR/metrics/sapphirerapids_metrics.json @@ -1,12 +1,109 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V", - "DatePublished": "11/09/2023", - "Version": "", - "Legend": "" + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0", + "DatePublished": "01/17/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" }, "Metrics": [ + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_receive_bw", + "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, { "MetricName": "cpu_operating_frequency", "LegacyName": "metric_CPU operating frequency (in GHz)", @@ -937,6 +1034,83 @@ "ResolutionLevels": "CHA, SOCKET, SYSTEM", "MetricGroup": "" }, + { + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, { "MetricName": "percent_uops_delivered_from_decoded_icache", "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", @@ -1030,106 +1204,11 @@ "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, - { - "MetricName": "llc_miss_local_memory_bandwidth_read", - "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", - "Level": 1, - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", - "UnitOfMeasure": "MB/sec", - "Events": [ - { - "Name": "UNC_CHA_REQUESTS.READS_LOCAL", - "Alias": "a" - } - ], - "Constants": [], - "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", - "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" - }, - { - "MetricName": "llc_miss_local_memory_bandwidth_write", - "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", - "Level": 1, - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", - "UnitOfMeasure": "MB/sec", - "Events": [ - { - "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", - "Alias": "a" - } - ], - "Constants": [], - "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", - "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" - }, - { - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", - "Level": 1, - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", - "UnitOfMeasure": "MB/sec", - "Events": [ - { - "Name": "UNC_CHA_REQUESTS.READS_REMOTE", - "Alias": "a" - } - ], - "Constants": [], - "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", - "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" - }, - { - "MetricName": "llc_miss_remote_memory_bandwidth_write", - "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", - "Level": 1, - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", - "UnitOfMeasure": "MB/sec", - "Events": [ - { - "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", - "Alias": "a" - } - ], - "Constants": [], - "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", - "Category": "", - "Threshold": "", - "ResolutionLevels": "CHA, SOCKET, SYSTEM", - "MetricGroup": "" - }, - { - "MetricName": "upi_data_receive_bw", - "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", - "Level": 1, - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", - "UnitOfMeasure": "MB/sec", - "Events": [ - { - "Name": "UNC_UPI_RxL_FLITS.ALL_DATA", - "Alias": "a" - } - ], - "Constants": [], - "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", - "Category": "", - "Threshold": "", - "ResolutionLevels": "UPI, SOCKET, SYSTEM", - "MetricGroup": "" - }, { "MetricName": "Frontend_Bound", "LegacyName": "metric_TMA_Frontend_Bound(%)", "Level": 1, - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "UnitOfMeasure": "percent", "Events": [ { @@ -1230,7 +1309,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;IcMiss" + "MetricGroup": "BigFootprint;FetchLat;IcMiss" }, { "MetricName": "ITLB_Misses", @@ -1254,7 +1333,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB" + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" }, { "MetricName": "Branch_Resteers", @@ -1393,7 +1472,7 @@ "LegacyName": "metric_TMA_......Unknown_Branches(%)", "ParentCategory": "Branch_Resteers", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", "UnitOfMeasure": "percent", "Events": [ { @@ -1410,38 +1489,46 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "BigFoot;FetchLat" + "MetricGroup": "BigFootprint;FetchLat" }, { - "MetricName": "DSB_Switches", - "LegacyName": "metric_TMA_....DSB_Switches(%)", + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Name": "UOPS_RETIRED.MS:c1:e1", "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "UOPS_RETIRED.SLOTS", "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( ( 3 ) * a / ( b / c ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueFB", + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DSBmiss;FetchLat" + "MetricGroup": "FetchLat;MicroSeq" }, { "MetricName": "LCP", "LegacyName": "metric_TMA_....LCP(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", "UnitOfMeasure": "percent", "Events": [ { @@ -1461,52 +1548,28 @@ "MetricGroup": "FetchLat" }, { - "MetricName": "MS_Switches", - "LegacyName": "metric_TMA_....MS_Switches(%)", + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", "ParentCategory": "Fetch_Latency", "Level": 3, - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "UOPS_RETIRED.MS:c1:e1", + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "Alias": "a" }, - { - "Name": "PERF_METRICS.RETIRING", - "Alias": "b" - }, - { - "Name": "PERF_METRICS.FRONTEND_BOUND", - "Alias": "c" - }, - { - "Name": "PERF_METRICS.BAD_SPECULATION", - "Alias": "d" - }, - { - "Name": "PERF_METRICS.BACKEND_BOUND", - "Alias": "e" - }, - { - "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "f" - }, - { - "Name": "UOPS_ISSUED.ANY", - "Alias": "g" - }, { "Name": "CPU_CLK_UNHALTED.THREAD", - "Alias": "h" + "Alias": "b" } ], "Constants": [], - "Formula": "100 * ( min( ( ( 3 ) * a / ( ( ( b / ( c + d + b + e ) ) * ( f ) ) / g ) / ( h ) ) , ( 1 ) ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMS; $issueSO", + "Threshold": "> 5 & P; $issueFB", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "FetchLat;MicroSeq" + "MetricGroup": "DSBmiss;FetchLat" }, { "MetricName": "Fetch_Bandwidth", @@ -1548,7 +1611,7 @@ "Constants": [], "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P & #HighIPC; $issueFB", + "Threshold": "> 20; $issueFB", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "FetchBW;Frontend;TmaL2" }, @@ -1571,12 +1634,16 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a - b ) / ( c ) / 2 )", + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", - "Threshold": "> 10 & P; $issueFB; $issueMI", + "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, @@ -1599,12 +1666,16 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a - b ) / ( c ) / 2 )", + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", - "Threshold": "> 10 & P; $issueFB; $issueMI", + "Threshold": "> 10 & P; $issueD0", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "DSBmiss;FetchBW" }, @@ -1627,10 +1698,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a - b ) / ( c ) / 2 )", + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", "Category": "TMA", "Threshold": "> 15 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -1711,6 +1786,54 @@ "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;BrMispredicts;TmaL2" }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a / ( b + c + d + e ) ) * ( 1 - f / ( g - h ) ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, { "MetricName": "Machine_Clears", "LegacyName": "metric_TMA_..Machine_Clears(%)", @@ -1751,10 +1874,62 @@ "Constants": [], "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueMC", + "Threshold": "> 10 & P; $issueMC; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "BadSpec;MachineClears;TmaL2" }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) ) * ( 1 - h / i ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Machine_Clears" + }, { "MetricName": "Backend_Bound", "LegacyName": "metric_TMA_Backend_Bound(%)", @@ -1846,9 +2021,9 @@ "Constants": [], "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", "Category": "TMA", - "Threshold": "(> 10 & P); $issueL1; $issueMC", + "Threshold": "> 10 & P; $issueL1; $issueMC", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "DTLB_Load", @@ -1964,7 +2139,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2004,7 +2179,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueRFO", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2036,7 +2211,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a / b ) * c / ( d ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a / b ) * c / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2092,7 +2267,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "L3_Bound", @@ -2120,7 +2295,7 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem" + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" }, { "MetricName": "Contested_Accesses", @@ -2173,11 +2348,11 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DataSharing;Offcore" + "MetricGroup": "DataSharing;Offcore;Snoop" }, { "MetricName": "Data_Sharing", @@ -2230,18 +2405,18 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Offcore" + "MetricGroup": "Offcore;Snoop" }, { "MetricName": "L3_Hit_Latency", "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", "UnitOfMeasure": "percent", "Events": [ { @@ -2275,7 +2450,7 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e ) * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueLat; ~overlap", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2286,7 +2461,7 @@ "LegacyName": "metric_TMA_......SQ_Full(%)", "ParentCategory": "L3_Bound", "Level": 4, - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", "UnitOfMeasure": "percent", "Events": [ { @@ -2359,7 +2534,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( a / ( b ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) / ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) + ( 25 * ( ( i * ( 1 + ( d / e ) ) ) ) + 33 * ( ( j * ( 1 + ( d / e ) ) ) ) ) ) ) ) ) * ( a / ( b ) ) ) if ( ( 1000000 ) * ( j + i ) > e ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( a / ( b ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) / ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) + ( 25 * ( i * ( 1 + ( d / e ) ) ) + 33 * ( j * ( 1 + ( d / e ) ) ) ) ) ) ) * ( a / ( b ) ) ) if ( ( 1000000 ) * ( j + i ) > e ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2370,7 +2545,7 @@ "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2418,7 +2593,7 @@ "LegacyName": "metric_TMA_......MEM_Latency(%)", "ParentCategory": "DRAM_Bound", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", "UnitOfMeasure": "percent", "Events": [ { @@ -2442,8 +2617,8 @@ "MetricGroup": "MemoryLat;Offcore" }, { - "MetricName": "Local_DRAM", - "LegacyName": "metric_TMA_........Local_DRAM(%)", + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", @@ -2480,18 +2655,18 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 108 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 108 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Server" }, { - "MetricName": "Remote_DRAM", - "LegacyName": "metric_TMA_........Remote_DRAM(%)", + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2525,18 +2700,18 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( 186 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 186 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Server" + "MetricGroup": "Server;Snoop" }, { "MetricName": "Remote_Cache", "LegacyName": "metric_TMA_........Remote_Cache(%)", "ParentCategory": "MEM_Latency", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", "UnitOfMeasure": "percent", "Events": [ { @@ -2574,11 +2749,11 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Offcore;Server" + "MetricGroup": "Offcore;Server;Snoop" }, { "MetricName": "PMM_Bound", @@ -2630,7 +2805,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( ( 1 - ( ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( ( g * ( 1 + ( b / c ) ) ) ) + 33 * ( ( h * ( 1 + ( b / c ) ) ) ) ) ) ) ) ) * ( i / ( j ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( ( 1 - ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( g * ( 1 + ( b / c ) ) ) + 33 * ( h * ( 1 + ( b / c ) ) ) ) ) ) ) * ( i / ( j ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2690,7 +2865,7 @@ } ], "Constants": [], - "Formula": "100 * ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "Formula": "100 * ( min( ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2727,11 +2902,11 @@ "Alias": "durationtimeinmilliseconds" } ], - "Formula": "100 * ( min( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * e / ( a ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e / ( a ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueSyncxn", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "DataSharing;Offcore" + "MetricGroup": "DataSharing;Offcore;Snoop" }, { "MetricName": "Split_Stores", @@ -2748,10 +2923,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSpSt", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2775,7 +2954,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 9 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 9 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 20 & P; $issueSmSt", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2800,10 +2979,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( min( ( ( ( 7 ) * a + b ) / ( c ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P; $issueTLB", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2828,10 +3011,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( min( ( ( ( 7 ) * a + b ) / ( c ) ) , ( 1 ) ) ) - ( b / ( c ) ) )", + "Formula": "100 * ( min( ( ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) - ( min( ( b / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2852,10 +3039,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( a / ( b if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -2922,115 +3113,67 @@ "MetricGroup": "" }, { - "MetricName": "Ports_Utilization", - "LegacyName": "metric_TMA_....Ports_Utilization(%)", - "ParentCategory": "Core_Bound", + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Ports_Utilized_0", "Level": 3, - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Name": "RESOURCE_STALLS.SCOREBOARD", "Alias": "a" }, { - "Name": "RESOURCE_STALLS.SCOREBOARD", + "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "b" }, { - "Name": "CPU_CLK_UNHALTED.THREAD", + "Name": "CPU_CLK_UNHALTED.C02", "Alias": "c" - }, - { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", - "Alias": "d" - }, - { - "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", - "Alias": "e" - }, - { - "Name": "EXE_ACTIVITY.1_PORTS_UTIL", - "Alias": "f" - }, - { - "Name": "PERF_METRICS.RETIRING", - "Alias": "g" - }, - { - "Name": "PERF_METRICS.FRONTEND_BOUND", - "Alias": "h" - }, - { - "Name": "PERF_METRICS.BAD_SPECULATION", - "Alias": "i" - }, - { - "Name": "PERF_METRICS.BACKEND_BOUND", - "Alias": "j" - }, - { - "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", - "Alias": "k" - }, - { - "Name": "ARITH.DIV_ACTIVE", - "Alias": "l" } ], "Constants": [], - "Formula": "100 * ( ( a + ( b / ( c ) ) * ( d - e ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) if ( l < ( d - e ) ) else ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )", + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", "Category": "TMA", - "Threshold": "> 20 & P", + "Threshold": "> 10 & P; $issueSO", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, { - "MetricName": "Ports_Utilized_0", - "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", - "ParentCategory": "Ports_Utilization", + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", "Level": 4, - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Name": "CPU_CLK_UNHALTED.PAUSE", "Alias": "a" }, { "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "b" - }, - { - "Name": "RESOURCE_STALLS.SCOREBOARD", - "Alias": "c" - }, - { - "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", - "Alias": "d" - }, - { - "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", - "Alias": "e" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) * ( d - e ) / ( b ) )", + "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 20 & P", + "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "PortsUtil" + "MetricGroup": "" }, { - "MetricName": "Serializing_Operation", - "LegacyName": "metric_TMA_........Serializing_Operation(%)", - "ParentCategory": "Ports_Utilized_0", - "Level": 5, - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "MetricName": "C01_WAIT", + "LegacyName": "metric_TMA_......C01_WAIT(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", "UnitOfMeasure": "percent", "Events": [ { - "Name": "RESOURCE_STALLS.SCOREBOARD", + "Name": "CPU_CLK_UNHALTED.C01", "Alias": "a" }, { @@ -3041,20 +3184,20 @@ "Constants": [], "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 10 & P; $issueSO", + "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "MetricGroup": "C0Wait" }, { - "MetricName": "Slow_Pause", - "LegacyName": "metric_TMA_..........Slow_Pause(%)", + "MetricName": "C02_WAIT", + "LegacyName": "metric_TMA_......C02_WAIT(%)", "ParentCategory": "Serializing_Operation", - "Level": 6, - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", "UnitOfMeasure": "percent", "Events": [ { - "Name": "CPU_CLK_UNHALTED.PAUSE", + "Name": "CPU_CLK_UNHALTED.C02", "Alias": "a" }, { @@ -3067,13 +3210,13 @@ "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "MetricGroup": "C0Wait" }, { "MetricName": "Memory_Fence", - "LegacyName": "metric_TMA_..........Memory_Fence(%)", + "LegacyName": "metric_TMA_......Memory_Fence(%)", "ParentCategory": "Serializing_Operation", - "Level": 6, + "Level": 4, "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", "UnitOfMeasure": "percent", "Events": [ @@ -3087,59 +3230,163 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 5 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { - "MetricName": "Mixing_Vectors", - "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", "ParentCategory": "Ports_Utilized_0", - "Level": 5, - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", "UnitOfMeasure": "percent", "Events": [ { - "Name": "ASSISTS.SSE_AVX_MIX", + "Name": "EXE.AMX_BUSY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 50 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;HPC;Server" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", "Alias": "a" }, + { + "Name": "RS.EMPTY:u1", + "Alias": "b" + }, { "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "k" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "l" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a + b ) / ( c ) * ( d - e ) / ( c ) ) * ( c ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) if ( l < ( d - e ) ) else ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 15 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "RS.EMPTY:u1", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "e" } ], "Constants": [], - "Formula": "100 * ( min( ( 160 * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( ( a + b ) / ( c ) * ( d - e ) / ( c ) )", "Category": "TMA", - "Threshold": "> 5", + "Threshold": "> 20 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "" + "MetricGroup": "PortsUtil" }, { - "MetricName": "AMX_Busy", - "LegacyName": "metric_TMA_........AMX_Busy(%)", + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", "ParentCategory": "Ports_Utilized_0", "Level": 5, - "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations", + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "EXE.AMX_BUSY", + "Name": "ASSISTS.SSE_AVX_MIX", "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Name": "CPU_CLK_UNHALTED.THREAD", "Alias": "b" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( min( ( 160 * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 50 & P", + "Threshold": "> 5; $issueMV", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Compute;HPC;Server" + "MetricGroup": "" }, { "MetricName": "Ports_Utilized_1", @@ -3185,7 +3432,7 @@ "Constants": [], "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 20 & P; $issue2P", + "Threshold": "> 15 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, @@ -3209,7 +3456,7 @@ "Constants": [], "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 70 & P", + "Threshold": "> 40 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "PortsUtil" }, @@ -3240,12 +3487,16 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" } ], "Constants": [], - "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e ) ) )", + "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e if ( 1 ) else ( f ) ) ) )", "Category": "TMA", - "Threshold": "> 60", + "Threshold": "> 40", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, @@ -3264,10 +3515,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3288,10 +3543,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3302,7 +3561,7 @@ "LegacyName": "metric_TMA_..........Port_6(%)", "ParentCategory": "ALU_Op_Utilization", "Level": 6, - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", "UnitOfMeasure": "percent", "Events": [ { @@ -3312,10 +3571,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( b ) )", + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", "Category": "TMA", "Threshold": "> 60; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3336,10 +3599,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( a / ( 3 * ( b ) ) )", + "Formula": "100 * ( a / ( 3 * ( b if ( 1 ) else ( c ) ) ) )", "Category": "TMA", "Threshold": "> 60", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3364,10 +3631,14 @@ { "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" } ], "Constants": [], - "Formula": "100 * ( ( a + b ) / ( 4 * ( c ) ) )", + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if ( 1 ) else ( d ) ) ) )", "Category": "TMA", "Threshold": "> 60", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3409,7 +3680,7 @@ "LegacyName": "metric_TMA_..Light_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -3445,7 +3716,7 @@ "LegacyName": "metric_TMA_....FP_Arith(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired on AVX stack). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "UnitOfMeasure": "percent", "Events": [ { @@ -3473,7 +3744,7 @@ "Alias": "f" }, { - "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Name": "FP_ARITH_INST_RETIRED.SCALAR", "Alias": "g" }, { @@ -3485,20 +3756,16 @@ "Alias": "i" }, { - "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0x3c", + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", "Alias": "j" }, { "Name": "FP_ARITH_INST_RETIRED2.VECTOR", "Alias": "k" - }, - { - "Name": "AMX_OPS_RETIRED.BF16:c1", - "Alias": "l" } ], "Constants": [], - "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( min( ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) , ( 1 ) ) ) + ( l / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) )", + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( min( ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) , ( 1.0 ) ) ) )", "Category": "TMA", "Threshold": "> 20 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3509,7 +3776,7 @@ "LegacyName": "metric_TMA_......X87_Use(%)", "ParentCategory": "FP_Arith", "Level": 4, - "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. Tip: consider compiler flags to generate newer AVX (or SSE) instruction sets; which typically perform better and feature vectors.", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "UnitOfMeasure": "percent", "Events": [ { @@ -3549,11 +3816,11 @@ "LegacyName": "metric_TMA_......FP_Scalar(%)", "ParentCategory": "FP_Arith", "Level": 4, - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has executed (retired). May overcount due to FMA double counting.", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", + "Name": "FP_ARITH_INST_RETIRED.SCALAR", "Alias": "a" }, { @@ -3584,7 +3851,7 @@ "Constants": [], "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", + "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, @@ -3593,11 +3860,11 @@ "LegacyName": "metric_TMA_......FP_Vector(%)", "ParentCategory": "FP_Arith", "Level": 4, - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has executed (retired) aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0x3c", + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", "Alias": "a" }, { @@ -3626,9 +3893,9 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1.0 ) ) )", "Category": "TMA", - "Threshold": "> 20 & P", + "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, @@ -3674,7 +3941,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3722,7 +3989,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3770,52 +4037,12 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P; $issue2P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Compute;Flops" }, - { - "MetricName": "FP_AMX", - "LegacyName": "metric_TMA_......FP_AMX(%)", - "ParentCategory": "FP_Arith", - "Level": 4, - "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.", - "UnitOfMeasure": "percent", - "Events": [ - { - "Name": "AMX_OPS_RETIRED.BF16:c1", - "Alias": "a" - }, - { - "Name": "PERF_METRICS.RETIRING", - "Alias": "b" - }, - { - "Name": "PERF_METRICS.FRONTEND_BOUND", - "Alias": "c" - }, - { - "Name": "PERF_METRICS.BAD_SPECULATION", - "Alias": "d" - }, - { - "Name": "PERF_METRICS.BACKEND_BOUND", - "Alias": "e" - }, - { - "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "f" - } - ], - "Constants": [], - "Formula": "100 * ( a / ( ( b / ( c + d + b + e ) ) * ( f ) ) )", - "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Compute;Flops;HPC;Pipeline;Server" - }, { "MetricName": "Int_Operations", "LegacyName": "metric_TMA_....Int_Operations(%)", @@ -3863,18 +4090,10 @@ { "Name": "INT_VEC_RETIRED.VNNI_256", "Alias": "j" - }, - { - "Name": "INT_VEC_RETIRED.SHUFFLES", - "Alias": "k" - }, - { - "Name": "AMX_OPS_RETIRED.INT8:c1", - "Alias": "l" } ], "Constants": [], - "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( k / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( l / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", + "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -3929,7 +4148,7 @@ "LegacyName": "metric_TMA_......Int_Vector_256b(%)", "ParentCategory": "Int_Operations", "Level": 4, - "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", "UnitOfMeasure": "percent", "Events": [ { @@ -3973,91 +4192,99 @@ "MetricGroup": "Compute;IntVector;Pipeline" }, { - "MetricName": "Int_AMX", - "LegacyName": "metric_TMA_......Int_AMX(%)", - "ParentCategory": "Int_Operations", - "Level": 4, - "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.", + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "AMX_OPS_RETIRED.INT8:c1", + "Name": "PERF_METRICS.RETIRING", "Alias": "a" }, { - "Name": "PERF_METRICS.RETIRING", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "b" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "c" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "PERF_METRICS.BACKEND_BOUND", "Alias": "d" }, { - "Name": "PERF_METRICS.BACKEND_BOUND", + "Name": "PERF_METRICS.HEAVY_OPERATIONS", "Alias": "e" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "MEM_UOP_RETIRED.ANY", "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" } ], "Constants": [], - "Formula": "100 * ( a / ( ( b / ( c + d + b + e ) ) * ( f ) ) )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server" + "MetricGroup": "Pipeline" }, { - "MetricName": "Shuffles", - "LegacyName": "metric_TMA_......Shuffles(%)", - "ParentCategory": "Int_Operations", - "Level": 4, - "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.", + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", "UnitOfMeasure": "percent", "Events": [ { - "Name": "INT_VEC_RETIRED.SHUFFLES", + "Name": "PERF_METRICS.RETIRING", "Alias": "a" }, { - "Name": "PERF_METRICS.RETIRING", + "Name": "PERF_METRICS.FRONTEND_BOUND", "Alias": "b" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", + "Name": "PERF_METRICS.BAD_SPECULATION", "Alias": "c" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", + "Name": "PERF_METRICS.BACKEND_BOUND", "Alias": "d" }, { - "Name": "PERF_METRICS.BACKEND_BOUND", + "Name": "PERF_METRICS.HEAVY_OPERATIONS", "Alias": "e" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "INST_RETIRED.MACRO_FUSED", "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" } ], "Constants": [], - "Formula": "100 * ( a / ( ( b / ( c + d + b + e ) ) * ( f ) ) )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "MetricGroup": "Branches;Pipeline" }, { - "MetricName": "Memory_Operations", - "LegacyName": "metric_TMA_....Memory_Operations(%)", + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", "UnitOfMeasure": "percent", "Events": [ { @@ -4081,27 +4308,31 @@ "Alias": "e" }, { - "Name": "MEM_UOP_RETIRED.ANY", + "Name": "BR_INST_RETIRED.ALL_BRANCHES", "Alias": "f" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "INST_RETIRED.MACRO_FUSED", "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" } ], "Constants": [], - "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "MetricGroup": "Branches;Pipeline" }, { - "MetricName": "Fused_Instructions", - "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", "ParentCategory": "Light_Operations", "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "UnitOfMeasure": "percent", "Events": [ { @@ -4125,74 +4356,78 @@ "Alias": "e" }, { - "Name": "INST_RETIRED.MACRO_FUSED", + "Name": "UOPS_EXECUTED.X87", "Alias": "f" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", + "Name": "UOPS_EXECUTED.THREAD", "Alias": "g" - } - ], - "Constants": [], - "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", - "Category": "TMA", - "Threshold": "> 10 & P", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" - }, - { - "MetricName": "Non_Fused_Branches", - "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", - "ParentCategory": "Light_Operations", - "Level": 3, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", - "UnitOfMeasure": "percent", - "Events": [ + }, { - "Name": "PERF_METRICS.RETIRING", - "Alias": "a" + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "h" }, { - "Name": "PERF_METRICS.FRONTEND_BOUND", - "Alias": "b" + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "i" }, { - "Name": "PERF_METRICS.BAD_SPECULATION", - "Alias": "c" + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "j" }, { - "Name": "PERF_METRICS.BACKEND_BOUND", - "Alias": "d" + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "k" }, { - "Name": "PERF_METRICS.HEAVY_OPERATIONS", - "Alias": "e" + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "l" }, { - "Name": "BR_INST_RETIRED.ALL_BRANCHES", - "Alias": "f" + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "m" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "n" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "o" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "p" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "q" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "r" }, { "Name": "INST_RETIRED.MACRO_FUSED", - "Alias": "g" + "Alias": "s" }, { - "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "h" + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "t" } ], "Constants": [], - "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( min( ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) , ( 1.0 ) ) ) ) + ( ( ( m + n ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( o + p + q ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( t - s ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", "Category": "TMA", - "Threshold": "> 10 & P", + "Threshold": "> 30 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "Pipeline" }, { "MetricName": "Nop_Instructions", - "LegacyName": "metric_TMA_....Nop_Instructions(%)", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", "ParentCategory": "Light_Operations", - "Level": 3, + "Level": 4, "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", "UnitOfMeasure": "percent", "Events": [ @@ -4233,11 +4468,11 @@ "MetricGroup": "Pipeline" }, { - "MetricName": "Other_Light_Ops", - "LegacyName": "metric_TMA_....Other_Light_Ops(%)", - "ParentCategory": "Light_Operations", - "Level": 3, - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "MetricName": "Shuffles_256b", + "LegacyName": "metric_TMA_......Shuffles_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", "UnitOfMeasure": "percent", "Events": [ { @@ -4261,95 +4496,27 @@ "Alias": "e" }, { - "Name": "UOPS_EXECUTED.X87", + "Name": "INT_VEC_RETIRED.SHUFFLES", "Alias": "f" }, - { - "Name": "UOPS_EXECUTED.THREAD", - "Alias": "g" - }, - { - "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE:u0x03", - "Alias": "h" - }, - { - "Name": "FP_ARITH_INST_RETIRED2.SCALAR", - "Alias": "i" - }, { "Name": "TOPDOWN.SLOTS:perf_metrics", - "Alias": "j" - }, - { - "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0x3c", - "Alias": "k" - }, - { - "Name": "FP_ARITH_INST_RETIRED2.VECTOR", - "Alias": "l" - }, - { - "Name": "AMX_OPS_RETIRED.BF16:c1", - "Alias": "m" - }, - { - "Name": "INT_VEC_RETIRED.ADD_128", - "Alias": "n" - }, - { - "Name": "INT_VEC_RETIRED.VNNI_128", - "Alias": "o" - }, - { - "Name": "INT_VEC_RETIRED.ADD_256", - "Alias": "p" - }, - { - "Name": "INT_VEC_RETIRED.MUL_256", - "Alias": "q" - }, - { - "Name": "INT_VEC_RETIRED.VNNI_256", - "Alias": "r" - }, - { - "Name": "INT_VEC_RETIRED.SHUFFLES", - "Alias": "s" - }, - { - "Name": "AMX_OPS_RETIRED.INT8:c1", - "Alias": "t" - }, - { - "Name": "MEM_UOP_RETIRED.ANY", - "Alias": "u" - }, - { - "Name": "INST_RETIRED.MACRO_FUSED", - "Alias": "v" - }, - { - "Name": "BR_INST_RETIRED.ALL_BRANCHES", - "Alias": "w" - }, - { - "Name": "INST_RETIRED.NOP", - "Alias": "x" + "Alias": "g" } ], "Constants": [], - "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( min( ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) , ( 1 ) ) ) + ( m / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( ( n + o ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( p + q + r ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( t / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * u / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * v / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( w - v ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * x / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", "Category": "TMA", - "Threshold": "> 30 & P", + "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Pipeline" + "MetricGroup": "HPC;Pipeline" }, { "MetricName": "Heavy_Operations", "LegacyName": "metric_TMA_..Heavy_Operations(%)", "ParentCategory": "Retiring", "Level": 2, - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops. This highly-correlates with the uop length of these instructions/flows.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", "UnitOfMeasure": "percent", "Events": [ { @@ -4420,7 +4587,7 @@ "Constants": [], "Formula": "100 * ( max( 0 , ( a / ( b + c + d + e ) ) - ( f / ( g ) ) ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMI", + "Threshold": "> 5 & P; $issueD0", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, @@ -4444,7 +4611,7 @@ "Constants": [], "Formula": "100 * ( a / ( b ) )", "Category": "TMA", - "Threshold": "> 5 & P; $issueMS", + "Threshold": "> 5 & P; $issueMC; $issueMS", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "MicroSeq" }, @@ -4453,11 +4620,11 @@ "LegacyName": "metric_TMA_......Assists(%)", "ParentCategory": "Microcode_Sequencer", "Level": 4, - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be hundreds of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. #Link: article for compiler flags of DAZ and FTZ", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", "UnitOfMeasure": "percent", "Events": [ { - "Name": "ASSISTS.ANY:u0x1B", + "Name": "ASSISTS.ANY", "Alias": "a" }, { @@ -4466,7 +4633,7 @@ } ], "Constants": [], - "Formula": "100 * ( min( ( ( 100 ) * a / ( b ) ) , ( 1 ) ) )", + "Formula": "100 * ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a / ( b ) ) , ( 1.0 ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", @@ -4492,7 +4659,7 @@ "Constants": [], "Formula": "100 * ( 99 * a / ( b ) )", "Category": "TMA", - "Threshold": "> 10", + "Threshold": "> 5", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, @@ -4525,7 +4692,7 @@ "LegacyName": "metric_TMA_........AVX_Assists(%)", "ParentCategory": "Assists", "Level": 5, - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", "UnitOfMeasure": "percent", "Events": [ { @@ -4561,108 +4728,5048 @@ "Alias": "b" }, { - "Name": "ASSISTS.ANY:u0x1B", + "Name": "ASSISTS.ANY", "Alias": "c" } ], "Constants": [], - "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( min( ( ( 100 ) * c / ( b ) ) , ( 1 ) ) ) ) )", + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c / ( b ) ) , ( 1.0 ) ) ) ) )", "Category": "TMA", "Threshold": "> 10 & P", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", "MetricGroup": "" }, { - "MetricName": "Info_Core_CoreIPC", - "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "MetricName": "Info_Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Info_Bottleneck_Mispredictions", "Level": 1, - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", "UnitOfMeasure": "", "Events": [ { - "Name": "INST_RETIRED.ANY", + "Name": "UOPS_RETIRED.MS", "Alias": "a" }, { - "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Name": "TOPDOWN.SLOTS:perf_metrics", "Alias": "b" - } - ], - "Constants": [], - "Formula": "a / ( b )", - "Category": "TMA", - "Threshold": "", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Ret;SMT;TmaL1" - }, - { - "MetricName": "Info_Inst_Mix_IpTB", - "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", - "Level": 1, - "BriefDescription": "Instruction per taken branch", - "UnitOfMeasure": "", - "Events": [ + }, { - "Name": "INST_RETIRED.ANY", - "Alias": "a" + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" }, { - "Name": "BR_INST_RETIRED.NEAR_TAKEN", - "Alias": "b" - } - ], - "Constants": [], - "Formula": "a / b", - "Category": "TMA", - "Threshold": "< #Pipeline_Width * 2; $issueFB", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" - }, - { - "MetricName": "Info_Bad_Spec_IpMispredict", - "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", - "Level": 1, - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "UnitOfMeasure": "", - "Events": [ + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, { - "Name": "INST_RETIRED.ANY", - "Alias": "a" + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" }, { - "Name": "BR_MISP_RETIRED.ALL_BRANCHES", - "Alias": "b" - } - ], - "Constants": [], - "Formula": "a / b", - "Category": "TMA", - "Threshold": "< 200", - "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Bad;BadSpec;BrMispredicts" - }, - { - "MetricName": "Info_Memory_L2MPKI", - "LegacyName": "metric_TMA_Info_Memory_L2MPKI", - "Level": 1, - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "UnitOfMeasure": "", - "Events": [ + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, { - "Name": "MEM_LOAD_RETIRED.L2_MISS", - "Alias": "a" + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" }, { - "Name": "INST_RETIRED.ANY", - "Alias": "b" - } + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Info_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1.0 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB" + }, + { + "MetricName": "Info_Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Info_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "h" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW;Frontend" + }, + { + "MetricName": "Info_Bottleneck_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Info_Bottleneck_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "a_a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_b" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_d" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_e" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_f" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_g" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_h" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_i" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_j" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_k" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_l" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_m" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_n" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_o" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_p" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_q" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_r" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_s" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_t" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "k" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "l" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "m" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "p" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "q" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "s" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "t" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "u" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "v" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "w" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "x" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "y" + } + ], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) ) * ( ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( p - q ) / ( g ) , 0 ) ) + ( ( q - r ) / ( g ) ) + ( ( r - f ) / ( g ) ) + ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( g ) ) ) ) * ( ( ( min( g , t ) ) / ( g ) ) / ( ( ( min( g , t ) ) / ( g ) ) + ( ( min( g , u ) ) / ( g ) - ( ( min( g , t ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( r - f ) / ( g ) ) / ( ( max( ( p - q ) / ( g ) , 0 ) ) + ( ( q - r ) / ( g ) ) + ( ( r - f ) / ( g ) ) + ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( g ) ) ) ) * ( ( ( v + w ) / ( g ) ) / ( ( min( ( ( ( ( 80 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a * ( a_b / ( a_b + a_c ) ) ) + ( ( 79.5 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_d ) ) * ( 1 + ( i / j ) / 2 ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_e + a_a * ( 1 - ( a_b / ( a_b + a_c ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / x ) * y / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_f * ( 1 + ( i / j ) / 2 ) ) / ( g ) ) , ( 1.0 ) ) ) + ( ( v + w ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( p - q ) / ( g ) , 0 ) ) / ( ( max( ( p - q ) / ( g ) , 0 ) ) + ( ( q - r ) / ( g ) ) + ( ( r - f ) / ( g ) ) + ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( g ) ) ) ) * ( ( a_g / ( g ) ) / ( ( min( ( 7 ) * a_h + a_i , max( a_j - a_k , 0 ) ) / ( g ) ) + ( min( ( 13 * a_l / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , a_m - a_n ) + ( a_m / a_o ) * ( ( 10 ) * a_p + ( min( g , a_q ) ) ) ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( a_r / a_s ) * a_t / ( g ) ) , ( 1.0 ) ) ) + ( a_g / ( g ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBW", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Cache_Memory_Latency", + "LegacyName": "metric_TMA_Info_Bottleneck_Cache_Memory_Latency", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_d" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_e" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_f" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_h" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_i" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_j" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_k" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_l" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_m" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_n" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_o" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_p" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "k" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "l" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "m" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "p" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "q" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "s" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "t" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "u" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "w" + } + ], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) ) * ( ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) / ( ( max( ( p - q ) / ( g ) , 0 ) ) + ( ( q - r ) / ( g ) ) + ( ( r - f ) / ( g ) ) + ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( g ) ) ) ) * ( ( ( min( g , t ) ) / ( g ) - ( ( min( g , u ) ) / ( g ) ) ) / ( ( ( min( g , u ) ) / ( g ) ) + ( ( min( g , t ) ) / ( g ) - ( ( min( g , u ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( r - f ) / ( g ) ) / ( ( max( ( p - q ) / ( g ) , 0 ) ) + ( ( q - r ) / ( g ) ) + ( ( r - f ) / ( g ) ) + ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - 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w , 0 ) ) / ( h ) ) / max( ( max( ( f - g ) / ( h ) , 0 ) ) , ( ( min( ( 7 ) * t + u , max( v - w , 0 ) ) / ( h ) ) + ( min( ( 13 * x / ( h ) ) , ( 1.0 ) ) ) + ( min( ( ( 16 * max( 0 , y - z ) + ( y / a_a ) * ( ( 10 ) * a_b + ( min( h , a_c ) ) ) ) / ( h ) ) , ( 1.0 ) ) ) + ( min( ( ( a_d / a_e ) * a_f / ( h ) ) , ( 1.0 ) ) ) + ( a_g / ( h ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( s / ( h ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( min( ( ( ( j / ( h ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( k * ( 1 + ( l / m ) ) ) + 10 * ( ( n * ( 1 + ( l / m ) ) ) + ( o * ( 1 + ( l / m ) ) ) + ( p * ( 1 + ( l / m ) ) ) ) ) / ( ( 19 * ( k * ( 1 + ( l / m ) ) ) + 10 * ( ( n * ( 1 + ( l / m ) ) ) + ( o * ( 1 + ( l / m ) ) ) + ( p * ( 1 + ( l / m ) ) ) ) ) + ( 25 * ( q * ( 1 + ( l / m ) ) ) + 33 * ( r * ( 1 + ( l / m ) ) ) ) ) ) ) * ( j / ( h ) ) ) if ( ( 1000000 ) * ( r + q ) > m ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( k * ( 1 + ( l / m ) ) ) + 10 * ( ( n * ( 1 + ( l / m ) ) ) + ( o * ( 1 + ( l / m ) ) ) + ( p * ( 1 + ( l / m ) ) ) ) ) / ( ( 19 * ( k * ( 1 + ( l / m ) ) ) + 10 * ( ( n * ( 1 + ( l / m ) ) ) + ( o * ( 1 + ( l / m ) ) ) + ( p * ( 1 + ( l / m ) ) ) ) ) + ( 25 * ( q * ( 1 + ( l / m ) ) ) + 33 * ( r * ( 1 + ( l / m ) ) ) ) ) ) ) * ( j / ( h ) ) ) if ( ( 1000000 ) * ( r + q ) > m ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( h ) ) ) ) * ( ( min( ( ( ( 7 ) * a_h + a_i ) / ( a_j if ( 1 ) else ( h ) ) ) , ( 1.0 ) ) ) / ( ( min( ( ( ( a_k * ( 10 ) * ( 1 - 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( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( g ) ) ) ) * ( ( min( ( ( ( ( 80 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y * ( z / ( z + a_a ) ) ) + ( ( 79.5 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b ) ) * ( 1 + ( i / j ) / 2 ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c + y * ( 1 - ( z / ( z + a_a ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( g ) ) , ( 1.0 ) ) ) ) / ( ( min( ( ( ( ( 80 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y * ( z / ( z + a_a ) ) ) + ( ( 79.5 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b ) ) * ( 1 + ( i / j ) / 2 ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 79.5 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c + y * ( 1 - ( z / ( z + a_a ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 37 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_d * ( 1 + ( i / j ) / 2 ) ) / ( g ) ) , ( 1.0 ) ) ) + ( ( a_e + a_f ) / ( g ) ) ) + ( ( s / ( g ) ) / ( ( max( ( p - q ) / ( g ) , 0 ) ) + ( ( q - r ) / ( g ) ) + ( ( r - f ) / ( g ) ) + ( min( ( ( ( f / ( g ) ) - ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) ) ) , ( 1.0 ) ) ) + ( min( ( ( ( ( 1 - ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) / ( ( 19 * ( h * ( 1 + ( i / j ) ) ) + 10 * ( ( k * ( 1 + ( i / j ) ) ) + ( l * ( 1 + ( i / j ) ) ) + ( m * ( 1 + ( i / j ) ) ) ) ) + ( 25 * ( n * ( 1 + ( i / j ) ) ) + 33 * ( o * ( 1 + ( i / j ) ) ) ) ) ) ) * ( f / ( g ) ) ) if ( ( 1000000 ) * ( o + n ) > j ) else 0 ) ) , ( 1.0 ) ) ) + ( s / ( g ) ) ) ) * ( min( ( ( 80 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_g / ( g ) ) , ( 1.0 ) ) ) / ( ( ( min( ( ( ( a_h * ( 10 ) * ( 1 - ( a_i / a_j ) ) ) + ( 1 - ( a_i / a_j ) ) * ( min( g , a_k ) ) ) / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( 80 * ( ( ( g ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_g / ( g ) ) , ( 1.0 ) ) ) + ( a_l / ( a_m if ( 1 ) else ( g ) ) ) + ( min( ( 9 * a_n / ( g ) ) , ( 1.0 ) ) ) + ( min( ( ( ( 7 ) * a_o + a_p ) / ( a_m if ( 1 ) else ( g ) ) ) , ( 1.0 ) ) ) ) - ( min( ( ( ( a_h * ( 10 ) * ( 1 - ( a_i / a_j ) ) ) + ( 1 - ( a_i / a_j ) ) * ( min( g , a_k ) ) ) / ( g ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_q / ( a_r ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_q / ( a_r ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_s / ( b + c + d + e ) ) ) ) * ( 1 - a_t / a_u ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_q / ( a_r ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_s / ( b + c + d + e ) ) ) ) * ( 1 - a_t / a_u ) , 0.0001 ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueTLB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Info_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "l" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "p" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "q" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( f / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( j / ( k if ( 1 ) else ( g ) ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) * ( ( r / ( g ) ) / ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) + ( p / ( g ) ) + ( s / ( g ) ) + ( r / ( g ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueComp", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor" + }, + { + "MetricName": "Info_Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_a" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a_b" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a_d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_f" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a_g" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "a_h" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "a_k" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a_l" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "a_m" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "o" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "p" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "s" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "x" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "y" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "z" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 1 - a / b ) * ( ( ( c / ( d + e + f + g ) - h / ( i ) ) ) * ( ( min( ( ( 3 ) * j / ( k / l ) / ( m ) ) , ( 1.0 ) ) ) + ( n / ( m ) + ( o / ( m ) ) ) * ( ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) / ( ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) + ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( o / ( m ) ) ) ) / ( ( t / ( m ) ) + ( u / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) + ( min( ( ( 3 ) * j / ( k / l ) / ( m ) ) , ( 1.0 ) ) ) + ( v / ( m ) ) + ( w / ( m ) ) ) ) ) + ( 10 * ( x / ( i ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) * ( p / ( d + e + f + g ) ) + ( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - y / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - y / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( g / ( d + e + f + g ) ) - ( z / ( d + e + f + g ) ) ) ) * ( ( a_a / ( m ) + ( a_b / ( m ) ) ) + a_c / ( m ) * ( ( a_d + a_c ) / ( m ) * ( a_e - a_f ) / ( m ) ) ) / ( ( a_g / ( m ) ) + ( a_a / ( m ) + ( a_b / ( m ) ) ) + ( a_h / ( a_i if ( 1 ) else ( m ) ) ) + ( ( ( ( a_d + a_c ) / ( m ) * ( a_e - a_f ) / ( m ) ) * ( m ) + ( a_j + ( f / ( d + e + f + g ) ) * a_k ) ) / ( m ) if ( a_g < ( a_e - a_f ) ) else ( a_j + ( f / ( d + e + f + g ) ) * a_k ) / ( m ) ) ) ) + ( ( ( ( x / ( i ) ) / ( ( max( 0 , ( a_l / ( d + e + f + g ) ) - ( x / ( i ) ) ) ) + ( x / ( i ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a_m / ( i ) ) , ( 1.0 ) ) ) / ( x / ( i ) ) ) ) * ( a_l / ( d + e + f + g ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueMS", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Cor;Ret" + }, + { + "MetricName": "Info_Bottleneck_Other_Bottlenecks", + "LegacyName": "metric_TMA_Info_Bottleneck_Other_Bottlenecks", + "Level": 1, + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "a_a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "a_d" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "a_e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "a_f" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "a_g" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "a_h" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a_j" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a_k" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "a_m" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_n" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_o" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_p" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_q" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "a_t" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_u" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_x" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_y" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_z" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "b_a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b_b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "b_c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "b_d" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "b_e" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b_f" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b_g" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b_h" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "b_i" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "b_j" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "b_k" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b_l" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "b_m" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "b_n" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "b_o" + }, + { + "Name": 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( b_n * ( 10 ) * ( 1 - ( b_f / b_h ) ) ) + ( 1 - ( b_f / b_h ) ) * ( min( i , b_j ) ) ) / ( i ) ) , ( 1.0 ) ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_u / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_u / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( y / ( b + c + d + e ) ) ) ) * ( b_v / ( i ) ) / ( ( b_v / ( i ) ) + ( b_w / ( i ) + ( b_x / ( i ) ) ) + ( b_y / ( b_q if ( 1 ) else ( i ) ) ) + ( ( ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) * ( i ) + ( c_c + ( d / ( b + c + d + e ) ) * c_d ) ) / ( i ) if ( b_v < ( c_b - a_i ) ) else ( c_c + ( d / ( b + c + d + e ) ) * c_d ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( y / ( b + c + d + e ) ) ) ) * ( b_y / ( b_q if ( 1 ) else ( i ) ) ) / ( ( b_v / ( i ) ) + ( b_w / ( i ) + ( b_x / ( i ) ) ) + ( b_y / ( b_q if ( 1 ) else ( i ) ) ) + ( ( ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) * ( i ) + ( c_c + ( d / ( b + c + d + e ) ) * c_d ) ) / ( i ) if ( b_v < ( c_b - a_i ) ) else ( c_c + ( d / ( b + c + d + e ) ) * c_d ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( y / ( b + c + d + e ) ) ) ) * ( ( ( ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) * ( i ) + ( c_c + ( d / ( b + c + d + e ) ) * c_d ) ) / ( i ) if ( b_v < ( c_b - a_i ) ) else ( c_c + ( d / ( b + c + d + e ) ) * c_d ) / ( i ) ) / ( ( b_v / ( i ) ) + ( b_w / ( i ) + ( b_x / ( i ) ) ) + ( b_y / ( b_q if ( 1 ) else ( i ) ) ) + ( ( ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) * ( i ) + ( c_c + ( d / ( b + c + d + e ) ) * c_d ) ) / ( i ) if ( b_v < ( c_b - a_i ) ) else ( c_c + ( d / ( b + c + d + e ) ) * c_d ) / ( i ) ) ) ) * ( ( c_e / ( i ) ) / ( ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) + ( c_c / ( i ) ) + ( c_f / ( i ) ) + ( c_e / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1.0 ) ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1.0 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_u / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_u / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( y / ( b + c + d + e ) ) ) ) * ( ( b_w / ( i ) + ( b_x / ( i ) ) ) + c_a / ( i ) * ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) ) / ( ( b_v / ( i ) ) + ( b_w / ( i ) + ( b_x / ( i ) ) ) + ( b_y / ( b_q if ( 1 ) else ( i ) ) ) + ( ( ( ( b_z + c_a ) / ( i ) * ( c_b - a_i ) / ( i ) ) * ( i ) + ( c_c + ( d / ( b + c + d + e ) ) * c_d ) ) / ( i ) if ( b_v < ( c_b - a_i ) ) else ( c_c + ( d / ( b + c + d + e ) ) * c_d ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_g / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_h / ( g ) ) , ( 1.0 ) ) ) / ( r / ( g ) ) ) ) * ( c_g / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_i + c_j ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_i + c_j ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_g / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_h / ( g ) ) , ( 1.0 ) ) ) / ( r / ( g ) ) ) ) * ( c_g / ( b + c + d + e ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Offcore" + }, + { + "MetricName": "Info_Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a + b ) / ( c ) ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Bottleneck_Base_Non_Br", + "LegacyName": "metric_TMA_Info_Bottleneck_Base_Non_Br", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "i" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + a + d ) ) - ( ( e + f ) / ( g ) ) - ( ( ( ( h / ( g ) ) / ( ( max( 0 , ( i / ( b + c + a + d ) ) - ( h / ( g ) ) ) ) + ( h / ( g ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * j / ( g ) ) , ( 1.0 ) ) ) / ( h / ( g ) ) ) ) * ( i / ( b + c + a + d ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Info_Thread_Slots_Utilization", + "LegacyName": "metric_TMA_Info_Thread_Slots_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:percore", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b / 2 ) if ( 1 ) else 1", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "SMT;TmaL1" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "( ( 1 * a + 2 * b + 4 * c + 8 * d + 16 * e ) ) / ( f if ( 1 ) else ( g ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "FP_ARITH_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "FP_ARITH_DISPATCHED.PORT_5", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 2 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Botlnk_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "f" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "l" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "o" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) / ( ( ( ( f + g ) / ( h ) * ( i - j ) / ( h ) ) * ( h ) + ( k + ( d / ( b + c + d + a ) ) * l ) ) / ( h ) if ( m < ( i - j ) ) else ( k + ( d / ( b + c + d + a ) ) * l ) / ( h ) ) if ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) < ( ( ( ( f + g ) / ( h ) * ( i - j ) / ( h ) ) * ( h ) + ( k + ( d / ( b + c + d + a ) ) * l ) ) / ( h ) if ( m < ( i - j ) ) else ( k + ( d / ( b + c + d + a ) ) * l ) / ( h ) ) else 1 ) if ( 1 - n / o if ( 1 ) else 0 ) > 0.5 else 0", + "Category": "TMA", + "Threshold": "> 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( ( 1 * b + 2 * c + 4 * d + 8 * e + 16 * f ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( ( b + c ) + ( d + e ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_HP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType;Server" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.T0:u0xF", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_Strings_Cycles", + "LegacyName": "metric_TMA_Info_Pipeline_Strings_Cycles", + "Level": 1, + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.1", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_Unknown_Branch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "ICACHE_DATA.STALLS:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Botlnk_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "o" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "p" + }, + { + "Name": "DECODE.LCP", + "Alias": "q" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "t" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "u" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( j / ( i ) ) + ( k / ( i ) ) + ( l / ( i ) + ( m / ( i ) ) ) + ( min( ( ( 3 ) * n / ( o / p ) / ( i ) ) , ( 1.0 ) ) ) + ( q / ( i ) ) + ( h / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( ( r - s ) / ( t if ( 1 ) else ( i ) ) / 2 ) / ( ( ( r - s ) / ( t if ( 1 ) else ( i ) ) / 2 ) + ( ( u - v ) / ( t if ( 1 ) else ( i ) ) / 2 ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Botlnk_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) + ( l / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1.0 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueFL", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Ret", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Ret", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 500", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / h / 100", + "Category": "TMA", + "Threshold": "; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a - b - 2 * c ) / d", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Other_Branches", + "LegacyName": "metric_TMA_Info_Branches_Other_Branches", + "Level": 1, + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "1 - ( ( a / b ) + ( c / b ) + ( ( d + e ) / b ) + ( ( f - c - 2 * d ) / b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 4 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L3_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L3_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_Read_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_Read_L3M_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_L3M_PKI", + "Level": 1, + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_MWrite_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_MWrite_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Info_Memory_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_Bus_Lock_PKI", + "LegacyName": "metric_TMA_Info_Memory_Bus_Lock_PKI", + "Level": 1, + "BriefDescription": "\"Bus lock\" per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "SQ_MISC.BUS_LOCK", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 224 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( ( 1 * a + 2 * b + 4 * c + 8 * d + 16 * e ) ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / b if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_C0_Wait", + "LegacyName": "metric_TMA_Info_System_C0_Wait", + "Level": 1, + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C0_WAIT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } ], "Constants": [], - "Formula": "1000 * a / b", + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_PMM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_PMM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( ( 1000000000 ) * ( a / b ) / c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Read_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Read_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Write_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Write_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_UPI_Data_Transmit_BW", + "LegacyName": "metric_TMA_Info_System_UPI_Data_Transmit_BW", + "Level": 1, + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a * 64 / 9 / 1000000", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "SoC;Server" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" + }, + { + "MetricName": "Info_Memory_R2C_Offcore_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_Offcore_BW", + "Level": 1, + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_L3M_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_L3M_BW", + "Level": 1, + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_DRAM_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_DRAM_BW", + "Level": 1, + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.DRAM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", "Category": "TMA", "Threshold": "", "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", - "MetricGroup": "Mem;Backend;CacheMisses" + "MetricGroup": "HPC;Mem;MemoryBW;SoC" } ] } \ No newline at end of file diff --git a/SPR/metrics/sapphirerapidshbm_flat_metrics.json b/SPR/metrics/sapphirerapidshbm_flat_metrics.json new file mode 100644 index 00000000..7db6eeeb --- /dev/null +++ b/SPR/metrics/sapphirerapidshbm_flat_metrics.json @@ -0,0 +1,8587 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0", + "DatePublished": "01/12/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_per_instr", + "LegacyName": "metric_loads per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_per_instr", + "LegacyName": "metric_stores per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Level": 1, + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "b / d", + "Category": "", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "LegacyName": "metric_Average LLC demand data read miss to DCPMEM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "LegacyName": "metric_Average LLC demand data read miss to DRAM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_large_page_mpi", + "LegacyName": "metric_ITLB (2nd level) large page MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "LegacyName": "metric_DTLB (2nd level) 2MB large page load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "LegacyName": "metric_memory extra write b/w due to directory updates (MB/sec)", + "Level": 1, + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_DIR_UPDATE.HA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_DIR_UPDATE.TOR", + "Alias": "b" + }, + { + "Name": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "((a + b + c) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_read", + "LegacyName": "metric_DCPMEM_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_write", + "LegacyName": "metric_DCPMEM_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_total", + "LegacyName": "metric_DCPMEM_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + }, + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Level": 1, + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a / (a + b + c + d) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Level": 1, + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (b / (a + b + c + d) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "LegacyName": "metric_% Uops delivered from microcode sequencer (MS)", + "Level": 1, + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c / (a + b + c + d) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( a + b + c + d ) - e / ( f ) )", + "Category": "TMA", + "Threshold": "> 15", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1;PGO" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;IcMiss" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; ~overlap", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat" + }, + { + "MetricName": "Mispredicts_Resteers", + "LegacyName": "metric_TMA_......Mispredicts_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * h / ( i ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts" + }, + { + "MetricName": "Clears_Resteers", + "LegacyName": "metric_TMA_......Clears_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * h / ( i ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueMC", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears" + }, + { + "MetricName": "Unknown_Branches", + "LegacyName": "metric_TMA_......Unknown_Branches(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( 3 ) * a / ( b / c ) / ( d ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DECODE.LCP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW" + }, + { + "MetricName": "Decoder0_Alone", + "LegacyName": "metric_TMA_......Decoder0_Alone(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INST_DECODED.DECODERS:c1", + "Alias": "a" + }, + { + "Name": "INST_DECODED.DECODERS:c2", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueD0", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", + "Category": "TMA", + "Threshold": "> 15 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;FetchBW" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) )", + "Category": "TMA", + "Threshold": "> 15", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a / ( b + c + d + e ) ) * ( 1 - f / ( g - h ) ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueMC; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears;TmaL2" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) ) * ( 1 - h / i ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Machine_Clears" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + a ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueL1; $issueMC", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueTLB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Load_STLB_Hit", + "LegacyName": "metric_TMA_........Load_STLB_Hit(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Load_STLB_Miss", + "LegacyName": "metric_TMA_........Load_STLB_Miss(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueRFO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a / b ) * c / ( d ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 30; $issueBW; $issueSL; $issueSmSt", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DataSharing;Offcore;Snoop" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Snoop" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueLat; ~overlap", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 30 & P; $issueBW", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore" + }, + { + "MetricName": "HBM_Bound", + "LegacyName": "metric_TMA_....HBM_Bound(%)", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to High Bandwidth Memory (HBM) accesses by loads.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_DATA_RD.PMM", + "Alias": "c" + }, + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / d )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;Offcore;Server;TmaL3mem" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_DATA_RD.PMM", + "Alias": "c" + }, + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a / ( b ) ) - ( ( a / ( b ) ) * c / d ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueBW", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore" + }, + { + "MetricName": "MBA_Stalls", + "LegacyName": "metric_TMA_........MBA_Stalls(%)", + "ParentCategory": "MEM_Bandwidth", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.MBA_STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore;Server" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueLat", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat;Offcore" + }, + { + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 108 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server" + }, + { + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 186 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server;Snoop" + }, + { + "MetricName": "Remote_Cache", + "LegacyName": "metric_TMA_........Remote_Cache(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server;Snoop" + }, + { + "MetricName": "PMM_Bound", + "LegacyName": "metric_TMA_....PMM_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "i" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( ( 1 - ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( g * ( 1 + ( b / c ) ) ) + 33 * ( h * ( 1 + ( b / c ) ) ) ) ) ) ) * ( i / ( j ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;Server;TmaL3mem" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat;Offcore" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e / ( a ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DataSharing;Offcore;Snoop" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueSpSt", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 9 * a / ( b ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueSmSt", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueTLB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Store_STLB_Hit", + "LegacyName": "metric_TMA_........Store_STLB_Hit(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) - ( min( ( b / ( c if ( 1 ) else ( d ) ) ) , ( 1.0 ) ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Store_STLB_Miss", + "LegacyName": "metric_TMA_........Store_STLB_Miss(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( a / ( b if ( 1 ) else ( c ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueSO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.PAUSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "C01_WAIT", + "LegacyName": "metric_TMA_......C01_WAIT(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C01", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "C02_WAIT", + "LegacyName": "metric_TMA_......C02_WAIT(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "Memory_Fence", + "LegacyName": "metric_TMA_......Memory_Fence(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC2_RETIRED.LFENCE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE.AMX_BUSY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 50 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;HPC;Server" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "k" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "l" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a + b ) / ( c ) * ( d - e ) / ( c ) ) * ( c ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) if ( l < ( d - e ) ) else ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 15 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) * ( d - e ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 5, + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 160 * a / ( b ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueMV", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Ports_Utilized_1", + "LegacyName": "metric_TMA_......Ports_Utilized_1(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueL1", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_2", + "LegacyName": "metric_TMA_......Ports_Utilized_2(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 15 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_3m", + "LegacyName": "metric_TMA_......Ports_Utilized_3m(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 40 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "ALU_Op_Utilization", + "LegacyName": "metric_TMA_........ALU_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "UOPS_DISPATCHED.PORT_5_11", + "Alias": "c" + }, + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e if ( 1 ) else ( f ) ) ) )", + "Category": "TMA", + "Threshold": "> 40", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Port_0", + "LegacyName": "metric_TMA_..........Port_0(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 60; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute" + }, + { + "MetricName": "Port_1", + "LegacyName": "metric_TMA_..........Port_1(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 60; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Port_6", + "LegacyName": "metric_TMA_..........Port_6(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 60; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Load_Op_Utilization", + "LegacyName": "metric_TMA_........Load_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_2_3_10", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( 3 * ( b if ( 1 ) else ( c ) ) ) )", + "Category": "TMA", + "Threshold": "> 60", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Store_Op_Utilization", + "LegacyName": "metric_TMA_........Store_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_4_9", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_7_8", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if ( 1 ) else ( d ) ) ) )", + "Category": "TMA", + "Threshold": "> 60", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + a + d ) )", + "Category": "TMA", + "Threshold": "(> 70 | Heavy_Operations)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) )", + "Category": "TMA", + "Threshold": "> 60", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( min( ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) , ( 1.0 ) ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, + { + "MetricName": "X87_Use", + "LegacyName": "metric_TMA_......X87_Use(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) * e / f )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute" + }, + { + "MetricName": "FP_Scalar", + "LegacyName": "metric_TMA_......FP_Scalar(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector", + "LegacyName": "metric_TMA_......FP_Vector(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector_128b", + "LegacyName": "metric_TMA_........FP_Vector_128b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector_256b", + "LegacyName": "metric_TMA_........FP_Vector_256b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector_512b", + "LegacyName": "metric_TMA_........FP_Vector_512b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "h" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "i" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Int_Vector_128b", + "LegacyName": "metric_TMA_......Int_Vector_128b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline" + }, + { + "MetricName": "Int_Vector_256b", + "LegacyName": "metric_TMA_......Int_Vector_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "b" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "f" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "i" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "k" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "l" + }, + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "m" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "n" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "o" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "p" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "q" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "r" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "s" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "t" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( min( ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) , ( 1.0 ) ) ) ) + ( ( ( m + n ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( o + p + q ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( t - s ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 30 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Shuffles_256b", + "LegacyName": "metric_TMA_......Shuffles_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INT_VEC_RETIRED.SHUFFLES", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Pipeline" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + e ) ) - ( f / ( g ) ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueD0", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueMC; $issueMS", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq" + }, + { + "MetricName": "Assists", + "LegacyName": "metric_TMA_......Assists(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.ANY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a / ( b ) ) , ( 1.0 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Page_Faults", + "LegacyName": "metric_TMA_........Page_Faults(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 99 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 30 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, + { + "MetricName": "AVX_Assists", + "LegacyName": "metric_TMA_........AVX_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 63 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, + { + "MetricName": "CISC", + "LegacyName": "metric_TMA_......CISC(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c / ( b ) ) , ( 1.0 ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Info_Bottleneck_Mispredictions", + "Level": 1, + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Info_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1.0 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB" + }, + { + "MetricName": "Info_Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Info_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "h" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW;Frontend" + }, + { + "MetricName": "Info_Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Info_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "l" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "p" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "q" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( f / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( j / ( k if ( 1 ) else ( g ) ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) * ( ( r / ( g ) ) / ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) + ( p / ( g ) ) + ( s / ( g ) ) + ( r / ( g ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueComp", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor" + }, + { + "MetricName": "Info_Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_a" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a_b" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a_d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_f" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a_g" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "a_h" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "a_k" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a_l" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "a_m" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "o" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "p" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "s" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "x" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "y" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "z" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 1 - a / b ) * ( ( ( c / ( d + e + f + g ) - h / ( i ) ) ) * ( ( min( ( ( 3 ) * j / ( k / l ) / ( m ) ) , ( 1.0 ) ) ) + ( n / ( m ) + ( o / ( m ) ) ) * ( ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) / ( ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) + ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( o / ( m ) ) ) ) / ( ( t / ( m ) ) + ( u / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) + ( min( ( ( 3 ) * j / ( k / l ) / ( m ) ) , ( 1.0 ) ) ) + ( v / ( m ) ) + ( w / ( m ) ) ) ) ) + ( 10 * ( x / ( i ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) * ( p / ( d + e + f + g ) ) + ( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - y / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - y / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( g / ( d + e + f + g ) ) - ( z / ( d + e + f + g ) ) ) ) * ( ( a_a / ( m ) + ( a_b / ( m ) ) ) + a_c / ( m ) * ( ( a_d + a_c ) / ( m ) * ( a_e - a_f ) / ( m ) ) ) / ( ( a_g / ( m ) ) + ( a_a / ( m ) + ( a_b / ( m ) ) ) + ( a_h / ( a_i if ( 1 ) else ( m ) ) ) + ( ( ( ( a_d + a_c ) / ( m ) * ( a_e - a_f ) / ( m ) ) * ( m ) + ( a_j + ( f / ( d + e + f + g ) ) * a_k ) ) / ( m ) if ( a_g < ( a_e - a_f ) ) else ( a_j + ( f / ( d + e + f + g ) ) * a_k ) / ( m ) ) ) ) + ( ( ( ( x / ( i ) ) / ( ( max( 0 , ( a_l / ( d + e + f + g ) ) - ( x / ( i ) ) ) ) + ( x / ( i ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a_m / ( i ) ) , ( 1.0 ) ) ) / ( x / ( i ) ) ) ) * ( a_l / ( d + e + f + g ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueMS", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Cor;Ret" + }, + { + "MetricName": "Info_Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a + b ) / ( c ) ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Bottleneck_Base_Non_Br", + "LegacyName": "metric_TMA_Info_Bottleneck_Base_Non_Br", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "i" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + a + d ) ) - ( ( e + f ) / ( g ) ) - ( ( ( ( h / ( g ) ) / ( ( max( 0 , ( i / ( b + c + a + d ) ) - ( h / ( g ) ) ) ) + ( h / ( g ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * j / ( g ) ) , ( 1.0 ) ) ) / ( h / ( g ) ) ) ) * ( i / ( b + c + a + d ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Info_Thread_Slots_Utilization", + "LegacyName": "metric_TMA_Info_Thread_Slots_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:percore", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b / 2 ) if ( 1 ) else 1", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "SMT;TmaL1" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "( ( 1 * a + 2 * b + 4 * c + 8 * d + 16 * e ) ) / ( f if ( 1 ) else ( g ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "FP_ARITH_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "FP_ARITH_DISPATCHED.PORT_5", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 2 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Botlnk_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "f" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "l" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "o" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) / ( ( ( ( f + g ) / ( h ) * ( i - j ) / ( h ) ) * ( h ) + ( k + ( d / ( b + c + d + a ) ) * l ) ) / ( h ) if ( m < ( i - j ) ) else ( k + ( d / ( b + c + d + a ) ) * l ) / ( h ) ) if ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) < ( ( ( ( f + g ) / ( h ) * ( i - j ) / ( h ) ) * ( h ) + ( k + ( d / ( b + c + d + a ) ) * l ) ) / ( h ) if ( m < ( i - j ) ) else ( k + ( d / ( b + c + d + a ) ) * l ) / ( h ) ) else 1 ) if ( 1 - n / o if ( 1 ) else 0 ) > 0.5 else 0", + "Category": "TMA", + "Threshold": "> 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( ( 1 * b + 2 * c + 4 * d + 8 * e + 16 * f ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( ( b + c ) + ( d + e ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_HP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType;Server" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.T0:u0xF", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_Strings_Cycles", + "LegacyName": "metric_TMA_Info_Pipeline_Strings_Cycles", + "Level": 1, + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.1", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "i", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_Unknown_Branch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "ICACHE_DATA.STALLS:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Botlnk_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "o" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "p" + }, + { + "Name": "DECODE.LCP", + "Alias": "q" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "t" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "u" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( j / ( i ) ) + ( k / ( i ) ) + ( l / ( i ) + ( m / ( i ) ) ) + ( min( ( ( 3 ) * n / ( o / p ) / ( i ) ) , ( 1.0 ) ) ) + ( q / ( i ) ) + ( h / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( ( r - s ) / ( t if ( 1 ) else ( i ) ) / 2 ) / ( ( ( r - s ) / ( t if ( 1 ) else ( i ) ) / 2 ) + ( ( u - v ) / ( t if ( 1 ) else ( i ) ) / 2 ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Botlnk_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) + ( l / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1.0 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueFL", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Ret", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Ret", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 500", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1.0 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / h / 100", + "Category": "TMA", + "Threshold": "; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a - b - 2 * c ) / d", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Other_Branches", + "LegacyName": "metric_TMA_Info_Branches_Other_Branches", + "Level": 1, + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "1 - ( ( a / b ) + ( c / b ) + ( ( d + e ) / b ) + ( ( f - c - 2 * d ) / b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 4 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L3_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L3_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_Read_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_Read_L3M_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_L3M_PKI", + "Level": 1, + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_MWrite_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_MWrite_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Info_Memory_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_Bus_Lock_PKI", + "LegacyName": "metric_TMA_Info_Memory_Bus_Lock_PKI", + "Level": 1, + "BriefDescription": "\"Bus lock\" per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "SQ_MISC.BUS_LOCK", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 224 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_Memory_Offcore_Read_HBM_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_HBM_PKI", + "Level": 1, + "BriefDescription": "High-Bandwidth Memory (HBM) accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.DEMAND_DATA_RD.PMM", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( ( 1 * a + 2 * b + 4 * c + 8 * d + 16 * e ) ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / b if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_C0_Wait", + "LegacyName": "metric_TMA_Info_System_C0_Wait", + "Level": 1, + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C0_WAIT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_PMM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_PMM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( ( 1000000000 ) * ( a / b ) / c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Read_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Read_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Write_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Write_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_UPI_Data_Transmit_BW", + "LegacyName": "metric_TMA_Info_System_UPI_Data_Transmit_BW", + "Level": 1, + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a * 64 / 9 / 1000000", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "SoC;Server" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" + }, + { + "MetricName": "Info_Memory_R2C_Offcore_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_Offcore_BW", + "Level": 1, + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_L3M_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_L3M_BW", + "Level": 1, + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_DRAM_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_DRAM_BW", + "Level": 1, + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.DRAM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_HBM_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_HBM_BW", + "Level": 1, + "BriefDescription": "Average HBM BW for Reads-to-Core. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.DEMAND_DATA_RD.PMM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;SoC" + } + ] +} \ No newline at end of file diff --git a/SPR/metrics/sapphirerapidshbm_only_metrics.json b/SPR/metrics/sapphirerapidshbm_only_metrics.json new file mode 100644 index 00000000..ed823094 --- /dev/null +++ b/SPR/metrics/sapphirerapidshbm_only_metrics.json @@ -0,0 +1,8573 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0", + "DatePublished": "01/12/2024", + "Version": "0", + "Legend": "", + "TmaVersion": "4.7", + "TmaFlavor": "Full" + }, + "Metrics": [ + { + "MetricName": "upi_data_receive_bw", + "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_per_instr", + "LegacyName": "metric_loads per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_per_instr", + "LegacyName": "metric_stores per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Level": 1, + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "b / d", + "Category": "", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "LegacyName": "metric_Average LLC demand data read miss to DCPMEM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "LegacyName": "metric_Average LLC demand data read miss to DRAM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_large_page_mpi", + "LegacyName": "metric_ITLB (2nd level) large page MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "LegacyName": "metric_DTLB (2nd level) 2MB large page load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "LegacyName": "metric_memory extra write b/w due to directory updates (MB/sec)", + "Level": 1, + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_DIR_UPDATE.HA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_DIR_UPDATE.TOR", + "Alias": "b" + }, + { + "Name": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "((a + b + c) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_read", + "LegacyName": "metric_DCPMEM_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_write", + "LegacyName": "metric_DCPMEM_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_total", + "LegacyName": "metric_DCPMEM_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + }, + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "", + "Threshold": "", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Level": 1, + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a / (a + b + c + d) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Level": 1, + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (b / (a + b + c + d) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "LegacyName": "metric_% Uops delivered from microcode sequencer (MS)", + "Level": 1, + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c / (a + b + c + d) )", + "Category": "", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( a + b + c + d ) - e / ( f ) )", + "Category": "TMA", + "Threshold": "> 15", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1;PGO" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;IcMiss" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; ~overlap", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat" + }, + { + "MetricName": "Mispredicts_Resteers", + "LegacyName": "metric_TMA_......Mispredicts_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * h / ( i ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts" + }, + { + "MetricName": "Clears_Resteers", + "LegacyName": "metric_TMA_......Clears_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * h / ( i ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueMC", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears" + }, + { + "MetricName": "Unknown_Branches", + "LegacyName": "metric_TMA_......Unknown_Branches(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;FetchLat" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( 3 ) * a / ( b / c ) / ( d ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueMC; $issueMS; $issueMV; $issueSO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DECODE.LCP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW" + }, + { + "MetricName": "Decoder0_Alone", + "LegacyName": "metric_TMA_......Decoder0_Alone(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INST_DECODED.DECODERS:c1", + "Alias": "a" + }, + { + "Name": "INST_DECODED.DECODERS:c2", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueD0", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c if ( 1 ) else ( d ) ) / 2 )", + "Category": "TMA", + "Threshold": "> 15 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;FetchBW" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) )", + "Category": "TMA", + "Threshold": "> 15", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a / ( b + c + d + e ) ) * ( 1 - f / ( g - h ) ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueMC; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears;TmaL2" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) ) * ( 1 - h / i ) , 0.0001 ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Machine_Clears" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + a ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueL1; $issueMC", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueTLB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Load_STLB_Hit", + "LegacyName": "metric_TMA_........Load_STLB_Hit(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Load_STLB_Miss", + "LegacyName": "metric_TMA_........Load_STLB_Miss(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueRFO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a / b ) * c / ( d ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 30; $issueBW; $issueSL; $issueSmSt", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DataSharing;Offcore;Snoop" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 79.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Snoop" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueLat; ~overlap", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 30 & P; $issueBW", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueBW", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore" + }, + { + "MetricName": "MBA_Stalls", + "LegacyName": "metric_TMA_........MBA_Stalls(%)", + "ParentCategory": "MEM_Bandwidth", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.MBA_STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore;Server" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueLat", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat;Offcore" + }, + { + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 108 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server" + }, + { + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( 186 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server;Snoop" + }, + { + "MetricName": "Remote_Cache", + "LegacyName": "metric_TMA_........Remote_Cache(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( ( 172.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server;Snoop" + }, + { + "MetricName": "PMM_Bound", + "LegacyName": "metric_TMA_....PMM_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.LOCAL_PMM", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "i" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( ( 1 - ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) / ( ( 19 * ( a * ( 1 + ( b / c ) ) ) + 10 * ( ( d * ( 1 + ( b / c ) ) ) + ( e * ( 1 + ( b / c ) ) ) + ( f * ( 1 + ( b / c ) ) ) ) ) + ( 25 * ( g * ( 1 + ( b / c ) ) ) + 33 * ( h * ( 1 + ( b / c ) ) ) ) ) ) ) * ( i / ( j ) ) ) if ( ( 1000000 ) * ( h + g ) > c ) else 0 ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;Server;TmaL3mem" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueRFO; $issueSL; ~overlap", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat;Offcore" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( min( ( ( 80 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) ) ) * e / ( a ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueSyncxn", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DataSharing;Offcore;Snoop" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueSpSt", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 9 * a / ( b ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueSmSt", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueTLB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Store_STLB_Hit", + "LegacyName": "metric_TMA_........Store_STLB_Hit(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( min( ( ( ( 7 ) * a + b ) / ( c if ( 1 ) else ( d ) ) ) , ( 1 ) ) ) - ( min( ( b / ( c if ( 1 ) else ( d ) ) ) , ( 1 ) ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Store_STLB_Miss", + "LegacyName": "metric_TMA_........Store_STLB_Miss(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( a / ( b if ( 1 ) else ( c ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issueSO", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.PAUSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "C01_WAIT", + "LegacyName": "metric_TMA_......C01_WAIT(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C01", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "C02_WAIT", + "LegacyName": "metric_TMA_......C02_WAIT(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "Memory_Fence", + "LegacyName": "metric_TMA_......Memory_Fence(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC2_RETIRED.LFENCE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 13 * a / ( b ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE.AMX_BUSY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 50 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;HPC;Server" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "k" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "l" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a + b ) / ( c ) * ( d - e ) / ( c ) ) * ( c ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) if ( l < ( d - e ) ) else ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 15 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) * ( d - e ) / ( c ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 5, + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 160 * a / ( b ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueMV", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Ports_Utilized_1", + "LegacyName": "metric_TMA_......Ports_Utilized_1(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 20 & P; $issueL1", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_2", + "LegacyName": "metric_TMA_......Ports_Utilized_2(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 15 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "Ports_Utilized_3m", + "LegacyName": "metric_TMA_......Ports_Utilized_3m(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 40 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil" + }, + { + "MetricName": "ALU_Op_Utilization", + "LegacyName": "metric_TMA_........ALU_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "UOPS_DISPATCHED.PORT_5_11", + "Alias": "c" + }, + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e if ( 1 ) else ( f ) ) ) )", + "Category": "TMA", + "Threshold": "> 40", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Port_0", + "LegacyName": "metric_TMA_..........Port_0(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 60; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute" + }, + { + "MetricName": "Port_1", + "LegacyName": "metric_TMA_..........Port_1(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 60; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Port_6", + "LegacyName": "metric_TMA_..........Port_6(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b if ( 1 ) else ( c ) ) )", + "Category": "TMA", + "Threshold": "> 60; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Load_Op_Utilization", + "LegacyName": "metric_TMA_........Load_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_2_3_10", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( 3 * ( b if ( 1 ) else ( c ) ) ) )", + "Category": "TMA", + "Threshold": "> 60", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Store_Op_Utilization", + "LegacyName": "metric_TMA_........Store_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_4_9", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_7_8", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if ( 1 ) else ( d ) ) ) )", + "Category": "TMA", + "Threshold": "> 60", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + a + d ) )", + "Category": "TMA", + "Threshold": "(> 70 | Heavy_Operations)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) )", + "Category": "TMA", + "Threshold": "> 60", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( min( ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) , ( 1 ) ) ) )", + "Category": "TMA", + "Threshold": "> 20 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, + { + "MetricName": "X87_Use", + "LegacyName": "metric_TMA_......X87_Use(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) * e / f )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute" + }, + { + "MetricName": "FP_Scalar", + "LegacyName": "metric_TMA_......FP_Scalar(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector", + "LegacyName": "metric_TMA_......FP_Vector(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector_128b", + "LegacyName": "metric_TMA_........FP_Vector_128b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector_256b", + "LegacyName": "metric_TMA_........FP_Vector_256b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "FP_Vector_512b", + "LegacyName": "metric_TMA_........FP_Vector_512b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "h" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "i" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Int_Vector_128b", + "LegacyName": "metric_TMA_......Int_Vector_128b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline" + }, + { + "MetricName": "Int_Vector_256b", + "LegacyName": "metric_TMA_......Int_Vector_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "b" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P; $issue2P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Pipeline" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "f" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "i" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "k" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "l" + }, + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "m" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "n" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "o" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "p" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "q" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "r" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "s" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "t" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( min( ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) , ( 1 ) ) ) ) + ( ( ( m + n ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( o + p + q ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( t - s ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 30 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Shuffles_256b", + "LegacyName": "metric_TMA_......Shuffles_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INT_VEC_RETIRED.SHUFFLES", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Pipeline" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + e ) ) - ( f / ( g ) ) ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueD0", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5 & P; $issueMC; $issueMS", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq" + }, + { + "MetricName": "Assists", + "LegacyName": "metric_TMA_......Assists(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.ANY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a / ( b ) ) , ( 1 ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Page_Faults", + "LegacyName": "metric_TMA_........Page_Faults(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 99 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 30 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, + { + "MetricName": "AVX_Assists", + "LegacyName": "metric_TMA_........AVX_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 63 * a / ( b ) )", + "Category": "TMA", + "Threshold": "> 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC" + }, + { + "MetricName": "CISC", + "LegacyName": "metric_TMA_......CISC(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c / ( b ) ) , ( 1 ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10 & P", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Info_Bottleneck_Mispredictions", + "Level": 1, + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueBM", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Info_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB" + }, + { + "MetricName": "Info_Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Info_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "h" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1 ) ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW;Frontend" + }, + { + "MetricName": "Info_Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Info_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "l" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "p" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "q" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "s" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( f / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( j / ( k if ( 1 ) else ( g ) ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if ( 1 ) else ( g ) ) ) + ( ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) * ( ( r / ( g ) ) / ( ( ( l + m ) / ( g ) * ( n - o ) / ( g ) ) + ( p / ( g ) ) + ( s / ( g ) ) + ( r / ( g ) ) ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20; $issueComp", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor" + }, + { + "MetricName": "Info_Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_a" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a_b" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a_d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_f" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a_g" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "a_h" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "a_k" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a_l" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "a_m" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "o" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "p" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "s" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "x" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "y" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "z" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( 1 - a / b ) * ( ( ( c / ( d + e + f + g ) - h / ( i ) ) ) * ( ( min( ( ( 3 ) * j / ( k / l ) / ( m ) ) , ( 1 ) ) ) + ( n / ( m ) + ( o / ( m ) ) ) * ( ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) / ( ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) + ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( o / ( m ) ) ) ) / ( ( t / ( m ) ) + ( u / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) + ( min( ( ( 3 ) * j / ( k / l ) / ( m ) ) , ( 1 ) ) ) + ( v / ( m ) ) + ( w / ( m ) ) ) ) ) + ( 10 * ( x / ( i ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) * ( p / ( d + e + f + g ) ) + ( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - y / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - y / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( g / ( d + e + f + g ) ) - ( z / ( d + e + f + g ) ) ) ) * ( ( a_a / ( m ) + ( a_b / ( m ) ) ) + a_c / ( m ) * ( ( a_d + a_c ) / ( m ) * ( a_e - a_f ) / ( m ) ) ) / ( ( a_g / ( m ) ) + ( a_a / ( m ) + ( a_b / ( m ) ) ) + ( a_h / ( a_i if ( 1 ) else ( m ) ) ) + ( ( ( ( a_d + a_c ) / ( m ) * ( a_e - a_f ) / ( m ) ) * ( m ) + ( a_j + ( f / ( d + e + f + g ) ) * a_k ) ) / ( m ) if ( a_g < ( a_e - a_f ) ) else ( a_j + ( f / ( d + e + f + g ) ) * a_k ) / ( m ) ) ) ) + ( ( ( ( x / ( i ) ) / ( ( max( 0 , ( a_l / ( d + e + f + g ) ) - ( x / ( i ) ) ) ) + ( x / ( i ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a_m / ( i ) ) , ( 1 ) ) ) / ( x / ( i ) ) ) ) * ( a_l / ( d + e + f + g ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueMS", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Cor;Ret" + }, + { + "MetricName": "Info_Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Info_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a + b ) / ( c ) ) )", + "Category": "TMA", + "Threshold": "> 5", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Bottleneck_Base_Non_Br", + "LegacyName": "metric_TMA_Info_Bottleneck_Base_Non_Br", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "i" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( a / ( b + c + a + d ) ) - ( ( e + f ) / ( g ) ) - ( ( ( ( h / ( g ) ) / ( ( max( 0 , ( i / ( b + c + a + d ) ) - ( h / ( g ) ) ) ) + ( h / ( g ) ) ) ) * ( ( min( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * j / ( g ) ) , ( 1 ) ) ) / ( h / ( g ) ) ) ) * ( i / ( b + c + a + d ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 20", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Ret" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "> 1.05", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 1.5", + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1" + }, + { + "MetricName": "Info_Thread_Slots_Utilization", + "LegacyName": "metric_TMA_Info_Thread_Slots_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:percore", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b / 2 ) if ( 1 ) else 1", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "SMT;TmaL1" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b if ( 1 ) else ( c ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "( 1 * a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( f if ( 1 ) else ( g ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "FP_ARITH_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "FP_ARITH_DISPATCHED.PORT_5", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 2 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a if ( 1 ) else ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_Botlnk_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "f" + }, + { + "Name": "RS.EMPTY:u1", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL:u0xc", + "Alias": "l" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "o" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) / ( ( ( ( f + g ) / ( h ) * ( i - j ) / ( h ) ) * ( h ) + ( k + ( d / ( b + c + d + a ) ) * l ) ) / ( h ) if ( m < ( i - j ) ) else ( k + ( d / ( b + c + d + a ) ) * l ) / ( h ) ) if ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) < ( ( ( ( f + g ) / ( h ) * ( i - j ) / ( h ) ) * ( h ) + ( k + ( d / ( b + c + d + a ) ) * l ) ) / ( h ) if ( m < ( i - j ) ) else ( k + ( d / ( b + c + d + a ) ) * l ) / ( h ) ) else 1 ) if ( 1 - n / o if ( 1 ) else 0 ) > 0.5 else 0", + "Category": "TMA", + "Threshold": "> 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 3", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 8", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instruction per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< #Pipeline_Width * 2 + 1; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch. ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( 1 * b + 2 * c + 4 * d + 8 * e + 16 * f )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE:u0xfc", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( ( b + c ) + ( d + e ) )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_HP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType;Server" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "Category": "TMA", + "Threshold": "< 10", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.T0:u0xF", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_Strings_Cycles", + "LegacyName": "metric_TMA_Info_Pipeline_Strings_Cycles", + "Level": 1, + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.1", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 100000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per physical core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( ( b / 2 ) if ( 1 ) else c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "< 0.7 & #HighIPC; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW" + }, + { + "MetricName": "Info_Frontend_Unknown_Branch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "ICACHE_DATA.STALLS:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 50", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss" + }, + { + "MetricName": "Info_Botlnk_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "o" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "p" + }, + { + "Name": "DECODE.LCP", + "Alias": "q" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "t" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "u" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( j / ( i ) ) + ( k / ( i ) ) + ( l / ( i ) + ( m / ( i ) ) ) + ( min( ( ( 3 ) * n / ( o / p ) / ( i ) ) , ( 1 ) ) ) + ( q / ( i ) ) + ( h / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( ( r - s ) / ( t if ( 1 ) else ( i ) ) / 2 ) / ( ( ( r - s ) / ( t if ( 1 ) else ( i ) ) / 2 ) + ( ( u - v ) / ( t if ( 1 ) else ( i ) ) / 2 ) ) ) )", + "Category": "TMA", + "Threshold": "> 10; $issueFB", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed" + }, + { + "MetricName": "Info_Botlnk_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( 100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) + ( l / ( i ) ) ) + ( min( ( ( 3 ) * m / ( n / o ) / ( i ) ) , ( 1 ) ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) ) )", + "Category": "TMA", + "Threshold": "> 5; $issueFL", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 200", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Ret", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Ret", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 500", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( min( ( ( 3 ) * r / ( s / t ) / ( n ) ) , ( 1 ) ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) ) ) * ( b ) / h / 100", + "Category": "TMA", + "Threshold": "; $issueBM", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a - b - 2 * c ) / d", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Branches_Other_Branches", + "LegacyName": "metric_TMA_Info_Branches_Other_Branches", + "Level": 1, + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "1 - ( ( a / b ) + ( c / b ) + ( ( d + e ) / b ) + ( ( f - c - 2 * d ) / b ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "( a + b + c ) / ( 4 * ( d if ( 1 ) else ( e ) ) )", + "Category": "TMA", + "Threshold": "> 0.5", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore" + }, + { + "MetricName": "Info_Memory_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server" + }, + { + "MetricName": "Info_Memory_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L3_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_L3_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore" + }, + { + "MetricName": "Info_Memory_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_Read_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_Read_L3M_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_Read_L3M_PKI", + "Level": 1, + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Info_Memory_Offcore_MWrite_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Offcore_MWrite_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore" + }, + { + "MetricName": "Info_Memory_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_Memory_Bus_Lock_PKI", + "LegacyName": "metric_TMA_Info_Memory_Bus_Lock_PKI", + "Level": 1, + "BriefDescription": "\"Bus lock\" per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "SQ_MISC.BUS_LOCK", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "( 224 ) * ( a / b )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 1 * a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( 1000000000 ) ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 - a / b if ( 1 ) else 0", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "SMT" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_Kernel_CPI", + "LegacyName": "metric_TMA_Info_System_Kernel_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY_P:SUP", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "OS" + }, + { + "MetricName": "Info_System_C0_Wait", + "LegacyName": "metric_TMA_Info_System_C0_Wait", + "Level": 1, + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C0_WAIT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "Category": "TMA", + "Threshold": "> 0.05", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait" + }, + { + "MetricName": "Info_System_DRAM_BW_Use", + "LegacyName": "metric_TMA_Info_System_DRAM_BW_Use", + "Level": 1, + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * ( a + b ) / ( 1000000000 ) ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "; $issueBW", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_System_MEM_PMM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_PMM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( ( 1000000000 ) * ( a / b ) / c )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Read_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Read_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_PMM_Write_BW", + "LegacyName": "metric_TMA_Info_System_PMM_Write_BW", + "Level": 1, + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( 64 * a / ( 1000000000 ) ) / ( durationtimeinmilliseconds / 1000 ) )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryBW;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b ) * 64 / ( 1000000000 ) / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server" + }, + { + "MetricName": "Info_System_UPI_Data_Transmit_BW", + "LegacyName": "metric_TMA_Info_System_UPI_Data_Transmit_BW", + "Level": 1, + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a * 64 / 9 / 1000000", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "SoC;Server" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "( > 1.1 | < 0.9 )", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "TMA", + "Threshold": "< 1000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS" + }, + { + "MetricName": "Info_Memory_R2C_Offcore_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_Offcore_BW", + "Level": 1, + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_L3M_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_L3M_BW", + "Level": 1, + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + }, + { + "MetricName": "Info_Memory_R2C_DRAM_BW", + "LegacyName": "metric_TMA_Info_Memory_R2C_DRAM_BW", + "Level": 1, + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.DRAM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( durationtimeinmilliseconds / 1000 )", + "Category": "TMA", + "Threshold": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC" + } + ] +} \ No newline at end of file diff --git a/scripts/config/replacements_config.json b/scripts/config/replacements_config.json index 8e63d1a0..f81ffa87 100644 --- a/scripts/config/replacements_config.json +++ b/scripts/config/replacements_config.json @@ -13,6 +13,7 @@ "PERF_METRICS.FETCH_LATENCY":"topdown\\-fetch\\-lat", "PERF_METRICS.MEMORY_BOUND":"topdown\\-mem\\-bound", "TOPDOWN.SLOTS:perf_metrics":"slots", + "TOPDOWN.SLOTS:percore":"TOPDOWN.SLOTS", "SOCKET_COUNT":"#num_packages", "HYPERTHREADING_ON":"#SMT_on", "CORES_PER_SOCKET":"#num_cores / #num_packages", @@ -22,7 +23,12 @@ "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2":"UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3":"UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART4":"UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "MSR_EVENT:msr=0x611:type=FREERUN:scope=PACKAGE":"power@energy\\-pkg@" + "MSR_EVENT:msr=0x611:type=FREERUN:scope=PACKAGE":"power@energy\\-pkg@", + "CPU_CLK_UNHALTED.THREAD_P:SUP":"CPU_CLK_UNHALTED.THREAD_P:k", + "CPU_CLK_UNHALTED.THREAD:SUP":"CPU_CLK_UNHALTED.THREAD:k", + "UNC_M_CLOCKTICKS:one_unit": "imc_0@event\\=0x0@", + "UNC_C_CLOCKTICKS:one_unit": "cbox_0@event\\=0x0@", + "UNC_CHA_CLOCKTICKS:one_unit": "cha_0@event\\=0x0@" }, "metric_source_events":{ "CHAS_PER_SOCKET":"UNC_CHA([^\\s]*)", @@ -31,7 +37,8 @@ "association_option_replacements": [ { "events": ["ICACHE_", "INT_MISC", "UOPS_", "IDQ", "OFFCORE_", - "L1D_", "DTLB_", "AMX_", "ITLB_", "EXE_", "INST_", "ASSISTS"], + "L1D_", "DTLB_", "AMX_", "ITLB_", "EXE_", "INST_", "ASSISTS", + "SW_", "RS", "DSB2MITE_"], "unit":"cpu", "translations":{ "c":"cmask", diff --git a/scripts/perf_format_converter.py b/scripts/perf_format_converter.py index 3fe08c60..d642799e 100644 --- a/scripts/perf_format_converter.py +++ b/scripts/perf_format_converter.py @@ -52,7 +52,7 @@ OUTPUT_DIR_PATH = Path("./outputs/") # Fields to always display event if empty -PERSISTENT_FIELDS = ["MetricGroup"] +PERSISTENT_FIELDS = ["MetricGroup", "BriefDescription"] def main():