diff --git a/LNL/events/lunarlake_lioncove_core.json b/LNL/events/lunarlake_lioncove_core.json index b9dd4055..04ba29c0 100644 --- a/LNL/events/lunarlake_lioncove_core.json +++ b/LNL/events/lunarlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.01", - "DatePublished": "02/28/2024", - "Version": "1.01", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.03", + "DatePublished": "06/12/2024", + "Version": "1.03", "Legend": "" }, "Events": [ @@ -35,6 +35,34 @@ "PDISTCounter": "32", "Speculative": "0" }, + { + "EventCode": "0x00", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired with PEBS precise-distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, { "EventCode": "0x00", "UMask": "0x02", @@ -148,15 +176,15 @@ "Speculative": "1" }, { - "EventCode": "0x03", - "UMask": "0x82", + "EventCode": "0x02", + "UMask": "0x07", "UMaskExt": "0x00", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", - "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "EventName": "DEPENDENT_LOADS.ANY", + "BriefDescription": "Count number of times a load is depending on another load that had just write back its data or in previous or 2 cycles back. This event supports in-direct dependency through a single uop.", + "PublicDescription": "Count number of times a load is depending on another load that had just write back its data or in previous or 2 cycles back. This event supports in-direct dependency through a single uop.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -176,12 +204,12 @@ "Speculative": "1" }, { - "EventCode": "0x11", - "UMask": "0x0e", + "EventCode": "0x03", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", @@ -204,12 +232,12 @@ "Speculative": "1" }, { - "EventCode": "0x12", - "UMask": "0x0e", + "EventCode": "0x03", + "UMask": "0x82", "UMaskExt": "0x00", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", @@ -232,12 +260,12 @@ "Speculative": "1" }, { - "EventCode": "0x13", - "UMask": "0x0e", + "EventCode": "0x03", + "UMask": "0x88", "UMaskExt": "0x00", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", - "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", @@ -260,19 +288,19 @@ "Speculative": "1" }, { - "EventCode": "0x2A,0x2B", - "UMask": "0x01", + "EventCode": "0x11", + "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", - "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", - "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", - "PEBScounters": "0", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0xFE7F8000001", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -284,23 +312,23 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0x2A,0x2B", - "UMask": "0x01", + "EventCode": "0x11", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", - "BriefDescription": "Counts demand data reads that have any type of response.", - "PublicDescription": "Counts demand data reads that have any type of response.", - "Counter": "0,1,2,3", - "PEBScounters": "0", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -312,23 +340,23 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0x2A,0x2B", - "UMask": "0x01", + "EventCode": "0x11", + "UMask": "0x0e", "UMaskExt": "0x00", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", - "BriefDescription": "Counts demand data reads that were supplied by DRAM.", - "PublicDescription": "Counts demand data reads that were supplied by DRAM.", - "Counter": "0,1,2,3", - "PEBScounters": "0", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E780000001", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -340,25 +368,25 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0x2A,0x2B", - "UMask": "0x01", + "EventCode": "0x11", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "OCR.DEMAND_RFO.L3_MISS", - "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", - "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", - "PEBScounters": "0", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0xFE7F8000002", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", - "CounterMask": "0", + "CounterMask": "1", "Invert": "0", "EdgeDetect": "0", "PEBS": "0", @@ -368,23 +396,23 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0x2A,0x2B", - "UMask": "0x01", + "EventCode": "0x11", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", - "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "Counter": "0,1,2,3", - "PEBScounters": "0", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10002", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -396,16 +424,16 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0x2e", - "UMask": "0x41", - "UMaskExt": "0x00", - "EventName": "LONGEST_LAT_CACHE.MISS", - "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", - "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "EventCode": "0x11", + "UMask": "0x20", + "UMaskExt": "0x01", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", @@ -428,12 +456,12 @@ "Speculative": "1" }, { - "EventCode": "0x2e", - "UMask": "0x4f", + "EventCode": "0x12", + "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", - "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100003", @@ -456,15 +484,15 @@ "Speculative": "1" }, { - "EventCode": "0x3c", - "UMask": "0x00", + "EventCode": "0x12", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "BriefDescription": "Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.CORE_P]", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -484,15 +512,15 @@ "Speculative": "1" }, { - "EventCode": "0x3c", - "UMask": "0x00", + "EventCode": "0x12", + "UMask": "0x08", "UMaskExt": "0x00", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "BriefDescription": "Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -512,15 +540,15 @@ "Speculative": "1" }, { - "EventCode": "0x3c", - "UMask": "0x01", + "EventCode": "0x12", + "UMask": "0x0e", "UMaskExt": "0x00", - "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -540,21 +568,21 @@ "Speculative": "1" }, { - "EventCode": "0x9c", - "UMask": "0x01", + "EventCode": "0x12", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "IDQ_BUBBLES.CORE", - "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", - "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", - "CounterMask": "0", + "CounterMask": "1", "Invert": "0", "EdgeDetect": "0", "PEBS": "0", @@ -568,15 +596,15 @@ "Speculative": "1" }, { - "EventCode": "0xa4", - "UMask": "0x01", + "EventCode": "0x12", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "TOPDOWN.SLOTS_P", - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method.", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "10000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -596,15 +624,15 @@ "Speculative": "1" }, { - "EventCode": "0xa4", - "UMask": "0x02", - "UMaskExt": "0x00", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", - "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "EventCode": "0x12", + "UMask": "0x20", + "UMaskExt": "0x03", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "10000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -624,43 +652,43 @@ "Speculative": "1" }, { - "EventCode": "0xc0", - "UMask": "0x00", + "EventCode": "0x13", + "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "INST_RETIRED.ANY_P", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xc2", - "UMask": "0x02", + "EventCode": "0x13", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "UOPS_RETIRED.SLOTS", - "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", - "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -676,19 +704,6207 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xc4", - "UMask": "0x00", + "EventCode": "0x13", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x0e", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x20", + "UMaskExt": "0x03", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "PublicDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", + "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.", + "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", + "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "BriefDescription": "Cacheable and Non-Cacheable code read requests", + "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS.DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", + "PublicDescription": "Counts demand data read requests that miss the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Any memory transaction that reached the SQ.", + "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).", + "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x9E7FA000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E780000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).", + "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO).", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x9E7FA000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40001E00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20001E00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40001E00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2c", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "SQ_MISC.BUS_LOCK", + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2d", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "XQ.FULL", + "BriefDescription": "Cycles the uncore cannot take further requests", + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "UMaskExt": "0x00", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "UMaskExt": "0x00", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "BriefDescription": "Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x0f", + "UMaskExt": "0x00", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x42", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "BriefDescription": "Cycles when L1D is locked", + "PublicDescription": "This event counts the number of cycles when the L1D is locked.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x44", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_STORE_RETIRED.L2_HIT", + "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "PublicDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x46", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEMORY_STALLS.L1", + "BriefDescription": "Counts cycles where no execution is happening due to loads waiting for L1 cache (that is: no execution & load in flight & no load missed L1 cache)", + "PublicDescription": "Counts cycles where no execution is happening due to loads waiting for L1 cache (that is: no execution & load in flight & no load missed L1 cache)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x46", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEMORY_STALLS.L2", + "BriefDescription": "Counts cycles where no execution is happening due to loads waiting for L2 cache (that is: no execution & load in flight & load missed L1 & no load missed L2 cache)", + "PublicDescription": "Counts cycles where no execution is happening due to loads waiting for L2 cache (that is: no execution & load in flight & load missed L1 & no load missed L2 cache)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x46", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEMORY_STALLS.L3", + "BriefDescription": "Counts cycles where no execution is happening due to loads waiting for L3 cache (that is: no execution & load in flight & load missed L1 & load missed L2 cache & no load missed L3 Cache)", + "PublicDescription": "Counts cycles where no execution is happening due to loads waiting for L3 cache (that is: no execution & load in flight & load missed L1 & load missed L2 cache & no load missed L3 Cache)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x46", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "MEMORY_STALLS.MEM", + "BriefDescription": "Counts cycles where no execution is happening due to loads waiting for Memory (that is: no execution & load in flight & a load missed L3 cache)", + "PublicDescription": "Counts cycles where no execution is happening due to loads waiting for Memory (that is: no execution & load in flight & a load missed L3 cache)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "L1D_PENDING.LOAD", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "2", + "PEBScounters": "2", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "L1D_MISS.LOAD", + "BriefDescription": "Number of demand requests that missed L1D cache", + "PublicDescription": "Count occurrences (rising-edge) of DCACHE_PENDING sub-event0. Impl. sends per-port binary inc-bit the occupancy increases* (at FB alloc or promotion).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "L1D_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "L1D_MISS.L2_STALLS", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Clears due to Unknown Branches.", + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x61", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x76", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_DECODED.DEC0_UOPS", + "BriefDescription": "Number of non dec-by-all uops decoded by decoder", + "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "IDQ.MS_CYCLES_ANY", + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "PublicDescription": "Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "ICACHE_DATA.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "PublicDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "DECODE.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "DECODE.MS_BUSY", + "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "PublicDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "IDQ_BUBBLES.CORE", + "BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "This event is deprecated. [This event is alias to IDQ_BUBBLES.STARVATION_CYCLES]", + "PublicDescription": "This event is deprecated. [This event is alias to IDQ_BUBBLES.STARVATION_CYCLES]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "IDQ_BUBBLES.STARVATION_CYCLES", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "IDQ_BUBBLES.FETCH_LATENCY", + "BriefDescription": "Cycles when no uops are delivered by the IDQ for 2 or more cycles when backend of the machine is not stalled - normally indicating a Fetch Latency issue", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls for 2 or more cycles - normally indicating a Fetch Latency issue.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculations.", + "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "PublicDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "RS.EMPTY_RESOURCE", + "BriefDescription": "Cycles when RS was empty and a resource allocation stall is asserted", + "PublicDescription": "Cycles when RS was empty and a resource allocation stall is asserted", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "UMaskExt": "0x00", + "EventName": "RS.EMPTY", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "UMaskExt": "0x00", + "EventName": "RS.EMPTY_COUNT", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x0c", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x21", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.", + "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "INT_MISC.CLEARS_COUNT", + "BriefDescription": "Clears speculative count", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "PublicDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x7", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_ISSUED.CYCLES", + "BriefDescription": "UOPS_ISSUED.CYCLES", + "PublicDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_ACTIVE", + "BriefDescription": "Cycles when integer divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer operations only.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x09", + "UMaskExt": "0x00", + "EventName": "ARITH.DIV_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.STALLS", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "3", + "PEBScounters": "3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_DISPATCHED.INT_EU_ALL", + "BriefDescription": "Uops executed on any INT EU ports 0 through 5", + "PublicDescription": "Number of integer uops dispatched to execution.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UOPS_DISPATCHED.LOAD", + "BriefDescription": "Uops executed on Load ports 2, 3 and 12", + "PublicDescription": "Number of Load uops dispatched to execution.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "UOPS_DISPATCHED.JMP", + "BriefDescription": "Number of Uops dispatched/executed by any of the 3 JEUs (all ups that hold the JEU including macro; micro jumps; fetch-from-eip)", + "PublicDescription": "Number of jump uops dispatch to execution", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_DISPATCHED.V0", + "BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD*/SUB*/MUL/FMA*/DPP.", + "PublicDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD*/SUB*/MUL/FMA*/DPP.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_DISPATCHED.V1", + "BriefDescription": "Number of FP-arith-uops dispatched on 2nd VEC port (port 1)", + "PublicDescription": "Number of FP-arith-uops dispatched on 2nd VEC port (port 1)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_DISPATCHED.V2", + "BriefDescription": "Number of FP-arith-uops dispatched on 3rd VEC port (port 5)", + "PublicDescription": "Number of FP-arith-uops dispatched on 3rd VEC port (port 5)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.NOP", + "BriefDescription": "Retired NOP instructions.", + "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.REP_ITERATION", + "BriefDescription": "Iterations of Repeat string retired instructions.", + "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.BR_FUSED", + "BriefDescription": "retired macro-fused uops when there is a branch in the macro-fused pair (the two instructions that got macro-fused count once in this pmon)", + "PublicDescription": "retired macro-fused uops when there is a branch in the macro-fused pair (the two instructions that got macro-fused count once in this pmon)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x30", + "UMaskExt": "0x00", + "EventName": "INST_RETIRED.MACRO_FUSED", + "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "PublicDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "ASSISTS.HARDWARE", + "BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.", + "PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "ASSISTS.PAGE_FAULT", + "BriefDescription": "ASSISTS.PAGE_FAULT", + "PublicDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "ASSISTS.SSE_AVX_MIX", + "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "PublicDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x1f", + "UMaskExt": "0x00", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.HEAVY", + "BriefDescription": "Retired uops except the last uop of each instruction.", + "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.STALLS", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.CYCLES", + "BriefDescription": "Cycles with retired uop(s).", + "PublicDescription": "Counts cycles where at least one uop has retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.MS", + "BriefDescription": "UOPS_RETIRED.MS", + "PublicDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.MS_SWITCHES", + "BriefDescription": "Number of non-speculative switches to the Microcode Sequencer (MS)", + "PublicDescription": "Switches to the Microcode Sequencer", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", "UMaskExt": "0x00", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "BriefDescription": "All branch instructions retired.", "PublicDescription": "Counts all branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "400009", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "UMaskExt": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "UMaskExt": "0x01", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x41", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", + "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x42", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL_COST", + "BriefDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x44", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_COST", + "BriefDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x48", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.RET_COST", + "BriefDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN_COST", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x51", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND_COST", + "BriefDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x60", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN_COST", + "BriefDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xc0", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.INDIRECT_COST", + "BriefDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.MISP_ANT", + "BriefDescription": "Mispredicted Retired ANT branches", + "PublicDescription": "ANT retired branches that got just mispredicted", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x608006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x601006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x610006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x602006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600406", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x620006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x604006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600806", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "BriefDescription": "Retired instructions that caused clears due to being Unknown Branches.", + "PublicDescription": "Number retired branch instructions that caused the front-end to be resteered when it finds the instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x17", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.MS_FLOWS", + "BriefDescription": "Counts flows delivered by the Microcode Sequencer", + "PublicDescription": "Counts flows delivered by the Microcode Sequencer", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED.ANY_ANT", + "BriefDescription": "Retired ANT branches", + "PublicDescription": "Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted)", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.SCALAR", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x0C", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_128B", + "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_128B", + "PublicDescription": "FP_ARITH_OPS_RETIRED.VECTOR_128B", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x18", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x18", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.4_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x30", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_256B", + "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_256B", + "PublicDescription": "FP_ARITH_OPS_RETIRED.VECTOR_256B", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x3c", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR", + "PublicDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x3c", + "UMaskExt": "0x00", + "EventName": "FP_ARITH_OPS_RETIRED.VECTOR", + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "53", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "23", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", + "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "2", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x09", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "BriefDescription": "Retired load instructions that hit the STLB.", + "PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x0a", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES", + "BriefDescription": "Retired store instructions that hit the STLB.", + "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "Counts all retired load instructions.", + "PublicDescription": "Counts Instructions with at least one architecturally visible load retired.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -698,7 +6914,7 @@ "Invert": "0", "EdgeDetect": "0", "PEBS": "1", - "Data_LA": "0", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", @@ -708,15 +6924,43 @@ "Speculative": "0" }, { - "EventCode": "0xc5", - "UMask": "0x00", + "EventCode": "0xd0", + "UMask": "0x82", "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "BriefDescription": "All mispredicted branch instructions retired.", - "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "Retired store instructions.", + "PublicDescription": "Counts all retired store instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x87", + "UMaskExt": "0x00", + "EventName": "MEM_INST_RETIRED.ANY", + "BriefDescription": "All retired memory instructions.", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "400009", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -726,7 +6970,35 @@ "Invert": "0", "EdgeDetect": "0", "PEBS": "1", - "Data_LA": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", @@ -736,24 +7008,80 @@ "Speculative": "0" }, { - "EventCode": "0xcd", + "EventCode": "0xd1", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", - "Counter": "0,1,2,3,4,5,6,7,8,9", - "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "1009", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "1", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", + "PEBS": "1", "Data_LA": "1", "L1_Hit_Indication": "0", "Errata": "null", @@ -764,368 +7092,480 @@ "Speculative": "0" }, { - "EventCode": "0xcd", + "EventCode": "0xd2", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "MISC2_RETIRED.LFENCE", + "BriefDescription": "LFENCE instructions retired", + "PublicDescription": "number of LFENCE retired instructions", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe4", "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "LBR record is inserted", + "PublicDescription": "LBR record is inserted", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "20011", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", "Precise": "1", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe5", + "UMask": "0x0f", + "UMaskExt": "0x00", + "EventName": "MEM_UOP_RETIRED.ANY", + "BriefDescription": "Retired memory uops for any access", + "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "INT_VEC_RETIRED.ADD_128", + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0x0c", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.ADD_256", + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "503", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.VNNI_128", + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "PublicDescription": "INT_VEC_RETIRED.VNNI_128", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100007", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0x13", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.128BIT", + "BriefDescription": "Number of vector integer instructions retired of 128-bit vector-width.", + "PublicDescription": "Number of vector integer instructions retired of 128-bit vector-width.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100003", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0x20", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.VNNI_256", + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "PublicDescription": "INT_VEC_RETIRED.VNNI_256", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "101", - "MSRIndex": "0x3F6", - "MSRValue": "0x200", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0x40", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.SHUFFLES", + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "PublicDescription": "INT_VEC_RETIRED.SHUFFLES", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "2003", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0x80", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.MUL_256", + "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "PublicDescription": "INT_VEC_RETIRED.MUL_256", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "50021", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xe7", + "UMask": "0xac", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "INT_VEC_RETIRED.256BIT", + "BriefDescription": "Number of vector integer instructions retired of 256-bit vector-width.", + "PublicDescription": "Number of vector integer instructions retired of 256-bit vector-width.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "53", - "MSRIndex": "0x3F6", - "MSRValue": "0x400", - "Precise": "1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", + "PDISTCounter": "NA", "Speculative": "0" }, { - "EventCode": "0xcd", - "UMask": "0x01", + "EventCode": "0xec", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency.", + "EventName": "CPU_CLK_UNHALTED.C01", + "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "23", - "MSRIndex": "0x3F6", - "MSRValue": "0x800", - "Precise": "1", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", "CollectPEBSRecord": "2", - "TakenAlone": "1", + "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xcd", - "UMask": "0x02", + "EventCode": "0xec", + "UMask": "0x20", "UMaskExt": "0x00", - "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", - "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", - "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", - "Counter": "0,1", - "PEBScounters": "0,1", - "SampleAfterValue": "1000003", + "EventName": "CPU_CLK_UNHALTED.C02", + "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "2", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xd0", - "UMask": "0x81", + "EventCode": "0xec", + "UMask": "0x40", "UMaskExt": "0x00", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "BriefDescription": "Retired load instructions.", - "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", - "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "EventName": "CPU_CLK_UNHALTED.PAUSE", + "BriefDescription": "Core clocks when a PAUSE is pending.", + "PublicDescription": "Core clocks when a PAUSE is pending.", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "1", - "Data_LA": "1", + "PEBS": "0", + "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xd0", - "UMask": "0x82", + "EventCode": "0xec", + "UMask": "0x40", "UMaskExt": "0x00", - "EventName": "MEM_INST_RETIRED.ALL_STORES", - "BriefDescription": "Retired store instructions.", - "PublicDescription": "Counts all retired store instructions.", - "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", + "BriefDescription": "Number of Pause instructions", + "PublicDescription": "Number of Pause instructions", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", - "CounterMask": "0", + "CounterMask": "1", "Invert": "0", - "EdgeDetect": "0", - "PEBS": "1", - "Data_LA": "1", - "L1_Hit_Indication": "1", + "EdgeDetect": "1", + "PEBS": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xe4", - "UMask": "0x01", + "EventCode": "0xec", + "UMask": "0x70", "UMaskExt": "0x00", - "EventName": "MISC_RETIRED.LBR_INSERTS", - "BriefDescription": "LBR record is inserted", - "PublicDescription": "LBR record is inserted", + "EventName": "CPU_CLK_UNHALTED.C0_WAIT", + "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "1000003", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "PEBS": "1", + "PEBS": "0", "Data_LA": "0", "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" } ] } \ No newline at end of file diff --git a/LNL/events/lunarlake_skymont_core.json b/LNL/events/lunarlake_skymont_core.json index 906d3ac5..467f1357 100644 --- a/LNL/events/lunarlake_skymont_core.json +++ b/LNL/events/lunarlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.01", - "DatePublished": "02/28/2024", - "Version": "1.01", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.03", + "DatePublished": "06/12/2024", + "Version": "1.03", "Legend": "" }, "Events": [ diff --git a/mapfile.csv b/mapfile.csv index 819b6b33..05bc16db 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -175,5 +175,5 @@ GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_uncore_experimental.json,uncore GenuineIntel-6-B6,V1.03,/GRR/events/grandridge_core.json,core,,, GenuineIntel-6-B6,V1.03,/GRR/events/grandridge_uncore.json,uncore,,, GenuineIntel-6-B6,V1.03,/GRR/events/grandridge_uncore_experimental.json,uncore experimental,,, -GenuineIntel-6-BD,V1.01,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-BD,V1.01,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-BD,V1.03,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-BD,V1.03,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core