From 71f7ea1b0b4080a43ba2f97761201e7f28a28f5b Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Fri, 26 May 2023 11:18:24 -0700 Subject: [PATCH 1/2] mapfile: Add missing fp_arith references This commit adds fp_arith_inst.json rows for IVB, HSW, and GLM. --- mapfile.csv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/mapfile.csv b/mapfile.csv index 3dce8f5..60d85b8 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -18,8 +18,10 @@ GenuineIntel-6-5A,V15,/SLM/events/Silvermont_core.json,core,,, GenuineIntel-6-5A,V15,/SLM/events/Silvermont_matrix.json,offcore,,, GenuineIntel-6-5C,V13,/GLM/events/goldmont_core.json,core,,, GenuineIntel-6-5C,V13,/GLM/events/goldmont_matrix.json,offcore,,, +GenuineIntel-6-5C,V13,/GLM/events/goldmont_fp_arith_inst.json,fp_arith_inst,,, GenuineIntel-6-5F,V13,/GLM/events/goldmont_core.json,core,,, GenuineIntel-6-5F,V13,/GLM/events/goldmont_matrix.json,offcore,,, +GenuineIntel-6-5F,V13,/GLM/events/goldmont_fp_arith_inst.json,fp_arith_inst,,, GenuineIntel-6-1C,V5,/BNL/events/bonnell_core.json,core,,, GenuineIntel-6-26,V5,/BNL/events/bonnell_core.json,core,,, GenuineIntel-6-27,V5,/BNL/events/bonnell_core.json,core,,, @@ -34,6 +36,7 @@ GenuineIntel-6-2D,V24,/JKT/events/Jaketown_uncore.json,uncore,,, GenuineIntel-6-3A,V24,/IVB/events/ivybridge_core.json,core,,, GenuineIntel-6-3A,V24,/IVB/events/ivybridge_matrix.json,offcore,,, GenuineIntel-6-3A,V24,/IVB/events/ivybridge_uncore.json,uncore,,, +GenuineIntel-6-3A,V24,/IVB/events/ivybridge_fp_arith_inst.json,fp_arith_inst,,, GenuineIntel-6-3E,V24,/IVT/events/ivytown_core.json,core,,, GenuineIntel-6-3E,V24,/IVT/events/ivytown_matrix.json,offcore,,, GenuineIntel-6-3E,V24,/IVT/events/ivytown_uncore.json,uncore,,, From 545f610ce852a15dd588bd70cdc1608452d2aa0a Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Mon, 28 Nov 2022 12:00:07 -0700 Subject: [PATCH 2/2] CI: Introduce mapfile.csv verification The mapfile.csv is used by numerous downstream tools and needs to be consistent. This tooling checks for common issues such as bad file paths, version mismatches, or missing file references. --- .github/workflows/verify-mapfile.yml | 36 ++ .gitignore | 3 + scripts/ci/verify_mapfile/.coveragerc | 9 + scripts/ci/verify_mapfile/README.md | 54 +++ scripts/ci/verify_mapfile/__init__.py | 0 scripts/ci/verify_mapfile/mapfile_schema.json | 49 +++ scripts/ci/verify_mapfile/requirements.txt | 1 + .../00_missing_mapfile_column/mapfile.csv | 159 +++++++++ .../SPR/events/sapphirerapids_core.json | 11 + .../SPR/events/sapphirerapids_uncore.json | 11 + .../01_missing_event_file/mapfile.csv | 4 + .../SPR/events/sapphirerapids_core.json | 11 + .../SPR/events/sapphirerapids_uncore.json | 11 + .../02_mismatched_versions/mapfile.csv | 3 + .../03_correct_event_types/mapfile.csv | 159 +++++++++ .../mapfile.csv | 13 + .../ICX/events/icelakex_core.json | 11 + .../ICX/events/icelakex_uncore.json | 11 + .../events/icelakex_uncore_experimental.json | 11 + .../mapfile.csv | 6 + .../06_extra_mapfile_column/mapfile.csv | 4 + .../07_duplicate_event_file_type/mapfile.csv | 25 ++ .../mapfile.csv | 11 + .../SPR/events/sapphirerapids_core.json | 11 + .../SPR/events/sapphirerapids_uncore.json | 11 + .../test_data/09_correct_mapfile/mapfile.csv | 3 + .../10_bad_mapfile_version/mapfile.csv | 3 + .../11_mismatched_file_type/mapfile.csv | 4 + .../12_unexpected_file_path/mapfile.csv | 3 + .../13_duplicate_metric_entries/mapfile.csv | 16 + .../ci/verify_mapfile/test_verify_mapfile.py | 149 ++++++++ scripts/ci/verify_mapfile/verify_mapfile.py | 333 ++++++++++++++++++ 32 files changed, 1146 insertions(+) create mode 100644 .github/workflows/verify-mapfile.yml create mode 100644 scripts/ci/verify_mapfile/.coveragerc create mode 100644 scripts/ci/verify_mapfile/README.md create mode 100644 scripts/ci/verify_mapfile/__init__.py create mode 100644 scripts/ci/verify_mapfile/mapfile_schema.json create mode 100644 scripts/ci/verify_mapfile/requirements.txt create mode 100644 scripts/ci/verify_mapfile/test_data/00_missing_mapfile_column/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_core.json create mode 100644 scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_uncore.json create mode 100644 scripts/ci/verify_mapfile/test_data/01_missing_event_file/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_core.json create mode 100644 scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_uncore.json create mode 100644 scripts/ci/verify_mapfile/test_data/02_mismatched_versions/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/03_correct_event_types/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/04_platform_referencing_multiple_event_dirs/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_core.json create mode 100644 scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore.json create mode 100644 scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore_experimental.json create mode 100644 scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/06_extra_mapfile_column/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/07_duplicate_event_file_type/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/08_mismatched_event_file_versions/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_core.json create mode 100644 scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_uncore.json create mode 100644 scripts/ci/verify_mapfile/test_data/09_correct_mapfile/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/10_bad_mapfile_version/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/11_mismatched_file_type/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/12_unexpected_file_path/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_data/13_duplicate_metric_entries/mapfile.csv create mode 100644 scripts/ci/verify_mapfile/test_verify_mapfile.py create mode 100755 scripts/ci/verify_mapfile/verify_mapfile.py diff --git a/.github/workflows/verify-mapfile.yml b/.github/workflows/verify-mapfile.yml new file mode 100644 index 0000000..6430402 --- /dev/null +++ b/.github/workflows/verify-mapfile.yml @@ -0,0 +1,36 @@ +# This workflow will setup Python, run unittests, and execute verify_mapfile.py. + +name: Verify mapfile.csv + +on: + push: + pull_request: + +permissions: + contents: read + +jobs: + verify-mapfile: + runs-on: ubuntu-latest + + defaults: + run: + working-directory: ${{ github.workspace }}/scripts/ci/verify_mapfile + + steps: + - name: Checkout perfmon + uses: actions/checkout@692973e3d937129bcbf40652eb9f2f61becf3332 # v4.1.7 + + - name: Set up Python 3.x + uses: actions/setup-python@39cd14951b08e74b54015e9e001cdefcf80e669f # v5.1.1 + with: + python-version: "3.x" + + - name: Install Python packages + run: pip install -r requirements.txt + + - name: Run verify_mapfile self tests + run: python -m unittest + + - name: Validate mapfile.csv + run: python verify_mapfile.py diff --git a/.gitignore b/.gitignore index 0358f69..cc2fa67 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,7 @@ __pycache__/ +*.pyc +*.coverage +htmlcov/ .idea scripts/inputs scripts/outputs diff --git a/scripts/ci/verify_mapfile/.coveragerc b/scripts/ci/verify_mapfile/.coveragerc new file mode 100644 index 0000000..8b57a01 --- /dev/null +++ b/scripts/ci/verify_mapfile/.coveragerc @@ -0,0 +1,9 @@ +[run] +branch = True + +[report] +include = + verify_mapfile.py + +exclude_lines = + if __name__ == '__main__': diff --git a/scripts/ci/verify_mapfile/README.md b/scripts/ci/verify_mapfile/README.md new file mode 100644 index 0000000..4a07574 --- /dev/null +++ b/scripts/ci/verify_mapfile/README.md @@ -0,0 +1,54 @@ +# Verify `mapfile.csv` + +## Overview + +The goal of this helper script is to automatically check `mapfile.csv` for common issues. A few +examples: + +* Bad file paths. +* Incorrect versions. +* Mismatched uncore experimental. +* Unexpected columns. +* Event files missing from family models. + +## Setup + +Install required packages either using the package manager or with `pip`. + +```bash +pip install -r requirements.txt +``` + +## Running + +```bash +python verify_mapfile.py +``` + +### Running Tests + +```bash +python -m unittest +``` + +### Coverage + +Coverage output is written to `htmlcov`. + +```bash +python -m coverage run -m unittest +python -m coverage html +``` + +## Formatting + +VS Code was configured as below for formatting. + +```json +"[python]": { + "editor.defaultFormatter": "eeyore.yapf" +}, +"yapf.args": [ + "--style={based_on_style: google, indent_width: 4, column_limit: 100}" +] +``` diff --git a/scripts/ci/verify_mapfile/__init__.py b/scripts/ci/verify_mapfile/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/scripts/ci/verify_mapfile/mapfile_schema.json b/scripts/ci/verify_mapfile/mapfile_schema.json new file mode 100644 index 0000000..01d1eb0 --- /dev/null +++ b/scripts/ci/verify_mapfile/mapfile_schema.json @@ -0,0 +1,49 @@ +{ + "$schema": "https://json-schema.org/draft/2020-12/schema", + "title": "Perfmon Events mapfile.csv Schema", + "description": "A schema for validating https://github.com/intel/perfmon/blob/main/mapfile.csv", + "type": "array", + "items": { + "type" : "object", + "properties" : { + "Family-model" : { + "type": "string", + "pattern": "^GenuineIntel-6-[A-F0-9]{2}(-\\[[A-F0-9]+\\])?$" + }, + "Version" : { + "type": "string", + "pattern": "^V\\d+(\\.\\d+)?$" + }, + "Filename" : { + "type": "string", + "pattern": "^/[A-Z-]+/(events|metrics)/[a-z_DEJNPSWX-]+\\.json$" + }, + "EventType" : { + "type": "string", + "pattern": "^(core|fp_arith_inst|hybridcore|metrics|offcore|uncore|uncore experimental)$" + }, + "Core Type" : { + "type": "string", + "pattern": "^(0x[A-F0-9]{2})?$" + }, + "Native Model ID" : { + "type": "string", + "pattern": "^(0x[A-F0-9]{6})?$" + }, + "Core Role Name" : { + "type": "string", + "pattern": "^(Core|Atom)?$" + } + }, + "required" : [ + "Family-model", + "Version", + "Filename", + "EventType", + "Core Type", + "Native Model ID", + "Core Role Name" + ], + "additionalProperties": false + } +} diff --git a/scripts/ci/verify_mapfile/requirements.txt b/scripts/ci/verify_mapfile/requirements.txt new file mode 100644 index 0000000..d89304b --- /dev/null +++ b/scripts/ci/verify_mapfile/requirements.txt @@ -0,0 +1 @@ +jsonschema diff --git a/scripts/ci/verify_mapfile/test_data/00_missing_mapfile_column/mapfile.csv b/scripts/ci/verify_mapfile/test_data/00_missing_mapfile_column/mapfile.csv new file mode 100644 index 0000000..f61f525 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/00_missing_mapfile_column/mapfile.csv @@ -0,0 +1,159 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-2E,V3,/NHM-EX/events/NehalemEX_core.json,core,,, +GenuineIntel-6-1E,V3,/NHM-EP/events/NehalemEP_core.json,core,,, +GenuineIntel-6-1F,V3,/NHM-EP/events/NehalemEP_core.json,core,,, +GenuineIntel-6-1A,V3,/NHM-EP/events/NehalemEP_core.json,core,,, +GenuineIntel-6-2F,V3,/WSM-EX/events/WestmereEX_core.json,core,,, +GenuineIntel-6-25,V3,/WSM-EP-SP/events/WestmereEP-SP_core.json,core,,, +GenuineIntel-6-2C,V3,/WSM-EP-DP/events/WestmereEP-DP_core.json,core,,, +GenuineIntel-6-37,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-37,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-4A,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-4A,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-4D,V14,/SLM/events/Silvermont_core.json,core,, +GenuineIntel-6-4D,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-4C,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-4C,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-5A,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-5A,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-5C,V13,/GLM/events/goldmont_core.json,core,,, +GenuineIntel-6-5C,V13,/GLM/events/goldmont_matrix.json,offcore,,, +GenuineIntel-6-5F,V13,/GLM/events/goldmont_core.json,core,,, +GenuineIntel-6-5F,V13,/GLM/events/goldmont_matrix.json,offcore,,, +GenuineIntel-6-1C,V4,/BNL/events/Bonnell_core.json,core,,, +GenuineIntel-6-26,V4,/BNL/events/Bonnell_core.json,core,,, +GenuineIntel-6-27,V4,/BNL/events/Bonnell_core.json,core,,, +GenuineIntel-6-36,V4,/BNL/events/Bonnell_core.json,core,,, +GenuineIntel-6-35,V4,/BNL/events/Bonnell_core.json,core,,, +GenuineIntel-6-2A,V17,/SNB/events/sandybridge_core.json,core,,, +GenuineIntel-6-2A,V17,/SNB/events/sandybridge_matrix.json,offcore,,, +GenuineIntel-6-2A,V17,/SNB/events/sandybridge_uncore.json,uncore,,, +GenuineIntel-6-2D,V21,/JKT/events/Jaketown_core.json,core,,, +GenuineIntel-6-2D,V21,/JKT/events/Jaketown_matrix.json,offcore,,, +GenuineIntel-6-2D,V21,/JKT/events/Jaketown_uncore.json,uncore,,, +GenuineIntel-6-3A,V23,/IVB/events/ivybridge_core.json,core,,, +GenuineIntel-6-3A,V23,/IVB/events/ivybridge_matrix.json,offcore,,, +GenuineIntel-6-3A,V23,/IVB/events/ivybridge_uncore.json,uncore,,, +GenuineIntel-6-3E,V22,/IVT/events/ivytown_core.json,core,,, +GenuineIntel-6-3E,V22,/IVT/events/ivytown_matrix.json,offcore,,, +GenuineIntel-6-3E,V22,/IVT/events/ivytown_uncore.json,uncore,,, +GenuineIntel-6-3C,V32,/HSW/events/haswell_core.json,core,,, +GenuineIntel-6-45,V32,/HSW/events/haswell_core.json,core,,, +GenuineIntel-6-46,V32,/HSW/events/haswell_core.json,core,,, +GenuineIntel-6-3C,V32,/HSW/events/haswell_matrix.json,offcore,,, +GenuineIntel-6-45,V32,/HSW/events/haswell_matrix.json,offcore,,, +GenuineIntel-6-46,V32,/HSW/events/haswell_matrix.json,offcore,,, +GenuineIntel-6-3C,V32,/HSW/events/haswell_uncore.json,uncore,,, +GenuineIntel-6-45,V32,/HSW/events/haswell_uncore.json,uncore,,, +GenuineIntel-6-46,V32,/HSW/events/haswell_uncore.json,uncore,,, +GenuineIntel-6-3F,V26,/HSX/events/haswellx_core.json,core,,, +GenuineIntel-6-3F,V26,/HSX/events/haswellx_matrix.json,offcore,,, +GenuineIntel-6-3F,V26,/HSX/events/haswellx_uncore.json,uncore,,, +GenuineIntel-6-3D,V26,/BDW/events/broadwell_core.json,core,,, +GenuineIntel-6-3D,V26,/BDW/events/broadwell_matrix.json,offcore,,, +GenuineIntel-6-3D,V26,/BDW/events/broadwell_uncore.json,uncore,,, +GenuineIntel-6-3D,V26,/BDW/events/broadwell_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-47,V26,/BDW/events/broadwell_core.json,core,,, +GenuineIntel-6-47,V26,/BDW/events/broadwell_matrix.json,offcore,,, +GenuineIntel-6-47,V26,/BDW/events/broadwell_uncore.json,uncore,,, +GenuineIntel-6-47,V26,/BDW/events/broadwell_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-4F,V19,/BDX/events/broadwellx_core.json,core,,, +GenuineIntel-6-4F,V19,/BDX/events/broadwellx_matrix.json,offcore,,, +GenuineIntel-6-4F,V19,/BDX/events/broadwellx_uncore.json,uncore,,, +GenuineIntel-6-56,V7,/BDW-DE/events/broadwellde_core.json,core,,, +GenuineIntel-6-56,V7,/BDW-DE/events/broadwellde_uncore.json,uncore,,, +GenuineIntel-6-4E,V53,/SKL/events/skylake_core.json,core,,, +GenuineIntel-6-5E,V53,/SKL/events/skylake_core.json,core,,, +GenuineIntel-6-4E,V53,/SKL/events/skylake_matrix.json,offcore,,, +GenuineIntel-6-5E,V53,/SKL/events/skylake_matrix.json,offcore,,, +GenuineIntel-6-4E,V53,/SKL/events/skylake_uncore.json,uncore,,, +GenuineIntel-6-5E,V53,/SKL/events/skylake_uncore.json,uncore,,, +GenuineIntel-6-4E,V53,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-5E,V53,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-8E,V53,/SKL/events/skylake_core.json,core,,, +GenuineIntel-6-9E,V53,/SKL/events/skylake_core.json,core,,, +GenuineIntel-6-8E,V53,/SKL/events/skylake_matrix.json,offcore,,, +GenuineIntel-6-9E,V53,/SKL/events/skylake_matrix.json,offcore,,, +GenuineIntel-6-8E,V53,/SKL/events/skylake_uncore.json,uncore,,, +GenuineIntel-6-9E,V53,/SKL/events/skylake_uncore.json,uncore,,, +GenuineIntel-6-8E,V53,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-9E,V53,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-A5,V53,/SKL/events/skylake_core.json,core,,, +GenuineIntel-6-A6,V53,/SKL/events/skylake_core.json,core,,, +GenuineIntel-6-A5,V53,/SKL/events/skylake_matrix.json,offcore,,, +GenuineIntel-6-A6,V53,/SKL/events/skylake_matrix.json,offcore,,, +GenuineIntel-6-A5,V53,/SKL/events/skylake_uncore.json,uncore,,, +GenuineIntel-6-A6,V53,/SKL/events/skylake_uncore.json,uncore,,, +GenuineIntel-6-A5,V53,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-A6,V53,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-57,V9,/KNL/events/KnightsLanding_core.json,core,,, +GenuineIntel-6-57,V9,/KNL/events/KnightsLanding_matrix.json,offcore,,, +GenuineIntel-6-57,V9,/KNL/events/KnightsLanding_uncore.json,uncore,,, +GenuineIntel-6-85,V9,/KNM/events/KnightsLanding_core.json,core,,, +GenuineIntel-6-85,V9,/KNM/events/KnightsLanding_matrix.json,offcore,,, +GenuineIntel-6-85,V9,/KNM/events/KnightsLanding_uncore.json,uncore,,, +GenuineIntel-6-55-[01234],V1.28,/SKX/events/skylakex_core.json,core,,, +GenuineIntel-6-55-[01234],V1.28,/SKX/events/skylakex_matrix.json,offcore,,, +GenuineIntel-6-55-[01234],V1.28,/SKX/events/skylakex_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-55-[01234],V1.28,/SKX/events/skylakex_uncore.json,uncore,,, +GenuineIntel-6-55-[01234],V1.28,/SKX/events/skylakex_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-55-[56789ABCDEF],V1.16,/CLX/events/cascadelakex_core.json,core,,, +GenuineIntel-6-55-[56789ABCDEF],V1.16,/CLX/events/cascadelakex_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-55-[56789ABCDEF],V1.16,/CLX/events/cascadelakex_uncore.json,uncore,,, +GenuineIntel-6-55-[56789ABCDEF],V1.16,/CLX/events/cascadelakex_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-7A,V1.01,/GLP/events/goldmontplus_core.json,core,,, +GenuineIntel-6-7A,V1.01,/GLP/events/goldmontplus_fp_arith_inst.json,fp_arith_inst,,, +GenuineIntel-6-7A,V1.01,/GLP/events/goldmontplus_matrix.json,offcore,,, +GenuineIntel-6-7D,V1.15,/ICL/events/icelake_core.json,core,,, +GenuineIntel-6-7D,V1.15,/ICL/events/icelake_uncore.json,uncore,,, +GenuineIntel-6-7E,V1.15,/ICL/events/icelake_core.json,core,,, +GenuineIntel-6-7E,V1.15,/ICL/events/icelake_uncore.json,uncore,,, +GenuineIntel-6-A7,V1.15,/ICL/events/icelake_core.json,core,,, +GenuineIntel-6-A7,V1.15,/ICL/events/icelake_uncore.json,uncore,,, +GenuineIntel-6-86,V1.20,/SNR/events/snowridgex_core.json,core,,, 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a/scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_core.json b/scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_core.json new file mode 100644 index 0000000..f5b7071 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_core.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder core event file.", + "DatePublished": "", + "Version": "", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_uncore.json b/scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_uncore.json new file mode 100644 index 0000000..4432784 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/01_missing_event_file/SPR/events/sapphirerapids_uncore.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder uncore event file.", + "DatePublished": "", + "Version": "", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/01_missing_event_file/mapfile.csv b/scripts/ci/verify_mapfile/test_data/01_missing_event_file/mapfile.csv new file mode 100644 index 0000000..e91ce7a --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/01_missing_event_file/mapfile.csv @@ -0,0 +1,4 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_uncore.json,uncore,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, diff --git a/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_core.json b/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_core.json new file mode 100644 index 0000000..833b4a9 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_core.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder core event file.", + "DatePublished": "", + "Version": "1.09", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_uncore.json b/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_uncore.json new file mode 100644 index 0000000..89769de --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/SPR/events/sapphirerapids_uncore.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder uncore event file.", + "DatePublished": "", + "Version": "1.09", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/mapfile.csv b/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/mapfile.csv new file mode 100644 index 0000000..ad19433 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/02_mismatched_versions/mapfile.csv @@ -0,0 +1,3 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.08,/SPR/events/sapphirerapids_uncore.json,uncore,,, diff --git a/scripts/ci/verify_mapfile/test_data/03_correct_event_types/mapfile.csv b/scripts/ci/verify_mapfile/test_data/03_correct_event_types/mapfile.csv new file mode 100644 index 0000000..b9253b7 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/03_correct_event_types/mapfile.csv @@ -0,0 +1,159 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-2E,V3,/NHM-EX/events/NehalemEX_core.json,core,,, +GenuineIntel-6-1E,V3,/NHM-EP/events/NehalemEP_core.json,core,,, +GenuineIntel-6-1F,V3,/NHM-EP/events/NehalemEP_core.json,core,,, +GenuineIntel-6-1A,V3,/NHM-EP/events/NehalemEP_core.json,core,,, +GenuineIntel-6-2F,V3,/WSM-EX/events/WestmereEX_core.json,core,,, +GenuineIntel-6-25,V3,/WSM-EP-SP/events/WestmereEP-SP_core.json,core,,, +GenuineIntel-6-2C,V3,/WSM-EP-DP/events/WestmereEP-DP_core.json,core,,, +GenuineIntel-6-37,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-37,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-4A,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-4A,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-4D,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-4D,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-4C,V14,/SLM/events/Silvermont_core.json,core,,, +GenuineIntel-6-4C,V14,/SLM/events/Silvermont_matrix.json,offcore,,, +GenuineIntel-6-5A,V14,/SLM/events/Silvermont_core.json,core,,, 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+GenuineIntel-6-86,V1.20,/SNR/events/snowridgex_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-8C,V1.08,/TGL/events/tigerlake_core.json,core,,, +GenuineIntel-6-8D,V1.08,/TGL/events/tigerlake_core.json,core,,, +GenuineIntel-6-8C,V1.08,/TGL/events/tigerlake_uncore.json,uncore,,, +GenuineIntel-6-8D,V1.08,/TGL/events/tigerlake_uncore.json,uncore,,, +GenuineIntel-6-8C,V1.08,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-8D,V1.08,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_uncore.json,uncore,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-6A,V1.17,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6A,V1.17,/ICX/events/icelakex_uncore.json,uncore,,, +GenuineIntel-6-6A,V1.17,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-6C,V1.17,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6C,V1.17,/ICX/events/icelakex_uncore.json,uncore,,, +GenuineIntel-6-96,V1.03,/EHL/events/elkhartlake_core.json,core,,, +GenuineIntel-6-9C,V1.03,/EHL/events/elkhartlake_core.json,core,,, +GenuineIntel-6-97,V1.16,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-97,V1.16,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-97,V1.16,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-97,V1.16,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-9A,V1.16,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-9A,V1.16,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-9A,V1.16,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-9A,V1.16,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B7,V1.16,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-B7,V1.16,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-B7,V1.16,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-B7,V1.16,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BA,V1.16,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BA,V1.16,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BA,V1.16,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BA,V1.16,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BF,V1.16,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BF,V1.16,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BF,V1.16,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BF,V1.16,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BE,V1.16,/ADL/events/alderlake_gracemont_core.json,core,,, +GenuineIntel-6-BE,V1.16,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-AA,V1.00,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-AA,V1.00,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-AC,V1.00,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-AC,V1.00,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-AD,V1.00,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AE,V1.00,/GNR/events/graniterapids_core.json,core,,, diff --git a/scripts/ci/verify_mapfile/test_data/04_platform_referencing_multiple_event_dirs/mapfile.csv b/scripts/ci/verify_mapfile/test_data/04_platform_referencing_multiple_event_dirs/mapfile.csv new file mode 100644 index 0000000..638efba --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/04_platform_referencing_multiple_event_dirs/mapfile.csv @@ -0,0 +1,13 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-3C,V33,/HSW/events/haswell_core.json,core,,, +GenuineIntel-6-45,V33,/HSW/events/haswell_core.json,core,,, +GenuineIntel-6-46,V33,/HSW/events/haswell_core.json,core,,, +GenuineIntel-6-3C,V33,/HSW/events/haswell_matrix.json,offcore,,, +GenuineIntel-6-45,V33,/HSW/events/haswell_matrix.json,offcore,,, +GenuineIntel-6-46,V33,/HSW/events/haswell_matrix.json,offcore,,, +GenuineIntel-6-3C,V33,/HSW/events/haswell_uncore.json,uncore,,, +GenuineIntel-6-45,V33,/HSW/events/haswell_uncore.json,uncore,,, +GenuineIntel-6-46,V33,/HSW/events/haswell_uncore.json,uncore,,, +GenuineIntel-6-3F,V27,/HSX/events/haswellx_core.json,core,,, +GenuineIntel-6-3C,V27,/HSX/events/haswellx_matrix.json,offcore,,, +GenuineIntel-6-3F,V27,/HSX/events/haswellx_uncore.json,uncore,,, diff --git a/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_core.json b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_core.json new file mode 100644 index 0000000..f5b7071 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_core.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder core event file.", + "DatePublished": "", + "Version": "", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore.json b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore.json new file mode 100644 index 0000000..9ed8121 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder uncore experimental event file.", + "DatePublished": "", + "Version": "", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore_experimental.json b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore_experimental.json new file mode 100644 index 0000000..4432784 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/ICX/events/icelakex_uncore_experimental.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder uncore event file.", + "DatePublished": "", + "Version": "", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/mapfile.csv b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/mapfile.csv new file mode 100644 index 0000000..bdca83e --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/05_mapfile_missing_event_file_reference/mapfile.csv @@ -0,0 +1,6 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_uncore.json,uncore,,, +GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-6C,V1.20,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6C,V1.20,/ICX/events/icelakex_uncore.json,uncore,,, diff --git a/scripts/ci/verify_mapfile/test_data/06_extra_mapfile_column/mapfile.csv b/scripts/ci/verify_mapfile/test_data/06_extra_mapfile_column/mapfile.csv new file mode 100644 index 0000000..1b81cd9 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/06_extra_mapfile_column/mapfile.csv @@ -0,0 +1,4 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-8F,V1.13,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.13,/SPR/events/sapphirerapids_uncore.json,uncore,,, +GenuineIntel-6-8F,V1.13,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,,Extra column? diff --git a/scripts/ci/verify_mapfile/test_data/07_duplicate_event_file_type/mapfile.csv b/scripts/ci/verify_mapfile/test_data/07_duplicate_event_file_type/mapfile.csv new file mode 100644 index 0000000..5ce3103 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/07_duplicate_event_file_type/mapfile.csv @@ -0,0 +1,25 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-97,V1.21,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-97,V1.21,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-97,V1.21,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-97,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-9A,V1.21,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-9A,V1.21,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-9A,V1.21,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-9A,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B7,V1.21,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-B7,V1.21,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-B7,V1.21,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-B7,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BA,V1.21,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BA,V1.21,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BA,V1.21,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BA,V1.21,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BA,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BF,V1.21,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BF,V1.21,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BF,V1.21,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BF,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BE,V1.21,/ADL/events/alderlake_gracemont_core.json,core,,, +GenuineIntel-6-BE,V1.21,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BE,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, diff --git a/scripts/ci/verify_mapfile/test_data/08_mismatched_event_file_versions/mapfile.csv b/scripts/ci/verify_mapfile/test_data/08_mismatched_event_file_versions/mapfile.csv new file mode 100644 index 0000000..ea3a36a --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/08_mismatched_event_file_versions/mapfile.csv @@ -0,0 +1,11 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore.json,uncore,,, +GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-CF,V1.14,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore.json,uncore,,, +GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-6C,V1.22,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore.json,uncore,,, +GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, diff --git a/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_core.json b/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_core.json new file mode 100644 index 0000000..833b4a9 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_core.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder core event file.", + "DatePublished": "", + "Version": "1.09", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_uncore.json b/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_uncore.json new file mode 100644 index 0000000..89769de --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/SPR/events/sapphirerapids_uncore.json @@ -0,0 +1,11 @@ +{ + "Header": { + "Copyright": "", + "Info": "Placeholder uncore event file.", + "DatePublished": "", + "Version": "1.09", + "Legend": "" + }, + "Events": [ + ] +} \ No newline at end of file diff --git a/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/mapfile.csv b/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/mapfile.csv new file mode 100644 index 0000000..7aa5e34 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/09_correct_mapfile/mapfile.csv @@ -0,0 +1,3 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_uncore.json,uncore,,, diff --git a/scripts/ci/verify_mapfile/test_data/10_bad_mapfile_version/mapfile.csv b/scripts/ci/verify_mapfile/test_data/10_bad_mapfile_version/mapfile.csv new file mode 100644 index 0000000..cadd262 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/10_bad_mapfile_version/mapfile.csv @@ -0,0 +1,3 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-8F,1.09,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.09,/SPR/events/sapphirerapids_uncore.json,uncore,,, diff --git a/scripts/ci/verify_mapfile/test_data/11_mismatched_file_type/mapfile.csv b/scripts/ci/verify_mapfile/test_data/11_mismatched_file_type/mapfile.csv new file mode 100644 index 0000000..989b306 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/11_mismatched_file_type/mapfile.csv @@ -0,0 +1,4 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-6C,V1.22,/ICX/events/icelakex_core.json,core,,, +GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore.json,core,,, +GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, diff --git a/scripts/ci/verify_mapfile/test_data/12_unexpected_file_path/mapfile.csv b/scripts/ci/verify_mapfile/test_data/12_unexpected_file_path/mapfile.csv new file mode 100644 index 0000000..b92e12e --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/12_unexpected_file_path/mapfile.csv @@ -0,0 +1,3 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-AA,V1.00,/MTL/events/meteorlake_crestmont_coree.json,hybridcore,0x20,0x000002,Atom + diff --git a/scripts/ci/verify_mapfile/test_data/13_duplicate_metric_entries/mapfile.csv b/scripts/ci/verify_mapfile/test_data/13_duplicate_metric_entries/mapfile.csv new file mode 100644 index 0000000..7c643d4 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_data/13_duplicate_metric_entries/mapfile.csv @@ -0,0 +1,16 @@ +Family-model,Version,Filename,EventType,Core Type,Native Model ID,Core Role Name +GenuineIntel-6-AD,V1.02,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AD,V1.02,/GNR/events/graniterapids_uncore.json,uncore,,, +GenuineIntel-6-AD,V1.02,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AD,V0,/GNR/metrics/graniterapids_metrics.json,metrics,,, +GenuineIntel-6-AE,V1.02,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AE,V1.02,/GNR/events/graniterapids_uncore.json,uncore,,, +GenuineIntel-6-AE,V1.02,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AD,V0,/GNR/metrics/graniterapids_metrics.json,metrics,,, +GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_core.json,core,,, +GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_uncore.json,uncore,,, +GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AF,V0,/SRF/metrics/sierraforest_metrics.json,metrics,,, +GenuineIntel-6-B6,V1.03,/GRR/events/grandridge_core.json,core,,, +GenuineIntel-6-B6,V1.03,/GRR/events/grandridge_uncore.json,uncore,,, +GenuineIntel-6-B6,V1.03,/GRR/events/grandridge_uncore_experimental.json,uncore experimental,,, diff --git a/scripts/ci/verify_mapfile/test_verify_mapfile.py b/scripts/ci/verify_mapfile/test_verify_mapfile.py new file mode 100644 index 0000000..31fd852 --- /dev/null +++ b/scripts/ci/verify_mapfile/test_verify_mapfile.py @@ -0,0 +1,149 @@ +# Copyright (C) 2024 Intel Corporation +# SPDX-License-Identifier: BSD-3-Clause + +import unittest +import jsonschema +from pathlib import Path + +from verify_mapfile import * + +_script_dir = Path(__file__).resolve().parent +_test_data_dir = Path(_script_dir, 'test_data') + + +class TestVerifyMapfileSchema(unittest.TestCase): + + def test_missing_mapfile(self): + perfmon_repo_dir = Path(_test_data_dir, 'bad_folder_path') + + with self.assertRaises(FileNotFoundError) as assertion_context: + load_mapfile(perfmon_repo_dir) + self.assertRegex(str(assertion_context.exception), r'Could not locate.*mapfile') + + def test_missing_mapfile_column(self): + perfmon_repo_dir = Path(_test_data_dir, '00_missing_mapfile_column') + + with self.assertRaises(jsonschema.exceptions.ValidationError) as assertion_context: + verify_mapfile_schema(perfmon_repo_dir) + self.assertIn('Failed validating', str(assertion_context.exception)) + + def test_extra_mapfile_column(self): + perfmon_repo_dir = Path(_test_data_dir, '06_extra_mapfile_column') + + with self.assertRaises(jsonschema.exceptions.ValidationError) as assertion_context: + verify_mapfile_schema(perfmon_repo_dir) + self.assertIn('Additional properties are not allowed', str(assertion_context.exception)) + + +class TestVerifyMapfilePaths(unittest.TestCase): + + def test_missing_event_file(self): + perfmon_repo_dir = Path(_test_data_dir, '01_missing_event_file') + + with self.assertRaises(FileNotFoundError) as assertion_context: + verify_mapfile_paths(perfmon_repo_dir) + self.assertIn('sapphirerapids_uncore_experimental.json', str(assertion_context.exception)) + self.assertIn('does not exist', str(assertion_context.exception)) + + def test_correct_files_referenced(self): + perfmon_repo_dir = Path(_test_data_dir, '09_correct_mapfile') + verify_mapfile_paths(perfmon_repo_dir) + + +class TestVerifyEventFileVersions(unittest.TestCase): + + def test_mismatched_versions(self): + perfmon_repo_dir = Path(_test_data_dir, '02_mismatched_versions') + + with self.assertRaises(RuntimeError) as assertion_context: + verify_event_file_versions(perfmon_repo_dir) + self.assertRegex(str(assertion_context.exception), r'Version \d.\d\d on mapfile line \d') + + def test_bad_mapfile_version(self): + perfmon_repo_dir = Path(_test_data_dir, '10_bad_mapfile_version') + + with self.assertRaises(RuntimeError) as assertion_context: + # Comparing event file versions first extracts versions from the mapfile column. + verify_event_file_versions(perfmon_repo_dir) + + self.assertIn('Failed to extract version', str(assertion_context.exception)) + + def test_correct_versions(self): + perfmon_repo_dir = Path(_test_data_dir, '09_correct_mapfile') + verify_event_file_versions(perfmon_repo_dir) + + +class TestVerifyEventTypeMatchesFile(unittest.TestCase): + + def test_correct_event_types(self): + perfmon_repo_dir = Path(_test_data_dir, '03_correct_event_types') + # Should not raise an exception + verify_event_type_matches_file(perfmon_repo_dir) + + def test_incorrect_file_type(self): + perfmon_repo_dir = Path(_test_data_dir, '11_mismatched_file_type') + with self.assertRaises(RuntimeError) as assertion_context: + verify_event_type_matches_file(perfmon_repo_dir) + + self.assertRegex(str(assertion_context.exception), r'expected.*uncore.*found.*core') + + def test_unexpected_file_path(self): + perfmon_repo_dir = Path(_test_data_dir, '12_unexpected_file_path') + with self.assertRaises(RuntimeError) as assertion_context: + verify_event_type_matches_file(perfmon_repo_dir) + + self.assertIn('does not match type checks', str(assertion_context.exception)) + + +class TestVerifyFamilyModelMapsToEventFiles(unittest.TestCase): + + def test_platform_referencing_multiple_event_directories(self): + perfmon_repo_dir = Path(_test_data_dir, '04_platform_referencing_multiple_event_dirs') + + with self.assertRaises(RuntimeError) as assertion_context: + verify_family_model_maps_to_event_files(perfmon_repo_dir) + self.assertIn('references multiple event directories', str(assertion_context.exception)) + + def test_mapfile_missing_event_file_reference(self): + perfmon_repo_dir = Path(_test_data_dir, '05_mapfile_missing_event_file_reference') + + with self.assertRaises(RuntimeError) as assertion_context: + verify_family_model_maps_to_event_files(perfmon_repo_dir) + self.assertRegex(str(assertion_context.exception), r'Event file .* is not referenced') + + +class TestVerifyMapfileDuplicateTypes(unittest.TestCase): + + def test_duplicate_event_file_type(self): + perfmon_repo_dir = Path(_test_data_dir, '07_duplicate_event_file_type') + + with self.assertRaises(RuntimeError) as assertion_context: + verify_mapfile_duplicate_types(perfmon_repo_dir) + self.assertIn('duplicate entry for EventType', str(assertion_context.exception)) + + def test_duplicate_metric_entries(self): + perfmon_repo_dir = Path(_test_data_dir, '13_duplicate_metric_entries') + + with self.assertRaises(RuntimeError) as assertion_context: + verify_mapfile_duplicate_types(perfmon_repo_dir) + self.assertIn('duplicate entry for EventType', str(assertion_context.exception)) + + def test_no_duplicates(self): + perfmon_repo_dir = Path(_test_data_dir, '03_correct_event_types') + # Should not raise an exception + verify_mapfile_duplicate_types(perfmon_repo_dir) + + +class TestVerifyMapfileModelUniqueVersions(unittest.TestCase): + + def test_verify_mismatched_event_versions(self): + perfmon_repo_dir = Path(_test_data_dir, '08_mismatched_event_file_versions') + + with self.assertRaises(RuntimeError) as assertion_context: + verify_mapfile_model_event_versions(perfmon_repo_dir) + self.assertIn('multiple event file versions', str(assertion_context.exception)) + + def test_ok_event_versions(self): + perfmon_repo_dir = Path(_test_data_dir, '03_correct_event_types') + # Should not raise an exception + verify_mapfile_model_event_versions(perfmon_repo_dir) diff --git a/scripts/ci/verify_mapfile/verify_mapfile.py b/scripts/ci/verify_mapfile/verify_mapfile.py new file mode 100755 index 0000000..23a2523 --- /dev/null +++ b/scripts/ci/verify_mapfile/verify_mapfile.py @@ -0,0 +1,333 @@ +#!/usr/bin/env python3 +# Copyright (C) 2024 Intel Corporation +# SPDX-License-Identifier: BSD-3-Clause + +import argparse +import csv +import json +import logging +import re +from jsonschema import validate +from pathlib import Path + +logger = logging.getLogger(__name__) + + +def load_csv(filepath: Path, delimiter: str = ','): + """Load CSV as list(dict) where each dict corresponds to a CSV row, keyed by the header.""" + with Path(filepath).open() as fi: + reader = csv.DictReader(fi, delimiter=delimiter) + return [x for x in reader] + + +def csv_to_jsonstr(filepath: Path, delimiter: str = ','): + """Convert CSV contents into a JSON str.""" + csv_dict_list = load_csv(filepath, delimiter=delimiter) + return json.dumps(csv_dict_list) + + +def load_schema(schemapath: Path): + """Basic helper to load a JSON schema.""" + with Path(schemapath).open() as f: + return json.load(f) + + +def load_mapfile(perfmon_repo_path: Path) -> list[dict]: + """Load mapfile.csv.""" + mapfile_path = Path(perfmon_repo_path, 'mapfile.csv') + + if not mapfile_path.is_file(): + raise FileNotFoundError(f'Could not locate {mapfile_path}.') + + return load_csv(mapfile_path) + + +def get_unique_mapfile_models(mapfile_data) -> list[str]: + """Find the unique set of Family-model entries.""" + models = [row['Family-model'] for row in mapfile_data] + return sorted(set(models)) + + +def validate_csv(filepath: Path, schemapath: Path, delimiter: str = ','): + """Validate the JSON conversion of the csv [filepath] by the json schema [schemapath].""" + json_s = csv_to_jsonstr(filepath, delimiter=delimiter) + json_data = json.loads(json_s) + schema = load_schema(schemapath) + + validate(json_data, schema) + + +def verify_mapfile_schema(perfmon_repo_path: Path): + """Verify all mapfile rows match the expected schema definition.""" + mapfile = Path(perfmon_repo_path, 'mapfile.csv') + # Use a path relative to verify_mapfile.py to simplify unittests. Otherwise, + # each unittest directory would need to create or link to the schema. + schema = Path(Path(__file__).resolve().parent, 'mapfile_schema.json') + + logger.info('Checking mapfile.csv schema against %s.', schema.name) + validate_csv(mapfile, schema) + + +def verify_mapfile_paths(perfmon_repo_path: Path): + """Verify files in the Filename column exist.""" + logger.info('Checking mapfile.csv event file paths.') + + for line_number, row in enumerate(load_mapfile(perfmon_repo_path), 2): + # Trim leading slash from filename and build full path + event_path = Path(perfmon_repo_path, row['Filename'][1:]) + + if not event_path.exists(): + msg = f"Event file {row['Filename']} on line {line_number} does not exist." + raise FileNotFoundError(msg) + + +def verify_event_file_versions(perfmon_repo_path: Path): + """Verify mapfile Version column matches event file Header.""" + version_re = re.compile(r'^[vV](\d{1,2}|\d\.\d\d)$') + + logger.info('Checking mapfile.csv version matches event file version.') + + for line_number, row in enumerate(load_mapfile(perfmon_repo_path), 2): + # Trim V from Version column + mapfile_version = version_re.match(row['Version']) + if not mapfile_version: + msg = (f"Failed to extract version from '{row['Version']}' on mapfile.csv line" + f" {line_number}. Expected pattern '{version_re.pattern}'.") + raise RuntimeError(msg) + mapfile_version = mapfile_version[1] + + # Load JSON version + event_file_path = Path(perfmon_repo_path, row['Filename'][1:]) + with open(event_file_path, 'r') as f: + json_header = json.load(f)['Header'] + + if mapfile_version != json_header['Version']: + msg = (f'Version {mapfile_version} on mapfile line {line_number} does not' + f' match {event_file_path.name} version {json_header["Version"]}.\n' + f'mapfile.csv row {json.dumps(row, indent=2)}\n' + f'JSON header {json.dumps(json_header, indent=2)}') + raise RuntimeError(msg) + + +def verify_event_type_matches_file(perfmon_repo_path: Path): + """ + Verify EventType column matches filename + + Examples: + WestmereEP-SP_core.json -> core + sapphirerapids_core.json -> core + sapphirerapids_uncore.json -> uncore + skylake_fp_arith_inst.json -> fp_arith_inst + alderlake_gracemont_core.json -> hybridcore (except for ADL-N) + sierraforest_metrics.json -> metrics + """ + # Certain model IDs have unique comparisons. As an example, ADL-N is not listed in the + # mapfile as a hybridcore. Use the default otherwise. + event_type_checks = { + 'default': [(re.compile(r'.*/[a-zA-Z-]*_core\.json'), 'core'), + (re.compile(r'.*/[a-z]*_[a-z]*_core\.json'), 'hybridcore'), + (re.compile(r'.*_uncore\.json'), 'uncore'), + (re.compile(r'.*_uncore_experimental\.json'), 'uncore experimental'), + (re.compile(r'.*_matrix\.json'), 'offcore'), + (re.compile(r'.*_metrics\.json'), 'metrics'), + (re.compile(r'.*_fp_arith_inst\.json'), 'fp_arith_inst')], + 'GenuineIntel-6-BE': [(re.compile(r'.*/[a-z]*_[a-z]*_core\.json'), 'core'), + (re.compile(r'.*uncore\.json'), 'uncore'), + (re.compile(r'.*uncore_experimental\.json'), 'uncore experimental')] + } + + logger.info('Checking mapfile.csv EventType matches expected filename patterns.') + + for line_number, row in enumerate(load_mapfile(perfmon_repo_path), 2): + checks = event_type_checks['default'] + if row['Family-model'] in event_type_checks: + checks = event_type_checks[row['Family-model']] + + file_pattern_matched = False # One of the file patterns matched + for file_pattern, expected_event_type in checks: + if file_pattern.match(row['Filename']): + file_pattern_matched = True + + if row['EventType'] != expected_event_type: + msg = (f"Mapfile line {line_number} expected EventType '{expected_event_type}'" + f" for {row['Filename']} but found '{row['EventType']}'.") + raise RuntimeError(msg) + + if not file_pattern_matched: + raise RuntimeError(f"Filename {row['Filename']} does not match type checks. {checks}.") + + +def verify_family_model_maps_to_event_files(perfmon_repo_path: Path): + """ + For each Family-Model verify that all event files are mentioned in mapfile.csv + + Failing example: + mapfile.csv: + + GenuineIntel-6-CF,V1.13,/SPR/events/sapphirerapids_core.json,core,,, + GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_core.json,core,,, + GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_uncore.json,uncore,,, + GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, + GenuineIntel-6-6C,V1.20,/ICX/events/icelakex_core.json,core,,, + GenuineIntel-6-6C,V1.20,/ICX/events/icelakex_uncore.json,uncore,,, + GenuineIntel-6-96,V1.04,/EHL/events/elkhartlake_core.json,core,,, + + Files in ICX/events/: + icelakex_core.json + icelakex_uncore.json + icelakex_uncore_experimental.json + Failure: + Family-Model 0x6C is missing icelakex_uncore_experimental.json. + """ + # Known exceptions. Do not flag these combinations of models and files as issues. + exceptions = { + # ADL-N is an E-Core only product. Refer to Table 1 in + # https://cdrdv2.intel.com/v1/dl/getContent/759603 + 'GenuineIntel-6-BE': ['alderlake_goldencove_core.json'], + } + + logger.info('Checking mapfile.csv for missing event files.') + + mapfile_data = load_mapfile(perfmon_repo_path) + + # With the set of unique models compare mapfile.csv rows to actual event files. + for model in get_unique_mapfile_models(mapfile_data): + # Filter for any rows with a matching model. + mapfile_model_rows = [x for x in mapfile_data if x['Family-model'] == model] + # Then extract file paths that are mentioned. The Filename column includes a leading slash + # which is trimmed before combining with the repository path. + mapfile_event_files = [ + Path(perfmon_repo_path, x['Filename'][1:]) for x in mapfile_model_rows + ] + + # Platforms should only reference event files in one directory. Platform ABC should only + # use event files in ABC/events. ABC using events in ABC/events and XYZ/events is likely + # a typo or a mistake. + mapfile_event_dir = set([x.parent for x in mapfile_event_files]) + mapfile_event_dir = [x for x in mapfile_event_dir if x.name != 'metrics'] + if len(mapfile_event_dir) != 1: + msg = (f'Family-model {model} references multiple event directories.\n' + f'{mapfile_event_dir}') + raise RuntimeError(msg) + mapfile_event_dir = mapfile_event_dir.pop() + + # Verify that all event files are mentioned in the mapfile for this specific model. + event_files = sorted(mapfile_event_dir.glob('*.json')) + for event_file in event_files: + if event_file not in mapfile_event_files: + # First check known exceptions before flagging as an actual issue. + if model in exceptions and event_file.name in exceptions[model]: + logger.warning('\tmapfile.csv %s missing row for %s. Known exception, OK.', + model, event_file.name) + continue + + event_files_msg = '\n '.join([x.name for x in event_files]) + msg = (f'Event file {event_file.name} is not referenced by {model}.\n' + f'mapfile.csv\n{json.dumps(mapfile_model_rows, indent=2)}\n' + f'Files in {mapfile_event_dir}\n {event_files_msg}') + raise RuntimeError(msg) + + +def verify_mapfile_duplicate_types(perfmon_repo_path: Path): + """ + Per Family-Model verify that there is only one instance of each event file type. + + Failing example: + mapfile.csv: + GenuineIntel-6-A7,V1.18,/ICL/events/icelake_core.json,core,,, + GenuineIntel-6-A7,V1.18,/ICL/events/icelake_uncore.json,uncore,,, + GenuineIntel-6-A7,V1.18,/ICL/events/icelake_uncore_experimental.json,uncore experimental,,, + GenuineIntel-6-A7,V1.18,/ICL/events/icelake_core.json,core,,, + GenuineIntel-6-86,V1.21,/SNR/events/snowridgex_core.json,core,,, + GenuineIntel-6-86,V1.21,/SNR/events/snowridgex_uncore.json,uncore,,, + GenuineIntel-6-86,V1.21,/SNR/events/snowridgex_uncore_experimental.json,uncore experimental,,, + Failure: + 0xA7 has two entries for 'core'. + """ + logger.info('Checking mapfile.csv for EventType duplicates.') + + mapfile_data = load_mapfile(perfmon_repo_path) + + for model in get_unique_mapfile_models(mapfile_data): + # Filter for any rows with a matching model. + mapfile_rows = [x for x in mapfile_data if x['Family-model'] == model] + + # Create a dict key based on EventType and Core Type. Otherwise, for hybrid platforms + # there would be overlapping entries for 'hybridcore'. Combinations of 'hybridcore' + # and core type should be unique. + event_and_core_types = {} + for row in mapfile_rows: + event_type = row['EventType'] + core_type = row['Core Type'] + key = f'{event_type}_{core_type}' + + # This row already existed if the key is present. + if key in event_and_core_types: + msg = (f'Family-model {model} includes duplicate entry for EventType={event_type} and ' + f'Core Type={core_type}.') + raise RuntimeError(msg) + + event_and_core_types[key] = 1 + + +def verify_mapfile_model_event_versions(perfmon_repo_path: Path): + """ + Per Family-Model verify only one version is used across all event entries. + + Failing example: + mapfile.csv: + GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_core.json,core,,, + GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore.json,uncore,,, + GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, + GenuineIntel-6-CF,V1.14,/SPR/events/sapphirerapids_core.json,core,,, + GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_core.json,core,,, + GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore.json,uncore,,, + GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, + GenuineIntel-6-6C,V1.22,/ICX/events/icelakex_core.json,core,,, + GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore.json,uncore,,, + GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,, + Failure: + 0x6C references both V1.21 and V1.22. + """ + + logger.info('Checking mapfile.csv for consistent event versions.') + + mapfile_data = load_mapfile(perfmon_repo_path) + + for model in get_unique_mapfile_models(mapfile_data): + # Extract file versions for rows with a matching model. + event_file_versions = [ + x['Version'] + for x in mapfile_data + if x['Family-model'] == model and x['EventType'] != 'metrics' + ] + event_file_versions = set(event_file_versions) + + if len(event_file_versions) != 1: + msg = f'Family-model {model} has multiple event file versions {event_file_versions}' + raise RuntimeError(msg) + + +if __name__ == '__main__': + logging.basicConfig(format='%(levelname).4s; %(message)s', level=logging.INFO) + + script_dir = Path(__file__).resolve().parent + perfmon_repo_path = script_dir.parents[2] + + parser = argparse.ArgumentParser(description='Verify mapfile.csv.', + epilog='This utility does not require any arguments.') + args = parser.parse_args() + + verifications = [ + verify_mapfile_schema, + verify_mapfile_paths, + verify_event_file_versions, + verify_event_type_matches_file, + verify_family_model_maps_to_event_files, + verify_mapfile_duplicate_types, + verify_mapfile_model_event_versions, + ] + for verification in verifications: + verification(perfmon_repo_path) + + logger.info('All mapfile.csv checks passed.')