diff --git a/MTL/events/meteorlake_crestmont_core.json b/MTL/events/meteorlake_crestmont_core.json
index cf08dcbd..623e4799 100644
--- a/MTL/events/meteorlake_crestmont_core.json
+++ b/MTL/events/meteorlake_crestmont_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.03",
-    "DatePublished": "05/30/2023",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04",
+    "DatePublished": "06/29/2023",
+    "Version": "1.04",
     "Legend": ""
   },
   "Events": [
diff --git a/MTL/events/meteorlake_redwoodcove_core.json b/MTL/events/meteorlake_redwoodcove_core.json
index 0526a0b3..7425e84f 100644
--- a/MTL/events/meteorlake_redwoodcove_core.json
+++ b/MTL/events/meteorlake_redwoodcove_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.03",
-    "DatePublished": "05/30/2023",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04",
+    "DatePublished": "06/29/2023",
+    "Version": "1.04",
     "Legend": ""
   },
   "Events": [
@@ -127,6 +127,126 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x03",
+      "UMask": "0x04",
+      "EventName": "LD_BLOCKS.ADDRESS_ALIAS",
+      "BriefDescription": "False dependencies in MOB due to partial compare on address.",
+      "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x03",
+      "UMask": "0x82",
+      "EventName": "LD_BLOCKS.STORE_FORWARD",
+      "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
+      "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x03",
+      "UMask": "0x88",
+      "EventName": "LD_BLOCKS.NO_SR",
+      "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+      "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x09",
+      "UMask": "0x01",
+      "EventName": "MEMORY_ORDERING.MD_NUKE",
+      "BriefDescription": "MEMORY_ORDERING.MD_NUKE",
+      "PublicDescription": "MEMORY_ORDERING.MD_NUKE",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x09",
+      "UMask": "0x02",
+      "EventName": "MEMORY_ORDERING.MRN_NUKE",
+      "BriefDescription": "Counts the number of memory ordering machine clears due to memory renaming.",
+      "PublicDescription": "Counts the number of memory ordering machine clears due to memory renaming.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x11",
       "UMask": "0x02",
@@ -399,7 +519,319 @@
       "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x12",
+      "UMask": "0x20",
+      "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
+      "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
+      "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x02",
+      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
+      "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
+      "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x04",
+      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
+      "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
+      "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x08",
+      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
+      "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
+      "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x0e",
+      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
+      "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
+      "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x10",
+      "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
+      "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
+      "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x10",
+      "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
+      "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
+      "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x13",
+      "UMask": "0x20",
+      "EventName": "DTLB_STORE_MISSES.STLB_HIT",
+      "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
+      "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x01",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
+      "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
+      "PublicDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x01",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+      "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
+      "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x01",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
+      "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
+      "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "6",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x02",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
+      "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
+      "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x20",
+      "UMask": "0x02",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+      "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
+      "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
@@ -416,19 +848,19 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x12",
-      "UMask": "0x20",
-      "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-      "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-      "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
+      "EventCode": "0x20",
+      "UMask": "0x04",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
+      "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
+      "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
-      "CounterMask": "0",
+      "CounterMask": "1",
       "Invert": "0",
       "EdgeDetect": "0",
       "PEBS": "0",
@@ -440,14 +872,14 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
-      "UMask": "0x02",
-      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-      "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
-      "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "EventCode": "0x20",
+      "UMask": "0x04",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
+      "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
+      "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
@@ -464,19 +896,19 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
-      "UMask": "0x04",
-      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-      "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
-      "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "EventCode": "0x20",
+      "UMask": "0x08",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
+      "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
+      "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
-      "CounterMask": "0",
+      "CounterMask": "1",
       "Invert": "0",
       "EdgeDetect": "0",
       "PEBS": "0",
@@ -488,14 +920,14 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
+      "EventCode": "0x20",
       "UMask": "0x08",
-      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
-      "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
-      "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
+      "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
+      "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
@@ -512,19 +944,19 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
-      "UMask": "0x0e",
-      "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-      "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-      "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
+      "EventCode": "0x20",
+      "UMask": "0x10",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
+      "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
+      "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
-      "CounterMask": "0",
+      "CounterMask": "1",
       "Invert": "0",
       "EdgeDetect": "0",
       "PEBS": "0",
@@ -536,19 +968,19 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
+      "EventCode": "0x20",
       "UMask": "0x10",
-      "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
-      "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
-      "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
+      "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
+      "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
-      "CounterMask": "1",
+      "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
       "PEBS": "0",
@@ -560,19 +992,19 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
+      "EventCode": "0x20",
       "UMask": "0x10",
-      "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-      "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
-      "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
+      "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
+      "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
+      "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.  Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
-      "SampleAfterValue": "100003",
+      "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
-      "CounterMask": "0",
+      "CounterMask": "6",
       "Invert": "0",
       "EdgeDetect": "0",
       "PEBS": "0",
@@ -584,11 +1016,11 @@
       "Speculative": "1"
     },
     {
-      "EventCode": "0x13",
-      "UMask": "0x20",
-      "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-      "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-      "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
+      "EventCode": "0x21",
+      "UMask": "0x01",
+      "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
+      "BriefDescription": "Demand Data Read requests sent to uncore",
+      "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "100003",
@@ -609,10 +1041,10 @@
     },
     {
       "EventCode": "0x21",
-      "UMask": "0x01",
-      "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
-      "BriefDescription": "Demand Data Read requests sent to uncore",
-      "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
+      "UMask": "0x02",
+      "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
+      "BriefDescription": "Cacheable and Non-Cacheable code read requests",
+      "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "100003",
@@ -1567,6 +1999,126 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x40",
+      "UMask": "0x01",
+      "EventName": "SW_PREFETCH_ACCESS.NTA",
+      "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+      "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x40",
+      "UMask": "0x02",
+      "EventName": "SW_PREFETCH_ACCESS.T0",
+      "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+      "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x40",
+      "UMask": "0x04",
+      "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+      "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+      "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x40",
+      "UMask": "0x08",
+      "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+      "BriefDescription": "Number of PREFETCHW instructions executed.",
+      "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x42",
+      "UMask": "0x02",
+      "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
+      "BriefDescription": "Cycles when L1D is locked",
+      "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x43",
       "UMask": "0xfd",
@@ -1591,6 +2143,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x44",
+      "UMask": "0x01",
+      "EventName": "MEM_STORE_RETIRED.L2_HIT",
+      "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
+      "PublicDescription": "MEM_STORE_RETIRED.L2_HIT",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0x47",
       "UMask": "0x03",
@@ -1759,6 +2335,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x48",
+      "UMask": "0x04",
+      "EventName": "L1D_PEND_MISS.L2_STALLS",
+      "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
+      "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x51",
       "UMask": "0x01",
@@ -1855,6 +2455,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x62",
+      "UMask": "0x10",
+      "EventName": "DSB_FILL.FB_STALL_OT",
+      "BriefDescription": "DSB_FILL.FB_STALL_OT",
+      "PublicDescription": "DSB_FILL.FB_STALL_OT",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x75",
       "UMask": "0x01",
@@ -2679,7 +3303,31 @@
       "PublicDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "0,1,2,3,4,5,6,7",
-      "SampleAfterValue": "10000003",
+      "SampleAfterValue": "10000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xa5",
+      "UMask": "0x01",
+      "EventName": "RS.EMPTY_RESOURCE",
+      "BriefDescription": "RS.EMPTY_RESOURCE",
+      "PublicDescription": "RS.EMPTY_RESOURCE",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
@@ -3007,6 +3655,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xad",
+      "UMask": "0x01",
+      "EventName": "INT_MISC.CLEARS_COUNT",
+      "BriefDescription": "Clears speculative count",
+      "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "500009",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "1",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xad",
       "UMask": "0x03",
@@ -3031,6 +3703,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xad",
+      "UMask": "0x08",
+      "EventName": "INT_MISC.RAT_STALLS",
+      "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
+      "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xad",
       "UMask": "0x10",
@@ -3751,6 +4447,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xb3",
+      "UMask": "0x04",
+      "EventName": "FP_ARITH_DISPATCHED.PORT_5",
+      "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
+      "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xc0",
       "UMask": "0x00",
@@ -3775,6 +4495,54 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xc0",
+      "UMask": "0x02",
+      "EventName": "INST_RETIRED.NOP",
+      "BriefDescription": "Retired NOP instructions.",
+      "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
+    {
+      "EventCode": "0xc0",
+      "UMask": "0x08",
+      "EventName": "INST_RETIRED.REP_ITERATION",
+      "BriefDescription": "Iterations of Repeat string retired instructions.",
+      "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xc0",
       "UMask": "0x10",
@@ -3823,6 +4591,30 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xc1",
+      "UMask": "0x08",
+      "EventName": "ASSISTS.PAGE_FAULT",
+      "BriefDescription": "ASSISTS.PAGE_FAULT",
+      "PublicDescription": "ASSISTS.PAGE_FAULT",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xc1",
       "UMask": "0x10",
@@ -3943,6 +4735,54 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xc2",
+      "UMask": "0x02",
+      "EventName": "UOPS_RETIRED.STALLS",
+      "BriefDescription": "Cycles without actually retired uops.",
+      "PublicDescription": "This event counts cycles without actually retired uops.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "1",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
+    {
+      "EventCode": "0xc2",
+      "UMask": "0x02",
+      "EventName": "UOPS_RETIRED.CYCLES",
+      "BriefDescription": "Cycles with retired uop(s).",
+      "PublicDescription": "Counts cycles where at least one uop has retired.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xc2",
       "UMask": "0x04",
@@ -3991,6 +4831,54 @@
       "Deprecated": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xc3",
+      "UMask": "0x02",
+      "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
+      "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
+      "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xc3",
+      "UMask": "0x04",
+      "EventName": "MACHINE_CLEARS.SMC",
+      "BriefDescription": "Self-modifying code (SMC) detected.",
+      "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xc4",
       "UMask": "0x00",
@@ -4279,6 +5167,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xc5",
+      "UMask": "0x08",
+      "EventName": "BR_MISP_RETIRED.RET",
+      "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
+      "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100007",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xc5",
       "UMask": "0x10",
@@ -4555,7 +5467,31 @@
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
       "CollectPEBSRecord": "2",
-      "TakenAlone": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
+    {
+      "EventCode": "0xc6",
+      "UMask": "0x02",
+      "EventName": "FRONTEND_RETIRED.MISP_ANT",
+      "BriefDescription": "Mispredicted Retired ANT branches",
+      "PublicDescription": "ANT retired branches that got just mispredicted",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100007",
+      "MSRIndex": "0x3F7",
+      "MSRValue": "0x9",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
@@ -4569,15 +5505,15 @@
     },
     {
       "EventCode": "0xc6",
-      "UMask": "0x02",
-      "EventName": "FRONTEND_RETIRED.MISP_ANT",
-      "BriefDescription": "Mispredicted Retired ANT branches",
-      "PublicDescription": "ANT retired branches that got just mispredicted",
+      "UMask": "0x03",
+      "EventName": "FRONTEND_RETIRED.DSB_MISS",
+      "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
+      "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
       "Counter": "0,1,2,3,4,5,6,7",
       "PEBScounters": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "100007",
       "MSRIndex": "0x3F7",
-      "MSRValue": "0x9",
+      "MSRValue": "0x11",
       "CollectPEBSRecord": "2",
       "TakenAlone": "1",
       "CounterMask": "0",
@@ -4639,6 +5575,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xc6",
+      "UMask": "0x03",
+      "EventName": "FRONTEND_RETIRED.L2_MISS",
+      "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
+      "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100007",
+      "MSRIndex": "0x3F7",
+      "MSRValue": "0x13",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xc6",
       "UMask": "0x03",
@@ -4903,6 +5863,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xc6",
+      "UMask": "0x03",
+      "EventName": "FRONTEND_RETIRED.STLB_MISS",
+      "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
+      "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100007",
+      "MSRIndex": "0x3F7",
+      "MSRValue": "0x15",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xc6",
       "UMask": "0x03",
@@ -4951,6 +5935,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xc6",
+      "UMask": "0x03",
+      "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
+      "BriefDescription": "Retired Instructions who experienced DSB miss.",
+      "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "100007",
+      "MSRIndex": "0x3F7",
+      "MSRValue": "0x1",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xc6",
       "UMask": "0x03",
@@ -5383,6 +6391,54 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xcd",
+      "UMask": "0x01",
+      "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
+      "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
+      "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency.",
+      "Counter": "1,2,3,4,5,6,7",
+      "PEBScounters": "1,2,3,4,5,6,7",
+      "SampleAfterValue": "53",
+      "MSRIndex": "0x3F6",
+      "MSRValue": "0x400",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "2",
+      "Data_LA": "1",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
+    {
+      "EventCode": "0xcd",
+      "UMask": "0x01",
+      "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048",
+      "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.",
+      "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.  Reported latency may be longer than just the memory latency.",
+      "Counter": "1,2,3,4,5,6,7",
+      "PEBScounters": "1,2,3,4,5,6,7",
+      "SampleAfterValue": "23",
+      "MSRIndex": "0x3F6",
+      "MSRValue": "0x800",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "1",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "2",
+      "Data_LA": "1",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xcd",
       "UMask": "0x02",
@@ -5815,6 +6871,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xd2",
+      "UMask": "0x01",
+      "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
+      "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
+      "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "20011",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "1",
+      "Data_LA": "1",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0xd2",
       "UMask": "0x02",
@@ -5983,6 +7063,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0xe0",
+      "UMask": "0x20",
+      "EventName": "MISC2_RETIRED.LFENCE",
+      "BriefDescription": "LFENCE instructions retired",
+      "PublicDescription": "number of LFENCE retired instructions",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "400009",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xe5",
       "UMask": "0x03",
@@ -6222,6 +7326,126 @@
       "Offcore": "0",
       "Deprecated": "0",
       "Speculative": "1"
+    },
+    {
+      "EventCode": "0xec",
+      "UMask": "0x10",
+      "EventName": "CPU_CLK_UNHALTED.C01",
+      "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
+      "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xec",
+      "UMask": "0x20",
+      "EventName": "CPU_CLK_UNHALTED.C02",
+      "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
+      "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xec",
+      "UMask": "0x40",
+      "EventName": "CPU_CLK_UNHALTED.PAUSE",
+      "BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
+      "PublicDescription": "CPU_CLK_UNHALTED.PAUSE",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xec",
+      "UMask": "0x40",
+      "EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
+      "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
+      "PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "1",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0xec",
+      "UMask": "0x70",
+      "EventName": "CPU_CLK_UNHALTED.C0_WAIT",
+      "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
+      "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
     }
   ]
 }
\ No newline at end of file
diff --git a/MTL/events/meteorlake_uncore.json b/MTL/events/meteorlake_uncore.json
index a4e96e6d..3ab7251d 100644
--- a/MTL/events/meteorlake_uncore.json
+++ b/MTL/events/meteorlake_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.03",
-    "DatePublished": "05/30/2023",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04",
+    "DatePublished": "06/29/2023",
+    "Version": "1.04",
     "Legend": ""
   },
   "Events": [
diff --git a/SPR/events/sapphirerapids_core.json b/SPR/events/sapphirerapids_core.json
index 70ae79f8..eff171d9 100644
--- a/SPR/events/sapphirerapids_core.json
+++ b/SPR/events/sapphirerapids_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.14",
-    "DatePublished": "06/19/2023",
-    "Version": "1.14",
+    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
+    "DatePublished": "06/28/2023",
+    "Version": "1.15",
     "Legend": ""
   },
   "Events": [
@@ -8311,6 +8311,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0x2A,0x2B",
+      "UMask": "0x01",
+      "EventName": "OCR.DEMAND_DATA_RD.PMM",
+      "BriefDescription": "Counts demand data reads that were supplied by PMM.",
+      "PublicDescription": "Counts demand data reads that were supplied by PMM.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x1a6,0x1a7",
+      "MSRValue": "0x703C00001",
+      "CollectPEBSRecord": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "1",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0x2A,0x2B",
       "UMask": "0x01",
@@ -8911,6 +8935,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0x2A,0x2B",
+      "UMask": "0x01",
+      "EventName": "OCR.DEMAND_DATA_RD.LOCAL_SOCKET_PMM",
+      "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
+      "PublicDescription": "Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x1a6,0x1a7",
+      "MSRValue": "0x700C00001",
+      "CollectPEBSRecord": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "1",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0x2A,0x2B",
       "UMask": "0x01",
diff --git a/SPR/events/sapphirerapids_uncore.json b/SPR/events/sapphirerapids_uncore.json
index c9aee42e..6483ecc7 100644
--- a/SPR/events/sapphirerapids_uncore.json
+++ b/SPR/events/sapphirerapids_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.14",
-    "DatePublished": "06/19/2023",
-    "Version": "1.14",
+    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
+    "DatePublished": "06/28/2023",
+    "Version": "1.15",
     "Legend": ""
   },
   "Events": [
diff --git a/SPR/events/sapphirerapids_uncore_experimental.json b/SPR/events/sapphirerapids_uncore_experimental.json
index caf40667..5351180f 100644
--- a/SPR/events/sapphirerapids_uncore_experimental.json
+++ b/SPR/events/sapphirerapids_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.14",
-    "DatePublished": "06/19/2023",
-    "Version": "1.14",
+    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
+    "DatePublished": "06/28/2023",
+    "Version": "1.15",
     "Legend": ""
   },
   "Events": [
diff --git a/mapfile.csv b/mapfile.csv
index 5434fe5a..0ffcb7bd 100644
--- a/mapfile.csv
+++ b/mapfile.csv
@@ -115,10 +115,10 @@ GenuineIntel-6-8C,V1.13,/TGL/events/tigerlake_uncore.json,uncore,,,
 GenuineIntel-6-8D,V1.13,/TGL/events/tigerlake_uncore.json,uncore,,,
 GenuineIntel-6-8C,V1.13,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-8D,V1.13,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_core.json,core,,,
-GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore.json,uncore,,,
-GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-CF,V1.14,/SPR/events/sapphirerapids_core.json,core,,,
+GenuineIntel-6-8F,V1.15,/SPR/events/sapphirerapids_core.json,core,,,
+GenuineIntel-6-8F,V1.15,/SPR/events/sapphirerapids_uncore.json,uncore,,,
+GenuineIntel-6-8F,V1.15,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-CF,V1.15,/SPR/events/sapphirerapids_core.json,core,,,
 GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_core.json,core,,,
 GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore.json,uncore,,,
 GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
@@ -148,12 +148,12 @@ GenuineIntel-6-BF,V1.21,/ADL/events/alderlake_uncore.json,uncore,,,
 GenuineIntel-6-BF,V1.21,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-BE,V1.21,/ADL/events/alderlake_gracemont_core.json,core,,,
 GenuineIntel-6-BE,V1.21,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-AA,V1.03,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom
-GenuineIntel-6-AA,V1.03,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core
-GenuineIntel-6-AA,V1.03,/MTL/events/meteorlake_uncore.json,uncore,,,
-GenuineIntel-6-AC,V1.03,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom
-GenuineIntel-6-AC,V1.03,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core
-GenuineIntel-6-AC,V1.03,/MTL/events/meteorlake_uncore.json,uncore,,,
+GenuineIntel-6-AA,V1.04,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom
+GenuineIntel-6-AA,V1.04,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core
+GenuineIntel-6-AA,V1.04,/MTL/events/meteorlake_uncore.json,uncore,,,
+GenuineIntel-6-AC,V1.04,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom
+GenuineIntel-6-AC,V1.04,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core
+GenuineIntel-6-AC,V1.04,/MTL/events/meteorlake_uncore.json,uncore,,,
 GenuineIntel-6-AD,V1.01,/GNR/events/graniterapids_core.json,core,,,
 GenuineIntel-6-AE,V1.01,/GNR/events/graniterapids_core.json,core,,,
 GenuineIntel-6-AF,V1.00,/SRF/events/sierraforest_core.json,core,,,