From c4744e49f60ea3bce5a38d4917bcde8eb8abb7e1 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 19 Sep 2024 16:33:30 +0200 Subject: [PATCH] [LSR] Regenerate test checks (NFC) --- .../AMDGPU/preserve-addrspace-assert.ll | 68 +++++++++++++++---- .../ARM/illegal-addr-modes.ll | 8 +-- 2 files changed, 59 insertions(+), 17 deletions(-) diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll index cd161fea9c1485..5e72e13a26edb9 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -loop-reduce %s | FileCheck %s ; Test for assert resulting from inconsistent isLegalAddressingMode @@ -7,13 +8,36 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3 %0 = type { i32, double, i32, float } -; CHECK-LABEL: @lsr_crash_preserve_addrspace_unknown_type( -; CHECK: %scevgep1 = getelementptr i8, ptr addrspace(3) %tmp, i32 8 -; CHECK: load double, ptr addrspace(3) %scevgep1 -; CHECK: %scevgep = getelementptr i8, ptr addrspace(3) %tmp, i32 16 -; CHECK: %tmp14 = load i32, ptr addrspace(3) %scevgep define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type() #0 { +; CHECK-LABEL: define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[BB:.*]]: +; CHECK-NEXT: br label %[[BB1:.*]] +; CHECK: [[BB1]]: +; CHECK-NEXT: [[TMP:%.*]] = phi ptr addrspace(3) [ undef, %[[BB]] ], [ [[TMP18:%.*]], %[[BB17:.*]] ] +; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 8 +; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr addrspace(3) [[SCEVGEP1]], align 8 +; CHECK-NEXT: br label %[[BB4:.*]] +; CHECK: [[BB4]]: +; CHECK-NEXT: br i1 false, label %[[BB8:.*]], label %[[BB5:.*]] +; CHECK: [[BB5]]: +; CHECK-NEXT: unreachable +; CHECK: [[BB8]]: +; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(3) [[TMP]], align 4 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 0, [[TMP10]] +; CHECK-NEXT: br i1 [[TMP11]], label %[[BB12:.*]], label %[[BB17]] +; CHECK: [[BB12]]: +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 16 +; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(3) [[SCEVGEP]], align 4 +; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 0, [[TMP14]] +; CHECK-NEXT: br i1 [[TMP15]], label %[[BB16:.*]], label %[[BB17]] +; CHECK: [[BB16]]: +; CHECK-NEXT: unreachable +; CHECK: [[BB17]]: +; CHECK-NEXT: [[TMP18]] = getelementptr inbounds [[TMP0:%.*]], ptr addrspace(3) [[TMP]], i64 2 +; CHECK-NEXT: br label %[[BB1]] +; bb: br label %bb1 @@ -48,15 +72,33 @@ bb17: ; preds = %bb12, %bb8 br label %bb1 } -; CHECK-LABEL: @lsr_crash_preserve_addrspace_unknown_type2( -; CHECK: %idx = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j -; CHECK: %idx1 = getelementptr inbounds i8, ptr addrspace(3) %array2, i32 %j -; CHECK: %t = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j -; CHECK: %n8 = load i8, ptr addrspace(5) %t, align 4 -; CHECK: call void @llvm.memcpy.p5.p3.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false) -; CHECK: call void @llvm.memmove.p5.p3.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false) -; CHECK: call void @llvm.memset.p5.i64(ptr addrspace(5) %idx, i8 42, i64 42, i1 false) define void @lsr_crash_preserve_addrspace_unknown_type2(ptr addrspace(5) %array, ptr addrspace(3) %array2) { +; CHECK-LABEL: define void @lsr_crash_preserve_addrspace_unknown_type2( +; CHECK-SAME: ptr addrspace(5) [[ARRAY:%.*]], ptr addrspace(3) [[ARRAY2:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[FOR_BODY:.*]] +; CHECK: [[FOR_BODY]]: +; CHECK-NEXT: [[J:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_INC:.*]] ], [ 0, %[[ENTRY]] ] +; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ARRAY]], i32 [[J]] +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[ARRAY2]], i32 [[J]] +; CHECK-NEXT: [[T:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ARRAY]], i32 [[J]] +; CHECK-NEXT: [[N8:%.*]] = load i8, ptr addrspace(5) [[T]], align 4 +; CHECK-NEXT: [[N7:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[T]], i32 42 +; CHECK-NEXT: [[N9:%.*]] = load i8, ptr addrspace(5) [[N7]], align 4 +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[J]], 42 +; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN17:.*]], label %[[FOR_INC]] +; CHECK: [[IF_THEN17]]: +; CHECK-NEXT: call void @llvm.memcpy.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false) +; CHECK-NEXT: call void @llvm.memmove.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false) +; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[IDX]], i8 42, i64 42, i1 false) +; CHECK-NEXT: br label %[[FOR_INC]] +; CHECK: [[FOR_INC]]: +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i1 [[CMP]], true +; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[J]], 1 +; CHECK-NEXT: br i1 [[EXITCOND]], label %[[END:.*]], label %[[FOR_BODY]] +; CHECK: [[END]]: +; CHECK-NEXT: ret void +; entry: br label %for.body diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll index 7d7c7efdfa2525..745b54e2bdc642 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll @@ -18,8 +18,8 @@ target triple = "thumbv6m-arm-none-eabi" ; Test case 01: -1*reg is not free for the Thumb1 target. define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n) nounwind { -; CHECK-LABEL: define ptr @negativeOneCase -; CHECK-SAME: (ptr returned [[A:%.*]], ptr nocapture readonly [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-LABEL: define ptr @negativeOneCase( +; CHECK-SAME: ptr returned [[A:%.*]], ptr nocapture readonly [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 -1 ; CHECK-NEXT: br label [[WHILE_COND:%.*]] @@ -85,8 +85,8 @@ while.end8: ; preds = %while.cond2 ; Test case 02: 4*reg({0,+,-1}) and -4*reg({0,+,-1}) are not supported for ; the Thumb1 target. define void @negativeFourCase(ptr %ptr1, ptr %ptr2) nounwind { -; CHECK-LABEL: define void @negativeFourCase -; CHECK-SAME: (ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] { +; CHECK-LABEL: define void @negativeFourCase( +; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[FOR_COND6_PREHEADER_US_I_I:%.*]] ; CHECK: for.cond6.preheader.us.i.i: