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EMMC data end bit error #162

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HiFiPhile opened this issue Apr 27, 2023 · 2 comments
Open

EMMC data end bit error #162

HiFiPhile opened this issue Apr 27, 2023 · 2 comments

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@HiFiPhile
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HiFiPhile commented Apr 27, 2023

Hardware: SAMA5D27 customized board, EMMC connected to SDMMC0. EMMC model Kingston EMMC08G-ML36-01B00.

Version: e05486a

On our board I met an issue where bootstrap report an error of SDHC: Error detected in status: 0x8020, 0x40, which seems to be data end bit error.

However the EMMC seems working, it can be read and write by SAM-BA, also U-Boot loaded correctly.

CONFIG_CRYSTAL_24_000MHZ=y
CONFIG_CPU_CLK_498MHZ=y
CONFIG_CONSOLE_INDEX=0
CONFIG_DEBUG=y
CONFIG_DDR_SET_BY_DEVICE=y
CONFIG_DDR_AD220032D=y
CONFIG_SDCARD=y
# CONFIG_SDHC_8BIT_SUPPORT is not set
CONFIG_LED_ON_BOARD=y
CONFIG_LED_R_ON_PIOA=y
CONFIG_LED_R_PIN=13
CONFIG_LED_G_ON_PIOA=y
CONFIG_LED_G_PIN=11
CONFIG_LED_G_VALUE=0
AT91Bootstrap 4.0.6-rc1 (2023-04-26 14:27:58)

SD/MMC: Image: Read file u-boot.bin to 0x26f00000
MMC: ADMA supported
MMC: Specification Version 4.0 or higher
MMC: v5.1 detected
MMC: highspeed supported
MMC: Dual Data Rate supported
MMC: detecting buswidth...
SDHC: Error detected in status: 0x8020, 0x40
MMC: 4-bit bus width detected
SD/MMC: Done to load image


U-Boot 2022.01-linux4sam-2022.10-00001-gc7b4dece46-dirty (Apr 27 2023 - 17:54:09 +0200)

CPU:   SAMA5D27 2G bits LPDDR2 SDRAM
Crystal frequency:       24 MHz
CPU clock        :      492 MHz
Master clock     :      164 MHz

DRAM:  256 MiB
MMC:   sdio-host@a0000000: 0
Loading Environment from FAT... OK
In:    serial@f801c000
Out:   serial@f801c000
Err:   serial@f801c000
Model: DUMMY
Net:   eth0: ethernet@f8008000

Below is the schematic, these connections are routed as impedance & length matched line, so there is a minimal chance to have signal integrity issue.

image
image

@SimoneBongini
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Hello,
I got the same problem. Did you resolve?

@HiFiPhile
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No it's still exist. But looking into the code seems it's just a false warning during bus width detection.

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