-
Notifications
You must be signed in to change notification settings - Fork 1
/
arm-unwind-dump.cpp
877 lines (736 loc) · 25.8 KB
/
arm-unwind-dump.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
//===-- arm-unwind-dump.cpp - ARM Unwind Opcode Tool ----------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is a testing tool for ARM ELF EHABI unwind opcodes.
//
//===----------------------------------------------------------------------===//
#include <llvm/ADT/OwningPtr.h>
#include <llvm/Object/ELF.h>
#include <llvm/Object/ELFObjectFile.h>
#include <llvm/Object/ELFTypes.h>
#include <llvm/Object/ObjectFile.h>
#include <llvm/Support/CommandLine.h>
#include <llvm/Support/Endian.h>
#include <llvm/Support/Format.h>
#include <llvm/Support/FormattedStream.h>
#include <llvm/Support/MemoryBuffer.h>
#include <llvm/Support/system_error.h>
#include <algorithm>
#include <vector>
#include <stdlib.h>
using namespace llvm;
using namespace llvm::object;
namespace {
cl::opt<std::string> InputFile(
cl::Positional, cl::desc("<input file>"), cl::init("-"));
bool IsError(error_code EC) {
if (!EC) return false;
errs() << "ERROR: " << EC.message() << "\n";
errs().flush();
return true;
}
void Ensure(error_code EC) {
if (IsError(EC)) {
exit(EXIT_FAILURE);
}
}
bool DecodeULEB128(uint64_t &Result, unsigned &Len,
const std::vector<uint8_t> &Data, size_t Begin) {
size_t Pos = Begin;
unsigned Shift = 0;
uint64_t Value = 0;
do {
if (Pos >= Data.size()) {
return false;
}
Value += (Data[Pos] & 0x7fu) << Shift;
Shift += 7;
} while (Data[Pos++] >= 128);
Result = Value;
Len = Pos - Begin;
return true;
}
void DumpHex(formatted_raw_ostream &OS, const std::vector<uint8_t> &Data) {
size_t size = Data.size();
for (size_t i = 0; i < size; i += 16) {
OS << format("%08zx | ", i);
for (size_t j = i, n = std::min(j + 16, size); j < n; ++j) {
OS << format(" %02x", static_cast<unsigned>(Data[j]));
}
OS << "\n";
}
}
} // end anonymous namespace
typedef ELFType<support::little, 4, false> ARM_ELFType;
typedef ELFObjectFile<ARM_ELFType> ARM_ELFObjectFile;
typedef ELFFile<ARM_ELFType> ARM_ELFFile;
typedef Elf_Shdr_Impl<ARM_ELFType> ARM_ELF_Shdr;
typedef Elf_Sym_Impl<ARM_ELFType> ARM_ELF_Sym;
typedef Elf_Dyn_Impl<ARM_ELFType> ARM_ELF_Dyn;
typedef Elf_Rel_Impl<ARM_ELFType, false> ARM_ELF_Rel;
typedef Elf_Rel_Impl<ARM_ELFType, true> ARM_ELF_Rela;
class ARMUnwindOpcodesDisassembler {
private:
ARM_ELFObjectFile &ObjFile;
formatted_raw_ostream &OS;
public:
ARMUnwindOpcodesDisassembler(ARM_ELFObjectFile &ObjFile_,
formatted_raw_ostream &OS_);
void Dump();
private:
section_iterator getSection(size_t i);
symbol_iterator getSymbol(section_iterator Section,
uint64_t Offset,
SymbolRef::Type Ty);
relocation_iterator getRelocation(section_iterator Section,
uint64_t Offset,
uint64_t Type);
const ARM_ELF_Shdr *getELFSectionHeader(section_iterator Section) {
DataRefImpl DRI = Section->getRawDataRefImpl();
return reinterpret_cast<const ARM_ELF_Shdr *>(DRI.p);
}
int64_t getELFRelocationAddend(relocation_iterator Reloc) {
int64_t Addend = 0;
Ensure(ObjFile.getRelocationAddend(Reloc->getRawDataRefImpl(), Addend));
return Addend;
}
void DumpSections();
void DumpSection(section_iterator Section);
void DumpExIdxEntries(section_iterator Section);
void DumpExIdxEntry(section_iterator Section,
StringRef Contents,
uint64_t Offset);
void DecodeOpcodes(const std::vector<uint8_t> &Opcodes);
// vsp = vsp + (a << 2) + 4
void Decode_00aaaaaa(llvm::raw_ostream &OS, uint16_t Opcode);
// vsp = vsp - (a << 2) - 4
void Decode_01aaaaaa(llvm::raw_ostream &OS, uint16_t Opcode);
// refuse unwind
void Decode_10000000_00000000(llvm::raw_ostream &OS, uint16_t Opcode);
// pop r[4-15]
void Decode_1000aaaa_bbbbbbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// vsp = r[a]
void Decode_1001aaaa(llvm::raw_ostream &OS, uint16_t Opcode);
// arm reg-to-reg move
void Decode_10011101(llvm::raw_ostream &OS, uint16_t Opcode);
// intel wireless reg-to-reg move
void Decode_10011111(llvm::raw_ostream &OS, uint16_t Opcode);
// pop r[4-(4+a)]
void Decode_10100aaa(llvm::raw_ostream &OS, uint16_t Opcode);
// pop r[4-(4+a)], r14
void Decode_10101aaa(llvm::raw_ostream &OS, uint16_t Opcode);
// finish
void Decode_10110000(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_10110001_00000000(llvm::raw_ostream &OS, uint16_t Opcode);
// pop r[0-3]
void Decode_10110001_0000aaaa(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_10110001_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// pop d[a-(a+b)]
void Decode_10110011_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_101101aa(llvm::raw_ostream &OS, uint16_t Opcode);
// pop d[8-(8+a)]
void Decode_10111aaa(llvm::raw_ostream &OS, uint16_t Opcode);
// pop wR[10-(10+a)]
void Decode_11000aaa(llvm::raw_ostream &OS, uint16_t Opcode);
// pop wR[a-(a+b)]
void Decode_11000110_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_11000111_00000000(llvm::raw_ostream &OS, uint16_t Opcode);
// pop wR[0-3]
void Decode_11000111_0000aaaa(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_11000111_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// pop d[(16+a)-(16+a+b)]
void Decode_11001000_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// pop d[a-(a+b)]
void Decode_11001001_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_11001aaa(llvm::raw_ostream &OS, uint16_t Opcode);
// pop d[8-(8+a)]
void Decode_11010aaa(llvm::raw_ostream &OS, uint16_t Opcode);
// spare
void Decode_11aaabbb(llvm::raw_ostream &OS, uint16_t Opcode);
// vsp = vsp + (value << 2) + 0x204
void Decode_10110010(llvm::raw_ostream &OS,
const uint8_t *Opcodes,
uint64_t Value,
unsigned Len);
void PrintRegMask(llvm::raw_ostream &OS,
const char *RegClass,
uint32_t Mask);
void PrintRegRange(llvm::raw_ostream &OS,
const char *RegClass,
uint32_t Begin,
uint32_t Range);
};
ARMUnwindOpcodesDisassembler::
ARMUnwindOpcodesDisassembler(ARM_ELFObjectFile &ObjFile_,
formatted_raw_ostream &OS_)
: ObjFile(ObjFile_), OS(OS_) {
}
section_iterator ARMUnwindOpcodesDisassembler::getSection(size_t i) {
error_code EC;
section_iterator SI = ObjFile.begin_sections();
section_iterator SE = ObjFile.end_sections();
while (SI != SE && i > 0) {
SI.increment(EC);
Ensure(EC);
--i;
}
return SI;
}
symbol_iterator ARMUnwindOpcodesDisassembler::
getSymbol(section_iterator Section, uint64_t Offset, SymbolRef::Type Ty) {
error_code EC;
for (symbol_iterator SYMI = ObjFile.begin_symbols(),
SYME = ObjFile.end_symbols(); SYMI != SYME; SYMI.increment(EC)) {
Ensure(EC);
section_iterator SYMISection(ObjFile.end_sections());
uint64_t SYMIOffset;
SymbolRef::Type SYMIType;
Ensure(SYMI->getSection(SYMISection));
Ensure(SYMI->getValue(SYMIOffset));
Ensure(SYMI->getType(SYMIType));
if (Section == SYMISection && Offset == SYMIOffset && Ty == SYMIType) {
return SYMI;
}
}
return ObjFile.end_symbols();
}
relocation_iterator ARMUnwindOpcodesDisassembler::
getRelocation(section_iterator Section, uint64_t Offset, uint64_t Type) {
error_code EC;
// Find the relocation section
section_iterator RelSec = ObjFile.begin_sections();
section_iterator SE = ObjFile.end_sections();
while (RelSec != SE) {
Ensure(EC);
if (RelSec->getRelocatedSection() == Section) {
break;
}
RelSec.increment(EC);
}
if (RelSec == SE) {
return Section->end_relocations();
}
// Look for the relocation at the offset with same type
for (relocation_iterator RI = RelSec->begin_relocations(),
RE = RelSec->end_relocations(); RI != RE; RI.increment(EC)) {
Ensure(EC);
uint64_t RIOffset, RIType;
Ensure(RI->getOffset(RIOffset));
Ensure(RI->getType(RIType));
if (Offset == RIOffset && Type == RIType) {
return RI;
}
}
return Section->end_relocations();
}
void ARMUnwindOpcodesDisassembler::Dump() {
DumpSections();
}
void ARMUnwindOpcodesDisassembler::DumpSections() {
error_code EC;
section_iterator SI = ObjFile.begin_sections();
section_iterator SE = ObjFile.end_sections();
if (SI != SE) {
DumpSection(SI);
SI.increment(EC);
Ensure(EC);
for (; SI != SE; SI.increment(EC)) {
Ensure(EC);
OS << "\n";
DumpSection(SI);
}
}
}
void ARMUnwindOpcodesDisassembler::DumpSection(section_iterator Section) {
// Dump section name
StringRef Name;
Ensure(Section->getName(Name));
OS << "- section: " << Name << "\n";
// Dump section flags and linked section
DataRefImpl DRI = Section->getRawDataRefImpl();
const ARM_ELF_Shdr *Shdr = reinterpret_cast<const ARM_ELF_Shdr *>(DRI.p);
uint32_t sh_flags = Shdr->sh_flags;
uint32_t sh_link = Shdr->sh_link;
OS << " flag: " << format("%08"PRIx32, sh_flags) << "\n";
OS << " link: ";
if (sh_link == 0) {
OS << " None";
} else {
section_iterator LinkSec(getSection(sh_link));
StringRef LinkSecName;
Ensure(LinkSec->getName(LinkSecName));
OS << " \"" << LinkSecName << "\"";
}
OS << "\n";
// Dump exception handling entries (if this is .ARM.exidx)
if (Shdr->sh_type == ELF::SHT_ARM_EXIDX) {
DumpExIdxEntries(Section);
}
}
void ARMUnwindOpcodesDisassembler::DumpExIdxEntries(section_iterator Section) {
StringRef Contents;
Ensure(Section->getContents(Contents));
if (Contents.size() % 8 != 0) {
errs() << "ERROR: Content size does not align to 8\n";
exit(EXIT_FAILURE);
}
OS << " entries:\n";
for (size_t i = 0; i < Contents.size(); i += 8) {
DumpExIdxEntry(Section, Contents, i);
}
}
void ARMUnwindOpcodesDisassembler::DumpExIdxEntry(section_iterator Section,
StringRef Contents,
uint64_t Offset) {
const uint32_t *Data =
reinterpret_cast<const uint32_t *>(Contents.data() + Offset);
relocation_iterator FuncReloc(
getRelocation(Section, Offset, ELF::R_ARM_PREL31));
if (FuncReloc == Section->end_relocations()) {
OS << " - function: <unknown>+0x" << format("%"PRIx32, Data[0]) << "\n";
} else {
// Get the referee symbol
symbol_iterator Sym = FuncReloc->getSymbol();
int64_t Addend = getELFRelocationAddend(FuncReloc);
Addend += static_cast<int32_t>(Data[0]);
// Get the symbol offset to the section containing the symbol
section_iterator SymSection(ObjFile.end_sections());
uint64_t SymOffset;
Ensure(Sym->getSection(SymSection));
Ensure(Sym->getValue(SymOffset));
// Backward search for the function symbol
symbol_iterator FuncSym(getSymbol(SymSection, SymOffset + Addend,
SymbolRef::ST_Function));
OS << " - function: ";
StringRef Name;
if (FuncSym != ObjFile.end_symbols()) {
Ensure(FuncSym->getName(Name));
OS << Name;
} else {
Ensure(Sym->getName(Name));
OS << Name;
if (Addend > 0) {
OS << "+0x" << format("%"PRIx32, static_cast<int32_t>(Addend));
} else if (Addend < 0) {
OS << "-0x" << format("%"PRIx32, static_cast<int32_t>(-Addend));
}
}
OS << "\n";
}
relocation_iterator DataReloc(
getRelocation(Section, Offset + 4, ELF::R_ARM_PREL31));
StringRef Personality;
std::vector<uint8_t> Opcodes;
if (DataReloc == Section->end_relocations()) {
if (Data[1] == 0x00000001u) {
OS << " cant_unwind: 1\n";
} else {
Personality = "__aeabi_unwind_cpp_pr0";
Opcodes.push_back((Data[1] >> 16) & 0xff);
Opcodes.push_back((Data[1] >> 8) & 0xff);
Opcodes.push_back((Data[1]) & 0xff);
OS << " personality: " << Personality << "\n";
OS << " unwind_opcodes: |\n";
DecodeOpcodes(Opcodes);
}
} else {
// Get the referee symbol
symbol_iterator Sym = DataReloc->getSymbol();
int64_t Addend = getELFRelocationAddend(DataReloc);
Addend += static_cast<int32_t>(Data[1]);
// Get the symbol offset to the section containing the symbol
section_iterator SymSection(ObjFile.end_sections());
uint64_t SymOffset;
Ensure(Sym->getSection(SymSection));
Ensure(Sym->getValue(SymOffset));
// Get the contents of the section
StringRef Contents;
Ensure(SymSection->getContents(Contents));
const uint32_t *Data =
reinterpret_cast<const uint32_t *>(Contents.data() + SymOffset + Addend);
size_t Size = 0;
unsigned MSB = (Data[0] >> 24) & 0xffu;
if (MSB == 0x80u) {
Personality = "__aeabi_unwind_cpp_pr0";
Opcodes.push_back((Data[0] >> 16) & 0xff);
Opcodes.push_back((Data[0] >> 8) & 0xff);
Opcodes.push_back((Data[0]) & 0xff);
} else if (MSB == 0x81u || MSB == 0x82u) {
Personality = (MSB == 0x81u) ? "__aeabi_unwind_cpp_pr1"
: "__aeabi_unwind_cpp_pr2";
Size = ((Data[0] >> 16) & 0xffu) + 1;
Opcodes.push_back((Data[0] >> 8) & 0xff);
Opcodes.push_back((Data[0]) & 0xff);
for (size_t i = 1; i < Size; ++i) {
Opcodes.push_back((Data[i] >> 24) & 0xff);
Opcodes.push_back((Data[i] >> 16) & 0xff);
Opcodes.push_back((Data[i] >> 8) & 0xff);
Opcodes.push_back((Data[i]) & 0xff);
}
} else {
Size = ((Data[1] >> 24) & 0xffu) + 2;
relocation_iterator PersonalityReloc(
getRelocation(SymSection, SymOffset + Addend, ELF::R_ARM_PREL31));
if (PersonalityReloc == SymSection->end_relocations()) {
Personality = "<< no relocation for personality >>";
} else {
symbol_iterator PersonalitySym = PersonalityReloc->getSymbol();
PersonalitySym->getName(Personality);
}
Opcodes.push_back((Data[1] >> 16) & 0xff);
Opcodes.push_back((Data[1] >> 8) & 0xff);
Opcodes.push_back((Data[1]) & 0xff);
for (size_t i = 2; i < Size; ++i) {
Opcodes.push_back((Data[i] >> 24) & 0xff);
Opcodes.push_back((Data[i] >> 16) & 0xff);
Opcodes.push_back((Data[i] >> 8) & 0xff);
Opcodes.push_back((Data[i]) & 0xff);
}
}
OS << " personality: " << Personality << "\n";
OS << " unwind_opcodes: |\n";
DecodeOpcodes(Opcodes);
}
}
void ARMUnwindOpcodesDisassembler::
DecodeOpcodes(const std::vector<uint8_t> &Opcodes) {
size_t i = 0;
std::vector<std::string> HexColumn;
std::vector<std::string> AsmColumn;
while (i < Opcodes.size()) {
HexColumn.push_back(std::string());
AsmColumn.push_back(std::string());
raw_string_ostream HexOS(HexColumn.back());
raw_string_ostream AsmOS(AsmColumn.back());
HexOS << format("%02x", static_cast<unsigned>(Opcodes[i]));
uint16_t Op = Opcodes[i++];
#define FETCH_NEXT_BYTE() \
do { \
if (i >= Opcodes.size()) { \
AsmOS << "Bad instruction sequence"; \
break; \
} \
HexOS << format(" %02x", static_cast<unsigned>(Opcodes[i])); \
Op = (Op << 8) | Opcodes[i++]; \
} while (0)
// NOTE: Check ARM EHABI page 41-42 for unwind opcode decoding table:
// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0038a/
// IHI0038A_ehabi.pdf
if ((Op & 0xc0u) == 0x00u) {
Decode_00aaaaaa(AsmOS, Op);
} else if ((Op & 0xc0u) == 0x40u) {
Decode_01aaaaaa(AsmOS, Op);
} else if (Op == 0x80u) {
FETCH_NEXT_BYTE();
if ((Op & 0xffu) == 0x00u) {
Decode_10000000_00000000(AsmOS, Op);
} else {
Decode_1000aaaa_bbbbbbbb(AsmOS, Op);
}
} else if ((Op & 0xf0u) == 0x80u) {
FETCH_NEXT_BYTE();
Decode_1000aaaa_bbbbbbbb(AsmOS, Op);
} else if ((Op & 0xf0u) == 0x90u) {
if (Op == 0x9du) {
Decode_10011101(AsmOS, Op);
} else if (Op == 0x9fu) {
Decode_10011111(AsmOS, Op);
} else {
Decode_1001aaaa(AsmOS, Op);
}
} else if ((Op & 0xf8u) == 0xa0u) {
Decode_10100aaa(AsmOS, Op);
} else if ((Op & 0xf8u) == 0xa8u) {
Decode_10101aaa(AsmOS, Op);
} else if (Op == 0xb0u) {
Decode_10110000(AsmOS, Op);
} else if (Op == 0xb1u) {
FETCH_NEXT_BYTE();
if ((Op & 0xffu) == 0x00u) {
Decode_10110001_00000000(AsmOS, Op);
} else if ((Op & 0xf0u) == 0x00u) {
Decode_10110001_0000aaaa(AsmOS, Op);
} else {
Decode_10110001_aaaabbbb(AsmOS, Op);
}
} else if (Op == 0xb2u) {
uint64_t Value = 0u;
unsigned Len = 0u;
if (!DecodeULEB128(Value, Len, Opcodes, i)) {
AsmOS << "Bad instruction sequence";
break;
}
for (size_t j = 0; j < Len; ++j) {
HexOS << format(" %02x", static_cast<unsigned>(Opcodes[i + j]));
}
Decode_10110010(AsmOS, &*Opcodes.begin() + i - 1, Value, Len);
i += Len;
} else if (Op == 0xb3u) {
FETCH_NEXT_BYTE();
Decode_10110011_aaaabbbb(AsmOS, Op);
} else if ((Op & 0xfcu) == 0xb4u) {
Decode_101101aa(AsmOS, Op);
} else if ((Op & 0xf8u) == 0xb8u) {
Decode_10111aaa(AsmOS, Op);
} else if (Op == 0xc6u) {
FETCH_NEXT_BYTE();
Decode_11000110_aaaabbbb(AsmOS, Op);
} else if (Op == 0xc7u) {
FETCH_NEXT_BYTE();
if ((Op & 0xffu) == 0x00u) {
Decode_11000111_00000000(AsmOS, Op);
} else if ((Op & 0xf0u) == 0x00u) {
Decode_11000111_0000aaaa(AsmOS, Op);
} else {
Decode_11000111_aaaabbbb(AsmOS, Op);
}
} else if ((Op & 0xf8u) == 0xc0u) {
Decode_11000aaa(AsmOS, Op);
} else if (Op == 0xc8u) {
FETCH_NEXT_BYTE();
Decode_11001000_aaaabbbb(AsmOS, Op);
} else if (Op == 0xc9u) {
FETCH_NEXT_BYTE();
Decode_11001001_aaaabbbb(AsmOS, Op);
} else if ((Op & 0xf8u) == 0xc8u) {
Decode_11001aaa(AsmOS, Op);
} else if ((Op & 0xf8u) == 0xd0u) {
Decode_11010aaa(AsmOS, Op);
} else if ((Op & 0xc0u) == 0xc0u) {
Decode_11aaabbb(AsmOS, Op);
} else {
assert(0 && "Unexpected cases");
}
#undef FETCH_NEXT_BYTE
}
size_t ColumnWidth = 0;
for (size_t i = 0; i < HexColumn.size(); ++i) {
ColumnWidth = std::max(ColumnWidth, HexColumn[i].size());
}
for (size_t i = 0; i < HexColumn.size(); ++i) {
OS.PadToColumn(6);
OS << HexColumn[i];
OS.PadToColumn(7 + ColumnWidth);
OS << "| ";
OS << AsmColumn[i];
OS << "\n";
}
}
void ARMUnwindOpcodesDisassembler::Decode_00aaaaaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
uint16_t Offset = ((Opcode & 0x3fu) << 2) + 4;
OS << "vsp = vsp + " << Offset;
}
void ARMUnwindOpcodesDisassembler::Decode_01aaaaaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
uint16_t Offset = ((Opcode & 0x3fu) << 2) + 4;
OS << "vsp = vsp - " << Offset;
}
void ARMUnwindOpcodesDisassembler::
Decode_10000000_00000000(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "refuse to unwind";
}
void ARMUnwindOpcodesDisassembler::
Decode_1000aaaa_bbbbbbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Mask = (Opcode & 0x0fffu) << 4;
PrintRegMask(OS, "r", Mask);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::Decode_1001aaaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
uint16_t Reg = Opcode & 0x0fu;
OS << "vsp = r" << Reg;
}
void ARMUnwindOpcodesDisassembler::Decode_10011101(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "reserved for ARM reg-to-reg move";
}
void ARMUnwindOpcodesDisassembler::Decode_10011111(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "reserved for Intel wireless reg-to-reg move";
}
void ARMUnwindOpcodesDisassembler::Decode_10100aaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "pop {";
uint16_t Range = Opcode & 0x07u;
PrintRegRange(OS, "r", 4, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::Decode_10101aaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "pop {";
uint16_t Range = Opcode & 0x07u;
PrintRegRange(OS, "r", 4, Range);
OS << ", r14}";
}
void ARMUnwindOpcodesDisassembler::Decode_10110000(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "finish";
}
void ARMUnwindOpcodesDisassembler::
Decode_10110001_00000000(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::
Decode_10110001_0000aaaa(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Mask = Opcode & 0x0fu;
PrintRegMask(OS, "r", Mask);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::
Decode_10110001_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::
Decode_10110011_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Begin = (Opcode & 0xf0u) >> 4;
uint16_t Range = (Opcode & 0x0fu);
PrintRegRange(OS, "d", Begin, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::Decode_101101aa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::Decode_10111aaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "pop {";
uint16_t Range = Opcode & 0x07u;
PrintRegRange(OS, "d", 8, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::Decode_11000aaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "pop {";
uint16_t Range = Opcode & 0x07u;
PrintRegRange(OS, "wR", 10, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::
Decode_11000110_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Begin = (Opcode & 0xf0u) >> 4;
uint16_t Range = (Opcode & 0x0fu);
PrintRegRange(OS, "wR", Begin, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::
Decode_11000111_00000000(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::
Decode_11000111_0000aaaa(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Mask = Opcode & 0x0fu;
PrintRegMask(OS, "wR", Mask);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::
Decode_11000111_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::
Decode_11001000_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Begin = (Opcode & 0xf0u) >> 4;
uint16_t Range = (Opcode & 0x0fu);
PrintRegRange(OS, "d", 16 + Begin, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::
Decode_11001001_aaaabbbb(llvm::raw_ostream &OS, uint16_t Opcode) {
OS << "pop {";
uint16_t Begin = (Opcode & 0xf0u) >> 4;
uint16_t Range = (Opcode & 0x0fu);
PrintRegRange(OS, "d", Begin, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::Decode_11001aaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::Decode_11010aaa(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "pop {";
uint16_t Range = Opcode & 0x07u;
PrintRegRange(OS, "d", 8, Range);
OS << "}";
}
void ARMUnwindOpcodesDisassembler::Decode_11aaabbb(llvm::raw_ostream &OS,
uint16_t Opcode) {
OS << "spare";
}
void ARMUnwindOpcodesDisassembler::Decode_10110010(llvm::raw_ostream &OS,
const uint8_t *Opcodes,
uint64_t Value,
unsigned Len) {
uint64_t Offset = (Value << 2) + 0x204u;
OS << "vsp = vsp + " << Offset;
}
void ARMUnwindOpcodesDisassembler::PrintRegMask(llvm::raw_ostream &OS,
const char *RegClass,
uint32_t Mask) {
bool PrintSep = false;
for (uint32_t R = 0, B = 1u; R < 32; ++R, B <<= 1) {
if (Mask & B) {
if (PrintSep) {
OS << ", ";
} else {
PrintSep = true;
}
OS << RegClass << R;
}
}
}
void ARMUnwindOpcodesDisassembler::PrintRegRange(llvm::raw_ostream &OS,
const char *RegClass,
uint32_t Begin,
uint32_t Range) {
bool PrintSep = false;
for (uint32_t R = Begin, End = Begin + Range + 1; R < End; ++R) {
if (PrintSep) {
OS << ", ";
} else {
PrintSep = true;
}
OS << RegClass << R;
}
}
int main(int argc, char **argv) {
// Read command line options
cl::ParseCommandLineOptions(argc, argv);
// Load the input file to memory buffer
OwningPtr<MemoryBuffer> MemBuf;
Ensure(MemoryBuffer::getFileOrSTDIN(InputFile, MemBuf));
// Open the object file
OwningPtr<ObjectFile> ObjFile(ObjectFile::createObjectFile(MemBuf.take()));
if (!ObjFile) {
errs() << "ERROR: Failed to load the input object file\n";
exit(EXIT_FAILURE);
}
ARM_ELFObjectFile *ARMObjFile = dyn_cast<ARM_ELFObjectFile>(ObjFile.get());
if (!ARMObjFile) {
errs() << "ERROR: The input object file is not an ARM ELF object file\n";
exit(EXIT_FAILURE);
}
// Create ARMUnwindOpcodesDisassembler
formatted_raw_ostream OS(outs(), false);
ARMUnwindOpcodesDisassembler DisAsm(*ARMObjFile, OS);
DisAsm.Dump();
return EXIT_SUCCESS;
}