Is it possible to add a RISC-V 5-stage processor config with hazard detection but no forwarding?

[tobias1610]

I am interested in using a 5-stage RISC-V processor with hazard detection but no forwarding unit in the simulator. Can you tell me, how difficult it is to add this to the simulator?

Thanks,
Tobi

[mortbopet]

I think that would be a great addition, and it shouldn't be too difficult to implement.
I haven't made a guide yet for how to add new processor models, so here's the rough idea:

1. duplicate the RV5S model to a separate folder, and rename the model (+ files) to RV5S_NO_FW
2. Add the new model to https://github.com/mortbopet/Ripes/blob/assembler/src/processorregistry.h
3. Remove the forwarding unit as well as the forwarding multipexers which it controls.
4. Replace the outputs of the (now removed) forwarding mulitplexers (reg1_fw_src->out) with the output from the IDEX register (idex_reg->r1_out)
5. Create a new, nice looking layout. This can be done by right-clicking outside of the processor and selecting "unlock". You can now move around components inside the datapath, drag wires around, remove intermediate wire points etc. There might be some bugs here - hopefully nothing that crashes. When the layout is finished, you can right-click inside the processor and select layout->save layout.

I just pushed some changes to master which fixes some bugs when adding new processor models, make sure you're on at least 20e6207.

[tobias1610]

OK thank you. I've now done all of this and created the new layouts. Now the only missing thing is the insertion of the stalls in case of RAW conflicts and load operation. Will all of this be done in the hazard unit?

[mortbopet]

Sounds good. At this point you'll probably want to route the register write idx + register write enable from the ex, mem and wb stages to the hazard unit, and then in the hazard unit elaborate the current code which controls the clear/enable signals.