This project involves implementing a digital clock using hardware description language, prototyped on an FPGA. This clock will be organized hierarchically through a set of circuits to be developed by the group. The following blocks are required for the circuit construction:
- Clock divider (for time counting from a 100MHz reference signal)
- Debounce circuit (for button reading)
- Various counters (for seconds, minutes, and hours)
- State machine for operation and time adjustment (ready, seconds, minutes, and hours)
- Driver for the displays
- Top-level for project simulation and synthesis
- Testbench for simulation
The digital clock will utilize 7-segment displays to show the hour (0 to 23), minutes (0 to 59), and seconds (0 to 59). Three buttons will be used for adjustment:
- a) Function selection (adjustment of hours, minutes, seconds, or ready);
- b) Decrease value;
- c) Increase value.
During time adjustment, the specific displays for the part being adjusted should blink (on for 500ms, off for 500ms). After adjustment (ready state), the hour should be displayed without blinking. All buttons must have a debounce circuit, and the clock should count time accurately.
To explore the circuit verification technique, two errors will be introduced into the project that will cause incorrect clock operation. The introduced errors were demonstrated and detected through in-circuit verification.